Encoding method and apparatus, decoding method and apparatus, and system

Abstract

The present application provides an encoding method and apparatus, a decoding method and apparatus, and a system. In the encoding method, by defining a strategy for code block encoding of a training frame, the training frame having undergone code block encoding comprises control code blocks, the control code blocks can be used to determine boundary code blocks between a code block set corresponding to subframes which are comprised in the training frame and have undergone code block encoding and adjacent code block sets, and the boundary code blocks correspond to the boundaries between the subframes and adjacent subframes in the training frame, so that during the decoding process, the boundaries of subframes in the obtained training sequence can be determined by means of the control code blocks.

Description

Coding method, decoding method, device and system

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on February 8, 2024, with application number 202410179140.3 and invention name “A Coding Method, Decoding Method, Device and System”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to an encoding method, a decoding method, a device and a system. Background Art

[0003] In order to meet the needs of industrial scenarios, it is necessary to introduce forward error correction (FEC) in the physical coding sublayer (PCS) of the equipment to ensure reliable transmission of signals between devices. However, when FEC is introduced in PCS, in order to meet the requirements of intrinsic safety, before implementing pulse amplitude modulation (PAM) symbol mapping, the training frame is subjected to code block encoding (hereinafter referred to as code block encoding) for controlling disparity (also called inconsistency). Currently, after the training frame is code block encoded, the boundary features of the subframes included in the training frame are hidden, and the boundaries of the subframes included in the training frame cannot be quickly identified based on the content after code block encoding. Summary of the Invention

[0004] Based on this, the present application provides an encoding method, a decoding method, an apparatus and a system, which can accurately identify the boundaries of subframes included in a training frame when performing code block encoding on the training frame.

[0005] In a first aspect, the present application provides a coding method that can be applied to a first physical layer (PHY). The method may include, for example, the first PHY obtaining a training frame including multiple subframes, performing code block coding on a first subframe of the multiple subframes to obtain a first code block set, the first code block set including a first control code block, and the first control code block being used to determine a boundary code block between the first code block set and an adjacent code block set. Thus, by defining a strategy for performing code block coding on the training frame, the content obtained after code block coding on the training frame includes a control code block. The control code block can be used to determine a boundary code block between a code block set corresponding to a subframe included in the training frame after code block coding and an adjacent code block set. The boundary code block corresponds to a boundary between the subframe and an adjacent subframe in the training frame. Consequently, during code block decoding of a training sequence including the training frame, the control code block can be used to quickly and accurately determine a subframe boundary in the obtained training sequence, paving the way for quickly and accurately implementing scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0006] As an example, the first control code block may also be referred to as a synchronization K code. For example, the first control code block may include, but is not limited to, any one of K28.1, K28.5, or K28.7 in the 8B / 10B special code groups. Since only K28.1, K28.5, or K28.7 includes a unique b'0011111' (comma+) or b'1100000' (comma-), any one of K28.1, K28.5, or K28.7 may be used as the first control code block and included in the first code block set. In this way, by searching for the comma in the first code block set, the first control code block in the first code block set can be quickly identified, thereby determining the boundary code block between the first code block set and the adjacent code block set based on the first control code block.

[0007] It should be noted that in this application, using 8B / 10B encoding as an example, Kx.y represents a 10-bit code group generated by following the encoding rules for the control variable with the pre-encoding value xy. Specifically, K represents the control code group encoding rule, and x and y represent the decimal values ​​of the EDCBA and HGF bits, respectively, in the 8-bit position HGFEDCBA before 8B / 10B encoding. For example, 28.1 indicates that the value corresponding to the 8-bit position HGFEDCBA before encoding is 00111100.

[0008] In one possible implementation, the multiple subframes of the training frame may further include a second subframe carrying an information field, where the information field includes configuration information for the link between the first PHY and the second PHY. The configuration information may, for example, include at least one of the following: operating rate, status information, or capability information. The status information may, for example, include the status of the physical medium attachment (PMA) layer or the PCS, where the PCS status may include whether the PCS scrambling code is synchronized. The capability information may, for example, include support for different standard rates such as 10M and 100M, and support for simplex, full-duplex, symmetric, and asymmetric modes. Furthermore, the information field may further include control parameters for the link between the first PHY and the second PHY. The control parameters may, for example, include timestamp, transmit power, equalizer coefficients, or signal quality evaluation indicators. The signal quality evaluation indicators may, for example, include, but are not limited to, signal-to-noise ratio (SNR), SNR margin, or bit error rate (BER).

[0009] In a possible implementation, the method may further include: the first PHY performs code block encoding on the second subframe to obtain a second code block set.

[0010] As an example, the second code block set may consist of multiple data code blocks, excluding control code blocks. For example, if the first code block set includes one first control code block and the rest are data code blocks, the number of data code blocks in the second code block set may be one more than the number of data code blocks in the first code block set, and the number of code blocks included in the second code block set may be the same as the number of code blocks included in each first code block set.

[0011] As another example, the second code block set may include a second control code block. For the first control code block and the second control code block, the value of the second control code block before encoding may be the same as the value of the first control code block before encoding, for example, the first control code block and the second control code block are both K28.1; the value of the second control code block before encoding may also be different from the value of the first control code block before encoding, for example, the first control code block is K28.1, and the second control code block may be K28.5 or K28.7; the number of second control code blocks may be the same as the number of first control code blocks, for example, each first code block set includes a first control code block, and the second code block set also includes a second control code block; the number of second control code blocks may be the same as the number of first control code blocks. The number of the first control code blocks may also be different from the number of the first control code blocks, for example, each first code block set includes one first control code block, and the second code block set includes two second control code blocks; the positions of the second control code blocks and the first control code blocks in the corresponding code block sets may be the same, for example, the first control code block is the starting code block of each first code block set, and the second control code block is the starting code block of the second code block set; the positions of the second control code blocks and the first control code blocks in the corresponding code block sets may also be different, for example, the first control code block is the starting code block of each first code block set, and the second control code block is the middle code block or the ending code block of the second code block set.

[0012] In a possible implementation, if the first control code block is a start code block or an end code block of the first code block set, then the first control code block is a boundary code block.

[0013] In another possible implementation, if the first control code block is a middle code block in the first code block set, the first PHY may determine a boundary code block based on the position of the first control code block in the first code block set. It will be appreciated that, given the first control code block in the first code block set and the offset (offset bits or number of offset code blocks) of the first control code block relative to the boundary code block in the first code block set, the first PHY may offset the first control code block in the first code block set by the offset relative to the boundary code block to determine the boundary code block.

[0014] In one possible implementation, some or all of the first code block sets may further include a third control code block. The third control code block is used to indicate the position of the first code block set in which it is located within multiple code block sets obtained by performing code block encoding on a training frame. Unlike the first control code block, the third control code block can be any control code block that does not include a comma, including but not limited to K23.7 or K27.7.

[0015] In one possible implementation, the method may further include: the first PHY sending multiple code block sets including the first code block set to the second PHY. As an example, the first PHY may first perform PAM mapping on the multiple code block sets (including the first code block set) obtained by code block encoding the training frame to obtain a symbol sequence; then, the first PHY sends the symbol sequence to the second PHY via a cable, thereby implementing signal transmission between the first PHY and the second PHY.

[0016] In one possible implementation, the first PHY performs code block encoding on a first subframe among multiple subframes to obtain a first code block set. For example, this may include: the first PHY encodes the first subframe in an 8B / 10B manner to obtain a first code block set. The 8B / 10B encoding method can be understood as encoding each 8 bits of data in the first subframe into a 10-bit code block. The encoding method used in the method provided in the embodiment of the present application is not limited to the 8B / 10B method, and can be any other possible method, for example, the 9B / 10B method.

[0017] In a possible implementation, the training frame mentioned in the present application may be a PMA training frame. In the PMA training frame, the information field is located at the 0th bit to the 95th bit of the last subframe of the PMA training frame.

[0018] In a second aspect, the present application also provides a decoding method, which is applied to a second PHY. The method may, for example, include: the second PHY obtains a training sequence including a first code block set, the first code block set including a first control code block; then, the second PHY can determine a first boundary code block between the first code block set and an adjacent code block set based on the first control code block; then, the second PHY determines a second boundary between a first subframe and an adjacent subframe based on the first boundary code block. In this way, by defining a code block decoding strategy corresponding to the encoding method provided in an embodiment of the present application, it is possible to quickly and accurately determine the boundary code block between the code block set and the adjacent code block set based on the control code block included in the code block set in the training sequence, and determine the boundary between the subframe and the adjacent subframe corresponding to the code block set after code block decoding based on the boundary code block. In this way, the boundary of the subframe in the obtained training sequence is quickly and accurately determined, making it possible to quickly and accurately implement scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0019] In one possible implementation, the method may further include: the second PHY determining a training frame from the acquired training sequence, where the training frame includes the first subframe. The training sequence may further include a second code block set, where the second code block set is obtained by performing code block encoding on the second subframe, and the second subframe includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

[0020] As an example, the second code block set may include a second control code block, and the method may further include: the second PHY determines a third boundary code block between the second code block set and the adjacent code block set based on the second control code block; and the second PHY determines a fourth boundary between the second subframe and the adjacent subframe based on the third boundary code block.

[0021] As another example, the second code block set may be composed of multiple data code blocks, and the method may also include: the second PHY determines the fourth boundary between the second subframe and the adjacent subframe based on the data code block in the second code block set corresponding to the occurrence position of the first control code block in the first code block set.

[0022] In a possible implementation, when the second PHY determines the fourth boundary, the second PHY determining the training frame may include: the second PHY decoding the training sequence to obtain a training bit stream; and the second PHY determining the training frame in the training bit stream according to the second boundary and the fourth boundary.

[0023] In another possible implementation, when any one or more first code block sets also include a third control code block, the third control code block is used to indicate a position of the first code block set including the third control code block in multiple code block sets, and the multiple code block sets are obtained by code block encoding for a training frame. Then, the second PHY determining the training frame may include: the second PHY decoding the training sequence to obtain a training bit stream; and the second PHY determining the boundary of the training frame in the training bit stream based on the third control code block and the second boundary, thereby determining the training frame from the training sequence.

[0024] In one possible implementation, the second PHY determines the second boundary between the first subframe and the adjacent subframe based on the first boundary code block, which may include: the second PHY generates indication information (indicating the position of the first boundary code block in the code block set) based on the first boundary code block and decodes the training sequence to obtain a training bit stream, where the training bit stream includes the first subframe; then, the second PHY determines the second boundary in the training bit stream according to the indication information.

[0025] In one possible implementation, the code block encoding of the second PHY may be implemented in 8B / 10B mode. The decoding mode used in the method provided in the embodiment of the present application is not limited to 8B / 10B mode, and may be any other possible mode, such as 9B / 10B mode.

[0026] In a possible implementation, the training frame mentioned in the present application may be a PMA training frame. In the PMA training frame, the information field is located at the 0th bit to the 95th bit of the last subframe of the PMA training frame.

[0027] In a third aspect, the present application further provides an encoding device, applied to a first PHY, which may include an acquisition unit and a first encoding unit. The acquisition unit is configured to acquire a training frame, the training frame including multiple subframes; the first encoding unit is configured to perform code block encoding on a first subframe among the multiple subframes in the training frame to obtain a first code block set, the first code block set including a first control code block, the first control code block being configured to determine a boundary code block between the first code block set and an adjacent code block set.

[0028] In a possible implementation, a second subframe among the multiple subframes includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

[0029] In a possible implementation, the apparatus may further include: a second encoding unit configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set includes a second control code block.

[0030] As an example, the value of the first control code block before encoding is the same as the value of the second control code block before encoding.

[0031] As another example, the value of the first control code block before encoding is different from the value of the second control code block before encoding.

[0032] As yet another example, the number of the first control code blocks is different from the number of the second control code blocks.

[0033] As another example, the position of the first control code block in the first code block set is different from the position of the second control code block in the second code block set.

[0034] In a possible implementation, the apparatus further includes a third encoding unit configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set consists of multiple data code blocks.

[0035] In a possible implementation, the first control code block is a start code block or an end code block of the first code block set, and the first control code block is a boundary code block.

[0036] In another possible implementation, the first control code block is an intermediate code block of the first code block set, and the boundary code block is determined based on the position of the first control code block in the first code block set.

[0037] In a possible implementation, the first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame.

[0038] In a possible implementation, the apparatus may further include: a sending unit configured to send the first code block set to the second PHY.

[0039] In a possible implementation, the first encoding unit is specifically configured to encode the first subframe in 8B / 10B mode to obtain a first code block set.

[0040] In a possible implementation, the training frame is a PMA training frame.

[0041] It should be noted that for the relevant description of the encoding device of the third aspect, please refer to the corresponding description of the first aspect.

[0042] In a fourth aspect, the present application further provides a decoding device, applied to a second PHY. The device may include: an acquisition unit, a first determination unit, and a second determination unit. The acquisition unit is configured to acquire a training sequence, the training sequence including a first code block set, the first code block set including a first control code block; the first determination unit is configured to determine a first boundary code block between the first code block set and an adjacent code block set based on the first control code block; and the second determination unit is configured to determine a second boundary between a first subframe and an adjacent subframe based on the first boundary code block.

[0043] In a possible implementation, the apparatus may further include: a third determining unit configured to determine a training frame, where the training frame includes the first subframe.

[0044] In a possible implementation, the training sequence further includes a second code block set, where the second code block set is obtained by performing code block encoding on the second subframe. The second subframe includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

[0045] As an example, the second code block set includes a second control code block, and the apparatus further includes: a fourth determining unit and a fifth determining unit. The fourth determining unit is configured to determine a third boundary code block between the second code block set and an adjacent code block set based on the second control code block; and the fifth determining unit is configured to determine a fourth boundary between the second subframe and an adjacent subframe based on the third boundary code block.

[0046] As another example, the second code block set includes multiple data code blocks, and the apparatus further includes a sixth determining unit configured to determine a fourth boundary between the second subframe and an adjacent subframe based on a data code block in the second code block set corresponding to a position where the first control code block in the first code block set appears.

[0047] In this implementation, the third determining unit is specifically configured to: decode the training sequence to obtain a training bit stream; and determine a training frame in the training bit stream according to the second boundary and the fourth boundary.

[0048] In another possible implementation, the first code block set also includes a third control code block, and the third control code block is used to indicate the position of the first code block set including the third control code block in multiple code block sets. The multiple code block sets are obtained by performing code block encoding on the training frame. The third determination unit is specifically used to: decode the training sequence to obtain a training bit stream; and determine the boundary of the training frame in the training bit stream based on the third control code block and the second boundary.

[0049] In one possible implementation, the second determination unit is specifically used to: decode the training sequence according to the first boundary code block to obtain a training bit stream, where the training bit stream includes a first subframe; and determine the second boundary in the training bit stream according to the indication information, where the indication information is used to indicate the position of the first boundary code block in the corresponding code block set.

[0050] In a possible implementation, decoding is performed in 8B / 10B mode.

[0051] It should be noted that for the relevant description of the decoding device of the fourth aspect, please refer to the corresponding description of the second aspect.

[0052] In a fifth aspect, the present application provides a communication device, which may include a first PHY and / or a second PHY;

[0053] A first PHY, configured to execute the method provided in the first aspect or any possible implementation manner of the first aspect;

[0054] The second PHY is configured to execute the method provided in the second aspect or any possible implementation manner of the second aspect.

[0055] In a sixth aspect, the present application provides a communication device, the communication device including a memory and a processor;

[0056] a memory for storing instructions;

[0057] A processor is used to execute the instructions in the memory and execute the method provided in the above-mentioned first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0058] In a seventh aspect, the present application provides a communication system, which may include a first communication device and a second communication device, the first communication device including a first PHY, and the second communication device including a second PHY;

[0059] A first PHY, configured to execute the method provided in the first aspect or any possible implementation manner of the first aspect;

[0060] The second PHY is configured to execute the method provided in the second aspect or any possible implementation manner of the second aspect.

[0061] In an eighth aspect, the present application also provides a storage medium comprising instructions, which, when executed on a processor, cause the processor to execute the method provided in the first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0062] In the ninth aspect, the present application also provides a program product, which includes a program. When the program runs on a processor, it executes the method provided in the above-mentioned first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect.

[0063] In the tenth aspect, the present application also provides a PHY chip, comprising a processor and an interface circuit; the interface circuit is used to receive instructions and transmit them to the processor; the processor is used to execute the method provided in the above-mentioned first aspect, any possible implementation of the first aspect, the second aspect, or any possible implementation of the second aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] FIG1 is a schematic diagram of a possible format of a training frame in an embodiment of the present application;

[0065] FIG2 is a schematic diagram of performing code block encoding on the training frame shown in FIG1 in an embodiment of the present application;

[0066] FIG3 a is a schematic diagram of a scenario in which switches 1 and 2 are interconnected via cables, to which an embodiment of the present application is applicable;

[0067] FIG3 b is a schematic diagram of a scenario in which a switch 1 and a terminal device 2 are interconnected via cables, to which an embodiment of the present application is applicable;

[0068] FIG3 c is a schematic diagram of a scenario in which switches 3 and 4 are interconnected via cables, to which an embodiment of the present application is applicable;

[0069] FIG3 d is a schematic diagram of a scenario in which a switch 3 and a terminal device 4 are interconnected via cables, to which an embodiment of the present application is applicable;

[0070] FIG4 is a schematic diagram of a flow chart of an encoding method 100 in an embodiment of the present application;

[0071] FIG5 is a schematic diagram of a plurality of code block sets after code block encoding of a training frame according to an embodiment of the present application;

[0072] FIG6 is another schematic diagram of a plurality of code block sets after code block encoding of a training frame in an embodiment of the present application;

[0073] FIG7 is another schematic diagram of a plurality of code block sets after code block encoding of a training frame in an embodiment of the present application;

[0074] FIG8 is another schematic diagram of a plurality of code block sets after code block encoding of a training frame according to an embodiment of the present application;

[0075] FIG9 is another schematic diagram of a plurality of code block sets after code block encoding of a training frame in an embodiment of the present application;

[0076] FIG10 is a schematic flow chart of a decoding method 200 according to an embodiment of the present application;

[0077] FIG11 is a schematic diagram of a possible decoding process in an embodiment of the present application;

[0078] FIG12a is a schematic diagram of another possible decoding process in an embodiment of the present application;

[0079] FIG12b is a schematic diagram of another possible decoding process in an embodiment of the present application;

[0080] FIG13 is a schematic structural diagram of a communication device 1300 according to an embodiment of the present application;

[0081] FIG14 is a schematic structural diagram of a communication device 1400 according to an embodiment of the present application;

[0082] FIG15 is a schematic structural diagram of a communication device 1500 according to an embodiment of the present application;

[0083] FIG16 is a schematic structural diagram of a communication system 1600 in an embodiment of the present application. DETAILED DESCRIPTION

[0084] In data communication scenarios, as the data rate continues to increase, interference from electrical fast transients (EFT) and ringing signals will affect communication between devices. Therefore, FEC needs to be introduced on the devices to ensure the reliability of communication between devices. For example, FEC can be introduced in the PCS of the device. In addition, in order to meet the requirements of intrinsic safety, it is also necessary to use code block coding that controls disparity before PAM implements symbol mapping. However, code block coding causes the boundary features between the subframes included in the training frame to be hidden, so that the boundaries between the subframes included in the training frame cannot be quickly and accurately identified from the content after code block coding. However, quickly and accurately identifying the boundaries between the subframes included in the training frame is very important for scrambling code synchronization, training frame delimitation, and FEC delimitation. Among them, intrinsic safety is a protection technology that enables equipment to operate safely in explosive gas environments and abnormal operating conditions. The design method is to prevent the equipment from releasing energy sufficient to ignite flammable materials. It can also be understood that intrinsic safety is to achieve the purpose of explosion protection through safety barrier limit energy, or that the sparks generated by the energy passing through are not sufficient to cause an explosion, which is considered to meet the requirements of intrinsic safety.

[0085] Among them, the training frame refers to the training data constructed by the PHY of the device in the training mode, which is not used to transmit business data. In the embodiment of the present application, the signal frame to be code block encoded in the training mode is called a training frame. Relative to the training mode, the PHY can also include a data mode. In the data mode, business data can be transmitted between the PHYs of the devices. These business data can be transmitted between the PHYs of the devices through data frames (also called business frames). The training frame usually includes an information field, which may include: configuration information of the link between the PHYs of the two communicating devices. The configuration information may include, for example, at least one of the following information: working rate, status information or capability information. Among them, the status information may include, for example, the status of the PMA layer or the status of the PCS. The status of the PCS may include, for example, whether the PCS scrambling code is synchronized; the capability information may include, for example: support for different standard rates such as 10M, 100M, and support for different working modes such as simplex, full-duplex, symmetric and asymmetric. In addition, the information domain may also include control parameters of the link between the PHYs of the two communicating devices. The control parameters may include, for example, timestamp, transmit power, equalizer coefficient or signal quality evaluation index, wherein the signal quality evaluation index may include, for example, but not limited to: SNR, SNR margin or BER.

[0086] For example, FIG1 shows a schematic diagram of a possible format of a training frame. The training frame can be obtained by processing the pseudo-random binary sequence (PRBS) generated by the PCS scrambler according to certain rules. The training frame shown in FIG1 can include L bits, and the generation process of the training frame can include: S11, the L-bit PRBS generated by the PCS scrambler is divided into several N-bit subframes, and the length of each subframe in the obtained subframe 1, subframe 2, ... is N bits; S12, except for the last subframe, the first bit of the other subframes is XORed with 1, which is equivalent to inverting the first bit of the other subframes except the last subframe; S13, the first 96 bits of the last subframe are scrambled with the information field (also called Infofield information). The relationship between the training frame and the PRBS in this process can be seen in the following formula (1). Wherein, L and N are both integers greater than 1, and L is an integer multiple of N. It should be noted that the execution order of S12 and S13 does not need to be limited.

[0087] For the training frame shown in Figure 1, for the PHY of the receiving device, under ideal conditions (i.e., not considering the impact of the link bit error rate), if it is determined that at least [(L / N)-1] bits out of [(L / N)] bits obtained after descrambling are all 1, then descrambling code synchronization and subframe delimitation are considered to have been achieved. Next, by identifying the first three bytes (i.e., 24 bits) of each descrambled subframe, it is determined whether the content of the first three bytes of the subframe is consistent with the Start Frame Delimiter (SFD) information in the information field. If they are consistent, the subframe is determined to be the last subframe of the training frame, thereby locating the training frame boundary and achieving training frame boundary alignment.

[0088] Figure 2 shows a schematic diagram of conventional block encoding of the training frame shown in Figure 1. Block encoding is performed on the training frame before PAM symbol mapping to meet intrinsic safety requirements in industrial scenarios. However, as shown in Figure 2, the block-encoded content fails to reflect the boundary characteristics of each subframe within the training frame. This makes it impossible to quickly determine the boundaries of each subframe within the training frame based on the block-encoded content. Consequently, scrambling code synchronization, training frame delimitation, and FEC delimitation cannot be achieved quickly and accurately.

[0089] It's understandable that when devices communicate with each other, they typically complete training in training mode before entering data mode to carry real service data. The training mode facilitates this by ensuring accurate identification of FEC codeword boundaries during data mode. For example, the length of the training frame is an integer multiple of the FEC codeword. Therefore, by determining the boundaries of the training frame during training mode, the FEC codeword can be accurately identified after entering data mode. For example, in a 1000BASE-T1 scenario, the data mode uses RS (450, 406, 22, 9), resulting in an FEC codeword length of 450 × 9 = 4050 bits. However, considering that the data mode uses 3B2T 3-Level Pulse Amplitude Modulation (PAM3), which converts 3 bits into 2 symbols, while the training mode uses 2-Level Pulse Amplitude Modulation (PAM2), which converts 2 bits into 2 symbols, a training frame length of 4050 / 3 × 2 = 2700 bits is used due to the difference in coding efficiency between the two. For example, in training mode, the information field in the training frame is extracted. Based on the relevant information in the information field, the PHYs of the two communicating devices can be quickly and stably switched to data mode. In other words, the rapid and accurate identification of subframe boundaries in the signal frame is the basis for scrambling code synchronization and FEC boundary identification, and is therefore a necessary condition for ensuring a smooth transition from training mode to data mode. Therefore, the training mode is a critical step for single-pair full-duplex PHY. The ability to quickly and accurately identify subframe boundaries in the training frame in training mode is the basis for the rapid and accurate implementation of subsequent operations such as scrambling code synchronization, training frame delimitation, and FEC delimitation.

[0090] Based on this, an embodiment of the present application provides an encoding method and a decoding method. By defining a strategy for code block encoding of a training frame, the content obtained after the code block encoding of the training frame includes a control code block. The control code block can be used to determine the boundary code block between the code block set corresponding to the subframe included in the training frame after code block encoding and the adjacent code block set. The boundary code block corresponds to the boundary between the subframe and the adjacent subframe in the training frame. Therefore, during the decoding process, the boundary of the subframe in the obtained training sequence can be determined by the control code block.

[0091] In one possible implementation, an embodiment of the present application provides an encoding method, which may include, for example, the following: a first PHY obtains a training frame including multiple subframes, and performs code block encoding on a first subframe of the multiple subframes to obtain a first code block set, wherein the first code block set includes a first control code block, and the first control code block is used to determine a boundary code block between the first code block set and an adjacent code block set. Thus, through the strategy for performing code block encoding on the training frame defined in the embodiment of the present application, the code block set obtained after code block encoding of the subframes in the training frame includes a control code block, and the control code block is used to determine a boundary code block between the code block set and an adjacent code block set. Thus, during code block decoding of a training sequence including the training frame, the boundary of the subframe in the obtained training sequence can be quickly and accurately determined using the control code block, paving the way for quickly and accurately implementing scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0092] In another possible implementation, an embodiment of the present application further provides a decoding method, which may include, for example: a second PHY obtains a training sequence, the training sequence including a first code block set, the first code block set including a first control code block; then, the second PHY determines a first boundary code block between the first code block set and an adjacent code block set based on the first control code block; then, the second PHY determines a second boundary between a first subframe and an adjacent subframe based on the first boundary code block. In this way, by defining a code block decoding strategy corresponding to the encoding method provided in an embodiment of the present application, during code block decoding of the obtained training sequence, the boundary code block between the code block set and the adjacent code block set can be quickly and accurately determined based on the control code block included in the code block set in the training sequence, and the boundary between the subframe corresponding to the code block set after code block decoding and the adjacent subframe can be determined based on the boundary code block. In this way, the boundary of the subframe in the obtained training sequence is quickly and accurately determined, making it possible to quickly and accurately implement scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0093] In an embodiment of the present application, the device where the PHY is located (also referred to as a communication device) can be a network device or a terminal device, wherein the network device can be, for example, a switch, a router, or a firewall, and the terminal device can be, for example, a user host or a vehicle-side host or other end-side device.

[0094] In the embodiment of the present application, the first PHY and the second PHY may belong to the same device, which has the encoding function and decoding function provided by the embodiment of the present application, and can implement the following method 100 for the training frame to be encoded by the code block, and implement the following method 200 for the training sequence to be decoded by the code block. Alternatively, from the perspective of interaction, the first PHY and the second PHY can be considered to belong to two devices respectively, and the two devices can be two interconnected network devices, or one interconnected network device and one terminal device. Figures 3a to 3d show schematic diagrams of four possible applicable scenarios of the embodiment of the present application.

[0095] Figure 3a shows a schematic diagram of a scenario where switch 1 and switch 2 are interconnected via a cable. The internal structures of switches 1 and 2 are similar, so switch 1 will be used as an example to explain the internal structure of the switches. Switch 1 may include a switch chip and a physical physical layer (PHY) 1. PHY 1 illustrates the functional modules involved in training mode and data mode, respectively, when switch 1 acts as a transmitter and receiver. In training mode, PHY 1, acting as a transmitter, may include at least modules implementing PCS scrambling, code block encoding, and PAM2 mapping. In data mode, service data sent by the switch chip undergoes processing that may include at least PCS code block encoding, FEC encoding, PCS scrambling, and PAM5 mapping. Regardless of whether the mode is data or training, the symbol sequence after symbol mapping undergoes mode selection and PMA before being connected to switch 2 via a twisted pair. As a receiver, PHY 1 may include at least the following functional modules in training mode: implementing PAM2 demapping, code block decoding, and PCS scrambling corresponding functions. In data mode, service data undergoes at least the following processing: PAM5 demapping, PCS scrambling, FEC decoding, and PCS code block decoding before arriving at the switching chip. Regardless of data mode or training mode, the received symbol sequence undergoes symbol demapping after PMA and mode selection.

[0096] Figure 3b shows a schematic diagram of a scenario in which switch 1 and terminal device 2 are interconnected via a cable. Terminal device 2 may include a microcontroller unit (MCU) and PHY 2. The internal structure of PHY 2 is similar to that of PHY 1 in switch 1. For details, see the above introduction to PHY 1 in switch 1 in Figure 3a.

[0097] It should be noted that Figures 3a and 3b use PAM5 mapping and PAM5 demapping as examples. In actual scenarios, the PAM order used for symbol mapping and demapping can be flexibly set according to requirements. When the PAM order is not an integer power of 2, for example, a PAM order of 5 or 3, the PHY needs to use a PCS scrambler for PCS scrambling in both training mode and data mode.

[0098] Figure 3c shows a schematic diagram of a scenario where switches 3 and 4 are interconnected via a cable. The internal structures of switches 3 and 4 are similar, so the internal structure of switch 3 will be described using switch 3 as an example. Switch 3 may include a switching chip and a physical physical layer (PHY) 3. PHY 3 illustrates the functional modules involved in training mode and data mode, respectively, when switch 3 functions as a transmitter and receiver. In training mode, PHY 3, acting as a transmitter, may include at least modules implementing PCS scrambling, code block encoding, and PAM2 mapping. In data mode, service data sent by the switching chip undergoes processing that may include at least PCS code block encoding, FEC encoding, PCS scrambling, code block encoding, and PAM4 mapping. Regardless of whether the mode is data or training, the symbol sequence after symbol mapping undergoes mode selection and PMA before entering switch 4 via the duplexer cable. As the receiver, PHY 3 can at least include the following functional modules in training mode: PAM2 demapping, code block decoding, and PCS scrambling. In data mode, the service data undergoes at least PAM4 demapping, code block decoding, PCS scrambling, FEC decoding, and PCS code block decoding before reaching the switching chip. Regardless of data mode or training mode, the received symbol sequence undergoes symbol demapping after PMA and mode selection. Compared with Figure 3a, the differences are: (1) PHY 3 adds code block encoding and code block decoding functional modules in data mode, (2) symbol processing uses PAM4 mapping and PAM4 demapping, and (3) the data mode and training mode use the same PCS scrambler for scrambling.

[0099] Figure 3d shows a schematic diagram of a scenario in which the switch 3 and the terminal device 4 are interconnected via a cable. The terminal device 4 may include an MCU and a PHY 4. The internal structure of the PHY 4 is similar to that of the PHY 3 in the switch 3. For details, see the above introduction to the PHY 3 in the switch 3 in Figure 3c.

[0100] It should be noted that Figures 3a and 3b use PAM5 mapping and PAM5 demapping as examples, and Figures 3c and 3d use PAM4 mapping and PAM4 demapping as examples. In actual scenarios, the PAM order used for symbol mapping and symbol demapping can be flexibly set according to requirements. When the PAM order is not an integer power of 2, for example, a PAM order of 5, the PHY needs to use a PCS scrambler for PCS scrambling in both training mode and data mode. When the PAM order is an integer power of 2, for example, a PAM order of 4, the PHY can use a single PCS scrambler for PCS scrambling in both training mode and data mode.

[0101] It should be noted that, in training mode, PHY 1 (or PHY 3) acts as a transmitter, and a training frame refers to content obtained by processing the PRBS generated by the PCS scrambling code and the training information, wherein the training information may include the rules used by the PRBS to generate the training frame, for example, see formula (1) or the above S11 to S13; in training mode, PHY 1 (or PHY 3) acts as a receiver, and the content after code block decoding and the PRBS generated by the PCS scrambling code are processed to obtain training information, which may be the same as or different from the training information when PHY 1 (or PHY 3) acts as a transmitter.

[0102] In order to introduce the embodiments of the present application more clearly, the method provided in the embodiments of the present application is described below with reference to the accompanying drawings.

[0103] FIG4 is a flow chart illustrating an encoding method 100 provided in an embodiment of the present application. In this method 100, the present application embodiment is described using a first PHY as the execution entity. The first PHY can be, for example, any of the PHYs in the scenarios shown in FIG3a through FIG3d. For example, if the first PHY corresponds to PHY 1 in FIG3a or FIG3b, then the method 100 can be understood as being implemented by PHY 1 or by switch 1 including PHY 1. For another example, if the first PHY corresponds to PHY 2 in FIG3b, then the method 100 can be understood as being implemented by PHY 2 or by terminal device 2 including PHY 2.

[0104] As shown in FIG4 , the method 100 may include, for example, the following S101 to S102:

[0105] S101: Acquire a training frame, where the training frame includes multiple subframes.

[0106] If the first PHY is a transmitter in training mode, the first PHY may implement method 100. As an example, the first PHY may include a functional module for implementing code block encoding, and the functional module may implement method 100. For example, in S101, the functional module for implementing code block encoding may obtain a training frame after processing the PRBS generated by the PCS scrambler.

[0107] A training frame can be understood as training data constructed by the first PHY in training mode and is not used to transmit service data. In the embodiment of the present application, the signal frame to be code block encoded in training mode is referred to as a training frame. A training frame includes multiple subframes, and each subframe is generally the same length. A training frame may include an information field, which may be located in any one or more subframes of the training frame. The following description takes the last subframe in the training frame as an example.

[0108] The information field may include configuration information for the link between the PHYs of two communicating devices. In embodiments of the present application, the information field may include configuration information for the link between the first PHY and the second PHY. This configuration information may include, for example, at least one of the following: operating rate, status information, or capability information. Furthermore, the information field may also include control parameters, such as timestamps, transmit power, equalizer coefficients, or signal quality evaluation indicators.

[0109] As an example, the training frame may be a PMA training frame, and the structure of the PMA training frame may be shown in Figure 1. In the PMA training frame, the information field is located at bits 0 to 95 of the last subframe of the PMA training frame.

[0110] Alternatively, the training frame may be other types of training frames. For example, the information field may be in the middle or end of the last subframe of the training frame. For another example, the subframe where the information field is located may be a middle subframe of the training frame. For another example, the subframe where the information field is located may be the first subframe of the training frame.

[0111] The following description is made by taking the subframe where the information field is located as the last subframe of the training frame as an example.

[0112] S102 , performing code block encoding on a first subframe among multiple subframes to obtain a first code block set, where the first code block set includes a first control code block, and the first control code block is used to determine a boundary code block between the first code block set and an adjacent code block set.

[0113] It should be noted that code block encoding of a training frame can be considered as code block encoding of each of the multiple subframes included in the training frame. The first subframe can be any subframe in the training frame. For example, the first subframe can be a subframe in the training frame that includes an information field. For another example, the first subframe can be any subframe in the training frame that does not include an information field. Therefore, when code block encoding is performed on each subframe in the training frame, the subframe can be considered as the first subframe, and S102 is executed.

[0114] Block coding can be understood as the process of encoding the data in each subframe into a corresponding code block set. The subframe before block coding corresponds to the code block set after block coding. During block coding, encoding each subframe can be understood as encoding each piece of data of a first length in the subframe into a code block of a second length. The number of data of the first length included in each subframe is the same as the number of code blocks included in the code block set corresponding to the subframe.

[0115] For example, in S102, the first subframe may be code block encoded in 8B / 10B format to obtain a first code block set. The first length corresponds to 8 bits, and the second length corresponds to 10 bits. Thus, during the code block encoding of the first subframe, every 8 bits of data in the first subframe are encoded into a 10-bit code block, resulting in multiple 10-bit code blocks. These multiple 10-bit code blocks all belong to the first code block set.

[0116] In order to achieve the purpose of the embodiment of the present application, in the coding strategy designed in the embodiment of the present application, the generated first code block set includes a first control code block for determining the boundary code block between the first code block set and the adjacent code block set.

[0117] The first control code block may also be referred to as a synchronization K code. For example, the first control code block may include, but is not limited to, any one of K28.1, K28.5, or K28.7 in the 8B / 10B special code groups. Since only the K28.1, K28.5, or K28.7 code groups include the unique b'0011111' (comma+) or b'1100000' (comma-), any one of the K28.1, K28.5, or K28.7 code groups may be used as the first control code block and included in the first code block set. In this way, by searching for the comma in the first code block set, the first control code block in the first code block set can be quickly identified, thereby determining the boundary code block between the first code block set and the adjacent code block set based on the first control code block.

[0118] In the following, in order to distinguish the subframe including the information field from other subframes in the multiple subframes included in the training frame, the above-mentioned first subframe can be considered as other subframes that do not include the information field. Then, the subframe including the information field in the training frame can be recorded as the second subframe.

[0119] In this way, code block encoding of the training frame obtained in S101 includes: S21, code block encoding each first subframe in multiple first subframes to obtain multiple first code block sets, each first code block set in the multiple first code block sets includes a first control code block; S22, code block encoding the second subframe to obtain a second code block set.

[0120] In a possible implementation, for the first code block set obtained in S21, the first control code block may be a start code block, an end code block, or an intermediate code block of the first code block set.

[0121] As an example, if the first control code block is the starting code block or the ending code block of the first code block set, then the first control code block itself can serve as the boundary code block between the first code block set and the adjacent code block set. Let the first control code block be denoted as K and the data code block as D. Then, if the first control code block is the starting code block of the first code block set, the first code block set can be represented as: KDD...D; if the first control code block is the ending code block of the first code block set, the first code block set can be represented as: DD...DK.

[0122] As another example, if the first control code block is an intermediate code block in the first code block set, the first PHY can determine the boundary code block between the first code block set and the adjacent code block set based on the position of the first control code block in the first code block set. It can be understood that if the first control code block in the first code block set is known, and the offset (offset bits or number of offset code blocks) of the first control code block relative to the boundary code block in the first code block set is known, the boundary code block can be determined by offsetting the first control code block in the first code block set by the code block at the offset relative to the boundary code block. Still denoting the first control code block as K and the data code block as D, then, if the first control code block is an intermediate code block in the first code block set, the first code block set can be represented as: DD…DKD…D.

[0123] It should be noted that the number of data code blocks (i.e., D in this example) in the first code block set is determined based on the length of the first subframe. For example, assuming the length of the first subframe is 128 bits and the code block encoding is implemented using 8B / 10B, since 128 bits consists of 16 8-bit blocks, the first code block set can include 16 10-bit code blocks. If the first code block set includes a first control code block, then the first code block set can also include 15 data code blocks.

[0124] In one possible implementation, the second code block set obtained in S22 may be composed of multiple data code blocks, excluding the control code block; it may also include a second control code block, the value of the second control code block before encoding may be the same as or different from the value of the first control code block before encoding, the number of second control code blocks may be the same as or different from the number of first control code blocks, and the positions of the second control code block and the first control code block in the corresponding code block set may be the same as or different.

[0125] As an example, the second code block set is composed of multiple data code blocks. This example can be combined with any of the cases where the first control code block is the starting code block, ending code block, or intermediate code block of the first code block set. Still taking the first control code block as K, the data code block as D, and the first control code block as the starting code block of the first code block set as an example, after the training frame is encoded with the code block provided in the embodiment of the present application, the multiple code block sets obtained can be as shown in Figure 5, and the multiple code block sets include multiple first code block sets and a second code block set in sequence, wherein each first code block set in the multiple first code block sets can be expressed as: KDD...D, and the second code block set can be expressed as: DD...D. Among them, the number of data code blocks in the second code block set can be one more than the number of data code blocks in the first code block set, and the number of code blocks included in the second code block set can be the same as the number of code blocks included in each first code block set.

[0126] As another example, the second code block set includes a second control code block, and the value of the second control code block before encoding can be the same as the value of the first control code block before encoding, or it can be combined with the case where the first control code block is any of the starting code block, ending code block, or middle code block of the first code block set. If the first control code block is K28.1, then the second control code block can also be K28.1; if the first control code block is K28.5, then the second control code block can also be K28.5; if the first control code block is K28.7, then the second control code block can also be K28.7. It should be noted that the same value before encoding of the control code block can be understood as the same control variable name corresponding to the control code block, or the same hexadecimal or binary input value corresponding to the control code block. In this case, the number of second control code blocks included in the second code block set can be the same as or different from the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set can be the same as or different from the position of the second control code block in the second code block set. The number of second control code blocks included in the second code block set is at least 1, and the number of first control code blocks included in the first code block set is at least 1.

[0127] For the case where the second code block set includes a second control code block, the value of the second control code block before encoding is the same as the value of the first code block before encoding, the number of second control code blocks included in the second code block set is the same as the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set is the same as the position of the second control code block in the second code block set, taking the case where the first code block set includes one first control code block and the second code block set includes one second control code block as an example, in one case, for the case where the first control code block and the second control code block are both the starting code blocks of the corresponding code block set, the first code block set and the second code block set can both be expressed as: KDD...D; in another case, for the case where the first control code block and the second control code block are both the ending code blocks of the corresponding code block set, the first code block set and the second code block set can both be expressed as: DD...DK; in yet another case, for the case where the first control code block and the second control code block are both intermediate code blocks of the corresponding code block set, the first code block set and the second code block set can both be expressed as: DD...DKD...D. Taking the example where the first control code block is the end code block of the first code block set and the second control code block is the end code block of the second code block set, after the training frame is encoded with the code blocks provided in the embodiment of the present application, the multiple code block sets obtained can be shown in Figure 6. The multiple code block sets include multiple first code block sets and one second code block set in sequence. Both the first code block set and the second code block set can be expressed as: DD...DK.

[0128] For the case where the second code block set includes a second control code block, the value of the second control code block before encoding is the same as the value of the first code block before encoding, the number of second control code blocks included in the second code block set is different from the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set is the same as the position of the second control code block in the second code block set, taking the first code block set including one first control code block and the second code block set including two second control code blocks as an example, in one case, for the case where both the first control code block and the second control code block are the starting code blocks of the corresponding code block sets In another case, when the first control code block and the second control code block are both the ending code blocks of the corresponding code block set, the first code block set can be expressed as: DD...DK, and the second code block set can be expressed as: DD...DKK; in another case, when the first control code block and the second control code block are both the middle code blocks of the corresponding code block set, the first code block set can be expressed as: DD...DKD...D, and the second code block set can be expressed as: DD...DKKD...D. Taking the example that the first control code block is the starting code block of the first code block set and the second control code block is the starting code block of the second code block set, after the code block encoding provided by the embodiment of the present application is performed on the training frame, the multiple code block sets obtained can be shown in Figure 7. The multiple code block sets sequentially include multiple first code block sets and one second code block set. Each first code block set in the multiple first code block sets can be expressed as: KDD...D, and the second code block set can be expressed as: KKDD...D.

[0129] It should be noted that, for the second code block set including the second control code block, on the premise that the value of the second control code block before encoding is the same as the value of the first code block before encoding, the number of second control code blocks included in the second code block set is different from the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set is different from the position of the second control code block in the second code block set; or, the number of second control code blocks included in the second code block set is the same as the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set is different from the position of the second control code block in the second code block set. Different code block encoding results can be flexibly combined, which will not be introduced in detail in the embodiments of the present application.

[0130] As another case, the case where the second code block set includes a second control code block, and the value of the second control code block before encoding is different from the value of the first code block before encoding, can also be combined with the case where the first control code block is any of the starting code block, ending code block, or middle code block of the first code block set. If the first control code block is K28.1, then the second control code block can be K28.5 or K28.7; if the first control code block is K28.5, then the second control code block can be K28.1 or K28.7; if the first control code block is K28.7, then the second control code block can be K28.1 or K28.5. In this case, the number of second control code blocks included in the second code block set can be the same as or different from the number of first control code blocks included in the first code block set, and the position of the first control code block in the first code block set can be the same as or different from the position of the second control code block in the second code block set. The number of second control code blocks included in the second code block set is at least 1, and the number of first control code blocks included in the first code block set is at least 1. Let K1 represent the first control code block and K2 represent the second control code block. Then, in one case, for the case where the first control code block and the second control code block are both the starting code blocks of the corresponding code block set, the first code block set can be expressed as: K1DD...D, and the second code block set can be expressed as: K2DD...D; in another case, for the case where the first control code block and the second control code block are both the ending code blocks of the corresponding code block set, the first code block set can be expressed as: DD...DK1, and the second code block set can be expressed as: DD...DK2; in yet another case, for the case where the first control code block and the second control code block are both the middle code blocks of the corresponding code block set, the first code block set can be expressed as: DD...DK1D...D, and the second code block set can be expressed as: DD...DK2D...D. Taking the example that the first control code block is the starting code block of the first code block set and the second control code block is the starting code block of the second code block set, after the training frame is encoded with the code block provided in the embodiment of the present application, the multiple code block sets obtained can be shown in Figure 8. The multiple code block sets include multiple first code block sets and one second code block set in sequence. Each first code block set in the multiple first code block sets can be expressed as: K1DD...D, and the second code block set can be expressed as: K2DD...D.

[0131] In one possible implementation, any one or more of the multiple first code block sets obtained in S21 may further include a third control code block, which can be used to indicate the position of the first code block set to which it belongs in the multiple code block sets. The third control code block is a control code block whose position in the multiple code block sets is known in the code block encoding strategy provided in the embodiment of the present application. Unlike the first control code block, the third control code block can be any control code block that does not include a comma, including but not limited to K23.7 or K27.7. Taking the example where the first control code block is the starting code block of the first code block set, the second first code block set includes a third control code block adjacent to the first control code block, and the second code block set is composed of multiple data code blocks, the first control code block is still represented as K, the third control code block is represented as F, and the data code block is represented as D. After the training frame is encoded with the code block provided in the embodiment of the present application, the multiple code block sets obtained can be shown in Figure 9. The multiple code block sets include multiple first code block sets and one second code block set in sequence. The first code block sets other than the second first code block set in the multiple first code block sets can be represented as: KDD...D, the second first code block set can be represented as: KFD...D, and the second code block set can be represented as: DD...D.

[0132] It should be noted that, if the second control code block is the starting code block of the second code block set, the information field in the second subframe needs to not occupy the first several bits of the second subframe. For example, the information field shown in FIG1 needs to be moved to the middle or end of subframe L / N. Similarly, if the second control code block is the ending code block of the second code block set, the information field in the second subframe needs to not occupy the last several bits of the second subframe. That is, the information field shown in FIG1 needs to remain at the beginning of subframe L / N or be moved to the middle of subframe L / N.

[0133] The various possible situations after the code block encoding of the training frame mentioned above are all possible results obtained under the code block encoding strategy provided in the embodiment of the present application. The technical effects of different code block encoding strategies and corresponding decoding strategies are detailed in the relevant description of the following method 200.

[0134] In one possible implementation, after S102, method 100 may further include: the first PHY sending the first code block set to the second PHY. As an example, referring to the scenarios shown in Figures 3a to 3d, the first PHY may first perform PAM mapping on multiple code block sets (including the first code block set) obtained by code block encoding the training frame to obtain a symbol sequence; then, the first PHY sends the symbol sequence to the second PHY via a cable, thereby implementing signal transmission between the first PHY and the second PHY.

[0135] It can be seen that, through this method 100, the code block set obtained after code block encoding of the subframe in the training frame includes a control code block. The control code block is used to determine the boundary code block between the code block set and the adjacent code block set. Therefore, during the code block decoding process of the training sequence including the training frame, the boundary of the subframe in the obtained training sequence can be quickly and accurately determined through the control code block, paving the way for the rapid and accurate implementation of scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0136] Figure 10 is a flowchart illustrating a decoding method 200 provided in an embodiment of the present application. In this method 200, the present application embodiment is described using the second PHY as the execution entity. The second PHY can be, for example, any of the PHYs in the scenarios shown in Figures 3a to 3d. For example, if the second PHY corresponds to PHY 2 in Figure 3a, then the method 200 can be understood as being implemented by PHY 2 or by switch 2 including PHY 2. For another example, if the second PHY corresponds to PHY 4 in Figure 3d, then the method 200 can be understood as being implemented by PHY 4 or by terminal device 4 including PHY 4.

[0137] As shown in FIG10 , the method 200 may include, for example, the following steps S201 to S203 :

[0138] S201: A second PHY obtains a training sequence, where the training sequence includes a first code block set, and the first code block set includes a first control code block.

[0139] As an example, S201 may include: after the second PHY receives the symbol sequence sent by the first PHY, performing PAM demapping on the received symbol sequence to obtain a corresponding bit sequence, which can be used as the training sequence obtained in S201. Therefore, before S201, the first PHY may execute S101 to S103 above, paving the way for the second PHY, as the receiver, to accurately execute S201 to S203.

[0140] The second PHY can process the training sequence in a serial or parallel manner, where parallel processing means that one clock beat processes a bit sequence corresponding to m bits (m is usually an integer multiple of 2). Therefore, parallel processing can reduce the requirements for the hardware clock frequency. Taking m=50 as an example, that is, one clock beat processes a bit sequence corresponding to 50 bits in parallel. The second PHY can first align the boundaries of the code blocks with the clock edges based on methods such as code block reorganization. For example, first, search for the first control code block including the comma field in the 50 bits to identify the code block boundaries. Assuming that the 14th bit in the data set of a clock beat corresponds to the starting boundary of the code block, the 14th to 50th bits of this clock beat can be reorganized with the 1st to 13th bits of the next clock beat to form a new data set of a clock beat. In this way, it is ensured that the data set of each clock beat includes 5 complete 10-bit code blocks.

[0141] If the PAM mapping process of the multiple code block sets after the first PHY performs code block encoding on the training frame, the cable transmission process, and the analog and digital signal processing and PAM demapping process of the received signal by the second PHY are all correct, then the training sequence recovered by the receiving end can be understood as the data obtained after the first PHY performs code block encoding on at least one training frame. The beginning of the training sequence can be any code block set corresponding to a training frame, and the end of the training sequence can be any code block set corresponding to the training frame or another training frame. It should be noted that the training sequence does not necessarily include all code block sets corresponding to any training frame. For example, the training sequence can include, in sequence: all code block sets after the third first code block set corresponding to training frame A, all code block sets corresponding to training frame B, all code block sets corresponding to training frame C, and the first five first code block sets corresponding to training frame D.

[0142] For the relevant description of the first code block set and the first control code block in S201, reference may be made to the relevant description in S102 of the above method 100.

[0143] S202: The second PHY determines, according to the first control code block, a first boundary code block between the first code block set and an adjacent code block set.

[0144] As an example, if the first control code block is the starting code block or the ending code block of the first code block set, then the first control code block is the first boundary code block between the first code block set and the adjacent code block set. In the scenarios shown in Figures 5, 7, 8, and 9, if the first control code block is the starting code block of the first code block set, then the first control code block can serve as the first boundary code block between the first code block set and the adjacent previous code block set; in the scenario shown in Figure 6, if the first control code block is the ending code block of the first code block set, then the first control code block can serve as the first boundary code block between the first code block set and the adjacent subsequent code block set.

[0145] As another example, if the first control code block is an intermediate code block of the first code block set, then the first boundary code block can be determined based on the first control code block and the offset (offset bit or number of offset code blocks) of the first control code block relative to the first boundary code block in the first code block set. For example, the first control code block can be offset in the first code block set by its offset relative to the first boundary code block to determine the first boundary code block.

[0146] It can be seen that by identifying the first control code block in the first code block set in S202, the first boundary code block between the first code block set and the adjacent code block set can be quickly determined based on the first control code block, preparing for determining the subframe boundary in S203.

[0147] It should be noted that after the reliable delimitation of the code blocks is completed in S202, the delimitation result of the code block set can also be used to initialize the PCS scrambler. For example, the initialization value of the PCS scrambler can be selected from the training bit stream after decoding the first boundary code block. Taking the PMA training scenario as an example, in the training bit stream obtained by decoding the first code block set starting from the first boundary code block, the first bit is inverted, and the other bits can remain unchanged. After the PCS scrambler is initialized, an exclusive OR operation is performed with the decoded training bit stream to achieve descrambling.

[0148] In one possible implementation, to improve the reliability of code block set delimitation, the following operation may be performed: using the position of the first control code block as a reference, the position where the first control code block should appear is inferred, and the reliability of the code block set delimitation performed in S202 is determined based on whether the first control code block actually appears at the position where the first control code block should appear. Taking into account the impact of the bit error rate, a preset value may be set. If greater than or equal to the preset number of first control code blocks actually appear at the position where the first control code block should appear in a target number of training frames, the code block set delimitation is considered reliable. The preset value may refer to the minimum number of first control code blocks allowed to actually appear at the position where the first control code block should appear in the target number of training frames, provided that the code block set delimitation is reliable.

[0149] Taking the total length of the training frame L bits, including (L / N) = M subframes as an example, N is the length of each subframe, and each subframe is coded in 8B / 10B mode to generate a corresponding code block set formed by (L / 8M) = (N / 8) code blocks. Assuming that the second code block set corresponding to the subframe where the information domain is located is composed of multiple data code blocks, and the first code block in the first code block set generated by other subframes is the first control code block containing the comma field, as shown in Figure 5, then the second PHY can search the comma field in the training sequence corresponding to the received symbol sequence to preliminarily identify the first control code block, and use it as the first code block set and the adjacent code block set. Boundary code blocks: Starting from the current first control code block, code blocks are periodically extracted at intervals of (L / 8M-1) code blocks to obtain M code blocks. Ideally, if the code block set is correctly delimited, then there should be at least (M-1) first control code blocks in these M code blocks, that is, 10*(M-1) bits are completely matched. However, due to factors such as link errors, the probability of meeting the ideal condition for determining accurate code block set delimitation (i.e., 10*(M-1) bits are completely matched) is very low. Therefore, this condition can be appropriately modified based on fault tolerance. For example, for each code block, whether the bit content at some positions matches can be used to determine whether the code block is the first control code block. For example, for the control code blocks generated by 8B / 10B encoding, if the content at the corresponding position of the comma in the 10-bit code block is b'0011111' or b'1100000', the current code block is considered to be the first control code block. For the P code blocks obtained, if O first control code blocks appear, the delimitation of the sub-code block set can be considered reliable. For another example, for the P code blocks obtained, if the proportion of first control code blocks reaches X%, the delimitation of the sub-code block set can be considered reliable. P can be less than or equal to M; the preset value can be O, the actual number of first control code blocks that appear, or X% (e.g., 80%) of the actual proportion of first control code blocks that appear. It should be noted that the specific values ​​of P, O, and X can be determined based on the content of fault tolerance considerations, for example, based on the link bit error rate in training mode.

[0150] S203: The second PHY determines a second boundary between the first subframe and an adjacent subframe according to the first boundary code block.

[0151] As an example, the second PHY may obtain indication information based on a delimitation rule, etc., which can provide information about whether the data set currently being processed in parallel includes the first boundary code block, as well as information about the position of the first boundary code block in the current data set. Thus, it can be understood that the indication information is used to indicate the position of the first boundary code block in the corresponding code block set. S203 may, for example, include: decoding the training sequence obtained in S201 based on the first boundary code block to obtain a training bit stream including at least the first subframe; and determining, in the training bit stream, a second boundary between the first subframe and an adjacent subframe according to the indication information. Still taking a data set with 50 bits in one clock beat and code block decoding using 8B / 10B as an example, a data set may include 5 code blocks. Then, the first boundary code block in these 5 code blocks may be the first code block, the second code block, the third code block, the fourth code block, or the fifth code block. Therefore, indication information with a length of at least 3 bits can be used to indicate which code block in the data set is a boundary code block. In this way, the position of the subframe boundary can be determined in a parallel bit set of the training bit stream after code block decoding based on the indication information. For example, if the indication information = 010, indicating that the second code block in the 50-bit data set is a boundary code block, then after decoding, it can be determined that the 9th bit corresponds to the 1st bit of the subframe, that is, the 9th bit after decoding is the boundary of the subframe.

[0152] As another example, S203 may include: the second PHY first decodes the training sequence to obtain a training bit stream; performs an exclusive-OR operation (i.e., descrambling) on ​​the training bit stream and the PRBS generated by the PCS scrambler; and determines whether the bit stream obtained by the exclusive-OR operation within a preset time meets expected characteristics. If so, the scrambling code synchronization is determined; if not, the scrambling code is determined to be out of synchronization; if the scrambling code synchronization is determined, the second PHY may determine the subframe boundary, including the second boundary between the first subframe and the adjacent subframe, based on the characteristics of the descrambled bit stream. It should be noted that the second PHY may decode the training sequence according to a pre-assumed code block boundary. If the scrambling code is determined to be out of synchronization, it indicates that the pre-assumed code block boundary is inaccurate. In this case, the code block boundary may be shifted by 1 bit and the training sequence may be decoded again. This process is repeated until scrambling code synchronization is determined after decoding the training sequence.

[0153] It should be noted that the first code block set mentioned above can refer to the code block set obtained by performing code block encoding on any subframe of the training frame. To distinguish the code block sets obtained by performing code block encoding on a subframe including an information field from those obtained by performing code block encoding on a subframe not including an information field, the following description will use the first code block set to represent the code block set obtained by performing code block encoding on a first subframe not including an information field, and the second code block set to represent the code block set obtained by performing code block encoding on a second subframe including an information field. For details on the information field and the second code block set, refer to the description of method 100 above.

[0154] As an example, the second code block set may include a second control code block. Then, method 200 may further include: S204, the second PHY determining a third boundary code block between the second code block set and an adjacent code block set based on the second control code block; S205, the second PHY determining a fourth boundary between the second subframe and an adjacent subframe based on the third boundary code block. The fourth boundary may be, for example, a boundary between the second subframe and the first subframe of the next adjacent training frame; or a boundary between the second subframe and the previous adjacent first subframe.

[0155] Depending on the code block encoding strategy used, the method for determining the third boundary code block in S204 varies. For example, assuming that the value of the second control code block before encoding is the same as the value of the first control code block before encoding, the number of second control code blocks is the same as the number of first control code blocks, and the second control code block and the first control code block are in the same position in the corresponding code block set, as shown in Figure 6, then the information domain and the fourth boundary between the second subframe in which it is located and the adjacent subframe can be identified by comparing the bit stream characteristics obtained after code block decoding and descrambling with the information characteristics of the information domain to see if they match. For another example, assuming that the value of the second control code block before encoding is the same as the value of the first control code block before encoding, the second control code block and the first control code block are in the same position in the corresponding code block set, and the number of second control code blocks is different from the first control code block, as shown in Figure 7, then the second code block set in which the information domain is located can be determined by the number of second control code blocks. Then, the third boundary code block of the second code block set can be determined by the second control code blocks in the second code block set, thereby determining the fourth boundary between the second subframe and the adjacent subframe. For another example, assuming that the value of the second control code block before encoding is different from the value of the first control code block before encoding, but the second control code block and the first control code block have the same position in the corresponding code block set, and the number of second control code blocks is the same as the number of first control code blocks, as shown in Figure 8, then the fourth boundary between the second subframe and the adjacent subframe can be determined by the decoded value of the second control code block and its bit position in the training frame.

[0156] As another example, the second code block set may be composed of multiple data code blocks, excluding the second control code block. In this case, the method may further include: S204, the second PHY determining a third boundary code block between the second code block set and the adjacent code block set based on the data code block in the second code block set corresponding to the position where the first control code block in the first code block set appears; S205, the second PHY determining a fourth boundary code block between the second subframe and the adjacent subframe based on the third boundary code block. For example, as shown in FIG5 , when periodically searching for the first control code block, once it is detected that a data code block has encroached on the position where the first control code block should appear, the current code block set may be considered to be the second code block set where the information domain is located. Thus, the position in the second code block set that encroaches on the first control code block (actually a data code block) is recorded as the third boundary code block between the second code block set and the previous code block set. Thus, based on the third boundary code block, the fourth boundary between the second subframe and the adjacent subframe is determined.

[0157] In the above two examples, for the specific implementation of S205, reference may be made to the above two possible implementations of S203.

[0158] In one possible implementation, after S203, method 200 may further include: S206, determining a training frame, where the training frame may include at least a first subframe. That is, after delimiting the subframes, the training frame may be delimited based on the delimited subframes to obtain at least one training frame included in the training bitstream after decoding the training sequence.

[0159] As an example, S206 may include: decoding a training sequence to obtain a training bit stream; determining a boundary of a subframe based on the descrambled characteristics of the training bit stream, and further determining a subframe in the training bit stream that includes an information domain by comparing whether the characteristics of the descrambled bit stream match the characteristics of the information in the information domain; determining the end boundary of the subframe that includes the information domain as the boundary of the training frame; and obtaining at least one training frame from the training bit stream based on the boundary of the training frame.

[0160] Taking the PMA training frame shown in Figure 1 as an example, since for the first PHY, except for the last second subframe carrying the information field, the first bit of other first subframes has been inverted, therefore, under the condition of a relatively low bit error rate, the training bit stream for determining scrambler synchronization should satisfy: in the training bit stream, for a bit sequence S[n] (0 ≤ n ≤ L - 1) of the same length as the training frame (including M subframes), starting from position k (0 ≤ k < L / M), the bit set T (T[m] = S[k + m*N], 0 ≤ m < M) at intervals of a certain length (N - 1 bit, where N = L / M) is almost all 1 (the value of the first bit after descrambling the second subframe carrying the information field can be 1 or 0, and the values of the first bits after descrambling other first subframes are all 1), and the information between two adjacent 1 bits are all 0, thereby confirming that the scrambler is synchronized, and position k corresponds to the start boundary of the subframe. According to the position where the continuous 1 bits in the bit set T[m] are interrupted (such as T[y]), or from matching with the start delimiter field of the InfoField, the position where the information field is located ( to ) and the boundary of the training frame (that is, corresponding to the first bit of the training frame) can be obtained. In this way, based on the rule that each training frame in the decoded training bit stream should follow, the subframe boundary, information field, and training frame boundary can be accurately determined.

[0161] Taking the implementation of decoding in the 8B / 10B manner as an example, the decoding process corresponding to this example can be seen in Figure 11 for example. This process can include: S31, for any bit position in the training sequence, set Slide = 0 for this bit position; S32, perform 8B / 10B decoding on the training sequence to obtain the training bit stream; S33, perform descrambling on the training bit stream to obtain the descrambling result; S34, judge whether the scrambler is synchronized according to the descrambling result. If so, execute S35, otherwise, Slide = Slide + 1, and return to execute S32 again; S35, subframe delimitation; S36, identify the boundary of the subframe where the information field is located and extract the information field; S37, training frame delimitation. In this way, accurate subframe delimitation of the training sequence after block coding can be achieved, thereby realizing information field extraction and training frame delimitation.

[0162] As another example, if the second boundary and the fourth boundary are determined in method 200, then S206 may, for example, include: decoding the training sequence to obtain a training bit stream; and determining a training frame in the training bit stream based on the second boundary and the fourth boundary. In the case where the second subframe is located at the boundary of the training frame, if the fourth boundary in the training bit stream is determined, the fourth boundary can be directly used as the boundary between different training frames, and at least one training frame can be obtained from the training bit stream. In the case where the second subframe is located in the middle of the training frame, if the fourth boundary in the training bit stream is determined, the boundary of the training frame can be determined based on the position of the second subframe in the training frame (such as the subframe sequence number) and the fourth boundary, thereby obtaining at least one training frame from the training bit stream. In this way, the boundary of the training frame can be quickly determined by combining the boundary of the second subframe including the information field and the boundary of the first subframe not including the information field.

[0163] As another example, if at least one first code block set in a training sequence includes, in addition to the first control code block, a third control code block, where the third control code block indicates the position of the first code block set within the plurality of code block sets, then training frame delimitation can be achieved regardless of whether the boundary of the second subframe including the information field is identified. S206 may, for example, include: decoding the training sequence to obtain a training bit stream; and determining a training frame in the training bit stream based on the third control code block and the second boundary. As shown in FIG9 , in addition to delimiting the training frame based on the second boundary and the fourth boundary, training frame delimitation can also be achieved based on the method shown in this example. Because the second boundary of each first subframe is known, and it is also known that the third control code block is located one block after the first control code block in the second first code block set, and because each training frame includes a fixed number of subframes and a fixed length, the boundary of the training frame can be determined by identifying the third control code block in the training sequence, thereby obtaining at least one training frame in the training bit stream based on the boundary of the training frame. In this way, the boundary of the training frame can be quickly determined by combining the boundary of the first subframe excluding the information field and the third control code block indicating the position.

[0164] Taking 8B / 10B decoding as an example and the second code block set consisting of multiple data code blocks as an example, the decoding process corresponding to the above two examples can be shown in Figure 12a. The process can include: S41, obtaining a code block boundary by identifying the first control code block in the training sequence; S42, decoding the training sequence in 8B / 10B to obtain a training bit stream; S43, for the first control code block in the training sequence, determining the first boundary code block between the first code block set and the adjacent code block set, and the indication information corresponding to the first boundary code block; S44, determining the second boundary between the first subframe and the adjacent subframe based on the indication information corresponding to the first boundary code block; S45, identifying the boundary of the subframe where the information field is located by monitoring whether the first control code block in the training bit stream is occupied by a data code block; S46, delimiting the training frame. S42 and S43 can be executed simultaneously between S41 and S44, or can be executed sequentially. The order of execution is not limited. If the training bit stream is descrambled before S45 , then the step of extracting the information field may be further performed while S45 is being executed or after S45 .

[0165] Alternatively, taking 8B / 10B decoding as an example and the second code block set consisting of multiple data code blocks as an example, the decoding process corresponding to the above two examples can be seen in Figure 12b. This process can include, for example: S51, identifying the first control code block in the training sequence to obtain the code block boundary; S52, decoding the training sequence in 8B / 10B mode to obtain a training bit stream; S53, identifying the boundary of the subframe where the information domain is located by monitoring whether the first control code block in the training bit stream is occupied by the data code block; S54, descrambling the training bit stream to obtain a descrambling result; S55, determining the second boundary between the first subframe and the adjacent subframe based on the descrambling result; S56, delimiting the training frame. After S54, the step of extracting the information domain can also be performed. In this way, it is possible to achieve fast and accurate subframe delimitation of the training sequence after code block encoding, thereby achieving fast and accurate training frame delimitation and information domain extraction.

[0166] It should be noted that fast and accurate training frame delimitation is critical for quickly switching to data mode and ensuring accurate FEC boundaries in data mode. Optionally, the accuracy of training frame delimitation can be further improved by verifying the consistency of the descrambled bitstream information with the SFD of the InfoField, thereby achieving reliable FEC delimitation.

[0167] In this way, through method 200, a code block decoding strategy corresponding to the training frame encoding method provided in the embodiment of the present application is defined. During code block decoding of the acquired training sequence, the boundary code blocks between the code block set and the adjacent code block set can be quickly and accurately determined based on the control code blocks included in the code block set in the training sequence. The boundary between the subframe corresponding to the code block set after code block decoding and the adjacent subframe is determined based on the boundary code blocks. In this way, the boundary of the subframe in the acquired training sequence is quickly and accurately determined, making it possible to quickly and accurately implement scrambling code synchronization, training frame delimitation, or FEC delimitation.

[0168] It should be noted that the above embodiments are described using 8B / 10B encoding or decoding as an example, which does not constitute a limitation on the encoding or decoding methods applicable to the embodiments of the present application. For example, the embodiments of the present application can also be applied to 9B / 10B encoding or decoding.

[0169] It should be noted that the steps in each process in the embodiments of the present application can be combined or replaced as long as the technical effects of the embodiments of the present application can be achieved, and do not constitute a special limitation on the embodiments of the present application.

[0170] Accordingly, the embodiment of the present application further provides a communication device 1300 (also referred to as an encoding device 1300 ), as shown in FIG13 . The communication device 1300 is applied to a first PHY, and may include: an acquisition unit 1301 and a first encoding unit 1302 .

[0171] in:

[0172] The acquisition unit 1301 is configured to acquire a training frame, where the training frame includes multiple subframes. The acquisition unit 1301 may execute S101 shown in FIG. 4 or FIG. 9 .

[0173] A first encoding unit 1302 is configured to perform code block encoding on a first subframe among the multiple subframes to obtain a first code block set. The first code block set includes a first control code block, and the first control code block is used to determine a boundary code block between the first code block set and an adjacent code block set. The first encoding unit 1302 may execute S102 shown in FIG. 4 or FIG. 9 .

[0174] In a possible implementation, a second subframe among the multiple subframes includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

[0175] In a possible implementation, the apparatus 1300 may further include: a second encoding unit configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set includes a second control code block.

[0176] As an example, the value of the first control code block before encoding is the same as the value of the second control code block before encoding.

[0177] As another example, the value of the first control code block before encoding is different from the value of the second control code block before encoding.

[0178] As yet another example, the number of the first control code blocks is different from the number of the second control code blocks.

[0179] As another example, the position of the first control code block in the first code block set is different from the position of the second control code block in the second code block set.

[0180] In a possible implementation, the apparatus 1300 further includes a third encoding unit configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set consists of multiple data code blocks.

[0181] In a possible implementation, the first control code block is a start code block or an end code block of the first code block set, and the first control code block is a boundary code block.

[0182] In another possible implementation, the first control code block is an intermediate code block of the first code block set, and the boundary code block is determined based on the position of the first control code block in the first code block set.

[0183] In a possible implementation, the first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame.

[0184] In a possible implementation, the apparatus 1300 may further include a sending unit, configured to send the first code block set to the second PHY, and may execute S103 shown in FIG9 .

[0185] In a possible implementation, the first encoding unit 1302 is specifically configured to encode the first subframe in 8B / 10B mode to obtain a first code block set.

[0186] In a possible implementation, the training frame is a PMA training frame.

[0187] It should be noted that various specific implementation modes of the communication device 1300 can be found in the relevant introduction of the method 100 corresponding to FIG. 4 or FIG. 9 , and will not be described in detail in this embodiment.

[0188] Correspondingly, an embodiment of the present application further provides a communication device 1400 (also referred to as a decoding device 1400 ), as shown in FIG14 .

[0189] The communication device 1400 may include: an acquisition unit 1401, a first determination unit 1402, and a second determination unit 1403.

[0190] The acquisition unit 1401 is configured to acquire a training sequence, where the training sequence includes a first code block set, and the first code block set includes a first control code block. The acquisition unit 1401 may execute S201 shown in FIG9 .

[0191] The first determining unit 1402 is configured to determine a first boundary code block between the first code block set and the adjacent code block set according to the first control code block. The first determining unit 1402 may execute S202 shown in FIG9 .

[0192] The second determining unit 1403 is configured to determine a second boundary between the first subframe and an adjacent subframe according to the first boundary code block. The second determining unit 1403 may execute S203 shown in FIG9 .

[0193] In a possible implementation, the apparatus 1400 may further include: a third determining unit, configured to determine a training frame, where the training frame includes a first subframe.

[0194] In a possible implementation, the training sequence further includes a second code block set, where the second code block set is obtained by performing code block encoding on the second subframe. The second subframe includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

[0195] As an example, the second code block set includes a second control code block, and the apparatus 1400 further includes: a fourth determining unit and a fifth determining unit. The fourth determining unit is configured to determine, based on the second control code block, a third boundary code block between the second code block set and an adjacent code block set; and the fifth determining unit is configured to determine, based on the third boundary code block, a fourth boundary between the second subframe and an adjacent subframe.

[0196] As another example, the second code block set consists of multiple data code blocks, and the apparatus 1400 further includes a sixth determining unit configured to determine a fourth boundary between the second subframe and an adjacent subframe based on a data code block in the second code block set corresponding to an occurrence position of the first control code block in the first code block set.

[0197] In this implementation, the third determining unit is specifically configured to: decode the training sequence to obtain a training bit stream; and determine a training frame in the training bit stream according to the second boundary and the fourth boundary.

[0198] In another possible implementation, the first code block set also includes a third control code block, and the third control code block is used to indicate the position of the first code block set including the third control code block in multiple code block sets. The multiple code block sets are obtained by performing code block encoding on the training frame. The third determination unit is specifically used to: decode the training sequence to obtain a training bit stream; and determine the boundary of the training frame in the training bit stream based on the third control code block and the second boundary.

[0199] In one possible implementation, the second determination unit 1402 is specifically used to: decode the training sequence according to the first boundary code block to obtain a training bit stream, where the training bit stream includes a first subframe; and determine the second boundary in the training bit stream according to the indication information, where the indication information is used to indicate the position of the first boundary code block in the corresponding code block set.

[0200] In a possible implementation, decoding is performed in 8B / 10B mode.

[0201] It should be noted that various specific implementation modes of the communication device 1400 can be found in the relevant introduction of the method 200 corresponding to FIG9 , and will not be described in detail in this embodiment.

[0202] Referring to Figure 15 , an embodiment of the present application provides a communication device 1500. This communication device 1500 can be the execution entity of any of the aforementioned embodiments. This communication device 1500 can implement the functions of the aforementioned embodiments. This communication device 1500 includes at least one processor 1501, a bus system 1502, a memory 1503, and at least one communication interface 1504.

[0203] The communication device 1500 is a hardware device that can be used to implement the functional modules in the communication device 1300 shown in Figure 13. For example, those skilled in the art can imagine that the acquisition unit 1301 and the first encoding unit 1302 in the communication device 1300 shown in Figure 13 can be implemented by the at least one processor 1501 calling the code in the memory 1503. For another example, those skilled in the art can imagine that the acquisition unit 1401, the first determination unit 1402, and the second determination unit 1403 in the communication device 1400 shown in Figure 14 can be implemented by the at least one processor 1501 calling the code in the memory 1503.

[0204] Optionally, the communication device 1500 may be a network device or a control entity implementing an embodiment of the present application.

[0205] Optionally, the processor 1501 may be a general-purpose central processing unit (CPU), a network processor (NP), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.

[0206] The bus system 1502 may include a channel for transmitting information between the components.

[0207] The communication interface 1504 is used to communicate with other devices or communication networks.

[0208] The above-mentioned memory 1503 can be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited to this. The memory can exist independently and be connected to the processor through a bus. The memory can also be integrated with the processor.

[0209] The memory 1503 is used to store application code for executing the solution of the present application, and the execution is controlled by the processor 1501. The processor 1501 is used to execute the application code stored in the memory 1503, thereby realizing the functions of the method of the present application.

[0210] In a specific implementation, as an embodiment, the processor 1501 may include one or more CPUs, such as CPU0 and CPU1 in FIG15 .

[0211] In a specific implementation, as an embodiment, the communication device 1500 may include multiple processors, such as processor 1501 and processor 1507 in Figure 15. Each of these processors may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. The processor here may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0212] It should be understood that the communication devices or communication equipment in the various product forms mentioned above respectively have any functions implemented by the execution subject in the above method embodiments, which will not be described in detail here.

[0213] The present application also provides a chip including a processor and an interface circuit, wherein the interface circuit is configured to receive instructions and transmit them to the processor; the processor, which may be, for example, a specific implementation of the message processing device in the present application embodiment, may be configured to execute the above-described method 100 or method 200. The processor is coupled to a memory configured to store programs or instructions. When the programs or instructions are executed by the processor, the chip system implements the method in any of the above-described method embodiments.

[0214] Optionally, there may be one or more processors in the chip system. The processor may be implemented in hardware or software. When implemented in hardware, the processor may be a logic circuit, an integrated circuit, etc. When implemented in software, the processor may be a general-purpose processor implemented by reading software code stored in a memory.

[0215] Optionally, the memory in the chip system may be one or more memories. The memory may be integrated with the processor or may be provided separately from the processor, which is not limited in this application. For example, the memory may be a non-transient processor, such as a read-only memory (ROM), which may be integrated with the processor on the same chip or provided on different chips. This application does not specifically limit the type of memory or the configuration of the memory and the processor.

[0216] Exemplarily, the chip system can be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on chip (SoC), a central processor unit (CPU), a network processor (NP), a digital signal processor (DSP), a microcontroller unit (MCU), a programmable logic device (PLD) or other integrated chips.

[0217] In addition, an embodiment of the present application further provides a communication device, which includes a first PHY and / or a second PHY, the first PHY is used to execute the method 100 shown in Figure 4 or Figure 9; the second PHY is used to execute the method 200 shown in Figure 9.

[0218] In addition, an embodiment of the present application further provides a communication system 1600, as shown in FIG16 . The communication system 1600 may include a first communication device 1610 and a second communication device 1620, wherein the first communication device includes a first PHY 1611, and the second communication device includes a second PHY 1621. The first PHY 1611 is configured to execute the method 100 shown in FIG4 or FIG9 ; the second PHY 1621 is configured to execute the method 200 shown in FIG9 .

[0219] In addition, an embodiment of the present application further provides a storage medium, in which program code or instructions are stored. When the storage medium is run on a processor, the processor executes a method in any one of the implementation modes of the above embodiments.

[0220] In addition, an embodiment of the present application also provides a program product, which, when executed on a processor, enables the processor to execute any one of the aforementioned methods 100 or 200.

[0221] It should be understood that "determining B based on A" mentioned in the embodiments of the present application does not mean determining B only based on A, but B can also be determined based on A and / or other information.

[0222] It should be understood that the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0223] In this application, ordinal numbers such as "1", "2", "3", "first", "second" and "third" are used to distinguish multiple objects and are not used to limit the order of multiple objects.

[0224] “A and / or B” mentioned in this application should be understood to include the following situations: only A, only B, or both A and B.

[0225] Through the description of the above embodiments, it can be known that those skilled in the art can clearly understand that all or part of the steps in the above embodiment methods can be implemented by means of software plus a general hardware platform. Based on this understanding, the technical solution of the present application can be embodied in the form of a software product, which can be stored in a storage medium, such as a read-only memory (ROM) / RAM, a magnetic disk, an optical disk, etc., and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network communication device such as a router) to execute the methods described in each embodiment or certain parts of the embodiments of the present application.

[0226] Each embodiment in this specification is described in a progressive manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments. In particular, for system embodiments and device embodiments, since they are basically similar to method embodiments, the description is relatively simple. For relevant parts, refer to the partial description of the method embodiment. The device and system embodiments described above are merely schematic. The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without making any creative effort.

[0227] The above description is only a preferred embodiment of the present application and is not intended to limit the scope of protection of the present application. It should be noted that those skilled in the art may make several improvements and modifications without departing from the scope of protection of the present application, and such improvements and modifications should also be considered as within the scope of protection of the present application.

Claims

1. A coding method, characterized in that: Applied to the first physical layer PHY, the method includes: Acquire a training frame, where the training frame includes multiple subframes; Code block encoding is performed on a first subframe of the multiple subframes to obtain a first code block set, where the first code block set includes a first control code block, and the first control code block is used to determine a boundary code block between the first code block set and an adjacent code block set.

2. The method according to claim 1, characterized in that A second subframe of the plurality of subframes includes an information field including configuration information for a link between the first PHY and the second PHY.

3. The method according to claim 2, characterized in that The method further comprises: Code block encoding is performed on the second subframe to obtain a second code block set, where the second code block set includes a second control code block.

4. The method according to claim 3, characterized in that The value of the first control code block before encoding is the same as the value of the second control code block before encoding.

5. The method according to claim 3, characterized in that A value of the first control code block before encoding is different from a value of the second control code block before encoding.

6. The method according to claim 3, characterized in that The number of the first control code blocks is different from the number of the second control code blocks; or, A position of the first control code block in the first code block set is different from a position of the second control code block in the second code block set.

7. The method according to claim 2, characterized in that The method further comprises: Code block encoding is performed on the second subframe to obtain a second code block set, where the second code block set consists of multiple data code blocks.

8. The method according to any one of claims 1 to 7, characterized in that The first control code block is a start code block or an end code block of the first code block set, and the first control code block is the boundary code block.

9. The method according to any one of claims 1 to 7, characterized in that The first control code block is an intermediate code block of the first code block set, and the boundary code block is determined based on a position of the first control code block in the first code block set.

10. The method according to any one of claims 1 to 9, characterized in that The first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame.

11. The method according to any one of claims 1 to 10, characterized in that The method further comprises: The first set of code blocks is sent to a second PHY.

12. The method according to any one of claims 1 to 11, characterized in that The performing code block encoding on a first subframe among the multiple subframes to obtain a first code block set includes: The first subframe is encoded in 8B / 10B mode to obtain the first code block set.

13. The method according to any one of claims 1 to 12, characterized in that The training frame is a physical medium attachment (PMA) training frame.

14. A decoding method, characterized in that: Applied to the second physical layer PHY, the method includes: Acquire a training sequence, where the training sequence includes a first code block set, and the first code block set includes a first control code block; determining, according to the first control code block, a first boundary code block between the first code block set and an adjacent code block set; A second boundary between a first subframe and an adjacent subframe is determined according to the first boundary code block.

15. The method according to claim 14, characterized in that The method further comprises: A training frame is determined, where the training frame includes the first subframe.

16. The method according to claim 15, characterized in that The training sequence further includes a second code block set, where the second code block set is obtained by performing code block encoding on a second subframe. The second subframe includes an information field, where the information field includes configuration information for a link between the first PHY and the second PHY.

17. The method according to claim 16, characterized in that The second code block set includes a second control code block, and the method further includes: Determine, according to the second control code block, a third boundary code block between the second code block set and an adjacent code block set; A fourth boundary between the second subframe and an adjacent subframe is determined according to the third boundary code block.

18. The method according to claim 16, characterized in that The second code block set consists of multiple data code blocks, and the method further includes: A fourth boundary between the second subframe and an adjacent subframe is determined according to a data code block in the second code block set corresponding to an occurrence position of the first control code block in the first code block set.

19. The method according to claim 17 or 18, characterized in that The determining of the training frame comprises: Decoding the training sequence to obtain a training bit stream; The training frame is determined in the training bitstream according to the second boundary and the fourth boundary.

20. The method according to any one of claims 15 to 19, characterized in that: The first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set including the third control code block in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame. Determining the training frame includes: Decoding the training sequence to obtain a training bit stream; The boundary of the training frame is determined in the training bit stream based on the third control code block and the second boundary.

21. The method according to any one of claims 14 to 20, characterized in that: The determining, according to the first boundary code block, a second boundary between the first subframe and an adjacent subframe includes: Decoding the training sequence according to the first boundary code block to obtain a training bit stream, where the training bit stream includes the first subframe; The second boundary is determined in the training bit stream according to indication information, where the indication information is used to indicate a position of the first boundary code block in a corresponding code block set.

22. The method according to any one of claims 14 to 21, characterized in that The decoding is implemented in 8B / 10B mode.

23. A PHY chip, characterized in that: including a processor and an interface circuit; The interface circuit is used to receive instructions and transmit them to the processor; The processor is configured to obtain a training frame, where the training frame includes a plurality of subframes; The processor is further configured to perform code block encoding on a first subframe of the multiple subframes to obtain a first code block set, where the first code block set includes a first control code block, and the first control code block is used to determine a boundary code block between the first code block set and an adjacent code block set.

24. The PHY chip according to claim 23, wherein: A second subframe of the plurality of subframes includes an information field, where the information field includes configuration information for a link between the PHY chip and a counterpart PHY chip.

25. The PHY chip according to claim 24, wherein: The processor is further configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set includes a second control code block.

26. The PHY chip according to claim 25, characterized in that: The value of the first control code block before encoding is the same as the value of the second control code block before encoding; Alternatively, the value of the first control code block before encoding is different from the value of the second control code block before encoding; Alternatively, the number of the first control code blocks is different from the number of the second control code blocks; Alternatively, the position of the first control code block in the first code block set is different from the position of the second control code block in the second code block set.

27. The PHY chip according to claim 24, wherein: The processor is further configured to perform code block encoding on the second subframe to obtain a second code block set, where the second code block set consists of multiple data code blocks.

28. The PHY chip according to any one of claims 23 to 27, wherein: The first control code block is a start code block or an end code block of the first code block set, and the first control code block is the boundary code block; Alternatively, the first control code block is an intermediate code block of the first code block set, and the boundary code block is determined based on a position of the first control code block in the first code block set.

29. The PHY chip according to any one of claims 23 to 28, wherein: The first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame.

30. The PHY chip according to any one of claims 23 to 29, wherein: The interface circuit is further configured to send the first code block set to the opposite-end PHY chip.

31. A PHY chip, characterized in that: including a processor and an interface circuit; The interface circuit is used to receive instructions and transmit them to the processor; The processor is configured to obtain a training sequence, the training sequence including a first code block set, the first code block set including a first control code block; The processor is further configured to determine, based on the first control code block, a first boundary code block between the first code block set and an adjacent code block set; The processor is further configured to determine a second boundary between the first subframe and an adjacent subframe according to the first boundary code block.

32. The PHY chip according to claim 31, wherein: The processor is further configured to determine a training frame, where the training frame includes the first subframe.

33. The PHY chip according to claim 32, wherein: The training sequence also includes a second code block set, where the second code block set is obtained by performing code block encoding on a second subframe. The second subframe includes an information field, where the information field includes configuration information for a link between a peer PHY chip and the PHY.

34. The PHY chip according to claim 33, wherein: The second code block set includes a second control code block, The processor is further configured to determine, based on the second control code block, a third boundary code block between the second code block set and an adjacent code block set; The processor is further configured to determine a fourth boundary between the second subframe and an adjacent subframe according to the third boundary code block.

35. The PHY chip according to claim 33, wherein: The second code block set consists of multiple data code blocks, The processor is further configured to determine a fourth boundary between the second subframe and an adjacent subframe based on a data code block in the second code block set corresponding to an occurrence position of the first control code block in the first code block set.

36. The PHY chip according to claim 34 or 35, characterized in that: The processor is specifically configured to: Decoding the training sequence to obtain a training bit stream; The training frame is determined in the training bitstream according to the second boundary and the fourth boundary.

37. The PHY chip according to any one of claims 32 to 36, wherein: The first code block set further includes a third control code block, where the third control code block is used to indicate a position of the first code block set including the third control code block in multiple code block sets, where the multiple code block sets are obtained by performing code block encoding on the training frame. The processor is specifically configured to: Decoding the training sequence to obtain a training bit stream; The boundary of the training frame is determined in the training bit stream based on the third control code block and the second boundary.

38. The PHY chip according to any one of claims 31 to 37, wherein: The processor is specifically configured to: Decoding the training sequence according to the first boundary code block to obtain a training bit stream, where the training bit stream includes the first subframe; The second boundary is determined in the training bit stream according to indication information, where the indication information is used to indicate a position of the first boundary code block in a corresponding code block set.

39. A communication device, characterized in that: The communication device includes a memory and a processor; The memory is used to store instructions; The processor is configured to execute the instructions in the memory and perform the method according to any one of claims 1 to 22.

40. A communication system, characterized in that comprising a first communication device and a second communication device, wherein the first communication device comprises a first PHY and the second communication device comprises a second PHY; The first PHY is configured to perform the method according to any one of claims 1 to 13; The second PHY is configured to execute the method according to any one of claims 14 to 22.

41. A storage medium, characterized in that The storage medium includes instructions, and when the instructions are executed on a processor, the processor is caused to perform the method according to any one of claims 1 to 22.

42. A program product, characterized in that The program product includes a program, and when the program is run on a processor, the method according to any one of claims 1 to 22 is executed.

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