Optimized topology of a multi-core spiking neural network

Abstract

The disclosure regards a spiking neural network device comprising a plurality of cores, wherein each core is configured to generate and process a sequence of spike packets, wherein each of the cores is assigned to a router, said router being configured to transmit sequences of spike packets to one or more other routers or to receive sequences of spike packets from one or more other routers, and a plurality of transmission paths, wherein each transmission path is configured to connect two routers so that sequences of spike packets can be transmitted between the two routers, wherein the topology of the spiking neural network device is represented by a grid, in which the plurality of routers are arranged in a plurality of rows and a plurality of columns, wherein a substantially diamond-shaped or rhomboidal outline of the grid is obtained by letting the number of routers arranged in each row increase gradually by one or two routers between neighbouring rows from a minimum row length, such as one or two routers, in the two outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and by letting the number of routers arranged in each column increase gradually by one or two routers between neighbouring columns from a minimum column height, such as one or two routers, in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid.

Description

[0001] Optimized topology of a multi-core spiking neural network

[0002] The present disclosure relates to a novel topology of cores in a multi-core spiking neural network device.

[0003] Background

[0004] A spiking neural network (SNN) is an artificial neural network that can mimic a natural neural network. Spiking neural networks incorporate the concept of time into their operating model, meaning that neurons in the SNN do not transmit information at each propagation cycle, but only do so when a threshold value in the neuron is satisfied. When the threshold value is satisfied, the neuron can generate a signal that can be transmitted to other neurons.

[0005] The state of the art of multi-core spiking neural network involves a multitude of cores, which are connected via a router network, typically in two-dimensional meshes , allowing the transmission of information in the form of spike packets. Each core comprises a multitude of neurons as described above, where the threshold value for transmitting a spike packet is controlled by the individual neuron. The routers have the function of transmitting the generated spike packets among the cores, when the command to transmit a spike packet is given.

[0006] In multi-core SNN processors, a common challenge occurs which is the increased traffic of spike packets between routers, leading to traffic congestion and the potential loss of packets, and therefore to the reduction of throughput and accuracy of the SNN. To address such an issue, researchers have made modifications in the way the routers function, and in the way the routers can communicate with their surrounding routers. However, such modifications may still lead to packet loss or other complications. For example, it is possible to use a buffer in the router that stores more than one spike packet, yet such a technique is highly costly and it cannot guarantee solving the information loss challenge when the number of spike packets exceeds the buffer size.

[0007] Summary

[0008] One objective of the present disclosure is to provide a solution to traffic congestion and information loss in spiking neural network systems. In the state of the art of multi-core SNNs, as shown in Fig. 1 , a conventional setup of cores relates to a square pattern, where this example comprises 25 cores wherein each core is assigned to a single router. Each of the routers communicates with its neighbouring routers through transmission paths. In this example, the interior routers are connected to four other neighbouring routers, while the corner routers and the perimeter routers are connected to two and three neighbouring routers, respectively. A definition of the way the routers are classified in the present disclosure is provided in the next paragraphs. The fewer connections a router has to other routers, the higher the traffic congestions problems may occur in SNNs, and spike packets can be lost. In general, one router and one core are mutually assigned to each other. However, there can be multiple router networks routing spikes at the same time to reduce traffic. In an embodiment, it is possible to allocate more than one core to each router, increasing the traffic in the network.

[0009] Thus, a traditional spiking neural network device comprises a plurality of cores, wherein each core is configured to generate and process a sequence of spike packets, wherein each of the cores is assigned to a router, said router being configured to transmit sequences of spike packets to one or more other routers or to receive sequences of spike packets from one or more other routers, and a plurality of transmission paths, wherein each transmission path is configured to connect two routers so that sequences of spike packets can be transmitted between the two routers. The topology of the spiking neural network device is typically represented by a two-dimensional grid, in which the plurality of routers are arranged in a plurality of rows and a plurality of columns.

[0010] In order to overcome or at least minimise the above-mentioned problems related to traditional SNNs, the topology of the SNN according to the present disclosure is configured in such a way that a substantially diamond-shaped or rhomboidal topology is obtained by letting the number of routers arranged in each row increase gradually by one or two routers between neighbouring rows from a minimum row length, such as one or two routers, in the two outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and by letting the number of routers arranged in each column increase gradually by one or two routers between neighbouring columns from a minimum column height, such as one or two routers, in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid. For example, as shown in Fig. 2, 25 routers as in Fig. 1 are arranged in a rhomboidal topology comprising seven horizontal rows and seven vertical columns. Such a topology allows the maximization of transmission paths to each router, as for instance each of the perimeter routers are connected to four neighbouring routers and each of the four corner routers are connected to three neighbouring routers. In contrast, in the topology of Fig. 1 all the perimeter routers are connected to three neighbouring routers and the corner routers are connected to only two neighbouring routers. Therefore, such a rhomboidal arrangement of routers significantly enhances the efficiency of the spike packet transfer among routers of the spiking neural network device.

[0011] The routers can be classified in different groups of routers, namely interior routers, first type perimeter routers, second type perimeter routers and corner routers. Specifically, the spiking neural network device can be configured such that one or more of the routers are interior routers, which are characterised by neither being arranged at the start or the end of a row, nor at the top or the bottom of a column of the grid and by being connected through four transmission paths to its neighbouring routers on both sides within the row and to its neighbouring routers on both sides within the column, respectively.

[0012] In addition, the spiking neural network device can be configured such that one or more of the routers are first type perimeter routers, which are characterised by being arranged at the start or the end of a row with at least two routers and at the top or the bottom of a column with at least two routers and by being connected through four transmission paths to its neighbouring router in the row, to its neighbouring router in the column, and to the two routers arranged at the corresponding start or end of the two neighbouring rows, which are also the two routers arranged at the corresponding top or bottom of the two neighbouring columns, respectively.

[0013] Moreover, the spiking neural network device can be configured such that one or more of the routers are second type perimeter routers, which are characterised by being arranged at the start or the end of a row with at least two routers and at the top or the bottom of a column with at least two routers and by being connected through three transmission paths to its neighbouring router in the row, to its neighbouring router in the column, and to a router arranged at the corresponding start or end of a neighbouring row and at the corresponding top or bottom of a neighbouring column, respectively. The spiking neural network device can be configured, such that one or more of the routers are corner routers, which are characterised by being arranged as the single routers in the outermost rows or outermost columns of the grid, each of which corner routers is connected through two or three transmission paths to the each of the routers in the neighbouring row or column, respectively.

[0014] In some embodiments of the spiking neural network device according to the present disclosure, each of the plurality of cores can be equipped with a sparse synapse address generator, configured to skip the processing of non-firing inputs. Such a mechanism can improve the processing speed of neurons in a core, resulting in realtime processing of data.

[0015] The routers of the SNN can be configured, such that each router comprises a communication system, controlling the communication between said router and its neighbouring routers. The term neighbouring routers is defined as the routers, which are connected to each other through a transmission path, thereby allowing the transmission of spike packets between them.

[0016] In summary, the present disclosure provides an efficient novel configuration of routers in a spiking neural network device, which can minimize the loss of information and increase the efficiency of the spiking neural network device, while at the same time keeping the costs of developing a spiking neural network device at a minimum.

[0017] Description of Drawings

[0018] Various embodiments are described hereinafter with reference to the drawings. The drawings are examples of embodiments and are intended to illustrate some of the features of the presently disclosed optimized topology of a spiking neural network device, and are not limiting to the presently disclosed system and method.

[0019] Fig. 1 shows a schematic of 25 routers arranged in a square mesh as known in the art. Fig. 2 shows a schematic of 25 routers arranged in a substantially rhomboidal grid according to an embodiment of the present disclosure.

[0020] Fig. 3 shows a schematic of 64 routers arranged in a substantially rhomboidal grid according to an embodiment of the present disclosure. Fig. 4 shows a schematic of 256 routers arranged in a substantially rhomboidal grid according to an embodiment of the present disclosure.

[0021] Fig. 5 shows a format example of a generated spike packet.

[0022] Fig. 6 A and B show an example of synaptic connections in a core and a synaptic crossbar architecture of cores.

[0023] Fig. 7 shows an embodiment of a router according to an embodiment of the present disclosure.

[0024] Fig. 8 shows an example of a spiking neural network device illustrating the possible paths for transmitting spike packets between routers depending on the initial routing direction.

[0025] Fig. 9 shows a schematic illustrating intradevice and interdevice communication among spiking neural network devices.

[0026] Fig. 10 shows an example of a generated spike packet comprising intradevice and interdevice information.

[0027] Fig. 11 A, B shows a schematic of an integrated circuit and a system respectively comprising one or more spiking neural network devices.

[0028] Detailed description

[0029] The present disclosure relates to a spiking neural network device comprising a plurality of cores, wherein each core is configured to generate and process a sequence of spike packets, wherein each of the cores is assigned to a router, said router being configured to transmit sequences of spike packets to one or more other routers or to receive sequences of spike packets from one or more other routers. Each core can comprise a plurality of neurons, and the router assigned to each core can manage the spike packets generated by the neurons. Each core can also comprise a plurality of input axons and synaptic crossbar implementing the synaptic connections in the core.

[0030] The spiking neural network device further comprises a router network comprising a plurality of transmission paths, wherein each transmission path is configured to connect two routers so that sequences of spike packets can be transmitted between the two routers.

[0031] The topology of the spiking neural network device can be represented by a grid, in which the plurality of routers are arranged in a plurality of rows and a plurality of columns, wherein a substantially diamond-shaped or rhomboidal outline of the grid is obtained by letting the number of routers arranged in each row increase gradually by one or two routers between neighbouring rows from a minimum row length, such as one or two routers, in the two outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and by letting the number of routers arranged in each column increase gradually by one or two routers between neighbouring columns from a minimum column height, such as one or two routers, in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid.

[0032] For example, as shown in Fig. 2, 25 routers are arranged in a diamond-shaped grid 2, having seven horizontal rows and seven vertical columns. The number of routers in the first row 10 is one, and the number of routers increases gradually reaching a maximum number of routers at the central row 11 , before the number of routers decreases again. The columns of the grid are arranged in a symmetric fashion. The number of routers in the first column 12 is one, and the number of routers increases gradually reaching a maximum number of routers at the central column 13, before the number of routers decreases again. Such an arrangement of routers leads to maximizing the number of transmission paths 9 to each router, as every router in this example has four transmission paths 9 to neighbouring routers, except for the four routers in the single rows and columns respectively. In contrast, if that number of routers were arranged in a typical square mesh, as shown in Fig. 1 , then all the routers arranged in the perimeter (including the corners) of the square mesh would have two or three transmission paths 9 to neighbouring routers, leading to reduced connectivity of the routers, and possible traffic congestion. Fig. 1 shows a conventional setup of routers arranged in a square pattern 1 , where this example comprises 25 routers wherein each router is connected to a neighbouring router through a transmission path 9. In this example, the interior routers 5 are connected to four other neighbouring routers, while the corner routers 8 and the perimeter routers 7 are connected to two and three neighbouring routers, respectively. As a result, an SNN with 25 routers arranged in the topology of Fig. 1 has a total of 40 transmission paths, whereas an SNN with 25 routers arranged in the topology of Fig. 2 has a total of 48 transmission paths. Moreover, by arranging the routers in the rhomboidal topology as shown in Fig. 2, the rhomboidal topology can reduce the number of unutilized transmission paths by 50%, and it can reduce the average number of hops between any two routers by 14%, from average 2.5 hops to 2.15 hops. A hop is defined as a spike packet transfer between two neighbouring routers along a transmission path. A further advantage of the substantially diamond-shaped or rhomboidal outline of the grid is that the number of transmission paths (hops) bridging the two routers furthest apart from each other can be reduced significantly. For instance, the reduction is 17% for the case of 25 routers in a the router network. Depending on the total number of routers in the router network, that reduction will be different. For instance, the diagonally placed corner routers in Fig. 1 are connected via eight transmission paths 9, while in Fig. 2, the furthest apart routers can be connected via six transmission paths 9. Such a reduction of distance between routers can also lead to higher efficiency of the SNN, less routing latency, and reduction of spike traffic. Shortening the paths between cores results in less number of hops required for routing a spike, and reducing the latency as each hop takes one cycle in non-congested router. As a result, it can slightly reduce the congestion in the network. As also described in the summary of the present disclosure, such an arrangement of routers in a grid optimizes the number of transmission paths 9 to each router. A larger number of transmission paths allows the distribution of spikes over different transmission paths, resulting in less traffic in the router network and less probability of congestion. Therefore, the present disclosure provides a new setup of arranging routers in a number of rows and columns, by minimizing the number of routers that have three transmission paths, and maximizing the number of routers that have four transmission paths to neighbouring routers. The increase in transmission paths leads to a more controllable spike traffic.

[0033] As described in the summary of the present disclosure, the routers can be classified into different groups of routers, namely interior routers, first type perimeter routers, second type perimeter routers and corner routers. The interior routers and the first type perimeter routers are connected through four transmission paths to their neighbouring routers, while the second type perimeter routers are connected through three transmission paths to their neighbouring routers. The corner routers are connected through two or three transmission paths to each of the routers in the neighbouring row or column. A further advantage of the present disclosure, is that the first type perimeter routers have connections to routers which are positioned both in a different row and in a different column of the grid. As a result, when a spike packet is transmitted from a first type perimeter router, an option exists to perform both a vertical and a horizontal hop in a single hop, where a hop is defined as a spike packet transfer between two neighbouring routers. For example, the first type perimeter routers 6 pictured in Fig. 2 can transmit a spike packet to a different row and a to a different column by performing a single transfer towards the corner router 8. In contrast, an interior router 5 would be required to perform two hops, in order to transfer a spike packet to both a different row and a different column. As a result, first type perimeter routers 6 can assist in reducing the transmission distance and routing latency in spiking neural network devices, by benefiting from their unique topology.

[0034] Moreover, the spiking neural network device can be configured, such that each router is connected to at least two other routers via a plurality of transmission paths. For example, a corner router 8 shown in Fig. 3, is connected to two neighbouring routers, by using a transmission path 9 to each of the routers. Depending on the total number of routers in a grid, the number of connections to the corner routers can be changed. For example, for a total number of 25 routers, each corner router 8 is connected to three neighbouring routers, as shown in Fig. 2. However, for a number of 64 routers, each corner router 8 is connected to two neighbouring routers, as shown in Fig. 3.

[0035] Furthermore, the spiking neural network device can be configured, such that each router is connected with at most four other routers via a plurality of transmission paths. Typically, this limitation lies in the configuration of the routers, which are normally able to connect to four other routers only. However, if the configuration of the individual routers allows for it, in an embodiment, it is possible to introduce additional transmission paths 9, which can for example link routers in a diagonal pattern.

[0036] The possible number of routers in the spiking neural network device according to the present disclosure is not limited to square numbers, as will typically be the case with traditional SNNs like the one shown in Fig. 1. In the embodiments of Fig. 2, Fig. 3, and Fig. 4, the spiking neural network device is configured with square numbers of routers, namely 52, 82and 162, respectively. In fact, any square number of routers can be arranged in the substantially diamond-shaped or rhomboidal outline topology described in the present disclosure, whereby the number of interior routers 5 and first type perimeter routers 6 with four connections each is maximized.

[0037] A diamond-shaped topology with no second type perimeter routers and with three connections to each corner router can be obtained, if the number of routers within the SNN can be calculated from the expression 2N2+ 6N + 5, where N > 0 is an integer. For instance, the embodiment shown in Fig. 2 is represented by such a diamond- shaped topology, in which the number of routers is 25, which is obtained from this expression for N = 2.

[0038] A diamond-shaped topology with no second type perimeter routers but only two connections to each corner router can be obtained, if the number of routers within the SNN can be calculated from the expression 2N2+ 2N + 4, where N > 1 is an integer. For instance, the embodiment shown in Fig. 3 is represented by such an diamondshaped topology, in which the number of routers is 64, which is obtained from this expression for N = 5. As each core of the spiking neural network device is assigned to a router and only one core is assigned to each router, the number of cores is equal to the number of routers.

[0039] For the embodiment shown in Fig. 4, the number of routers is 256, which cannot be calculated from any of the two expressions. Therefore, the obtained substantially diamond-shaped topology comprises a number of second type perimeter routers with only three connections.

[0040] In an embodiment, the spiking neural network device is configured such that each core emulates a plurality of neurons and a plurality of input axons. For example, a core can emulate 256 neurons, 256 input axons and a 64k synaptic crossbar. Nevertheless, the number of neurons that can be emulated by a core can be scaled to larger numbers, too. An input axon can be considered as an element representing the information received from a neuron through the router network. An embodiment of a synaptic crossbar can be seen in Fig. 6A 600 where a plurality of input axons 605 are interconnected with a plurality of neurons 606. Neurons can be programmed to send spike packets to any input axon of any core. Moreover, the axons can be connected to the neurons of the core with an associated synaptic weight, programmed during the initialization of the system. Figure 6B shows an example of a synaptic crossbar architecture 601 of a core, comprising a plurality of neurons 603 and a plurality of input axons 604, where synaptic connections 602 are represented by dots.

[0041] In an embodiment, the spiking neural network device can be configured, such that each of the spike packets, which are generated by the cores, comprises a plurality of indexes, which indexes can be related to the validity, the destination, and the routing direction of the spike packet. The routing direction can be either horizontally and then vertically, or vice versa. The above features can be collected in the format of the spike packet, which is generated and injected into the router, to which the core is assigned, with the purpose to be sent to a core assigned to a router in the network.

[0042] For example, Fig. 5 shows an embodiment of a spike packet format 500, which is being transmitted through the router network. The direction bit 502 points to the first transmission direction of the spike packet. The dx and dy elements 503, 504 correspond to the number of horizontal and vertical hops respectively. For example, if a spike packet is to be transferred to a router that is on the column to the right of the router, and displaced two rows on top, then the dx would have a value “1” and the dy would have a value “2”. The input index 505 refers to the input axon of the destination core that is to receive the spike.

[0043] In an embodiment, the multi-core spiking neural network device can be further configured, such that each of the plurality of cores comprises a sparse synapse address generator, configured to skip the processing of non-firing inputs. The sparse synapse address generator can be a part of the synaptic crossbar architecture. During each timestep, the states of active neurons are updated by a sparse synapse address generator, which can skip the processing of non-firing inputs, thereby reducing the energy consumption, and accelerating the processing time.

[0044] Furthermore, the spiking neural network device can be configured, such that each router comprises a communication system having a sender and a receiver for each transmission path leading to and from the router, which senders and receivers are configured for controlling the communication between said router and its neighbouring routers, neighbouring routers being defined as routers, which are connected to each other through a transmission path. The communication system also comprises a core sender and a core receiver for sending spike packets to and from the core, which is assigned to the router. Controlling the communication may refer to modifying the rate of data transmission between routers, such that spike packets are not lost due to high congestion in a router. The communication system can for example comprise a plurality of senders and a plurality of receivers, which are configured to facilitate the spike transfer between neighbouring routers. The communication system can also comprise a core sender and a core receiver, facilitating the communication between a router and its corresponding core that is assigned to said router. Further details about that setup are given in the examples section of the application. Moreover, the spiking neural network device can be configured, such that the communication system allows each router to receive or request communication signals from a neighbouring router, or to send communication signals to a neighbouring router. Such communication signals can for example be handled from the receivers and senders in a router.

[0045] In an embodiment, the multi-core spiking neural network device can be further configured, such that one of the communication signals among routers is a status flag message, informing the neighbouring routers whether the transmission is permitted. Each sender of a router is connected to a specific receiver in a neighbouring router in a specific direction. For example, the “west” sender of a router is connected to the “east” receiver of the neighbouring router in the “west” direction. Such a solution can allow a status flag message to be shared among routers, and in the scenario that a router has a high load of spike packets, a new spike packet can be prevented from being sent to that router, to prevent spike transmission to a congested router and avoid packet drop. Such a status flag message can be set between each two neighbouring routers, generated by a receiver to inform a sender in the corresponding neighbouring router. Based on this status flag message, the corresponding sender may or may not allow spike transmission in that direction, possibly preventing a core from injecting a spike packet into a congested router, suspending the transmission of the spike packet for a given timeframe. Such a technique can further balance the operations in a spiking neural network device, and increase the throughput of the network. For example, if the “west" receiver of a router is congested, its neighbouring router in the “west” direction gets informed, and the “east” sender in the neighbouring router prohibits any packets from all receivers in that router to be sent in that direction.

[0046] Moreover, the present disclosure relates to an integrated circuit (IC) comprising a spiking neural network device that is configured according to any one of the embodiments described herein. Fig. 11 A shows a schematic of an integrated circuit 1101 comprising a spiking neural network device 2. The integrated circuit may also be understood as a chip.

[0047] The IC may be implemented as a standalone neuromorphic processing unit or integrated into a larger computing system, such as a multi-chip module (MCM) or a system-on-chip (SoC). The IC can be fabricated using various semiconductor technologies, including but not limited to CMOS, FinFET, or memristor-based architectures, enabling efficient implementation of spiking neural networks with low power consumption and high computational efficiency. The IC may be packaged in different formats, such as a ball grid array (BGA), quad flat package (QFP), or chip-scale package (CSP), depending on the target application and system integration requirements. In some embodiments, the IC may be mounted on a printed circuit board (PCB), where it interfaces with other components such as memory modules, sensor interfaces, and power management circuits. The PCB may further include high-speed data buses, network-on-chip (NoC) interconnects, or optical links to facilitate efficient communication between multiple ICs in a multi-chip neuromorphic system.

[0048] The present disclosure further relates to a system comprising a plurality of spiking neural network devices, the spiking neural networks devices arranged in a onedimensional or a two-dimensional array. Such an array may form a mesh network, where a plurality of spiking neural network devices can communicate with each other and internally to process and solve complex problems. A two-dimensional array enables the scalability of the spiking neural network device of the present disclosure, which enables the support of more extensive neural network architectures, leading to possibly improved fault tolerance and modularity. It should be stressed that the proposed architecture of the spiking neural network does not hinder the scalability of the disclosed system, as the system enables scaling the architecture using a plurality of spiking neural network devices arranged in a two-dimensional array. For example, such a geometry may be utilized for large language model development. In addition, the system may comprise a plurality of integrated circuits as described herein, wherein each integrated circuit comprises a spiking neural network device.

[0049] Furthermore, the system can be configured to perform intradevice routing. Intradevice routing refers to spike transfer between different routers inside a single spiking neural network device. For example, transmitting a spike packet from a corner router to a first type perimeter router is considered intradevice routing. By enabling intradevice routing, the system facilitates efficient communication within an individual SNN device, optimizing spike packet transmission between different regions while minimizing delays.

[0050] Moreover, the system can be configured to perform interdevice routing. Interdevice routing refers to spike transfer between neighbouring spiking neural network devices. By implementing interdevice routing, the system can extend neuromorphic processing across a plurality of devices, enabling larger and more distributed spiking neural networks. This allows for efficient neural signal transmission between devices, supporting scalability while maintaining low-latency operation. Interdevice routing is particularly useful for applications requiring massive parallelism, such as deep learning inference and real-time signal processing. Importantly, forming a two-dimensional architecture of SNN devices wherein each individual SNN device has the substantially diamond-shaped or rhomboidal geometry, as described in the present disclosure, can significantly reduce spike packet transmission latency, and increase the performance of SNN operations.

[0051] Furthermore, the system can be configured, such that interdevice routing is performed by transmitting a spike packet from a corner router of a first spiking neural network device to a corner router of a second spiking neural network device. For example, having two topologically adjacent SNN devices would lead to the eastward corner router of a first SNN device to being topologically adjacent to the westward corner router of a second SNN device. Therefore, it is possible to transmit a spike packet from the eastward corner router to the westward corner router, thereby enabling interdevice routing. The term “topologically adjacent” refers to SNN devices that are not necessarily physically adjacent in a circuit, but they are electrically adjacent. For example, in an integrated circuit, two SNN devices may be designed to communicate through two of their corner routers by using an electrical cable bridging the two corner routers. However, these two corner routers do not necessarily need to be physically adjacent for that connection to take place.

[0052] For example Fig. 9 shows a schematic of a system comprising four spiking neural network devices 900. A first router 901 of a first SNN device can transmit a spike packet to a corner router 902 of a second SNN device through a corner router 903 of the first SNN device. Such a process would require 4 horizontal hops. The dashed lines 904 relate to the process of interdevice routing among different corner routers.

[0053] Similarly to Fig. 5, Fig. 10 shows an embodiment of a spike packet format 1000 comprising an spike packet 1001 for interdevice routing, and an spike packet 1002 for intradevice routing. Such a spike packet can transmitted through various SNN devices. The input index 1003 refers to the input axon of the destination core that is to receive the spike. As also described in the previous sections, the dx and dy elements correspond to the number of horizontal and vertical hops respectively. To clarify which horizontal and vertical hop corresponds to spike transfer within an SNN device, or to spike transfer within different SNN devices, a notation can be used as following: dxintra, dyintra for intradevice hops, and dxinter, dyster for interdevice hops.

[0054] In an embodiment, the system can be configured, such that a corner router is configured to transmit a spike packet originating from a topologically adjacent spiking neural network towards one of its first type perimeter routers. For example, during interdevice routing, the corner routes may send the received spikes from the topologically adjacent devices in a predetermined direction, such as northward or southward for east and west corner routers, and eastward or westward for north and south corner routers. By relaying spike packets from corner routers to first type perimeter routers, the system establishes a structured routing hierarchy that improves communication efficiency while preventing congestion. This design can be particularly beneficial in multi-chip neuromorphic architectures where rapid spike transfer between chips is necessary for maintaining synchronous processing. Depending on the type and the needs of the application where a SNN devices can be used, different rules for spike transfer may be applied.

[0055] In an embodiment, each spiking neural network device may be associated with spike packets comprising more than one direction bits. Such a feature enables the corner routes to send the received spikes from the topologically adjacent devices to second type perimeter routers or to interior routers.

[0056] The system comprising a plurality of spiking neural network devices can be configured, such that each spiking neural network device is according to any one of the embodiments described in the present disclosure.

[0057] Fig. 11 B shows a schematic of a system 1 102 comprising four spiking neural network devices 2. The system may be programmed to enable communication between the various spiking neural networks devises that are comprised in the system. This may be achieved through configurable routing protocols that can manage the transfer of spike packets between topologically adjacent devices, ensuring low-latency and high- bandwidth data transfer. Depending on the type of application, the system can be programmed accordingly in order to achieve certain tasks. In addition, the spiking neural network device can be configured, such that each router comprises a stack register for storing one or more spike packets. Storing a plurality of spike packets can be beneficial, as it allows the spiking neural network device to control the spike traffic and prevent packet drop in case of congestion in the system. Even though a status flag message can be shared between routers, preventing an excess amount of spike packets from being transmitted, in certain cases, it may still be advantageous that each router comprises more than one stack register to be capable of storing more than one spike packet. For example, the receiver of a router can enable the stack register to store any pending spike packets, so that the receiver can store an incoming spike packet, guaranteeing that no spike packets will be dropped. In a synchronous circuit, updating the congestion status takes one cycle to be updated, and during that time, an incoming packet would be dropped. To avoid such a scenario, a stack register can be used to store the pending packet, allowing receiving the incoming spike and preventing packet drop. Then, in the next cycle, the status is updated, preventing the neighbouring routers from sending additional spikes.

[0058] Moreover, the spiking neural network device can further comprise a training algorithm. Such a training algorithm can for example be used to improve the accuracy of the spiking neural network device, while the system is compatible with the proposed router network architecture. A machine learning algorithm can be utilized, optionally with any kind of supervised or unsupervised training algorithm.

[0059] The present disclosure further relates to a method for designing a grid representing the topology of a spiking neural network according to the features described above. The method comprises the steps of obtaining a plurality of cores, wherein each of the cores is assigned to a router, arranging a plurality of routers in a plurality of rows and a plurality of columns, arranging the number of routers in each row by increasing gradually the number of routers by one or two routers between neighbouring rows from a minimum row length in the outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and arranging the number of routers in each column by increasing gradually the number of routers by one or two routers between neighbouring columns from a minimum column height in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid.

[0060] Examples Fig. 4 shows a schematic of a spiking neural network device with 256 routers arranged in a substantially rhomboidal-shaped grid. This network comprises interior routers 5, first type perimeter routers 6, corner routers 8 and second-type perimeter routers 7. The second-type perimeter routers 7 have the special feature that they are connected to three neighbouring routers only. Nevertheless, such an arrangement of 256 routers significantly increases the ratio of number of transmission paths 9 per router, as the state of the art method of arranging the routers in a square lattice leads to a much smaller number of transmission paths per router, and eventually the square lattice leads to higher spike traffic congestion in the network. In particular, 256 routers arranged in a square lattice would result in a total number of 480 transmission paths, while when arranged in the topology of Fig. 4, the total number of transmission paths 9 increases to 500. Furthermore, the distance between the furthest distant routers in a square lattice would be 30 hops, while for the topology shown in Fig. 4, it is reduced to 25 hops. Such a distance reduction can enhance the efficiency of the spiking neural network device.

[0061] Fig. 7 shows an example of a router architecture 704. The router architecture comprises four receivers 700, four senders 701 , a core receiver 702 and a core sender 703. Each core is assigned to a router, and its generated spike packets are injected into the router network through the core receiver to be delivered to the router of the destination core. Each of the four receivers of a core is configured to communicate with one of the neighbouring routers in the north, south, west, and east direction. Each packet is decoded, and a request is generated for a sender in connection with the next router. A handshake interface is employed between senders and receivers within a router, in which requests are sent to senders and accepted ones will be acknowledged. This router architecture can be implemented to the spiking neural network device according to any of the embodiments described above. Likewise, any type of routers may be used in other embodiments of SNNs according to the present disclosure.

[0062] In some representations of the topology of SNNs according to the present disclosure, the corner routers of the SNN can be displayed as not belonging to a distinct row or column, as shown in Fig. 8. Topologically, such an arrangement is considered similar to the way that the corner routers are shown in Fig. 4. In this particular example, 16 routers are arranged in a diamond-shaped grid, where the corner routers 800 have each two connections to neighbouring routers. Fig. 8 also illustrates the process of spike packet transmission between routers. For example, the router R3can transmit a spike packet to the router R4along a first path Pi or along a second path P2. Following the first path Pi, only two hops are required, whereas three hops (a vertical 801 hop followed by two horizontal hops 802, 803) are required if the second path P2is chosen. In a similar pattern, a spike packet can be transmitted between any two routers along different paths by performing a series of vertical and / or horizontal hops.

Claims

Claims1 . A spiking neural network device comprising:- a plurality of cores, wherein each core is configured to generate and process a sequence of spike packets, wherein each of the cores is assigned to a router, said router being configured to transmit sequences of spike packets to one or more other routers or to receive sequences of spike packets from one or more other routers, and- a router network comprising a plurality of transmission paths, wherein each transmission path is configured to connect two routers so that sequences of spike packets can be transmitted between the two routers, wherein the topology of the spiking neural network device is represented by a grid, in which the plurality of routers are arranged in a plurality of rows and a plurality of columns, wherein a substantially diamond-shaped or rhomboidal outline of the grid is obtained by letting the number of routers arranged in each row increase gradually by one or two routers between neighbouring rows from a minimum row length, such as one or two routers, in the two outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and by letting the number of routers arranged in each column increase gradually by one or two routers between neighbouring columns from a minimum column height, such as one or two routers, in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid.

2. The spiking neural network device according to claim 1 , wherein one or more of the routers are interior routers, which are characterised by neither being arranged at the start or the end of a row, nor at the top or the bottom of a column of the grid and by being connected through four transmission paths to its neighbouring routers on both sides within the row and to its neighbouring routers on both sides within the column, respectively.

3. The spiking neural network device according to any one of the preceding claims, wherein one or more of the routers are first type perimeter routers, which are characterised by being arranged at the start or the end of a row with at least two routes and at the top or the bottom of a column with at least two routers and by being connected through four transmission paths to its neighbouring router in the row, to its neighbouring router in the column, and to the two routers arranged at the corresponding start or end of the two neighbouring rows, which are also the two routers arranged at the corresponding top or bottom of the two neighbouring columns, respectively.

4. The spiking neural network device according to any one of the preceding claims, wherein one or more of the routers are second type perimeter routers, which are characterised by being arranged at the start or the end of a row with at least two routers and at the top or the bottom of a column with at least two routers and by being connected through three transmission paths to its neighbouring router in the row, to its neighbouring router in the column, and to a router arranged at the corresponding start or end of a neighbouring row and at the corresponding top or bottom of a neighbouring column, respectively.

5. The spiking neural network device according to any one of the preceding claims, wherein one or more of the routers are corner routers, which are characterised by being arranged as the single routers in the outermost rows or outermost columns of the grid, each of which corner routers is connected through two or three transmission paths to the each of the routers in the neighbouring row or column, respectively.

6. The spiking neural network device according to any one of the preceding claims, wherein each router is connected to at least two other routers via a plurality of transmission paths, and / or wherein each router is connected to at most four other routers via a plurality of transmission paths.

7. The spiking neural network device according to any one of the preceding claims, wherein the total number of routers is N2where N>3, such as 52, 82or8. The spiking neural network device according to any one of claims 1-8, wherein the total number of routers is 2N2+6N+5, where N> 0 is an integer, or 2N2+ 2N + 4, where N > 1 is an integer.

9. The spiking neural network device according to any one of the preceding claims, wherein the number of interior routers and first type perimeter routers is maximized.

10. The spiking neural network device according to any one of the preceding claims, wherein each of the spike packets, which are generated by the cores, comprises a plurality of indexes, which indexes are related to the validity, the destination, and the routing direction of the spike packet.11 . The spiking neural network device according to any one of the preceding claims, wherein each of the plurality of cores comprises a sparse synapse address generator, configured to skip the processing of non-firing inputs.

12. The spiking neural network device according to any one of the preceding claims, wherein each router comprises a communication system, controlling the communication between said router and its neighbouring routers, neighbouring routers being defined as routers, which are connected to each other through a transmission path.

13. The spiking neural network device according to claim 12, wherein the communication system allows each router to receive or request communication signals from a neighbouring router, or to send communication signals to a neighbouring router.

14. The spiking neural network device according to claim 13, wherein one of the communication signals is a status flag message, informing the neighbouring routers whether the transmission is permitted.

15. The spiking neural network device according to any one of the preceding claims, wherein each router comprises a stack register for storing one or morespike packets.

16. The spiking neural network device according to any one of the preceding claims, wherein each core emulates a plurality of neurons and a plurality of input axons connected with synaptic weights.

17. The spiking neural network device according to any one of the preceding claims, further comprising a training algorithm.

18. A method for designing a grid representing the topology of a spiking neural network according to any one of the preceding claims, the method comprising the steps of:• obtaining a plurality of cores, wherein each of the cores is assigned to a router,• arranging a plurality of routers in a plurality of rows and a plurality of columns,• arranging the number of routers in each row by increasing gradually the number of routers by one or two routers between neighbouring rows from a minimum row length in the outermost rows in the grid, to a maximum row length in one or more central rows in the grid, and• arranging the number of routers in each column by increasing gradually the number of routers by one or two routers between neighbouring columns from a minimum column height in the two outermost columns in the grid, to a maximum column height in one or more central columns in the grid.

19. An integrated circuit (IC) comprising a spiking neural network device according to any one of the claims 1 -17.

20. A system comprising a plurality of spiking neural network devices, the spiking neural networks devices arranged in a one-dimensional or a two-dimensional array.21 . The system according to claim 20, wherein the system is configured to perform intradevice routing.

22. The system according to any one of the claims 20-21 , wherein the system is configured to perform interdevice routing.

23. The system according to claim 22, wherein interdevice routing is performed by transmitting a spike packet from a corner router of a first spiking neural network device to a corner router of a second spiking neural network device.

24. The system according to claim 23, wherein a corner router is configured to transmit a spike packet originating from a topologically adjacent spiking neural network device towards one of its first type perimeter routers.

25. The system according to any one of the claims 20-24, wherein the spiking neural network devices are configured according to any one of the claims 1-17.

26. The system according to any one of claims 20-25, wherein the system is programmed to enable communication between the plurality of spiking neural network devices in the system.

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