Display device

Abstract

A display device is provided. The display device includes: a light-emitting element disposed on a substrate; a first transistor which controls a driving current supplied to the light-emitting element; a second transistor which supplies a data voltage to a source electrode of the first transistor; and a third transistor which electrically connects a drain electrode of the first transistor to a gate electrode of the first transistor, wherein the second transistor includes: a semiconductor region of a first active layer on the substrate; and a gate electrode disposed on a first gate layer on the first active layer, and the first transistor includes: a semiconductor region of a second active layer on the first gate layer, a gate electrode disposed on a second gate layer on the second active layer; and a bias electrode of the first active layer.

Description

display device

[0001] The present invention relates to a display device.

[0002] As the information society develops, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices such as smartphones, digital cameras, laptop computers, navigation devices, and smart televisions. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and organic light emitting displays (OLEDs). Among these flat panel displays, light emitting displays (LEDs) include light emitting elements in each pixel of the display panel that can emit light on their own, enabling images to be displayed without a backlight unit that provides light to the display panel.

[0003] The problem to be solved by the present invention is to provide a display device capable of reducing the number of contact holes in a pixel circuit and easily designing high-resolution pixels.

[0004] The tasks of the present invention are not limited to the tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] A display device of one embodiment for solving the above problem includes a light-emitting element disposed on a substrate, a first transistor for controlling a driving current supplied to the light-emitting element, a second transistor for supplying a data voltage to a source electrode of the first transistor, and a third transistor for electrically connecting a drain electrode of the first transistor and a gate electrode of the first transistor, wherein the second transistor includes a semiconductor region of a first active layer on the substrate and a gate electrode disposed on a first gate layer on the first active layer, and the first transistor includes a semiconductor region of a second active layer on the first gate layer, a gate electrode disposed on a second gate layer on the second active layer, and a bias electrode disposed on the first active layer.

[0006] The bias electrode of the first transistor is electrically connected to the source electrode of the first transistor and may overlap with the semiconductor region and the gate electrode of the first transistor.

[0007] The first active layer may include a silicon-based semiconductor region, and the second active layer may include an oxide-based semiconductor region.

[0008] The display device may further include a capacitor connected between the gate electrode of the first transistor and the first electrode of the light-emitting element, and a fourth transistor electrically connecting an initialization voltage line supplying an initialization voltage and the first electrode of the light-emitting element.

[0009] The display device may further include a fifth transistor electrically connecting a driving voltage line supplying a driving voltage and a drain electrode of the first transistor, and a sixth transistor electrically connecting a source electrode of the first transistor and a first electrode of the light-emitting element.

[0010] The bias electrode of the first transistor can be electrically connected to the source electrode of the sixth transistor.

[0011] A display device of one embodiment for solving the above problem includes a light-emitting element arranged on a substrate, a first transistor for controlling a driving current supplied to the light-emitting element, a second transistor for supplying a data voltage to a source electrode of the first transistor, a third transistor for electrically connecting a drain electrode of the first transistor and a gate electrode of the first transistor, and a capacitor connected between the gate electrode of the first transistor and the first electrode of the light-emitting element, wherein the first transistor includes a semiconductor region including an oxide, an N-type doped drain electrode and source electrode, and a P-type doped bias electrode.

[0012] The bias electrode of the first transistor may be arranged on the same layer as the semiconductor region of the second transistor.

[0013] The second transistor may include a P-type doped source electrode and drain electrode, and the third transistor may include an N-type doped drain electrode and source electrode.

[0014] The bias electrode of the first transistor is electrically connected to the source electrode of the first transistor and may overlap with the semiconductor region and the gate electrode of the first transistor.

[0015] The display device may further include an initialization voltage line supplying an initialization voltage and a fourth transistor electrically connecting the first electrode of the light-emitting element.

[0016] The display device may further include a fifth transistor electrically connecting a driving voltage line supplying a driving voltage and a drain electrode of the first transistor, and a sixth transistor electrically connecting a source electrode of the first transistor and a first electrode of the light-emitting element.

[0017] The fourth transistor may include an N-type doped drain electrode and source electrode, and the fifth and sixth transistors may include a P-type doped source electrode and drain electrode.

[0018] In one embodiment of a display device for solving the above problem, the display device includes a first active layer disposed on a substrate and including a silicon-based semiconductor region, a first gate layer disposed on the first active layer, a second active layer disposed on the first gate layer and including an oxide-based semiconductor region, a second gate layer disposed on the second active layer, a semiconductor region of the second active layer, a gate electrode disposed on the second gate layer, and a bias electrode disposed on the first active layer, a first transistor including a semiconductor region of the first active layer and supplying a data voltage to a source electrode of the first transistor, and a third transistor including a semiconductor region of the second active layer and electrically connecting a drain electrode of the first transistor and a gate electrode of the first transistor.

[0019] The display device may further include a capacitor including a third gate layer disposed on the second gate layer, a first capacitor electrode disposed on the second gate layer and including a gate electrode of the first transistor, and a second capacitor electrode disposed on the third gate layer.

[0020] The display device may further include a first source metal layer disposed on the third gate layer, a second source metal layer disposed on the first source metal layer, a first connection electrode disposed on the first source metal layer and connected to a source electrode of the second transistor, and a data line disposed on the second source metal layer and supplying a data voltage to the first connection electrode.

[0021] The display device may further include a second connection electrode disposed on the first source metal layer and electrically connecting the source electrode of the first transistor, the bias electrode of the first transistor, and the drain electrode of the second transistor.

[0022] The display device may further include a third connection electrode disposed on the first source metal layer and electrically connecting the gate electrode of the first transistor and the source electrode of the third transistor.

[0023] The display device may further include a light emitting element disposed on the second source metal layer, a driving voltage line disposed on the first source metal layer and supplying a driving voltage, an initialization voltage line disposed on the third gate layer and supplying an initialization voltage, a fourth transistor including a semiconductor region of the second active layer and electrically connecting the initialization voltage line and the first electrode of the light emitting element, a fifth transistor including a semiconductor region of the first active layer and electrically connecting the driving voltage line and the drain electrode of the first transistor, and a sixth transistor including a semiconductor region of the first active layer and electrically connecting the source electrode of the first transistor and the first electrode of the light emitting element.

[0024] The display device may further include a fourth connection electrode disposed on the first source metal layer and electrically connecting the drain electrode of the first transistor, the drain electrode of the third transistor, and the drain electrode of the fifth transistor, and a fifth connection electrode disposed on the first source metal layer and electrically connecting the initialization voltage line and the source electrode of the fourth transistor.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] According to the display device according to the embodiments, since the first transistor includes a bias electrode disposed in the first active layer and a semiconductor region of the second active layer, the number of contact holes of the pixel circuit can be reduced, and high-resolution pixels can be easily designed.

[0027] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0028] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0029] Fig. 2 is a cross-sectional view showing a display device according to one embodiment.

[0030] Fig. 3 is a plan view showing a display unit of a display device according to one embodiment.

[0031] FIG. 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0032] FIG. 5 is an equivalent circuit diagram showing a pixel of a display device according to one embodiment.

[0033] Figure 6 is a waveform diagram of signals supplied to the pixels illustrated in Figure 5.

[0034] Figure 7 is a layout diagram showing the pixels illustrated in Figure 5.

[0035] Figure 8 is a drawing showing some layers of the layout diagram of Figure 7.

[0036] Figure 9 is a drawing showing another part of the layout diagram of Figure 7.

[0037] Figure 10 is a drawing showing another part of the layout diagram of Figure 7.

[0038] Fig. 11 is a cross-sectional view taken along line I-I' of Fig. 7.

[0039] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0040] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer or intervening therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0041] Although terms like "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are used merely to distinguish one component from another. Therefore, it should be understood that a "first" component referred to below may also be a "second" component within the technical scope of the present invention.

[0042] The features of each of the various embodiments of the present invention can be partially or wholly combined or combined with each other, and various technical connections and operations are possible, and each embodiment can be implemented independently of each other or implemented together in a related relationship.

[0043] Specific embodiments are described below with reference to the attached drawings.

[0044] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0045] Referring to FIG. 1, the display device (10) can be applied to portable electronic devices such as a mobile phone, a smart phone, a tablet personal computer (PC), a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation device, an ultra mobile PC (UMPC), etc. For example, the display device (10) can be applied as a display unit of a television, a laptop, a monitor, a billboard, or the Internet of Things (IOT). As another example, the display device (10) can be applied to a wearable device such as a smart watch, a watch phone, a glasses-type display, and a head mounted display (HMD).

[0046] The display device (10) may be formed in a planar shape similar to a rectangle. For example, the display device (10) may have a planar shape similar to a rectangle having a short side in the X-axis direction and a long side in the Y-axis direction. The corner where the short side in the X-axis direction and the long side in the Y-axis direction meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The planar shape of the display device (10) is not limited to a rectangle, and may be formed similarly to other polygons, circles, or ovals.

[0047] The display device (10) may include a display panel (100), a display driver (200), a circuit board (300), and a touch driver (400).

[0048] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0049] The main area (MA) may include a display area (DA) having pixels for displaying an image, and a non-display area (NDA) arranged around the display area (DA). The display area (DA) may emit light from a plurality of light-emitting areas or a plurality of aperture areas. For example, the display panel (100) may include a pixel circuit including switching elements, a pixel definition film defining a light-emitting area or an aperture area, and a self-light emitting element.

[0050] For example, the self-luminous element may include, but is not limited to, at least one of an organic light emitting diode (OLED) including an organic light emitting layer, a quantum dot LED including a quantum dot light emitting layer, an inorganic LED including an inorganic semiconductor, and a micro LED.

[0051] The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be defined as an edge area of ​​the main area (MA) of the display panel (100). The non-display area (NDA) may include a scan driver (not shown) that supplies scan signals to scan lines, and fan-out lines (not shown) that connect the display driver (200) and the display area (DA).

[0052] The sub-area (SBA) may extend from one side of the main area (MA). The sub-area (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-area (SBA) is bent, the sub-area (SBA) may overlap the main area (MA) in the thickness direction (Z-axis direction). The sub-area (SBA) may include a display driver (200) and a pad portion connected to a circuit board (300). Optionally, the sub-area (SBA) may be omitted, and the display driver (200) and the pad portion may be arranged in a non-display area (NDA).

[0053] The display driver (200) can output signals and voltages for driving the display panel (100). The display driver (200) can supply data voltages to data lines. The display driver (200) can supply power voltage to a power line and supply scan control signals to the scan driver. The display driver (200) can be formed as an integrated circuit (IC) and mounted on the display panel (100) using a COG (Chip on Glass) method, a COP (Chip on Plastic) method, or an ultrasonic bonding method. For example, the display driver (200) can be placed in the sub-area (SBA) and can overlap the main area (MA) in the thickness direction (Z-axis direction) by bending the sub-area (SBA). As another example, the display driver (200) can be mounted on a circuit board (300).

[0054] The circuit board (300) may be attached to the pad portion of the display panel (100) using an anisotropic conductive film (ACF). Lead lines of the circuit board (300) may be electrically connected to the pad portion of the display panel (100). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip on film.

[0055] The touch driver (400) may be mounted on the circuit board (300). The touch driver (400) may be electrically connected to the touch sensing unit of the display panel (100). The touch driver (400) may supply a touch driving signal to a plurality of touch electrodes of the touch sensing unit and sense a change in electrostatic capacity between the plurality of touch electrodes. For example, the touch driving signal may be a pulse signal having a predetermined frequency. The touch driver (400) may calculate whether an input has occurred and the input coordinates based on the change in electrostatic capacity between the plurality of touch electrodes. The touch driver (400) may be formed as an integrated circuit (IC).

[0056] Fig. 2 is a cross-sectional view showing a display device according to one embodiment.

[0057] Referring to FIG. 2, the display panel (100) may include a display unit (DU), a touch sensing unit (TSU), and a color filter layer (CFL). The display unit (DU) may include a substrate (SUB), a transistor layer (TFTL), an light-emitting element layer (EDL), and an encapsulation layer (TFEL).

[0058] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In another example, the substrate (SUB) may include a glass material or a metal material.

[0059] A transistor layer (TFTL) may be disposed on a substrate (SUB). The transistor layer (TFTL) may include a plurality of transistors constituting a pixel circuit of pixels. The transistor layer (TFTL) may further include scan lines, data lines, power lines, scan control lines, fan-out lines connecting the display driver (200) and the data lines, and lead lines connecting the display driver (200) and the pad portion. Each of the transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. For example, when the scan driver is formed in the non-display area (NDA) of the display panel (100), the scan driver may include transistors.

[0060] The transistor layer (TFTL) may be arranged in a display area (DA), a non-display area (NDA), and a sub-area (SBA). The transistors, scan lines, data lines, and power lines of each pixel of the transistor layer (TFTL) may be arranged in the display area (DA). The scan control lines and fan-out lines of the transistor layer (TFTL) may be arranged in the non-display area (NDA). The lead lines of the transistor layer (TFTL) may be arranged in the sub-area (SBA).

[0061] An light-emitting device layer (EDL) may be disposed on a transistor layer (TFTL). The light-emitting device layer (EDL) may include a plurality of light-emitting devices that emit light, in which a first electrode, a light-emitting layer, and a second electrode are sequentially laminated, and a pixel definition film that defines pixels. The plurality of light-emitting devices of the light-emitting device layer (EDL) may be disposed in a display area (DA).

[0062] For example, the light-emitting layer may be an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transporting layer, an organic light-emitting layer, and an electron transporting layer. When the first electrode receives a predetermined voltage through a transistor of the transistor layer (TFTL) and the second electrode receives a cathode voltage, holes may move to the organic light-emitting layer through the hole transporting layer and electrons may move to the organic light-emitting layer through the electron transporting layer, and the holes and electrons may combine with each other in the organic light-emitting layer to emit light. For example, the first electrode may be an anode electrode or a pixel electrode, and the second electrode may be a cathode electrode or a common electrode, but is not limited thereto.

[0063] For another example, the plurality of light-emitting elements may include quantum dot light-emitting diodes including quantum dot light-emitting layers, inorganic light-emitting diodes including inorganic semiconductors, or micro-light-emitting diodes.

[0064] The encapsulation layer (TFEL) can cover the top and side surfaces of the light-emitting device layer (EDL) and protect the light-emitting device layer (EDL). The encapsulation layer (TFEL) can include at least one inorganic film and at least one organic film for encapsulating the light-emitting device layer (EDL).

[0065] A touch sensing unit (TSU) may be disposed on an encapsulation layer (TFEL). The touch sensing unit (TSU) may include a plurality of touch electrodes for detecting a user's touch in a capacitive manner, and touch lines connecting the plurality of touch electrodes and a touch driver (400). For example, the touch sensing unit (TSU) may sense a user's touch in a mutual capacitance manner or a self-capacitance manner. The plurality of touch electrodes of the touch sensing unit (TSU) may be disposed in a touch sensor area overlapping a display area (DA). The touch lines of the touch sensing unit (TSU) may be disposed in a touch peripheral area overlapping a non-display area (NDA).

[0066] For another example, the touch sensing unit (TSU) may be placed on a separate substrate placed on the display unit (DU). In this case, the substrate supporting the touch sensing unit (TSU) may be a base member encapsulating the display unit (DU).

[0067] A color filter layer (CFL) may be disposed on the touch sensing unit (TSU). The color filter layer (CFL) may include a plurality of color filters corresponding to each of a plurality of light-emitting regions. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of a different wavelength. The color filter layer (CFL) may absorb a portion of light entering from the outside of the display device (10) to reduce light reflected by external light. Therefore, the color filter layer (CFL) may prevent color distortion due to reflection of external light.

[0068] Since the color filter layer (CFL) is directly disposed on the touch sensing unit (TSU), the display device (10) may not require a separate substrate for the color filter layer (CFL). Accordingly, the thickness of the display device (10) can be relatively reduced.

[0069] The sub-area (SBA) of the display panel (100) may extend from one side of the main area (MA). The sub-area (SBA) may include a flexible material capable of bending, folding, rolling, etc. For example, when the sub-area (SBA) is bent, the sub-area (SBA) may overlap the main area (MA) in the thickness direction (Z-axis direction). The sub-area (SBA) may include a pad portion electrically connected to the display driver (200) and the circuit board (300).

[0070] Fig. 3 is a plan view showing a display unit of a display device according to one embodiment.

[0071] Referring to FIG. 3, the display unit (DU) may include a display area (DA) and a non-display area (NDA).

[0072] The display area (DA) is an area where an image is displayed, and may be defined as the central area of ​​the display panel (100). The display area (DA) may include a plurality of pixels (SP), a plurality of scan lines (SL), a plurality of data lines (DL), and a plurality of power lines (VL). Each of the plurality of pixels (SP) may be defined as the smallest unit that outputs light.

[0073] A plurality of scan lines (SL) can supply scan signals received from a scan driver (500) to a plurality of pixels (SP). The plurality of scan lines (SL) can extend in the X-axis direction and can be spaced apart from each other in the Y-axis direction intersecting (or perpendicular to) the X-axis direction.

[0074] A plurality of data lines (DL) can supply data voltages received from a display driver (200) to a plurality of pixels (SP). The plurality of data lines (DL) can extend in the Y-axis direction and be spaced apart from each other in the X-axis direction.

[0075] A plurality of power lines (VL) can supply a power voltage received from a display pad portion (DP) to a plurality of pixels (SP). Here, the power voltage can be at least one of a driving voltage, a high-potential voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-potential voltage. The plurality of power lines (VL) can extend in the Y-axis direction and can be spaced apart from each other in the X-axis direction.

[0076] A non-display area (NDA) may surround a display area (DA). The non-display area (NDA) may include a scan driver (500), fan-out lines (FOL), and scan control lines (SCL). The scan driver (500) may generate a plurality of scan signals based on a scan control signal, and may sequentially supply the plurality of scan signals to a plurality of scan lines (SL) in a set order.

[0077] Fan out lines (FOL) can extend from the display driver (200) to the display area (DA). The fan out lines (FOL) can supply data voltages received from the display driver (200) to a plurality of data lines (DL).

[0078] A scan control line (SCL) can extend from the display pad unit (DP) to the scan driver unit (500). The scan control line (SCL) can supply a scan control signal received from the display pad unit (DP) to the scan driver unit (500).

[0079] The sub-area (SBA) may include a display driver (200), a display pad area (DPA), and first and second touch pad areas (TPA1, TPA2).

[0080] The display driver (200) can output signals and voltages for driving the display panel (100) to the fan out lines (FOL). The display driver (200) can supply data voltages to the data lines (DL) through the fan out lines (FOL). The data voltages can be supplied to a plurality of pixels (SP) and can determine the brightness of the plurality of pixels (SP).

[0081] The display pad area (DPA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be arranged at the edge of the sub area (SBA). The display pad area (DPA), the first touch pad area (TPA1), and the second touch pad area (TPA2) may be electrically connected to the circuit board (300) using a low-resistance, high-reliability material such as an anisotropic conductive film or a self-assembly anisotropic conductive paste (SAP).

[0082] The display pad area (DPA) may include a plurality of display pad units (DP). The plurality of display pad units (DP) may be electrically connected to a graphic system via a circuit board (300). The plurality of display pad units (DP) may be connected to the circuit board (300) to receive digital video data and supply the digital video data to the display driver (200). The plurality of display pad units (DP) may supply a scan control signal to the scan driver (500) via a scan control line (SCL).

[0083] The first touch pad area (TPA1) may be arranged on one side of the display pad area (DPA) and may include a plurality of first touch pad portions (TP1). The plurality of first touch pad portions (TP1) may be electrically connected to a touch driver (400) arranged on a circuit board (300). The plurality of first touch pad portions (TP1) may supply touch drive signals to a plurality of drive electrodes through a plurality of drive lines.

[0084] The second touch pad area (TPA2) may be arranged on the other side of the display pad area (DPA) and may include a plurality of second touch pad portions (TP2). The plurality of second touch pad portions (TP2) may be electrically connected to a touch driver (400) arranged on a circuit board (300). The touch driver (400) may receive a touch sensing signal through a plurality of sensing lines connected to the plurality of second touch pad portions (TP2) and may sense a change in mutual electrostatic capacitance between the driving electrode and the sensing electrode.

[0085] FIG. 4 is a block diagram showing a display panel and a display driver according to one embodiment.

[0086] Referring to FIG. 4, the display panel (100) may include a display area (DA) and a non-display area (NDA).

[0087] The display area (DA) may include a plurality of pixels (SP), a plurality of power lines (VL) connected to the plurality of pixels (SP), a plurality of gate lines (GL), a plurality of emission control lines (EML), and a plurality of data lines (DL).

[0088] Each of the plurality of pixels (SP) may be connected to a gate line (GL), a data line (DL), a light emission control line (EML), and a power line (VL). Each of the plurality of pixels (SP) may include a plurality of transistors, light emitting elements, and capacitors.

[0089] The gate lines (GL) can extend in the X-axis direction and be spaced apart from each other in the Y-axis direction intersecting (or perpendicular to) the X-axis direction. The gate lines (GL) can sequentially supply gate signals to a plurality of pixels (SP).

[0090] The emission control lines (EML) can extend in the X-axis direction and be spaced apart from each other in the Y-axis direction. The emission control lines (EML) can sequentially supply emission signals to a plurality of pixels (SP).

[0091] The data lines (DL) can extend in the Y-axis direction and be spaced apart from each other in the X-axis direction. The data lines (DL) can supply data voltages to a plurality of pixels (SP). The data voltages can determine the brightness of each of the plurality of pixels (SP).

[0092] The power lines (VL) can extend in the Y-axis direction and be spaced apart from each other in the X-axis direction. The power lines (VL) can supply a power voltage to a plurality of pixels (SP). The power voltage can be at least one of a driving voltage, a high-potential voltage, an initialization voltage, a reference voltage, a bias voltage, and a low-potential voltage.

[0093] The timing control unit (210) can receive digital video data (DATA) and timing signals from the circuit board (300). The timing control unit (210) can generate a data control signal (DCS) based on the timing signals. The timing control unit (210) can control the operation timing of the display driver (200) by supplying the digital video data (DATA) and the data control signal (DCS) to the display driver (200). The display driver (200) can convert the digital video data (DATA) into analog data voltages and supply them to the data lines (DL). The timing control unit (210) can generate a gate control signal (GCS) based on the timing signals. The timing control unit (210) can control the operation timing of the gate driver (510) by supplying the gate control signal (GCS) to the gate driver (510). The timing control unit (210) can generate an emission control signal (ECS) based on the timing signals. The timing control unit (210) can control the operation timing of the light emitting control driving unit (520) by supplying a light emitting control signal (ECS) to the light emitting control driving unit (520).

[0094] The gate driver (510) and the light emission control driver (520) may be positioned on the left or right side of the non-display area (NDA). For example, the gate driver (510) and the light emission control driver (520) may be positioned on the left and right sides of the non-display area (NDA), but the present invention is not limited thereto. For another example, the gate driver (510) may be positioned on the left side of the non-display area (NDA), and the light emission control driver (520) may be positioned on the right side of the non-display area (NDA).

[0095] The gate driver (510) may include a plurality of transistors and generate gate signals based on a gate control signal (GCS). The gate signals of the gate driver (510) may select pixels (SP) to which a data voltage is supplied, and the selected pixels (SP) may receive the data voltage through data lines (DL). The light emission control driver (520) may include a plurality of transistors and generate light emission signals based on a light emission control signal (ECS). For example, the transistors of the gate driver (510) and the transistors of the light emission control driver (520) may be formed on the same layer as the transistors of each of the pixels (SP). The gate driver (510) may supply gate signals to the gate lines (GL), and the light emission control driver (520) may supply light emission signals to the light emission control lines (EML).

[0096] The power supply unit (600) can supply power voltage to the display driving unit (200) and the display panel (100). The power supply unit (600) can generate a driving voltage and supply it to a driving voltage line, generate an initialization voltage and supply it to an initialization voltage line, generate a bias voltage and supply it to a bias voltage line, and generate a low-potential voltage and supply it to a low-potential line.

[0097] FIG. 5 is an equivalent circuit diagram showing a pixel of a display device according to one embodiment, and FIG. 6 is a waveform diagram of signals supplied to the pixel shown in FIG. 5.

[0098] Referring to FIGS. 5 and 6, a pixel (SP) can be connected to a first gate line (GWL), a second gate line (GCL), a first emission control line (EML1), a second emission control line (EML2), a data line (DL), a driving voltage line (VDL), an initialization voltage line (VIL), and a low potential line (VSL).

[0099] A pixel (SP) may include a light-emitting element (ED) and a pixel circuit that drives the light-emitting element (ED). The pixel circuit may include first to sixth transistors (T1, T2, T3, T4, T5, T6) and a capacitor (C1).

[0100] A first transistor (T1) can control a driving current supplied to a light emitting element (ED). The first transistor (T1) can include a gate electrode, a drain electrode, and a source electrode. The gate electrode of the first transistor (T1) can be connected to a first node (N1), the drain electrode can be connected to a third node (N3), and the source electrode can be connected to a second node (N2). The first transistor (T1) can control a drain-source current (Ids, hereinafter referred to as “driving current”) according to a data voltage applied to the gate electrode. The driving current (Ids) flowing through a channel of the first transistor (T1) can be proportional to the square of the difference between a voltage (Vgs) and a threshold voltage (Vth) between the gate electrode and the source electrode of the first transistor (T1) (Ids = k × (Vgs - Vth)2). Here, k is a proportional coefficient determined by the structure and physical characteristics of the first transistor (T1), Vgs is the drain-source voltage of the first transistor (T1), and Vth is the threshold voltage of the first transistor (T1).

[0101] The first transistor (T1) may include a bias electrode. The bias electrode of the first transistor (T1) is electrically connected to the source electrode of the first transistor (T1) through the second node (N2) and may overlap with a semiconductor region of the first transistor (T1). The bias electrode of the first transistor (T1) can stabilize the operating point of the first transistor (T1) and stably control the driving current (Ids).

[0102] A light-emitting element (ED) can receive a driving current (Ids) and emit light. The amount of light emitted or luminance of the light-emitting element (ED) can be proportional to the magnitude of the driving current (Ids). The light-emitting element (ED) can include a first electrode, a second electrode, and a light-emitting layer disposed between the first electrode and the second electrode. The first electrode of the light-emitting element (ED) can be connected to a fourth node (N4). The first electrode of the light-emitting element (ED) can be connected to a drain electrode of a fourth transistor (T4) and a drain electrode of a sixth transistor (T6) via the fourth node (N4). The second electrode of the light-emitting element (ED) can be connected to a low-potential line (VSL) to receive a low-potential voltage. For example, the first electrode of the light-emitting element (ED) can be an anode electrode or a pixel electrode, and the second electrode can be a cathode electrode or a common electrode, but is not limited thereto. A parasitic capacitance (Ceq) may be formed between the first electrode and the second electrode of the light emitting element (ED).

[0103] The second transistor (T2) can be turned on by the first gate signal (GW) of the first gate line (GWL) to electrically connect the data line (DL) and the second node (N2), which is the source electrode of the first transistor (T1). The second transistor (T2) can be turned on based on the first gate signal (GW), thereby supplying a data voltage to the second node (N2). The gate electrode of the second transistor (T2) can be connected to the first gate line (GWL), the source electrode can be connected to the data line (DL), and the drain electrode can be connected to the second node (N2).

[0104] The third transistor (T3) can be turned on by the second gate signal (GC) of the second gate line (GCL) to electrically connect the third node (N3), which is the drain electrode of the first transistor (T1), and the first node (N1), which is the gate electrode of the first transistor (T1). The gate electrode of the third transistor (T3) can be connected to the second gate line (GCL), the drain electrode can be connected to the third node (N3), and the source electrode can be connected to the first node (N1).

[0105] The fourth transistor (T4) can be turned on by the second gate signal (GC) of the second gate line (GCL) to electrically connect the fourth node (N4), which is the first electrode of the light-emitting element (ED), and the initialization voltage line (VIL). The fourth transistor (T4) can be turned on based on the second gate signal (GC) to discharge the first electrode of the light-emitting element (ED) to the initialization voltage. The gate electrode of the fourth transistor (T4) can be connected to the second gate line (GCL), the drain electrode can be connected to the fourth node (N4), and the source electrode can be connected to the initialization voltage line (VIL).

[0106] The fifth transistor (T5) can be turned on by the first emission signal (EM1) of the first emission control line (EML1) to electrically connect the driving voltage line (VDL) and the third node (N3), which is the drain electrode of the first transistor (T1). The gate electrode of the fifth transistor (T5) can be connected to the first emission control line (EML1), the source electrode can be connected to the driving voltage line (VDL), and the drain electrode can be connected to the third node (N3).

[0107] The sixth transistor (T6) can be turned on by the second emission signal (EM2) of the second emission control line (EML2) to electrically connect the second node (N2), which is the source electrode of the first transistor (T1), and the fourth node (N4), which is the first electrode of the light emitting element (ED). The gate electrode of the sixth transistor (T6) can be connected to the second emission control line (EML2), the source electrode can be connected to the second node (N2), and the drain electrode can be connected to the fourth node (N4).

[0108] When the fifth transistor (T5), the first transistor (T1), and the sixth transistor (T6) are all turned on, the driving current (Ids) can be supplied to the light emitting element (ED).

[0109] The first transistor (T1), the third transistor (T3), and the fourth transistor (T4) may include an oxide-based semiconductor region. For example, the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) may have a coplanar structure in which a gate electrode is disposed on an upper portion of the oxide-based semiconductor region. A transistor having a coplanar structure has excellent leakage current characteristics and can be driven at a low frequency, thereby reducing power consumption. Therefore, the display device (10) includes the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) having excellent leakage current characteristics, thereby preventing leakage current from flowing within a pixel and stably maintaining a voltage within the pixel.

[0110] The first transistor (T1), the third transistor (T3), and the fourth transistor (T4) may correspond to n-type transistors. The first transistor (T1), the third transistor (T3), and the fourth transistor (T4) may include an n-type doped drain electrode and a source electrode. For example, the first transistor (T1), the third transistor (T3), and the fourth transistor (T4) may output a current flowing into the drain electrode to the source electrode based on a gate high voltage applied to the gate electrode.

[0111] The second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may include a silicon-based semiconductor region. For example, the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may include a semiconductor region made of low-temperature polycrystalline silicon (LTPS). A semiconductor region made of low-temperature polycrystalline silicon may have high electron mobility and excellent turn-on characteristics. Therefore, the display device (10) may stably and efficiently drive a plurality of pixels (SP) by including the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) having excellent turn-on characteristics.

[0112] The second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may correspond to p-type transistors. The second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may include a p-type doped source electrode and a drain electrode. For example, the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6) may output a current flowing into the source electrode to the drain electrode based on a gate low voltage applied to the gate electrode.

[0113] The capacitor (C1) can be connected between the first node (N1), which is the gate electrode of the first transistor (T1), and the fourth node (N4), which is the first electrode of the light-emitting element (ED). For example, the first capacitor electrode of the capacitor (C1) is connected to the first node (N1), and the second capacitor electrode of the capacitor (C1) is connected to the fourth node (N4), thereby maintaining a potential difference between the gate electrode of the first transistor (T1) and the first electrode of the light-emitting element (ED).

[0114] When FIG. 6 is connected to FIG. 5, the display device (10) can be driven through the first to fourth periods (t1 to t4) of one frame. The pixel (SP) can receive a first gate signal (GW), a second gate signal (GC), a first emission signal (EM1), and a second emission signal (EM2).

[0115] The fifth transistor (T5) may receive a first emission signal (EM1) of a low level during a first period (t1), and the third transistor (T3) may receive a second gate signal (GC) of a high level during a second period (t2). The first half of the second period (t2) may include the first period (t1). For example, the timings of the first and second periods (t1, t2) may be the same, and the end point of the second period (t2) may be after the end point of the first period (t1), but is not limited thereto. Accordingly, the driving voltage may be supplied to the first node (N1), which is the gate electrode of the first transistor (T1), so that the voltage of the first node (N1) may be initialized during the first period (t1).

[0116] The fourth transistor (T4) can receive a high-level second gate signal (GC) during the second period (t2). Accordingly, the initialization voltage is supplied to the fourth node (N4), which is the first electrode of the light-emitting element (ED), so that the fourth node (N4) can be discharged to the initialization voltage during the second period (t2).

[0117] The second transistor (T2) can receive a low-level first gate signal (GW) during a third period (t3). Accordingly, the second transistor (T2) can supply a data voltage during the third period (t3) to the second node (N2), which is the source electrode of the first transistor (T1). The second period (t2) may include a third period (t3). For example, the point in time of the third period (t3) may be after the end point of the first period (t1) and before the end point of the second period (t2), but is not limited thereto. When the source electrode of the first transistor (T1) receives the data voltage, the gate-source voltage (Vgs) of the first transistor (T1) becomes greater than the threshold voltage (Vth), so that the first transistor (T1) can be turned on. The first transistor (T1) can be turned on until the gate-source voltage (Vgs) reaches the threshold voltage (Vth) of the first transistor (T1). Accordingly, the data voltage and the threshold voltage (Vth) can be sampled at the gate electrode of the first transistor (T1).

[0118] The fifth transistor (T5) can receive the first light-emitting signal (EM1) at a low level during a fourth period (t4) following the second and third periods (t2, t3), and the sixth transistor (T6) can receive the second light-emitting signal (EM2) at a low level during the fourth period (t4). Accordingly, the fifth and sixth transistors (T5, T6) can be turned on, and the driving current (Ids) can be supplied to the light-emitting element (ED).

[0119] Fig. 7 is a layout diagram showing the pixel illustrated in Fig. 5. Fig. 8 is a diagram showing some layers of the layout diagram of Fig. 7, showing a stacked structure of a first active layer (ACTL1) and a first gate layer (GTL1). Fig. 9 is a diagram showing other layers of the layout diagram of Fig. 7, showing a stacked structure of a second active layer (ACTL2), a second gate layer (GTL2), and a third gate layer (GTL3). Fig. 10 is a diagram showing still other layers of the layout diagram of Fig. 7, showing a stacked structure of a first source metal layer (SDL1) and a second source metal layer (SDL2). Fig. 11 is a cross-sectional view taken along line II' of Fig. 7.

[0120] Referring to FIGS. 7 to 11, a pixel (SP) can be connected to a first gate line (GWL), a second gate line (GCL), a first emission control line (EML1), a second emission control line (EML2), a data line (DL), a driving voltage line (VDL), an initialization voltage line (VIL), and a low potential line (VSL).

[0121] A first transistor (T1) may include a semiconductor region (ACT1), a gate electrode (GE1), a drain electrode (DE1), a source electrode (SE1), and a bias electrode (BE1). The bias electrode (BE1) of the first transistor (T1) may be disposed in a first active layer (ACTL1), the semiconductor region (ACT1), the drain electrode (DE1), and the source electrode (SE1) of the first transistor (T1) may be disposed in a second active layer (ACTL2), and the gate electrode (GE1) of the first transistor (T1) may be disposed in a second gate layer (GTL2). The gate electrode (GE1) of the first transistor (T1) may be a portion of a first capacitor electrode (CPE1) of the second gate layer (GTL2) and may overlap with the semiconductor region (ACT1) and the bias electrode (BE1) of the first transistor (T1). For example, the bias electrode (BE1) of the first transistor (T1) may be formed by conducting low-temperature polycrystalline silicon (LTPS), and the semiconductor region (ACT1) of the first transistor (T1) may include an oxide. Accordingly, the bias electrode (BE1) of the first transistor (T1) may be formed by being P-type doped, and the drain electrode (DE1) and the source electrode (SE1) of the first transistor (T1) may be formed by being N-type doped. Since the first transistor (T1) includes the bias electrode (BE1) disposed in the first active layer (ACTL1), the display device (10) can reduce the number of contact holes of the pixel circuit and easily design high-resolution pixels.

[0122] The gate electrode (GE1) of the first transistor (T1) may be electrically connected to the source electrode (SE3) of the third transistor (T3) via the third connection electrode (CE3) of the first source metal layer (SDL1). The drain electrode (DE1) of the first transistor (T1) may be electrically connected to the drain electrode (DE3) of the third transistor (T3) and the drain electrode (DE5) of the fifth transistor (T5) via the fourth connection electrode (CE4) of the first source metal layer (SDL1). The source electrode (SE1) of the first transistor (T1) may be electrically connected to the bias electrode (BE1) of the first transistor (T1), the drain electrode (DE2) of the second transistor (T2), and the source electrode (SE6) of the sixth transistor (T6) via the second connection electrode (CE2) of the first source metal layer (SDL1).

[0123] The second transistor (T2) may include a semiconductor region (ACT2), a gate electrode (GE2), a source electrode (SE2), and a drain electrode (DE2). The semiconductor region (ACT2), the source electrode (SE2), and the drain electrode (DE2) of the second transistor (T2) may be disposed in a first active layer (ACTL1), and the gate electrode (GE2) of the second transistor (T2) may be disposed in a first gate layer (GTL1). The gate electrode (GE2) of the second transistor (T2) may be a portion of a first gate line (GWL) of the first gate layer (GTL1) and may overlap with the semiconductor region (ACT2) of the second transistor (T2). For example, the semiconductor region (ACT2) of the second transistor (T2) may include low-temperature polycrystalline silicon (LTPS).

[0124] The source electrode (SE2) of the second transistor (T2) may be electrically connected to the data line (DL) of the second source metal layer (SDL2) via the first connection electrode (CE1) of the first source metal layer (SDL1). The drain electrode (DE2) of the second transistor (T2) may be connected to the bias electrode (BE1) of the first transistor (T1) and the source electrode (SE6) of the sixth transistor (T6). The drain electrode (DE2) of the second transistor (T2) may be electrically connected to the source electrode (SE1) of the first transistor (T1) via the second connection electrode (CE2).

[0125] The third transistor (T3) may include a semiconductor region (ACT3), a gate electrode (GE3), a drain electrode (DE3), and a source electrode (SE3). The semiconductor region (ACT3), the drain electrode (DE3), and the source electrode (SE3) of the third transistor (T3) may be disposed in a second active layer (ACTL2), and the gate electrode (GE3) of the third transistor (T3) may be disposed in a second gate layer (GTL2). The gate electrode (GE3) of the third transistor (T3) may be a portion of a second gate line (GCL) of the second gate layer (GTL2) and may overlap with the semiconductor region (ACT3) of the third transistor (T3). For example, the semiconductor region (ACT3) of the third transistor (T3) may include an oxide.

[0126] The drain electrode (DE3) of the third transistor (T3) can be electrically connected to the drain electrode (DE1) of the first transistor (T1) and the drain electrode (DE5) of the fifth transistor (T5) via the fourth connection electrode (CE4). The source electrode (SE3) of the third transistor (T3) can be electrically connected to the gate electrode (GE1) of the first transistor (T1) via the third connection electrode (CE3).

[0127] The fourth transistor (T4) may include a semiconductor region (ACT4), a gate electrode (GE4), a drain electrode (DE4), and a source electrode (SE4). The semiconductor region (ACT4), the drain electrode (DE4), and the source electrode (SE4) of the fourth transistor (T4) may be disposed in a second active layer (ACTL2), and the gate electrode (GE4) of the fourth transistor (T4) may be disposed in a second gate layer (GTL2). The gate electrode (GE4) of the fourth transistor (T4) may be a portion of a second gate line (GCL) of the second gate layer (GTL2) and may overlap with the semiconductor region (ACT4) of the fourth transistor (T4). For example, the semiconductor region (ACT4) of the fourth transistor (T4) may include an oxide.

[0128] The drain electrode (DE4) of the fourth transistor (T4) may be electrically connected to the drain electrode (DE6) of the sixth transistor (T6) and the first electrode of the light-emitting element (ED) through the first anode connection electrode (ANE1) of the first source metal layer (SDL1). The source electrode (SE4) of the fourth transistor (T4) may be electrically connected to the initialization voltage line (VIL) of the third gate layer (GTL3) through the fifth connection electrode (CE5) of the first source metal layer (SDL1).

[0129] The fifth transistor (T5) may include a semiconductor region (ACT5), a gate electrode (GE5), a source electrode (SE5), and a drain electrode (DE5). The semiconductor region (ACT5), the source electrode (SE5), and the drain electrode (DE5) of the fifth transistor (T5) may be disposed in a first active layer (ACTL1), and the gate electrode (GE5) of the fifth transistor (T5) may be disposed in a first gate layer (GTL1). The gate electrode (GE5) of the fifth transistor (T5) may be a portion of a first emission control line (EML1) of the first gate layer (GTL1) and may overlap with the semiconductor region (ACT5) of the fifth transistor (T5). For example, the semiconductor region (ACT5) of the fifth transistor (T5) may include low-temperature polycrystalline silicon (LTPS).

[0130] The source electrode (SE5) of the fifth transistor (T5) may be electrically connected to a first portion (VDLa) and a second portion (VDLb) of the driving voltage line (VDL). The first portion (VDLa) of the driving voltage line (VDL) may be disposed on a second source metal layer (SDL2) and may extend in the Y-axis direction, and the second portion (VDLb) of the driving voltage line (VDL) may be disposed on a first source metal layer (SDL1) and may extend in the X-axis direction. The drain electrode (DE5) of the fifth transistor (T5) may be electrically connected to the drain electrode (DE1) of the first transistor (T1) and the drain electrode (DE3) of the third transistor (T3) via the fourth connection electrode (CE4).

[0131] The sixth transistor (T6) may include a semiconductor region (ACT6), a gate electrode (GE6), a source electrode (SE6), and a drain electrode (DE6). The semiconductor region (ACT6), the source electrode (SE6), and the drain electrode (DE6) of the sixth transistor (T6) may be disposed in a first active layer (ACTL1), and the gate electrode (GE6) of the sixth transistor (T6) may be disposed in a first gate layer (GTL1). The gate electrode (GE6) of the sixth transistor (T6) may be a portion of the second emission control line (EML2) and may overlap with the semiconductor region (ACT6) of the sixth transistor (T6). For example, the semiconductor region (ACT6) of the sixth transistor (T6) may include low-temperature polycrystalline silicon (LTPS).

[0132] The source electrode (SE6) of the sixth transistor (T6) may be connected to the bias electrode (BE1) of the first transistor (T1) and the drain electrode (DE2) of the second transistor (T2). The source electrode (SE6) of the sixth transistor (T6) may be electrically connected to the source electrode (SE1) of the first transistor (T1) via the second connection electrode (CE2). The drain electrode (DE6) of the sixth transistor (T6) may be electrically connected to the drain electrode (DE4) of the fourth transistor (T4) and the first electrode of the light emitting element (ED) via the first anode connection electrode (ANE1).

[0133] The capacitor (C1) may include a first capacitor electrode (CPE1) and a second capacitor electrode (CPE2). The first and second capacitor electrodes (CPE1, CPE2) may overlap each other. The first capacitor electrode (CPE1) of the capacitor (C1) may be disposed on a second gate layer (GTL2), and the second capacitor electrode (CPE2) may be disposed on a third gate layer (GTL3). The first capacitor electrode (CPE1) may include a gate electrode (GE1) of the first transistor (T1). The second capacitor electrode (CPE2) may be electrically connected to a drain electrode (DE4) of a fourth transistor (T4), a drain electrode (DE6) of a sixth transistor (T6), and a first electrode of a light-emitting element (ED) via a first anode connection electrode (ANE1).

[0134] In FIG. 11, the display panel (100) may include a substrate (SUB), a transistor layer (TFTL), a light-emitting element layer (EDL), and an encapsulation layer (TFEL).

[0135] The substrate (SUB) may be a base substrate or a base member. The substrate (SUB) may be a flexible substrate capable of bending, folding, rolling, etc. For example, the substrate (SUB) may include a polymer resin such as polyimide (PI), but is not limited thereto. In another example, the substrate (SUB) may include a glass material or a metal material.

[0136] The transistor layer (TFTL) may include a buffer layer (BF), a first active layer (ACTL1), a first gate insulating layer (GI1), a first gate layer (GTL1), a first interlayer insulating layer (ILD1), a second active layer (ACTL2), a second gate insulating layer (GI2), a second gate layer (GTL2), a second interlayer insulating layer (ILD2), a third gate layer (GTL3), a third interlayer insulating layer (ILD3), a first source metal layer (SDL1), a first via layer (VIA1), a second source metal layer (SDL2), and a second via layer (VIA2).

[0137] A buffer layer (BF) may be disposed on a substrate (SUB). For example, the buffer layer (BF) may include an inorganic film capable of preventing the penetration of air or moisture. For example, the buffer layer (BF) may include a plurality of inorganic films alternately laminated.

[0138] A first active layer (ACTL1) may be disposed on a buffer layer (BF). The first active layer (ACTL1) may include a silicon-based material. For example, the first active layer (ACTL1) may be made of low-temperature polycrystalline silicon (LTPS). The first active layer (ACTL1) may include semiconductor regions (ACT2, ACT5, ACT6), source electrodes (SE2, SE5, SE6), and drain electrodes (DE2, DE5, DE6) of the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6), respectively.

[0139] A first gate insulating layer (GI1) may be disposed on a first active layer (ACTL1). The first gate insulating layer (GI1) may insulate the first active layer (ACTL1) and the first gate layer (GTL1).

[0140] The first gate layer (GTL1) may be disposed on the first gate insulating layer (GI1). The first gate layer (GTL1) may include gate electrodes (GE2, GE5, GE6) of the second transistor (T2), the fifth transistor (T5), and the sixth transistor (T6), a first gate line (GWL), and first and second emission control lines (EML1, EML2), respectively.

[0141] A first interlayer insulating layer (ILD1) may be disposed on a first gate layer (GTL1). The first interlayer insulating layer (ILD1) may insulate the first gate layer (GTL1) and the second active layer (ACTL2).

[0142] The second active layer (ACTL2) may be disposed on the first interlayer insulating layer (ILD1). The second active layer (ACTL2) may include an oxide-based material. The second active layer (ACTL2) may include semiconductor regions (ACT1, ACT3, ACT4), drain electrodes (DE1, DE3, DE4), and source electrodes (SE1, SE3, SE4) of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4), respectively.

[0143] A second gate insulating layer (GI2) may be disposed on a second active layer (ACTL2). The second gate insulating layer (GI2) may insulate the second active layer (ACTL2) and the second gate layer (GTL2).

[0144] The second gate layer (GTL2) may be disposed on the second gate insulating layer (GI2). The second gate layer (GTL2) may include gate electrodes (GE1, GE3, GE4) of each of the first transistor (T1), the third transistor (T3), and the fourth transistor (T4), a second gate line (GCL), and a first capacitor electrode (CPE1).

[0145] A second interlayer insulating layer (ILD2) may be disposed on the second gate layer (GTL2). The second interlayer insulating layer (ILD2) may insulate the second gate layer (GTL2) and the third gate layer (GTL3).

[0146] The third gate layer (GTL3) may be disposed on the second interlayer insulating layer (ILD2). The third gate layer (GTL3) may include a second capacitor electrode (CPE2) and an initialization voltage line (VIL).

[0147] A third interlayer insulating layer (ILD3) may be disposed on the third gate layer (GTL3). The third interlayer insulating layer (ILD3) may insulate the third gate layer (GTL3) and the first source metal layer (SDL1).

[0148] A first source metal layer (SDL1) may be disposed on a third interlayer insulating layer (ILD3). The first source metal layer (SDL1) may include first to fifth connection electrodes (CE1, CE2, CE3, CE4, CE5), a first anode connection electrode (ANE1), and a second portion (VDLb) of a driving voltage line (VDL).

[0149] A first via layer (VIA1) may be disposed on a first source metal layer (SDL1). The first via layer (VIA1) may insulate the first source metal layer (SDL1) and the second source metal layer (SDL2).

[0150] A second source metal layer (SDL2) may be disposed on a first via layer (VIA1). The second source metal layer (SDL2) may include a data line (DL), a second anode connection electrode (ANE2), and a first portion (VDLa) of a driving voltage line (VDL).

[0151] A second via layer (VIA2) may be disposed on a second source metal layer (SDL2). The second via layer (VIA2) may insulate the second source metal layer (SDL2) from the first electrode (AE) of the light-emitting element (ED).

[0152] The light-emitting device layer (EDL) may include a pixel defining layer (PDL) and a light-emitting device (ED). The light-emitting device (ED) may include a first electrode (AE), an emitting layer (EL), and a second electrode (CAT).

[0153] A pixel defining layer (PDL) may be disposed on a planarization layer (OC). The pixel defining layer (PDL) may define a plurality of emission areas (EA). The pixel defining layer (PDL) may include an organic insulating material such as polyimide (PI).

[0154] A first electrode (AE) may be disposed on a second via layer (VIA2). The first electrode (AE) may overlap one of a plurality of light-emitting areas (EA) defined by a pixel defining layer (PDL). The first electrode (AE) may receive a driving current from a pixel circuit of a pixel (SP).

[0155] The light-emitting layer (EL) may be disposed on the first electrode (AE). For example, the light-emitting layer (EL) may be an organic light-emitting layer made of an organic material, but is not limited thereto. When the light-emitting layer (EL) corresponds to an organic light-emitting layer, when the pixel circuit of the pixel (SP) applies a predetermined voltage to the first electrode (AE) and the second electrode (CAT) receives a common voltage or a cathode voltage, holes may move to the organic light-emitting layer (EL) through the hole transport layer and electrons may move to the organic light-emitting layer (EL) through the electron transport layer, and the holes and electrons may combine with each other in the organic light-emitting layer (EL) to emit light.

[0156] The second electrode (CAT) may be disposed on the light-emitting layer (EL). For example, the second electrode (CAT) may be implemented in the form of an electrode common to all pixels (SP) without being differentiated for each pixel (SP). The second electrode (CAT) may be disposed on the light-emitting layer (EL) in a plurality of light-emitting regions, and may be disposed on the pixel defining layer (PDL) in an area excluding the plurality of light-emitting regions.

[0157] The encapsulation layer (TFEL) is disposed on the second electrode (CAT) and can cover a plurality of light-emitting elements (ED). The encapsulation layer (TFEL) can include at least one inorganic film to prevent oxygen or moisture from penetrating into the plurality of light-emitting elements (ED). The encapsulation layer (TFEL) can include at least one organic film to protect the plurality of light-emitting elements (ED) from foreign substances such as dust.

[0158] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. A light-emitting element arranged on a substrate; A first transistor that controls the driving current supplied to the light-emitting element; A second transistor that supplies a data voltage to the source electrode of the first transistor; and A third transistor is included that electrically connects the drain electrode of the first transistor and the gate electrode of the first transistor, The second transistor includes a semiconductor region of a first active layer on the substrate, and a gate electrode disposed on a first gate layer on the first active layer, A display device in which the first transistor includes a semiconductor region of a second active layer on the first gate layer, a gate electrode disposed on a second gate layer on the second active layer, and a bias electrode of the first active layer.

2. In paragraph 1, A display device in which the bias electrode of the first transistor is electrically connected to the source electrode of the first transistor and overlaps the semiconductor region and the gate electrode of the first transistor.

3. In paragraph 1, A display device wherein the first active layer includes a silicon-based semiconductor region, and the second active layer includes an oxide-based semiconductor region.

4. In paragraph 1, A capacitor electrically connected between the gate electrode of the first transistor and the first electrode of the light-emitting element; and A display device further comprising an initialization voltage line supplying an initialization voltage and a fourth transistor electrically connecting the first electrode of the light-emitting element.

5. In paragraph 4, A fifth transistor electrically connecting a driving voltage line supplying a driving voltage and a drain electrode of the first transistor; and A display device further comprising a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light-emitting element.

6. In paragraph 5, A display device in which the bias electrode of the first transistor is electrically connected to the source electrode of the sixth transistor.

7. A light-emitting element arranged on a substrate; A first transistor that controls the driving current supplied to the light-emitting element; A second transistor that supplies a data voltage to the source electrode of the first transistor; A third transistor electrically connecting the drain electrode of the first transistor and the gate electrode of the first transistor; and A capacitor connected between the gate electrode of the first transistor and the first electrode of the light-emitting element, A display device including a semiconductor region of a first active layer including an oxide, an N-type doped drain electrode and source electrode, and a P-type doped bias electrode, wherein the first transistor comprises:

8. In paragraph 7, A display device in which the bias electrode of the first transistor is disposed on the same layer as the semiconductor region of the second active layer of the second transistor.

9. In paragraph 7, A display device wherein the second transistor includes a P-type doped source electrode and a drain electrode, and the third transistor includes an N-type doped drain electrode and a source electrode.

10. In paragraph 7, A display device in which the bias electrode of the first transistor is electrically connected to the source electrode of the first transistor and overlaps the semiconductor region and the gate electrode of the first transistor.

11. In paragraph 7, A display device further comprising an initialization voltage line supplying an initialization voltage and a fourth transistor electrically connecting the first electrode of the light-emitting element.

12. In paragraph 11, A fifth transistor electrically connecting a driving voltage line supplying a driving voltage and a drain electrode of the first transistor; and A display device further comprising a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light-emitting element.

13. In paragraph 12, A display device wherein the fourth transistor includes an N-type doped drain electrode and source electrode, and the fifth and sixth transistors include a P-type doped source electrode and drain electrode.

14. A first active layer disposed on a substrate and including a silicon-based semiconductor region; A first gate layer disposed on the first active layer; A second active layer disposed on the first gate layer and including an oxide-based semiconductor region; A second gate layer disposed on the second active layer; A first transistor including a semiconductor region of the second active layer, a gate electrode disposed on the second gate layer, and a bias electrode of the first active layer; A second transistor including a semiconductor region of the first active layer and supplying a data voltage to the source electrode of the first transistor; and A display device including a semiconductor region of the second active layer and a third transistor electrically connecting a drain electrode of the first transistor and a gate electrode of the first transistor.

15. In paragraph 14, a third gate layer disposed on the second gate layer; and A display device further comprising a capacitor including a first capacitor electrode disposed on the second gate layer and including the gate electrode of the first transistor, and a second capacitor electrode disposed on the third gate layer.

16. In paragraph 15, A first source metal layer disposed on the third gate layer; A second source metal layer disposed on the first source metal layer; A first connection electrode disposed on the first source metal layer and connected to the source electrode of the second transistor; and A display device further comprising a data line disposed on the second source metal layer and supplying a data voltage to the first connection electrode.

17. In paragraph 16, A display device further comprising a second connection electrode disposed on the first source metal layer and electrically connecting the source electrode of the first transistor, the bias electrode of the first transistor, and the drain electrode of the second transistor.

18. In paragraph 16, A display device further comprising a third connection electrode disposed on the first source metal layer and electrically connecting the gate electrode of the first transistor and the source electrode of the third transistor.

19. In paragraph 16, A light emitting element disposed on the second source metal layer; A driving voltage line arranged on the first source metal layer and supplying a driving voltage; An initialization voltage line arranged on the third gate layer and supplying an initialization voltage; A fourth transistor including a semiconductor region of the second active layer and electrically connecting the initialization voltage line and the first electrode of the light-emitting element; A fifth transistor including a semiconductor region of the first active layer and electrically connecting the driving voltage line and the drain electrode of the first transistor; and A display device including a semiconductor region of the first active layer and further including a sixth transistor electrically connecting the source electrode of the first transistor and the first electrode of the light-emitting element.

20. In paragraph 19, A fourth connection electrode disposed on the first source metal layer and electrically connecting the drain electrode of the first transistor, the drain electrode of the third transistor, and the drain electrode of the fifth transistor; and A display device further comprising a fifth connection electrode disposed on the first source metal layer and electrically connecting the initialization voltage line and the source electrode of the fourth transistor.

Images