Memory device, memory system, memory controller, and operation method

Abstract

Disclosed in embodiments of the present application are a memory device, a memory system, a memory controller, and an operation method. The memory device comprises: a memory cell array comprising memory cells each having multiple storage bits, wherein a preset number of memory cells form a codeword, the multiple storage bits respectively correspond to multiple pages, at least one page corresponds to multiple levels, the multiple levels include first levels and second levels, and a read voltage corresponding to each second level is lower than that of the corresponding first level; and a peripheral circuit coupled to the memory cell array and configured to: acquire a target valley voltage of a first target level, wherein the first target level includes at least one first level among the multiple first levels corresponding to the multiple pages, and the target valley voltage is used as a read voltage when performing a read operation on at least one codeword; and acquire predicted valley voltages of second target levels on the basis of the target valley voltage of the first target level, wherein the second target levels include the remaining first levels and / or second levels, and a read voltage of each second target level is less than that of the first target level.

Description

Memory device, memory system, memory controller and operation method Technical Field

[0001] The present application relates to, but is not limited to, a memory device, a memory system, a memory controller, and an operating method. Background Art

[0002] With the advancement of technology, the integrated circuit industry has seen a growing market. Within this industry, the processes and technologies for non-volatile memory devices have seen rapid advancements in recent years, with NAND memory being particularly widely used. NAND memory achieves data storage by capturing and storing charge within the gate dielectric layer of its memory cells. However, over time, the charge stored in the memory cells changes due to factors such as age, repeated read operations, and cross-temperature fluctuations, thus affecting the accuracy of data read from the cells.

[0003] Summary of the Invention

[0004] In a first aspect, an embodiment of the present application provides a memory device, comprising: a memory cell array, comprising memory cells having a plurality of storage bits; a preset number of the memory cells forming a codeword, wherein the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, wherein the plurality of stages include a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; a peripheral circuit, coupled to the memory cell array and configured to: obtain a target valley voltage of a first target stage, wherein the first target stage includes at least one first stage among the plurality of first stages corresponding to the plurality of pages; the target valley voltage is used as a read voltage for at least one of the codewords when performing a read operation; and obtain a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage, wherein the second target stage includes the remaining first stages and / or second stages; and the read voltage of the second target stage is less than the read voltage of the first target stage.

[0005] In a second aspect, an embodiment of the present application provides a memory system, comprising: one or more memory devices described in any one of the first aspects; and a memory controller coupled to and controlling the memory device.

[0006] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, the memory device including a storage unit with a plurality of storage bits; a preset number of the storage units form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, the plurality of stages including a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the memory controller includes: a control unit configured to: obtain a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to a plurality of pages in the memory device; the target valley voltage is used as a read voltage for at least one of the codewords when performing a read operation; and obtain a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage; the second target stage includes the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0007] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, wherein the memory device includes a memory cell having a plurality of storage bits; a preset number of the memory cells form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, the plurality of stages include a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the operating method includes: obtaining a target valley voltage of a first target stage, the first target stage including at least one first stage among the plurality of first stages corresponding to the plurality of pages; the target valley voltage is used as a read voltage when performing a corresponding stage read operation; and obtaining a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage, the second target stage including the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0008] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: sending a data acquisition instruction, wherein the data acquisition instruction indicates obtaining a target valley voltage; the target valley voltage is obtained according to the operating method described in the fourth aspect; and performing a read operation on data stored in the memory device according to the target valley voltage.

[0009] In a sixth aspect, an embodiment of the present application provides an operating method of a memory controller, wherein the memory controller is coupled to at least one memory device, the memory device including a storage unit having a plurality of storage bits; a preset number of the storage units form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, the plurality of stages including a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the operating method includes: obtaining a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to a plurality of pages in the memory device; the target valley voltage is used as a read voltage when performing a read operation on at least one of the codewords; and obtaining a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage; the second target stage including the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0010] In the seventh aspect, an embodiment of the present application provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of any one of the operating methods provided in the fourth aspect, the fifth aspect, and the sixth aspect can be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar components or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0012] FIG1 is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0013] FIG2A is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0014] FIG2B is a schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0015] FIG3 is a schematic diagram of an exemplary memory including peripheral circuits according to an embodiment of the present application;

[0016] FIG4 is a cross-sectional schematic diagram of a memory cell array including a NAND memory string according to an embodiment of the present application;

[0017] FIG5 is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuits according to an embodiment of the present application;

[0018] FIG6 is a schematic diagram of an exemplary read operation flow of a memory system provided by the present application;

[0019] FIG7 is a schematic diagram illustrating a flowchart of an implementation of an operation method performed by a peripheral circuit of a memory device according to an embodiment of the present application;

[0020] FIG8A is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including two memory bits provided in one embodiment of the present application;

[0021] FIG8B is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including three memory bits provided in one embodiment of the present application;

[0022] FIG8C is a schematic diagram of a threshold voltage distribution corresponding to a memory cell including four memory bits provided in one embodiment of the present application;

[0023] FIG9 is a schematic diagram of a method for determining a target valley voltage of the second target step as shown in FIG8B , provided by an embodiment of the present application;

[0024] FIG10A is a schematic diagram of a method for confirming a predicted valley voltage of a second target step corresponding to the lower page shown in FIG8B according to an embodiment of the present application;

[0025] FIG10B is a schematic diagram of a method for confirming a predicted valley voltage of a second target step corresponding to the middle page shown in FIG8B according to an embodiment of the present application;

[0026] FIG10C is a schematic diagram of a method for confirming a predicted valley voltage of a second target step corresponding to the upper page shown in FIG8B according to an embodiment of the present application;

[0027] FIG10D is an enlarged schematic diagram of the rectangular dotted line area in FIG10A ;

[0028] FIG11 is a flowchart of a method for operating a memory device according to an embodiment of the present application;

[0029] FIG12 is a second flowchart of a method for operating a memory device according to an embodiment of the present application;

[0030] FIG13 is a schematic diagram of an exemplary structure of a memory system provided in one embodiment of the present application;

[0031] FIG14 is a block diagram of a memory system provided by an embodiment of the present application;

[0032] FIG15 is a flowchart of an operating method that a memory system is configured to perform according to an embodiment of the present application;

[0033] FIG16 is a timing diagram of an exemplary start-up single-level read mode operation provided by the present application;

[0034] FIG17 is a timing diagram of determining a target valley voltage and performing a read operation according to an embodiment of the present application;

[0035] FIG18 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0036] The exemplary embodiments disclosed herein will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the specific embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0037] In the following description, numerous specific details are provided to provide a more thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present application; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0038] In addition, the accompanying drawings are merely schematic illustrations of the present application and are not necessarily drawn to scale. Identical reference numerals in the figures denote identical or similar parts, and thus repetitive descriptions thereof will be omitted. Some of the blocks shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0039] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all steps. For example, some steps may be decomposed, while some steps may be combined or partially combined, so the actual execution order may change according to actual circumstances.

[0040] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, identify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0041] The memory device in the embodiments of the present application includes but is not limited to a three-dimensional NAND memory. For ease of understanding, the three-dimensional NAND memory is used as an example for description.

[0042] FIG1 shows a block diagram of an exemplary system 100 with a memory device according to some aspects of the present application. System 100 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG1 , system 100 can include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. Host 108 can be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. Host 108 can be configured to send data to or receive data from memory device 104.

[0043] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in a low duty cycle environment, such as a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0044] In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment Solid State Disk (SSD) or embedded Multi Media Card (eMMC), which is used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0045] The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including, but not limited to, bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 may also be configured to process error correction codes for data read from or written to the memory device 104.

[0046] The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., the host 108) according to a specific communication protocol. For example, the memory controller 106 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a Peripheral Component Interconnection (PCI) protocol, a PCI Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer Small Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Drive Electronics (IDE) protocol, a Firewire protocol, and the like.

[0047] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). In other words, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0048] In one example as shown in FIG2 a , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, etc. The memory card 202 can also include a memory card connector 204 that couples the memory card 202 to a host (e.g., the host 108 in FIG1 ).

[0049] In another example, as shown in FIG2 b , the memory controller 106 and the plurality of memory devices 104 can be integrated into an SSD 206. The SSD 206 can also include an SSD connector 208 that couples the SSD 206 to a host (e.g., the host 108 in FIG1 ). In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0050] In some embodiments, each memory block may be coupled to a plurality of word lines, and a plurality of memory cells coupled to each word line constitute a physical page.

[0051] FIG3 illustrates a schematic circuit diagram of an exemplary memory device 300 including peripheral circuitry according to some aspects of the present disclosure. Memory device 300 may be an example of memory device 104 in FIG1 . Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to memory cell array 301. For illustration, memory cell array 301 is described as a three-dimensional NAND-type memory cell array, wherein memory cells 306 are NAND-type memory cells provided in an array of memory strings 308, each memory string 308 extending vertically above a substrate (not shown). In some embodiments, each memory string 308 includes a plurality of memory cells 306 coupled in series and vertically stacked. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, that depends on the number of electrons trapped within the region of the memory cell 306. Each memory cell 306 may be a floating-gate memory cell including a floating-gate transistor, or a charge-trapping memory cell including a charge-trapping transistor.

[0052] In some embodiments, each memory cell 306 is a single-level cell (SLC) that has two possible storage states and can therefore store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) that can store more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell (TLC)), four bits per cell (also referred to as a quad-level cell (QLC)), five bits per cell (also referred to as a penta-level cell (PLC)), or more than five bits per cell. Each MLC can be programmed to take on a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to assume one of three possible programming levels from the erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0053] It should be noted that the storage state mentioned here is the storage state of the storage unit mentioned in this application. Different storage cells have different numbers of storage states. For example, an SLC type storage cell has 2 storage states (that is, two memory states), wherein these 2 storage states include: a programming state and an erased state. For another example, an MLC type storage cell has 4 storage states, wherein these 4 storage states include: an erased state and three programming states. For another example, a TLC type storage cell has 8 storage states, wherein these 8 storage states include: one erased state and seven programming states. In some embodiments, a QLC type storage cell has 16 storage states, wherein these 16 storage states include: one erased state and fifteen programming states.

[0054] As shown in FIG3 , each memory string 308 may include a lower select transistor (BSG) 310 (also known as a source-side select transistor) at its source terminal and an upper select transistor (TSG) 312 (also known as a drain-side select transistor) at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected memory string 308 during read and program operations. In some embodiments, the sources of the memory strings 308 in the same memory block 304 are coupled via the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some embodiments, each memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0V) to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0V) to a corresponding BSG 310 via one or more BSG lines 315.

[0055] As shown in FIG3 , a memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and to unselected memory blocks 304 in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory strings 308 can be coupled by word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0056] 3 , each memory cell 306 in the plurality of memory cells is coupled to a corresponding word line 318 , and each memory string 308 is coupled to a corresponding bit line 316 via a corresponding select transistor (eg, top select transistor (TSG) 312 ).

[0057] FIG4 illustrates a cross-sectional schematic diagram of an exemplary memory cell array 301 including a NAND memory string 308 according to some aspects of the present disclosure. As shown in FIG4 , the NAND memory cell array 301 may include a stacked structure 410 comprising a plurality of gate layers 411 and a plurality of insulating layers 412 alternately stacked in sequence, and a channel structure vertically extending through the gate layers 411 and the insulating layers 412. The channel structure is coupled to each gate layer to form a memory cell, and the channel structure is coupled to the plurality of gate layers in the stacked structure 410 to form the memory string 308. The gate layers 411 and the insulating layers 412 may be alternately stacked, with two adjacent gate layers 411 separated by an insulating layer 412.

[0058] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0059] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0060] In some embodiments, memory string 308 includes a channel structure extending vertically through stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with one or more semiconductor materials (e.g., serving as a semiconductor channel) and one or more dielectric materials (e.g., serving as a memory film). In some embodiments, the semiconductor channel includes silicon, such as polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). In some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially in this order from the center of the pillar toward the outer surface of the pillar. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0061] Referring back to FIG3 , the peripheral circuit 302 can be coupled to the memory cell array 301 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via the bit lines 316, word lines 318, source lines 314, BSG lines 315, and TSG lines 313. The peripheral circuit 302 can include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology. For example, FIG5 shows some exemplary peripheral circuits, including a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuits not shown in FIG. 5 may also be included.

[0062] The page buffer / sense amplifier 504 can be configured to read data from the memory cell array 301 and program (write) data to the memory cell array 301 according to a control signal from the control logic 512. In one example, the page buffer / sense amplifier 504 can store program data (write data) to be programmed into the memory cell array 301. In another example, the page buffer / sense amplifier 504 can perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 can also sense a low-power signal from the bit line 316 representing the data bit stored in the memory cell 306 and amplify the small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 506 can be configured to be controlled by the control logic 512 and select one or more memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0063] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive the word lines 318 using word line voltages generated from a voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive the BSG lines 315 and the TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cells 306 coupled to the selected word line(s) 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., a read voltage, a program voltage, a pass voltage, a channel boosting voltage, a verify voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0064] The control logic 512 can be coupled to each of the other parts in the peripheral circuit described above and is configured to control the operation of each of the other parts in the peripheral circuit. The register 514 can be coupled to the control logic 512 and includes a status register, a command register, and an address register for storing status information, command operation code (OP code), and command address for controlling the operation of each peripheral circuit. The interface 516 can be coupled to the control logic 512 and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic 512, as well as buffer status information received from the control logic 512 and relay it to the host. The interface 516 can also be coupled to the column decoder / bit line driver 506 via the data bus 518 and act as a data I / O interface and data buffer to buffer data and relay it to the memory cell array 301 or relay or buffer data from the memory cell array 301.

[0065] The basic principle of 3D NAND memory is that data is written by injecting a certain amount of charge into a memory cell, via carriers (electrons or holes) across a charge barrier. The stored data can then be read based on the threshold voltage at which the memory cell turns on. Therefore, to ensure accurate data is read, a robust and efficient error correction algorithm is typically employed during data reading.

[0066] However, as the charge stored in a memory cell changes over time due to age, repeated read operations, and temperature fluctuations, this can affect the accuracy of data reads. When the threshold voltage shifts significantly upward or downward, the likelihood of read errors is high when reading the data from the memory cell using the original read voltage. Furthermore, when the read error rate exceeds the error correction capability, data read failures can occur.

[0067] FIG6 is a schematic diagram illustrating an exemplary read operation flow for a memory system. As shown in FIG6 , when a memory controller controls a memory device to perform a read operation, it first performs a default read operation (FW default read) on the memory cell at the corresponding physical address. If the default read operation fails, a reread operation (Read retry) is performed. If the reread operation fails, a soft decode operation is performed. If the soft decode operation fails, a Redundant Array of Independent Disks (RAID) operation is performed. If the RAID operation fails, the read operation ceases and the read fails due to uncorrectable errors. The memory controller then sends a Read Fail signal to the host 108. The reread operation and the default read operation can be applied to hard decode.

[0068] In some embodiments, a reread operation can typically be performed by querying a retry table provided by the manufacturer. The reread operation is essentially an error correction mechanism. The reread table provides a reference voltage for reading data. By querying the reread table, each storage cell is read again at a read voltage that deviates from the normal threshold voltage and corrects the error in conjunction with an error correction algorithm in an attempt to correctly read the data. If the read error data is corrected, the reread table query stops. If the read error data cannot be corrected, the reread table query continues until the entire reread table is traversed.

[0069] The aforementioned reread operation method requires querying the reread table line by line, which inevitably increases the number of trial and error cycles and is time-consuming. Furthermore, the reread table provided by the manufacturer is only a reference value for specific environments. Real-world usage scenarios vary greatly, so the manufacturer's reread table does not cover many scenarios. Consequently, even after traversing the reread table, data may not be corrected, resulting in a significant waste of command processing time. In short, rereading by repeatedly polling the reread table is time-consuming, affecting the response time of subsequent commands and, consequently, device performance.

[0070] Based on one or more of the above problems, in a first aspect, embodiments of the present application provide a memory device.

[0071] As shown in FIG7 , the memory device includes: a memory cell array including memory cells having a plurality of storage bits; a predetermined number of memory cells forming a codeword, wherein the plurality of storage bits correspond to a plurality of pages; at least one page corresponds to a plurality of levels, wherein the plurality of levels includes a first level and a second level, wherein a read voltage of the second level is lower than a read voltage of the first level; and a peripheral circuit coupled to the memory cell array and configured to perform the following steps:

[0072] Step S10: obtaining a target valley voltage of a first target step, where the first target step includes at least one first step among a plurality of first steps corresponding to a plurality of pages; the target valley voltage is used as a read voltage when performing a read operation on at least one codeword.

[0073] Step S20: obtaining a predicted valley voltage of a second target step according to the target valley voltage of the first target step, where the second target step includes the remaining first steps and / or second steps; the read voltage of the second target step is lower than the read voltage of the first target step.

[0074] Here, the structure of the memory device is referred to above FIG3 and will not be described in detail here.

[0075] In some embodiments, a memory device includes a memory cell array, the memory cell array includes a plurality of memory cells, and a preset number of memory cells form a code word (CW).

[0076] In some embodiments, the number of storage cells included in a codeword is the same as the number of storage cells included in one encoding or decoding when performing error correction encoding or decoding. In some specific embodiments, the number of storage cells included in a codeword may be less than or equal to the number of storage cells coupled to a physical page, such as the number of storage cells included in a codeword is 1 / 4 of the number of storage cells coupled to a physical page. In some specific embodiments, a codeword may include a number ranging from 2 4 to 2 12 For example, a code word may include 2 4 , 2 8 or 2 12 storage units.

[0077] In general, different memory systems may choose codewords of different sizes to meet their performance, reliability, and storage requirements.

[0078] Memory cells in different types of memory devices (eg, MLC, TLC, or QLC) can store different numbers of bits.

[0079] It should be noted that in practice, codewords will have some additional reserved space for management and error correction, so the number of storage units actually required may slightly exceed the above calculation result.

[0080] It is understandable that a codeword may include multiple storage units, and the number of storage units included in a codeword may be adjusted according to actual conditions.

[0081] In some embodiments, the memory cell array includes memory cells with M storage bits, the M storage bits correspond to M pages, and the M-bit memory cells read their M-bit storage data through N-level read voltages; M and N are both integers greater than 1, and N=2 M -1.

[0082] For example, when the number of storage bits of a memory cell includes two, the corresponding storage states include states 0 to 4. Referring to FIG8A , the four states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, and state 3 (also called the third storage state) P3. The binary data corresponding to these four states are 11, 10, 00, and 01, respectively. Accordingly, the memory device includes two pages, namely, a lower page (LP) and an upper page (UP).

[0083] Taking the memory cell shown in FIG8A as an example, the two-bit memory cell reads its two-bit four-state storage data through three-level read voltages (first level read voltage L1, second level read voltage L2 and third level read voltage L3 shown in FIG8A).

[0084] For example, one page corresponds to multiple read voltages, and the other page corresponds to a single read voltage. As shown in FIG8A , the binary data corresponding to the lower page is 1001, and reading the lower page requires the corresponding first read voltage L1 and third read voltage L3. The binary data corresponding to the upper page is 1100, and reading the upper page requires the corresponding second read voltage L2.

[0085] For example, when the number of storage bits of a memory cell includes three bits, the corresponding storage states include states 0 to 7. Referring to FIG8B , the eight states are state 0 (also called the erased state) E, state 1 (also called the first storage state) P1, state 2 (also called the second storage state) P2, ... state 7 (also called the seventh storage state) P7. The binary data corresponding to the eight states are 111, 110, 100, 000, 010, 011, 001, and 101, respectively. Accordingly, the memory device includes three pages: a lower page, a middle page (MP), and an upper page.

[0086] Taking the memory cell shown in FIG8B as an example, the three-bit memory cell reads its three-bit eight-state storage data through seven levels of read voltages (the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7 shown in FIG8B ).

[0087] For example, each page corresponds to multiple read voltage levels. As shown in FIG8B , the binary data corresponding to the lower page are 10000111, and reading the lower page requires corresponding to the first read voltage L1 and the fifth read voltage L5. The binary data corresponding to the middle page are 11001100, and reading the middle page requires corresponding to the second read voltage L2, the fourth read voltage L4, and the sixth read voltage L6. The binary data corresponding to the upper page are 11100001, and reading the upper page requires corresponding to the third read voltage L3 and the seventh read voltage L7.

[0088] Exemplarily, when the number of storage bits of a memory cell includes four bits, the corresponding storage states include the 0th state to the 15th state. Referring to FIG8C , the 16 states are the 0th state (also called the erased state) E, the 1st state (also called the 1st storage state) P1, the 2nd state (also called the 2nd storage state) P2…the 15th state (also called the 15th storage state) P15, and the binary data corresponding to the 16 states are 1111, 0111, 0110….1110. Accordingly, the memory device includes four pages, namely, a lower page, a middle page, an upper page, and an extra page (XP). Here, the four storage bits corresponding to the 16 states are stored in the lower page, the middle page, the upper page, and the extra page, respectively.

[0089] Taking the memory cell shown in Figure 8C as an example, the four-bit memory cell reads its four-bit sixteen-state storage data through 15 levels of read voltages (the first level read voltage L1, the second level read voltage L2, the third level read voltage L3, the fourth level read voltage L4, the fifth level read voltage L5, the sixth level read voltage L6, the seventh level read voltage L7, the eighth level read voltage L8, the ninth level read voltage L9, the tenth level read voltage L10, the eleventh level read voltage L11, the twelfth level read voltage L12, the thirteenth level read voltage L13, the fourteenth level read voltage L14, and the fifteenth level read voltage L15 shown in Figure 8C).

[0090] For example, each page corresponds to multiple read voltage levels. As shown in FIG8C , the binary data corresponding to the lower page is 1100000011111100. Reading the lower page requires corresponding read voltages L2, L8, and L14. The binary data corresponding to the middle page is 1110000110000111. Reading the middle page requires corresponding read voltages L3, L7, L9, and L13. The binary data corresponding to the upper page is 1111100000110001. Reading the upper page requires corresponding read voltages L5, L10, L12, and L15. The binary data corresponding to the extra pages are 1000110000011111. Reading the extra pages requires corresponding first-level read voltage L1, fourth-level read voltage L4, sixth-level read voltage L6 and eleventh-level read voltage L11.

[0091] The lower page is usually closest to the source / drain, so each level of the read voltage corresponding to the lower page is determined first, with the fastest access speed and shortest response time, which can ensure balanced performance and durability during data access.

[0092] It should be noted that the method of preferentially determining each level of read voltage corresponding to the next page is only an example and is not used to limit the order of determining each level of read voltage in the multi-level read voltage corresponding to at least part of the pages in the embodiment of the present application.

[0093] In some embodiments, at least some pages correspond to multi-level read voltages, the multi-level read voltages including a first-level read voltage and a second-level read voltage, wherein the second-level read voltage is lower than the first-level read voltage. For example, the first-level read voltage can be understood as the highest read voltage among the multi-level read voltages for each page, and the second-level read voltage can be understood as other read voltages lower than the highest read voltage among the multi-level read voltages for each page.

[0094] It should be noted that the first and second levels are used to distinguish between a high-level read voltage and a low-level read voltage among the multiple-level read voltages corresponding to at least a portion of the page, with the low-level read voltage being lower than the high-level read voltage. For a memory cell containing multiple storage bits, a page corresponding to one storage bit may include one or more levels, and one level may include one or more levels.

[0095] For example, referring to FIG8A , a memory device includes a lower page and an upper page, wherein the lower page corresponds to multiple levels, and the multiple levels corresponding to the lower page include a first level and a third level, and a first level read voltage L1 is less than a third level read voltage L3. Here, the third level read voltage L3 corresponds to the read voltage of the first level, and the first level read voltage L1 corresponds to the read voltage of the second level.

[0096] For example, referring to FIG. 8B , a memory device includes a lower page, a middle page, and an upper page, wherein each page corresponds to multiple levels. The multiple levels corresponding to the lower page include a first level and a fifth level, where a first level read voltage L1 is less than a fifth level read voltage L5. The multiple levels corresponding to the middle page include a second level, a fourth level, and a sixth level, where a second level read voltage L2 and a fourth level read voltage L4 are both less than a sixth level read voltage L6. The multiple levels corresponding to the upper page include a third level and a seventh level, where a third level read voltage L3 is less than a seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively. The first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0097] Exemplarily, referring to Figure 8C, the memory device includes a lower page, a middle page, an upper page and an extra page, wherein each page corresponds to multiple levels, the multiple levels corresponding to the lower page include the second level, the eighth level and the fourteenth level, the second level read voltage L2 and the eighth level read voltage L8 are both less than the fourteenth level read voltage L14, the multiple levels corresponding to the middle page include the third level, the seventh level, the ninth level and the thirteenth level, the third level read voltage L3, the seventh level read voltage L7 and the ninth level read voltage L9 are all less than the thirteenth level read voltage L13, the multiple levels corresponding to the upper page include the fifth level, the tenth level, the twelfth level and the fifteenth level, the fifth level read voltage L5, the tenth level read voltage L10 and the twelfth level read voltage L12 are less than the fifteenth level read voltage L15, the multiple levels corresponding to the extra page include the first level, the fourth level, the sixth level and the eleventh level, the first level read voltage L1, the fourth level read voltage L4 and the sixth level read voltage L6 are less than the eleventh level read voltage L11. Here, the fourteenth-level read voltage L14, the thirteenth-level read voltage L13, the fifteenth-level read voltage L15 and the eleventh-level read voltage correspond to the first-level read voltages of the lower page, middle page, upper page and extra page respectively, the second-level read voltage L2 and the eighth-level read voltage L8 correspond to the second-level read voltage of the lower page, the third-level read voltage L3, the seventh-level read voltage L7 and the ninth-level read voltage L9 correspond to the second-level read voltage of the middle page, the fifth-level read voltage L5, the tenth-level read voltage L10 and the twelfth-level read voltage L12 correspond to the second-level read voltage of the upper page, the first-level read voltage L1, the fourth-level read voltage L4 and the sixth-level read voltage L6 correspond to the second-level read voltage of the extra page.

[0098] In some embodiments, the peripheral circuit is configured to: obtain a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to a plurality of pages; the target valley voltage is used as a read voltage when performing a read operation on at least one codeword; and obtain a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage, the second target stage including the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0099] Here and below, a memory cell array including memory cells with a storage bit count of 3 bits is used as an example for detailed description, but this is not intended to limit the various embodiments of the present application. As shown in FIG8B , the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7 correspond to the first-level read voltages of the lower, middle, and upper pages, respectively. The first-level read voltage L1, the second-level read voltage L2, and the fourth-level read voltage L4 and the third-level read voltage L3 correspond to the second-level read voltages of the lower, middle, and upper pages, respectively. The first target level includes at least one of the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7. The second target level includes the remaining first levels and / or second levels. For example, when the first target level is the seventh-level read voltage L7, the second target level includes the fifth-level read voltage L5, the sixth-level read voltage L6, and / or the first-level read voltage L1, the second-level read voltage L2, the fourth-level read voltage L4, and the third-level read voltage L3.

[0100] In some embodiments, when the first target level is the seventh-level read voltage L7, the predicted valley voltages of all other first and second levels can be obtained based on the target valley voltage of the seventh-level read voltage L7, that is, the predicted valley voltages of the first-level read voltage L1, the second-level read voltage L2, the fourth-level read voltage L4, the fifth-level read voltage L5, and the sixth-level read voltage L6 can be directly obtained based on the target valley voltage of the seventh-level read voltage L7.

[0101] It should be noted that the predicted valley voltage can be used directly as a target valley voltage to perform a read operation on the data to be read, or can be obtained after further processing. The specific method of obtaining the predicted valley voltage will be further described below.

[0102] FIG9 is a schematic diagram illustrating a method for determining a target valley voltage for the second target step, as shown in FIG8B , according to an embodiment of the present application. Referring to FIG8B and FIG9 , the peripheral circuit is configured to: obtain the target valley voltage for the first target step (the seventh-level read voltage L7); and, based on the target valley voltage for the first target step (the seventh-level read voltage L7), obtain predicted valley voltages for the second target step (the fifth-level read voltage L5, the sixth-level read voltage L6, and / or the first-level read voltage L1, the second-level read voltage L2, the fourth-level read voltage L4, and the third-level read voltage L3).

[0103] In some embodiments, the peripheral circuit is configured to: obtain, for a first target level, a first result corresponding to at least one codeword at a target read voltage; the first result includes a representation of the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; and adjust the target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; and determine the target valley voltage of the first target level based on the multiple first results.

[0104] In some embodiments, during the reading of the memory device, a read operation reads out the data of a physical page. When the number of storage cells contained in a codeword can be less than the number of storage cells coupled to a physical page, the codeword is a unit that can be executed to obtain the first result, but multiple codewords are not actually excluded. In other words, the first result corresponding to at least one codeword under the current read voltage can be obtained here. For example, a physical page can correspond to 4 codewords, and the page buffer hardware operation can count the fail bit count (FBC) of each of the 4 codewords at one time, and then add the FBC of the four codewords to obtain the FBC of a physical page. The subsequent calculation uses the added value. It can be understood that the first result here can be based on the data of a physical page, and a physical page can correspond to multiple codewords.

[0105] It should be noted that the difference between the first read voltage and the second read voltage can be less than a preset voltage. In some specific embodiments, the second read voltage is greater than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of 5mV to 20mV. For example, the difference between the first read voltage and the second read voltage can be 5mV, 10mV, 15mV, or 20mV. In other specific embodiments, the second read voltage is less than the first read voltage, and the difference between the first read voltage and the second read voltage is set to a range of -5mV to -20mV. For example, the difference between the first read voltage and the second read voltage can be -5mV, -10mV, -15mV, or -20mV.

[0106] It should be noted that the first read voltage and the second read voltage are contextually related, that is, the second read voltage is obtained after a first adjustment is performed based on the first read voltage. Based on this, the voltage difference between the first read voltage and the second read voltage is the step size of the first adjustment. The fact that the difference between the first read voltage and the second read voltage is less than the preset voltage can be understood as the first read voltage and the second read voltage having a smaller voltage difference. The preset voltage is related to the step size of the first adjustment and can be a voltage slightly larger than the step size of the first adjustment. In some specific embodiments, the preset voltage is set to a range of 6mV to 21mV. Exemplarily, the preset voltage can be 6mV, 11mV, 16mV, or 21mV. In other specific embodiments, the preset voltage is set to a range of -6mV to -21mV. Exemplarily, the preset voltage can be -6mV, -10mV, -16mV, or -21mV.

[0107] It should be noted that the first read voltage and the second read voltage are both general terms. The target read voltage and the read voltage obtained after the target read voltage is second-adjusted may both be referred to as the first read voltage, and the read voltage obtained after the first read voltage is first-adjusted with the first step size may both be referred to as the second read voltage. In other words, the first read voltage is a general term and may be understood as the target read voltage or the target adjusted read voltage (the voltage obtained after the target read voltage is second-adjusted with the second step size, where the second step size may range from 50 mV to 150 mV, and illustratively, the second step size may be 50 mV, 60 mV, 70 mV, 80 mV, 100 mV, 120 mV, or 150 mV).

[0108] In each embodiment of the present application, the first result corresponding to a specific voltage can be understood as: a first adjustment is made to a specific voltage, that is, a specific voltage and a specific voltage after the first adjustment have a first voltage difference ΔV1, and the number of bits flipped in the two reading results of a preset number of storage cells at a specific voltage and a specific voltage after the first adjustment can be used as the first result corresponding to the specific voltage, wherein the preset number of storage cells can form at least one codeword.

[0109] For example, the first result corresponding to the first read voltage can be understood as: the first read voltage is adjusted to obtain the second read voltage, that is, the first read voltage and the second read voltage have a first voltage difference ΔV1, and the number of bits flipped in the two read results of the preset number of memory cells at the first read voltage and the second read voltage can be used as the first result corresponding to the first read voltage. The first read voltage can be a target read voltage of the first target step (V0 shown in FIG9 ), and the second read voltage can be a read voltage obtained by performing the first adjustment on the first read voltage (V1 shown in FIG9 ), or the first read voltage can be a target adjusted read voltage of the first target step (V2 shown in FIG9 ), and the second read voltage can be a target read voltage obtained by performing the first adjustment on the target adjusted read voltage (V3 shown in FIG9 ).

[0110] In some embodiments, before obtaining a first result corresponding to at least one codeword at a target read voltage of a first target level, the read mode of the memory device is set to a single-level read mode (Single Level Read, SLR); the single-level read mode includes reading at least one bit of storage data stored in a memory cell through a first-level read voltage.

[0111] In some embodiments, the memory device is configured to enter a single-level read mode in response to a mode setting command, and obtain a first result corresponding to at least one codeword at a target read voltage of a first target step in the single-level read mode.

[0112] Exemplarily, as shown in Figure 9, the peripheral circuit is configured to: obtain a first result Y1 corresponding to at least one codeword at a target read voltage (V0 shown in Figure 9) for the seventh-level read voltage L7; and adjust the target read voltage (V0 shown in Figure 9) at least once, and obtain a first result Y2 corresponding to the adjusted target read voltage (V2 shown in Figure 9) after each adjustment; and determine the target valley voltage of the seventh-level read voltage L7 based on multiple first results.

[0113] In some specific embodiments, at least one adjustment can be a second adjustment; the second adjustment can be understood as a larger adjustment, with the second adjustment amplitude being greater than the first adjustment amplitude. In some specific embodiments, the step size of the second adjustment is set to range from 50mV to 150mV. Exemplarily, the second adjustment step size can be 50mV, 60mV, 70mV, 80mV, 100mV, 120mV, or 150mV. Exemplarily, as shown in FIG9 , a second adjustment is performed on the target read voltage of the seventh-level read voltage L7 ( V0 shown in FIG9 ) to obtain an adjusted target read voltage ( V2 shown in FIG9 ). The adjusted target read voltage ( V2 shown in FIG9 ) and the target read voltage of the seventh-level read voltage L7 ( V0 shown in FIG9 ) have a second voltage difference ΔV2. The magnitude of the second voltage difference ΔV2 is the step size of the second adjustment. The step size of the second adjustment is greater than the step size of the first adjustment, i.e., the second voltage difference ΔV2 is greater than the first voltage difference ΔV1.

[0114] In some embodiments, if the first result corresponding to the target read voltage after one adjustment is lower than the second threshold, or if the smallest first result among multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value, when the number of remaining multiple first results whose differences from the reference value are less than the third threshold is greater than a preset number, the adjustment is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage.

[0115] In some embodiments, the second threshold is used as a judgment threshold for the target valley voltage. That is, when the first result is less than or equal to the second threshold, it indicates that when the read voltage corresponding to the first result is used as the target valley voltage, the error rate of the read result is low and the reliability is high.

[0116] The second threshold value is related to the type and storage density of the memory device. The second threshold value can be an empirical value or a default value configured at the factory for the memory device, which is derived from extensive simulation experiments before the memory device leaves the factory. For example, the second threshold value is set in the range of 5 to 30. More specifically, the second threshold value can be 5, 10, 15, 20, 25, or 30.

[0117] As shown in FIG9 , the first result Y2 corresponding to the adjusted target read voltage (V2 shown in FIG9 ) is less than the second threshold value, so the adjusted target read voltage (V2 shown in FIG9 ) is used to determine the target valley voltage of the seventh-level read voltage L7 .

[0118] In some embodiments, the peripheral circuit is configured to obtain a predicted valley voltage of the second target step based on the target valley voltage of the first target step and a mapping function, wherein the mapping function is used to characterize the relationship between the target valley voltage of the first target step and the predicted valley voltage of the second target step.

[0119] In some embodiments, the peripheral circuit is configured to obtain a predicted valley voltage of the second target order based on the target valley voltage of the first target order, the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient in the mapping function; wherein the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

[0120] It should be noted that the predicted valley voltage can be directly used as the target valley voltage to perform a read operation on the data to be read, or the target valley voltage can be obtained after further processing. For ease of explanation, the mapping function in this embodiment is also referred to as the second mapping function, that is, the second mapping function is used to characterize the relationship between the target valley voltage / predicted valley voltage of the first target step and the predicted valley voltage of the second target step.

[0121] In some specific embodiments, a reference offset value ref_sft and a predicted offset value pred_sft of the predicted valley voltage pred_valley of the second target step relative to the target read voltage v_default of the second target step are obtained based on the target valley voltage valley_shift of the first target step, the first adjustment coefficient dir, the second adjustment coefficient pred_ref, and the third adjustment coefficient pred_mult. Exemplarily, formula (1) for obtaining the reference offset value ref_sft is: ref_sft = dir * valley_shift. Formula (2) for obtaining the predicted offset value pred_sft is: pred_sft = ref_sft / pred_ref + ref_sft / (pred_ref * pred_mult).

[0122] Here, the target read voltage v_default of the second target stage may refer to a preset read voltage that can distinguish two adjacent storage states of a memory cell of the memory device in a previous reading process, wherein the preset read voltage may be an empirical value; or it may be a default value configured when the memory device leaves the factory, which is obtained through a large number of simulation experiments before the memory device leaves the factory.

[0123] It should be noted that in formula (2), A / B represents the quotient obtained by dividing A by B. For example, ref_sft / pred_ref represents the quotient obtained by dividing the reference offset value ref_sft by the predicted offset value pred_sft. For example, when the reference offset value ref_sft is -35 and the predicted offset value pred_sft is 14, the result of ref_sft / pred_ref is -2.

[0124] In some specific embodiments, a predicted valley voltage pred_valley of the second target step is obtained based on the target read voltage v_default of the second target step and the predicted offset value pred_sft.

[0125] Exemplarily, the formula (3) for obtaining the predicted valley voltage pred_valley of the second target step is: pred_valley=pred_sft+v_default.

[0126] Exemplarily, taking TLC as an example, the exemplary first adjustment coefficient dir is 1 or -1. It should be noted that when the second target level is the second-level read voltage L2 or the third-level read voltage L3, the first adjustment coefficient dir is -1, and when the second target level is the first-level read voltage L1, the fourth-level read voltage L4, the fifth-level read voltage L5, or the sixth-level read voltage L6, the first adjustment coefficient dir is 1.

[0127] An exemplary second adjustment coefficient pred_ref is {DMY, 1, 1, 1, 4, 7, 2, 14}. In some embodiments, the value of the second adjustment coefficient pred_ref is related to the order of the read voltage. More specifically, when the read voltages used to obtain the predicted valley voltage of the second target order are the target valley voltage of the first level read voltage L1, the target valley voltage of the second level read voltage L2, the target valley voltage of the third level read voltage L3, the target valley voltage of the fourth level read voltage L4, the target valley voltage of the fifth level read voltage L5, the target valley voltage of the sixth level read voltage L6, and the target valley voltage of the seventh level read voltage L7, the second adjustment coefficient pred_ref takes values ​​of 1, 1, 1, 4, 7, 2, and 14, respectively.

[0128] An exemplary third adjustment coefficient pred_mult is {DMY, 1, 1, 1, 3, 1, 4, 3}. In some embodiments, the value of the third adjustment coefficient pred_mult is related to the order of the read voltage. More specifically, when the read voltages used to obtain the predicted valley voltage of the second target level are the target valley voltage of the first level read voltage L1, the target valley voltage of the second level read voltage L2, the target valley voltage of the third level read voltage L3, the target valley voltage of the fourth level read voltage L4, the target valley voltage of the fifth level read voltage L5, the target valley voltage of the sixth level read voltage L6, and the target valley voltage of the seventh level read voltage L7, the third adjustment coefficient pred_mult takes values ​​of 1, 1, 1, 3, 1, 4, and 3, respectively.

[0129] It should be noted that the first adjustment coefficient dir, the second adjustment coefficient pred_ref and the third adjustment coefficient pred_mult are all fixed values ​​related to the order of the read voltage. The first adjustment coefficient dir, the second adjustment coefficient pred_ref and the third adjustment coefficient pred_mult can be empirical values; they can also be default values ​​configured when the memory device leaves the factory, which are obtained through a large number of simulation experiments before the memory device leaves the factory.

[0130] Exemplarily, as shown in Figure 9, the peripheral circuit is configured to obtain the predicted valley voltage of the sixth-level read voltage L6 (V4 shown in Figure 9) based on the target valley voltage of the seventh-level read voltage L7 (V2 shown in Figure 9) and the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the seventh-level read voltage L7 and the predicted valley voltage of the sixth-level read voltage L6.

[0131] In a specific embodiment, combined with the specific examples of the first adjustment coefficient, the second adjustment coefficient and the third adjustment coefficient when taking TLC as an example in the above embodiment and Figure 9, since the first target level is the seventh-level read voltage L7 and the second target level is the sixth-level read voltage L6, the first adjustment coefficient dir takes a value of 1, the second adjustment coefficient pred_sft takes a value of 14, and the third adjustment coefficient pred_mult takes a value of 3. Exemplarily, the target valley voltage of the seventh-level read voltage L7 is -35DAC, and -35DAC represents the offset value of the target valley voltage of the seventh-level read voltage L7 compared to the target read voltage of the seventh-level read voltage L7. Therefore, according to formula (1), the reference offset value ref_sft = (-1)*(-35), and according to formula (2), the predicted offset value pred_sft = (-1)*(-35) / 14+1*(-35) / (14*3) = 2DAC are obtained. According to formula (3), the predicted valley voltage pred_valley = 2DAC+v_default of the sixth-level read voltage L6 is obtained. It can be understood that the magnitude of the predicted valley voltage pred_valley of the sixth-level read voltage L6 is 2DAC offset compared to the target read voltage of the sixth-level read voltage L6.

[0132] The above formulas and related parameters (such as the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient) are only used as an example. The formulas and related parameters in the embodiments of the present application can be adjusted according to actual product performance.

[0133] It should be noted that the conversion relationship between DAC and the aforementioned mV is 1DAC=10mV.

[0134] In some embodiments, the peripheral circuit is configured to: obtain a first result corresponding to at least one codeword at a target read voltage for a second target level; and obtain a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target level is less than the first threshold value, determine that the predicted valley voltage of the second target level is the target valley voltage of the second target level.

[0135] In some embodiments, the peripheral circuit is configured to: when the first result corresponding to the predicted valley voltage of the second target level is greater than or equal to a first threshold, adjust the predicted valley voltage reading voltage of the second target level at least once, and obtain the first result corresponding to the adjusted target reading voltage after each adjustment; determine the target valley voltage of the second target level based on multiple first results.

[0136] In some embodiments, the first threshold is greater than or equal to the second threshold.

[0137] For example, as shown in FIG9 , the peripheral circuit is configured to: obtain a first result corresponding to at least one codeword at a target read voltage for the sixth-level read voltage L6; and derive a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to represent the first result corresponding to the upper limit of the predicted valley voltage. The target read voltage for the sixth-level read voltage L6 can be an empirical value or a default value configured at the factory for the memory device.

[0138] As shown in Figure 9, the first result Y3 corresponding to the predicted valley voltage of the sixth-level read voltage L6 (V4 shown in Figure 9) is greater than the first threshold value. Therefore, the predicted valley voltage of the sixth-level read voltage L6 (V4 shown in Figure 9) is adjusted at least once, and the first result Y4 corresponding to the adjusted target read voltage (V6 shown in Figure 9) is obtained after each adjustment; based on multiple first results, the target valley voltage of the sixth-level read voltage L6 is determined.

[0139] The first result Y3 is the number of bits flipped in the two read results at the first read voltage V4 and the second read voltage V5, and the first result Y4 is the number of bits flipped in the two read results at the first read voltage V6 and the second read voltage V7.

[0140] Illustratively, the adjusted target read voltage (V6 shown in FIG. 9 ) and the predicted read voltage of the sixth level read voltage L6 (V4 shown in FIG. 9 ) have a second voltage difference ΔV2 .

[0141] As shown in Figure 9, since the first result Y4 corresponding to the adjusted target read voltage (V6 shown in Figure 9) is less than the first threshold, the adjusted target read voltage (V4 shown in Figure 9) is determined as the target valley voltage of the sixth-level read voltage L6.

[0142] In other embodiments, the peripheral circuit is configured as follows: when the first result corresponding to the predicted valley voltage of the second target order is greater than or equal to a first threshold, the predicted valley voltage of the second target order is obtained based on the target valley voltage of the first target order and the backup adjustment coefficient of the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the first target order and the predicted valley voltage of the second target order.

[0143] Exemplarily, as shown in Figure 9, the peripheral circuit is configured as follows: when the first result Y3 corresponding to the predicted valley voltage of the sixth-level read voltage L6 (V4 shown in Figure 9) is greater than the first threshold, the predicted valley voltage of the sixth-level read voltage L6 is obtained according to the target valley voltage of the seventh-level read voltage L7 and the backup adjustment coefficient of the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the seventh-level read voltage L7 and the predicted valley voltage of the sixth-level read voltage L6.

[0144] It should be noted that Figure 9 takes the first target level as the seventh-level read voltage L7 as an example, and illustrates the process of obtaining the predicted valley voltage of the sixth-level read voltage L6 based on the target valley voltage of the seventh-level read voltage L7. The process of obtaining the predicted valley voltages of other second levels based on the seventh-level read voltage L7 can refer to the relevant description and will not be repeated here.

[0145] In other embodiments, the predicted valley voltage of the sixth-level read voltage L6 can be obtained based on the seventh-level read voltage L7, the target valley voltage of the sixth-level read voltage L6 can be obtained based on the predicted valley voltage of the sixth-level read voltage L6, and then the predicted valley voltage of the fifth-level read voltage L5 can be obtained based on the valley voltage of the sixth-level read voltage L6, and so on, to obtain the target valley voltages of the fifth-level read voltage L5, the fourth-level read voltage L4, the third-level read voltage L3, the second-level read voltage L2 and the first-level read voltage L1 respectively.

[0146] In some embodiments, the peripheral circuit is configured to: obtain a target valley voltage of a first stage of each of the multiple pages; and obtain a predicted valley voltage of a second stage belonging to the same page as the first stage based on the target valley voltage of the first stage in each page.

[0147] Specifically, as shown in Figures 10A, 10B, 10C, and 10D, the number of storage bits of a memory cell of at least one codeword is 3, corresponding to the lower, middle, and upper pages, each corresponding to multiple levels. The multiple levels of the lower page include a first level and a fifth level, where the first level read voltage L1 is less than the fifth level read voltage L5. The multiple levels of the middle page include a second level, a fourth level, and a sixth level, where the second level read voltage L2 and the fourth level read voltage L4 are both less than the sixth level read voltage L6. The multiple levels of the upper page include a third level and a seventh level, where the third level read voltage L3 is less than the seventh level read voltage L7. Here, the fifth level read voltage L5, the sixth level read voltage L6, and the seventh level read voltage L7 correspond to the first level read voltages of the lower, middle, and upper pages, respectively, and the first level read voltage L1, the second level read voltage L2, the fourth level read voltage L4, and the third level read voltage L3 correspond to the second level read voltages of the lower, middle, and upper pages, respectively.

[0148] Exemplarily, as shown in Figures 10A and 10D, the peripheral circuit is configured to: obtain the target valley voltage of the fifth-level read voltage L5 of the lower page among multiple pages; and obtain the predicted valley voltage of the first-level read voltage L1 of the lower page based on the target valley voltage of the fifth-level read voltage L5 of the lower page.

[0149] Specifically, for the fifth-level read voltage L5, a first result Y5 corresponding to at least one codeword under the target read voltage (V8 shown in Figure 10A) is obtained; and the target read voltage (V8 shown in Figure 10A and Figure 10D) is adjusted at least once, and after each adjustment, a first result Y6 corresponding to the adjusted target read voltage (V10 shown in Figure 10A and Figure 10D) is obtained; based on multiple first results, the fifth-level read voltage L5 is determined.

[0150] The first result Y5 is the number of bits flipped in the two read results at the first read voltage V8 and the second read voltage V9, and the first result Y6 is the number of bits flipped in the two read results at the first read voltage V10 and the second read voltage V11.

[0151] Referring to the process of determining the target valley voltage of the seventh-level read voltage L7 in Figure 9, since the first result Y6 corresponding to the adjusted target read voltage (V10 shown in Figures 10A and 10D) is less than the second threshold, the adjusted target read voltage (V10 shown in Figure 10A) is determined to be the target valley voltage of the fifth-level read voltage L5.

[0152] As shown in Figures 10A and 10D , the peripheral circuit is configured to obtain a predicted valley voltage (V12 shown in Figure 10A ) of the first-level read voltage L1 based on the target valley voltage (V10 shown in Figures 10A and 10D ) of the fifth-level read voltage L5 and a mapping function. The process of obtaining the target valley voltage of the first-level read voltage L1 based on the predicted valley voltage (V12 shown in Figure 10A ) of the first-level read voltage L1 can be referred to the process of obtaining the target valley voltage of the sixth-level read voltage L6 based on the predicted valley voltage of the sixth-level read voltage L6 in Figure 9 , and will not be further described here.

[0153] In some embodiments, each page in the multiple pages includes multiple second stages; the peripheral circuit is configured to: obtain the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages belonging to the same page as the first stage based on the valley voltage of the first stage of each page in the multiple pages; and obtain the predicted valley voltage of the second stage with the smaller read voltage in the adjacent sequence based on the predicted valley voltage of the second stage with the larger read voltage among the multiple second stages belonging to the same page as the first stage, until the predicted valley voltages of all the second stages belonging to the same page as the first stage are obtained.

[0154] Exemplarily, as shown in FIG10B , the peripheral circuit is configured as follows: based on the valley voltage of the sixth-level read voltage L6 of the middle page among the multiple pages (V13 shown in FIG10B ), the predicted valley voltage of the fourth-level read voltage L4 having the largest read voltage among the multiple second-stage read voltages of the middle page is obtained (V14 shown in FIG10B ); based on the predicted valley voltage of the fourth-level read voltage L4, the target valley voltage of the fourth-level read voltage L4 is obtained; and based on the target valley voltage or predicted valley voltage of the fourth-level read voltage L4, the predicted valley voltage of the second-level read voltage L2 having a smaller read voltage than its adjacent sequence is obtained (V15 shown in FIG10B ).

[0155] As shown in Figure 10C, the peripheral circuit is configured to obtain the predicted valley voltage (V17 shown in Figure 10C) of the third-level read voltage L3 of the upper page based on the target valley voltage (V16 shown in Figure 10C) of the seventh-level read voltage L7 of the upper page.

[0156] In some embodiments, the peripheral circuit is configured to perform a read operation on at least one codeword according to target valley voltages of the first target step and the second target step.

[0157] Exemplarily, as shown in Figures 10A to 10C, the peripheral circuit is configured to perform a read operation on at least one codeword based on the target valley voltages of the first-level read voltage L1, the second-level read voltage L2, the third-level read voltage L3, the fourth-level read voltage L4, the fifth-level read voltage L5, the sixth-level read voltage L6, and the seventh-level read voltage L7.

[0158] In some embodiments, in the scenario of a QLC type memory cell, the number of storage bits of the memory cell includes four bits, and the corresponding storage states include the 0th state to the 15th state. The four storage bits corresponding to the 16 states are respectively stored in the lower page, the middle page, the upper page, and the extra page. The lower page includes a first level (i.e., the fourteenth level) and multiple second levels (i.e., the eighth level and the second level); the middle page includes a first level (i.e., the thirteenth level) and multiple second levels (i.e., the ninth level, the seventh level, and the third level); the upper page includes a first level (i.e., the fifteenth level) and multiple second levels (i.e., the twelfth level, the tenth level, and the fifth level); and the extra page includes a first level (i.e., the eleventh level) and multiple second levels (i.e., the sixth level, the fourth level, and the first level).

[0159] In some embodiments, as shown in FIG8C , the peripheral circuit is configured to: obtain the predicted valley voltage of the eighth level read voltage L8 of the lower page according to the target valley voltage of the fourteenth level read voltage L14 of the lower page, obtain the predicted valley voltage of the second level read voltage L2 of the lower page according to the predicted valley voltage of the eighth level read voltage L8 of the lower page; obtain the predicted valley voltage of the ninth level read voltage L9 of the middle page according to the target valley voltage of the thirteenth level read voltage L13 of the middle page, obtain the predicted valley voltage of the seventh level read voltage L7 of the middle page according to the predicted valley voltage of the ninth level read voltage L9 of the middle page, obtain the predicted valley voltage of the third level read voltage L3 of the middle page according to the predicted valley voltage of the seventh level read voltage L7 of the middle page; obtain the predicted valley voltage of the tenth level read voltage L13 of the upper page according to the predicted valley voltage of the thirteenth level read voltage L13 of the middle page, obtain the predicted valley voltage of the ninth level read voltage L7 of the middle page, obtain the predicted valley voltage of the third level read voltage L3 of the middle page according to the predicted valley voltage of the seventh level read voltage L7 of the middle page; obtain the predicted valley voltage of the ninth level read voltage L13 of the upper page according to the predicted valley voltage of the thirteenth level read voltage L13 of the middle page The target valley voltage of the fifth-level read voltage L15 is obtained, and the predicted valley voltage of the twelfth-level read voltage L12 of the previous page is obtained. Based on the predicted valley voltage of the twelfth-level read voltage L12 of the previous page, the predicted valley voltage of the tenth-level read voltage L10 of the previous page is obtained. Based on the predicted valley voltage of the tenth-level read voltage L10 of the previous page, the predicted valley voltage of the fifth-level read voltage L5 of the previous page is obtained. Based on the target valley voltage of the eleventh-level read voltage L11 of the additional page, the predicted valley voltage of the sixth-level read voltage L6 of the additional page is obtained. Based on the predicted valley voltage of the sixth level of the additional page, the predicted valley voltage of the fourth level of the additional page is obtained. Based on the valley voltage of the sixth level of the additional page, the predicted valley voltage of the first-level read voltage L1 of the additional page is obtained. In this way, the predicted valley voltages of the 15-level read voltages required for reading the QLC type memory cell are obtained, and the method for obtaining the valley voltages based on the predicted valley voltages shown in FIG. 9 can be used to obtain the target valley voltages of the 15-level read voltages required for reading the QLC type memory cell.

[0160] In some embodiments, the memory device is a memory device after data retention.

[0161] In some specific embodiments, the predicted valley voltage of the second target level may refer to a predicted read voltage predicted based on the target valley voltage of the first target level and a usage scenario (eg, data retention scenario) of the memory device.

[0162] In some embodiments, the peripheral circuit is configured to: read the stored data of at least one codeword at a first read voltage to obtain a second result; read the stored data of at least one codeword at a second read voltage to obtain a third result; perform a logical operation on the second result and the third result to obtain a fourth result; and count the number of bits in the fourth result that represent the flipping of the third result compared to the second result to obtain the first result.

[0163] Exemplarily, as shown in FIG9 , data stored in a storage cell in at least one codeword is read at a first read voltage (V0 shown in FIG9 ), and a storage cell having a threshold voltage less than the first read voltage is marked as bit 1, and a storage cell having a threshold voltage greater than the first read voltage is marked as bit 0, thereby obtaining a second result.

[0164] Exemplarily, as shown in FIG9 , data stored in a storage cell in at least one codeword is read at a second read voltage (V1 shown in FIG9 ), and a storage cell whose threshold voltage is less than the second read voltage is marked as bit 1, and a storage cell whose threshold voltage is greater than the second read voltage is marked as bit 0, to obtain a third result.

[0165] Exemplarily, the second result and the third result are subjected to an XOR operation to obtain a fourth result. It should be noted that the XOR operation is one of the basic logical operations. In binary, if two binary numbers at the same position are the same, the result is "0", and if two binary numbers at the same position are different, the result is "1" (i.e., the same is 0, and different is 1).

[0166] Exemplarily, a bit set to 1 in the fourth result indicates that the data read from a memory cell in at least one codeword at the first read voltage and the data read from the second read voltage are different, while a bit set to 0 in the fourth result indicates that the data read from a memory cell in at least one codeword at the first read voltage and the data read from the second read voltage are the same. In other words, the number of bits set to 1 in the fourth result indicates the number of bits flipped between the first and second read voltages for the at least one codeword, while the number of bits set to 0 in the fourth result indicates the number of bits that are identical between the first and second read voltages for the at least one codeword. Since a single-level read mode is employed, i.e., both read operations read a single bit of data stored in the same page of memory cells in the at least one codeword, the number of bits set to 1 in the fourth result indicates the number of memory cells flipped between the first and second read voltages for the at least one codeword, which are recorded as the first result corresponding to the first read voltage. For example, the first result Y1 corresponding to the at least one codeword at the target read voltage of the first target level (V0 shown in FIG. 9 ) and the first result Y2 corresponding to the at least one codeword at the target adjusted read voltage of the first level (V2 shown in FIG. 9 ) are.

[0167] In some embodiments, the peripheral circuit includes: a first latch, a second latch, and a third latch; the first latch is configured to store the second result; the second latch is configured to store the third result; and the third latch is configured to store the fourth result.

[0168] Exemplarily, the stored data of at least one codeword read at a first read voltage (i.e., the second result) is stored in the first latch, the stored data of at least one codeword read at a second read voltage (i.e., the third result) is stored in the second latch, and the data after performing an XOR operation on the second result and the third result (i.e., the fourth result) is stored in the third latch.

[0169] On the first aspect, in each memory device provided by the embodiments of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), thereby reducing the amount of data transmitted; the process of obtaining the first result is converged inside the memory device, does not occupy the space of, for example, a memory controller, and has a low degree of dependence on, for example, a memory controller; completing the process of obtaining the target valley voltage based on the first result and obtaining the predicted valley voltage of the second target stage based on the target valley voltage of the first target stage in the memory device reduces the transmission time of the output port; and the present invention is applicable to MLC, TLC or QLC type memory devices.

[0170] FIG11 is a flowchart of a method for operating a memory device according to an embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG11. It should be noted that, herein and hereinafter, the target valley voltage refers to the voltage used to perform a read operation on the data to be read.

[0171] In step S101, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S102 is executed.

[0172] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level of read voltage corresponding to each page in the multiple pages is determined in sequence. In step S103, one level is selected from the multiple levels corresponding to a page as the target level, and the target read voltage corresponding to the target level read voltage is first determined. For example, taking TLC as an example, the target valley voltages of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S103 is executed.

[0173] In step S103, the main task is to determine the type of the target level. Here, the target level can be divided into two categories, the first level (also called high level) and the second level (also called low level), wherein the read voltage of the first level is greater than the read voltage of the second level. For example, still taking the lower page of TLC as an example, L5 is the first level and L1 is the second level. If L1 is selected as the target level in step S103, the target level is the second level, that is, the low level; if L5 is selected as the target level in step S104, the target level is the first level, that is, the high level. According to the target level being the low level, execute step S104; according to the target level being the high level, execute step S106.

[0174] In step S104, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S105 is executed.

[0175] In step S105, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the first mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the second mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is directly performed using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding is successful, the two-step prediction is successful. At this time, the search for the target valley voltage is stopped and step S121 is executed. If the hard decoding fails, the two-step prediction is failed. At this time, the point corresponding to the predicted valley voltage is used as the near-valley point for the subsequent iteration, and step S107 is continued.

[0176] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jump from step S105 to S107.

[0177] If the target level is a high level, a target valley voltage for the high level is determined by searching or looping. In step S106, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be a read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S107 is executed after step S106.

[0178] In step S107, the target valley voltage is determined by searching or looping. After step S107, step S108 is executed.

[0179] For the first execution loop, in step S108, a first result at the target read voltage is obtained. It is understood that for subsequent execution loops, in step S108, a first result at an adjusted target read voltage is obtained. After step S108, step S109 is executed.

[0180] In step S109, a first threshold value TH1 is determined or adjusted based on the first result at the target read voltage. It is understood that, during a read operation, the further the threshold voltage of a memory cell deviates from the threshold voltage during a write operation, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result at the default read voltage can be used to determine the first threshold value TH1. The first threshold value TH1 is used to characterize the change (increase) in the valley voltage caused by the memory cell threshold voltage deviation. Step S110 is executed after step S109.

[0181] It should be noted that step S109 is mainly for the first execution of the loop process, and can be skipped for subsequent execution of the loop process.

[0182] In step S110, a predicted valley voltage is obtained, and a determination is made as to whether the first result corresponding to the predicted valley voltage is less than the aforementioned first threshold TH1. Based on the first result corresponding to the target read voltage after the previous adjustment and the related mapping function (such as the aforementioned first mapping function), the predicted read voltage after the next adjustment is obtained, and the first result corresponding to the predicted valley voltage obtained is compared with the first threshold TH1. If the determination result of step S110 is negative, it indicates that the first result corresponding to the predicted valley voltage obtained at this time is greater than or equal to the first threshold TH1. The loop continues with step S108, adjusting the target read voltage and re-obtaining the predicted valley voltage. Each re-obtained first result corresponding to the predicted valley voltage is compared with the first threshold TH1 until the first result corresponding to the predicted read voltage obtained is less than the first threshold TH1. In other words, the prediction is iterated using the aforementioned prediction formula or related mapping function until the first result corresponding to the predicted read voltage obtained is less than the first threshold TH1. When the judgment result of step S110 is yes, it means that the first result corresponding to the predicted valley voltage obtained at this time is less than the first threshold TH1, and the process goes to the next step S111.

[0183] In step S111, an inflection point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. The inflection point can be understood as a point relatively close to the bottom of the valley. In some embodiments, the search can be performed from the near-valley point with a coarser step size (second step size) to the left and right boundaries respectively until the left and right boundaries are reached, and the point corresponding to the minimum first result in the search process is used as the inflection point. Here, the inflection point is a point closer to the bottom of the valley than the near-valley point, and the point less than the first threshold in the aforementioned step can be used as the near-valley point. The second step size can be a larger step size. In some embodiments, the second step size can be 5DAC-15DAC. Exemplarily, the second step size can be 5DAC, 10DAC or 15DAC. Step S112 is performed after step S111.

[0184] In step S112, it is determined whether an inflection point has been found. If no inflection point has been found, the search continues, and step S111 is continued until an inflection point is found. After the inflection point is found, step S113 is executed.

[0185] In step S113 and step S114, the search can be performed starting from the near-valley point with a finer step size (third step size) to the left boundary and the right boundary respectively until the left boundary and the right boundary are reached or the statistics of the upward trend exceed the preset number of times. Here, when the first result corresponding to the target read voltage after the next adjustment is greater than the first result corresponding to the target read voltage after the previous adjustment, a statistics of the upward trend is performed. In some embodiments, the preset number of times is 3-7 times. Exemplarily, the preset number of times can be 3, 5 or 7 times. It should be noted that the positions of step S113 and step S114 can be interchanged. The third step size can be a smaller step size. In some embodiments, the third step size can be 1DAC-4DAC. Exemplarily, the third step size can be 2DAC or 3DAC.

[0186] When the searches in step S113 and step S114 satisfy the aforementioned conditions (reaching the boundary or the statistics showing an upward trend exceed the preset number of times), step S115 is executed.

[0187] In step S115, the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S115, step S116 is executed.

[0188] In step S116, it is determined whether the target valley voltage is valid. The method for determining whether the target valley voltage is valid may be to read data using the target valley voltage and decode the read data via the memory controller. Successful decoding indicates whether the target valley voltage is valid. If the result of step S116 is yes, step S121 is executed; if the result of step S116 is no, step S117 is executed.

[0189] In step S117, it is determined whether the loop has ended. If the determination result of step S117 is yes, step S119 is executed; if the determination result of step S117 is no, step S118 is executed.

[0190] In step S118, the process enters the next loop and continues searching. Step S118 jumps to step S107.

[0191] In step S119, it is determined whether the target order is a high order. If the determination result of step S119 is yes, step S120 is executed; if the determination result of step S119 is no, step S121 is executed.

[0192] In step S120, the predicted valley voltage of the low-order is obtained based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be obtained by using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the second mapping function described above). Step S121 is executed after step S120.

[0193] In step S121, it is determined whether the corresponding target valley voltages for all the read voltage levels included in the page have been determined. If the determination result in step S121 is yes, it means that the target valley voltages for all the read voltage levels included in the page have been determined, and step S123 can be executed. If the determination result in step S121 is no, it means that the target valley voltages for all the read voltage levels included in the page have not yet been determined, and step S122 can be executed.

[0194] In step S122, for the steps whose valley bottom voltages are not determined, the valley bottom voltages of each step are determined in sequence. Step S122 jumps to step S102.

[0195] In step S123 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S123 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0196] FIG12 is a second flowchart of the operating method of the memory device provided in one embodiment of the present application. The detailed process of determining the target valley voltage will be described in detail below with reference to FIG12.

[0197] In step S201, the target valley voltage acquisition procedure is triggered, and the target valley voltage acquisition process is started. Next, step S202 is executed.

[0198] In step S202, in some embodiments, the read mode of the memory device is set to a single-level read mode, where the single-level read mode includes reading at least one bit of data stored in the memory cell using a single-level read voltage.

[0199] As previously mentioned, since the memory cell has multiple storage bits, the multiple storage bits correspond to multiple pages, and at least one page corresponds to multiple levels. When determining the target valley voltage, the target valley voltage of each level of the at least one level of read voltage corresponding to each page in the multiple pages is determined in sequence. In step S203, one level is selected from the multiple levels corresponding to a page as the target level, and the target read voltage corresponding to the target level read voltage is first determined. For example, taking TLC as an example, the target valley voltages of the first level read voltage L1 and the fifth level read voltage L5 corresponding to the next page are first determined. Either L1 or L5 can be selected as the target level. After the target level is determined, step S204 is executed.

[0200] In step S204, the main task is to determine the type of the target order. Here, the target order can be divided into two categories, the first order (also called high order) and the second order (also called low order), wherein the read voltage of the first order is greater than the read voltage of the second order. For example, still taking the lower page of TLC as an example, L5 is the first order and L1 is the second order. If L1 is selected as the target order in step S203, the target order is the second order, that is, the low order; if L5 is selected as the target order in step S204, the target order is the first order, that is, the high order. According to the target order being the low order, execute step S205; according to the target order being the high order, execute step S207.

[0201] In step S205, a predicted valley voltage is obtained. Here, the predicted valley voltage is obtained by deriving the predicted valley voltage corresponding to the lower order based on the target valley voltage corresponding to the higher order and a related mapping function. Here and below, the related mapping function may be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device. Next, step S206 is executed.

[0202] In step S206, it is determined whether the two-step prediction is successful. Here, the so-called two-step prediction may include a first prediction and a second prediction. The first prediction is to obtain a high-order predicted valley voltage. Specifically, the high-order predicted valley voltage is obtained based on the first result corresponding to the target read voltage (default read voltage), the order of the high-order, and the first mapping function. The second prediction is to obtain a low-order predicted valley voltage. Specifically, the low-order predicted valley voltage is obtained based on the high-order predicted valley voltage, the order of the low-order, and the second mapping function. After the two-step prediction, the predicted valley voltage is not confirmed. Hard decoding is performed directly using the high-order predicted valley voltage and the low-order predicted valley voltage. If the hard decoding succeeds, the two-step prediction is successful. The search for the target valley voltage is then stopped, and step S245 is executed. If the hard decoding fails, the two-step prediction fails. The point corresponding to the predicted valley voltage is used as the near-valley point for subsequent iterations, and step S220 is continued. Step S220 will be described in detail in the subsequent description.

[0203] It should be noted that if the hard decoding fails, it means that the two-step prediction is unsuccessful. At this time, it is necessary to determine the target valley voltage through searching or also called looping (or iteration). Therefore, when the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the search process can be directly executed from the beginning of the loop, that is, jumping from step S206 to S208; or the point corresponding to the predicted valley voltage can be directly used as the near-valley point of the subsequent iteration, that is, jumping from step S206 (S219) to S220.

[0204] If the target level is high, a search or loop is performed to determine the target valley voltage for the high level. In step S207, a default read voltage is used as the target read voltage. Here, the target read voltage can serve as the initial value for subsequent searches or loops. In some implementations, the default read voltage can be the read voltage when the threshold voltage of the memory cell has not shifted, such as the read voltage corresponding to a write operation, in which case the corresponding offset value is 0 DAC. Step S208 is executed after step S207.

[0205] In step S208, the target valley voltage is determined by searching or looping. After step S208, step S209 is executed.

[0206] During the first execution of the loop, step S209 is to obtain the first result at the target read voltage. It is understood that during subsequent execution of the loop, step S209 is to obtain the first result at the adjusted target read voltage. Step S210 is executed after step S209.

[0207] In step S210, various parameters are determined or adjusted based on the first result under the target read voltage. Here, the various parameters may include at least a first threshold, a first boundary voltage (the position corresponding to the first boundary voltage is also called the left boundary) and a second boundary voltage (the position corresponding to the second boundary voltage is also called the right boundary). It is understandable that when performing a read operation, the further the threshold voltage of the memory cell shifts compared to the threshold voltage during writing, the larger the first result read using the target read voltage will generally be. Based on this, the specific value of the first result under the default read voltage can be used to confirm the first threshold value. The first threshold value is used to characterize the change (lift) in the valley voltage caused by the shift of the threshold voltage of the memory cell. Here, the initial first boundary voltage and the initial second boundary voltage can be set based on empirical values, such as initially setting an initial first boundary voltage and an initial second boundary voltage with a relatively large range. Then, based on the first result under the target read voltage, the initial first boundary voltage and the initial second boundary voltage are adjusted, such as narrowing the range of the first boundary voltage and the second boundary voltage to obtain the first boundary voltage and the second boundary voltage. Step S211 is performed after step S210.

[0208] It should be noted that step S210 is mainly for the first execution cycle process, and can be skipped for subsequent execution cycles.

[0209] During the first execution of the loop, step S211 determines whether the first result at the target read voltage is less than the first threshold. It is understood that during subsequent executions of the loop, step S211 determines whether the first result at the adjusted target read voltage is less than the first threshold. If the determination result in step S211 is yes, it can be assumed that the first result corresponding to the adjusted target read voltage basically meets the requirements for read data decoding. The process then jumps to step S242, terminating the loop and outputting the corresponding target valley voltage. If the determination result in step S211 is no, the loop continues to step S212.

[0210] In step S212, it is determined whether the target memory block is a partially written memory block. Here, the target memory block is the memory block where at least one codeword to be read is located. A partially written memory block includes a memory block that has both a programmed state and an erased state. If the result of step S212 is yes, step S213 is executed; if the result of step S212 is no, step S214 is executed.

[0211] It should be noted that step S212 is mainly for the first execution of the loop process, and for subsequent execution of the loop process, this step can be skipped. After skipping this step, step S214 is continued.

[0212] In step S213, considering that the offset of the threshold voltage of a memory cell in an underfilled memory block is more complex than the offset of the threshold voltage of a memory cell in a full memory block (a full memory block can be understood as a memory block with a write time difference less than a preset time length in the same application scenario as the underfilled memory block), the offset of the threshold voltage of a memory cell in an underfilled memory block is also related to the position of the first blank physical page in the underfilled memory block (the first blank physical page can be understood as the physical page in which the first data state appearing in the underfilled memory block is all erased according to the programming order) and the position of the physical page to be read (the physical page where the at least one codeword to be read is located). Based on this, a predicted valley voltage can be obtained based on the first offset corresponding to the full memory block, the second offset corresponding to the position of the first blank physical page in the underfilled memory block, and the third offset corresponding to the position of the physical page to be read, and then the process proceeds to step S214. It is understandable that the obtained predicted valley voltage is more targeted than blindly adjusting the target read voltage, and can shorten the search time to a certain extent and determine the target valley voltage more quickly.

[0213] In step S214, determine whether a near-valley point is found. Here, the target read voltage after each adjustment is used as the horizontal coordinate, and the first result corresponding to the corresponding adjusted target read voltage is used as the vertical coordinate, and the horizontal and vertical coordinates will form a point. In the process of adjusting the target read voltage multiple times, the point corresponding to the multiple first results corresponding to the multiple adjusted target read voltages that is first less than the near-valley threshold can be used as the near-valley point. The near-valley threshold is used to characterize the maximum value of the first result corresponding to the voltage close to the bottom of the valley. It should be noted that the near-valley threshold is different from the aforementioned first threshold. When the first result is less than the near-valley threshold, it means that a more refined search can be carried out next; when the first result is less than the first threshold, it means that the search can be stopped next. When the judgment result of step S214 is yes, execute step S219; when the judgment result of step S214 is no, execute step S215.

[0214] If no near-valley point is found in step S215, the process proceeds to step S215, where the predicted read voltage after the next adjustment is obtained based on the first result corresponding to the target read voltage after the previous adjustment and the related mapping function (such as the first mapping function described above). That is, the prediction is iterated using the aforementioned prediction formula or mapping function. After step S215, step S216 is executed.

[0215] In step S216, a determination is made as to whether the next adjusted predicted read voltage hits a boundary. The boundary here can be either the left boundary or the right boundary, and hitting the boundary can be understood as being exactly on the boundary or crossing the boundary. If the determination result in step S216 is yes, step S217 is executed; if the determination result in step S216 is no, step S218 is executed.

[0216] In step S217, the adjustment direction is changed. There are two adjustment directions for adjusting the target read voltage: positive (rightward) and negative (leftward). Adjusting the offset direction can be understood as: previously adjusting to the right, then adjusting to the left after hitting the right boundary; or previously adjusting to the left, then adjusting to the right after hitting the left boundary. After step S217, step S218 is executed.

[0217] In step S218, the first result of the adjusted target read voltage is obtained. After step S218, step S214 is executed. That is, after each target voltage adjustment and the corresponding first result is obtained, a determination is made as to whether the latest adjustment point is a near-valley point. One or more adjustments are performed until a near-valley point is found.

[0218] It should be noted that if the next cycle is entered after the step of finding the near valley point because the subsequent conditions are not met, steps S215 to S218 can be skipped.

[0219] In step S219, you can refer to the description in step S206. When the two-step prediction is unsuccessful, the loop process will be entered. After the two-step prediction is unsuccessful, the point corresponding to the predicted valley bottom voltage can be directly used as the near-valley point of the subsequent iteration, that is, jump from step S219 to S220.

[0220] In step S220, it is determined whether the predicted valley voltage at the current point (the latest adjusted target read voltage) is valid. In some embodiments, the predicted valley voltage can be determined to be valid by the first result corresponding to the latest adjusted target read voltage being less than the first threshold. It should be noted that although in step S211, when the first result under the (adjusted) target read voltage is not less than the first threshold, S212 and subsequent steps are entered, but before the judgment result of step S214 is yes, the target read voltage is adjusted at least once, so the new adjusted target read voltage may be less than the first threshold at this time. When the judgment result of step S220 is yes, step S224 is executed; when the judgment result of step S220 is no, step S221 is executed.

[0221] In step S221, a determination is made as to whether the first result fbc of the current point is greater than the fbc of the previous point. After finding the near-valley point, a rough search for an inflection point begins to the left. Generally, the magnitude of fbc decreases and then increases. When the first result fbc of the current point is greater than the fbc of the previous point, this indicates that fbc will increase further during the subsequent leftward adjustment, and the previous point was a relatively small point. In this case, the previous point is set as the inflection point. In some embodiments, the step size used for the rough search can be a larger step size, for example, 5DAC-15DAC, or more specifically, 5DAC, 10DAC, or 15DAC. Based on this, if the determination result of step S221 is yes, step S223 is executed; if the determination result of step S221 is no, step S222 is executed.

[0222] In step S222, a rough search is performed to the left starting from the point near the valley, and each search is compared with the fbc of the previous search until a point is found where the value stops decreasing and starts increasing. Once this point is found, step S222 is completed and the process goes to step S223.

[0223] In step S223, the previous point (i.e., the point where the decrease stops and the increase begins) is set as the inflection point, and a fine search is performed to the right starting from the inflection point. In some embodiments, the step size used in the fine search can be a smaller step size, for example, 1DAC-4DAC, more specifically, 2DAC or 3DAC. After step S223, step S225 is executed.

[0224] In step S224, the current point is set as the inflection point, and a fine search is started from the inflection point to the right. In some embodiments, the step size used in the fine search can refer to step S223. After step S224, step S225 is executed.

[0225] In step S225 , it is determined whether the target read voltage is adjusted to the left. If the determination result of step S225 is yes, step S229 is executed; if the determination result of step S225 is no, step S226 is executed.

[0226] In step S226, the target read voltage is adjusted rightward. During the adjustment, a determination is made as to whether the right boundary is hit or whether the rise count (also known as an upward trend count, where an upward trend count is performed when the first result corresponding to the next adjusted target read voltage is greater than the first result corresponding to the previous adjusted target read voltage) exceeds a preset number TH2. In some embodiments, the preset number is 3-7 times, and illustratively, the preset number can be 3, 5, or 7 times. If the determination in step S226 is yes, step S228 is executed; if the determination in step S226 is no, step S227 is executed.

[0227] In step S227, if the right boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the right boundary, and a judgment is made after each search until the right boundary is hit or the lift count exceeds the preset number TH2. In other words, when step S227 is completed, jump to step S228.

[0228] In step S228 , the target read voltage starts to be adjusted leftward.

[0229] In step S229, while adjusting the target read voltage to the left, it is determined whether the left boundary or lift count is hit. The lift count here can be understood with reference to the aforementioned step S226. The thresholds for the left and right lift counts are generally set to the same value. If the judgment result of step S229 is yes, step S231 is executed; if the judgment result of step S229 is no, step S230 is executed.

[0230] In step S230, if the left boundary is not hit or the lift count does not exceed the preset number TH2, the search continues to the left boundary, and a judgment is made after each search until the left boundary is hit or the lift count exceeds the preset number TH2. That is, when step S230 is completed, jump to step S231.

[0231] In step S231, a determination is made as to whether the most recent first result is the minimum. Here, the most recent first result refers to whether the first result at the adjusted target read voltage after the last target read voltage adjustment is the minimum. At this point, it is necessary to traverse all search points in at least this loop to find the adjusted target read voltage corresponding to the point with the minimum first result. If the determination result in step S231 is yes, step S233 is executed; if the determination result in step S231 is no, step S232 is executed.

[0232] In step S232, the latest first result is updated using the found minimum first result. Step S233 is executed after step S232.

[0233] In step S233, a determination is made as to whether the near-valley count exceeds a preset number TH3. Here, the smallest first result among the multiple first results corresponding to the target read voltage after multiple adjustments is used as a reference value. If the number of remaining first results whose difference from the reference value is less than a third threshold is greater than a preset number, the search is stopped and the target read voltage corresponding to the smallest first result among the multiple first results is used as the target valley voltage. In some embodiments, the third threshold and the preset number can be set together based on actual conditions. Generally, if the third threshold is set slightly larger, the preset number is also relatively larger; generally, if the third threshold is set slightly smaller, the preset number is also relatively smaller. If the determination result in step S233 is yes, the search is stopped and step S237 is executed. If the determination result in step S233 is no, the process proceeds to the next determination and step S234 is executed.

[0234] In step S234, a determination is made as to whether the repeated valley count exceeds a preset number TH4. Here, during multiple adjustments to the target read voltage, different adjustment methods may be employed. If the adjusted target read voltages corresponding to the different adjustment methods exceeding the preset number are the same, and the first result corresponding to the same target read voltage is the minimum value among all first results, the same target read voltage is used as the target valley voltage. In some embodiments, the preset number is 2-4, and illustratively, the preset number may be 2, 3, or 4. If the determination result in step S234 is yes, the search is terminated and step S237 is executed. If the determination result in step S234 is no, the process proceeds to the next determination step, executing step S235.

[0235] It should be noted that step S233 and step S234 belong to different judgment methods and their positions can be interchanged. In other words, the repeated valley count can be judged first, and then the approximate estimate can be judged when the repeated valley count does not meet the conditions. It is understandable that other judgments can also be performed here to determine whether the loop has ended.

[0236] In step S235, it is determined whether the loop has ended. If the determination result of step S235 is yes, step S237 is executed; if the determination result of step S235 is no, step S236 is executed.

[0237] In step S236, the process enters the next loop and continues searching. Step S236 jumps to step S209.

[0238] In step S237, the target step search is completed, and the adjusted target read voltage corresponding to the minimum first result is used as the target valley voltage. After step S237, step S238 is executed.

[0239] In step S238, it is determined whether the target order is a high order. If the determination result of step S238 is yes, step S239 is executed; if the determination result of step S238 is no, step S240 is executed.

[0240] In step S239, the predicted valley voltage of the low-order is obtained based on the target valley voltage of the high-order. Here, the predicted valley voltage of the low-order can be obtained by using the target valley voltage of the high-order, the order of the low-order, and a related mapping function (such as the second mapping function described above). Step S240 is executed after step S239.

[0241] In step S240, it is determined whether the corresponding target valley voltages have been determined for all the read voltage levels included in the page. If the determination result in step S240 is yes, it means that the target valley voltages corresponding to all the read voltage levels included in the page have been determined, and step S242 can be executed. If the determination result in step S240 is no, it means that the target valley voltages corresponding to all the read voltage levels included in the page have not yet been determined, and step S241 can be executed.

[0242] In step S241, for the steps whose valley bottom voltage has not been determined, the valley bottom voltage of each step is determined in sequence. Step S236 jumps to step S202.

[0243] In step S242 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S242 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0244] It should be noted that the method disclosed in the embodiments of the present application can solve many problems existing in the reread operation, but it is not used to limit the application scenarios in the embodiments of the present application. The method disclosed in the embodiments of the present application is also applicable to conventional read operations.

[0245] It should be noted that the execution entity of the specific implementation process of each step in Figures 11 and 12 can be a peripheral circuit or a memory controller.

[0246] In a second aspect, an embodiment of the present application provides a memory system, as shown in Figures 13 and 14, the memory system 102 includes: one or more memory devices 104 as provided in the first aspect; and a memory controller 106, which is coupled to the memory device 104 and controls the memory device 104.

[0247] As shown in FIG13 , in some embodiments, a memory system 102 is coupled to a host, responding to host instructions and performing various feedback operations. The memory system 102 may include a memory controller 106 and a memory device 104 . The memory controller 106 is configured to control the memory device 104 to perform operations such as read, write, and erase operations. The memory controller 106 and the memory device 104 may also be coupled in any suitable manner.

[0248] The memory controller 106 may include a host interface (I / F) 1061, a memory interface (I / F) 1062, a processor 1063, a read-only memory (ROM) 1069, a random access memory (RAM) 1070, an error correction module 1064, a garbage collection module 1065, a wear leveling module 1066, a data buffer 1067, and a bus 1060. The host interface 1061 connects the host 108 and the memory controller 106. It allows the host and memory controller to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1062 connects the memory controller 106 and the memory device 104. The memory interface 1062 is used to facilitate data transmission between the memory controller 106 and the memory device 104. The processor 1063 is used to control the memory system 106 as a whole. The specific steps executed by the memory controller are primarily executed and completed by the processor 1063. In some specific embodiments, processor 1063 is, for example, a central processing unit (CPU), a microprocessor (MCU), or the like. ROM 1069 typically contains firmware or firmware program code for memory controller 106, which is used to initialize and operate various components of the memory controller. RAM 1070 is typically used to cache data. Error correction module 1064 may further include an encoding unit and a decoding unit; the encoding unit is used to encode the data to be stored to obtain check data, and the decoding unit is used to decode the check data to detect and correct possible erroneous data during data transmission.

[0249] The garbage collection module 1065 is used to read valid data from some storage blocks, rewrite it, and then mark these storage blocks as new backup storage blocks after the storage space of the memory device reaches a certain threshold. Garbage collection is generally implemented in three steps: selecting a source storage block with less valid data; finding valid data from the source storage block; and writing the valid data to the target storage block. At this point, all data in the source storage block becomes invalid data, and the source storage block is marked and can be used as a new backup storage block. The wear leveling module 1066 is used to maintain a balanced wear (number of erases) on each storage block in the memory system through data statistics and algorithms. Wear leveling is generally implemented in two steps: selecting a source storage block containing cold data; reading valid data from the source storage block and writing it to a storage block with a relatively high erase count. At this point, the valid data in the source storage block becomes invalid data and is marked. The buffer 1067 is used to cache data.

[0250] In some specific embodiments, the memory controller 106 is configured to control the memory device 104 to perform a read operation on at least one codeword.

[0251] In some specific embodiments, the memory device 104 includes: a memory cell array, including memory cells having a plurality of storage bits; a preset number of memory cells forming a codeword, wherein the plurality of storage bits correspond to a plurality of pages; at least one page corresponds to a plurality of levels, wherein the plurality of levels include a first level and a second level, and a read voltage of the second level is lower than a read voltage of the first level; a peripheral circuit of the memory device 104 is coupled to the memory cell array and configured to: obtain a target valley voltage of a first target level, wherein the first target level includes at least one first level among a plurality of first levels corresponding to the plurality of pages; the target valley voltage is used as a read voltage when performing a read operation on at least one codeword; and obtain a predicted valley voltage of a second target level based on the target valley voltage of the first target level, wherein the second target level includes the remaining first levels and / or the second levels; and the read voltage of the second target level is lower than the read voltage of the first target level.

[0252] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: obtain the valley voltage of the first stage of each of the multiple pages; and obtain a predicted valley voltage of the second stage belonging to the same page as the first stage based on the valley voltage of the first stage in each page.

[0253] In some specific embodiments, each of the multiple pages includes multiple second stages; the peripheral circuit of the memory device 104 is configured to: obtain a predicted valley voltage of the second stage with the largest read voltage among the multiple second stages belonging to the same page as the first stage based on the valley voltage of the first stage of each page in the multiple pages; and obtain, in sequence, predicted valley voltages of the second stages with smaller read voltages adjacent to the second stage with larger read voltage among the multiple second stages belonging to the same page as the first stage, until the predicted valley voltages of all the second stages belonging to the same page as the first stage are obtained.

[0254] In some specific embodiments, the number of storage bits of the memory cell is three, and the three storage bits correspond to the lower page, the middle page, and the upper page, respectively; the multi-stage includes a first-level read voltage to a seventh-level read voltage in which the read voltages increase sequentially; the fifth to seventh-level read voltages in the multi-stage are the first stages of the lower page, the middle page, and the upper page, respectively, the first-level read voltage is the second stage of the lower page, the second-level read voltage in the multi-stage and the fourth-level read voltage in the multi-stage are the second stage of the middle page, and the third-level read voltage in the multi-stage is the second stage of the upper page; the peripheral circuit of the memory device 104 is configured to: obtain a predicted valley voltage of the first-level read voltage of the lower page according to the valley voltage of the fifth-level read voltage of the lower page; obtain a predicted valley voltage of the fourth-level read voltage of the middle page according to the valley voltage of the sixth-level read voltage of the middle page; and obtain a predicted valley voltage of the second-level read voltage of the middle page according to the predicted valley voltage of the fourth-level read voltage of the middle page; and obtain a predicted valley voltage of the third-level read voltage of the upper page according to the valley voltage of the seventh-level read voltage of the upper page.

[0255] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to obtain a predicted valley voltage of the second target level based on the valley voltage of the first target level and a mapping function, where the mapping function is used to characterize the relationship between the valley voltage of the first target level and the predicted valley voltage of the second target level.

[0256] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to obtain a predicted valley voltage of the second target level based on the valley voltage of the first target level, the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient in the mapping function; wherein the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

[0257] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: obtain, for a first target level, a first result corresponding to at least one codeword at a target read voltage; the first result includes a number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; and adjust the target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; and determine the valley voltage of the first target level based on the multiple first results.

[0258] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: obtain a first result corresponding to at least one codeword at a target read voltage for the second target level; and obtain a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target level is less than the first threshold value, determine that the predicted valley voltage of the second target level is the target valley voltage of the second target level.

[0259] In some specific embodiments, the peripheral circuit of the memory device 104 is configured to: when the first result corresponding to the predicted valley voltage of the second target level is greater than or equal to a first threshold, adjust the predicted read voltage of the second target level at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; and determine the valley voltage of the second target level based on the multiple first results.

[0260] In some specific embodiments, the peripheral circuit of the memory device 104 is configured as follows: when the first result corresponding to the predicted valley voltage of the second target level is greater than or equal to a first threshold, the predicted valley voltage of the second target level is obtained based on the valley voltage of the first target level and a backup adjustment coefficient of a mapping function, and the mapping function is used to characterize the relationship between the valley voltage of the first target level and the predicted valley voltage of the second target level.

[0261] In some embodiments, the memory device is a memory device after data retention.

[0262] In some embodiments, the memory controller 106 is configured to: send a data acquisition instruction, the data acquisition instruction instructing to obtain the valley voltage; the memory device 104 is configured to: receive the data acquisition instruction, obtain the valley voltage, and send information including the valley voltage to the memory controller; the memory controller is further configured to: perform a read operation on the data stored in the memory device according to the valley voltage in the information.

[0263] In some embodiments, the memory controller 106 is further configured to perform an error correction code decoding operation on the read result of the read operation. In some implementations, the error correction code decoding operation includes a hard decoding operation using a low density parity check code (LDPC).

[0264] In some specific embodiments, as shown in FIG. 14 , the memory controller 106 is configured to send a data acquisition instruction instructing to acquire a target valley voltage; and the memory device 104 is configured to acquire the target valley voltage and send information including the target valley voltage to the memory controller 106 .

[0265] In some specific embodiments, as shown in FIG. 14 and FIG. 15 , the memory device 104 is configured to receive a data acquisition instruction, acquire a target valley voltage, and send information including the target valley voltage to a memory controller, including performing the following steps:

[0266] Step S301, start. In step S301, the program for obtaining the target valley voltage is triggered, and the process of obtaining the target valley voltage is started. Then, step S302 is executed.

[0267] Step S302: Select the target level.

[0268] Step S303: Determine whether the target level is the first target level. The first target level includes at least one first level among the plurality of first levels corresponding to the plurality of pages.

[0269] If the judgment result of step S303 is yes, step S305 is executed.

[0270] Step S305: Obtain a target valley voltage for the first target step. Specifically, for the first target step, obtain a first result corresponding to at least one codeword at a target read voltage; the first result includes a number of bits flipped in the read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; and the target read voltage is adjusted at least once, and after each adjustment, obtain a first result corresponding to the adjusted target read voltage; and determine the target valley voltage for the first target step based on the multiple first results.

[0271] If the judgment result of step S303 is no, step S304 is executed.

[0272] In step S304, the predicted valley voltage of the second target step is obtained. Specifically, the predicted valley voltage of the second target step is obtained based on the target valley voltage of the first target step; wherein the second target step includes the remaining first steps and / or second steps; the read voltage of the second target step is less than the read voltage of the first target step. Here, the predicted valley voltage is obtained based on the target valley voltage corresponding to the first target step (higher step) and the related mapping function to obtain the predicted valley voltage corresponding to the second target step whose read voltage is less than the read voltage of the first target step. Here and below, the related mapping function can be obtained by fitting a large number of experimental results before the memory device leaves the factory and stored in the memory device.

[0273] After step S304, step S306 is executed.

[0274] In step S306, a target valley voltage of the second target step is obtained. Specifically, for the second target step, a first result corresponding to at least one codeword at the target read voltage is obtained; and a first threshold is obtained based on the first result corresponding to the target read voltage; the first threshold is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target step is less than the first threshold, the predicted valley voltage of the second target step is determined to be the target valley voltage of the second target step. When the first result corresponding to the predicted valley voltage of the second target step is greater than or equal to the first threshold, the predicted valley voltage of the second target step is adjusted at least once, and the first result corresponding to the adjusted target read voltage is obtained after each adjustment; based on the multiple first results, the target valley voltage of the second target step is determined.

[0275] After step S305 or step S306, step S307 is executed.

[0276] In step S307 , it is determined whether corresponding target valley voltages have been determined for all the read voltage levels included in the page.

[0277] When the judgment result of step 307 is yes, it means that the target valley voltages corresponding to all the levels of read voltages included in the page have been determined, and step S309 can be executed at this time; when the judgment result of step S307 is no, it means that there are still undetermined levels of target valley voltages corresponding to all the levels of read voltages included in the page, and step S308 is executed at this time.

[0278] In step S308, for the steps for which the target valley voltage has not been determined, the target valley voltage of each step is determined in sequence. Step S308 jumps to step S303.

[0279] In step S309 , the process of obtaining the target valley voltage is terminated. It should be noted that after step S309 , the target valley voltages corresponding to the read voltages of all steps of the next page can be determined.

[0280] In some embodiments, the memory controller 106 is configured to: send a mode setting command, the mode setting command instructing to set the read mode of the memory device to a single-level read mode; the single-level read mode includes reading at least one bit of storage data stored in the memory cell using a first-level read voltage; and the memory device 104 is configured to: enter the single-level read mode in response to the mode setting command, and, in the single-level read mode, obtain a first result corresponding to at least one codeword at a target read voltage.

[0281] Secondly, in the memory system provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; the process of obtaining the target valley voltage according to the first result and obtaining the predicted valley voltage of the second target level according to the target valley voltage of the first target level in the memory device reduces the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller, saves the iteration time of the error correction decoding algorithm of the memory controller, and the error correction decoding speed is faster; it is suitable for MLC, TLC or QLC type memory systems.

[0282] In a third aspect, an embodiment of the present application provides a memory controller coupled to at least one memory device, the memory device including a memory cell having a plurality of storage bits; a preset number of memory cells form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, the plurality of stages including a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the memory controller includes: a control unit configured to: obtain a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to a plurality of pages in the memory device; the valley voltage is used as a read voltage for at least one codeword when performing a read operation; and obtain a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage; the second target stage includes the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0283] In some embodiments, the control unit is configured to: obtain a target valley voltage of a first stage of each of the plurality of pages; and obtain a predicted valley voltage of a second stage belonging to the same page as the first stage based on the target valley voltage of the first stage in each page.

[0284] In some embodiments, each page in the multiple pages includes multiple second stages; the control unit is configured to: obtain the predicted valley voltage of the second stage with the largest read voltage among the multiple second stages belonging to the same page as the first stage based on the target valley voltage of the first stage of each page in the multiple pages; and obtain the predicted valley voltage of the second stage with the smaller read voltage in the adjacent sequence based on the predicted valley voltage of the second stage with the larger read voltage among the multiple second stages belonging to the same page as the first stage, until the predicted valley voltages of all the second stages belonging to the same page as the first stage are obtained.

[0285] In some embodiments, the control unit is configured to: obtain the predicted valley voltage of the second target step based on the target valley voltage of the first target step and a mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the first target step and the predicted valley voltage of the second target step.

[0286] In some embodiments, the control unit is configured to obtain the predicted valley voltage of the second target order based on the target valley voltage of the first target order, the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient in the mapping function; wherein the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

[0287] In some embodiments, the control unit is configured to: obtain, for a first target level, a first result corresponding to at least one codeword at a target read voltage; the first result includes a representation of the number of bits flipped in two read results of the at least one codeword at the first read voltage and the second read voltage; the difference between the first read voltage and the second read voltage is less than a preset voltage; and adjust the target read voltage at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; and determine the target valley voltage of the first target level based on the multiple first results.

[0288] In some embodiments, the control unit is configured to: obtain a first result corresponding to at least one codeword under a target read voltage for a second target level; and obtain a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target level is less than the first threshold value, determine that the predicted valley voltage of the second target level is the target valley voltage of the second target level.

[0289] In some embodiments, the control unit is configured to: when the first result corresponding to the predicted valley voltage of the second target level is greater than or equal to a first threshold, adjust the predicted valley voltage of the second target level at least once, and obtain the first result corresponding to the adjusted target read voltage after each adjustment; determine the target valley voltage of the second target level based on multiple first results.

[0290] In some embodiments, the control unit is configured to: when the first result corresponding to the predicted valley voltage of the second target order is greater than or equal to a first threshold, obtain the predicted valley voltage of the second target order based on the target valley voltage of the first target order and the backup adjustment coefficient of the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the first target order and the predicted valley voltage of the second target order.

[0291] In some embodiments, the memory device is a memory device after data retention.

[0292] In some embodiments, the data volume of the first result is less than a preset data volume threshold.

[0293] On the third aspect, in the memory system provided by the embodiment of the present application, the first result (the size of the first result can be several bytes) is transmitted without transmitting at least one codeword (for example, the size of the codeword can be 4KB), and the amount of data transmitted between the memory device and the memory controller is reduced; the process of obtaining the first result converges inside the memory device, does not occupy the space of the memory controller, and has a low degree of dependence on the memory controller; compared with in the memory device, the process of obtaining the target valley voltage according to the first result and obtaining the predicted valley voltage of the second target level according to the target valley voltage of the first target level in the memory controller is more efficient, reducing the transmission time of the input and output ports of the memory device and / or the time of the error correction decoding operation of the memory controller, saving the iteration time of the error correction decoding algorithm of the memory controller, and making the error correction decoding faster; it is suitable for MLC, TLC or QLC type memory systems.

[0294] In a fourth aspect, an embodiment of the present application provides an operating method for a memory device, wherein the memory device includes a memory cell having a plurality of storage bits; a preset number of memory cells forms a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, the plurality of stages include a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the operating method includes: obtaining a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to the plurality of pages; the target valley voltage is used as a read voltage for at least one codeword when performing a read operation; and obtaining a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage, the second target stage including the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0295] In some embodiments, a method for operating a memory device includes: obtaining a valley voltage of a first stage of each of a plurality of pages; and obtaining a predicted valley voltage of a second stage belonging to the same page as the first stage based on a target valley voltage of the first stage in each page.

[0296] In some embodiments, each of the multiple pages includes multiple second stages; the operating method of the memory device includes: obtaining a predicted valley voltage of the second stage with the largest read voltage among the multiple second stages belonging to the same page as the first stage based on the target valley voltage of the first stage of each page in the multiple pages; and sequentially obtaining predicted valley voltages of the second stages with smaller read voltages adjacent to the first stage based on the predicted valley voltage of the second stage with larger read voltage among the multiple second stages belonging to the same page as the first stage, until the predicted valley voltages of all the second stages belonging to the same page as the first stage are obtained.

[0297] In some embodiments, a memory cell has three storage bits, the three storage bits corresponding to a lower page, a middle page, and an upper page, respectively; the multi-level includes first to seventh levels with increasing read voltages; the fifth to seventh levels in the multi-level include the first levels of the lower page, the middle page, and the upper page, respectively; the first level is the second level of the lower page; the second level in the multi-level and the fourth level in the multi-level are the second level of the middle page; and the third level in the multi-level includes the second level of the upper page; and a method for operating a memory device includes:

[0298] According to the target valley voltage of the fifth stage of the lower page, the predicted valley voltage of the first stage of the lower page is obtained; according to the target valley voltage of the sixth stage of the middle page, the predicted valley voltage of the fourth stage of the middle page is obtained; and according to the predicted valley voltage of the fourth stage of the middle page, the predicted valley voltage of the second stage of the middle page is obtained; and according to the target valley voltage of the seventh stage of the upper page, the predicted valley voltage of the third stage of the upper page is obtained.

[0299] In some embodiments, a method for operating a memory device includes obtaining a predicted valley voltage of a second target level based on a target valley voltage of a first target level and a mapping function, wherein the mapping function is used to characterize a relationship between the target valley voltage of the first target level and the predicted valley voltage of the second target level.

[0300] In some embodiments, a method for operating a memory device includes obtaining a predicted valley voltage of a second target level based on a target valley voltage of a first target level, a first adjustment coefficient, a second adjustment coefficient, and a third adjustment coefficient in a mapping function; wherein the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

[0301] In some embodiments, a method for operating a memory device includes: obtaining, for a first target level, a first result corresponding to at least one codeword at a target read voltage; the first result including a number of bits flipped in two read results representing the at least one codeword at the first read voltage and at a second read voltage; the difference between the first read voltage and the second read voltage being less than a preset voltage; and adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; and determining a target valley voltage for the first target level based on the multiple first results.

[0302] In some embodiments, a method for operating a memory device includes: obtaining, for a second target level, a first result corresponding to at least one codeword at a target read voltage; and obtaining a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target level is less than the first threshold value, determining that the predicted valley voltage of the second target level is the target valley voltage of the second target level.

[0303] In some embodiments, a method for operating a memory device includes: when a first result corresponding to a predicted valley voltage of a second target level is greater than or equal to a first threshold, adjusting the predicted read voltage of the second target level at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; and determining a target valley voltage of the second target level based on the multiple first results.

[0304] In some embodiments, a method for operating a memory device includes: when a first result corresponding to a predicted valley voltage of a second target level is greater than or equal to a first threshold, obtaining the predicted valley voltage of the second target level based on a target valley voltage of the first target level and a backup adjustment coefficient of a mapping function, wherein the mapping function is used to characterize a relationship between the target valley voltage of the first target level and the predicted valley voltage of the second target level.

[0305] In a fifth aspect, an embodiment of the present application provides an operating method for a memory system, comprising: sending a data acquisition instruction, the data acquisition instruction instructing to obtain a target valley voltage; the target valley voltage is obtained according to the operating method described in any embodiment of the fourth aspect; and performing a read operation on data stored in the memory device according to the target valley voltage.

[0306] In some specific embodiments, a memory device in a memory system includes a memory cell having a plurality of storage bits; a preset number of memory cells form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of levels, the plurality of levels include a first level and a second level, and a read voltage of the second level is less than a read voltage of the first level; an operating method of the memory system includes: obtaining a target valley voltage of a first target level, the first target level including at least one first level among a plurality of first levels corresponding to a plurality of pages in the memory device; the valley voltage is used as a read voltage when performing a read operation on at least one codeword; and obtaining a predicted valley voltage of a second target level based on the target valley voltage of the first target level; the second target level includes the remaining first levels and / or second levels; the read voltage of the second target level is less than the read voltage of the first target level.

[0307] In a sixth aspect, an embodiment of the present application provides an operating method of a memory controller, which is coupled to at least one memory device, and the memory device includes a storage unit with a plurality of storage bits; a preset number of storage units form a codeword, and the plurality of storage bits correspond to a plurality of pages respectively; at least one page corresponds to a plurality of stages, and the plurality of stages include a first stage and a second stage, and a read voltage of the second stage is less than a read voltage of the first stage; the operating method of the memory controller of the memory device includes: obtaining a target valley voltage of a first target stage, the first target stage including at least one first stage among a plurality of first stages corresponding to a plurality of pages in the memory device; the target valley voltage is used as a read voltage for at least one codeword when performing a read operation; and obtaining a predicted valley voltage of a second target stage based on the target valley voltage of the first target stage; the second target stage includes the remaining first stages and / or second stages; the read voltage of the second target stage is less than the read voltage of the first target stage.

[0308] In some embodiments, a method for operating a memory controller of a memory device includes: obtaining a target valley voltage of a first stage of each of a plurality of pages; and obtaining a predicted valley voltage of a second stage belonging to the same page as the first stage based on the target valley voltage of the first stage in each page.

[0309] In some embodiments, each of the multiple pages includes multiple second stages; the operating method of the memory controller of the memory device includes: obtaining a predicted valley voltage of the second stage with the largest read voltage among the multiple second stages belonging to the same page as the first stage based on the target valley voltage of the first stage of each page in the multiple pages; and sequentially obtaining the predicted valley voltages of the second stages with smaller read voltages adjacent to the second stage with the larger read voltage among the multiple second stages belonging to the same page as the first stage based on the predicted valley voltage of the second stage with the larger read voltage, until the predicted valley voltages of all the second stages belonging to the same page as the first stage are obtained.

[0310] In some embodiments, a method for operating a memory controller of a memory device includes obtaining a predicted valley voltage of a second target step based on a target valley voltage of a first target step and a mapping function, wherein the mapping function is used to characterize a relationship between the target valley voltage of the first target step and the predicted valley voltage of the second target step.

[0311] In some embodiments, a method for operating a memory controller of a memory device includes obtaining a predicted valley voltage of a second target level based on a target valley voltage of a first target level, a first adjustment coefficient, a second adjustment coefficient, and a third adjustment coefficient in a mapping function; wherein the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

[0312] In some embodiments, a method for operating a memory controller of a memory device includes: obtaining, for a first target level, a first result corresponding to at least one codeword at a target read voltage; the first result including a number of bits flipped in two read results representing the at least one codeword at the first read voltage and at a second read voltage; a difference between the first read voltage and the second read voltage being less than a preset voltage; and adjusting the target read voltage at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; and determining a target valley voltage for the first target level based on the multiple first results.

[0313] In some embodiments, an operating method of a memory controller of a memory device includes: obtaining a first result corresponding to at least one codeword at a target read voltage for a second target level; and obtaining a first threshold value based on the first result corresponding to the target read voltage; the first threshold value is used to characterize the first result corresponding to the upper limit of the predicted valley voltage; when the first result corresponding to the predicted valley voltage of the second target level is less than the first threshold value, determining that the predicted valley voltage of the second target level is the target valley voltage of the second target level.

[0314] In some embodiments, a method for operating a memory controller of a memory device includes: when a first result corresponding to a predicted valley voltage of a second target level is greater than or equal to a first threshold, adjusting the predicted valley voltage of the second target level at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; and determining a target valley voltage of the second target level based on the multiple first results.

[0315] In some embodiments, a method for operating a memory controller of a memory device includes: when a first result corresponding to a predicted valley voltage of a second target level is greater than or equal to a first threshold, obtaining the predicted valley voltage of the second target level based on a target valley voltage of the first target level and a backup adjustment coefficient of a mapping function, wherein the mapping function is used to characterize a relationship between the target valley voltage of the first target level and the predicted valley voltage of the second target level.

[0316] In some embodiments, the memory device is a memory device after data retention.

[0317] In some embodiments, the data volume of the first result is less than a preset data volume threshold.

[0318] Figure 16 is an exemplary timing diagram for starting a single-stage read mode operation provided by the present application. DQx can be represented as a data bus signal, and Cycle Type can further represent the type of the data bus signal.

[0319] As shown in FIG16 , the set function command may include, for example, a sub-command (e.g., EFh). Exemplarily, the memory device starts the single-level read mode upon receiving a sub-command EFh. In the single-level read mode, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. During the read time, the data DATA (e.g., Dn) corresponding to the page of the received address may be cached in the page buffer first, and then the data DATA may be read on demand. It should be noted that, in the above embodiment, when performing a reread operation, the data corresponding to a physical page (e.g., Dn) needs to be frequently transmitted (Din / Dout) between the memory device and the memory controller, and the transmission of the data takes a long time.

[0320] Figure 17 is a timing diagram for determining valley voltage and performing a read operation according to an embodiment of the present application. As shown in Figure 17, a read command may include, for example, two sub-commands (e.g., 00h and 30h). For example, the memory device transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received sub-commands 00h and 30h. After the memory device receives sub-command 30h, it may first cache the corresponding data DATA (e.g., Dn) in the page of the received address in the page buffer within the read time, and then read the data DATA on demand.

[0321] In an exemplary embodiment, the memory device 104 transmits the address ADDR of the data to be read (e.g., two column addresses C1-C2 and three row addresses R1-R3) between the received subcommands 00h and 30h. After receiving subcommand 30h, the memory device 104 receives subcommands EFh and xxh of the data acquisition instruction. Under the instruction of the data acquisition instruction, the memory device 104 acquires the first result corresponding to the codeword at the corresponding read voltage and sends the acquired first result to the memory controller. The memory controller determines a target valley voltage based on the multiple first results corresponding to the multiple different read voltages received from the memory device and performs a read operation on the data stored in the memory device according to the target valley voltage.

[0322] It should be noted that the data acquisition instruction provided in the embodiment of the present application is only an example and should not unduly limit the scope of protection of the present application.

[0323] In some embodiments, the data volume of the first result is less than a preset data volume threshold, for example, the data volume of the first result ranges from 1 byte to 4 bytes. Therefore, in the process of determining the target valley voltage, the amount of data transmitted between the memory device and the memory controller is small and the speed is fast, which is conducive to improving the overall speed of the read operation.

[0324] An embodiment of the present application further provides a storage medium having executable instructions stored thereon. When the executable instructions are executed, the steps of the operating method in the above embodiment of the present application can be implemented.

[0325] In some specific embodiments, the storage medium can be a memory such as Ferromagnetic Random Access Memory (FRAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Flash Memory, magnetic surface storage, an optical disc, or a Compact Disc Read-Only Memory (CD-ROM); it can also be various devices including one or any combination of the above memory devices.

[0326] In some embodiments, executable instructions may be in the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0327] As an example, executable instructions may, but need not, correspond to a file in a file system, may be stored as part of a file that stores other programs or data, e.g., in one or more scripts in a HyperText Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple coordinating files (e.g., files storing one or more modules, subroutines, or code portions).

[0328] As an example, executable instructions may be deployed to be executed on one electronic device, or on multiple electronic devices located at one site, or on multiple electronic devices distributed across multiple sites and interconnected by a communication network.

[0329] In some specific embodiments, referring to Figure 18, Figure 18 is a schematic diagram of the composition structure of a storage medium provided in an embodiment of the present application; wherein, the storage medium includes a first storage medium corresponding to the memory device 104, a second storage medium corresponding to the memory controller 104, and a third storage medium corresponding to the memory system 102; when the executable instruction is executed by the memory device, the first storage medium can be used to implement the steps of the operating method of the memory device described in the above embodiment of the present application; when the executable instruction is executed by the memory controller, the second storage medium can be used to implement the steps of the operating method of the memory controller described in the above embodiment of the present application; when the executable instruction is executed by the memory system, the third storage medium can be used to implement the steps of the operating method of the memory system described in the above embodiment of the present application.

[0330] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0331] The above description is only a preferred embodiment of the present application and does not limit the patent scope of the present application. All equivalent structural transformations made using the contents of the present application description and drawings under the inventive concept of the present application, or direct / indirect application in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A memory device comprising: A memory cell array including memory cells having a plurality of storage bits; A preset number of storage units form a codeword, and a plurality of storage bits correspond to a plurality of pages respectively; At least one page corresponds to a plurality of levels, the plurality of levels including a first level and a second level, a read voltage of the second level being lower than a read voltage of the first level; A peripheral circuit is coupled to the memory cell array and is configured to: Obtaining a target valley voltage of a first target step, the first target step including at least one first step among a plurality of first steps corresponding to the plurality of pages; the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; and According to the target valley voltage of the first target step, a predicted valley voltage of a second target step is obtained, where the second target step includes the remaining first steps and / or second steps; and a read voltage of the second target step is lower than a read voltage of the first target step.

2. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: obtaining a target valley voltage of a first stage of each of the plurality of pages; and According to the target valley voltage of the first stage in each page, a predicted valley voltage of the second stage belonging to the same page as the first stage is obtained.

3. The memory device according to claim 2, wherein Each of the plurality of pages comprises a plurality of second stages; The peripheral circuit is configured as follows: Obtaining, according to a target valley voltage of the first stage of each of the plurality of pages, a predicted valley voltage of a second stage having a maximum read voltage among a plurality of second stages belonging to the same page as the first stage; and The predicted valley bottom voltage of the second stage with a larger read voltage among the multiple second stages belonging to the same page as the first stage is obtained in sequence, and the predicted valley bottom voltage of the second stage with a smaller read voltage in the adjacent sequence is obtained until the predicted valley bottom voltage of all the second stages belonging to the same page as the first stage is obtained.

4. The memory device according to claim 3, wherein The number of storage bits of the memory cell is three, and the three storage bits correspond to a lower page, a middle page, and an upper page respectively; the multi-level includes a first-level reading voltage to a seventh-level reading voltage with increasing reading voltages; the fifth to seventh-level reading voltages in the multi-level include the first levels of the lower page, the middle page, and the upper page respectively, the first-level reading voltage is the second level of the lower page, the second-level reading voltage in the multi-level and the fourth-level reading voltage in the multi-level are the second level of the middle page, and the third-level reading voltage in the multi-level is the second level of the upper page; The peripheral circuit is configured as follows: Obtaining a predicted valley voltage of the first level read voltage of the lower page according to a target valley voltage of the fifth level read voltage of the lower page; Obtaining a predicted valley voltage of the fourth level read voltage of the middle page according to a target valley voltage of the sixth level read voltage of the middle page; and obtaining a predicted valley voltage of the second level read voltage of the middle page according to the predicted valley voltage of the fourth level read voltage of the middle page; and According to the target valley voltage of the seventh level read voltage of the upper page, a predicted valley voltage of the third level read voltage of the upper page is obtained.

5. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: The predicted valley voltage of the second target step is obtained according to the target valley voltage of the first target step and a mapping function, wherein the mapping function is used to characterize the relationship between the target valley voltage of the first target step and the predicted valley voltage of the second target step. The memory device according to claim 5 , wherein: The peripheral circuit is configured as follows: Obtaining a predicted valley voltage of the second target step according to the target valley voltage of the first target step, the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient in the mapping function; The first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

7. The memory device according to claim 1, wherein The peripheral circuit is configured as follows: For the first target level, obtaining a first result corresponding to at least one of the codewords at a target read voltage; the first result includes a number of bits flipped in the at least one codeword read at the first read voltage and at the second read voltage; and a difference between the first read voltage and the second read voltage is less than a preset voltage; and The target read voltage is adjusted at least once, and the adjusted voltage is obtained after each adjustment. The first result corresponding to the target read voltage; A target valley voltage of the first target step is determined according to the plurality of first results.

8. The memory device according to claim 7, wherein The peripheral circuit is configured as follows: For the second target level, obtaining a first result corresponding to at least one of the codewords at a target read voltage; and obtaining a first threshold value according to a first result corresponding to the target reading voltage; The first threshold is used to represent a first result corresponding to the upper limit of the predicted valley voltage; When the first result corresponding to the predicted valley voltage of the second target step is less than the first threshold, the predicted valley voltage of the second target step is determined as the target valley voltage of the second target step.

9. The memory device according to claim 8, wherein The peripheral circuit is configured as follows: When the first result corresponding to the predicted valley voltage of the second target step is greater than or equal to the first threshold, adjusting the predicted read voltage of the second target step at least once, and obtaining the first result corresponding to the adjusted target read voltage after each adjustment; A target valley voltage of the second target step is determined according to the plurality of first results.

10. The memory device according to claim 8, wherein The peripheral circuit is configured as follows: When the first result corresponding to the predicted valley voltage of the second target order is greater than or equal to the first threshold, the predicted valley voltage of the second target order is obtained based on the target valley voltage of the first target order and the backup adjustment coefficient of the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the first target order and the predicted valley voltage of the second target order.

11. The memory device according to claim 1, wherein The memory device is a memory device after data retention.

12. A memory system comprising: One or more memory devices according to any one of claims 1 to 11; as well as A memory controller is coupled to the memory device and controls the memory device.

13. The memory system according to claim 12, wherein: The memory controller is configured to: send a data acquisition instruction, wherein the data acquisition instruction instructs acquisition of a target valley voltage; The memory device is configured to: receive the data acquisition instruction, acquire a target valley voltage, and send information including the target valley voltage to the memory controller; The memory controller is further configured to perform a read operation on data stored in the memory device according to the target valley voltage in the information.

14. The memory system according to claim 13, wherein: The memory controller is further configured to perform an error correction code decoding operation on a read result of the read operation.

15. A memory controller coupled to at least one memory device, the memory device comprising a plurality of memory cells each storing a plurality of bits; a predetermined number of the memory cells forming a codeword, the plurality of memory bits corresponding to a plurality of pages; At least one page corresponds to multiple levels, the multiple levels including a first level and a second level, a read voltage of the second level being lower than a read voltage of the first level; the memory controller includes: The control unit is configured to: Obtaining a target valley voltage of a first target level, the first target level including at least one first level among a plurality of first levels corresponding to a plurality of pages in a memory device; the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; and According to the target valley voltage of the first target step, a predicted valley voltage of the second target step is obtained; the second target step includes the remaining first steps and / or second steps; and the read voltage of the second target step is less than the read voltage of the first target step.

16. The memory controller according to claim 15, wherein: The control unit is configured to: obtaining a target valley voltage of a first stage of each of the plurality of pages; and According to the target valley voltage of the first stage in each page, a predicted valley voltage of the second stage belonging to the same page as the first stage is obtained.

17. The memory controller according to claim 16, wherein: Each of the plurality of pages includes a plurality of second stages; the control unit is configured to: Obtaining, according to a target valley voltage of the first stage of each of the plurality of pages, a predicted valley voltage of a second stage having a maximum read voltage among a plurality of second stages belonging to the same page as the first stage; and The predicted valley bottom voltage of the second stage with a larger read voltage among the multiple second stages belonging to the same page as the first stage is obtained in sequence, and the predicted valley bottom voltage of the second stage with a smaller read voltage in the adjacent sequence is obtained until the predicted valley bottom voltage of all the second stages belonging to the same page as the first stage is obtained.

18. The memory controller according to claim 15, wherein: The control unit is configured to: The predicted valley voltage of the second target step is obtained according to the target valley voltage of the first target step and a mapping function, wherein the mapping function is used to characterize the relationship between the target valley voltage of the first target step and the predicted valley voltage of the second target step.

19. The memory controller according to claim 18, wherein: The control unit is configured to: Obtaining a predicted valley voltage of the second target step according to the target valley voltage of the first target step, the first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient in the mapping function; The first adjustment coefficient, the second adjustment coefficient, and the third adjustment coefficient are all fixed values ​​related to the order of the read voltage.

20. The memory controller according to claim 15, wherein The control unit is configured to: For the first target level, obtaining a first result corresponding to at least one of the codewords at a target read voltage; the first result includes a number of bits flipped in the at least one codeword read at the first read voltage and at the second read voltage; and a difference between the first read voltage and the second read voltage is less than a preset voltage; and Adjusting the target read voltage at least once, and obtaining a first result corresponding to the adjusted target read voltage after each adjustment; A target valley voltage of the first target step is determined according to the plurality of first results.

21. The memory controller according to claim 20, wherein: The control unit is configured to: For the second target level, obtaining a first result corresponding to at least one of the codewords at a target read voltage; and obtaining a first threshold value according to a first result corresponding to the target reading voltage; The first threshold is used to represent a first result corresponding to the upper limit of the predicted valley voltage; When the first result corresponding to the predicted valley voltage of the second target step is less than the first threshold, the predicted valley voltage of the second target step is determined as the target valley voltage of the second target step.

22. The memory controller according to claim 21, wherein: The control unit is configured to: When the first result corresponding to the predicted valley voltage of the second target step is greater than or equal to the first threshold, adjusting the predicted valley voltage reading voltage of the second target step at least once, and obtaining the first result corresponding to the adjusted target reading voltage after each adjustment; A target valley voltage of the second target step is determined according to the plurality of first results.

23. The memory controller according to claim 21, wherein: The control unit is configured to: When the first result corresponding to the predicted valley voltage of the second target order is greater than or equal to the first threshold, the predicted valley voltage of the second target order is obtained based on the valley voltage of the first target order and the backup adjustment coefficient of the mapping function, and the mapping function is used to characterize the relationship between the target valley voltage of the first target order and the predicted valley voltage of the second target order.

24. The memory controller according to claim 15, wherein: The memory device is a memory device after data retention.

25. The memory controller according to claim 21, wherein The data volume of the first result is less than a preset data volume threshold.

26. A method for operating a memory device, the memory device comprising a plurality of storage units each having a plurality of storage bits; a predetermined number of the storage units forming a codeword, wherein the plurality of storage bits correspond to a plurality of pages; At least one page corresponds to multiple levels, the multiple levels include a first level and a second level, a read voltage of the second level is lower than a read voltage of the first level; the operating method includes: Obtaining a target valley voltage of a first target step, the first target step including at least one first step among the plurality of first steps corresponding to the plurality of pages; the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; and According to the target valley voltage of the first target step, a predicted valley voltage of a second target step is obtained, where the second target step includes the remaining first steps and / or second steps; and a read voltage of the second target step is lower than a read voltage of the first target step.

27. A method for operating a memory system, comprising: Sending a data acquisition instruction, wherein the data acquisition instruction instructs obtaining a target valley voltage; The target valley voltage is Obtained by the operating method according to claim 26; A read operation is performed on data stored in the memory device according to the target valley voltage.

28. A method for operating a memory controller, the memory controller being coupled to at least one memory device, the memory device comprising a plurality of memory cells each storing a plurality of bits; a predetermined number of the memory cells forming a codeword, the plurality of memory bits corresponding to a plurality of pages; At least one page corresponds to multiple levels, the multiple levels include a first level and a second level, a read voltage of the second level is lower than a read voltage of the first level; the operating method includes: Obtaining a target valley voltage of a first target level, the first target level including at least one first level among a plurality of first levels corresponding to a plurality of pages in a memory device; the target valley voltage being used as a read voltage when performing a read operation on at least one of the codewords; and According to the target valley voltage of the first target step, a predicted valley voltage of the second target step is obtained; the second target step includes the remaining first steps and / or second steps; and the read voltage of the second target step is less than the read voltage of the first target step.

29. A storage medium having executable instructions stored thereon, wherein when the executable instructions are executed, the steps of the operating method according to any one of claims 26 to 28 can be implemented.

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