Liquid crystal display panel and display device

Abstract

A liquid crystal display panel. The liquid crystal display panel comprises a first sub-display area and a second sub-display area adjacent to each other. The display panel comprises an array substrate and a counter substrate arranged opposite each other. The array substrate comprises a plurality of pixel units, wherein the plurality of pixel units comprise a first pixel unit located in the first sub-display area and a second pixel unit located in the second sub-display area. A first signal line comprises a first line segment and a second line segment, wherein the first line segment is electrically connected to the first pixel unit, and the second line segment is electrically connected to the second pixel unit. A common electrode layer comprises a first common electrode located in the first sub-display area and a second common electrode located in the second sub-display area, and a first slit extending in a second direction is provided between the first common electrode and the second common electrode. The counter substrate comprises a light-shielding layer, wherein the light-shielding layer comprises a first light-shielding portion, and the orthographic projection of the first light-shielding portion on a first base at least partially overlaps the orthographic projection of the first slit on the first base.

Description

Liquid crystal display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a liquid crystal display panel and display device. BACKGROUND

[0002] At present, liquid crystal display devices (English full name: Liquid Crystal Display, English abbreviation: LCD) have been widely used in mobile phones, computers and other electronic products.

[0003] SUMMARY

[0004] In one aspect, a liquid crystal display panel is provided. The liquid crystal display panel has a display area, along a first direction, the display area includes adjacent first and second sub-display areas. The display panel includes an array substrate, a counter substrate and a liquid crystal layer disposed between the array substrate and the counter substrate. The array substrate includes a first substrate, a plurality of pixel units on the first substrate, a plurality of first signal lines extending along the first direction and a common electrode layer. The pixel units include at least one sub-pixel region, the plurality of pixel units include first pixel units in the first sub-display area and second pixel units in the second sub-display area. The first signal lines include first and second line segments, the first line segment is electrically connected to the first pixel units, and the second line segment is electrically connected to the second pixel units. The common electrode layer includes first and second common electrodes, the first common electrode is located in the first sub-display area, the second common electrode is located in the second sub-display area, and the first and second common electrodes have a first gap extending along a second direction therebetween. The first and second directions intersect. The counter substrate includes a light shielding layer, the light shielding layer includes a first light shielding portion, a projection of the first light shielding portion on the first substrate at least partially overlaps a projection of the first gap on the first substrate.

[0005] In some embodiments, the projection of the first light shielding portion on the first substrate covers the projection of the first gap on the first substrate.

[0006] In some embodiments, the array substrate further includes a plurality of second signal lines, the plurality of second signal lines extend along the second direction and are arranged along the first direction. One of the second signal lines is located on a side of a column of the sub-pixel regions, which is away from a first reference line, where the first reference line is an intersection line of the first and second sub-display areas.

[0007] In some embodiments, the sub-pixel region comprises a driving transistor and a pixel electrode, a control electrode of the driving transistor is electrically connected with the first signal line, a first electrode of the driving transistor is electrically connected with the pixel electrode, and a second electrode of the driving transistor is electrically connected with the second signal line. The sub-pixel region in the first pixel unit is a first sub-pixel region, and the sub-pixel region in the second pixel unit is a second sub-pixel region. In the first sub-pixel region and the second sub-pixel region arranged along the first direction: the driving transistor in the first sub-pixel region and the driving transistor in the second sub-pixel region are mirror-symmetrical with respect to a second reference line. The second reference line is a center line of a line connecting the first sub-pixel region and the second sub-pixel region.

[0008] In some embodiments, the pixel electrode is a dual-domain pixel electrode, the dual-domain pixel electrode comprises a first domain and a second domain, and the first domain and the second domain are cross in extension direction. A corner formed by the first domain and the second domain of the pixel electrode in any of the first sub-pixel region is a first corner, and a corner formed by the first domain and the second domain of the pixel electrode in any of the second sub-pixel region is a second corner. The first corner and the second corner protrude towards one direction.

[0009] In some embodiments, the array substrate further comprises a gate metal layer, an active layer, a source-drain metal layer and the pixel electrode layer which are arranged in a stack on the first substrate. The pixel electrode layer comprises a plurality of the pixel electrodes, the common electrode layer is between the source-drain metal layer and the pixel electrode layer, the common electrode layer comprises a plurality of via holes, and a footprint of the pixel electrode on the common electrode layer covers the via holes. The gate metal layer comprises the first signal line, along the first direction, the first signal line comprises a first part and a second part, the first part is multiplexed as the control electrode of the driving transistor, and a footprint of the via hole on the first substrate is between footprints of the first part and the second part on the first substrate. The source-drain metal layer comprises the second signal line, the second signal line comprises a first sub-portion, the first sub-portion of the second signal line is multiplexed as the second electrode of the driving transistor, the source-drain metal layer further comprises a first conductive portion, the first conductive portion comprises a third part and a fourth part, the third part is multiplexed as the first electrode of the driving transistor, and a footprint of the via hole on the first substrate is between footprints of the third part and the fourth part on the first substrate. The second part of the first signal line on the first substrate at least partially overlaps with the fourth part of the first conductive portion on the first substrate.

[0010] In some embodiments, a projection of the fourth portion of the first conductive part on the first substrate is located within a boundary of a projection of the second portion of the first signal line on the first substrate.

[0011] In some embodiments, a length of the fourth portion of the first conductive part in the first direction is greater than or equal to 2 μm.

[0012] In some embodiments, the light shielding layer further comprises a plurality of second light shielding parts, a projection of the second signal line on the first substrate is located within a boundary of a projection of the second light shielding parts on the first substrate. A width of the first light shielding part in the first direction is W1, a width of the second light shielding part in the first direction is W2, and W1≤1.5W2.

[0013] In some embodiments, the liquid crystal display panel further comprises a plurality of support parts between the array substrate and the counter substrate. The plurality of support parts comprises first support parts and second support parts. The sub-pixel region comprises a drive transistor. A projection of the first support part on the first substrate at least partially overlaps a projection of the drive transistor on the first substrate. A projection of the second support part on the first substrate is located within a projection of the first gap on the first substrate. The second support part and the plurality of first support parts are arranged in the first direction. A distance between two adjacent first support parts in the first direction is d1, a distance between the first support part and the second support part in the first direction is d2, and |d2-d1|≤0.1d1.

[0014] In some embodiments, the pixel unit comprises a plurality of sub-pixel regions. The array substrate further comprises a gate metal layer, an active layer, a source-drain metal layer, and a first metal layer stacked on the first substrate. The first metal layer is between the source-drain metal layer and the common electrode layer. The first metal layer comprises a plurality of first traces. A projection of one of the first traces on the first substrate is between projections of any two adjacent sub-pixel regions of one of the pixel units on the first substrate.

[0015] In some embodiments, the sub-pixel region comprises a drive transistor. A projection of the first trace on the first substrate does not overlap a projection of the drive transistor on the first substrate.

[0016] In some embodiments, the array substrate further comprises a plurality of second signal lines extending in the second direction and arranged in the first direction. A projection of the first trace on the first substrate at least partially overlaps a projection of the second signal line on the first substrate.

[0017] In some embodiments, the light-shielding layer further comprises a plurality of second light-shielding portions, and a projection of the first trace on the first substrate is located within a boundary of a projection of the second light-shielding portion on the first substrate.

[0018] In some embodiments, the array substrate further comprises an organic layer, and the organic layer is located between the source-drain metal layer and the first metal layer. A thickness of the organic layer ranges from 0.1 μm to 1 μm.

[0019] In some embodiments, the liquid crystal display panel is a special-shaped liquid crystal display panel, and at least two of the first traces have different lengths along the second direction. In the at least two of the first traces, a first one of the first traces has a length greater than a length of a second one of the first traces, and a line width of the first one of the first traces is greater than a line width of the second one of the first traces.

[0020] In some embodiments, in the first sub-display region or the second sub-display region, a plurality of the first traces arranged along a direction close to a first reference line have gradually increasing lengths and gradually increasing widths. The first reference line is a boundary between the first sub-display region and the second sub-display region.

[0021] In some embodiments, the array substrate further comprises an auxiliary electrode layer, and the auxiliary electrode layer is located on a side of the common electrode layer away from the first substrate. The auxiliary electrode layer and the common electrode layer are in contact.

[0022] In some embodiments, the light-shielding layer further comprises a plurality of second light-shielding portions, and the auxiliary electrode layer comprises a plurality of auxiliary electrodes. A projection of the auxiliary electrode on the first substrate is located within a boundary of a projection of the second light-shielding portion on the first substrate.

[0023] In another aspect, a display device is provided. The display device comprises a cover plate and a liquid crystal display panel as described in any of the above embodiments. The cover plate is located on a light-emitting side of the liquid crystal display panel. BRIEF DESCRIPTION OF DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only the drawings of some embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings described in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual time sequence, etc. of the products involved in the embodiments of the present disclosure.

[0025] Fig. 1 is a schematic diagram of a display device according to some embodiments;

[0026] Fig. 2 is a plan view of a display panel according to some embodiments;

[0027] Fig. 3 is a sectional view of the display panel according to some embodiments;

[0028] Fig. 4 is a structural diagram of the display panel according to some embodiments;

[0029] Fig. 5 is a layout diagram of the display panel of Fig. 4;

[0030] Fig. 6 is a structural diagram of a display panel according to other embodiments;

[0031] Fig. 7 is a layout diagram of the display panel of Fig. 6;

[0032] Fig. 8 is a sectional view of the direction of M1-M1' in Fig. 7;

[0033] Fig. 9 is a stacked structure diagram of the gate metal layer, the active layer and the source-drain metal layer in Fig. 7;

[0034] Fig. 10 is a stacked structure diagram of the gate metal layer, the active layer, the source-drain metal layer and the common electrode layer in Fig. 7;

[0035] Fig. 11 is a stacked structure diagram of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in Fig. 7;

[0036] Fig. 12 is a structural diagram of the light shielding layer in Fig. 7;

[0037] Fig. 13 is another layout diagram of the display panel of Fig. 6;

[0038] Fig. 14 is a sectional view of the direction of M2-M2' in Fig. 13;

[0039] Fig. 15 is a stacked structure diagram of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in Fig. 13;

[0040] Fig. 16 is a structural diagram of the light shielding layer in Fig. 13;

[0041] Fig. 17 is yet another layout diagram of the display panel of Fig. 6;

[0042] Fig. 18 is a sectional view of the direction of M3-M3' in Fig. 17;

[0043] Fig. 19 is a stacked structure diagram of the gate metal layer and the active layer in Fig. 17;

[0044] Fig. 20 is a stacked structure diagram of the gate metal layer, the active layer and the source-drain metal layer in Fig. 17;

[0045] Fig. 21 is a structural diagram of the common electrode layer in Fig. 17;

[0046] Fig. 22 is a structural diagram of the stack of the gate metal layer, the active layer, the source-drain metal layer and the common electrode layer in Fig. 17;

[0047] Fig. 23 is a structural diagram of the stack of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in Fig. 17;

[0048] Fig. 24 is a structural diagram of the light shielding layer in Fig. 17;

[0049] Fig. 25 is an enlarged view of I in Fig. 23;

[0050] Fig. 26 is a sectional view of N1-N1' direction in Fig. 25;

[0051] Fig. 27 is a sectional view of N2-N2' direction in Fig. 25;

[0052] Fig. 28 is a plan view of another version of the display panel in Fig. 6;

[0053] Fig. 29 is a structural diagram of the support layer in Fig. 28;

[0054] Fig. 30 is a structural diagram of the stack of the gate metal layer, the active layer, the source-drain metal layer and the support layer in Fig. 28;

[0055] Fig. 31 is a plan view of another version of the display panel in Fig. 6;

[0056] Fig. 32 is a sectional view of H1-H1' direction in Fig. 31;

[0057] Fig. 33 is a sectional view of H2-H2' direction in Fig. 31;

[0058] Fig. 34 is a sectional view of H3-H3' direction in Fig. 31;

[0059] Fig. 35 is a sectional view of H4-H4' direction in Fig. 31;

[0060] Fig. 36 is a plan view of a display panel according to other embodiments. DETAILED DESCRIPTION

[0061] The technical solutions in some embodiments of the present disclosure will be described clearly and completely below with reference to the drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, but not all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those skilled in the art belong to the scope of protection of the present disclosure.

[0062] Unless otherwise required by context, as used herein and throughout this specification, the term "comprise" and variations of the term, such as "comprises" and "comprising," will be understood to enable open, inclusive meaning that the specification as a whole is not intended to be limited to the listed items. In describing the specification, the terms "some embodiments," "an example," or "some examples" as used herein are intended to mean that a particular feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure. These terms are not necessarily intended to refer to the same embodiment or example. Furthermore, these terms are not necessarily intended to refer to an embodiment or example that is preferred "over" or "as opposed to" another embodiment or example.

[0063] Hereinafter, the terms "first", "second", etc. are used only for the purpose of description, and should not be construed to indicate or imply relative importance or to imply the number of the indicated technical features. Thus, the features defined with "first", "second", etc. can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, the meaning of "a plurality of" is two or more, unless otherwise specified.

[0064] In describing some embodiments, the term "connected" and variations thereof can be used. The term "connected" is used broadly and exemplarily, and can be a fixed connection, a detachable connection, or an integral connection; can be directly connected, or indirectly connected through an intermediate medium. The embodiments disclosed herein are not necessarily limited by the content herein.

[0065] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C", and includes the following combinations of A, B, and C: only A, only B, only C, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0066] "A and / or B" includes the following three combinations: only A, only B, and a combination of A and B.

[0067] As used herein, the term "if' is, optionally, interpreted as meaning "when" or "while", depending on the context. Similarly, the phrase "if it is determined" or "if [stated condition or event] is detected" is, optionally, interpreted as meaning "upon determining" or "in response to determining", depending on the context.

[0068] The use of "configured to" herein means open and inclusive language that does not exclude devices that are adapted to perform additional tasks or steps.

[0069] Additionally, the use of "based on" means open and inclusive, as "based on" one or more stated conditions or values can in practice be based on additional conditions or values beyond those stated.

[0070] As used herein, "about," "approximately," or "around" includes the recited value and average values falling within an acceptable range of deviation thereof, as determined by one of ordinary skill in the art considering the measurement in question and the error intended to be eliminated in that particular measurement.

[0071] As used herein, "parallel," "perpendicular," and "equal" include the recited condition and conditions approximating the recited condition within an acceptable range of deviation, as determined by one of ordinary skill in the art considering the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where near parallel can have an acceptable range of deviation of, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where near perpendicular can also have an acceptable range of deviation of, for example, within 5°. "Equal" includes absolute equality and near equality, where near equality can have an acceptable range of deviation of, for example, a difference between the two of less than or equal to 5% of either.

[0072] It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0073] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples of exemplary embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0074] FIG. 1 is a schematic diagram of a display device, according to some embodiments. As shown in FIG. 1, some embodiments of the present disclosure provide a display device 200 including a liquid crystal display panel 100.

[0075] Exemplarily, the display device 200 further comprises a frame, a display driving integrated circuit (IC) and other electronic accessories, etc.

[0076] Exemplarily, the display device 200 can be a liquid crystal display device (LCD). In the case that the display device 200 is a liquid crystal display device, the display device 200 comprises a cover plate, a liquid crystal display panel 100 and a backlight assembly. The liquid crystal display panel 100 is located between the cover plate and the backlight assembly, the cover plate is used to protect the liquid crystal display panel 100, and the backlight assembly is used to provide a light source for the liquid crystal display panel 100.

[0077] Exemplarily, the display device 200 described above can be any display device that displays images whether in motion (e.g., video) or fixed (e.g., a still image) and whether textual or pictorial. More specifically, it is contemplated that the display device of the described embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or pocket computers, GPS receivers / navigators, cameras, MP4 video players, camcorders, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automobile displays (e.g., odometer display, etc.), navigation instruments, cockpit controls and / or displays, camera view displays (e.g., displays of rear view cameras in vehicles), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., displays of images of a piece of jewelry) and the like.

[0078] FIG. 2 is a plan view of a display panel according to some embodiments, FIG. 3 is a cross-sectional view of a display panel according to some embodiments, FIG. 4 is a structural view of a display panel according to some embodiments, and FIG. 5 is a layout view of the display panel of FIG. 4.

[0079] As shown in FIGS. 2-5, the liquid crystal display panel 100 has an active area (AA) AA.

[0080] The liquid crystal display panel 100 comprises an array substrate 10, a counter substrate 20 and a liquid crystal layer 30 disposed between the array substrate 10 and the counter substrate 20.

[0081] The array substrate 10 comprises a first substrate 11, and a gate metal layer G, an active layer Act, a source-drain metal layer SD, a common electrode layer 12 and a pixel electrode layer 13 which are laminated on the first substrate 11.

[0082] In some examples, the first substrate 11 can be a flexible substrate. For example, the material of the first substrate 11 can be any one of polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0083] In other examples, the first substrate 11 can be a rigid substrate. For example, the rigid substrate can be a glass substrate or a PMMA (Polymethyl methacrylate) substrate, etc.

[0084] The common electrode layer 12 includes a common electrode 121, which can be a surface electrode.

[0085] In some examples, the common electrode 121 is a transparent electrode. For example, the material of the common electrode 21 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide (FTO).

[0086] The pixel electrode layer 13 includes a plurality of pixel electrodes 131, which can be a plurality of strip sub-electrodes in a comb structure.

[0087] In some examples, the pixel electrode 131 is a transparent electrode. For example, the material of the pixel electrode 61 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide (FTO).

[0088] In some examples, the common electrode 121 is a transparent electrode. For example, the material of the common electrode 21 can be at least one of indium tin oxide (ITO), indium zinc oxide (IZO), or fluorine-doped tin oxide (FTO).

[0089] The array substrate 10 further includes a plurality of pixel units P, and the plurality of pixel units P are located in the display area AA. For the convenience of description, the plurality of pixel units P are taken as an example to be arranged in an array form in the disclosure. At this time, the pixel units P arranged in a row along the first direction X are referred to as a row of pixel units, and the pixel units P arranged in a row along the second direction Y are referred to as a column of pixel units. Among them, a plurality of first pixel units P1 are arranged in an array form in the first sub-display area AA1, and a plurality of second pixel units P2 are arranged in an array form in the second sub-display area AA2, so as to realize the array form arrangement of the plurality of pixel units P in the display area AA.

[0090] The first direction X and the second direction Y intersect. Among them, the first direction X can be approximately parallel to the row direction, and the second direction Y can be approximately parallel to the column direction.

[0091] In some examples, the first direction X and the second direction Y can be approximately vertically arranged, and at this time, the included angle between the first direction X and the second direction Y is approximately equal to 90°. For example, the included angle between the first direction X and the second direction Y can be 85°, 90° or 95°.

[0092] Among them, the pixel unit P includes at least one sub-pixel region P0. One sub-pixel region P0 corresponds to the smallest unit for picture display of the liquid crystal display panel 100.

[0093] In some examples, one pixel unit P can include a plurality of sub-pixel regions P0. At this time, the display area AA of the liquid crystal display panel 100 includes a plurality of sub-pixel regions P0. Among them, FIG. 2 takes one pixel unit P including 3 sub-pixel regions P0 as an example for introduction.

[0094] For the convenience of description, the plurality of sub-pixel regions P0 are taken as an example to be arranged in a matrix form in the disclosure. At this time, the sub-pixel regions P0 arranged in a row along the first direction X are referred to as a row of sub-pixel regions, and the sub-pixel regions P0 arranged in a row along the second direction Y are referred to as a column of sub-pixel regions.

[0095] Among them, the plurality of sub-pixel regions P0 can include a first color sub-pixel region, a second color sub-pixel region and a third color sub-pixel region. The first color sub-pixel region, the second color sub-pixel region and the third color sub-pixel region respectively emit three primary colors of light, for example, the first color sub-pixel region can emit red light, the second color sub-pixel region can emit green light, and the third color sub-pixel region can emit blue light. Based on this, the display of a plurality of colors can be realized through color combination and superposition by adjusting the brightness (gray scale) of the color sub-pixel regions of different colors, so as to realize the full-color display of the liquid crystal display panel 100.

[0096] In some examples, one pixel unit P can include one sub-pixel region P0. In this case, the pixel unit P and the sub-pixel region P0 are in one-to-one correspondence, and the display area AA of the liquid crystal display panel 100 includes a plurality of sub-pixel regions P0.

[0097] In addition, the array substrate 10 further includes a plurality of signal lines L, which can include a plurality of first signal lines L1 extending along the first direction X and arranged along the second direction Y. In examples, the first signal lines L1 can be gate lines.

[0098] The plurality of signal lines L can further include a plurality of second signal lines L2 extending along the second direction Y and arranged along the first direction X. In examples, the second signal lines L2 can be data lines.

[0099] In some examples, one row of sub-pixel regions P0 can be connected to one first signal line L1 (gate line), and one column of sub-pixel regions P0 can be connected to one second signal line L2 (data line).

[0100] However, the present disclosure is not limited thereto. In other examples, the first direction X can be substantially parallel to the column direction, and the second direction Y can be substantially parallel to the row direction, and the first signal lines L1 can be data lines, and the second signal lines can be gate lines.

[0101] The sub-pixel region P0 is provided with a pixel circuit W for controlling the display of the sub-pixel region P0, and the pixel circuit W is arranged on the first substrate 11.

[0102] In examples, the pixel circuit W includes a drive transistor TD and a liquid crystal capacitor C. The two plates of the liquid crystal capacitor C are respectively formed by the pixel electrode 131 and the common electrode 121. The control electrode of the drive transistor TD is connected to the gate line GL, the first electrode of the drive transistor TD is connected to the liquid crystal capacitor C, and the second electrode of the drive transistor TD is connected to the second signal line L2 (data line) for transmitting the data signal on the second signal line L2 (data line) to the liquid crystal capacitor C. That is, the electric field formed between the common electrode 121 and the pixel electrode 131 can be used to deflect the liquid crystal in the liquid crystal layer 30 of the display panel 100 to realize picture display.

[0103] However, the inventor has found that, because one row of sub-pixel regions P0 can be connected to one first signal line L1 (gate line), and the common electrode 121 in the common electrode layer 12 is a surface electrode designed as an integral layer, one row of sub-pixel regions P0 in the liquid crystal display panel 100 is simultaneously driven. Furthermore, the sub-pixel regions P0 in the entire display area AA of the liquid crystal display panel 100 are simultaneously driven, so that the liquid crystal display panel 100 cannot achieve division of the display area AA into at least two regions for independent control, which limits the application scenarios of the liquid crystal display panel 100.

[0104] For example, when the display area AA is divided into two adjacent display sub-areas, neither of the two display sub-areas can be independently controlled. That is, the liquid crystal display panel 100 cannot achieve half-screen driving, which reduces the applicability of the liquid crystal display panel 100.

[0105] FIG. 6 is a structural diagram of a display panel according to some embodiments, FIG. 7 is a layout structural diagram of the display panel of FIG. 6, FIG. 8 is a sectional view of M1-M1' direction in FIG. 7, FIG. 9 is a structural diagram of a stack of a gate metal layer, an active layer, and a source-drain metal layer in FIG. 7, FIG. 10 is a structural diagram of a stack of the gate metal layer, the active layer, the source-drain metal layer, and a common electrode layer in FIG. 7, FIG. 11 is a structural diagram of a stack of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer, and a pixel electrode layer in FIG. 7, and FIG. 12 is a structural diagram of a light shielding layer in FIG. 7.

[0106] Based on this, in combination with FIGS. 6-12, the liquid crystal display panel 100 provided by some embodiments of the present disclosure can include, along the first direction X, a first display sub-area AA1 and a second display sub-area AA2 adjacent to each other. The first display sub-area AA1 is adjacent to a side edge of the second display sub-area AA2, and coincides with a side edge of the second display sub-area AA2 adjacent to the first display sub-area AA1.

[0107] The plurality of pixel units P include a plurality of first pixel units P1 in the first display sub-area AA1 and a plurality of second pixel units P2 in the second display sub-area AA2. The sub-pixel regions P0 in the first pixel units P1 are first sub-pixel regions P01, and the sub-pixel regions P0 in the second pixel units P2 are second sub-pixel regions P02.

[0108] The first signal line L1 includes a first line segment L11 and a second line segment L12 which are disconnected from each other, the first line segment L11 is located in the first sub-display area AA1, and the second line segment L12 is located in the second sub-display area AA2. The first line segment L11 is electrically connected with the first pixel unit P1, so as to drive the first pixel unit P1 in the first sub-display area AA1 by the first line segment L11 located in the first sub-display area AA1. The second line segment L12 is electrically connected with the second pixel unit P2, so as to drive the second pixel unit P2 in the second sub-display area AA2 by the second line segment L12 located in the second sub-display area AA2.

[0109] That is, a plurality of first signal lines L1 can be disconnected at the position of the first reference line O, the part of the first signal line L1 located in the first sub-display area AA1 is the first line segment L11, and the part of the first signal line L1 located in the second sub-display area AA2 is the second line segment L12. The first reference line O can be the boundary line of the first sub-display area AA1 and the second sub-display area AA2.

[0110] For example, the first reference line O can be the center line of the liquid crystal display panel 100, so that the number of sub-pixel areas in the first sub-display area AA1 is approximately equal to the number of sub-pixel areas in the second sub-display area AA2.

[0111] Based on this, the first line segment L11 of the first signal line L1 can be connected with a plurality of first sub-pixel areas P01 in a row of sub-pixel areas corresponding to the first signal line L1 and located in the first sub-display area AA1, and the second line segment L12 of the first signal line L1 can be connected with a plurality of second sub-pixel areas P02 in a row of sub-pixel areas corresponding to the first signal line L1 and located in the second sub-display area AA2.

[0112] In this way, different line segments of the first signal line can be used to drive sub-pixel areas P0 in different display areas, so as to prevent a first signal line L1 from simultaneously driving all sub-pixel areas P0 in a row of sub-pixel areas in the display area AA.

[0113] The common electrode layer 12 includes a first common electrode C1 located in the first sub-display area AA1 and a second common electrode C2 located in the second sub-display area AA2.

[0114] That is, the common electrode 121 in the common electrode layer 12 is disconnected at the position of the first reference line O, the part of the common electrode 121 located in the first sub-display area AA1 is the first common electrode C1, and the part of the common electrode 121 located in the second sub-display area AA2 is the second common electrode C2.

[0115] The orthogonal projection of the first common electrode C1 on the first substrate 11 can cover the pixel electrode 131 in the first sub-pixel area P01 in the first sub-display area AA1. Based on this, when the first line segment L11 drives the pixel circuit W in the first sub-pixel area P01 to be turned on, an electric field can be formed between the first common electrode C1 and the pixel electrode 131 in the first sub-pixel area P01, and then the liquid crystal in the liquid crystal layer 30 corresponding to the first sub-display area AA1 can be deflected, so that the first sub-display area AA1 in the liquid crystal display panel 100 realizes picture display.

[0116] In addition, the orthogonal projection of the second common electrode C2 on the first substrate 11 can cover the pixel electrode 131 in the second sub-pixel area P02 in the second sub-display area AA2. Based on this, when the second line segment L12 drives the pixel circuit W in the second sub-pixel area P02 to be turned on, an electric field can be formed between the second common electrode C2 and the pixel electrode 131 in the second sub-pixel area P02, and then the liquid crystal in the liquid crystal layer 30 corresponding to the second sub-display area AA2 can be deflected, so that the second sub-display area AA2 in the liquid crystal display panel 100 realizes picture display.

[0117] Therefore, the partial display area AA in the liquid crystal display panel 100 can be driven to realize picture display, so as to realize the partition control of the liquid crystal display panel 100 and improve the applicability of the liquid crystal display panel 100.

[0118] In some examples, along the first direction X, the first gap Q is between the first common electrode C1 and the second common electrode C2, and the first gap Q extends along the second direction Y. Therefore, the distance between the first common electrode C1 in the first sub-display area AA1 and the second common electrode C2 in the second sub-display area AA2 can be increased, so as to reduce the mutual coupling effect between the first common electrode C1 and the second common electrode C2 when the first sub-pixel area P01 in the first sub-display area AA1 is driven or the second sub-pixel area P02 in the second sub-display area AA2 is driven, so as to prevent the problem of light leakage in the un-driven sub-display area, and improve the accuracy of the partition control of the liquid crystal display panel 100.

[0119] In some examples, along the first direction X, the width of the first gap Q is greater than or equal to 8 μm.

[0120] When the width of the first gap Q in the first direction X is equal to or approaches 8 μm, the width of the first gap Q is large. That is, the distance between the first common electrode C1 located in the first sub-display area AA1 and the second common electrode C2 located in the second sub-display area AA2 is large, which can prevent the mutual coupling effect between the first common electrode C1 and the second common electrode C2, so as to prevent the problem of affecting the light leakage in the un-driven sub-display area.

[0121] For example, the width of the first gap Q is about any one of 8 μm, 8.2 μm, 8.5 μm, 8.8 μm, 9 μm, 9.5 μm or 10 μm. However, the embodiment of the present disclosure is not limited thereto.

[0122] It should be noted that the width of the first gap Q is about 8 μm as an example. Due to the existence of uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), when the width of the first gap Q is within the range of ±10% × 8 μm, it can also be considered that the size of the first gap Q meets the requirement of being equal to 8 μm.

[0123] In some examples, as shown in FIGS. 6-8, the cell substrate 20 further includes a second substrate 22 and a color filter layer (not shown in the figure) located on the second substrate 22. In this case, the cell substrate 20 can also be referred to as a color filter substrate (English full name: Color filter, English abbreviation: CF). The color filter layer includes at least a red photoresist unit, a green photoresist unit and a blue photoresist unit, and the red photoresist unit, the green photoresist unit and the blue photoresist unit are respectively one-to-one opposite to the sub-pixel area P0 on the array substrate 10.

[0124] The cell substrate 20 further includes a light shielding layer 21 disposed on the second substrate 22, and the light shielding layer 21 is used to separate the red photoresist unit, the green photoresist unit and the blue photoresist unit.

[0125] In some examples, the material of the light shielding layer 21 can be a light shielding material. For example, the material of the light shielding layer 21 can be black resin.

[0126] The light shielding layer 21 includes a first light shielding portion 211, and the orthographic projection of the first light shielding portion 211 on the first substrate 11 at least partially overlaps the orthographic projection of the first gap Q on the first substrate 11.

[0127] That is, the first light shielding portion 211 is located on the side of the first slit Q away from the first substrate 11, and the first light shielding portion 211 can be used to shield the light emitted at the position of the first slit Q to prevent light leakage at the position of the first slit Q. That is, the light leakage at the position of the junction line O between the first sub-display area AA1 and the second sub-display area AA2 of the liquid crystal display panel 100 can be further reduced, and the display quality of the liquid crystal display panel 100 can be improved.

[0128] In summary, the liquid crystal display panel 100 provided by the embodiments of the present disclosure divides the display area AA into the first sub-display area AA1 and the second sub-display area AA2, and truncates the first signal line L1 and the common electrode 121 in the first sub-display area AA1 and the second sub-display area AA2, so that the signal line, the electrode, or other conductive structure in any sub-display area of the display area AA of the liquid crystal display panel 100 is an independent structure, and the partial display area AA of the liquid crystal display panel 100 is driven to realize a picture, so as to realize the partition control of the liquid crystal display panel 100 and improve the applicability of the liquid crystal display panel 100. In addition, the first light shielding portion 211 corresponding to the first slit Q can be provided on the opposing substrate 20 of the liquid crystal display panel 100, so as to reduce the light leakage at the position of the junction line O between the first sub-display area AA1 and the second sub-display area AA2 of the liquid crystal display panel 100, and improve the display quality of the liquid crystal display panel 100.

[0129] In some embodiments, as shown in FIGS. 6-8, the orthographic projection of the first light shielding portion 211 on the first substrate 11 at least partially overlaps the orthographic projection of the first slit Q on the first substrate 11, which can include the following three cases:

[0130] Firstly, the orthographic projection of the first light shielding portion 211 on the first substrate 11 partially overlaps the orthographic projection of the first slit Q on the first substrate 11.

[0131] Secondly, the boundary of the orthographic projection of the first light shielding portion 211 on the first substrate 11 substantially overlaps the boundary of the orthographic projection of the first slit Q on the first substrate 11.

[0132] Thirdly, the orthographic projection of the first slit Q on the first substrate 11 is located within the boundary of the orthographic projection of the first light shielding portion 211 on the first substrate 11. That is, the orthographic projection of the first light shielding portion 211 on the first substrate 11 covers the orthographic projection of the first slit Q on the first substrate 11.

[0133] In the three setting modes of the first light shielding part 211 and the first gap Q, any one of the setting modes can use the first light shielding part 211 to shield the light emitted at the position of the first gap Q to a certain extent, so as to improve the light leakage problem at the position of the first gap Q. Among them, the larger the size of the first light shielding part 211, the more light emitted at the position of the first gap Q can be shielded. The third setting mode can shield more light emitted from the position of the first gap Q than the first and second setting modes.

[0134] In some examples, when the width of the first gap Q in the first direction X is greater than or equal to 8 μm, the width of the first light shielding part 211 in the first direction X can be greater than or equal to 8 μm, so as to better realize the second and third setting modes of the first light shielding part 211 and the first gap Q, shield more light emitted at the position of the first gap Q, and improve the light leakage problem at the position of the first gap Q in the liquid crystal display panel 100.

[0135] In some embodiments, as shown in FIGS. 6-8 and 12, the light shielding layer 21 further includes a plurality of second light shielding parts 212 extending in the second direction Y. The second light shielding parts 212 are used to isolate two adjacent color group units in the first direction X to prevent the color light emitted by the two adjacent color group units in the first direction X from interfering with each other, thereby causing the problem of color bleeding in the two adjacent sub-pixel regions P0.

[0136] It should be noted that the difference between the first light shielding part 211 and the second light shielding part 212 in the light shielding layer 21 is that the first light shielding part 211 in the light shielding layer 21 is used to isolate the color group unit located in the first display area AA1 and the color group unit adjacent to the color group unit and located in the second display area AA2, so as to improve the light leakage problem at the position of the first display area AA1 and the second display area AA2. The second light shielding part 212 in the light shielding layer 21 is used to isolate two adjacent color group units in the first direction X in the same sub-display area, so as to prevent the problem of color bleeding in the two adjacent sub-pixel regions P0 in the same sub-display area.

[0137] In some examples, the orthographic projection of the second signal line L2 on the first substrate 11 at least partially overlaps with the orthographic projection of the second light shielding part 212 on the first substrate 11. The second light shielding part 212 can be used to prevent the problem of reflection of the second signal line L2 and the problem of light leakage at the position of the second signal line L2.

[0138] Among them, the orthographic projection of the second signal line L2 on the first substrate 11 at least partially overlaps with the orthographic projection of the second light shielding part 212 on the first substrate 11, which can include the following three setting modes.

[0139] The first kind: the orthographic projection of the second signal line L2 on the first substrate 11 partially overlaps with the orthographic projection of the second light shielding portion 212 on the first substrate 11.

[0140] The second kind: the boundary of the orthographic projection of the second signal line L2 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11.

[0141] The third kind: the orthographic projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11.

[0142] Among the above three kinds of arrangements of the second signal line L2 and the second light shielding portion 212, any one of the arrangements can reduce the problem of light leakage at the position of the second signal line L2 to a certain extent by using the second light shielding portion 212. Among them, the third kind of arrangement can completely cover the second signal line L2 relative to the first and second kinds of arrangements, and can better reduce the problem of light leakage at the position of the second signal line L2.

[0143] In some embodiments, as shown in FIGS. 6, 7, 8 and 12, along the first direction X, the width of the first light shielding portion 211 is W1, and the width of the second light shielding portion 212 is W2, and W1≤1.5W2.

[0144] In this way, the width of the first light shielding portion 211 can be prevented from being too wide to cause a large difference between the width of the first light shielding portion 211 and the width of the second light shielding portion 212, and thus a black line problem at the position of the first light shielding portion 211 in the liquid crystal display panel 100 can be prevented while the first light shielding portion 211 completely covers the first gap Q. Therefore, setting the width of the first light shielding portion 211 to be less than or equal to 1.5 times the width of the second light shielding portion 212 is beneficial to improve the quality of the display picture of the liquid crystal display panel 100.

[0145] In some examples, W1≤1.3W2. Based on this, the difference between the width of the first light shielding portion 211 and the width of the second light shielding portion 212 can be further reduced to prevent the black line problem at the position of the first light shielding portion 211 in the liquid crystal display panel 100 while the first light shielding portion 211 completely covers the first gap Q.

[0146] For example, any one of W1=1.2W2, W1=1.3W2, W1=1.4W2 or W1=1.5W2. However, the embodiments of the present disclosure are not limited thereto.

[0147] In some embodiments, the light shielding layer 21 further comprises a plurality of third light shielding portions 213 extending along the first direction X, the third light shielding portions 213 being configured to isolate two adjacent color group units in the second direction Y to prevent the color light emitted by the two adjacent color group units in the second direction Y from interfering with each other, thereby causing the problem of color bleeding in the two adjacent sub-pixel regions P0. The plurality of first light shielding portions 211, the plurality of second light shielding portions 212 and the plurality of third light shielding portions 213 in the light shielding layer 21 can form a grid-shaped light shielding layer 21.

[0148] In some examples, the orthographic projection of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11. The third light shielding portion 213 can be used to prevent the problem of light reflection of the first signal line L1 and the problem of light leakage at the position of the first signal line L1.

[0149] In some examples, the orthographic projection of the first signal line L1 on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11. The third light shielding portion 213 can be used to prevent the problem of light reflection of the first signal line L1 and the problem of light leakage at the position of the first signal line L1.

[0150] The first kind: the orthographic projection of the first signal line L1 on the first substrate 11 partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0151] The second kind: the boundary of the orthographic projection of the first signal line L1 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0152] The third kind: the orthographic projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0153] In the above three kinds of arrangements of the first signal line L1 and the third light shielding portion 213, any one of the arrangements can use the third light shielding portion 213 to reduce the problem of light leakage at the position of the first signal line L1 to a certain extent. In the third kind of arrangement, the third light shielding portion 213 can completely cover the first signal line L1, and can better reduce the problem of light leakage at the position of the first signal line L1 compared to the first kind and the second kind of arrangement.

[0154] In some examples, the orthographic projection of the driving transistor TD on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11. The third light shielding portion 213 can be used to prevent the problem of light reflection of the driving transistor TD and the problem of light leakage at the position of the driving transistor TD.

[0155] The orthographic projection of the driving transistor TD on the first substrate 11 at least partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11. The three setting modes can include the following three setting modes.

[0156] The first setting mode is that the orthographic projection of the driving transistor TD on the first substrate 11 partially overlaps with the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0157] The second setting mode is that the boundary of the orthographic projection of the driving transistor TD on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0158] The third setting mode is that the orthographic projection of the driving transistor TD on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0159] In the three setting modes of the driving transistor TD and the third light shielding portion 213, any one of the setting modes can reduce the light leakage problem at the position of the driving transistor TD to a certain extent by using the third light shielding portion 213. In the third setting mode, the third light shielding portion 213 can completely cover the driving transistor TD, and the light leakage problem at the position of the driving transistor TD can be better reduced.

[0160] FIG. 13 is another layout structure diagram of the display panel of FIG. 6, FIG. 14 is a sectional view in the direction of M2-M2' in FIG. 13, FIG. 15 is a stack structure diagram of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in FIG. 13, FIG. 16 is a structure diagram of the light shielding layer in FIG. 13. FIG. 17 is another layout structure diagram of the display panel of FIG. 6, FIG. 18 is a sectional view in the direction of M3-M3' in FIG. 17, FIG. 19 is a stack structure diagram of the gate metal layer and the active layer in FIG. 17, FIG. 20 is a stack structure diagram of the gate metal layer, the active layer and the source-drain metal layer in FIG. 17, FIG. 21 is a structure diagram of the common electrode layer in FIG. 17, FIG. 22 is a stack structure diagram of the gate metal layer, the active layer, the source-drain metal layer and the common electrode layer in FIG. 17, FIG. 23 is a stack structure diagram of the gate metal layer, the active layer, the source-drain metal layer, the common electrode layer and the pixel electrode layer in FIG. 17, and FIG. 24 is a structure diagram of the light shielding layer in FIG. 17.

[0161] The difference between the liquid crystal display panel shown in FIG. 13 and the liquid crystal display panel shown in FIG. 17 is that the arrangement of the sub-pixel regions is different, and the specific arrangement will be described in detail below.

[0162] The liquid crystal display panel shown in FIGS. 13 and 17 differs from the liquid crystal display panel 100 shown in FIGS. 7 and 8 in that, in the liquid crystal display panel 100 shown in FIGS. 7 and 8, the second signal line L2 in the first sub-display area AA1 and the second signal line L2 in the second sub-display area AA2 are both located on the same side of the column of sub-pixel regions P0 to which they are connected. For example, the second signal line L2 in the first sub-display area AA1 and the second signal line L2 in the second sub-display area AA2 are both located on the left side of the column of sub-pixel regions P0 to which they are connected. As a result, the normal projection of the second signal line L2 in the second sub-display area AA2 closest to the first sub-display area AA1 on the first substrate 11 is located close to the side of the normal projection of the second common electrode C2 on the first substrate 11 that is closest to the first sub-display area AA1. That is, the normal projection of the second signal line L2 in the second sub-display area AA2 closest to the first sub-display area AA1 on the first substrate 11 does not overlap the normal projection of the second common electrode C2 on the first substrate 11.

[0163] Because the normal projection of the second signal line L2 on the first substrate 11 does not overlap the normal projection of the second common electrode C2 on the first substrate 11, the common electrode layer is not provided between the second signal line L2 and the liquid crystal layer. Based on this, the electric field generated by the second signal line L2 when transmitting a data signal can cause the liquid crystal at the corresponding position of the liquid crystal layer to deflect, thereby causing a light leakage problem.

[0164] In the liquid crystal display panel 100 shown in FIGS. 7 and 8, in order to improve the light leakage problem of the liquid crystal display panel 100, the width of the first light shielding portion 211 is increased to cover the second signal line L2 with the first light shielding portion 211 to prevent the light leakage problem at the position of the second signal line L2. However, increasing the width of the first light shielding portion 211 can easily cause a black line problem of the liquid crystal display panel 100.

[0165] Based on this, in some embodiments, as shown in FIGS. 13-20, one of the second signal lines L2 is located on the side away from the first reference line O of the column of sub-pixel regions P0 to which it is connected.

[0166] Because the normal projection of the first common electrode C1 on the first substrate 11 can cover the pixel electrode 131 in all the first sub-pixel regions P01 in the first sub-display area AA1, the electric field formed between the first common electrode C1 and the pixel electrode 131 in the first sub-pixel region P01 can cause the liquid crystal in the first sub-display area AA1 of the liquid crystal display panel 100 to deflect, thereby achieving half-screen control display control of the liquid crystal display panel 100.

[0167] Therefore, any one of the second signal lines L2 is arranged on the side of the column of sub-pixel regions P0 to which the second signal line L2 is electrically connected, away from the first reference line O. That is, the second signal line L2 located in the first sub-display area AA1 is arranged on the side of the column of first sub-pixel regions P01 to which the second signal line L2 is electrically connected, away from the second sub-display area AA2, so that the orthogonal projection of the second signal line L2 located in the first sub-display area AA1 on the first substrate 11 is located on the side of the orthogonal projection of the pixel electrode 131 corresponding to the second signal line L2 on the first substrate 11, away from the orthogonal projection of the first slit Q on the first substrate 11.

[0168] Therefore, the orthogonal projection of the second signal line L2 located in the first sub-display area AA1 on the first substrate 11 is located within the boundary of the orthogonal projection of the first common electrode C1 on the first substrate 11.

[0169] In this way, the first common electrode C1 can shield the second signal line L2 and the liquid crystal layer, so as to prevent the electric field generated by the second signal line L2 when transmitting the data signal from causing the liquid crystal at the corresponding position of the liquid crystal layer to deflect, thereby preventing the problem of light leakage.

[0170] The second signal line L2 located in the second sub-display area AA2 is arranged on the side of the column of second sub-pixel regions P02 to which the second signal line L2 is electrically connected, away from the second sub-display area AA2, so that the orthogonal projection of the second signal line L2 located in the second sub-display area AA2 on the first substrate 11 is located on the side of the orthogonal projection of the pixel electrode 131 corresponding to the second signal line L2 on the first substrate 11, away from the orthogonal projection of the first slit Q on the first substrate 11.

[0171] Therefore, the orthogonal projection of the second signal line L2 located in the second sub-display area AA2 on the first substrate 11 is located within the boundary of the orthogonal projection of the second common electrode C2 on the first substrate 11.

[0172] In this way, the second common electrode C2 can shield the second signal line L2 and the liquid crystal layer, so as to prevent the electric field generated by the second signal line L2 when transmitting the data signal from causing the liquid crystal at the corresponding position of the liquid crystal layer to deflect, thereby preventing the problem of light leakage.

[0173] In addition, the first common electrode C1 and the second common electrode C2 can cover the entire second signal line L2 on the first substrate 11 in the orthographic projection, and the common electrode layer 12 can shield the light. Therefore, the first light shielding portion 211 does not need to be widened to improve the light leakage problem of the liquid crystal display panel 100. Furthermore, the width of the first light shielding portion 211 in the liquid crystal display panel 100 shown in FIGS. 13 and 17 can be reduced by the width of the second signal line L2 compared with the width of the first light shielding portion 211 in the liquid crystal display panel 100 shown in FIGS. 7 and 8. This can improve the black line problem of the liquid crystal display panel 100 and improve the aperture ratio of the liquid crystal display panel 100.

[0174] In some embodiments, as shown in FIGS. 13-24, the driving transistor TD in the sub-pixel region P0 is electrically connected to the first signal line L1, the second signal line L2 and the pixel electrode 131, respectively. Specifically, the control electrode g of the driving transistor TD is electrically connected to the first signal line L1, the first electrode s of the driving transistor TD is electrically connected to the pixel electrode, and the second electrode d of the driving transistor TD is electrically connected to the second signal line L2.

[0175] In the first sub-pixel region P01, the driving transistor TD is electrically connected to the first line segment L11, the second signal line L2 and the pixel electrode 131, respectively, and the orthographic projection of the pixel electrode 131 and the first common electrode C1 on the first substrate 11 at least partially overlaps, so that an electric field is formed between the pixel electrode 131 and the first common electrode C1, the liquid crystal in the first sub-display area AA1 is deflected, and the first sub-display area AA1 in the liquid crystal display panel 100 displays the picture, and the second sub-display area AA2 can display the picture or not according to the internal control.

[0176] In the second sub-pixel region P02, the driving transistor TD is electrically connected to the second line segment L12, the second signal line L2 and the pixel electrode 131, respectively, and the orthographic projection of the pixel electrode 131 and the second common electrode C2 on the first substrate 11 at least partially overlaps, so that an electric field is formed between the pixel electrode 131 and the second common electrode C2, the liquid crystal in the second sub-display area AA2 is deflected, and the second sub-display area AA2 in the liquid crystal display panel 100 displays the picture, and the first sub-display area AA1 can display the picture or not according to the internal control.

[0177] Based on this, the driving transistor TD can be arranged to project orthogonally on the first substrate 11 in a region surrounded by the orthogonally projected regions of the first signal line L1, the second signal line L2 and the pixel unit P on the first substrate 11, so as to electrically connect the driving transistor TD with the first signal line L1, the second signal line L2 and the pixel electrode 131, reduce the problem of winding of each film layer in the array substrate, and improve the regularity of the array substrate wiring.

[0178] The liquid crystal display panel shown in FIG. 13 and the liquid crystal display panel shown in FIG. 17 are the same in that, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction in the liquid crystal display panel 100 shown in FIG. 13: the driving transistor TD in the first sub-pixel region P01 and the driving transistor TD in the second sub-pixel region P02 are mirror-symmetrical about the second reference line. That is, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction: the driving transistor TD in the first sub-pixel region P01 and the driving transistor TD in the second sub-pixel region P02 are mirror-symmetrical about the second reference line. While in the liquid crystal display panel shown in FIG. 17: the driving transistor TD in the first sub-pixel region P01 and the driving transistor TD in the second sub-pixel region P02 are also mirror-symmetrical about the second reference line.

[0179] The second reference line is the center line of the line connecting the first sub-pixel region P01 and the second sub-pixel region P02. The center line can be a line perpendicular to the line connecting the first sub-pixel region P01 and the second sub-pixel region P02 and passing through the center of the line connecting the first sub-pixel region P01 and the second sub-pixel region P02.

[0180] In some embodiments, as shown in FIG. 13 and FIG. 17, the driving transistor TD in the first sub-pixel region P01 and the driving transistor TD in the second sub-pixel region P02 arranged along the first direction are mirror-symmetrical about the second reference line.

[0181] In this way, the second electrode d of the driving transistor TD in the first sub-pixel region P01 can be closer to the pixel electrode 131 in the same first sub-pixel region P01 and the second signal line L2. In the case where any one of the second signal lines L2 is located on the side away from the first reference line O of the column of sub-pixel regions P0 to which it is electrically connected, the second electrode d of the driving transistor TD is electrically connected to the corresponding second signal line L2, and the first electrode s of the driving transistor TD is also electrically connected to the corresponding pixel electrode 131. Therefore, it is beneficial to simplify the wiring layout in the array substrate.

[0182] The liquid crystal display panel shown in FIG. 13 is different from the liquid crystal display panel shown in FIG. 17 in that, in the liquid crystal display panel 100 shown in FIG. 13, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction: the first sub-pixel region P01 and the second sub-pixel region P02 are mirror-symmetrical about the second reference line. That is, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction: the pixel electrode 131 in the first sub-pixel region P01 and the pixel electrode 131 in the second sub-pixel region P02 are also mirror-symmetrical about the second reference line. In the liquid crystal display panel shown in FIG. 17, in the first sub-pixel region P01 and the second sub-pixel region P02 arranged along the first direction: the pixel electrode 131 in the first sub-pixel region P01 and the pixel electrode 131 in the second sub-pixel region P02 do not need to be mirror-symmetrical about the second reference line.

[0183] In some embodiments, as shown in FIGS. 17-22, the pixel electrode 131 is a dual-domain pixel electrode, which includes a first domain portion 131A and a second domain portion 131B, and the first domain portion 131A and the second domain portion 131B extend in intersecting directions. The corner formed by the intersection of the first domain portion 131A and the second domain portion 131B of the pixel electrode in any first sub-pixel region is a first corner, and the corner formed by the intersection of the first domain portion 131A and the second domain portion 131B of the pixel electrode in any second sub-pixel region is a second corner. The first corner and the second corner protrude in the same direction.

[0184] That is, the arrangement of all the pixel electrodes 131 in the liquid crystal display panel 100 is the same. In this way, the dual-domain pixel electrode in the column of first sub-pixel regions P01 in the first display area AA1 closest to the second display area AA2 is arranged in the same way as the dual-domain pixel electrode in the column of second sub-pixel regions P02 in the second display area AA2 closest to the first display area AA1.

[0185] Therefore, the edge of the first common electrode C1 close to the second display area AA2 can be arranged along the contour of the dual-domain pixel electrode in the column of first sub-pixel regions P01 in the first display area AA1 closest to the second display area AA2 to form an electric field between the first common electrode C1 and the pixel electrode 131. Similarly, the edge of the second common electrode C2 close to the first display area AA1 can be arranged along the contour of the dual-domain pixel electrode in the column of second sub-pixel regions P02 in the second display area AA2 closest to the first display area AA1 to form an electric field between the second common electrode C2 and the pixel electrode 131.

[0186] As shown in the structure above, the first corner corresponding to the dual-domain pixel electrode in the first sub-pixel region P01 closest to the second sub-pixel region AA2 in the first sub-display area AA1 and the second corner corresponding to the dual-domain pixel electrode in the second sub-pixel region P02 closest to the first sub-display area AA1 in the second sub-display area AA2 protrude in one direction, and the corresponding common electrode is also arranged corresponding to the outer contour of the pixel electrode. In contrast to the liquid crystal display panel 100 shown in FIGS. 13-17, the first corner corresponding to the dual-domain pixel electrode in the first sub-pixel region P01 closest to the second sub-pixel region AA2 in the first sub-display area AA1 and the second corner corresponding to the dual-domain pixel electrode in the second sub-pixel region P02 closest to the first sub-display area AA1 in the second sub-display area AA2 are arranged in opposite directions, and the corresponding common electrode is also arranged corresponding to the outer contour of the pixel electrode. This can help to reduce the distance between the pixel electrodes on the left and right sides of the first reference line O. Furthermore, the distance between the first gap Q between the first common electrode C1 and the second common electrode C2 can be indirectly reduced. Therefore, the width of the first light shielding portion 211 can also be correspondingly reduced to reduce the problem of black lines appearing on the liquid crystal display panel 100, thereby improving the aperture ratio of the liquid crystal display panel 100.

[0187] In addition, the orientations of the driving transistors TD in the first sub-pixel region P01 and the second sub-pixel region P02 are mirror-symmetrically designed, and other parameters of the driving transistors TD are consistent. For example, the channel width, channel length, and via size of the driving transistors TD in the first sub-pixel region P01 and the second sub-pixel region P02 are consistent.

[0188] In some examples, as shown in FIGS. 20-23, since the common electrode layer 12 is located between the pixel electrode layer 13 and the source-drain metal layer SD, the first electrode s of the driving transistor TD on the source-drain metal layer SD needs to be electrically connected to the pixel electrode 131 in the pixel electrode layer 13.

[0189] Based on this, the common electrode on the common electrode layer can include a plurality of vias K, and the orthographic projection of the pixel electrode 131 on the first substrate 11 covers the orthographic projection of the hollow area K on the first substrate 11. Based on this, the first electrode s of the driving transistor TD on the source-drain metal layer SD can be electrically connected to the pixel electrode 131 in the pixel electrode layer 13 through the hollow area K, to prevent the first electrode s of the driving transistor TD from being short-circuited with the common electrode.

[0190] For example, the plurality of vias K on the first common electrode C1 correspond to the pixel electrodes 131 in the plurality of first sub-pixel regions P01. Similarly, the plurality of vias K on the second common electrode C2 correspond to the pixel electrodes 131 in the plurality of second sub-pixel regions P02.

[0191] In some embodiments, as shown in FIGS. 17 and 19, the gate metal layer G can include a first signal line L1, the first signal line L1 including a first portion 01 multiplexed as a control electrode g of the driving transistor TD.

[0192] The first line segment L11 of the first signal line L1 can include the first portion 01 multiplexed as the control electrode g of the driving transistor TD electrically connected to the first line segment L11.

[0193] In this way, the control electrode g of the driving transistor TD does not need to be formed separately, which facilitates simplifying the manufacturing process of the liquid crystal display panel 100. In addition, an additional conductive part does not need to be provided to electrically connect the control electrode g of the driving transistor TD and the first line segment L11, which facilitates simplifying the structure of the driving circuit.

[0194] Similarly, the second line segment L12 of the first signal line L1 can include the first portion 01 multiplexed as the control electrode g of the driving transistor TD electrically connected to the second line segment L12.

[0195] In this way, the control electrode g of the driving transistor TD does not need to be formed separately, which facilitates simplifying the manufacturing process of the liquid crystal display panel 100. In addition, an additional conductive part does not need to be provided to electrically connect the control electrode g of the driving transistor TD and the second line segment L12, which facilitates simplifying the structure of the driving circuit.

[0196] In some examples, as shown in FIGS. 17 and 20, the source-drain metal layer SD includes a second signal line L2, the second signal line L2 including a first sub-portion L21 multiplexed as a second electrode d of the driving transistor TD.

[0197] In this way, the second electrode d of the driving transistor TD does not need to be formed separately, which facilitates simplifying the manufacturing process of the liquid crystal display panel 100. In addition, an additional conductive part does not need to be provided to electrically connect the second electrode d of the driving transistor TD and the second signal line L2, which facilitates simplifying the structure of the driving circuit.

[0198] In addition, the source-drain metal layer SD can further include a first conductive part E including a third portion 03 multiplexed as a first electrode s of the driving transistor TD. The first conductive part E, the second electrode d of the driving transistor TD, and the second signal line L2 are designed in the same layer, which can facilitate simplifying the manufacturing process of the liquid crystal display panel 100.

[0199] It should be noted that "same layer" refers to a layer structure formed by using the same film forming process to form a film layer for forming a specific pattern, and then using the same mask plate to form by a one-time patterning process. Depending on the specific pattern, the one-time patterning process can include multiple exposure, development or etching processes, and the specific patterns in the formed layer structure can be continuous or discontinuous, and these specific patterns can also be at different heights or have different thicknesses.

[0200] FIG. 25 is a partial enlarged view of I in FIG. 23, FIG. 26 is a sectional view of N1-N1' direction in FIG. 25, and FIG. 27 is a sectional view of N2-N2' direction in FIG. 25.

[0201] In some embodiments, as shown in FIGS. 19-23 and 25-27, the first signal line L1 can further include a second portion 02, and the first portion 01 and the second portion 02 of the first signal line L1 are arranged along the first direction X. The orthographic projection of the via K on the first substrate 11 is located between the orthographic projections of the first portion 01 and the second portion 02 of the first signal line L1 on the first substrate 11.

[0202] In some examples, the first signal line L1 includes a first gap B, and the first gap B divides the first signal line L1 into the first portion 01 and the second portion 02. The orthographic projection of the first gap B on the first substrate 11 at least partially overlaps with the orthographic projection of the via K on the first substrate 11, so as to prevent the formation of a coupling capacitance between the first signal line L1 and the pixel electrode 131 above it, thereby increasing the load.

[0203] In some examples, as shown in FIGS. 19-23 and 25-27, the first signal line L1 can further include a first connecting portion 011, and the first connecting portion 011 is located in the first gap B. That is, the first connecting portion 011 is located between the first portion 01 and the second portion 02 of the first signal line L1, and is used to connect the first portion 01 and the second portion 02 of the first signal line L1. The orthographic projection of the first connecting portion on the first substrate 11 is located on one side of the orthographic projection of the pixel electrode 131 on the first substrate 11, so that the orthographic projection of the first connecting portion on the first substrate 11 does not overlap with the orthographic projection of the pixel electrode 131 on the first substrate 11, so as to prevent the formation of a coupling capacitance between the two, thereby increasing the load of the two.

[0204] The first conductive portion E on the source-drain metal layer SD can further include a fourth portion 04, and the third portion 03 and the fourth portion 04 of the first conductive portion E are arranged along the first direction X. The first conductive portion E can further include a second connecting portion 012, and the second connecting portion 012 is located between the third portion 03 and the fourth portion 04 of the first conductive portion E, and is used to connect the third portion 03 and the fourth portion 04 of the first conductive portion E.

[0205] The orthogonal projection of the via K on the first substrate 11 is located between the orthogonal projection of the third portion 03 and the fourth portion 04 of the first conductive portion E on the first substrate 11. That is, the via K can expose the second connecting portion 012 of the first conductive portion E on the source-drain metal layer SD, so that the pixel electrode 131 in the pixel electrode layer 13 can be electrically connected to the second connecting portion 012 of the first conductive portion E through the via K, and then electrically connected to the first electrode s of the driving transistor TD.

[0206] The orthogonal projection of the first portion 01 of the first signal line L1 on the first substrate 11 at least partially overlaps the orthogonal projection of the third portion 03 of the first conductive portion E on the first substrate 11, and the orthogonal projection of the second portion 02 of the first signal line L1 on the first substrate 11 at least partially overlaps the orthogonal projection of the fourth portion 04 of the first conductive portion E on the first substrate 11.

[0207] Based on the above structure, when the gate metal layer G and the source-drain metal layer SD in the liquid crystal display panel 100 are offset, the coupling capacitance formed between the second portion 02 of the first signal line L1 and the fourth portion 04 of the first conductive portion E can be used to compensate for the coupling capacitance formed between the first portion 01 of the first signal line L1 and the third portion 03 of the first conductive portion W, so as to improve the problem that the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 of the liquid crystal display panel 100 is too different from the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2.

[0208] Specifically, in the case of left offset of the source-drain metal layer SD, the overlapping area of the orthogonal projection of the first portion 01 of the first signal line L (the first line segment L11) on the first substrate 11 and the orthogonal projection of the third portion 03 (the first electrode s of the driving transistor TD) of the first conductive portion W on the first substrate 11 in the first sub-display area AA1 will increase, but the overlapping area of the orthogonal projection of the second portion 02 of the first signal line L (the first line segment L11) on the first substrate 11 and the orthogonal projection of the fourth portion 04 of the first conductive portion W on the first substrate 11 in the source-drain metal layer SD will decrease. Thus, whether the gate metal layer G and the source-drain metal layer SD in the liquid crystal display panel 100 are offset or not, the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 can be kept at a dynamically stable value.

[0209] Similarly, in the case of the leftward offset of the source-drain metal layer SD, the overlapping area between the normal projection of the first part 01 of the first signal line L (the second line segment L12) of the metal layer G on the first substrate 11 and the normal projection of the third part 03 (the first electrode s of the driving transistor TD) of the first conductive part W on the first substrate 11 will decrease in the second sub-display area AA2, but the overlapping area between the normal projection of the second part 02 of the first signal line L (the second line segment L12) of the metal layer G on the first substrate 11 and the normal projection of the fourth part 04 of the first conductive part W on the first substrate 11 will increase. Thus, no matter whether the offset occurs between the gate metal layer G and the source-drain metal layer SD in the liquid crystal display panel 100, the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2 can be kept at a dynamically stable value.

[0210] In summary, since the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 can be kept at a dynamically stable value, and the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2 can be kept at a dynamically stable value, the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the display area AA of the liquid crystal display panel 100 can be kept at a dynamically stable value, so as to improve the problem that the capacitance value of the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 of the liquid crystal display panel 100 is too different from the capacitance value of the coupling capacitance formed between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2.

[0211] In some embodiments, as shown in FIGS. 25-26, the normal projection of the fourth part 04 of the first connecting part E on the first substrate 11 is located in the boundary of the normal projection of the second part 02 of the first signal line L1 on the first substrate 11.

[0212] Since the second portion 02 of the first signal line L1 is located on the gate metal layer G, and the fourth portion 04 of the first connecting portion E is located on the source-drain metal layer SD, the second portion 02 of the first signal line L1 is located between the fourth portion 04 of the first connecting portion E and the first substrate 11. That is, the second portion 02 of the first signal line L1 is located below the fourth portion 04 of the first connecting portion E. Based on this, the fourth portion 04 of the first connecting portion E is arranged such that a projection of the fourth portion 04 of the first connecting portion E on the first substrate 11 is located within a projection of the second portion 02 of the first signal line L1 on the first substrate 11, which can prevent a part of the fourth portion 04 of the first connecting portion E from being provided with the second portion 02 of the first signal line L1 between the first substrate 11, and another part of the fourth portion 04 of the first connecting portion E from being provided without the second portion 02 of the first signal line L1 between the first substrate 11, which can prevent the fourth portion 04 of the first connecting portion E from being uneven below, and can prevent the fourth portion 04 of the first connecting portion E from being prone to climbing and causing various problems, so as to improve the yield of the fourth portion 04 of the first connecting portion E.

[0213] In some embodiments, the length of the fourth portion 04 of the first connecting portion E in the first direction X is greater than or equal to 2 μm.

[0214] When the length of the fourth portion 04 of the first connecting portion E in the first direction X is equal to or close to 2 μm, the length of the fourth portion of the first connecting portion E can be made larger. This can prevent the fourth portion 04 of the first connecting portion E located in the first sub-display area AA1 from being close to the edge of the second sub-display area AA2 on the first substrate 11, which is located within the projection of the gap B of the first signal line L (the first line segment L11) on the first substrate 11, and which can cause the projection of the fourth portion 04 of the first connecting portion E on the first substrate 11 to be non-overlapping with the projection of the second portion 02 of the first signal line L1 (the first line segment L11) on the first substrate 11, which can affect the formation of the coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1. Similarly, this can prevent the fourth portion 04 of the first connecting portion E located in the second sub-display area AA2 from being close to the edge of the first sub-display area AA1 on the first substrate 11, which is located within the projection of the gap B of the first signal line L (the second line segment L12) on the first substrate 11, and which can cause the projection of the fourth portion 04 of the first connecting portion E on the first substrate 11 to be non-overlapping with the projection of the second portion 02 of the first signal line L1 (the second line segment L12) on the first substrate 11, which can affect the formation of the coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2.

[0215] Therefore, the length of the fourth portion 04 of the first connecting portion E is greater than or equal to 2 μm. The coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the display area AA of the liquid crystal display panel 100 can be dynamically stabilized at a certain value, so as to improve the problem that the coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the first sub-display area AA1 of the liquid crystal display panel 100 is too different from the coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the second sub-display area AA2.

[0216] In some examples, the length of the fourth portion 04 of the first connecting portion E along the first direction X is greater than or equal to 3 μm. The length of the fourth portion of the first connecting portion E can be further increased, so as to ensure that the orthographic projection of the fourth portion of the first connecting portion E on the first substrate 11 can overlap with the orthographic projection of the first signal line L1 on the first substrate 11, so that the coupling capacitance between the gate metal layer G and the source-drain metal layer SD in the display area AA of the liquid crystal display panel 100 can be dynamically stabilized at a certain value.

[0217] For example, the length of the fourth portion 04 of the first connecting portion E along the first direction X is about any one of 2 μm, 2.5 μm, 3 μm or 3.5 μm. However, the embodiments of the present disclosure are not limited thereto.

[0218] It should be noted that the length of the fourth portion 04 of the first connecting portion E along the first direction X is about 2.5 μm. Due to uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), when the length of the fourth portion 04 of the first connecting portion E is within the range of ±10%×2.5 μm, it can also be considered that the length of the fourth portion 04 of the first connecting portion E satisfies 2.5 μm.

[0219] FIG. 28 is another layout structure diagram of the display panel of FIG. 6, FIG. 29 is a structure diagram of a support layer in FIG. 28, and FIG. 30 is a structure diagram of a stack of a gate metal layer, an active layer, a source-drain metal layer and the support layer in FIG. 28. The liquid crystal display panel shown in FIG. 28 is different from the liquid crystal display panel shown in FIG. 17 in that the liquid crystal display panel 100 shown in FIG. 28 shows a support layer 23, and other film layers in the liquid crystal display panel 100 can have the same structure as the other film layers shown in the liquid crystal display panel shown in FIG. 17. Therefore, the structures of the other film layers in the liquid crystal display panel shown in FIG. 28 except the support layer can be referred to the structures of the other film layers in the liquid crystal display panel shown in FIG. 17.

[0220] In some embodiments, as shown in FIGS. 28-30, the liquid crystal display panel 100 further comprises a support layer 23, the support layer 23 comprises a plurality of support portions 230, the plurality of support portions 230 are located between the array substrate 10 and the counter substrate 20 to support the array substrate 10 and the counter substrate 20.

[0221] The plurality of support portions 230 comprise a plurality of first support portions 231 and a plurality of second support portions 232, the plurality of first support portions 231 are located in the first display area AA and the second display area AA2, and the plurality of second support portions 232 are located at the position where the first display area AA and the second display area AA2 meet (the reference line O), that is, the orthographic projection of the plurality of second support portions 232 on the first substrate 11 is located in the orthographic projection of the first gap Q on the first substrate 11.

[0222] In this way, the plurality of first support portions 231 and the plurality of second support portions 232 are distributed in different areas of the liquid crystal display panel 100, so as to improve the support force of the plurality of support portions 230 and prevent the problem of uneven stress caused by the absence of support portions 230 in a certain area of the liquid crystal display panel 100, thereby affecting the quality of the liquid crystal display panel 100.

[0223] In some examples, as shown in FIGS. 23, 28-30, the orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps the orthographic projection of the driving transistor TD on the first substrate 11.

[0224] In this way, the first support portion 231 and the driving transistor TD are arranged oppositely, so as to prevent the first support portion 231 from affecting the light output of the liquid crystal display panel 100 and affecting the aperture ratio of the liquid crystal display panel 100.

[0225] The orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps the orthographic projection of the driving transistor TD on the first substrate 11, which can include the following three arrangement modes.

[0226] Firstly, the orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps the orthographic projection of the driving transistor TD on the first substrate 11.

[0227] Secondly, the boundary of the orthographic projection of the first support portion 231 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the driving transistor TD on the first substrate 11.

[0228] Thirdly, the orthographic projection of the first support portion 231 on the first substrate 11 is located in the boundary of the orthographic projection of the driving transistor TD on the first substrate 11.

[0229] The first support portion 231 can overlap the driving transistor TD in a direction perpendicular to the first substrate in any of the three arrangements of the driving transistor TD, so as to reduce the influence of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100. In the third arrangement, the orthographic projection of the driving transistor TD on the first substrate completely covers the orthographic projection of the first support portion 231 on the first substrate, so as to better reduce the influence of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100.

[0230] In some examples, as shown in FIGS. 23, 28-30, the orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0231] In this way, the first support portion 231 and the third light shielding portion 213 are arranged oppositely, so as to prevent the first support portion 231 from affecting the light emission of the liquid crystal display panel 100 and affecting the aperture ratio of the liquid crystal display panel 100.

[0232] The orthographic projection of the first support portion 231 on the first substrate 11 at least partially overlaps the orthographic projection of the third light shielding portion 213 on the first substrate 11 can include the following three arrangements.

[0233] Firstly, the orthographic projection of the first support portion 231 on the first substrate 11 partially overlaps the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0234] Secondly, the boundary of the orthographic projection of the first support portion 231 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0235] Thirdly, the orthographic projection of the first support portion 231 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0236] The first support portion 231 can overlap the third light shielding portion 213 in a direction perpendicular to the first substrate in any of the three arrangements of the first support portion 231 and the third light shielding portion 213, so as to reduce the influence of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100. In the third arrangement, the orthographic projection of the third light shielding portion 213 on the first substrate completely covers the orthographic projection of the first support portion 231 on the first substrate, so as to better reduce the influence of the first support portion 231 on the aperture ratio of the liquid crystal display panel 100.

[0237] In some examples, as shown in FIGS. 28-30, the second support portion 232 and the plurality of first support portions 231 are arranged along the first direction X. Along the first direction X, the distance between two adjacent first support portions 231 is d1, and the distance between an adjacent first support portion 231 and the second support portion 232 is d2. Here, |d2-d1|≤0.1d1.

[0238] In this way, the distance d2 between the adjacent first support portion 231 and the second support portion 232 is smaller than the distance d1 between any two adjacent first support portions 231, and the ratio of the distance d2 to the distance d1 is less than or equal to 0.1. Thus, the distance d2 between the adjacent first support portion 231 and the second support portion 232 is smaller than the distance d1 between any two adjacent first support portions 231, and the support layer 23 can provide a more uniform support force.

[0239] In some examples, as shown in FIGS. 28-30, the second support portion 232 and the plurality of first support portions 231 are arranged along the first direction X. Along the first direction X, the distance between two adjacent first support portions 231 is d1, and the distance between an adjacent first support portion 231 and the second support portion 232 is d2, 0μm≤d2-d1≤2μm.

[0240] In this way, the distance d2 between the adjacent first support portion 231 and the second support portion 232 is smaller than the distance d1 between any two adjacent first support portions 231, and the ratio of the distance d2 to the distance d1 is less than or equal to 0.1. Thus, the distance d2 between the adjacent first support portion 231 and the second support portion 232 is smaller than the distance d1 between any two adjacent first support portions 231, and the support layer 23 can provide a more uniform support force.

[0241] It should be noted that the distance between the plurality of first sub-pixel regions P01 in the first sub-display area AA1 and the plurality of second sub-pixel regions P02 in the second sub-display area AA2 can be adjusted to satisfy the following conditions: the orthogonal projection of the second support portion 232 on the first substrate 11 is located within the boundary of the orthogonal projection of the first gap Q on the first substrate 11, and 0μm≤d2-d1≤2μm. In this way, the support layer 23 can provide a more uniform support force, and the width of the first gap Q can be prevented from being too large, which can prevent the width of the corresponding first light shielding portion 211 from being too large and causing the liquid crystal display panel 100 to have a black line.

[0242] The inventor has found that the liquid crystal display panel 100 mainly uses nematic liquid crystal. However, when the operating temperature of the liquid crystal display exceeds the working temperature range (Tsn-Tni) of the liquid crystal display, the liquid crystal display panel 100 cannot normally operate.

[0243] FIG. 31 is another layout structure diagram of the display panel of FIG. 6, FIG. 32 is a sectional view in the H1-H1' direction of FIG. 31, FIG. 33 is a sectional view in the H2-H2' direction of FIG. 31, FIG. 34 is a sectional view in the H3-H3' direction of FIG. 31, and FIG. 35 is a sectional view in the H4-H4' direction of FIG. 31.

[0244] Based on this, in some embodiments, as shown in FIGS. 31-35, the array substrate 10 of the liquid crystal display panel 100 can further include a first metal layer 14, which is located between the source-drain metal layer SD and the common electrode layer 12. At this time, the array substrate 10 includes a first substrate 11, and the gate metal layer G, the active layer Act, the source-drain metal layer SD, the first metal layer 14, the common electrode layer 12, and the pixel electrode layer 13 are stacked on the first substrate 11. The first metal layer 14 is configured to provide heat to the liquid crystal layer.

[0245] In this way, the first metal layer 14 can be used to provide heat to the liquid crystal layer 30 in the liquid crystal display panel 100, so that the liquid crystal layer 30 in the liquid crystal display panel 100 can be in the working temperature range of the liquid crystal display, thereby improving the problem that the liquid crystal in the liquid crystal layer 30 cannot normally operate due to temperature problems in the liquid crystal display panel 100.

[0246] In some examples, the first metal layer 14 can be applied with a driving current, and the first metal layer 14 generates corresponding heat when the driving current flows through it, so as to provide heat to the liquid crystal layer 30.

[0247] It should be noted that the working temperature range of the liquid crystal display of the liquid crystal layer 30 in the liquid crystal display panel 100 can be Tsn-Tni. Tsn is the transition temperature from the smectic phase to the nematic phase of the liquid crystal, and Tni is the temperature at which the nematic phase of the liquid crystal changes to the liquid state.

[0248] In some examples, the working temperature range of the liquid crystal display of the liquid crystal layer 30 in the liquid crystal display panel 100 can be -20°C-75°C. The first metal layer 14 is configured to provide heat to the liquid crystal layer, so that the liquid crystal in the liquid crystal layer 30 in the liquid crystal display panel 100 is in a working environment of -20°C-75°C, thereby improving the problem that the liquid crystal display panel 100 cannot normally operate due to temperature.

[0249] In addition, the first metal layer 14 is arranged between the source-drain metal layer SD and the common electrode layer 12, and the orthographic projections of the first metal layer 14, the common electrode layer 12 and the liquid crystal layer 30 on the first substrate 11 have an overlapping region.

[0250] Based on this, the common electrode layer 12 is arranged between the first metal layer 14 and the liquid crystal layer 30, so that the common electrode layer 12 plays a role of isolating the first metal layer 14 and the liquid crystal layer 30, preventing the liquid crystal in the liquid crystal layer 30 from deflecting due to the electric field generated by the first metal layer 14 when flowing through the driving current, and further preventing the problem of light leakage of the liquid crystal display panel 100.

[0251] In some examples, the orthographic projection of the first metal layer 14 on the first substrate 11 is located within the boundary of the orthographic projection of the common electrode layer 12 on the first substrate 11.

[0252] In this way, the common electrode layer 12 can completely cover the first metal layer 14, preventing the liquid crystal in the liquid crystal layer 30 from deflecting due to the electric field generated by the first metal layer 14, and further preventing the problem of light leakage of the liquid crystal display panel 100.

[0253] In some embodiments, as shown in FIGS. 31-35, the first metal layer 14 includes a plurality of first wires 141, and one first wire 141 is arranged corresponding to one pixel unit P to provide heat to the liquid crystal at the corresponding position of the pixel unit P.

[0254] The arrangement of the first wire 141 corresponding to one pixel unit P can include the following two arrangements.

[0255] First, the pixel unit P can include a plurality of sub-pixel regions P0, and the orthographic projection of one first wire 141 on the first substrate 11 is located between the orthographic projections of two adjacent pixel units P on the first substrate.

[0256] In this way, the first wire 141 is arranged corresponding to one pixel unit P on the side of the outermost sub-pixel region P0 of the pixel unit P adjacent to the adjacent pixel unit. In other words, the first wire 141 is arranged along the edge of the outermost sub-pixel region P0 of the pixel unit P. Based on this, the first wire 141 can provide heat to the liquid crystal at the corresponding position of the pixel unit P, and can also reduce the influence of the first wire 141 on the aperture ratio of the sub-pixel region P0 in the pixel unit P.

[0257] Second, the pixel unit P can include a plurality of sub-pixel regions P0. A first run 141 on the first substrate 11 in orthographic projection is located between any two adjacent sub-pixel regions P0 in a pixel unit P. In this way, the first run 141 on the first substrate 11 in orthographic projection can be prevented from overlapping with the opening area of any sub-pixel region P0 in the pixel unit P in orthographic projection on the first substrate 11, thereby preventing the problem of reducing the aperture ratio of the sub-pixel region P0 in the pixel unit P.

[0258] For example, in the first direction X, the plurality of sub-pixel regions P0 in a pixel unit P can be a first color sub-pixel region, a second color sub-pixel region, and a third color sub-pixel region in sequence. For example, the first color sub-pixel region can emit red light, the second color sub-pixel region can emit green light, and the third color sub-pixel region can emit blue light.

[0259] The first run 141 on the first substrate 11 in orthographic projection can be located between the first substrate 11 in orthographic projection of the second color sub-pixel region and the third color sub-pixel region in the pixel unit P. Alternatively, the first run 141 on the first substrate 11 in orthographic projection can be located between the first substrate 11 in orthographic projection of the first color sub-pixel region and the second color sub-pixel region in the pixel unit P.

[0260] In this way, the first run 141 can not only provide heat to the liquid crystal at the corresponding position of the pixel unit P, but also reduce the influence of the first run 141 on the aperture ratio of the sub-pixel region P0 in the pixel unit P.

[0261] In some embodiments, as shown in FIGS. 31-35, the first run 141 on the first substrate 11 in orthographic projection does not overlap with the driving transistor TD of any sub-pixel region P0 in orthographic projection on the first substrate 11.

[0262] Since a first run 141 is arranged corresponding to a pixel unit P, rather than a sub-pixel region P0 corresponding to a first run 141. By arranging the first run 141 on the first substrate 11 in orthographic projection to not overlap with the driving transistor TD of any sub-pixel region P0 in orthographic projection on the first substrate 11, the problem of the first run 141 passing through the driving transistor TD of a certain sub-pixel region P0 in a certain pixel unit P, causing the temperature of the driving transistor TD to be higher than the temperature of other sub-pixel regions P0, and causing display abnormalities due to the different heating of the driving transistor TD in different sub-pixel regions P0, can be prevented.

[0263] In some embodiments, as shown in FIGS. 31-35, the first trace 141 is disposed opposite the second signal line L2. That is, the first trace 141 is disposed along the extension direction of the second signal line L2, and the orthogonal projection of the first trace 141 on the first substrate 11 at least partially overlaps the orthogonal projection of the second signal line L2 on the first substrate 11.

[0264] In this way, by concentrating the first trace 141 and the second signal line L2, the orthogonal projection of the second light-blocking portion 212 on the first substrate 11 can cover the orthogonal projections of the first trace 141 and the second signal line L2 on the first substrate 11 without increasing the width of the second light-blocking portion 212, thereby preventing light leakage at the positions of the first trace 141 and the second signal line L2.

[0265] In this way, by concentrating the first trace 141 and the second signal line L2, the orthogonal projection of the second light-blocking portion 212 on the first substrate 11 can cover the orthogonal projections of the first trace 141 and the second signal line L2 on the first substrate 11 without increasing the width of the second light-blocking portion 212, thereby preventing light leakage at the positions of the first trace 141 and the second signal line L2.

[0266] First, the orthogonal projection of the first trace 141 on the first substrate 11 partially overlaps the orthogonal projection of the second signal line L2 on the first substrate 11.

[0267] Second, the boundary of the orthogonal projection of the first trace 141 on the first substrate 11 substantially coincides with the boundary of the orthogonal projection of the second signal line L2 on the first substrate 11.

[0268] Third, the orthogonal projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthogonal projection of the first trace 141 on the first substrate 11.

[0269] In the above three arrangements of the first trace 141 and the second signal line L2, the width of the first trace 141 gradually increases. However, the embodiments of the present disclosure are not limited thereto, and the width of the first trace 141 can be adjusted according to actual needs.

[0270] In some embodiments, as shown in FIGS. 31-35, the orthogonal projection of the first trace 141 on the first substrate 11 is located within the boundary of the orthogonal projection of the second light-blocking portion 212 on the first substrate 11.

[0271] In this way, the second light shielding portion 212 can completely cover the projection of the first trace 141 on the first substrate 11, so that the second light shielding portion 212 can shield light to prevent light leakage at the position of the first trace 141. It can be understood that the maximum width of the first trace 141 can be equal to the width of the second light shielding portion 212, so that the projection of the first trace 141 on the first substrate 11 does not overlap with the projection of the second light shielding portion 212 on the first substrate 11, and the second light shielding portion 212 can completely shield the first trace 141 to prevent light leakage.

[0272] In some embodiments, as shown in FIGS. 31-35, when the first trace 141 is arranged along the extension direction of the second signal line L2, one of the first traces 141 can be arranged on the side of the column of pixel units P away from the first reference line O, and the first reference line O is the boundary between the first sub-display area AA1 and the second sub-display area AA2.

[0273] In this way, the first gap Q can not be provided with the first trace 141, and the projection of all the first traces 141 on the first substrate 11 can be located within the boundary of the projection of the common electrode layer 12 on the first substrate 11, so that the electric field generated by the first metal layer 14 does not cause the liquid crystal in the liquid crystal layer 30 to deflect, thereby preventing the liquid crystal display panel 100 from leaking light. In addition, the width of the first light shielding portion 211 does not need to be increased to prevent light leakage at the position of the first gap Q, and the problem of black lines in the liquid crystal display panel 100 can be reduced.

[0274] In other embodiments, the first trace 141 is arranged opposite to the first signal line L1. That is, the first trace 141 is arranged along the extension direction of the first signal line L1, and the projection of the first trace 141 on the first substrate 11 at least partially overlaps with the projection of the first signal line L1 on the first substrate 11.

[0275] In this way, the first trace 141 and the first signal line L1 are arranged together, and the projection of the second light shielding portion 212 on the first substrate 11 can cover the projections of the first trace 141 and the first signal line L1 on the first substrate 11 without increasing the width of the second light shielding portion 212, so that the first trace 141 and the first signal line L1 do not leak light.

[0276] The projection of the first trace 141 on the first substrate 11 at least partially overlaps with the projection of the first signal line L1 on the first substrate 11, and includes the following three arrangements.

[0277] The first type: the orthographic projection of the first trace 141 on the first substrate 11 partially overlaps the orthographic projection of the first signal line L1 on the first substrate 11.

[0278] The second type: the boundary of the orthographic projection of the first trace 141 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the first signal line L1 on the first substrate 11.

[0279] The third type: the orthographic projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthographic projection of the first trace 141 on the first substrate 11.

[0280] In the above three types of arrangement of the first trace 141 and the first signal line L1, the width of the first trace 141 gradually increases. However, the embodiments of the present disclosure are not limited thereto, and the width of the first trace 141 can be adjusted according to actual needs.

[0281] It should be noted that in the case where the first trace 141 is arranged along the extension direction of the first signal line L1, the first trace 141 also needs to be disconnected at the reference line O position. So that the part of the first trace 141 located in the first sub-display area AA1 corresponds to the first line segment L11, and the part of the first trace 141 located in the second sub-display area AA2 corresponds to the second line segment L12. In order to prevent the part of the first trace 141 corresponding to the first gap Q from being unable to be shielded by the common electrode layer 12, and causing the liquid crystal at the position corresponding to the first gap Q to deflect, resulting in the problem of light leakage.

[0282] In some embodiments, in the case where the first trace 141 is arranged opposite to the first signal line L1, the orthographic projection of the first trace 141 on the first substrate 11 can be arranged within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0283] In this way, the orthographic projection of the first trace 141 on the first substrate 11 can be completely covered by the orthographic projection of the third light shielding portion 213 on the first substrate 11, so as to use the third light shielding portion 213 to shield light, thereby preventing the problem of light leakage at the position of the first trace 141. It can be understood that the maximum value of the width of the first trace 141 can be the width value of the third light shielding portion 213, so as to prevent the problem that part of the first trace 141 is not overlapped with the orthographic projection of the third light shielding portion 213 on the first substrate 11, and the third light shielding portion 213 cannot completely shield the first trace 141 from light leakage.

[0284] In some embodiments, the plurality of first traces 141 in the first metal layer 14 can form a mesh structure. That is, the plurality of first traces 141 includes two portions of first traces 141, one portion corresponding to the first signal line L1 and the other portion corresponding to the second signal line L2. In this way, the first traces 141 in the first metal layer 14 can be evenly distributed to achieve uniform heating of the liquid crystal in the liquid crystal layer 30. However, the embodiments of the present disclosure are not limited thereto.

[0285] It should be noted that for the above-mentioned arrangement of the first traces 141 corresponding to the first signal line L1 only or the arrangement of the first traces 141 corresponding to the second signal line L2 only, the plurality of first traces 141 can be connected in series with each other, which can facilitate the transmission of the driving current to the first traces 141. In addition, it can also be beneficial to the layout of the traces at the peripheral area of the liquid crystal display panel 100. For example, four first traces 141 can be connected in series with each other. Based on this, the number of traces in the peripheral area 75% of the liquid crystal display panel 100 can be reduced, and the driving current can be transmitted to each of the first traces 141. However, the embodiments of the present disclosure are not limited thereto.

[0286] In some embodiments, as shown in FIGS. 31-35, the array substrate 10 can further include a first insulating layer 15 between the gate metal layer G and the active layer Act, so that the gate metal layer G and the active layer Act are electrically insulated by the first insulating layer 15.

[0287] For example, the material of the first insulating layer includes any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first insulating layer can also include silicon dioxide, and the present disclosure is not limited thereto.

[0288] The array substrate 10 can further include a second insulating layer, which can be an organic layer 16 between the source-drain metal layer SD and the first metal layer 14, so that the source-drain metal layer SD and the first metal layer 14 are electrically insulated by the organic layer 16.

[0289] For example, the organic layer 16 can include at least one of a photosensitizer, an acrylic resin, and an organic solvent. However, the embodiments of the present disclosure are not limited thereto.

[0290] In addition, compared with the arrangement of the second insulating layer being an insulating layer composed of any one of inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide, the dielectric constant 3.2 of the organic layer 16 can be significantly lower than the dielectric constant 6.5 of the insulating layer (SiNx).

[0291] In addition, since the orthographic projection of the source-drain metal layer SD on the first substrate 11 overlaps with the orthographic projection of the first metal layer 14 on the first substrate 11, a coupling capacitor is formed between the source-drain metal layer SD and the first metal layer 14. According to the formula C = εS / 4πkd, it can be known that the smaller the dielectric constant ε of the second insulating layer, the smaller the coupling capacitor formed between the source-drain metal layer SD and the first metal layer 14, so as to improve the problem of increased load of the source-drain metal layer SD and the first metal layer 14. That is, compared with the case where the second insulating layer is composed of any one of the inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, the second insulating layer being the organic layer 16 can effectively reduce the coupling capacitor formed between the source-drain metal layer SD and the first metal layer 14, and improve the problem of increased load of the two.

[0292] In some examples, k is a constant, d is the thickness of the second insulating layer (the organic layer 16), and S is the overlapping area, which can include the overlapping area formed by the orthographic projection of the first electrode s and the second electrode d of the driving transistor TD in the source-drain metal layer SD on the first substrate 11 and the orthographic projection of the first trace 141 in the first metal layer 14 on the first substrate 11.

[0293] Based on this, compared with the case where the second insulating layer is composed of any one of the inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, the second insulating layer being the organic layer 16 can effectively reduce the coupling capacitor formed between the driving transistor TD and the first trace 141, reduce the load of the driving transistor TD, and improve the stability of the driving transistor TD.

[0294] In addition, the overlapping area can also include the overlapping area formed by the orthographic projection of the second signal line L2 in the source-drain metal layer SD on the first substrate 11 and the orthographic projection of the first trace 141 in the first metal layer 14 on the first substrate 11.

[0295] Based on this, compared with the case where the second insulating layer is composed of any one of the inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, the second insulating layer being the organic layer 16 can effectively reduce the coupling capacitor formed between the second signal line L2 and the first trace 141, reduce the load of the second signal line L2, and reduce the problem of display failure of the liquid crystal display panel 100.

[0296] In other examples, k is a constant, d is the thickness of the second insulating layer (the organic layer 16), and S is the overlapping area, which can be the overlapping area formed by the orthographic projection of the first electrode s and the second electrode d of the driving transistor TD in the source-drain metal layer SD on the first substrate 11 and the orthographic projection of the common electrode (the first common electrode C1 or the second common electrode C2) in the common electrode layer 12 on the first substrate 11.

[0297] Based on this, compared with the case where the second insulating layer is an insulating layer composed of any one of inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, the second insulating layer is set as the organic layer 16, which can effectively reduce the coupling capacitance formed between the drive transistor TD and the common electrode (the first common electrode C1 or the second common electrode C2), reduce the load of the drive transistor TD, and improve the stability of the drive transistor TD.

[0298] In addition, the overlapping area can further include an overlapping area formed between a normal projection of the second signal line L2 on the first substrate 11 in the source-drain metal layer SD and a normal projection of the common electrode (the first common electrode C1 or the second common electrode C2) on the first substrate 11 in the common electrode layer 12.

[0299] Based on this, compared with the case where the second insulating layer is an insulating layer composed of any one of inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, the second insulating layer is set as the organic layer 16, which can effectively reduce the coupling capacitance formed between the second signal line L2 and the common electrode (the first common electrode C1 or the second common electrode C2), reduce the load of the second signal line L2, and reduce the display problems of the liquid crystal display panel 100.

[0300] In some examples, when the second insulating layer is an insulating layer composed of any one of inorganic insulating materials of silicon nitride, silicon nitride oxide and silicon oxide, due to the limitation of the material, in order to prevent the second insulating layer from being separated, the thickness of the second insulating layer is about 100 nm to 300 nm. When the second insulating layer is the organic layer 16, the thickness of the second insulating layer (the organic layer 16) is about 100 nm to 300 nm.

[0301] When the thickness of the organic layer 16 is within the range of 100 nm to 300 nm, the thickness of the organic layer 16 can be relatively thick, which can facilitate increasing the spacing between the source-drain metal layer SD and the first metal layer 14, preventing the coupling capacitance from being formed between the source-drain metal layer SD and the first metal layer 14, and preventing the load from being increased to affect the display. In addition, the spacing between the source-drain metal layer SD and the common electrode layer 12 can also be increased, preventing the coupling capacitance from being formed between the source-drain metal layer SD and the common electrode layer 12, and preventing the load from being increased to affect the display. In some examples, the thickness of the organic layer 16 can be about 100 nm to 300 nm.

[0302]

[0303] ​In this way, the thickness of the organic layer 16 can be thickened to increase the distance between the source-drain metal layer SD and the first metal layer 14 and the common electrode layer 12, so as to reduce the coupling capacitance formed between the source-drain metal layer SD and the first metal layer 14 and the common electrode layer 12, and meanwhile, the process requirement for manufacturing the organic layer 16 can be met.

[0304] For example, the thickness of the organic layer 16 is about 1000 nm. However, the embodiments of the present disclosure are not limited thereto.

[0305] It should be noted that due to certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), the thickness of the organic layer 16 is about 1000 nm. For example, the thickness of the organic layer 16 is about 1000 nm. For example, the thickness of the organic layer 16 is about 1000 nm.

[0306] In some embodiments, as shown in FIGS. 31-35, when the second insulating layer is the organic layer 16, the array substrate 10 can further include a first protective layer (not shown in the figure) and a second protective layer (not shown in the figure), and the first protective layer and the second protective layer are respectively located on both sides of the organic layer 16.

[0307] In some examples, the material of the first protective layer includes any one of inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide. The material of the first protective layer can also include silicon dioxide, and the present disclosure is not limited thereto.

[0308] In some examples, the material of the second protective layer includes any one of inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide. The material of the second protective layer can also include silicon dioxide, and the present disclosure is not limited thereto.

[0309] The adhesion between the first protective layer and the second protective layer and the metal layer is better than the adhesion between the organic layer 16 and the metal layer. Based on this, the first protective layer is arranged between the source-drain metal layer SD and the organic layer 16, so as to improve the adhesion between the source-drain metal layer SD and the organic layer 16 by using the first protective layer, thereby improving the stability between the source-drain metal layer SD and the organic layer 16.

[0310] In addition, the second protective layer can be arranged between the organic layer 16 and the first metal layer 14, so as to improve the adhesion between the organic layer 16 and the first metal layer 14 by using the second protective layer, thereby improving the stability between the organic layer 16 and the first metal layer 14.

[0311] In some examples, the thickness of the first protective layer can be in a range of 100 nm to 1000 nm. When the thickness of the first protective layer is within the range of When the thickness of the first protective layer is within the range of

[0312] For example, the thickness of the first protective layer is about or However, the embodiments of the present disclosure are not limited thereto.

[0313] It should be noted that due to the existence of certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), the thickness of the first protective layer is about For example, the thickness of the first protective layer is within the range of When the thickness of the first protective layer is within the range of

[0314] In some examples, the thickness of the second protective layer can be within the range of When the thickness of the second protective layer is within the range of When the thickness of the second protective layer is within the range of

[0315] For example, the thickness of the second protective layer is about or However, the embodiments of the present disclosure are not limited thereto.

[0316] It should be noted that due to the existence of certain uncontrollable errors (such as manufacturing process errors, equipment precision, measurement errors, etc.), the thickness of the second protective layer is about For example, the thickness of the second protective layer is within the range of When the thickness of the second protective layer is within the range of

[0317] In some embodiments, the array substrate 10 can further include a third insulating layer 17, the third insulating layer 17 is located between the first metal layer 14 and the common electrode layer 12, so as to electrically insulate the first metal layer 14 and the common electrode layer 12 by using the third insulating layer 17.

[0318] Exemplarily, the material of the third insulating layer 17 includes any one of inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide. The material of the first insulating layer can also include silicon dioxide, and the present disclosure is not limited thereto.

[0319] In some embodiments, the array substrate 10 can further include a fourth insulating layer 18 located between the common electrode layer 12 and the pixel electrode layer 13 to electrically insulate the common electrode layer 12 and the pixel electrode layer 13 by the third insulating layer 17.

[0320] Exemplarily, the material of the fourth insulating layer 18 includes any one of inorganic insulating materials of silicon nitride, silicon oxynitride and silicon oxide. The material of the first insulating layer can also include silicon dioxide, and the present disclosure is not limited thereto.

[0321] In some implementable manners, taking indium tin oxide as the material of the common electrode layer 12 as an example, the resistivity of the indium tin oxide is higher than that of the metal, thus resulting in a relatively large resistance of the first common electrode C1 and the second common electrode C1 in the common electrode layer 12, and further resulting in the crosstalk and the greenish phenomenon of the array substrate 10, which affects the picture quality of the liquid crystal display panel.

[0322] Based on this, in some embodiments, as shown in FIGS. 31-35, the array substrate 10 can further include an auxiliary electrode layer 19 located on the side of the common electrode layer 12 away from the first substrate 11, and the auxiliary electrode layer 19 is in contact with the common electrode layer 12.

[0323] In this way, the auxiliary electrode layer 19 can be in contact with the common electrode layer 12 to reduce the resistance of the common electrode layer 12. Thus, the problem of the voltage fluctuation of the first common electrode C1 and the second common electrode C2 in the common electrode layer 12 caused by the second signal line L2 can be reduced.

[0324] In addition, the auxiliary electrode layer 19 is directly formed on the side of the common electrode layer 12 away from the first substrate 11, which can realize the formation of the auxiliary electrode layer 19 without increasing the number of masks used for manufacturing the array substrate 10.

[0325] Specifically, the common electrodes (the first common electrode C1 and the second common electrode C2) of the common electrode layer 12 and the auxiliary electrodes 191 of the auxiliary electrode layer 19 can be formed by one photoetching process by using a half-tone mask (English full name: HalfTone Mask; English abbreviation: HTM).

[0326] In some examples, since the resistance of the metal material is smaller, the material of the auxiliary electrode layer 19 can adopt the metal material to further reduce the resistance of the common electrode layer 12.

[0327] Exemplarily, the metal material can include copper, aluminum, or the like. However, embodiments of the present disclosure are not limited thereto.

[0328] In some embodiments, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 is located within the boundary of the orthographic projection of the second light shielding portion 212 on the first substrate 11.

[0329] In this way, the orthographic projection of the second light shielding portion 212 on the first substrate 11 can completely cover the orthographic projection of the auxiliary electrode 191 on the first substrate 11, so that the second light shielding portion 212 can shield light to prevent light leakage at the position of the auxiliary electrode 191. It can be understood that the maximum value of the width of the auxiliary electrode 191 can be the width value of the second light shielding portion 212, so as to prevent the problem that part of the auxiliary electrode 191 is not overlapped with the orthographic projection of the second light shielding portion 212 on the first substrate 11, and thus the second light shielding portion 212 cannot completely shield the auxiliary electrode 191 from light leakage.

[0330] In some examples, the auxiliary electrode layer 19 includes a plurality of auxiliary electrodes 191, and the orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11.

[0331] In this way, by concentrating the auxiliary electrode 191 and the second signal line L2, the orthographic projection of the second light shielding portion 212 on the first substrate 11 can cover the orthographic projection of the auxiliary electrode 191 and the second signal line L2 on the first substrate 11 without increasing the width of the second light shielding portion 212, so as to prevent light leakage at the positions of the auxiliary electrode 191 and the second signal line L2.

[0332] In some examples, the auxiliary electrode layer 19 includes a plurality of auxiliary electrodes 191, and the orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11.

[0333] Firstly, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the second signal line L2 on the first substrate 11.

[0334] Secondly, the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11 substantially coincides with the boundary of the orthographic projection of the second signal line L2 on the first substrate 11.

[0335] Thirdly, the orthographic projection of the second signal line L2 on the first substrate 11 is located within the boundary of the orthographic projection of the auxiliary electrode 191 on the first substrate 11.

[0336] In the three setting modes of the auxiliary electrode 191 and the second signal line L2, the width of the auxiliary electrode 191 gradually increases. However, the embodiments of the present disclosure are not limited thereto, and the width of the auxiliary electrode 191 can be adjusted according to actual needs.

[0337] It should be noted that in the case where the auxiliary electrode 191 is arranged along the extension direction of the second signal line L2, the auxiliary electrode 191 also needs to be disconnected at the reference line O position. So that the part of the auxiliary electrode 191 located in the first sub-display area AA1 corresponds to the first line segment L11, and the part of the auxiliary electrode 191 located in the second sub-display area AA2 corresponds to the second line segment L12. In order to prevent the part of the auxiliary electrode 191 corresponding to the first gap Q from being unable to be shielded by the common electrode layer 12, and the problem of causing the liquid crystal at the position corresponding to the first gap Q to deflect, resulting in light leakage.

[0338] In other embodiments, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 is located within the boundary of the orthographic projection of the third light shielding portion 213 on the first substrate 11.

[0339] In this way, the orthographic projection of the auxiliary electrode 191 on the first substrate 11 can be completely covered by the orthographic projection of the third light shielding portion 213 on the first substrate 11, so as to use the third light shielding portion 213 to shield light, thereby preventing the problem of light leakage at the position of the auxiliary electrode 191. It can be understood that the maximum value of the width of the auxiliary electrode 191 can be the width value of the third light shielding portion 213, so as to prevent the problem that part of the auxiliary electrode 191 is not overlapped with the orthographic projection of the third light shielding portion 213 on the first substrate 11, resulting in the third light shielding portion 213 being unable to completely shield the auxiliary electrode 191 from light leakage.

[0340] In some examples, the auxiliary electrode 191 is arranged opposite to the first signal line L1. That is, the auxiliary electrode 191 is arranged along the extension direction of the first signal line L1, and the orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11.

[0341] In this way, by concentrating the auxiliary electrode 191 and the first signal line L1, the orthographic projection of the second light shielding portion 212 on the first substrate 11 can cover the orthographic projection of the auxiliary electrode 191 and the first signal line L1 on the first substrate 11 without increasing the width of the second light shielding portion 212, thereby preventing the problem of light leakage at the positions of the auxiliary electrode 191 and the first signal line L1.

[0342] The orthographic projection of the auxiliary electrode 191 on the first substrate 11 at least partially overlaps with the orthographic projection of the first signal line L1 on the first substrate 11, including the following three setting modes.

[0343] The first type: the orthogonal projection of the auxiliary electrode 191 on the first substrate 11 partially overlaps with the orthogonal projection of the first signal line L1 on the first substrate 11.

[0344] The second type: the boundary of the orthogonal projection of the auxiliary electrode 191 on the first substrate 11 substantially coincides with the boundary of the orthogonal projection of the first signal line L1 on the first substrate 11.

[0345] The third type: the orthogonal projection of the first signal line L1 on the first substrate 11 is located within the boundary of the orthogonal projection of the auxiliary electrode 191 on the first substrate 11.

[0346] In the above three types of arrangement of the auxiliary electrode 191 and the first signal line L1, the width of the auxiliary electrode 191 gradually increases. However, the embodiments of the present disclosure are not limited thereto, and the width of the auxiliary electrode 191 can be adjusted according to actual needs.

[0347] It should be noted that in the case where the auxiliary electrode 191 is arranged along the extension direction of the first signal line L1, the auxiliary electrode 191 also needs to be disconnected at the reference line O position. So that the part of the auxiliary electrode 191 located in the first sub-display area AA1 corresponds to the first line segment L11, and the part of the auxiliary electrode 191 located in the second sub-display area AA2 corresponds to the second line segment L12. In order to prevent the part of the auxiliary electrode 191 corresponding to the first gap Q from being unable to be shielded by the common electrode layer 12, and causing the liquid crystal at the position corresponding to the first gap Q to deflect, resulting in the problem of light leakage.

[0348] In yet some embodiments, the plurality of auxiliary electrodes 191 in the auxiliary electrode layer 19 can form a grid structure. That is, the plurality of auxiliary electrodes 191 include two parts of auxiliary electrodes 191, one part is arranged corresponding to the first signal line L1, and the other part is arranged corresponding to the second signal line L2. In this way, the auxiliary electrodes 191 in the first metal layer 14 can be uniformly arranged to uniformly heat the liquid crystal in the liquid crystal layer 30. However, the embodiments of the present disclosure are not limited thereto.

[0349] In some embodiments, as shown in FIG. 2 and FIG. 31, when the liquid crystal display panel 100 is a conventional liquid crystal display panel, for example, the shape of the liquid crystal display panel 100 is rectangular, the length of each first trace 141 can be set to be equal, and then the width of each first trace 141 can be set to be equal, so that the heat provided by each first trace 141 is substantially equal. In order to facilitate the first metal layer 14 to uniformly provide heat to the liquid crystal at each position in the liquid crystal layer of the liquid crystal display panel 100, and prevent the problem of display failure caused by uneven heating in the liquid crystal display panel 100.

[0350] FIG. 36 is a plan view of a display panel according to some embodiments.

[0351] In some embodiments, as shown in FIG. 31 and FIG. 36, the liquid crystal display panel 100 is a special-shaped liquid crystal display panel, and the plurality of first wires 141 includes at least two first wires 141 having different lengths along the second direction Y. In the two first wires 141 having different lengths, the length of the first first wire 141 is greater than the length of the second first wire 141, and the width of the first first wire 141 is greater than the width of the second first wire 141.

[0352] Since the heating effect of the first wire 141 depends on the heating power P, and the heating power of the first wire 141 is related to the resistance R of the first wire 141. Moreover, according to the calculation formula of the resistance R of the first wire 141, the length of the first wire 141 is inversely proportional to the width of the first wire 141. Wherein, W is the length of the first wire 141, L is the width of the first wire 141, and Rs is the sheet resistance of the first wire 141.

[0353] Therefore, the length of the first wire 141 can be set to be longer, so as to reduce the heating power of the first wire 141 by increasing the width of the first wire 141. That is, the width of the first wire 141 along the first direction X can be adjusted according to the length of the first wire 141 along the second direction Y, so as to reduce the difference between the resistances of any two first wires 141 and the difference between the heating powers of any two first wires 141, thereby improving the heating uniformity of the liquid crystal display panel 100.

[0354] It should be noted that the special-shaped liquid crystal display panel can be a non-rectangular liquid crystal display panel. For example, the display area AA in the special-shaped liquid crystal display panel 100 includes a special-shaped boundary S1, and the special-shaped boundary S1 is not straight. For example, the special-shaped boundary S1 can be an arc.

[0355] In some embodiments, the first sub-display area AA1 of the liquid crystal display panel 100 includes a plurality of regions in a direction away from the first reference line O, and the number of first wires 141 in each region is substantially equal.

[0356] When the length of the first wire 141 in each region gradually increases in a direction close to the first reference line O, the width of the first wire 141 in each region can be correspondingly set to gradually increase.

[0357] ​In this way, the resistance of the first wires 141 in the plurality of regions in the first sub-display area AA1 gradually changes, and the heating power of the first wires 141 in the plurality of regions in the first sub-display area AA1 gradually changes, so as to improve the heating uniformity of the liquid crystal display panel 100.

[0358] In addition, the second sub-display area AA2 can be set in the same way as the first sub-display area AA1. Details are not described herein.

[0359] In some embodiments, as shown in FIG. 31 and FIG. 36, in the plurality of first wires 141 arranged along the direction close to the first reference line O in the first sub-display area AA1 of the liquid crystal display panel 100, the length of the plurality of first wires 141 in the second direction Y gradually increases. The length of the plurality of first wires 141 in the second direction Y gradually increases, so as to gradually change the difference between the plurality of first wires 141, so as to prevent the difference between two adjacent first wires 141 from being too large, and thus causing the heating power difference between the two first wires 141 to be too large.

[0360] In addition, in the plurality of first wires 141 arranged along the direction close to the first reference line O in the first sub-display area AA1 of the liquid crystal display panel 100, the length of the plurality of first wires 141 in the second direction Y gradually increases, and the width of the plurality of first wires 141 in the first direction X can be correspondingly set to gradually increase.

[0361] That is, the width of the first wire 141 in the first direction X can be adjusted according to the length of the first wire 141 in the second direction Y, so as to reduce the resistance difference between two adjacent first wires 141, reduce the resistance difference between the plurality of first wires 141, and make the heating power of the plurality of first wires 141 substantially equal, which is beneficial to improve the heating uniformity of the first sub-display area AA1 of the liquid crystal display panel 100.

[0362] In addition, the second sub-display area AA2 can be set in the same way as the first sub-display area AA1. That is, in the plurality of first wires 141 arranged along the direction close to the first reference line O in the second sub-display area AA2, the length of the plurality of first wires 141 in the second direction Y gradually increases, and the width of the plurality of first wires 141 in the first direction X can be correspondingly set to gradually increase.

[0363] That is, the width of the first wire 141 in the first direction X can be adjusted according to the length of the first wire 141 in the second direction Y, so as to reduce the resistance difference between two adjacent first wires 141, reduce the resistance difference between the plurality of first wires 141, and make the heating power of the plurality of first wires 141 substantially equal, which is beneficial to improve the heating uniformity of the second sub-display area AA2 of the liquid crystal display panel 100.

[0364] The first wire 141 arranged in the first sub-display area AA1 and the second sub-display area AA2 as above can improve the heating uniformity of the liquid crystal display panel 100.

[0365] In some examples, as shown in FIGS. 31 and 36, the lengths of the plurality of first wires 141 gradually decrease in a direction away from the first reference line O. An example is taken in which the first sub-display area AA1 includes n first wires 141.

[0366] In the first sub-display area AA1: the first wire 141 farthest from the first reference line O is the first first wire 141_1, and the first wire 141 closest to the first reference line O is the nth first wire 141_n.

[0367] The length of the first first wire 141_1 is the shortest, Lmin, and the length of the nth first wire 141_n is the longest, Lmax. Based on this, the difference in length between two adjacent first wires 141 can be obtained based on the difference between the length of the nth first wire 141_n and the length of the first first wire 141_1. Wherein n is a positive integer.

[0368] For example, the difference between the length of the m-1th first wire and the length of the mth first wire is Wherein m is a positive integer, and m≤n+1.

[0369] Based on this, the lengths of the plurality of first wires 141 gradually increase in the arrangement direction of the plurality of first wires 141, which can gradually change the difference between the plurality of first wires 141 to prevent the difference between two adjacent first wires 141 from being too large, which can cause the heating power difference between the two first wires 141 to be too large.

[0370] It should be noted that the length Lmin of the first first wire 141_1 with the shortest length and the length Lmax of the nth first wire 141_n with the longest length can be limited according to the shape of the liquid crystal display panel 100. That is, the length of each first wire 141 can be matched with the shape of the liquid crystal display panel 100.

[0371] Correspondingly, in the first sub-display area AA1: the first wire 141 farthest from the first reference line O is the first first wire 141_1, and the first wire 141 closest to the first reference line O is the nth first wire 141_n.

[0372] The width of the first first trace 141_1 is Wmin, and the width of the nth first trace 141_n is Wmax. Based on this, the difference in width between two adjacent first traces 141 can be obtained based on the difference between the width of the nth first trace 141_n and the width of the first first trace 141_1. Wherein n is a positive integer.

[0373] For example, the difference between the width of the m-1th first trace and the width of the mth first trace is Wherein m is a positive integer, and m≤n+1.

[0374] Based on this, the width of the plurality of first traces 141 gradually increases along the arrangement direction of the plurality of first traces 141, which can gradually change the difference between the plurality of first traces 141 to prevent the difference between two adjacent first traces 141 from being too large, which can cause the heating power difference between the two first traces 141 to be too large.

[0375] It should be noted that the width Wmax of the nth first trace 141_n with the largest width can be approximately equal to the width of the second light shielding portion 212, so as to prevent the orthographic projection of the second light shielding portion 212 on the first substrate 11 from not being able to completely cover the first trace 141, which can cause the liquid crystal display panel 100 to leak light. The width Wmin of the first first trace 141_1 with the smallest width can be set according to the length Lmin of the first first trace 141_1, and the width Wmin of the first first trace 141_1 needs to meet the demand of the existing working precision.

[0376] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art can think of changes or replacements within the technical range disclosed in the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A liquid crystal display panel having a display area, along a first direction, the display area comprising adjacent first and second sub-display areas. The display panel comprises: an array substrate, a counter substrate, and a liquid crystal layer arranged between the array substrate and the counter substrate; The array substrate comprises: a first substrate; a plurality of pixel units arranged on the first substrate, each of the pixel units comprising at least one sub-pixel region, the plurality of pixel units comprising first pixel units arranged in the first sub-display region and second pixel units arranged in the second sub-display region; a plurality of first signal lines extending along the first direction, the first signal lines comprising first line segments and second line segments, the first line segments being electrically connected to the first pixel units, and the second line segments being electrically connected to the second pixel units; a common electrode layer comprising a first common electrode and a second common electrode, the first common electrode being arranged in the first sub-display region, the second common electrode being arranged in the second sub-display region, and the first common electrode and the second common electrode having a first gap extending along a second direction therebetween, the first direction and the second direction being intersected; the counter substrate comprises: a light shielding layer comprising a first light shielding portion, a projection of the first light shielding portion on the first substrate at least partially overlapping a projection of the first gap on the first substrate.

2. The liquid crystal display panel according to claim 1, wherein The projection of the first light shielding portion on the first substrate covers the projection of the first gap on the first substrate.

3. The liquid crystal display panel according to claim 1 or 2, wherein The array substrate further comprises: a plurality of second signal lines extending along the second direction and arranged along the first direction, one of the second signal lines being arranged on a side of a column of the sub-pixel regions away from a first reference line, the first reference line being a boundary line between the first sub-display region and the second sub-display region.

4. The liquid crystal display panel according to claim 3, wherein The sub-pixel region comprises: a driving transistor and a pixel electrode, a control electrode of the driving transistor being electrically connected to the first signal line, a first electrode of the driving transistor being electrically connected to the pixel electrode, and a second electrode of the driving transistor being electrically connected to the second signal line; the sub-pixel region in the first pixel unit is a first sub-pixel region, and the sub-pixel region in the second pixel unit is a second sub-pixel region; in the first sub-pixel region and the second sub-pixel region arranged along the first direction: the driving transistor in the first sub-pixel region and the driving transistor in the second sub-pixel region are mirror-symmetrical with respect to a second reference line, the second reference line being a center line of a line connecting the first sub-pixel region and the second sub-pixel region.

5. The liquid crystal display panel according to claim 4, wherein the pixel electrode is a dual-domain pixel electrode, the dual-domain pixel electrode comprising a first domain portion and a second domain portion, and the first domain portion and the second domain portion extending in intersected directions; a corner formed by the first domain portion and the second domain portion of the pixel electrode in any one of the first sub-pixel regions is a first corner, and a corner formed by the first domain portion and the second domain portion of the pixel electrode in any one of the second sub-pixel regions is a second corner, wherein the first corner and the second corner protrude towards one direction.

6. The liquid crystal display panel according to claim 4 or 5, wherein The array substrate further comprises a gate metal layer, an active layer, a source-drain metal layer and the pixel electrode layer which are stacked on the first substrate; the pixel electrode layer comprises a plurality of pixel electrodes, the common electrode layer is located between the source-drain metal layer and the pixel electrode layer, the common electrode layer comprises a plurality of vias, and the orthogonal projection of the pixel electrode on the common electrode layer covers the vias; The gate metal layer comprises the first signal line, along the first direction, the first signal line comprises a first part and a second part, the first part is multiplexed as the control electrode of the drive transistor, and the orthogonal projection of the via on the first substrate is located between the orthogonal projections of the first part and the second part on the first substrate; The source-drain metal layer comprises the second signal line, the second signal line comprises a first sub-part, the first sub-part of the second signal line is multiplexed as the second electrode of the drive transistor; the source-drain metal layer further comprises a first conductive part, the first conductive part comprises a third part and a fourth part, the third part is multiplexed as the first electrode of the drive transistor, and the orthogonal projection of the via on the first substrate is located between the orthogonal projections of the third part and the fourth part on the first substrate; The orthogonal projection of the second part of the first signal line on the first substrate at least partially overlaps with the orthogonal projection of the fourth part of the first conductive part on the first substrate.

7. The liquid crystal display panel according to claim 6, wherein The orthogonal projection of the fourth part of the first conductive part on the first substrate is located within the boundary of the orthogonal projection of the second part of the first signal line on the first substrate.

8. The liquid crystal display panel according to claim 7, wherein Along the first direction, the length of the fourth part of the first conductive part is greater than or equal to 2μm.

9. The liquid crystal display panel according to any one of claims 3-8, wherein The light shielding layer further comprises a plurality of second light shielding parts, the orthogonal projection of the second signal line on the first substrate is located within the boundary of the orthogonal projection of the second light shielding part on the first substrate; Along the first direction, the width of the first light shielding part is W1, the width of the second light shielding part is W2, and W1≤1.5W2. 10.The liquid crystal display panel of claim 9, further comprising a plurality of support portions between the array substrate and the counter substrate; wherein, The plurality of support parts comprise a first support part and a second support part, The sub-pixel region comprises a drive transistor, the orthogonal projection of the first support part on the first substrate at least partially overlaps with the orthogonal projection of the drive transistor on the first substrate; The orthogonal projection of the second support part on the first substrate is located within the orthogonal projection of the first slit on the first substrate, and the second support part and the plurality of first support parts are arranged along the first direction; Along the first direction, the distance between two adjacent first support parts is d1, the distance between the adjacent first support part and the second support part is d2, and |d2-d1|≤0.1d1.

11. The liquid crystal display panel according to any one of claims 1 to 10, wherein The pixel unit comprises a plurality of sub-pixel regions; the array substrate further comprises a gate metal layer, an active layer, a source-drain metal layer and a first metal layer which are stacked on the first substrate; The first metal layer is located between the source-drain metal layer and the common electrode layer, and the first metal layer comprises a plurality of first traces, a footprint of one of the first traces on the first substrate being located between footprints of any two adjacent sub-pixel regions in one of the pixel units on the first substrate.

12. The liquid crystal display panel according to claim 11, wherein, The sub-pixel region comprises a drive transistor, and a footprint of the first trace on the first substrate does not overlap with a footprint of the drive transistor on the first substrate.

13. The liquid crystal display panel according to claim 11 or 12, wherein, The array substrate further comprises a plurality of second signal lines extending along the second direction and arranged along the first direction. A footprint of the first trace on the first substrate at least partially overlaps with a footprint of the second signal line on the first substrate.

14. The liquid crystal display panel according to any one of claims 11 to 13, wherein The light-blocking layer further comprises a plurality of second light-blocking portions, and a footprint of the first trace on the first substrate is located within a boundary of a footprint of the second light-blocking portion on the first substrate.

15. The liquid crystal display panel according to any one of claims 11 to 14, wherein The array substrate further comprises an organic layer, and the organic layer is located between the source-drain metal layer and the first metal layer. The thickness of the organic layer is in the range of 1 to 100 nm 16. The liquid crystal display panel according to any one of claims 11 to 15, wherein The liquid crystal display panel is a special-shaped liquid crystal display panel, and at least two of the plurality of first traces have different lengths along the second direction. In the two first traces, a first one of the first traces has a length greater than that of a second one of the first traces, and the first one of the first traces has a line width greater than that of the second one of the first traces.

17. The liquid crystal display panel according to claim 16, wherein In the first sub-display region or the second sub-display region, among the plurality of first traces arranged along a direction close to a first reference line: the lengths of the plurality of first traces gradually increase, and the widths of the plurality of first traces gradually increase; and the first reference line is a boundary line between the first sub-display region and the second sub-display region.

18. The liquid crystal display panel of any one of claims 1-17, wherein the array substrate further comprises: an auxiliary electrode layer, the auxiliary electrode layer being located on a side of the common electrode layer facing away from the first substrate, and the auxiliary electrode layer and the common electrode layer being in contact.

19. The liquid crystal display panel according to claim 18, wherein, The light-blocking layer further comprises a plurality of second light-blocking portions, and the auxiliary electrode layer comprises a plurality of auxiliary electrodes, a footprint of one of the auxiliary electrodes on the first substrate being located within a boundary of a footprint of one of the second light-blocking portions on the first substrate.

20. A display device, comprising: the liquid crystal display panel of any one of claims 1-19; and a cover plate located on an out-coupling side of the liquid crystal display panel. ​

Images