Data access for phase change memory

Abstract

Embodiments of the present disclosure provide a data access method for a phase change memory (PCM), a related device, and a storage medium. A small amount of SRAM resources are added to a controller of a PCM. In a write stage, whether a write operation occurs in each coarse-grained unit time can be recorded by using a bitmap provided by an SRAM; and whether a write operation occurs in each fine-grained unit time can be recorded by using a Bloom filter provided by an SRAM. In a subsequent read stage, even in the case of a large bandwidth, the bitmap and the Bloom filter provided by the SRAM resources can be used to correctly distinguish three-level read voltages designed for the PCM, so that a correct read voltage in response to a read I / O request can be found in one pass with a large probability, thereby significantly reducing the number of read retries.

Description

[0001] Phase change memory data access technology field

[0002]

[0001] The present disclosure relates to the field of computer technology, and more particularly to data access to a phase change memory.

[0003]

[0002] Phase change memory (PCM) is a new type of memory that uses phase change material as a storage medium. It stores 0 bits (bits) or 1 bits by inducing the material to undergo a reversible transition between a high-resistance amorphous state and a low-resistance crystalline state. PCM has become increasingly popular due to its advantages, including low latency, byte-accessibility, long lifespan, low cost, large capacity, and non-volatility. For example, an increasing number of cloud service products utilize in-memory database (MMDB) systems, which generally utilize PCM, effectively reducing the overall TCO (Total Cost of Ownership) of cloud service products.

[0004] Due to its inherent material properties, phase-change memory (PCM) suffers from read voltage drift. This problem occurs when the read voltage required to read correct data from a written memory cell in a PCM storage medium drifts over time. In practical applications, multiple read voltage levels are typically designed to address this problem. When responding to a read I / O (Input / Output) request, the phase-change memory uses a Read Retry mechanism to repeatedly retry read operations on the memory cells in the PCM storage medium using different read voltage levels until the correct read voltage is found and the correct data is read.

[0005]

[0004] However, if most read UO requests require multiple read retries to find the correct read voltage, the I / O latency will increase, greatly degrading the QoS (Quality of Service) of the service system using phase change memory.

[0006]

[0005] Various aspects of the present disclosure provide a phase change memory data access method, related devices, and storage medium, which are used to find the correct read voltage to respond to a read I / O request with a high probability in one go, thereby greatly optimizing the QoS of a service system using the phase change memory.

[0007]

[0006] An embodiment of the present disclosure provides a data access method for a phase change memory, wherein the phase change memory comprises at least: a controller and a storage medium, wherein the controller comprises at least a first SRAM and a second SRAM, wherein the phase change memory is configured with a first read voltage, a second read voltage, and a third read voltage having a minimum read-after-write delay from small to large; the method is executed by the controller, and comprises: in response to a write I / O request including a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to the parity type of a coarse-grained unit time of the current timing, wherein the duration of the coarse-grained unit time is related to the minimum read-after-write delay of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage in a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; selecting a target Bloom filter from a first Bloom filter and a second Bloom filter included in the second SRAM according to the parity type of a fine-grained unit time of the current timing, wherein The length of the fine-grained unit time is related to the minimum read-after-write delay of the second read voltage. The first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage during the read phase. A second write operation identifier of the write address is stored in the target Bloom filter, where the second write operation identifier indicates that a write operation has been performed on the target storage unit. The data requested by the write UO request is written into the target storage unit.

[0008]

[0007] An embodiment of the present disclosure further provides a data access method for a phase change memory, wherein the phase change memory includes at least: a controller and a storage medium, the controller includes at least a first SRAM and a second SRAM, and the phase change memory is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order; the method is executed by the controller, and includes: in response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as a target read voltage; if the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, selecting one of the first read voltage and the second read voltage as a target read voltage based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM; and performing a read operation on a storage cell corresponding to the read address in the storage medium according to the target read voltage.

[0009]

[0008] An embodiment of the present disclosure further provides a data access method for a phase change memory, wherein the phase change memory includes at least: a controller and a storage medium, the controller includes at least a third SRAM, and the phase change memory is configured with a fourth read voltage and a fifth read voltage with a minimum read-after-write delay from small to large; the method is executed by the controller, and the method includes: responding to a write I / O request including a write address, selecting a target bitmap from a third bitmap and a fourth bitmap included in the third SRAM according to the parity type of the unit time currently counted, wherein the third bitmap is associated with an odd unit time, the fourth bitmap is associated with an even unit time, and the length of the unit time is associated with the minimum read-after-write delay of the fifth read voltage; storing a write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested to be written by the write I / O request into the target storage unit.

[0010]

[0009] An embodiment of the present disclosure further provides a data access method for a phase change memory, wherein the phase change memory includes at least: a controller and a storage medium, wherein the controller includes at least a third SRAM, and the phase change memory is configured with a fourth read voltage and a fifth read voltage with minimum read-after-write delay from small to large; the method is executed by the controller, and includes: in response to a write I / O request including a write address, selecting a target Bloom filter from a third Bloom filter and a fourth Bloom filter included in the third SRAM according to the parity type of a currently counted unit time, wherein the third Bloom filter is associated with an odd-numbered unit time, the fourth Bloom filter is associated with an even-numbered unit time, and the length of the unit time is associated with the minimum read-after-write delay of the fifth read voltage; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested to be written by the write I / O request into the target storage unit.

[0011]

[0010] An embodiment of the present disclosure further provides a data access method for a phase change memory, the phase change memory comprising at least: a controller and a storage medium, the controller comprising at least a first SRAM and a second SRAM, the phase change memory being configured with a first read voltage, a second read voltage, and a third read voltage having a minimum read-after-write delay in ascending order; the method being executed by the controller, comprising: in response to a write I / O request comprising a write address, selecting a target bitmap from a first bitmap and a second bitmap comprised in the first SRAM according to a parity type of a coarse-grained unit time currently being counted, wherein the duration of the coarse-grained unit time is related to the minimum read-after-write delay of the third read voltage, the first bitmap and the second bitmap being used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and arranging a target position in a fine-grained unit time currently being counted according to a sub-unit time to which the current time belongs. A target Bloom filter located at a target arrangement position is selected from a Bloom filter group included in a second SRAM, wherein the fine-grained unit time includes n sub-unit times divided in sequence, the duration of the fine-grained unit time is related to a minimum read-after-write delay of the second read voltage, the Bloom filter group is used to select the first read voltage or the second read voltage during a read phase, and the Bloom filter group includes n sequentially arranged Bloom filters; a second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit; and data requested by the write I / O request is written into the target storage unit.

[0012]

[0011] Embodiments of the present disclosure also provide a data access method for a phase-change memory, the phase-change memory comprising at least: a controller and a storage medium, the controller comprising at least a first SRAM and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage in ascending order of minimum read-after-write delay. The method, executed by the controller, comprises: in response to a read I / O request including a read address, searching a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as a target read voltage; if the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, selecting one of the first read voltage and the second read voltage as the target read voltage based on the presence of the second write operation identifier of the read address in a Bloom filter bank included in the second SRAM; and performing a read operation on a memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0013]

[0012] An embodiment of the present disclosure further provides a data access method for a phase change memory, the phase change memory comprising at least: a controller and a storage medium, the controller comprising at least a third SRAM, the phase change memory being configured with a fourth read voltage and a fifth read voltage having minimum read-after-write delays in ascending order; the method being executed by the controller, comprising: responding to a write UO request comprising a write address, selecting a target Bloom filter located at a target arrangement position in a Bloom filter group included in the third SRAM according to a target arrangement position of a sub-unit time to which a current time belongs in a unit time currently being counted, wherein the unit time comprises n sub-unit times divided in sequence, the duration of the unit time being related to the minimum read-after-write delay of the fifth read voltage, and the Bloom filter group comprising n Bloom filters arranged in sequence; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested to be written by the write UO request into the target storage unit.

[0014]

[0013] Embodiments of the present disclosure also provide a data access method for a phase-change memory, the phase-change memory comprising at least a controller and a storage medium, the controller comprising at least a third SRAM, the phase-change memory being configured with fourth and fifth read voltages, with minimum read-after-write delays ranging from small to large. The method, executed by the controller, comprises: in response to a read I / O request including a read address, searching a Bloom filter bank included in the third SRAM for a write operation identifier for the read address; if the write operation identifier for the read address is not found in the Bloom filter bank, selecting the fifth read voltage as a target read voltage; if the write operation identifier for the read address is found in the Bloom filter bank, selecting the fourth read voltage as the target read voltage; and performing a read operation on a memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0015]

[0014] The embodiment of the present disclosure further provides a phase change memory, comprising at least: a controller and a storage medium, wherein the controller comprises at least one SRAM; and the controller is configured to execute the steps in the data access method of the phase change memory.

[0016]

[0015] The embodiment of the present disclosure also provides a memory database system, which at least includes: the phase change memory provided by the embodiment of the present disclosure.

[0017]

[0016] The embodiment of the present disclosure also provides a cloud service product, which at least includes: the in-memory database system provided by the embodiment of the present disclosure.

[0018]

[0017] The embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor is enabled to implement the steps in the data access method of the phase change memory.

[0019]

[0018] In an embodiment of the present disclosure, a small amount of SRAM (Static Random Access Memory) resources are added to the PCM controller. During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation occurs at each coarse-grained unit time; and the Bloom filter provided by the SRAM can be used to record whether a write operation occurs at each fine-grained unit time. In this way, during the subsequent read phase, even in the case of large bandwidth, the bitmap and Bloom filter provided by the SRAM resources can correctly distinguish the three read voltage levels designed for the phase change memory, achieving a high probability of finding the correct read voltage to respond to a read I / O request in one go, significantly reducing the number of read retries, and greatly optimizing the QoS of a service system using phase change memory without affecting the latency and bandwidth of the overall system. DESCRIPTION OF THE DRAWINGS

[0020]

[0019] The drawings described herein are intended to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the drawings:

[0021] FIG1 is a schematic diagram of a read voltage drift of a phase change memory;

[0022] FIG2 is a schematic diagram of the structure of a phase change memory provided in an embodiment of the present disclosure;

[0023] FIG3 is a flow chart of a data access method for a phase change memory provided in an embodiment of the present disclosure;

[0024] FIG4 is a schematic diagram of a data access process of a phase change memory provided by an embodiment of the present disclosure;

[0025] FIG5 is another schematic diagram of a data access process of a phase change memory provided by an embodiment of the present disclosure;

[0026]

[0025] FIG6 is a flow chart of another data access method of a phase change memory provided in an embodiment of the present disclosure;

[0027] FIG7 is a flow chart of another data access method for a phase change memory provided in an embodiment of the present disclosure;

[0028] FIG8 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0029] FIG9 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0030] FIG10 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0031] FIG11 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0032] FIG12 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0033] FIG13 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0034] FIG. 14 is a schematic diagram of another process for accessing data in a phase change memory according to an embodiment of the present disclosure; FIG. 15 is a flowchart of another method for accessing data in a phase change memory according to an embodiment of the present disclosure;

[0035] FIG16 is a flow chart of another method for accessing data in a phase change memory according to an embodiment of the present disclosure;

[0036] FIG17 is a flow chart of another method for accessing data of a phase change memory according to an embodiment of the present disclosure;

[0037] FIG18 is a flow chart of another method for accessing data in a phase change memory according to an embodiment of the present disclosure;

[0038] FIG19 is a flow chart of another method for accessing data in a phase change memory according to an embodiment of the present disclosure;

[0039] FIG20 is a schematic diagram of the structure of another phase change memory provided by an embodiment of the present disclosure.

[0040] To make the objectives, technical solutions, and advantages of the present disclosure more clearly apparent, the technical solutions of the present disclosure will be described clearly and completely below in conjunction with specific embodiments of the present disclosure and the corresponding drawings. Obviously, the described embodiments are only some of the embodiments of the present disclosure, and are not all of the embodiments. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present disclosure without inventive effort are within the scope of protection of the present disclosure.

[0041]

[0041] In the embodiments of the present disclosure, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the access relationship of associated objects, indicating that three relationships can exist. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. In the text descriptions of the present disclosure, the character "" generally indicates that the associated objects are in an "or" relationship. In addition, in the embodiments of the present disclosure, "first," "second," "third," etc. are merely used to distinguish the contents of different objects and have no other special meanings.

[0042] FIG1 is a schematic diagram illustrating read voltage drift in a phase-change memory. The horizontal axis of the coordinate system shown in FIG1 corresponds to time t, and the vertical axis corresponds to read voltage Vt. After data is written to a memory cell (cell) in a phase-change memory, the read voltage (Drift) used to read the correct data from the memory cell drifts over time. The dashed line corresponding to zero drift represents the time-varying curve of the read voltage for correctly reading 0 bits in the memory cell; the solid line corresponding to drift represents the time-varying curve of the read voltage for correctly reading 1 bit in the memory cell. If data is read from a memory cell in a phase-change memory at different times using a given read voltage Vread, erroneous data can be easily read.

[0043] In practical applications, to address the problem of read voltage drift, multiple read voltage levels are typically designed. Each read voltage corresponds to a write-to-read delay (WDR) time range. Typically, the write-to-read delay time ranges covered by multiple read voltage levels may partially overlap. The write-to-read delay (WDR) refers to the time between when data is written and when it is read. For example, if data is written at 18:14:30 on November 29, 2023, and read at 18:14:31 on November 29, 2023, the write-to-read delay is 1 second. Table 1 lists the write-to-read delays corresponding to successful reads and read failures for different read voltages. Taking multiple read voltage levels, denoted as Vread1, Vread2, and Vread3, as an example, the write-after-read delay corresponding to Vread1 ranges from 1 μs to 1000 ms; the write-after-read delay corresponding to Vread2 ranges from 100 ms to 1000 s; and the write-after-read delay corresponding to Vread3 ranges from 100 s to 12 hours. For each read voltage, for read I / O requests triggered within the time range of the write-after-read delay corresponding to that read voltage, using that read voltage to read data guarantees the correctness of the read data (which can be understood as a successful read). This also guarantees the correctness of read I / O requests triggered within the time range of the write-after-read delay corresponding to that read voltage. However, for read I / O requests triggered outside the time range of the write-after-read delay corresponding to that read voltage, using that read voltage to read data will not successfully read the correct data (which can be understood as a read failure). Table 1

[0044] In practical applications, the time range of the post-write read delay covered by the read voltages of multiple gears can ensure the read correctness of all VO requests within a certain range of the post-write read time width. The post-write read time width refers to the overall time range defined by the time range of the post-write read delay covered by the read voltages of all gears. For example, the time range of the post-write read delay corresponding to Vread 1 is 1 μs to 1000 ms; the time range of the post-write read delay corresponding to Vread 2 is 100 ms to 1000 s, and the time range of the post-write read delay corresponding to Vread 3 is 100 s to 12 h (hours). The post-write read time width is 1 μs to 12 h.

[0045] When the read-after-write time width is exceeded, a retention mechanism is used to ensure that all storage cells of the PCM are refreshed once within the read-after-write time width. This ensures that the time interval between the time when a write operation is performed on all storage cells of the PCM and the time when a read operation is performed on all storage cells of the PCM does not exceed the read-after-write time width. Retention time generally indicates the time range within which a storage medium can be correctly read after being erased or written. The longer the better, and it is one of the important indicators of storage medium reliability.

[0046] Using multiple read voltage levels can effectively address the read voltage drift problem. In practical applications, when responding to a read UO request, the phase-change memory initiates a read operation on a storage cell in the PCM storage medium using a read voltage level at one level to read data. Error checking and correction (ECC) is then performed on the read data. If the ECC result indicates that the read data is incorrect, a new read voltage level is used, and a new read operation is initiated on the storage cell in the PCM storage medium using the new read voltage level. These steps are repeated until the correct data is read. This data reading method can be understood as a read retry method, in which read operations are repeatedly initiated on the storage cell in the PCM storage medium using read voltage levels at different levels until the correct read voltage is found and the correct data is read using the correct read voltage level.

[0047]

[0047] However, if most read UO requests require multiple read retries to find the correct read voltage, the I / O latency will increase, significantly degrading the QoS (Quality of Service) of the service system using phase-change memory.

[0048]

[0048] To this end, embodiments of the present disclosure provide a phase change memory data access method, related devices, and storage medium. In this embodiment, a small amount of SRAM resources are added to the PCM controller. During the write phase, a bitmap provided by the SRAM can be used to record whether a write operation occurs at each coarse-grained unit time; and a Bloom filter provided by the SRAM can be used to record whether a write operation occurs at each fine-grained unit time. Thus, during the subsequent read phase, even under high bandwidth conditions, the bitmap and Bloom filter provided by the SRAM resources can accurately distinguish the three read voltage levels designed for the phase change memory, achieving a high probability of finding the correct read voltage to respond to a read I / O request in one go, significantly reducing the number of read retries and greatly optimizing the QoS of a service system using the phase change memory with little impact on the overall system latency and bandwidth.

[0049]

[0049] The following describes in detail the technical solutions provided by various embodiments of the present disclosure in conjunction with the accompanying drawings.

[0050] FIG2 is a schematic diagram of the structure of a phase change memory provided in an embodiment of the present disclosure. Referring to FIG2 , the phase change memory includes at least a controller and a storage medium. The PCM controller includes, but is not limited to, an MCU (microcontroller), a CPU (central processing unit), and an MPU (microprocessor unit). The storage medium has a storage space that provides multiple storage cells, each of which can store either 0 bits or 1 bits.

[0051]

[0051] During the data write phase, the host sends a write I / O request including a write address to the phase-change memory. The phase-change memory writes the data requested by the write I / O request to the storage unit corresponding to the write address in the PCM storage medium. During the data read phase, the host sends a read I / O request including a read address to the phase-change memory. The phase-change memory initiates a read operation on the storage unit corresponding to the read address in the PCM storage medium according to the read voltage to read the written data and return it to the host. In addition, the host can receive write I / O requests or read I / O requests from a service system using the PCM and forward them to the phase-change memory. A service system using the PCM is, for example, a cloud service product. Cloud service products include, but are not limited to, cloud servers, cloud database systems, or cloud desktop systems.

[0052] In this embodiment, the host includes, but is not limited to, a computer system in any device form factor, such as a notebook computer, a desktop computer, a smart phone, a tablet computer, an industrial computer, and a server. The host system and the phase-change memory may be in the same device or in different devices, without limitation.

[0053]

[0053] In actual applications, the PCM controller may further include more functional modules. For example, the PCM controller may further include: a front-end control module, an address mapping module, an ECC module, a media manager module, a global timer, etc., without limitation.

[0054]

[0054] The front-end control module completes the analysis of the read I / O request and write I / O request transmitted by the host, and sends them to the subsequent stage, for example, to the address mapping module and the ECC module.

[0055] The address mapping module is used to convert the logical address (LA) sent by the host into a physical address (PA). Specifically, it converts the read address in the LA format in a read I / O request into a read address in the PA format; and converts the write address in the LA format in a write I / O request into a write address in the PA format. The read address refers to the address information of the storage unit to be read during the data read phase; the write address refers to the address information of the storage unit to be written during the data write phase.

[0056] The ECC module encodes the write data requested by the write UO request and determines redundant check bits for the write data using an ECC algorithm. The encoded write data and its redundant check bits are written into a storage cell corresponding to the write address in the PCM storage medium. During the data reading phase, the encoded write data and its redundant check bits are read from the PCM storage medium and decoded using the ECC module to obtain the write data. The ECC module also uses the ECC algorithm to re-determine the redundant check bits of the read write data and, based on a comparison result between the redundant check bits re-determined using the ECC algorithm and the redundant check bits read from the storage medium, determines whether the encoded write data read from the PCM storage medium is correct read data. For more information about the ECC module, see the related art.

[0057]

[0057] The Media Manager module is used to manage storage media, for example but not limited to: using the Retention mechanism to refresh the storage media of the PCM.

[0058]

[0058] The global timer is used for timing, and the timing starting point is not limited. For example, the timing starts after the PCM is started.

[0059]

[0059] In this embodiment, the PCM controller includes at least a first SRAM and a second SRAM; the first SRAM is an SRAM (Static Random Access Memory) that provides a bitmap; and the second SRAM is an SRAM that provides a Bloom filter.

[0060] A bitmap is a commonly used data structure used to represent a set, where each element corresponds to a binary bit. In other words, a bit is used to mark the value corresponding to an element, and the key is the element. If the element exists in the set, the corresponding binary bit is 1, otherwise it is 0. In short, a bit (0 or 1) indicates whether an element has appeared. Because data is stored in bits, storage space can be greatly saved.

[0061] A Bloom filter is a special type of hash table used to quickly check whether an element belongs to a set. It can quickly determine whether an element is in a large set, and the determination is fast and does not take up much memory space. The main principle of a Bloom filter is to use a set of hash functions to map elements to index positions in a set of bit arrays. To check whether an element is in a set, the element is hashed and the value of the bit array corresponding to the hash value is checked to see if it is 1. If the values ​​of the bit arrays corresponding to the hash values ​​are all 1, then the element is likely in the set; otherwise, it is definitely not. Because hash function mappings may conflict, a Bloom filter may misjudge an element that is not in the set as being in the set. However, a Bloom filter will not miss a value, i.e., it will not misjudge an element that is in the set as not being in the set.

[0062] In this embodiment, the first SRAM can provide two bitmaps, namely a first bitmap and a second bitmap. The second SRAM can provide two Bloom filters, namely a first Bloom filter and a second Bloom filter. Thus, even in the case of high bandwidth, the two bitmaps and two Bloom filters can correctly distinguish the three read voltage levels designed for the phase change memory using relatively few SRAM resources, thereby accurately finding the correct read voltage to respond to a read I / O request with a high probability, significantly reducing the number of read retries, and greatly optimizing the QoS of a service system using the phase change memory while barely affecting the latency and bandwidth of the overall system.

[0063] When the controller of the phase change memory includes at least a first SRAM and a second SRAM, the read voltages of the three gears can be correctly distinguished. The time range of the read-after-write delay of the read voltage falls within the minimum read-after-write delay and the maximum read-after-write delay, that is, the read-after-write delay of the read voltage is greater than or equal to the minimum read-after-write delay and less than or equal to the maximum read-after-write delay.

[0064] Specifically, the phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage having minimum read-after-write delays from small to large. It is understood that the minimum read-after-write delays are arranged in ascending order as follows: the first read voltage, the second read voltage, and the third read voltage. In practical applications, the time ranges of the read-after-write delays corresponding to any two read voltages may not overlap. Furthermore, optionally, the time range of the read-after-write delay covered by the first read voltage partially overlaps with the time range of the read-after-write delay covered by the second read voltage, and / or the time range of the read-after-write delay covered by the second read voltage partially overlaps with the time range of the read-after-write delay covered by the third read voltage. It is understood that the minimum read-after-write delay of the second read voltage is less than the maximum read-after-write delay of the first read voltage, and / or the minimum read-after-write delay of the third read voltage is less than the maximum read-after-write delay of the second read voltage. For example, the write-post-read delay corresponding to the first read voltage Vread1 ranges from 1 μs to 1000 ms; the write-post-read delay corresponding to the second read voltage Vread2 ranges from 100 ms to 1000 s; and the write-post-read delay corresponding to the third read voltage Vread3 ranges from 100 s to 12 hours. The minimum write-post-read delay of 100 ms for the second read voltage Vread2 is less than the maximum write-post-read delay of 1000 ms for the first read voltage Vread1. The minimum write-post-read delay of 100 s for the third read voltage Vread3 is less than the maximum write-post-read delay of 1000 s for the second read voltage Vread2.

[0065] In this embodiment, two unit times of different granularities are defined: a coarse-grained unit time and a fine-grained unit time. The duration of the coarse-grained unit time is related to the minimum read-after-write delay of the third read voltage. For example, the duration of the coarse-grained unit time is equal to the minimum read-after-write delay of the third read voltage, or the duration of the coarse-grained unit time is obtained by increasing or decreasing the minimum read-after-write delay of the third read voltage. This is not limited to this. The duration of the fine-grained unit time is related to the minimum read-after-write delay of the second read voltage. For example, the duration of the fine-grained unit time is equal to the minimum read-after-write delay of the second read voltage, or the duration of the fine-grained unit time is obtained by increasing or decreasing the minimum read-after-write delay of the second read voltage. This is not limited to this.

[0066] In this embodiment, the two bitmaps provided by the first SRAM can record whether a write operation occurs for each coarse-grained unit time; and the two Bloom filters provided by the second SRAM can record whether a write operation occurs for each fine-grained unit time. The two bitmaps provided by the first SRAM can distinguish between (Vread1 / Vread2) and Vread3, that is, determine whether the desired read voltage is either the third read voltage Vread3, the second read voltage Vread2, or the first read voltage Vread1. The two Bloom filters provided by the second SRAM can distinguish between Vread1 and (Vread2 / Vread3), that is, determine whether the desired read voltage is either the first read voltage Vread1, the second read voltage Vread2, or the third read voltage Vread3. The combination of the first and second SRAMs can correctly distinguish the read voltages of the three levels.

[0067] The following describes a phase change memory write process in conjunction with FIG3 . FIG3 is a flow chart of a data access method for a phase change memory provided by an embodiment of the present disclosure. The phase change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase change memory is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order. The method is executed by the controller. Referring to FIG3 , the method may include the following steps.

[0068]

[0068] 301. In response to a write I / O request including a write address, a target bitmap is selected from a first bitmap and a second bitmap included in a first SRAM according to the parity type of a coarse-grained unit time currently being counted, wherein the duration of the coarse-grained unit time is related to a minimum read-after-write delay of a third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage in a read phase.

[0069] Specifically, the PCM controller receives a write I / O request including a write address from a host and responds. During the response, the write address in the LA format in the write I / O request may be converted to a write address in the PA format. The ECC module may also be called to encode the write data requested by the write I / O request, and the ECC algorithm may be used to determine redundancy check bits of the write data, but the present invention is not limited thereto.

[0070]

[0070] In this embodiment, when the PCM controller responds to the write UO request, it determines the number of the coarse-grained unit time and the parity type of the coarse-grained unit time currently being counted based on the current time and the timing starting point. The timing starting point is flexibly set as needed. For example, the timing starts when the PCM starts, that is, the timing starting point is the startup time of the PCM.

[0071] If the coarse-grained unit time currently being measured is of the odd type, then the coarse-grained unit time currently being measured is the odd-numbered coarse-grained unit time. If the coarse-grained unit time currently being measured is of the even type, then the coarse-grained unit time currently being measured is the even-numbered coarse-grained unit time. For example, if the coarse-grained unit time duration is 100 seconds, the time ranges corresponding to the odd-numbered coarse-grained unit time are: 0-100 seconds, 200-300 seconds, and 400-500 seconds; the time ranges corresponding to the even-numbered coarse-grained unit time are: 100-200 seconds, 300-400 seconds, and 500-600 seconds.

[0072]

[0072] Exemplarily, according to the parity type of the coarse-grained unit time currently being counted, the implementation method of selecting the target bitmap from the first bitmap and the second bitmap included in the first SRAM is as follows: if the parity type indicates that the coarse-grained unit time currently being counted is an odd-numbered coarse-grained unit time, the first bitmap is selected from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, and the first bitmap is associated with the odd-numbered coarse-grained unit time; if the parity type indicates that the coarse-grained unit time currently being counted is an even-numbered coarse-grained unit time, the second bitmap is selected from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, and the second bitmap is associated with the even-numbered coarse-grained unit time.

[0073]

[0073] 302. A first write operation identifier of the write address is stored in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on the target storage unit corresponding to the write address in the storage medium.

[0074] Specifically, when storing the first write operation identifier of the write address in the target bitmap, the write address is used as a key, and various mapping functions such as a hash function in the target bitmap are called to determine the mapping position of the write address in the target bitmap. The value of the bit at the mapping position of the write address in the bit array of the target bitmap is set to 1. 1 bit in the bit array of the target bitmap represents the first write operation identifier of the write address, and the first write operation identifier of the write address is stored in the target bitmap. It is understandable that if 0 bit in the bit array of the target bitmap indicates that the write address is not recorded.

[0075] For coarse-grained time units, due to their relatively large time range, it's difficult to record every write address without impacting the bandwidth and latency of the service system using PCM. Therefore, a mapping table-like approach is employed to increase the granularity of each bit in the target bitmap's bit array. This means that each bit can be used to determine whether a write operation has been performed on the target storage cell corresponding to a write address within a certain address range. From the perspective of the entire PCM, this improves the probability of correctly distinguishing read voltages.

[0075]

[0076] Based on the above, further optionally, when storing the first write operation identifier of the write address in the target bitmap, the write address may be right-shifted by M bits, where M is a positive integer; a first mapping position corresponding to the write address in the bit array of the target bitmap is determined based on the right-shifted write address; and the value of the bit at the first mapping position is set as the first write operation identifier of the write address, so as to store the first write operation identifier of the write address in the target bitmap.

[0076]

[0077] Specifically, the write address after being right-shifted by M bits is used as a key, and various mapping functions such as a hash function in the target bitmap are called to determine a mapping position corresponding to the write address in the bit array of the target bitmap (referred to herein as the first mapping position). The value of the bit at the first mapping position corresponding to the write address in the bit array of the target bitmap is set to 1. One bit in the bit array of the target bitmap represents the first write operation identifier of each write address within a range, so that the first write operation identifier of the write address is stored in the target bitmap.

[0077]

[0078] Further optionally, before storing the first write operation identifier of the write address in the target bitmap, the method further includes: if the current time is the start time of the coarse-grained unit time currently being measured, clearing the target bitmap, that is, setting the value of each bit in the bit array of the target bitmap to 0. If the current time is not the start time of the coarse-grained unit time currently being measured, directly storing the first write operation identifier of the write address in the target bitmap. In this way, the first write operation identifier of the write address within the time range corresponding to the coarse-grained unit time currently being measured can be effectively stored in the target bitmap, thereby better ensuring the read correctness of the I / O request.

[0078]

[0079] For a better understanding, see Figure 4 for an explanation. Referring to Figure 4, if the PCM controller receives a write I / O request from the host within an odd-numbered coarse-grained unit time, it right-shifts the write address by M bits. Using the M-bit right-shifted write address as the key, it calls the hash function of the first bitmap to map the key, obtaining the mapping location corresponding to the write address in the first bitmap's bit array. For example, if the first bitmap's bit array is 12 bits long, and the mapping location corresponding to the write address in the first bitmap's bit array is the 4th bit, the 4th bit in the first bitmap's bit array is set to 1 to indicate that a write operation has been performed on the write address corresponding to the write I / O request. Each bit in the first bitmap's bit array represents whether an address within the 2& range has been written to.

[0079]

[0080] In addition, after the PCM controller receives a write UO request from the host, if the current time is the start time of an odd-numbered coarse-grained unit time, the first bitmap may be cleared before calling the first bitmap. If the current time is not the start time of an odd-numbered coarse-grained unit time, the first bitmap may be directly called.

[0080]

[0081] Referring to Figure 4 , if the PCM controller receives a write I / O request from the host within an even-numbered coarse-grained unit time range, it right-shifts the write address by M bits. Using the M-bit right-shifted write address as the key, the second bitmap's hash function is invoked to map the key, obtaining the mapping location corresponding to the write address in the second bitmap's bit array. For example, if the second bitmap's bit array is 12 bits long, the mapping location corresponding to the write address in the second bitmap's bit array is the sixth bit. The sixth bit in the second bitmap's bit array is set to 1 to indicate that a write operation has been performed on the write address corresponding to the write I / O request. Each bit in the second bitmap's bit array represents whether an address within the range has been written to.

[0081]

[0082] In addition, after the PCM controller receives a write UO request sent by the host, if the current time is the start time of an even-numbered coarse-grained unit time, the second bitmap may be cleared first and then the second bitmap may be called. If the current time is not the start time of an even-numbered coarse-grained unit time, the second bitmap may be directly called.

[0082]

[0083] 303. Select a target Bloom filter from a first Bloom filter and a second Bloom filter included in a second SRAM based on the parity type of a currently measured fine-grained unit time. The length of the fine-grained unit time is related to a minimum read-after-write latency of the second read voltage. The first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage during a read phase.

[0083]

[0084] Specifically, when responding to a write I / O request, the PCM controller also determines the number of the fine-grained unit time and the parity type of the currently measured fine-grained unit time based on the current time and the starting point of the timing. If the currently measured fine-grained unit time is of the odd type, it indicates that the currently measured fine-grained unit time is the odd-numbered fine-grained unit time; if the currently measured fine-grained unit time is of the even type, it indicates that the currently measured fine-grained unit time is the even-numbered fine-grained unit time. Taking a fine-grained unit time length of 100 ms as an example, the time ranges corresponding to the odd-numbered fine-grained unit time are: 0-100 ms, 200 ms-300 ms, and 400 ms-500 ms; and the time ranges corresponding to the even-numbered fine-grained unit time are: 100 ms to 200 ms, 300 ms to 400 ms, and 500 ms to 600 ms.

[0084]

[0085] For example, selecting a target Bloom filter from the first and second Bloom filters included in the second SRAM based on the parity type of the currently measured fine-grained unit time is implemented as follows: if the parity type indicates that the currently measured fine-grained unit time is an odd-numbered fine-grained unit time, selecting the first Bloom filter from the first and second Bloom filters included in the second SRAM as the target Bloom filter, where the first Bloom filter is associated with the odd-numbered fine-grained unit time.

[0085]

[0086] If the parity type indicates that the fine-grained unit time of the current timing is an even fine-grained unit time, a second Bloom filter is selected from the first Bloom filter and the second Bloom filter included in the second SRAM as the target Bloom filter, and the second Bloom filter is associated with the even fine-grained unit time.

[0086]

[0087] 304. Save a second write operation identifier of the write address in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit.

[0087]

[0088] Exemplarily, the second write operation identifier of the write address is stored in the target Bloom filter by determining a second mapping position of the write address in the bit array of the target Bloom filter; and setting the value of the bit at the second mapping position to the second write operation identifier of the write address, so as to store the second write operation identifier of the write address in the target Bloom filter.

[0088]

[0089] Specifically, using the write address as a key, multiple mapping functions, such as a hash function, are called in the target Bloom filter to determine multiple mapping locations of the write address in the target Bloom filter's bit array (referred to herein as second mapping locations). The values ​​of the bits at the multiple mapping locations of the write address in the target Bloom filter's bit array are set to 1, and the corresponding 1 bit in the target Bloom filter's bit array represents the first write operation identifier of the write address, thereby storing the first write operation identifier of the write address in the target Bloom filter. It will be understood that if a 0 bit in the target Bloom filter's bit array indicates that the write address has not been recorded.

[0090] Further optionally, before storing the second write operation identifier of the write address in the target Bloom filter, the method further includes: if the current time is the start time of the fine-grained unit time currently being measured, clearing the target Bloom filter, that is, setting the value of each bit in the bit array of the target Bloom filter to 0. If the current time is not the start time of the fine-grained unit time currently being measured, directly performing the operation of storing the second write operation identifier of the write address in the target Bloom filter. In this way, the second write operation identifier of the write address within the time range corresponding to the fine-grained unit time currently being measured can be better stored in the target Bloom filter, thereby better ensuring the read correctness of the I / O request.

[0089]

[0091] For a better understanding, see Figure 5 for an explanation. Referring to Figure 5, if the PCM controller receives a write UO request from the host within an odd-numbered fine-grained time unit, it uses the write address as the key and calls multiple hash functions of the first Bloom filter to map the key. This results in multiple mapping locations corresponding to the write address in the first Bloom filter's bit array. These hash functions are denoted as Hash 00, Hash 01, and Hash 02, respectively. For example, if the first Bloom filter's bit array is 12 bits long, the mapping locations corresponding to the write address in the first Bloom filter's bit array are the second, fourth, and ninth bits. The fourth and ninth bits in the first Bloom filter's bit array are both set to 1 to indicate that the write address corresponding to the write UO request has been written to.

[0090]

[0092] Furthermore, after receiving a write UO request from the host, the PCM controller clears the first Bloom filter if the current time is the start of an odd-numbered fine-grained time unit, and then calls the first Bloom filter. If the current time is not the start of an odd-numbered fine-grained time unit, the first Bloom filter is called directly.

[0091]

[0093] If the PCM controller receives a write UO request from the host within an even-numbered fine-grained unit time range, it uses the write address as a key and calls multiple hash functions of the second Bloom filter to map the key. This results in multiple mapping locations corresponding to the write address in the second Bloom filter's bit array. These multiple hash functions are denoted as Hash 10, Hash 11, and Hash 12. For example, if the second Bloom filter's bit array is 12 bits long, the mapping locations corresponding to the write address in the second Bloom filter's bit array are the first, sixth, and tenth bits. The first, sixth, and tenth bits in the second Bloom filter's bit array are all set to 1 to indicate that a write operation has been performed on the write address corresponding to the write UO request.

[0092]

[0094] Furthermore, after receiving a write UO request from the host, the PCM controller clears the second Bloom filter before invoking it if the current time is the start of an even-numbered fine-grained time unit. If the current time is not the start of an even-numbered fine-grained time unit, the second Bloom filter is directly invoked.

[0093]

[0095] 305. Write the data requested by the write I / O request into the target storage unit.

[0094]

[0096] In practical applications, the data requested by the write UO request can be written directly to the target storage unit, or the ECC module can be called to encode the write data requested by the write UO request, and the ECC algorithm can be used to determine the redundant check bits of the write data, and the encoded write data and its redundant check bits can be written to the target storage unit. There are no restrictions on this.

[0095]

[0097] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the SRAM bitmap records whether a write operation has occurred at each coarse-grained unit time; the SRAM Bloom filter records whether a write operation has occurred at each fine-grained unit time. In this way, during the subsequent read phase, even under high bandwidth conditions, the SRAM bitmap and Bloom filter can accurately distinguish the three read voltage levels designed for the phase-change memory. This allows for a high probability of finding the correct read voltage to respond to a read I / O request, significantly reducing the number of read retries and greatly optimizing the QoS of service systems using phase-change memory with little impact on overall system latency and bandwidth.

[0096]

[0098] To better understand the write process, a specific write process is described below in conjunction with FIG6 . FIG6 is a flow chart of another data access method for a phase change memory provided by an embodiment of the present disclosure. Referring to FIG6 , the method may include the following steps.

[0097]

[0099] S1. In response to a write UO request, it is determined whether the coarse-grained unit time of the current timing belongs to an odd-numbered coarse-grained unit time; if so, execute S2; if not, execute S3.

[0098]

[0100] S2. If the current time is the start time of the coarse-grained unit time of the current timing, first clear the first bitmap; then right-shift the write address by M bits, and update the first bitmap based on the write address after right-shifting by M bits, and execute S4.

[0099]

[0101] The first bitmap is updated based on the write address after being right-shifted by M bits, that is, the write operation identifier corresponding to the write address is recorded in the first bitmap.

[0100]

[0102] S3. If the current time is not the start time of the coarse-grained unit time of the current timing, first clear the second bitmap; then right-shift the write address by M bits, and update the second bitmap based on the write address after right-shifting by M bits, and execute S4.

[0101]

[0103] The second bitmap is updated based on the write address that is right-shifted by M bits, that is, the write operation identifier corresponding to the write address is recorded in the second bitmap.

[0102]

[0104] S4. Determine whether the current timing fine-grained unit time belongs to an odd-numbered fine-grained unit time; if so, execute S5; if not, execute S6.

[0103]

[0105] S5. If the current time is the start time of the fine-grained unit time of the current timing, first clear the first Bloom filter; then update the first Bloom filter based on the write address, and execute S7.

[0104]

[0106] Updating the first Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the first Bloom filter.

[0105]

[0107] S6. If the current time is the start time of the fine-grained unit time of the current timing, first clear the second Bloom filter; then update the second Bloom filter based on the write address, and execute S7.

[0106]

[0108] Updating the second Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the second Bloom filter.

[0107]

[0109] S7. Write the data requested by the write I / O request into the storage unit.

[0108]

[0110] After writing data based on the above-described write process, the following describes the phase-change memory read process in conjunction with Figure 7 . Figure 7 is a flowchart of another phase-change memory data access method provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with first, second, and third read voltages that have a minimum read-after-write delay in ascending order. The method is executed by the controller. Referring to Figure 7 , the method may include the following steps.

[0109]

[0111] 701. In response to a read I / O request including a read address, search for a first write operation identifier of the read address in a first bitmap and a second bitmap included in a first SRAM.

[0110]

[0112] 702. If the first write operation identifier of the read address is not found in the first bitmap and the second bitmap, the third read voltage is selected as the target read voltage and step 704 is executed.

[0111]

[0113] 703. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, then based on the presence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM, one of the first read voltage and the second read voltage is selected as the target read voltage, and step 704 is executed.

[0112]

[0114] Exemplarily, step 703 is implemented as follows: searching for the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter; if the second write operation identifier of the read address is not found, selecting the second read voltage from the first read voltage and the second read voltage as the target read voltage; if the second write operation identifier of the read address is found, selecting the first read voltage from the first read voltage and the second read voltage as the target read voltage.

[0113]

[0115] 704. Perform a read operation on a storage cell corresponding to a read address in the storage medium according to a target read voltage.

[0114]

[0116] In this embodiment, the first bitmap is associated with odd-numbered coarse-grained unit times, the second bitmap is associated with even-numbered coarse-grained unit times, and the duration of the coarse-grained unit time is associated with the minimum read-after-write delay of the third read voltage; the first Bloom filter is associated with odd-numbered fine-grained unit times, the second Bloom filter is associated with even-numbered fine-grained unit times, and the duration of the fine-grained unit time is associated with the minimum read-after-write delay of the second read voltage.

[0115]

[0117] In this embodiment, the PCM controller receives a read UO request including a read address from the host and responds. During the response process, the read address in the LA format in the read UO request may be converted into a read address in the PA format, but the present invention is not limited thereto.

[0116]

[0118] During the write phase, a bitmap provided by the SRAM is used to record whether a write operation has occurred within each coarse-grained time unit. Specifically, for write operations initiated within odd-numbered coarse-grained time units, the first bitmap contained in the first SRAM already stores a first write operation identifier corresponding to at least one write address. For write operations initiated within even-numbered coarse-grained time units, the second bitmap contained in the first SRAM already stores a first write operation identifier corresponding to at least one write address.

[0117]

[0119] Therefore, when responding to a read I / O request, the controller of the PCM first searches for the first write operation identifier of the read address in the first bitmap and the second bitmap included in the first SRAM.

[0118]

[0120] As an example, using the read address as a key, various mapping functions, such as a hash function, in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the target bitmap's bit array is queried. If the value of the bit at the mapping position of the read address in the queried target bitmap's bit array is 1, it indicates that the first write operation identifier of the read address has been queried. If the value of the bit at the mapping position of the read address in the queried target bitmap's bit array is 0, it indicates that the first write operation identifier of the read address has not been queried. The target bitmap is either the first bitmap or the second bitmap.

[0119]

[0121] As another example, the read address is right-shifted by M bits, where M is a positive integer. Using the read address after the M-bit right-shift, as a key, various mapping functions, such as a hash function, in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is queried. If the value of the bit at the mapping position of the read address in the queried target bitmap is 1, it indicates that the first write operation identifier of the read address has been queried. If the value of the bit at the mapping position of the read address in the queried target bitmap is 0, it indicates that the first write operation identifier of the read address has not been queried. The target bitmap is either the first bitmap or the second bitmap.

[0120]

[0122] For better understanding, Figure 4 is used as an example. For all read I / O requests received by the PCM controller, both bitmaps are checked to determine whether the first write operation flag of the read address is in either bitmap. If not, the third read voltage is selected as the target read voltage. If it is in either bitmap, read voltage differentiation is required.

[0121]

[0123] It's worth noting that, based on the actual host's access locality principle, distinguishing the third read voltage based on a coarse-grained unit time (e.g., 100 seconds) can maintain a high probability of correctly reading data. Taking M as 16, the address granularity of each bit in the bitmap array is 64K (kilobytes). Specifically, taking the PCM capacity of 256GB (gigabytes) as an example, only 256G / 64K*2=8Mbit=1MB is required.

[0122] A PCM controller can provide 1 MB of SRAM resources with little impact on the overall system latency and bandwidth. If the PCM has a larger capacity, the address granularity represented by each bit can be appropriately increased.

[0123]

[0124] In this embodiment, if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, it indicates that the memory cell corresponding to the read address has not been written to within the time range corresponding to the coarse-grained unit time. In this case, the third read voltage is selected as the target read voltage. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, it indicates that the memory cell corresponding to the read address has a high probability of being written to within the time range corresponding to the coarse-grained unit time. In this case, the first Bloom filter and the second Bloom filter are used to determine whether the first read voltage or the second read voltage should be selected as the target read voltage.

[0124]

[0125] When selecting a target read voltage using the first and second Bloom filters, the second write operation identifier of the read address is searched in the first and second Bloom filters. Specifically, using the read address as a key, various mapping functions, such as a hash function, in the target Bloom filter are invoked to determine multiple mapping locations of the read address in the target Bloom filter. The values ​​of the bits at the multiple mapping locations of the read address in the bit array of the target Bloom filter are then searched. If the values ​​of the bits at the multiple mapping locations of the read address in the searched bit array of the target Bloom filter are all 1, then the second write operation identifier of the read address has been found. If the values ​​of one or more bits at the multiple mapping locations of the read address in the searched bit array of the target Bloom filter are 0, then the second write operation identifier of the read address has not been found. The target Bloom filter is either the first Bloom filter or the second Bloom filter.

[0125]

[0126] In this embodiment, if the second write operation identifier of the read address is not found in either the first Bloom filter or the second Bloom filter, the second read voltage is selected from the first read voltage and the second read voltage as the target read voltage. If the second write operation identifier of the read address is found in the first Bloom filter and / or the second Bloom filter, it indicates that the memory cell corresponding to the read address has been written within the time range corresponding to the fine-grained unit time, and the first read voltage is selected from the first read voltage and the second read voltage as the target read voltage.

[0126]

[0127] For a better understanding, Figure 5 is used as an example. For all read UO requests received by the PCM controller, both Bloom filters are checked to determine whether the second write operation identifier of the read address exists in either Bloom filter. Specifically, the read address is right-shifted by M bits, and the M-bit right-shifted read address is used as the key. Multiple hash functions of the target Bloom filter are invoked to map the key, obtaining multiple mapping locations of the read address in the target Bloom filter's bit array. These multiple hash functions are denoted as Hash 10, Hash 11, and Hash 12, respectively. If the value of one or more bits at the multiple mapping locations of the read address in the target Bloom filter's bit array is 0, it indicates that the second write operation identifier of the read address has not been found. If the value of all bits at the multiple mapping locations of the read address in the target Bloom filter's bit array is 1, it indicates that the second write operation identifier of the read address has been found. If it is not in any Bloom filter, the second read voltage is selected as the target read voltage; if it is in any Bloom filter, the first read voltage is selected as the target read voltage.

[0127]

[0128] Because Bloom filters have a certain degree of false positives, the probability of false positives is related to the size of the bit array in the Bloom filter and the number of mapping functions. Research has found that with a designed bandwidth of 8 GB / s and four hash functions, the probability of reading erroneous data is less than 0.0561. The PCM controller only requires 9.6MB of SRAM, which is readily available. This significantly reduces the probability of read retries, and multiple mapping functions can be calculated and checked simultaneously, with minimal impact on the PCM controller's latency and bandwidth. In practical applications, the bandwidth and number of mapping functions can be flexibly designed without any restrictions.

[0128]

[0129] In this embodiment, after selecting a target read voltage, a read operation is performed on a storage cell corresponding to a read address in the storage medium at the target read voltage to read data from the storage cell and return the read data to the host. In actual applications, if encoded data is written to the storage cell during the write phase, the ECC module can be invoked to decode the encoded data and return the decoded data to the host.

[0129]

[0130] In some optional embodiments, to improve the reliability of reading correct data, after performing a read operation on a storage cell corresponding to a read address in a storage medium at a target read voltage, if the target read voltage is a first read voltage, error checking and correction (ECC) processing is performed on the read data. If the ECC processing result indicates that the read data is erroneous, a second read voltage and a third read voltage are sequentially selected as the target read voltage, and data is read from the storage cell corresponding to the read address in the storage medium at the target read voltage until the ECC processing result indicates that the read data is correct.

[0130]

[0131] Bloom filters have a false positive rate, meaning that if an element is determined to exist, it may not necessarily exist, but if it is determined to not exist, it is definitely not. Taking this into account, when the first read voltage is selected as the target read voltage, after reading data from the storage cells of the PCM storage medium at the first read voltage, the read data needs to be processed by ECCC to verify whether the data is correct. If the read data is correct, the data is returned to the host, and the read process ends. If the read data is incorrect, the Read Retry mechanism is used to select a new target read voltage from the second or third read voltages and reread the data at the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism selects a new target read voltage from the second or third read voltages and rereads the data at the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism selects a new target read voltage from the second or third read voltages and rereads the data at the new target read voltage. If the newly read data is incorrect, an error message is returned to the host; if the newly read data is correct, the correct newly read data is returned to the host.

[0131]

[0132] In actual applications, when performing ECC processing on the read data, the ECC module uses an ECC algorithm to re-determine the redundant check bits of the read data. If the redundant check bits re-determined using the ECC algorithm are the same as the redundant check bits read from the storage medium, the data read from the storage medium of the PCM is correct read data. If the redundant check bits re-determined using the ECC algorithm are different from the redundant check bits read from the storage medium, the data read from the storage medium of the PCM is incorrect read data.

[0132]

[0133] It is understandable that the Read Retry mechanism is used to attempt to find the correct read voltage only when the target read voltage is the first read voltage and the data read by the first read voltage is erroneous. The probability of this situation occurring is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0133]

[0134] The technical solution provided by the embodiments of this disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the SRAM bitmap records whether a write operation has occurred at each coarse-grained unit time; the SRAM Bloom filter records whether a write operation has occurred at each fine-grained unit time. In this way, during the read phase, even under high bandwidth conditions, the SRAM bitmap and Bloom filter can accurately distinguish the three read voltage levels designed for phase-change memory, achieving a high probability of finding the correct read voltage to respond to a read UO request. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with minimal impact on overall system latency and bandwidth.

[0134]

[0135] To better understand the read process, a specific read process is described below in conjunction with FIG8 . FIG8 is a flow chart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. Referring to FIG8 , the method may include the following steps.

[0135]

[0136] S1. In response to a read I / O request including a read address, searching a first write operation identifier of the read address in a first bitmap and a second bitmap included in a first SRAM, and executing step S2 or S3.

[0136]

[0137] S2. If the first write operation identifier of the read address is not found in the first bitmap and the second bitmap, the third read voltage is selected as the target read voltage, and step S6 is executed.

[0137]

[0138] S3. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, the second write operation identifier of the read address is searched in the first Bloom filter and the second Bloom filter, and step S4 or S5 is executed.

[0138]

[0139] S4. If the second write operation identifier of the read address is not found, the second read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0139]

[0140] S5. If the second write operation identifier of the read address is found, the first read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0140]

[0141] S6. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0141]

[0142] The above embodiment describes a case where a phase change memory is configured with three levels of read voltage. The following describes a case where a phase change memory is configured with two levels of read voltage.

[0142]

[0143] In one case, FIG9 and FIG10 are combined to describe how to use two Bloom filters included in the SRAM provided by the controller to access data.

[0143]

[0144] FIG9 is a flowchart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays ranging from small to large. The method, executed by the controller, as shown in FIG9 , may include the following steps.

[0144]

[0145] S1. In response to a write I / O request including a write address, a target Bloom filter is selected from a third Bloom filter and a fourth Bloom filter included in a third SRAM based on the parity of a currently counted unit time. The third Bloom filter is associated with odd-numbered unit times, the fourth Bloom filter is associated with even-numbered unit times, and the duration of the unit time is associated with the minimum read-after-write delay of a fifth read voltage.

[0146] In this embodiment, when the phase-change memory controller includes at least a third SRAM, it can correctly distinguish between two read voltage levels. The two read voltage levels to be distinguished are referred to herein as the fourth read voltage and the fifth read voltage, respectively. The minimum read-after-write delay of the fourth read voltage is less than the minimum read-after-write delay of the fifth read voltage. In practical applications, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages may not overlap. Furthermore, optionally, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages partially overlap. It is understood that the minimum read-after-write delay of the fifth read voltage is less than the maximum read-after-write delay of the fourth read voltage.

[0145]

[0147] In this embodiment, the unit time is related to the minimum read-after-write delay of the fifth read voltage. For example, the unit time is equal to the minimum read-after-write delay of the fifth read voltage, or the unit time is obtained by increasing or decreasing the minimum read-after-write delay of the fifth read voltage. This is not limited to this.

[0146]

[0148] In this embodiment, the two Bloom filters provided by the third SRAM can record whether a write operation occurs in each unit time.

[0147]

[0149] Specifically, the PCM controller receives a write I / O request including a write address from a host and responds to it. During the response, the write address in LA format in the write I / O request may be converted to a write address in PA format. Alternatively, the ECC module may be invoked to encode the write data requested by the write I / O request and determine redundancy check bits of the write data using an ECC algorithm, but the present invention is not limited thereto.

[0148]

[0150] In this embodiment, when the PCM controller responds to a write UO request, it determines the number of the current time unit and the parity type based on the current time and the starting point. The starting point can be flexibly set as needed. For example, the timing starts at PCM startup, i.e., the starting point is the PCM startup time.

[0149]

[0151] If the unit time of the current timing is of odd type, it means that the unit time of the current timing is an odd-numbered unit time, and the third Bloom filter is selected from the third Bloom filter and the fourth Bloom filter included in the third SRAM as the target Bloom filter; if the unit time of the current timing is of even type, it means that the unit time of the current timing is an even-numbered unit time, and the fourth Bloom filter is selected from the third Bloom filter and the fourth Bloom filter included in the third SRAM as the target Bloom filter.

[0150]

[0152] Taking a unit time of 100 seconds as an example, the time ranges corresponding to odd-numbered unit times are: 0-100 seconds, 200 seconds -300 seconds, 400 seconds -500 seconds, etc.; the time ranges corresponding to even-numbered unit times are: 100 seconds to 200 seconds, 300 seconds to 400 seconds, 500 seconds to 600 seconds, etc.

[0151]

[0153] S2. Save the write operation identifier of the write address in the target Bloom filter, where the write operation identifier indicates that a write operation has been performed on the target storage unit corresponding to the write address in the storage medium.

[0152]

[0154] Exemplarily, the implementation method of storing the write operation identifier of the write address in the target Bloom filter is: determining a mapping position of the write address in the bit array of the target Bloom filter; and setting the value of the bit at the second mapping position as the write operation identifier of the write address, so as to store the write operation identifier of the write address in the target Bloom filter.

[0153]

[0155] Specifically, using the write address as a key, multiple mapping functions, such as a hash function, are called in the target Bloom filter to determine multiple mapping locations of the write address in the target Bloom filter's bit array. The values ​​of the bits at the multiple mapping locations of the write address in the target Bloom filter's bit array are set to 1, and the corresponding 1 bit in the target Bloom filter's bit array represents a write operation flag for the write address, thereby storing the write operation flag for the write address in the target Bloom filter. It should be understood that if a 0 bit in the target Bloom filter's bit array indicates that the write address has not been recorded.

[0154]

[0156] Further, optionally, before storing the write operation identifier of the write address in the target Bloom filter, the method further includes: if the current time is the start time of the currently measured unit time, clearing the target Bloom filter, that is, setting the value of each bit in the bit array of the target Bloom filter to 0. If the current time is not the start time of the currently measured unit time, directly storing the write operation identifier of the write address in the target Bloom filter. In this way, the write operation identifiers of the write addresses within the time range corresponding to the currently measured unit time can be effectively stored in the target Bloom filter, thereby better ensuring the read accuracy of the VO request.

[0155]

[0157] S3. Write the data requested by the write I / O request into the target storage unit.

[0156]

[0158] In practical applications, the data requested by a write VO request can be written directly to the target storage unit, or the ECC module can be called to encode the write data requested by a write I / O request, and the ECC algorithm can be used to determine the redundancy check bits of the write data. The encoded write data and its redundancy check bits can then be written to the target storage unit. There are no restrictions on this.

[0157]

[0159] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs at each unit time. In the subsequent read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory, achieving a high probability of finding the correct read voltage to respond to read I / O requests. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with little impact on overall system latency and bandwidth.

[0158]

[0160] After writing data based on the above-described write process, the phase-change memory read process is described below in conjunction with FIG10 . FIG10 is a flowchart of another phase-change memory data access method provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium, the controller including at least a third SRAM, and the phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays ranging from small to large. The method, executed by the controller, as shown in FIG10 , may include the following steps.

[0159]

[0161] S1. In response to a read UO request including a read address, searching for a write operation identifier of the read address in a third Bloom filter and a fourth Bloom filter.

[0160]

[0162] In this embodiment, the PCM controller receives a read UO request including a read address from the host and responds. During the response process, the read address in the LA format in the read UO request may be converted into a read address in the PA format, but the present invention is not limited thereto.

[0161]

[0163] During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs during each unit time. Specifically, for write operations initiated within odd-numbered unit time ranges, the third Bloom filter included in the third SRAM already stores at least one write operation identifier corresponding to the write address. For write operations initiated within even-numbered unit time ranges, the fourth Bloom filter included in the third SRAM already stores at least one write operation identifier corresponding to the write address.

[0162]

[0164] Therefore, when responding to a read UO request, the PCM controller searches the third and fourth Bloom filters for the write operation flag of the read address. Specifically, using the read address as a key, various mapping functions, such as hash functions, are invoked in the target Bloom filter to determine multiple mapping locations of the read address in the target Bloom filter. The values ​​of the bits at the multiple mapping locations of the read address in the target Bloom filter's bit array are then queried. If the values ​​of the bits at the multiple mapping locations of the read address in the queried target Bloom filter's bit array are all 1, the write operation flag of the read address has been found. If the values ​​of one or more bits at the multiple mapping locations of the read address in the queried target Bloom filter's bit array are 0, the write operation flag of the read address has not been found. The target Bloom filter is the third or fourth Bloom filter.

[0163]

[0165] S2. If no write operation identifier of the read address is found in either the third Bloom filter or the fourth Bloom filter, selecting the fifth read voltage as the target read voltage;

[0164]

[0166] S3. If the write operation identifier of the read address is found in the third Bloom filter and the fourth Bloom filter, the fourth read voltage is selected as the target read voltage.

[0165]

[0167] S4. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0166]

[0168] The specific implementation of the read operation is similar to that of the above embodiment and will not be repeated here.

[0167]

[0169] In some optional embodiments, taking into account the characteristic of a Bloom filter having a false positive rate, in order to improve the reliability of reading correct data, after performing a read operation on a storage cell corresponding to a read address in a storage medium according to a target read voltage, if the target read voltage is the fourth read voltage, error checking and correction ECC processing is performed on the read data; if the ECC processing result indicates that the read data is erroneous, the fifth read voltage is used as the target read voltage, and the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage is executed again.

[0168]

[0170] It is understandable that the Read Retry mechanism is used to attempt to find the correct read voltage only when the target read voltage is the fourth read voltage and the data read by the fourth read voltage is erroneous. The probability of this situation occurring is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0169]

[0171] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs within each unit time. Thus, during the read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory, achieving a high probability of finding the correct read voltage to respond to read I / O requests in one go. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with little impact on overall system latency and bandwidth.

[0170]

[0172] In another case, FIG. 11 and FIG. 12 are combined to describe how to use the two bitmaps included in the SRAM provided by the controller to access data.

[0171]

[0173] FIG11 is a flowchart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays ranging from small to large. The method, executed by the controller, as shown in FIG11 , may include the following steps.

[0172]

[0174] S1. In response to a write I / O request including a write address, a target bitmap is selected from a third bitmap and a fourth bitmap included in a third SRAM based on the parity type of a currently counted unit time. The third bitmap is associated with odd-numbered unit times, the fourth bitmap is associated with even-numbered unit times, and the duration of the unit time is associated with a minimum read-after-write delay of a fifth read voltage.

[0173]

[0175] In this embodiment, when the phase-change memory controller includes at least a third SRAM, it can correctly distinguish between two read voltage levels. The two read voltage levels to be distinguished are referred to herein as the fourth read voltage and the fifth read voltage, respectively. The minimum read-after-write delay of the fourth read voltage is less than the minimum read-after-write delay of the fifth read voltage. In practical applications, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages may not overlap. Furthermore, optionally, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages partially overlap. It is understood that the minimum read-after-write delay of the fifth read voltage is less than the maximum read-after-write delay of the fourth read voltage.

[0174]

[0176] In this embodiment, the unit time is related to the minimum read-after-write delay of the fifth read voltage. For example, the unit time is equal to the minimum read-after-write delay of the fifth read voltage, or the unit time is obtained by increasing or decreasing the minimum read-after-write delay of the fifth read voltage. This is not limited to this.

[0175]

[0177] In this embodiment, the two bitmaps provided by the third SRAM can be used to record whether a write operation occurs in each unit time.

[0176]

[0178] Specifically, the PCM controller receives a write I / O request including a write address from a host and responds to it. During the response, the write address in LA format in the write I / O request may be converted to a write address in PA format. Alternatively, the ECC module may be invoked to encode the write data requested by the write I / O request and determine redundancy check bits of the write data using an ECC algorithm, but the present invention is not limited thereto.

[0177]

[0179] In this embodiment, when the PCM controller responds to a write UO request, it determines the number of the current time unit and the parity type based on the current time and the starting point. The starting point can be flexibly set as needed. For example, the timing starts at PCM startup, i.e., the starting point is the PCM startup time.

[0178]

[0180] If the unit time of the current timing is an odd type, it means that the unit time of the current timing is an odd-numbered unit time, and the third bitmap from the third bitmap and the fourth bitmap included in the third SRAM is used as the target bitmap; if the unit time of the current timing is an even type, it means that the unit time of the current timing is an even-numbered unit time, and the fourth bitmap from the third bitmap and the fourth bitmap included in the third SRAM is used as the target bitmap.

[0179]

[0181] S2. Save the write operation identifier of the write address in the target bitmap, where the write operation identifier indicates that a write operation has been performed on the target storage unit corresponding to the write address in the storage medium.

[0180]

[0182] Specifically, when storing the write operation identifier of the write address in the target bitmap, the write address is used as a key, and various mapping functions in the target bitmap, such as a hash function, are called to determine the mapping location of the write address in the target bitmap. The value of the bit at the mapping location of the write address in the bit array of the target bitmap is set to 1. A 1 bit in the bit array of the target bitmap represents the write operation identifier of the write address, and the write operation identifier of the write address is stored in the target bitmap. It is understood that a 0 bit in the bit array of the target bitmap indicates that the write address has not been recorded.

[0181]

[0183] Regarding unit time, due to its relatively large time range, it is difficult to record every write address without affecting the bandwidth and latency of the service system using PCM. Therefore, a mapping table-like approach is adopted to increase the granularity of each bit in the target bitmap's bit array. In other words, each bit can be used to determine whether a write operation has been performed on the target storage cell corresponding to a write address within a certain address range. From the perspective of the entire PCM, this improves the probability of correctly distinguishing read voltages.

[0182]

[0184] Based on the above, further optionally, when storing the write operation flag of the write address in the target bitmap, the write address may be right-shifted by M bits, where M is a positive integer; a mapping position corresponding to the write address in the bit array of the target bitmap is determined based on the right-shifted write address; and the value of the bit at the mapping position is set as the write operation flag of the write address, thereby storing the write operation flag of the write address in the target bitmap.

[0183]

[0185] Specifically, the write address after right shifting by M bits is used as the key, and various mapping functions such as a hash function in the target bitmap are called to determine the mapping position corresponding to the write address in the bit array of the target bitmap. The value of the bit at the mapping position corresponding to the write address in the bit array of the target bitmap is set to 1. One bit in the bit array of the target bitmap represents the write operation identifier of each write address within the two countries, so that the write operation identifier of the write address is stored in the target bitmap.

[0184]

[0186] Further, optionally, before storing the write operation identifier of the write address in the target bitmap, the method further includes: if the current time is the start time of the current measured unit time, clearing the target bitmap, that is, setting the value of each bit in the bit array of the target bitmap to 0. If the current time is not the start time of the current measured unit time, directly storing the write operation identifier of the write address in the target bitmap. In this way, the write operation identifiers of the write addresses within the time range corresponding to the current measured unit time can be effectively stored in the target bitmap, thereby better ensuring the read accuracy of the I / O request.

[0185]

[0187] S3. Write the data requested by the write I / O request into the target storage unit.

[0186]

[0188] The specific implementation of the write operation is similar to that of the above embodiment and will not be described in detail here.

[0187]

[0189] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, a bitmap provided by the SRAM can be used to record whether a write operation occurs per unit time. Thus, during the read phase, even under high bandwidth conditions, the bitmap provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory. This allows for a high probability of finding the correct read voltage to respond to read I / O requests in one go, significantly reducing the number of read retries and greatly optimizing the QoS of service systems using phase-change memory with little impact on overall system latency and bandwidth.

[0188]

[0190] After writing data based on the above-mentioned writing process, the reading process of the phase change memory is described below in conjunction with FIG. 12 .

[0189]

[0191] FIG12 is a flowchart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with fourth and fifth read voltages that have a minimum read-after-write delay ranging from small to large. The method, executed by the controller, as shown in FIG12 , may include the following steps.

[0190]

[0192] S1. In response to a read I / O request including a read address, searching for a write operation identifier of the read address in the third bitmap and the fourth bitmap.

[0191]

[0193] In this embodiment, the PCM controller receives a read UO request including a read address from the host and responds. During the response process, the read address in the LA format in the read UO request may be converted into a read address in the PA format, but the present invention is not limited thereto.

[0192]

[0194] During the write phase, the bitmap provided by the SRAM can be used to record whether a write operation occurs in each unit time. Specifically, for write operations initiated within the time range of odd-numbered unit time, the third bitmap included in the third SRAM already stores a write operation identifier corresponding to at least one write address. For write operations initiated within the time range of even-numbered unit time, the fourth bitmap included in the third SRAM already stores a write operation identifier corresponding to at least one write address.

[0193]

[0195] Therefore, when responding to a read UO request, the PCM controller searches the third bitmap and the fourth bitmap for the write operation identifier of the read address.

[0194]

[0196] As an example, using the read address as a key, various mapping functions, such as a hash function, in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is queried. If the value of the bit at the mapping position of the read address in the queried target bitmap is 1, it indicates that the write operation flag of the read address has been queried. If the value of the bit at the mapping position of the read address in the queried target bitmap is 0, it indicates that the write operation flag of the read address has not been queried. The target bitmap is the third bitmap or the fourth bitmap.

[0195]

[0197] As another example, the read address is right-shifted by M bits, where M is a positive integer. Using the read address after the M-bit right-shift, as a key, various mapping functions, such as a hash function, in the target bitmap are called to determine the mapping position of the read address in the target bitmap. The value of the bit at the mapping position of the read address in the bit array of the target bitmap is queried. If the value of the bit at the mapping position of the read address in the queried bit array of the target bitmap is 1, it indicates that the write operation flag of the read address has been queried. If the value of the bit at the mapping position of the read address in the queried bit array of the target bitmap is 0, it indicates that the write operation flag of the read address has not been queried. The target bitmap is the third bitmap or the fourth bitmap.

[0196]

[0198] S2. If the write operation identifier of the read address is not found in either the third bitmap or the fourth bitmap, then the fifth read voltage is selected as the target read voltage.

[0197]

[0199] S3. If the write operation identifier of the read address is found in the third bitmap and / or the fourth bitmap, the fourth read voltage is selected as the target read voltage.

[0198]

[0200] S4. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0199]

[0201] The specific implementation of the read operation is similar to that of the above embodiment and will not be repeated here.

[0200]

[0202] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, a bitmap provided by the SRAM can be used to record whether a write operation occurs per unit time. Thus, during the read phase, even under high bandwidth conditions, the bitmap provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory. This allows for a high probability of finding the correct read voltage to respond to read I / O requests in one go, significantly reducing the number of read retries and greatly optimizing the QoS of service systems using phase-change memory with little impact on overall system latency and bandwidth.

[0201]

[0203] The following describes the case where a phase change memory is configured with a three-level read voltage and a two-level read voltage and a Bloom filter group is applied.

[0202]

[0204] In practical applications, when a phase-change memory is configured with three read voltage levels, two bitmaps provided by the first SRAM can be used to record whether a write operation occurs at each coarse-grained unit time; and a Bloom filter group provided by the second SRAM can be used to record whether a write operation occurs at each fine-grained unit time. The two bitmaps provided by the first SRAM can be used to distinguish between (Vread1 / Vread2) and Vread3, thereby determining whether the selected read voltage is either the third read voltage Vread3, the second read voltage Vread2, or the first read voltage Vread1. The Bloom filter group provided by the second SRAM can be used to distinguish between Vread1 and (Vread2 / Vread3), thereby determining whether the selected read voltage is either the first read voltage Vread1, the second read voltage Vread2, or the third read voltage Vread3. The combination of the first and second SRAMs can accurately distinguish between the three read voltage levels.

[0203]

[0205] Therefore, in view of the situation where the phase change memory is configured with three read voltage levels, the following describes a write process using two bitmaps provided by the first SRAM and a Bloom filter group provided by the second SRAM in conjunction with FIG. 13 .

[0204]

[0206] FIG13 is a flowchart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order. The method, executed by the controller, as shown in FIG13 , may include the following steps.

[0205]

[0207] 801. In response to a write UO request including a write address, a target bitmap is selected from a first bitmap and a second bitmap included in a first SRAM according to the parity type of a coarse-grained unit time of a current timing, wherein the duration of the coarse-grained unit time is related to a minimum post-write read delay of a third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage in a read phase.

[0206]

[0208] The implementation of step 801 can refer to the implementation of step 301 in the above embodiment, which will not be repeated here.

[0207]

[0209] 802. Save a first write operation identifier of the write address in a target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium.

[0208]

[0210] The implementation of step 802 can refer to the implementation of step 302 in the above embodiment, which will not be repeated here.

[0209]

[0211] 803. Based on a target arrangement position of a sub-unit time to which the current time belongs within a fine-grained unit time currently being counted, a target Bloom filter located at the target arrangement position is selected from a Bloom filter group included in a second SRAM, wherein the fine-grained unit time includes n sub-unit times divided in sequence, the duration of the fine-grained unit time is related to a minimum read-after-write delay of the second read voltage, the Bloom filter group is used to select the first read voltage or the second read voltage during a read phase, and the Bloom filter group includes n Bloom filters arranged in sequence.

[0210]

[0212] In this embodiment, the Bloom filter group included in the second SRAM includes n Bloom filters arranged in sequence, where n is a positive integer greater than or equal to 3, and each fine-grained unit time includes n sub-unit times divided in sequence. In this way, the write address corresponding to the write UO request in a sub-unit time of each fine-grained unit time is recorded in a Bloom filter. For example, a Bloom filter group includes 10 Bloom filters. Taking the length of a fine-grained unit time as 100 ms as an example, a fine-grained unit time is divided into 10 sub-unit time, each sub-unit time is 10 ms long, the time range corresponding to the first sub-unit time is 0-10 ms, the time range corresponding to the second sub-unit time is 10-20 ms, the time range corresponding to the third sub-unit time is 20-30 ms, the time range corresponding to the fourth sub-unit time is 30-40 ms, the time range corresponding to the fifth sub-unit time is 40-50 ms, the time range corresponding to the sixth sub-unit time is 50-60 ms, the time range corresponding to the seventh sub-unit time is 60-70 ms, the time range corresponding to the eighth sub-unit time is 70-80 ms, and the time range corresponding to the ninth sub-unit time is 80-90 ms. The time range corresponding to the 10th sub-unit time is: 90-100 mSo

[0211]

[0213] Specifically, in the process of responding to the write I / O request, the PCM controller further determines, based on the current time and the starting point of the timing, which fine-grained unit time the currently measured fine-grained unit time is, and determines a target arrangement position of the sub-unit time to which the current time belongs within the currently measured fine-grained unit time. The target arrangement position may be, for example, any one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, or tenth Bloom filters. A target Bloom filter located at the target arrangement position is selected from the Bloom filter group included in the second SRAM. For example, the target Bloom filter may be any one of the first, second, or tenth Bloom filters.

[0212]

[0214] 804. Save a second write operation identifier of the write address in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit.

[0213]

[0215] Exemplarily, storing the second write operation identifier of the write address in the target Bloom filter is implemented by: determining a second mapping location of the write address in the bit array of the target Bloom filter; and setting the value of the bit at the second mapping location as the second write operation identifier of the write address, thereby storing the second write operation identifier of the write address in the target Bloom filter.

[0214]

[0216] The implementation of step 804 can refer to the implementation of step 304 in the above embodiment, which will not be repeated here.

[0215]

[0217] Further optionally, before storing the second write operation identifier of the write address in the target Bloom filter, the method further includes: if the currently measured time is not the first fine-grained unit time, clearing the target Bloom filter, that is, setting the value of each bit in the bit array of the target Bloom filter to 0. If the currently measured time is the first fine-grained unit time, directly storing the second write operation identifier of the write address in the target Bloom filter. This ensures that the second write operation identifier of the write address within a sub-unit time of the currently measured fine-grained unit time is well stored in the target Bloom filter, thereby better ensuring the read correctness of the I / O request.

[0216]

[0218] For a better understanding, the following description is provided in conjunction with FIG14. Referring to FIG14, if the PCM controller receives a write UO request from the host within a certain fine-grained unit time range, using the write address as the key, and if the current time falls within the time range of the first sub-unit time of the certain fine-grained unit time, multiple hash functions of the first Bloom filter in the Bloom filter group are invoked to map the key, obtaining multiple mapping locations corresponding to the write address in the bit array of the first Bloom filter. These multiple hash functions are respectively denoted as Hash 00, Hash 01, and Hash 02. For example, if the length of the bit array of the first Bloom filter is 12 bits, the mapping locations corresponding to the write address in the bit array of the first Bloom filter are the second, fourth, and ninth bits. The values ​​of the fourth and ninth bits in the bit array of the first Bloom filter are both set to 1 to indicate that the write address corresponding to the write UO request has been written.

[0217]

[0219] If the current time falls within the second sub-unit time of a fine-grained unit time, multiple hash functions of the second Bloom filter in the Bloom filter group are called to map the key, obtaining multiple mapping locations corresponding to the write address in the second Bloom filter's bit array. These multiple hash functions are denoted as Hash 10, Hash 11, and Hash 12. For example, if the second Bloom filter's bit array is 12 bits long, the mapping locations corresponding to the write address in the first Bloom filter's bit array are bits 1, 6, and 10. The values ​​of bits 1, 6, and 10 in the second Bloom filter's bit array are all set to 1 to indicate that the write address corresponding to the write VO request has been written.

[0218]

[0220] By analogy, if the current time falls within the time range of the nth sub-unit time of a fine-grained unit time, multiple hash functions of the nth Bloom filter in the Bloom filter group are called to map the key. This results in multiple mapping locations corresponding to the write address in the nth Bloom filter's bit array. These multiple hash functions are denoted as Hash n0, Hash n1, and Hash n2. For example, if the nth Bloom filter's bit array is 12 bits long, the mapping locations corresponding to the write address in the nth Bloom filter's bit array are bits 1, 6, and 10. The values ​​of bits 1, 6, and 10 in the nth Bloom filter's bit array are all set to 1 to indicate that the write address corresponding to the write I / O request has been written.

[0219]

[0221] In addition, after the PCM controller receives a write I / O request from the host, if the current time is not the first fine-grained unit time, it first clears the target Bloom filter and then calls the target Bloom filter. If the current time is the first fine-grained unit time, it can directly call the target Bloom filter.

[0220]

[0222] 805. Write the data requested by the write VO request into the target storage unit.

[0221]

[0223] The implementation of step 805 can refer to the implementation of step 305 in the above embodiment, which will not be repeated here.

[0222]

[0224] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the SRAM bitmap records whether a write operation has occurred within each coarse-grained unit time. The SRAM Bloom filter group records whether a write operation has occurred within the multiple sub-unit times within each fine-grained unit time. In this way, during the subsequent read phase, even under high bandwidth conditions, the SRAM bitmap and Bloom filter can accurately distinguish the three read voltage levels designed for the phase-change memory, achieving a high probability of finding the correct read voltage to respond to read I / O requests. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with little impact on overall system latency and bandwidth. Furthermore, it is worth noting that compared to using two Bloom filters in the SRAM, using the SRAM Bloom filter group saves more SRAM resources, resulting in a more significant advantage.

[0223]

[0225] To better understand the write process, a specific write process is described below in conjunction with FIG15. FIG15 is a flowchart of another data access method for a phase change memory provided by an embodiment of the present disclosure. Referring to FIG15, the method may include the following steps.

[0224]

[0226] S1. In response to a write UO request, it is determined whether the coarse-grained unit time of the current timing belongs to an odd-numbered coarse-grained unit time; if so, execute S2; if not, execute S3.

[0225]

[0227] S2. If the current time is the start time of the coarse-grained unit time of the current timing, first clear the first bitmap; then right-shift the write address by M bits, and update the first bitmap based on the write address after right-shifting by M bits, and execute S4.

[0226]

[0228] The first bitmap is updated based on the write address after being right-shifted by M bits, that is, the write operation identifier corresponding to the write address is recorded in the first bitmap.

[0227]

[0229] S3. If the current time is not the start time of the coarse-grained unit time of the current timing, first clear the second bitmap; then right-shift the write address by M bits, and update the second bitmap based on the write address after right-shifting by M bits, and execute S4.

[0228]

[0230] The second bitmap is updated based on the write address that is right-shifted by M bits, that is, the write operation identifier corresponding to the write address is recorded in the second bitmap.

[0229]

[0231] S4. Selecting a target Bloom filter located at the target arrangement position from a Bloom filter group included in the second SRAM based on a target arrangement position of the sub-unit time to which the current time belongs within the fine-grained unit time currently being measured. The fine-grained unit time includes n sub-unit times divided in sequence, the duration of the fine-grained unit time is related to a minimum read-after-write delay of the second read voltage, the Bloom filter group is used to select the first read voltage or the second read voltage during a read phase, and the Bloom filter group includes n sequentially arranged Bloom filters.

[0230]

[0232] S5. If the currently counted fine-grained unit time is not the first fine-grained unit time, first clear the target Bloom filter, and then update the target Bloom filter based on the write address; if the currently counted fine-grained unit time is the first fine-grained unit time, update the target Bloom filter based on the write address.

[0231]

[0233] Here, updating the target Bloom filter based on the write address means recording the write operation identifier corresponding to the write address in the target Bloom filter.

[0232]

[0234] S6. Write the data requested by the write I / O request into the storage unit.

[0233]

[0235] After writing data based on the above-described write process, the following describes the phase-change memory read process in conjunction with FIG16 . FIG16 is a flowchart of another phase-change memory data access method provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium, the controller including at least a first SRAM and a second SRAM. The phase-change memory is configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order. The method, executed by the controller, as shown in FIG16 , may include the following steps.

[0234]

[0236] 901. In response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in a first SRAM.

[0235]

[0237] For the implementation of step 901, reference may be made to the implementation of step 701 in the embodiment shown in FIG. 7 , which will not be described in detail here.

[0236]

[0238] 902. If the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, the third read voltage is selected as the target read voltage.

[0237]

[0239] Regarding the implementation of step 902, reference may be made to the implementation of step 702 in the embodiment shown in FIG. 7 , which will not be described in detail here.

[0238]

[0240] 903. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, then based on the existence of the second write operation identifier of the read address in the Bloom filter group included in the second SRAM, select one of the first read voltage and the second read voltage as the target read voltage.

[0239]

[0241] Exemplarily, step 903 is implemented by searching the Bloom filter set for the second write operation identifier of the read address; if the second write operation identifier of the read address is not found, selecting the second read voltage from the first read voltage and the second read voltage as the target read voltage; and if the second write operation identifier of the read address is found in the target Bloom filter in the Bloom filter set, selecting the first read voltage from the first read voltage and the second read voltage as the target read voltage.

[0240]

[0242] When selecting a target read voltage using a Bloom filter group, the second write operation identifier of the read address is searched for in each Bloom filter included in the Bloom filter group. Specifically, using the read address as a key, various mapping functions, such as a hash function, in any Bloom filter are called to determine multiple mapping locations of the read address in the Bloom filter. The values ​​of the bits at the multiple mapping locations of the read address in the Bloom filter's bit array are then searched. If the values ​​of the bits at the multiple mapping locations of the read address in the searched Bloom filter's bit array are all 1, then the second write operation identifier of the read address has been found. If the values ​​of one or more bits at the multiple mapping locations of the read address in the searched Bloom filter's bit array are 0, then the second write operation identifier of the read address has not been found.

[0241]

[0243] In this embodiment, if the second write operation identifier of the read address is not found in any of the Bloom filter groups, the second read voltage is selected as the target read voltage from the first read voltage and the second read voltage. If the second write operation identifier of the read address is found in the Bloom filter group, it indicates that the first read voltage is selected as the target read voltage from the first read voltage and the second read voltage.

[0242]

[0244] For a better understanding, Figure 14 is used as an example. For all read UO requests received by the PCM controller, each Bloom filter included in the Bloom filter group is checked to determine whether the second write operation identifier of the read address is found in any Bloom filter. Specifically, the read address is right-shifted by M bits, and the M-bit right-shifted read address is used as the key. Multiple hash functions of each Bloom filter are called to map the key, obtaining multiple mapping locations of the read address in the Bloom filter bit array. For example, the multiple hash functions of the first Bloom filter are respectively denoted as Hash 10, Hash 11, and Hash 12. If the value of one or more bits at the multiple mapping locations of the read address in the queried bit array of the first Bloom filter is 0, it indicates that the second write operation identifier of the read address has not been found. If the value of the bits at the multiple mapping locations of the read address in the queried bit array of the first Bloom filter is all 1, it indicates that the second write operation identifier of the read address has been found. By analogy, all read VO requests received by the PCM controller are evaluated in each Bloom filter included in the Bloom filter group. If the second write operation identifier of the read address is not found in any Bloom filter, the second read voltage is selected as the target read voltage. If the second write operation identifier of the read address is found in any Bloom filter, the first read voltage is selected as the target read voltage.

[0243]

[0245] 904. Perform a read operation on a storage cell corresponding to a read address in a storage medium according to a target read voltage.

[0246] For the implementation of step 904, reference may be made to the implementation of step 704 in the embodiment shown in FIG. 7 , which will not be described in detail here.

[0244]

[0247] In some optional embodiments, to improve the reliability of reading correct data, after performing a read operation on a storage cell corresponding to a read address in a storage medium at a target read voltage, if the target read voltage is a first read voltage, error checking and correction (ECC) processing is performed on the read data. If the ECC processing result indicates that the read data is erroneous, a second read voltage and a third read voltage are sequentially selected as the target read voltage, and data is read from the storage cell corresponding to the read address in the storage medium at the target read voltage until the ECC processing result indicates that the read data is correct.

[0245]

[0248] Bloom filters have a false positive rate, meaning that if an element is determined to exist, it may not necessarily exist, but if it is determined to not exist, it is definitely not. Taking this into account, when the first read voltage is selected as the target read voltage, after reading data from the storage cells of the PCM storage medium at the first read voltage, the read data needs to be processed by ECCC to verify whether the data is correct. If the read data is correct, the data is returned to the host, and the read process ends. If the read data is incorrect, the Read Retry mechanism is used to select a new target read voltage from the second or third read voltages and reread the data at the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism selects a new target read voltage from the second or third read voltages and rereads the data at the new target read voltage. If the newly read data is incorrect, the Read Retry mechanism selects a new target read voltage from the second or third read voltages and rereads the data at the new target read voltage. If the newly read data is incorrect, an error message is returned to the host; if the newly read data is correct, the correct newly read data is returned to the host.

[0246]

[0249] In actual applications, when performing ECC processing on the read data, the ECC module uses an ECC algorithm to re-determine the redundant check bits of the read data. If the redundant check bits re-determined using the ECC algorithm are the same as the redundant check bits read from the storage medium, the data read from the storage medium of the PCM is correct read data. If the redundant check bits re-determined using the ECC algorithm are different from the redundant check bits read from the storage medium, the data read from the storage medium of the PCM is incorrect read data.

[0247]

[0250] It is understandable that the Read Retry mechanism is used to attempt to find the correct read voltage only when the target read voltage is the first read voltage and the data read by the first read voltage is erroneous. The probability of this situation occurring is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0248]

[0251] The technical solution provided by the disclosed embodiments adds a small amount of SRAM resources to the PCM controller. During the write phase, the SRAM bitmap records whether a write operation has occurred at each coarse-grained unit time; the SRAM Bloom filter records whether a write operation has occurred at each fine-grained unit time. In this way, during the read phase, even under high bandwidth conditions, the SRAM bitmap and Bloom filter can accurately distinguish the three read voltage levels designed for phase-change memory, achieving a high probability of finding the correct read voltage to respond to a read UO request. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with minimal impact on overall system latency and bandwidth.

[0249]

[0252] To better understand the read process, a specific read process is described below in conjunction with FIG17. FIG17 is a flowchart of another data access method for a phase change memory provided by an embodiment of the present disclosure. Referring to FIG17, the method may include the following steps.

[0250]

[0253] S1. In response to a read I / O request including a read address, searching a first write operation identifier of the read address in a first bitmap and a second bitmap included in a first SRAM, and executing step S2 or S3.

[0251]

[0254] S2. If the first write operation identifier of the read address is not found in the first bitmap and the second bitmap, the third read voltage is selected as the target read voltage, and step S6 is executed.

[0252]

[0255] S3. If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, the second write operation identifier of the read address is searched in the Bloom filter group, and step S4 or S5 is executed.

[0253]

[0256] S4. If the second write operation identifier of the read address is not found, the second read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0254]

[0257] S5. If the second write operation identifier of the read address is found, the first read voltage is selected from the first read voltage and the second read voltage as the target read voltage, and step S6 is executed.

[0255]

[0258] S6. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0256]

[0259] The following describes how to configure two levels of read voltage for a phase change memory based on a Bloom filter group included in an SRAM. The write process is described in conjunction with FIG18 , and the read process is described in conjunction with FIG19 .

[0257]

[0260] FIG18 is a flowchart of another data access method for a phase-change memory provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium. The controller includes at least a third SRAM. The phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays ranging from small to large. The method, executed by the controller, as shown in FIG18 , may include the following steps.

[0258]

[0261] S1. In response to a write I / O request including a write address, a target Bloom filter located at a target arrangement position in a Bloom filter group included in a third SRAM is selected based on a target arrangement position of a sub-unit time to which the current time belongs within a currently counted unit time. The unit time includes n sequentially divided sub-unit times, a duration of the unit time is related to a minimum read-after-write delay of a fifth read voltage, and the Bloom filter group includes n sequentially arranged Bloom filters.

[0259]

[0262] In this embodiment, when the phase-change memory controller includes at least a third SRAM, it can correctly distinguish between two read voltage levels. The two read voltage levels to be distinguished are referred to herein as the fourth read voltage and the fifth read voltage, respectively. The minimum read-after-write delay of the fourth read voltage is less than the minimum read-after-write delay of the fifth read voltage. In practical applications, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages may not overlap. Furthermore, optionally, the time ranges of the read-after-write delays corresponding to the fourth and fifth read voltages partially overlap. It is understood that the minimum read-after-write delay of the fifth read voltage is less than the maximum read-after-write delay of the fourth read voltage.

[0260]

[0263] In this embodiment, the unit time is related to the minimum read-after-write delay of the fifth read voltage. For example, the unit time is equal to the minimum read-after-write delay of the fifth read voltage, or the unit time is obtained by increasing or decreasing the minimum read-after-write delay of the fifth read voltage. This is not limited to this.

[0261]

[0264] Specifically, the PCM controller receives a write I / O request including a write address from a host and responds to it. During the response, the write address in LA format in the write I / O request may be converted to a write address in PA format. Alternatively, the ECC module may be invoked to encode the write data requested by the write I / O request and determine redundancy check bits of the write data using an ECC algorithm, but the present invention is not limited thereto.

[0265] In this embodiment, the Bloom filter group included in the third SRAM includes n Bloom filters arranged in sequence, n is a positive integer greater than or equal to 3, and each unit time includes n Sub-unit times, thus, the write address corresponding to the write UO request within a sub-unit time of each unit time is recorded into a Bloom filter. For example, a Bloom filter group includes 10 Bloom filters. Taking a unit time of 100 ms as an example, a unit time is divided into 10 sub-unit time, each sub-unit time is 10 ms long, the time range corresponding to the first sub-unit time is 0-10 ms, the time range corresponding to the second sub-unit time is 10-20 ms, the time range corresponding to the third sub-unit time is 20-30 ms, the time range corresponding to the fourth sub-unit time is 30-40 ms, the time range corresponding to the fifth sub-unit time is 40-50 ms, the time range corresponding to the sixth sub-unit time is 50-60 ms, the time range corresponding to the seventh sub-unit time is 60-70 ms, the time range corresponding to the eighth sub-unit time is 70-80 ms, and the time range corresponding to the ninth sub-unit time is 80-90 ms. The time range corresponding to the 10th sub-unit time is: 90-100 ms.

[0262]

[0266] Specifically, in the process of responding to the write I / O request, the PCM controller further determines, based on the current time and the starting point of the timing, which unit time the currently measured unit time is, and determines a target arrangement position of the sub-unit time to which the current time belongs within the currently measured unit time. The target arrangement position may be, for example, any one of the first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, or tenth Bloom filters. A target Bloom filter located at the target arrangement position is selected from the Bloom filter group included in the third SRAM. For example, the target Bloom filter may be any one of the first, second, or tenth Bloom filters.

[0263]

[0267] S2. Save the write operation identifier of the write address in the target Bloom filter, where the write operation identifier indicates that a write operation has been performed on the target storage unit corresponding to the write address in the storage medium.

[0264]

[0268] Exemplarily, the implementation method of storing the write operation identifier of the write address in the target Bloom filter is: determining a mapping position of the write address in the bit array of the target Bloom filter; and setting the value of the bit at the second mapping position as the write operation identifier of the write address, so as to store the write operation identifier of the write address in the target Bloom filter.

[0265]

[0269] Specifically, using the write address as a key, multiple mapping functions, such as a hash function, are called in the target Bloom filter to determine multiple mapping locations of the write address in the target Bloom filter's bit array. The values ​​of the bits at the multiple mapping locations of the write address in the target Bloom filter's bit array are set to 1, and the corresponding 1 bit in the target Bloom filter's bit array represents a write operation flag for the write address, thereby storing the write operation flag for the write address in the target Bloom filter. It should be understood that if a 0 bit in the target Bloom filter's bit array indicates that the write address has not been recorded.

[0266]

[0270] Further, optionally, before storing the write operation flag of the write address in the target Bloom filter, the method further includes: if the current time is not the first unit time, clearing the target Bloom filter, that is, setting the value of each bit in the bit array of the target Bloom filter to 0. If the current time is the first unit time, directly storing the write operation flag of the write address in the target Bloom filter. This can better ensure the read correctness of the I / O request.

[0267]

[0271] S3. Write the data requested by the write I / O request into the target storage unit.

[0268]

[0272] In practical applications, the data requested by a write VO request can be written directly to the target storage unit, or the ECC module can be called to encode the write data requested by a write I / O request, and the ECC algorithm can be used to determine the redundancy check bits of the write data. The encoded write data and its redundancy check bits can then be written to the target storage unit. There are no restrictions on this.

[0269]

[0273] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs at each unit time. In the subsequent read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory, achieving a high probability of finding the correct read voltage to respond to read I / O requests. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with little impact on overall system latency and bandwidth.

[0270]

[0274] After writing data based on the above-described write process, the phase-change memory read process is described below in conjunction with FIG19 . FIG19 is a flowchart of another phase-change memory data access method provided by an embodiment of the present disclosure. The phase-change memory includes at least a controller and a storage medium, the controller including at least a third SRAM, and the phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays ranging from small to large. The method, executed by the controller, as shown in FIG19 , may include the following steps.

[0271]

[0275] S1. In response to a read I / O request including a read address, searching a Bloom filter group for a write operation identifier of the read address.

[0272]

[0276] In this embodiment, the PCM controller receives a read UO request including a read address from the host and responds. During the response process, the read address in the LA format in the read UO request may be converted into a read address in the PA format, but the present invention is not limited thereto.

[0273]

[0277] During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs during each unit of time. When responding to a read UO request, the PCM controller searches the Bloom filter bank for the write operation flag for the read address. Specifically, using the read address as a key, various mapping functions, such as hash functions, are invoked within any Bloom filter to determine the multiple mapping locations of the read address within the Bloom filter. The values ​​of the bits at the multiple mapping locations of the read address within the Bloom filter's bit array are then queried. If the values ​​of the bits at the multiple mapping locations of the read address within the Bloom filter's bit array are all 1, the write operation flag for the read address has been found. If the values ​​of one or more bits at the multiple mapping locations of the read address within the Bloom filter's bit array are 0, the write operation flag for the read address has not been found.

[0274]

[0278] S2. If no write operation identifier of the read address is found in any of the Bloom filter groups, select the fifth read voltage as the target read voltage.

[0275]

[0279] S3. If a write operation identifier of the read address is found in the Bloom filter group, the fourth read voltage is selected as the target read voltage.

[0276]

[0280] S4. Perform a read operation on the memory cell corresponding to the read address in the storage medium according to the target read voltage.

[0277]

[0281] The specific implementation of the read operation is similar to that of the above embodiment and will not be repeated here.

[0278]

[0282] In some optional embodiments, taking into account the characteristic of a Bloom filter having a false positive rate, in order to improve the reliability of reading correct data, after performing a read operation on a storage cell corresponding to a read address in a storage medium according to a target read voltage, if the target read voltage is the fourth read voltage, error checking and correction ECC processing is performed on the read data; if the ECC processing result indicates that the read data is erroneous, the fifth read voltage is used as the target read voltage, and the step of reading data from the storage cell corresponding to the read address in the storage medium according to the target read voltage is executed again.

[0279]

[0283] It is understandable that the Read Retry mechanism is used to attempt to find the correct read voltage only when the target read voltage is the fourth read voltage and the data read by the fourth read voltage is erroneous. The probability of this situation occurring is very small, which greatly reduces the probability of Read Retry and has almost no impact on the latency and bandwidth of the PCM controller.

[0280]

[0284] The technical solution provided by the embodiments of the present disclosure adds a small amount of SRAM resources to the PCM controller. During the write phase, the Bloom filter provided by the SRAM can record whether a write operation occurs within each unit time. Thus, during the read phase, even under high bandwidth conditions, the Bloom filter provided by the SRAM resources can accurately distinguish the two read voltage levels designed for the phase-change memory, achieving a high probability of finding the correct read voltage to respond to read I / O requests in one go. This significantly reduces the number of read retries and greatly optimizes the QoS of service systems using phase-change memory, with little impact on overall system latency and bandwidth.

[0281]

[0285] FIG20 is a schematic diagram of the structure of another phase-change memory provided by an embodiment of the present disclosure. As shown in FIG20 , the phase-change memory includes a controller 11 and a storage medium 12. The controller includes at least one SRAM. The controller is configured to execute the steps in the phase-change memory data access method.

[0282]

[0286] As further optional, as shown in FIG20 , the phase-change memory may also include other components, such as a communication component 13, a display 14, and a power supply component 15. FIG20 schematically illustrates only some components and does not imply that the phase-change memory includes only the components shown in FIG13 . Furthermore, the components within the dashed box in FIG20 are optional, not mandatory, and may depend on the product form of the phase-change memory.

[0283]

[0287] The embodiment of the present disclosure further provides an in-memory database system, which at least includes: the phase change memory provided in the embodiment of the present disclosure.

[0284]

[0288] The embodiment of the present disclosure further provides a cloud service product, which at least includes: the in-memory database system provided by the embodiment of the present disclosure.

[0285]

[0289] An embodiment of the present disclosure further provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, the processor is enabled to implement the steps in the data access method of a phase change memory.

[0286]

[0290] An embodiment of the present disclosure further provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, the processor is enabled to implement the steps in the phase change memory data access method.

[0287]

[0291] The aforementioned communication component is configured to facilitate wired or wireless communication between the device housing the communication component and other devices. The device housing the communication component can access wireless networks based on communication standards, such as WiFi (Wireless Fidelity), 2G (2nd Generation), 3G (3rd Generation), 4G (4th Generation) / LTE (Long Term Evolution), 5G (5th Generation), and other mobile communication networks, or combinations thereof. In one exemplary embodiment, the communication component receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, the communication component also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on Radio Frequency Identification (RFID) technology, Infrared Data Association (IrDA) technology, Ultra Wide Band (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0288]

[0292] The display includes a screen, which may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from a user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensors can detect not only the boundaries of a touch or slide action, but also the duration and pressure associated with the touch or slide action.

[0289]

[0293] The power supply assembly provides power to various components of the device in which the power supply assembly is located. The power supply assembly may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the device in which the power supply assembly is located.

[0290]

[0294] It should be noted that the execution entity of each step of the method provided in the above embodiments may be the same device, or the method may be executed by different devices. Furthermore, some processes described in the above embodiments and accompanying drawings include multiple operations that appear in a specific order. However, it should be understood that these operations may be executed in a different order or in parallel. Operation sequence numbers, such as 301 and 302, are merely used to distinguish between different operations and do not represent any specific execution order. Furthermore, these processes may include more or fewer operations, and these operations may be executed sequentially or in parallel. It should be noted that terms such as "first" and "second" are used herein to distinguish between different messages, devices, modules, etc., and do not indicate a sequential order or limit "first" and "second" to different types.

[0291]

[0295] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and corresponding operation portals are provided for users to choose to authorize or refuse.

[0292]

[0296] It should also be noted that the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. In the absence of further limitations, the phrase "comprising a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus comprising the elements.

[0293]

[0297] The above are merely examples of the present disclosure and are not intended to limit the present disclosure. Persons skilled in the art will readily appreciate that various modifications and variations are possible with the present disclosure. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure are intended to be encompassed by the claims of the present disclosure.

Claims

Claims 1. A data access method for a phase change memory, wherein: The phase change memory comprises at least: a controller and a storage medium, the controller comprising at least a first static random access memory (SRAM) and a second SRAM, the phase change memory being configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order; the method being executed by the controller, comprising: in response to a write I / O request comprising a write address, selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to a parity type of a coarse-grained unit time currently being counted, wherein the duration of the coarse-grained unit time is related to the minimum read-after-write delay of the third read voltage, and the first bitmap and the second bitmap are used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and selecting a target Bloom filter from a first Bloom filter and a second Bloom filter included in the second SRAM according to a parity type of a fine-grained unit time currently being counted, wherein: The length of the fine-grained unit time is related to the minimum read-after-write delay of the second read voltage. The first Bloom filter and the second Bloom filter are used to select the first read voltage or the second read voltage in a read phase. The second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit. The data requested by the write I / O request is written into the target storage unit.

2. The method according to claim 1, wherein: Selecting a target bitmap from a first bitmap and a second bitmap included in the first SRAM according to a parity type of a coarse-grained unit time currently being measured includes: if the parity type indicates that the coarse-grained unit time currently being measured is an odd-numbered coarse-grained unit time, selecting the first bitmap from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, where the first bitmap is associated with the odd-numbered coarse-grained unit time; and if the parity type indicates that the coarse-grained unit time currently being measured is an even-numbered coarse-grained unit time, selecting the second bitmap from the first bitmap and the second bitmap included in the first SRAM as the target bitmap, where the second bitmap is associated with the even-numbered coarse-grained unit time.

3. The method according to claim 1, wherein: Saving a first write operation identifier of the write address in the target bitmap includes: right-shifting the write address by M bits, where M is a positive integer; determining a first mapping position corresponding to the write address in a bit array of the target bitmap based on the right-shifted write address; and setting a value of a bit at the first mapping position as the first write operation identifier of the write address, so as to save the first write operation identifier of the write address in the target bitmap.

4. The method according to any one of claims 1 to 3, wherein: Before storing the first write operation identifier of the write address in the target bitmap, the method further includes: if the current time is the start time of the coarse-grained unit time of the current timing, clearing the target bitmap.

5. The method according to claim 1, wherein: Selecting a target Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM according to the parity type of the fine-grained unit time of the current timing, including: if the parity type represents that the fine-grained unit time of the current timing is an odd-numbered fine-grained unit time, selecting the first Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM as the target Bloom filter, and the first Bloom filter is associated with the odd-numbered fine-grained unit time; if the parity type represents that the fine-grained unit time of the current timing is an even-numbered fine-grained unit time, selecting the second Bloom filter from the first Bloom filter and the second Bloom filter included in the second SRAM as the target Bloom filter, and the second Bloom filter is associated with the even-numbered fine-grained unit time.

6. The method according to claim 1, wherein: Saving the second write operation identifier of the write address in the target Bloom filter includes: determining a second mapping position of the write address in the bit array of the target Bloom filter; setting the value of the bit at the second mapping position to the second write operation identifier of the write address, so as to save the second write operation identifier of the write address in the target Bloom filter.

7. The method according to any one of claims 1 to 3, 5 and 6, wherein: Before storing the second write operation identifier of the write address in the target Bloom filter, the method further includes: if the current time is the start time of the fine-grained unit time of the current timing, clearing the target Bloom filter.

8. A data access method for a phase change memory, wherein: The phase-change memory comprises at least: a controller and a storage medium, the controller comprising at least a first SRAM and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage arranged in ascending order of minimum read-after-write delay; the method being executed by the controller, comprising: in response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; and if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as a target read voltage; If the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM, select one of the first read voltage and the second read voltage as the target read voltage; and perform a read operation on the storage cell corresponding to the read address in the storage medium according to the target read voltage.

9. The method according to claim 8, wherein Selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter included in the second SRAM includes: searching for the second write operation identifier of the read address in the first Bloom filter and the second Bloom filter; if the second write operation identifier of the read address is not found, selecting the second read voltage as the target read voltage from the first read voltage and the second read voltage; if the second write operation identifier of the read address is found, selecting the first read voltage as the target read voltage from the first read voltage and the second read voltage.

10. The method according to claim 9, wherein: After performing a read operation on the storage unit corresponding to the read address in the storage medium according to the target read voltage, the method further includes: if the target read voltage is the first read voltage, performing error checking and correction (ECC) processing on the read data; if the ECC processing result indicates that the read data is erroneous, sequentially using the second read voltage and the third read voltage as the target read voltages, and performing the step of reading data from the storage unit corresponding to the read address in the storage medium according to the target read voltages until the ECC processing result indicates that the read data is correct.

11. A data access method for a phase change memory, wherein: The phase-change memory comprises at least: a controller and a storage medium, the controller comprising at least a third SRAM, the phase-change memory being configured with a fourth read voltage and a fifth read voltage having minimum read-after-write delays from small to large; the method being executed by the controller, comprising: in response to a write I / O request comprising a write address, selecting a target bitmap from a third bitmap and a fourth bitmap comprised in the third SRAM according to the parity type of a currently timed unit time, wherein the third bitmap is associated with an odd-numbered unit time, the fourth bitmap is associated with an even-numbered unit time, and the duration of the unit time is associated with the minimum read-after-write delay of the fifth read voltage; storing a write operation identifier of the write address in the target bitmap, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested to be written by the write I / O request into the target storage unit.

12. The method according to claim 11, further comprising: In response to a read I / O request including a read address, searching for a write operation identifier of the read address in the third bitmap and the fourth bitmap; If the write operation identifier of the read address is not found in either the third bitmap or the fourth bitmap, selecting the fifth read voltage as the target read voltage; if the write operation identifier of the read address is found in the third bitmap and / or the fourth bitmap, selecting the fourth read voltage as the target read voltage; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

13. A data access method for a phase change memory, wherein: The phase change memory comprises at least: a controller and a storage medium, the controller comprising at least a third SRAM, the phase change memory being configured with a fourth read voltage and a fifth read voltage having minimum read-after-write delays from small to large; the method being executed by the controller, comprising: in response to a write I / O request comprising a write address, selecting a target Bloom filter from a third Bloom filter and a fourth Bloom filter comprised in the third SRAM according to the parity type of a currently counted unit time, wherein the third Bloom filter is associated with an odd-numbered unit time, the fourth Bloom filter is associated with an even-numbered unit time, and the duration of the unit time is associated with the minimum read-after-write delay of the fifth read voltage; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested by the write VO request into the target storage unit.

14. The method according to claim 13, further comprising: In response to a read I / O request including a read address, searching for a write operation identifier of the read address in the third Bloom filter and the fourth Bloom filter; If the write operation identifier of the read address is not found in either the third Bloom filter or the fourth Bloom filter, selecting the fifth read voltage as the target read voltage; if the write operation identifier of the read address is found in the third Bloom filter or the fourth Bloom filter, selecting the fourth read voltage as the target read voltage; A read operation is performed on a storage unit corresponding to the read address in the storage medium according to a target read voltage.

15. The method according to claim 14, wherein: After performing a read operation on the storage unit corresponding to the read address in the storage medium according to the target read voltage, the method further includes: if the target read voltage is the fourth read voltage, performing error checking and correction (ECC) processing on the read data; if the ECC processing result indicates that the read data is erroneous, using the fifth read voltage as the target read voltage and re-performing the target read operation; The step of reading data from the storage unit corresponding to the read address in the storage medium using a voltage.

16. A data access method for a phase change memory, wherein: The phase change memory comprises at least: a controller and a storage medium, the controller comprising at least a first SRAM and a second SRAM, the phase change memory being configured with a first read voltage, a second read voltage, and a third read voltage having a minimum read-after-write delay in ascending order; the method being executed by the controller, comprising: in response to a write I / O request comprising a write address, selecting a target bitmap from a first bitmap and a second bitmap comprised in the first SRAM according to a parity type of a coarse-grained unit time currently being counted, wherein the duration of the coarse-grained unit time is related to the minimum read-after-write delay of the third read voltage, and the first bitmap and the second bitmap being used to select the third read voltage during a read phase; storing a first write operation identifier of the write address in the target bitmap, wherein the first write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and arranging a target position in a fine-grained unit time currently being counted according to a sub-unit time to which the current time belongs. A target Bloom filter located at a target arrangement position is selected from a Bloom filter group included in a second SRAM, wherein the fine-grained unit time includes n sub-unit times divided in sequence, the duration of the fine-grained unit time is related to the minimum read-after-write delay of the second read voltage, the Bloom filter group is used to select the first read voltage or the second read voltage during a read phase, and the Bloom filter group includes n sequentially arranged Bloom filters; a second write operation identifier of the write address is stored in the target Bloom filter, wherein the second write operation identifier indicates that a write operation has been performed on the target storage unit; and data requested by the write VO request is written into the target storage unit.

17. A data access method for a phase change memory, wherein: The phase-change memory includes at least: a controller and a storage medium, the controller including at least a first SRAM and a second SRAM, the phase-change memory being configured with a first read voltage, a second read voltage, and a third read voltage with a minimum read-after-write delay in ascending order; the method being executed by the controller, comprising: in response to a read I / O request including a read address, searching for a first write operation identifier of the read address in a first bitmap and a second bitmap included in the first SRAM; if the first write operation identifier of the read address is not found in either the first bitmap or the second bitmap, selecting the third read voltage as a target read voltage; if the first write operation identifier of the read address is found in the first bitmap and / or the second bitmap, selecting one of the first read voltage and the second read voltage as the target read voltage based on the existence of the second write operation identifier of the read address in a Bloom filter group included in the second SRAM; and performing a read operation on a storage cell corresponding to the read address in the storage medium according to the target read voltage.

18. A data access method for a phase change memory, wherein: The phase-change memory includes at least: a controller and a storage medium, the controller including at least a third SRAM, the phase-change memory being configured with fourth and fifth read voltages with minimum read-after-write delays in ascending order; a method executed by the controller, the method comprising: in response to a write I / O request including a write address, selecting a target Bloom filter located at a target arrangement position in a Bloom filter group included in the third SRAM based on a target arrangement position of a sub-unit time to which a current time belongs within a currently counted unit time, wherein the unit time includes n sub-unit times divided in sequence, the duration of the unit time is related to the minimum read-after-write delay of the fifth read voltage, and the Bloom filter group includes n sequentially arranged Bloom filters; storing a write operation identifier of the write address in the target Bloom filter, wherein the write operation identifier indicates that a write operation has been performed on a target storage unit corresponding to the write address in the storage medium; and writing data requested by the write I / O request into the target storage unit.

19. A data access method for a phase change memory, wherein: The phase-change memory includes at least: a controller and a storage medium, the controller including at least a third SRAM, and the phase-change memory is configured with fourth and fifth read voltages with minimum read-after-write delays in ascending order. The method is executed by the controller, and includes: in response to a read I / O request including a read address, searching a Bloom filter group included in the third SRAM for a write operation identifier of the read address; if the write operation identifier of the read address is not found in the Bloom filter group, selecting the fifth read voltage as a target read voltage; if the write operation identifier of the read address is found in the Bloom filter group, selecting the fourth read voltage as the target read voltage; and performing a read operation on a storage cell corresponding to the read address in the storage medium according to the target read voltage.

20. A phase change memory, comprising at least: A controller and a storage medium, wherein the controller includes at least one SRAM; and the controller is configured to execute the steps of the method according to any one of claims 1 to 19.

21. An in-memory database system, comprising at least: The phase change memory according to claim 20.

22. A cloud service product, comprising at least: The in-memory database system of claim 21.

23. A computer-readable storage medium storing a computer program, wherein: When the computer program is executed by a processor, the processor is enabled to implement the steps of the method according to any one of claims 1 to 19.

Images