Display device

Abstract

[Problem] To provide a display device capable of improving lateral stripes even when efficiency is increased. [Solution] A display device according to a first aspect of the present disclosure comprises: a pixel array unit in which a plurality of pixels including a first sub-pixel, a second sub-pixel, and a third sub-pixel having colors different from each other are arranged in a matrix; a plurality of scanning lines that extend in the row direction of the pixel array unit and supply driving signals for the plurality of first to third sub-pixels; and a plurality of signal lines that extend in the column direction of the pixel array unit and supply pixel signals for the plurality of first to third sub-pixels. At least one sub-pixel among the sub-pixels arranged in each row is connected to the scanning line different from the scanning line to which the other sub-pixels are connected.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] In recent years, there has been a demand for improved efficiency in luminance conversion in displays such as OLEDs (Organic Light Emitting Diodes).

[0003] In displays, high efficiency can be achieved by increasing the efficiency of luminance conversion relative to the current flowing through the pixel. In displays, a voltage Vofs (Vth correction voltage) or Vsig (write voltage) is written sequentially to each pixel in each row in the vertical direction (hereinafter also referred to as the column direction). If Vofs or Vsig deviates from the target value, luminance fluctuations occur, which are perceived as random or fixed horizontal stripes.

[0004] Furthermore, when the efficiency of a display is increased, the brightness fluctuations due to voltage deviations become larger, and horizontal stripes become more visible during sequential writing.

[0005] In view of these problems, the present disclosure provides a display device that can improve horizontal stripes even when the efficiency is increased.

[0006] A display device according to a first aspect of the present disclosure includes a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix, a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels, and a plurality of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to a scanning line different from the scanning lines to which the other subpixels are connected. As a result, for example, the subpixels constituting each pixel are not simultaneously written in the same row, and the writing is shifted in horizontal period units, thereby dispersing variations in the Vth correction voltage Vofs or the write voltage Vsig and making horizontal stripes less visible.

[0007] In this first aspect, the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel, thereby preventing large fluctuations in luminance even when there is a voltage variation, and achieving high efficiency in the display device.

[0008] In this first aspect, the first to third sub-pixels included in the pixel are connected to the scanning line different from the scanning line of the sub-pixels of the same color included in the pixel adjacent in the row direction, thereby preventing large fluctuations in luminance even when there is a voltage variation, and achieving high efficiency in the display device.

[0009] In addition, in this first aspect, the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+5th signal lines (M is an integer of 1 or more), and are arranged in an Nth row, the first subpixel connected to the Mth signal line and the second subpixel connected to the M+2th signal line are connected to the Nth scan line, and are arranged in an Nth row, the third subpixel connected to the M+1th signal line is connected to the N+1th scan line, and are arranged in an Nth row, the first subpixel connected to the M+3rd signal line and the second subpixel connected to the M+5th signal line are connected to the Nth scan line, and are arranged in an Nth row, the third subpixel connected to the M+4th signal line is connected to the Nth scan line. As a result, for example, subpixels constituting each pixel are not simultaneously written in the same row, and the writing is shifted in horizontal period units, thereby dispersing voltage variations in the Vth correction voltage Vofs or the write voltage Vsig and making horizontal stripes less visible.

[0010] In addition, in this first aspect, the first subpixel arranged in the (N+1)th row and connected to the M signal line and the second subpixel connected to the (M+2)th signal line are connected to the (N+1)th scan line, the third subpixel arranged in the (N+1)th row and connected to the (M+1)th signal line is connected to the Nth scan line, the first subpixel arranged in the (N+1)th row and connected to the (M+3)th signal line and the second subpixel connected to the (M+5)th signal line are connected to the Nth scan line, and the third subpixel arranged in the (N+1)th row and connected to the (M+4)th signal line is connected to the Nth scan line. As a result, for example, the subpixels constituting each pixel are not simultaneously written in the same row, and the writing is shifted in horizontal period units, thereby dispersing voltage variations in the Vth correction voltage Vofs or the write voltage Vsig and making horizontal stripes less visible.

[0011] Moreover, in this first aspect, the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+2th signal lines (M is an integer of 1 or more), and are arranged in an Nth row, the first sub-pixel connected to the Mth signal line and the second sub-pixel connected to the M+2th signal line are connected to the Nth scan line, arranged in an Nth row, the third sub-pixel connected to the M+1th signal line is connected to the N+2th scan line, arranged in an N+2th row, the first sub-pixel connected to the Mth signal line and the second sub-pixel connected to the M+2th signal line are connected to the N+2 scan line, and arranged in an N+2th row, the first sub-pixel connected to the Mth signal line and the second sub-pixel connected to the M+2th signal line are connected to the N+2 scan line, and the third sub-pixel connected to the M+1st signal line is connected to the Nth scan line. As a result, for example, the sub-pixels that make up each pixel are not written to simultaneously in the same row, and the writing is shifted in horizontal period units, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0012] In the first aspect, the plurality of signal lines further include (M+3) to (M+5) signal lines (M is an integer of 1 or greater), each of which is arranged in an Nth row, and the first subpixel connected to the (M+3) signal line and the second subpixel connected to the (M+5) signal line are connected to the (N+2)th scan line, the third subpixel arranged in the Nth row and connected to the (M+4) signal line is connected to the Nth scan line, the third subpixel arranged in the N+2th row and the first subpixel connected to the (M+3) signal line and the second subpixel connected to the (M+5) signal line are connected to the Nth scan line, and the third subpixel arranged in the (N+2) row and connected to the (M+4) signal line is connected to the N+2 scan line. As a result, for example, subpixels constituting each pixel are not simultaneously written in the same row, and the writing is shifted in horizontal period units, thereby dispersing voltage variations in the Vth correction voltage Vofs or the write voltage Vsig and making horizontal stripes less visible.

[0013] In this first aspect, each pixel further includes a fourth subpixel, wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, the third subpixel is a blue subpixel, and the fourth subpixel is a white subpixel. Thus, for example, by connecting the green subpixel and the white subpixel, which affect luminance, to different control lines in the display device, horizontal stripes become less visible.

[0014] In addition, in this first aspect, of the first to fourth subpixels, the third and fourth subpixels are connected to the scanning line different from that of the first and second subpixels, so that, for example, the display device can make horizontal stripes less visible by connecting the green subpixel and the white subpixel, which affect luminance, to different control lines.

[0015] Moreover, in this first aspect, each pixel further includes a fourth subpixel, the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+3th signal lines (M is an integer of 1 or more), and are arranged in an Nth row, the fourth subpixel connected to the Mth signal line and the third subpixel connected to the M+2th signal line are connected to the Nth scan line, arranged in an Nth row, the first subpixel connected to the M+1th signal line and the second subpixel connected to the M+3rd signal line are connected to the N+2th scan line, arranged in an N+2th row, the fourth subpixel connected to the Mth signal line and the third subpixel connected to the M+2nd signal line are connected to the N+2nd scan line, and arranged in an N+2th row, the first subpixel connected to the M+1st signal line and the second subpixel connected to the M+3rd signal line are connected to the Nth scan line. As a result, for example, by connecting the green subpixel and the white subpixel, which affect the luminance, to different control lines in the display device, horizontal stripes become less visible.

[0016] In the first aspect, the plurality of signal lines further include (M+4) to (M+7) signal lines (N is an integer of 1 or greater), arranged in an Nth row, wherein the fourth subpixel connected to the (M+4) signal line and the third subpixel connected to the (M+6) signal line are connected to the (N+2) scanning line, the first subpixel connected to the (M+5) signal line and the second subpixel connected to the (M+7) signal line are connected to the (N+2) scanning line, the fourth subpixel connected to the (M+4) signal line and the third subpixel connected to the (M+6) signal line are connected to the (N+2) scanning line, and the first subpixel connected to the (M+5) signal line and the second subpixel connected to the (M+7) signal line are connected to the (N+2) scanning line. This makes it possible to make horizontal stripes less visible in the display device, for example, by connecting green subpixels and white subpixels, which affect luminance, to different control lines.

[0017] A display device according to a second aspect of the present disclosure includes a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix, a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the first to third subpixels, a first group of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a predetermined column, a second group of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a column other than the predetermined column, and a plurality of switches for switching electrical connections between the first group of signal lines and the second group of signal lines, wherein at least one subpixel arranged in each row is connected to a scanning line different from the scanning lines to which the other subpixels are connected. As a result, for example, by connecting the control lines as described above for the subpixels constituting each pixel, the display device can perform horizontal doubling processing and reduce power consumption.

[0018] In the second aspect, the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel. This prevents large luminance fluctuations even when there is voltage variation, and enables the display device to achieve high efficiency.

[0019] In addition, in this second aspect, the first group of signal lines includes M to M+2 signal lines and M+6 to M+8 signal lines (N is an integer of 1 or more), the second group of signal lines includes M+3 to M+5 signal lines and M+9 to M+11 signal lines (M is an integer of 1 or more), and the first subpixel is connected to the M signal line and the M+3 signal line and the M+6 signal line and the M+9 signal line, respectively, when the switch is conductive; the third subpixel is connected to the M+1 signal line and the M+4 signal line and the M+7 signal line and the M+10 signal line, respectively, when the switch is conductive; and the second subpixel is connected to the M+2 signal line and the M+5 signal line and the M+8 signal line and the M+11 signal line, respectively, when the switch is conductive. This allows the display device to perform horizontal doubler processing by connecting the control lines as described above for the sub-pixels that make up each pixel, thereby reducing power consumption.

[0020] Moreover, in this second aspect, the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), and are arranged in an Nth row, each of the first subpixels connected to the Mth signal line and the M+3rd signal line is connected to the Nth scan line and arranged in an Nth row, each of the third subpixels connected to the Mth signal line and the M+4th signal line is connected to the Nth scan line and arranged in an Nth row, each of the second subpixels connected to the Mth signal line and the M+5th signal line is connected to the Nth scan line and arranged in an Nth row, each of the first subpixels connected to the Mth signal line and the Mth signal line is connected to the Nth scan line and arranged in an Nth row, each of the first subpixels connected to the Mth signal line and the Mth signal line is connected to the Nth scan line and arranged in an Nth row, each of the third subpixels connected to the Mth signal line and the Mth signal line is connected to the Nth scan line and arranged in an Nth row, each of the third subpixels connected to the Mth signal line and the Mth signal line is connected to the Nth scan line and arranged in an Nth row, As a result, for example, horizontal doubling processing is performed on sub-pixels belonging to the same row, and the display device can output a display image with less jerky images.

[0021] Moreover, in this second aspect, the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), and are arranged in an Nth row, the first sub-pixels connected to the Mth signal line and the M+3rd signal line are connected to the Nth scan line and are arranged in an Nth row, the third sub-pixels connected to the Mth signal line and the M+4th signal line are connected to the Nth scan line and are arranged in an Nth row, the second sub-pixels connected to the Mth signal line and the M+5th signal line are connected to the Nth scan line and are arranged in an Nth row, the first sub-pixels connected to the Mth signal line and the Mth signal line are connected to the Nth scan line and are arranged in an Nth row, the first sub-pixels connected to the Mth signal line and the Mth signal line are connected to the Nth scan line and are arranged in an Nth row, the third sub-pixels connected to the Mth signal line and the Mth signal line are connected to the Nth scan line and are arranged in an Nth row, the third sub-pixels connected to the Mth signal line and the Mth signal line are connected to the Nth scan line and are arranged in an Nth row, As a result, for example, horizontal doubling processing is performed on sub-pixels belonging to the same row, and the display device can output a display image with less jerky images.

[0022] A display device according to a third aspect of the present disclosure includes a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix, a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels, and a plurality of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to a scanning line different from the scanning lines to which the other subpixels are connected, and a plurality of pairs of scanning lines, each pair of two of the plurality of scanning lines, supply the drive signals in each horizontal period. This enables, for example, the display device to perform vertical doubling processing and reduce power consumption by simultaneously writing subpixels of the same color to subpixels connected to control lines in rows (N+1) and (N+2), etc.

[0023] In addition, in this third aspect, the plurality of scanning lines include Nth to N+4th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+2th signal lines (M is an integer of 1 or more), wherein the pixel signal is supplied to the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1th scanning line, and the first sub-pixel arranged in the N+2th row and connected to the Mth signal line, during a first horizontal period; the second sub-pixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1st scanning line, and the second sub-pixel arranged in the N+2th row and connected to the M+2nd signal line and the N+2nd scanning line, during the first horizontal period; the third sub-pixel arranged in the Nth row and connected to the M+1st signal line and the N+1st scanning line, and the third sub-pixel arranged in the Nth row and connected to the M+1st signal line and the N+1st scanning line, and the third sub-pixel arranged in the N+3th row and connected to the M+1st signal line and the N+2nd scanning line, The pixel signal is supplied to the third sub-pixel connected to the M signal line and the N+3 scanning line during the first horizontal period, the first sub-pixel arranged in the N+3 row and connected to the M signal line and the N+3 scanning line, and the first sub-pixel arranged in the N+4 row and connected to the M signal line and the N+4 scanning line during a second horizontal period, the second sub-pixel arranged in the N+3 row and connected to the M+2 signal line and the N+3 scanning line, and the second sub-pixel arranged in the N+4 row and connected to the M+2 signal line and the N+4 scanning line during the second horizontal period, and the third sub-pixel arranged in the N+2 row and connected to the M+1 signal line and the N+3 scanning line and the third sub-pixel arranged in the N+5 row and connected to the M+1 signal line and the N+4 scanning line during the second horizontal period. This allows the display device to perform vertical doubling processing and reduce power consumption by simultaneously writing sub-pixels of the same color to sub-pixels connected to control lines in rows N+1 and N+2, for example.

[0024] In addition, in this third aspect, the plurality of scanning lines include Nth to N+3th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+5th signal lines (N is an integer of 1 or more), the pixel signals of a first field are supplied to the first sub-pixel arranged in the Nth row and connected to the Mth signal line and the Nth scanning line, and the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1th scanning line, during a first horizontal period of a first vertical period, and the plurality of scanning lines include Nth to N+5th signal lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+5th signal lines (N is an integer of 1 or more), the pixel signals of a first field are supplied to the first sub-pixel arranged in the Nth row and connected to the Mth signal line and the Nth scanning line, during a first horizontal period of a first vertical period, and the plurality of signal lines include Mth to M+5th signal lines (N is an integer of 1 or more), ... The pixel signal of the first field is supplied to the third subpixel connected to the third subpixel arranged in the N+1th row and connected to the M+1 signal line and the N+3 scanning line, during the second horizontal period of the first vertical period, and the pixel signal of the first field is supplied to the second subpixel arranged in the Nth row and connected to the M+2 signal line and the N scanning line, and the second subpixel arranged in the N+1th row and connected to the M+2 signal line and the N+1 scanning line, during the first horizontal period of the first vertical period. As a result, for example, the same pixel signal is supplied to subpixels adjacent to each other in the column direction, thereby reducing jerky images when displayed.

[0025] In addition, in this third aspect, the pixel signal of the second field is supplied to the first subpixel arranged in the Nth row and connected to the M signal line and the N scan line, and the first subpixel arranged in the N+1th row and connected to the M signal line and the N+1th scan line, during a first horizontal period of a second vertical period, the pixel signal of the second field is supplied to the third subpixel arranged in the Nth row and connected to the M+1th signal line and the N+2th scan line, and the third subpixel arranged in the N+1th row and connected to the M+1st signal line and the N+3th scan line, during a second horizontal period of the second vertical period, and the pixel signal of the second field is supplied to the second subpixel arranged in the Nth row and connected to the M+2nd signal line and the N scan line, and the second subpixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1th scan line, during the first horizontal period of the second vertical period. As a result, for example, the same pixel signal is supplied to subpixels adjacent to each other in the column direction, thereby reducing jerky images displayed.

[0026] 1 is a configuration example of a display system 2 according to the first embodiment; FIG. 2 is a configuration example of a display device 1 according to the first embodiment; FIG. 3 is a configuration example of a pixel array unit 11 according to the first embodiment; FIG. 4 is a configuration example of a pixel array unit 11 according to a comparative example; FIG. 5 is a diagram illustrating the relationship between the distribution of variations in the write voltage Vsig and the visibility of horizontal stripes; FIG. 6 is a configuration example 1 of sub-pixels according to the first embodiment; FIG. 7 is a configuration example 2 of sub-pixels according to the first embodiment; FIG. 8 is a configuration example 9 of sub-pixels according to the first embodiment; FIG. 9 is a timing chart illustrating the emission timing of each row of sub-pixels for one frame according to the first embodiment; FIG. 10 is a timing chart example 1 of sub-pixel emission according to the first embodiment; FIG. 11 is a timing chart example 2 of sub-pixel emission according to the first embodiment; FIG. 12 is a timing chart example 3 of sub-pixel emission according to the first embodiment; 10 is a timing chart showing example 4 when sub-pixels emit light in the first embodiment. FIG. 11 is a configuration diagram of a pixel array unit 11 in the second embodiment. FIG. 12 is another configuration diagram of a pixel array unit 11 in the second embodiment. FIG. 13 is a timing chart showing example 1 when sub-pixels emit light in the second embodiment. FIG. 14 is a timing chart showing example 2 when sub-pixels emit light in the second embodiment. FIG. 15 is a timing chart showing example 3 when sub-pixels emit light in the second embodiment. FIG. 16 is a timing chart showing example 4 when sub-pixels emit light in the second embodiment. FIG. 17 is a configuration diagram of a display device 1 in a third embodiment. FIG. 18 is a connection relationship of a display device 1 in a third embodiment. FIG. 19 is a configuration diagram of a pixel array unit 11 in a third embodiment. FIG. 19 is another configuration diagram of a pixel array unit 11 in a third embodiment. FIG. 19 is yet another configuration diagram of a pixel array unit 11 in a third embodiment. FIG. 19 is a diagram illustrating a light emission method of a pixel array unit 11 in a fourth embodiment. FIG. 19 is a diagram illustrating a light emission method of a pixel array unit 11 in a normal state in a fifth embodiment.10 is a diagram for explaining a light emission method during vertical doubler processing of the pixel array unit 11 in the fifth embodiment. FIG. 11 is a diagram illustrating the appearance of a head-mounted display, which is an example of an electronic device to which the display device according to the first to fifth embodiments is applied. FIG. 12 is a diagram illustrating the appearance of a head-mounted display, which is another example of an electronic device to which the display device according to the first to fifth embodiments is applied. FIG. 13 is a diagram illustrating the appearance of a digital camera, which is an example of an electronic device to which the display device according to the first to fifth embodiments is applied. FIG. 14 is a diagram illustrating the appearance of a television device, which is an example of an electronic device to which the display device according to the first to fifth embodiments is applied. FIG. 15 is a diagram illustrating the appearance of a smartphone, which is an example of an electronic device to which the display device according to the first to fifth embodiments is applied. FIG. 16 is a diagram illustrating an example configuration of a vehicle to which the display device according to the first to fifth embodiments is applied. FIG. 17 is a diagram illustrating the appearance of a liquid crystal projector, which is an example of an electronic device to which the display device according to the first to fifth embodiments is applied.

[0027] (First embodiment)

[0028] Hereinafter, an embodiment of a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0029] FIG. 1 shows an example of the configuration of a display system 2 according to the first embodiment.

[0030] 1 shows the configuration of a micro OLED (Organic Light Emitting Diode) system. Note that the display device 1 according to this embodiment can also be applied to a display system 2 including a large-screen display device 1 such as a TV or PC monitor.

[0031] 1 includes a display device 1, a display controller 3, a timing controller 4, and a data input / output I / F unit 5. Although the display controller 3 and the like are separate from the display device 1 in FIG. 1, the display controller and the like may be integrated into the display device 1.

[0032] The display device 1 includes a pixel array section 11, a V-DRV section 12, an H-DRV section 13, and a signal processing section .

[0033] The pixel array unit 11 has a plurality of pixels 15 arranged in the horizontal and vertical directions. Each pixel 15 includes a sub-pixel, and the sub-pixel has a light-emitting portion such as an organic EL element, a plurality of transistors that control the light-emitting portion, and a plurality of capacitors. The internal configuration of the pixel 15 and the sub-pixels will be described later. Hereinafter, a group of pixels arranged in the horizontal direction will be referred to as a "row," and a group of pixels arranged perpendicular to the row will be referred to as a "column."

[0034] The signal processing unit 14 processes the video signal to be displayed on the pixel array unit 11. The specific content of the signal processing is not important, but it may be, for example, gamma correction. The video signal processed by the signal processing unit 14 is sent to the H-DRV unit 13.

[0035] 2, which will be described later, the V-DRV unit 12 includes a write scanning unit 16 and a drive scanning unit 17. The write scanning unit 16 and the drive scanning unit 17 will be described with reference to FIG.

[0036] 2, the H-DRV unit 13 has a signal output unit 18. The signal output unit 18 will be described with reference to FIG.

[0037] The write voltage Vsig or the Vth correction voltage Vofs, which is alternatively output from the signal output unit 18, is supplied to each pixel array unit 11 via a signal line and is set to the sub-pixels that make up each pixel 15 on a row-by-row basis selected by scanning by the write scanning unit 16.

[0038] The display controller 3 has an HLOGIC unit 21 and a VLOGIC unit 22 , and performs display control for the pixel array unit 11 .

[0039] The HLOGIC unit 21 supplies a video signal to the H-DRV unit 13. The VLOGIC unit 22 supplies a signal that defines the timing of the scanning lines and control lines to the V-DRV unit 12.

[0040] The timing controller 4 has a clock generator 23, a timing generator 24, and an image processing unit 25. The clock generator 23 generates a vertical synchronization clock and a horizontal synchronization clock for the display device 1 and supplies them to the display controller 3. The timing generator 24 generates a signal that defines the operation timing of the display controller 3 and supplies it to the display controller 3. The image processing unit 25 performs various image processing on the video signal input to the data input / output I / F unit 5. The video signal after image processing is supplied to the HLOGIC unit 21 in the display controller 3.

[0041] The data input / output I / F unit 5 has an image I / F unit 31, a data S / P unit 32, a clock control unit 33, and an H / V synchronization unit 34. The image I / F unit 31 receives a video signal from an external device. The video signal is serial digital data. The data S / P unit 32 converts the video signal into parallel data and then sends it to the image processing unit 25 in the timing controller 4. The clock control unit 33 generates a clock that matches the display frequency of the display device 1. The H / V synchronization unit 34 generates signals that define the horizontal synchronization timing and vertical synchronization timing of the display device 1 and sends them to the timing generator 24.

[0042] FIG. 2 shows an example of the configuration of the display device 1 according to the first embodiment.

[0043] As shown in FIG. 2, the display device 1 includes a pixel array section 11, a write scanning section 16, a drive scanning section 17, and a signal output section .

[0044] The pixel array unit 11 has a configuration in which sub-pixels, each of which is provided with an organic EL element or other self-luminous element, are arranged in a matrix. In the pixel array unit 11, scanning lines extending in the row direction are provided for each line of the sub-pixels arranged in a matrix, and signal lines extending in the column direction are provided for each column so as to be perpendicular to the scanning lines.

[0045] The signal output unit 18 sequentially transfers predetermined sampling pulses and sequentially latches image data using these sampling pulses, thereby distributing the image data to the signal lines of each column. The signal output unit 18 also performs analog-to-digital conversion on the image data distributed to each signal line, thereby generating pixel signals for each sub-pixel connected to each signal line. The signal output unit 18 outputs these pixel signals to the corresponding signal lines and supplies them to each sub-pixel.

[0046] The write scanning unit 16 generates a drive signal for each pixel and outputs it to the scanning line. As a result, the display device 1 sequentially drives each sub-pixel arranged in the pixel array unit 11 using the write scanning unit 16, causes each sub-pixel to emit light at the signal level of each signal line set by the signal output unit 18, and displays a desired image on the pixel array unit 11.

[0047] The drive scanning unit 17 supplies a light emission control signal to a control line DSL (to be described later) in synchronization with the line sequential scanning by the write scanning unit 16, and controls the light emitting units to emit or not emit light.

[0048] FIG. 3 is a diagram illustrating an example of the configuration of the pixel array unit 11 according to the first embodiment.

[0049] In this embodiment, a set of pixels 15, which is a unit for forming a color image, is composed of sub-pixels of multiple colors, and these sub-pixels are arranged in a matrix in the pixel array section 11. For ease of explanation, below, scanning lines will also be referred to as control lines WSL, and signal lines will also be referred to as signal lines SGL.

[0050] Furthermore, the control line in the Nth row (N is an integer greater than or equal to 1) described below is an example of the Nth scanning line, and the signal line in the Mth column (M is an integer greater than or equal to 1) is an example of the Mth signal line.

[0051] In this example, each pixel is configured to include subpixels of the three primary colors of red, green, and blue, but the types of subpixels are not limited to these and may include, for example, a white subpixel. The red subpixel is an example of a first subpixel, the green subpixel is an example of a second subpixel, and the blue subpixel is an example of a third subpixel.

[0052] Furthermore, without being limited to the examples described in the following embodiments, different colors may be used for the first to third sub-pixels. For example, the sub-pixels may be arranged in a stripe pattern or a pentile pattern.

[0053] In this example, the blue subpixel of one set of pixels 15 is connected to a different control line WSL from the red and green subpixels. The method of connecting the control lines WSL is not limited to this; it is sufficient that at least one subpixel of one set of pixels 15 is connected to a control line WSL different from the control line WSL to which the other subpixels are connected. For example, only the green subpixel, which has a large influence on luminance, may be connected to a different control line WSL. Although not shown in this figure, each subpixel is connected to the write scanning unit 16 via the control line WSL and the control line AZSL.

[0054] As shown in the figure, the sub-pixels constituting a given pixel 15 are connected to a different control line WSL than the sub-pixels of the same color constituting the adjacent pixel 15 in the row direction.

[0055] For example, for a set of pixels 15 arranged in the Nth row (the pixel 15 on the left side in the figure will be taken as an example), the red subpixel 42 connected to the signal line SGL in the Mth column and the green subpixel 44 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43′ connected to the signal line SGL in the (M+1)th column is connected to the control line WSL in the (N+1)th row. Also, for a set of pixels 15 shown on the right side of the Nth row, the red subpixel 42′ connected to the signal line SGL in the (M+3)th column and the green subpixel 44′ connected to the signal line SGL in the (M+5)th row are connected to the control line WSL in the (N+1)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+4)th row is connected to the control line WSL in the Nth row.

[0056] For the pixel 15 shown on the left side of the N+1th row, the red subpixel 42′ connected to the signal line SGL in the Mth column and the green subpixel 44′ connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+1)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+1)th column is connected to the control line WSL in the Nth row. For the pixel 15 shown on the right side of the N+1th row, the red subpixel 42 connected to the signal line SGL in the (M+3)th column and the green subpixel 44 connected to the signal line SGL in the (M+5)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43′ connected to the signal line SGL in the (M+4)th column is connected to the control line WSL in the (N+1)th row.

[0057] Thus, in this embodiment, when the red subpixel 42 and the green subpixel 44 are connected to the control line WSL in the Nth row, the blue subpixel 43′ is connected to the control line WSL in the N+1th row, which is different from the control line WSL in the red subpixel 42 and the green subpixel 44. Furthermore, when the red subpixel 42 and the green subpixel 44 are connected to the control line WSL in the N+1th row, the blue subpixel 43′ is connected to the control line WSL in the Nth row, which is different from the control line WSL in the red subpixel 42 and the green subpixel 44.

[0058] The connection configuration of the Nth to N+1th rows is a repetition of the connection configuration shown by the two pixels 15 (six sub-pixels) on the left and right sides of each row. This connection configuration may also be provided in a part of the pixel array unit 11.

[0059] For a set of pixels 15 arranged in the Nth row (taking again the pixel 15 consisting of the red subpixel 42, blue subpixel 43′, and green subpixel 44 shown on the left), if the timing at which a pixel signal is supplied to the red subpixel 42 and the green subpixel 44 from the signal output unit 18 via the signal line SGL is H, then the pixel signal is supplied to the blue subpixel 43′ at timing H+1, which is delayed by one horizontal period.

[0060] For a set of pixels 15 arranged in the N+1th row (taking again the pixel 15 composed of the red subpixel 42′, blue subpixel 43, and green subpixel 44′ shown on the left), if the timing at which a pixel signal is supplied to the red subpixel 42′ and the green subpixel 44′ from the signal output unit 18 via the signal line SGL is H+1, then the pixel signal is supplied to the blue subpixel 43 at the timing of H, which is one horizontal period earlier.

[0061] FIG. 4 is an example of a configuration diagram of the pixel array unit 11 in the comparative example.

[0062] In the comparative example, a set of pixels 15, which is a unit for forming a color image, is made up of sub-pixels of a plurality of colors, and furthermore, these sub-pixels are arranged in a matrix in the pixel array section 11.

[0063] In the comparative example, the sub-pixels of the three primary colors of red, green and blue that make up one pixel are connected to the same control line WSL.

[0064] For example, for the pixel 15 shown on the left side of the Nth row, the red subpixel 42, the blue subpixel 43′, and the green subpixel 44 are connected to the control line WSL of the Nth row. For the pixel 15 shown on the right side of the Nth row, the red subpixel 42′, the blue subpixel 43, and the green subpixel 44′ are connected to the control line WSL of the Nth row.

[0065] For the pixel 15 shown on the left side of the N+1th row, the red subpixel 42′, the blue subpixel 43, and the green subpixel 44′ are connected to the control line WSL of the N+1th row. For the pixel 15 shown on the right side of the N+1th row, the red subpixel 42, the blue subpixel 43′, and the green subpixel 44 are connected to the control line WSL of the N+1th row.

[0066] FIG. 5 is a diagram showing an example of the relationship between the distribution of variations in the write voltage Vsig and the visibility of horizontal stripes.

[0067] In Figure 5, the horizontal axis represents the value of the write voltage Vsig supplied to the subpixel. Moving to the right from the center on the horizontal axis indicates that the write voltage Vsig is greater than the target value, and moving to the left from the center indicates that the write voltage Vsig is smaller than the target value. The vertical axis represents frequency. In other words, the graph in Figure 5 shows the distribution of variations in the write voltage Vsig, and as shown in Figure 5A, the write voltage Vsig varies slightly above and below the target value due to the influence of power supply noise in the display device 1, etc.

[0068] 5 indicates the voltage range in which horizontal stripes are visible. Horizontal stripes may be visible when the value of the write voltage Vsig exceeds this dashed line. As shown in FIG. 5A, when the efficiency of the display device 1 is increased, the dashed line is located further inward, making horizontal stripes more visible.

[0069] 5B , for a set of pixels 15 in this embodiment, if the value of the write voltage Vsig at the timing of a certain horizontal period H is the value indicated by a and the value of the write voltage Vsig at the timing of a certain horizontal period H+1 is the value indicated by b, the value at b exceeds the dashed line portion, but the deviation in the write voltage Vsig for the pixels 15 as a whole is dispersed, making horizontal stripes less visible. In this case, although the deviation in the voltage Vsig does not actually equal the value indicated by a×b, a person will perceive it to be about this value, and horizontal stripes will be less visible.

[0070] On the other hand, for a set of pixels 15 in the comparative example, if the value of the write voltage Vsig at the timing of a certain horizontal period H+1 is the value indicated by b, the deviation of the write voltage Vsig is not dispersed and horizontal stripes are visible.

[0071] FIG. 6 shows a first example of the configuration of a sub-pixel according to the first embodiment.

[0072] The display device 1 may employ, for example, the subpixels shown in FIG. 6 . In FIG. 6 , the red subpixel 42 is used as an example of the subpixel, but the other subpixels may have a similar configuration. In FIG. 6 , the subpixel includes a capacitor C01, transistors MN02 and MN03, and a light-emitting element EL. The transistors MN02 and MN03 are N-type MOSFETs. The gate of the transistor MN02 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of the transistor MN03 and the capacitor C01. One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light-emitting element EL. The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of the capacitor C01 and the anode of the light-emitting element EL. The light-emitting element EL is, for example, an organic EL element, and has an anode connected to the source of the transistor MN03 and the other end of the capacitor C01, and a cathode connected to the power supply line Vcath. The voltage of the power supply line VCCP is switched between a first voltage and a second voltage lower than the first voltage as appropriate.

[0073] With this configuration, in the subpixel, when the transistor MN02 is turned on, the voltage across the capacitor C01 is set based on the pixel signal supplied from the signal line SGL. During a period when the voltage of the power supply line VCCP is at a first voltage, the transistor MN03 passes a current corresponding to the voltage across the capacitor C01 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor MN03. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. During a period when the voltage of the power supply line VCCP is at a second voltage, the light-emitting element EL is extinguished.

[0074] FIG. 7 shows a second example of the configuration of the sub-pixel in the first embodiment.

[0075] The display device 1 can employ the subpixels shown in FIG. 7 in addition to the subpixels described in FIG. 7 . In FIG. 7 , the subpixel includes capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element EL. The transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the gate of transistor MP14 and capacitor C12. One end of capacitor C11 is connected to a power supply line VCCP, and the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14. One end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14. The gate of transistor MP13 is connected to the control line DSL, the source is connected to the power supply line VCCP, and the drain is connected to the source of transistor MP14, the other end of capacitor C11, and one end of capacitor C12. The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of the light-emitting element EL and the source of transistor MP15. The gate of transistor MP15 is connected to the control line AZSL, the source is connected to the drain of transistor MP14 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0076] With this configuration, in the subpixel, when transistor MP12 is turned on, the voltage across capacitor C12 is set based on the pixel signal supplied from signal line SGL. Transistor MP13 is turned on and off based on the signal on control line DSL. While transistor MP13 is on, transistor MP14 passes a current corresponding to the voltage across capacitor C12 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP14. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistor MP15 is turned on and off based on the signal on control line AZSL. While transistor MP15 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0077] FIG. 8 shows a third example of the configuration of the sub-pixel in the first embodiment.

[0078] The display device 1 can employ the subpixels shown in FIG. 8 in addition to the subpixels described with reference to FIG. 6. This subpixel includes a capacitor C21, transistors MN22 to MN25, and a light-emitting element EL. Transistors MN22 to MN25 are N-type MOSFETs. The gate of transistor MN22 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor MN24 and capacitor C21. One end of capacitor C21 is connected to the source of transistor MN22 and the gate of transistor MN24, and the other end is connected to the source of transistor MN24, the drain of transistor MN25, and the anode of the light-emitting element EL. The gate of transistor MN23 is connected to a control line DSL, the drain is connected to a power supply line VCCP, and the source is connected to the drain of transistor MN24. The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element EL. The gate of transistor MN25 is connected to control line AZSL, the drain is connected to the source of transistor MN24, the other end of capacitor C21, and the anode of light-emitting element EL, and the source is connected to power supply line VSS.

[0079] With this configuration, in the subpixel, when transistor MN22 is turned on, the voltage across capacitor C21 is set based on the pixel signal supplied from signal line SGL. Transistor MN23 is turned on and off based on the signal on control line DSL. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MN24. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistor MN25 is turned on and off based on the signal on control line AZSL. While transistor MN25 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0080] FIG. 9 shows a fourth example of the configuration of the sub-pixel in the first embodiment.

[0081] The display device 1 can employ the subpixel shown in FIG. 9 in addition to the subpixel described with reference to FIG. 6 . This subpixel includes a capacitor C31, transistors MP32 to MP36, and a light-emitting element EL. The transistors MP32 to MP36 are P-type MOSFETs. The gate of transistor MP32 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31. One end of capacitor C31 is connected to a power supply line VCCP, and the other end is connected to the drain of transistor MP32, the gate of transistor MP33, and the drain of transistor MP34. The gate of transistor MP34 is connected to a control line AZSL1, the source is connected to the drain of transistor MP33 and the source of transistor MP35, and the drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31. The gate of transistor MP35 is connected to the control line DSL, the source is connected to the drain of transistor MP33 and the source of transistor MP34, the drain is connected to the source of transistor MP36 and the anode of the light-emitting element EL, the gate of transistor MP36 is connected to the control line AZSL2, the source is connected to the drain of transistor MP35 and the anode of the light-emitting element EL, and the drain is connected to the power supply line VSS.

[0082] With this configuration, in the subpixel, when transistor MP32 is turned on, the voltage across capacitor C31 is set based on the pixel signal supplied from signal line SGL. Transistor MP35 is turned on and off based on the signal on control line DSL. During the period when transistor MP35 is on, transistor MP33 passes a current corresponding to the voltage across capacitor C31 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP33. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistor MP34 is turned on and off based on the signal on control line AZSL1. During the period when transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on the signal on control line AZSL2. During the period when transistor MP36 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0083] FIG. 10 shows a fifth example of pixel configuration in the first embodiment.

[0084] The display device 1 can employ the subpixels shown in Fig. 10 in addition to the subpixels described in Fig. 6. One end of a capacitor C48 is connected to a signal line SGL1, and the other end is connected to a power supply line VSS. One end of a capacitor C49 is connected to a signal line SGL1, and the other end is connected to a signal line SGL2. A transistor MP49 is a P-type MOSFET, and has a gate connected to a control line WSL2, a source connected to the signal line SGL1, and a drain connected to the signal line SGL2.

[0085] The subpixel includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element EL. Transistors MP42 to MP46 are P-type MOSFETs. The gate of transistor MP42 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor MP43 and capacitor C41. One end of capacitor C41 is connected to the power supply line VCCP, and the other end is connected to the drain of transistor MP42 and the gate of transistor MP43. The gate of transistor MP43 is connected to the drain of transistor MP42 and the other end of capacitor C41, its source is connected to the power supply line VCCP, and its drain is connected to the sources of transistors MP44 and MP45. The gate of transistor MP44 is connected to a control line AZSL1, its source is connected to the drain of transistor MP43 and the source of transistor MP45, and its drain is connected to signal line SGL2. The gate of transistor MP45 is connected to control line DSL, the source is connected to the drain of transistor MP43 and the source of transistor MP44, the drain is connected to the source of transistor MP46 and the anode of light-emitting element EL, the gate of transistor MP46 is connected to control line AZSL2, the source is connected to the drain of transistor MP45 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0086] With this configuration, in the subpixel, when transistor MP42 is turned on, the voltage across capacitor C41 is set based on the pixel signal supplied from signal line SGL1 via capacitor C49. Transistor MP45 is turned on and off based on the signal on control line DSL. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP43. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistor MP44 is turned on and off based on the signal on control line AZSL1. While transistor MP44 is on, the drain of transistor MP43 and signal line SGL2 are connected to each other. Transistor MP46 is turned on and off based on the signal on control line AZSL2. While transistor MP46 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0087] FIG. 11 shows a sixth example of pixel configuration in the first embodiment.

[0088] The display device 1 can employ the sub-pixels shown in Fig. 11 in addition to the sub-pixels described in Fig. 6. The sub-pixels are arranged in a matrix in a display region 100, and the display region 100 is provided between a first control unit 40 and a second control unit 70.

[0089] The first control unit 40 includes transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61. Transistors MP56 and MP57 are P-type MOSFETs. A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the signal line 14a. The input terminal of the transmission gate TG46 is connected to the signal line 14b, and the output terminal of the transmission gate TG46 is connected to the power supply line Vorst. One end of the capacitor C61 is connected to the signal line 14a, and the other end is connected to the power supply line VSS1. The gate of the transistor MP56 is connected to the signal line INIL, the source is connected to the power supply line Vini, and the drain is connected to the signal line 14b. The gate of the transistor MP57 is connected to the signal line ELL, the source is connected to the power supply line Vel, and the drain is connected to the signal line 14b.

[0090] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82. The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the signal line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82. The gate of the transistor MP73 is connected to the signal line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one end of the capacitor C82. One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the signal line 14b.

[0091] The subpixel includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element EL. Transistors MP121 to MP125 are P-type MOSFETs. The gate of transistor MP122 is connected to a control line WSL, its source is connected to a signal line 14b, and its drain is connected to the gate of transistor MP121 and capacitor C132. One end of capacitor C132 is connected to a power supply line Vel, and the other end is connected to the drain of transistor MP122 and the gate of transistor MP121. The gate of transistor MP121 is connected to the drain of transistor MP122 and the other end of capacitor C132, its source is connected to the power supply line Vel, and its drain is connected to the sources of transistors MP123 and MP124. The gate of transistor MP123 is connected to a control line AZSL, its source is connected to the drain of transistor MP121 and the source of transistor MP124, and its drain is connected to signal line 14b. The gate of transistor MP124 is connected to the control line DSL, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of the light-emitting element 130. The gate of transistor MP125 is connected to the control line AZSL, the source is connected to the power supply line Vorst, and the drain is connected to the drain of transistor MP124 and the anode of the light-emitting element 130.

[0092] With this configuration, in the subpixel, when transistor MP122 is turned on, the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, signal line 14a, transmission gate TG72, capacitor C82, and signal line 14b. Transistor MP124 is turned on and off based on the signal on control line DSL. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP121. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistors MP123 and MP125 are turned on and off based on the signal on control line AZSL. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to signal line 14b. During the period when transistor MP125 is in the ON state, the voltage of the anode of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor MP56 is turned on and off based on the signal on signal line INIL, transistor MP57 is turned on and off based on the signal on signal line ELL, and transistor MP73 is turned on and off based on the signal on signal line REFL. When transistor MP56 is in the ON state, signal line 14b is set to the voltage of power supply line Vini, and when transistor MP57 is in the ON state, signal line 14b is set to the voltage of power supply line Vel. When transistor MP73 is in the ON state, one end of capacitor C82 is initialized by being set to the voltage of power supply line Vref.

[0093] FIG. 12 shows a seventh example of pixel configuration according to the first embodiment.

[0094] The display device 1 can employ the subpixels shown in FIG. 12 in addition to the subpixels described with reference to FIG. 6 . This subpixel includes a capacitor C51, transistors MP52 to MP60, and a light-emitting element EL. The transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to a control line WSL, the source is connected to a signal line SGL, and the drain is connected to the drain of transistor MP53 and the source of transistor MP54. The gate of transistor MP53 is connected to a control line DSL, the source is connected to a power supply line VCCP, and the drain is connected to the drain of transistor MP52 and the source of transistor MP54. The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, the source is connected to the drains of transistors MP52 and MP53, and the drain is connected to the sources of transistors MP58 and MP59. One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel. Transistor MP55 has a gate connected to control line AZSL1, a source connected to the gate of transistor MP54, the drain of transistor MP57, and the other end of capacitor C51, and a drain connected to the source of transistor MP56. Transistor MP56 has a gate connected to control line AZSL1, a source connected to the drain of transistor MP55, and a drain connected to power supply line VSS. Transistor MP57 has a gate connected to control line WSL, a drain connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and a source connected to the drain of transistor MP58. The gate of the transistor MP58 is connected to the control line WSL, the drain is connected to the source of the transistor MP57, and the source is connected to the drain of the transistor MP54 and the source of the transistor MP59.The gate of transistor 59 is connected to control line DSL, the source is connected to the drain of transistor MP54 and the source of transistor MP58, the drain is connected to the source of transistor MP60 and the anode of light-emitting element EL, the gate of transistor MP60 is connected to control line AZSL2, the source is connected to the drain of transistor MP59 and the anode of light-emitting element EL, and the drain is connected to power supply line VSS.

[0095] With this configuration, in the subpixel, transistors MP52, MP54, MP58, and MP57 are turned on, and the voltage across capacitor C51 is set based on the pixel signal supplied from signal line SGL. Transistors MP53 and MP59 are turned on and off based on the signal on control line DSL. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor MP54. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal on control line AZSL1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor MP60 is in the on state, the voltage of the anode of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0096] FIG. 13 shows an eighth example of pixel configuration in the first embodiment.

[0097] The display device 1 can employ the subpixels shown in Fig. 13 in addition to the subpixels described in Fig. 6. The signal on the signal line WSNL and the signal on the signal line WSPL are mutually inverted signals.

[0098] The subpixel includes capacitors C61 and C62, transistors MN63, MP64, and MN65 to MN67, and a light-emitting element EL. The transistors MN63, MN65 to MN67 are N-type MOSFETs, and the transistor MP64 is a P-type MOSFET. The gate of the transistor MN63 is connected to the signal line WSNL, the drain is connected to the signal line SGL and the source of the transistor MP64, the source is connected to the drain of the transistor MP64, the capacitors C61 and C62, and the gate of the transistor MN65. The gate of the transistor MP64 is connected to the signal line WSPL, the source is connected to the signal line SGL and the drain of the transistor MN63, and the drain is connected to the source of the transistor MN63, the capacitors C61 and C62, and the gate of the transistor MN65. The capacitor C61 is configured using, for example, a metal oxide metal (MOM) capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C61 may be configured using, for example, a metal oxide metal (MOS) capacitor or a metal insulator metal (MIM) capacitor. The capacitor C62 is configured using, for example, a MOS capacitor, with one end connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end connected to the power supply line VSS2. The capacitor C62 may be configured using, for example, a MOM capacitor or a MIM capacitor. The other end of the capacitor C62 may be connected to the power supply line VSS3 (not shown). The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to the power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67. The gate of transistor MN66 is connected to signal line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.The gate of the transistor MN67 is connected to the control line DSL, the drain is connected to the source of the transistor MN65 and the drain of the transistor MN66, and the source is connected to the anode of the light-emitting element EL.

[0099] With this configuration, in the subpixel, when at least one of transistors MN63 and MP64 is turned on, the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from signal line SGL. Transistor MN67 is turned on and off based on the signal on control line DSL. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor MP65. In this way, the subpixel emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on signal line AZL. Transistor MN66 may also function as a resistor element having a resistance value corresponding to the signal on signal line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0100] FIG. 14 shows a ninth example of a pixel configuration according to the first embodiment.

[0101] The display device 1 can employ the subpixels shown in FIG. 14 in addition to the subpixels described in FIG. 6 . FIG. 14 illustrates the configuration of subpixels in a liquid crystal display device. Note that FIG. 14 illustrates regions corresponding to four subpixels. As described above, a subpixel includes a liquid crystal element LC, a storage capacitor Cp, and an FET 110. A scanning line GL and a signal line DL are connected to each subpixel. The scanning line GL is connected to, for example, the gate of the FET 110 and is a wiring for supplying a scanning signal to the FET 110 at a predetermined timing from a scanning line driving circuit (not shown). The signal line DL is a wiring for supplying a signal based on an externally input video signal from the signal line driving circuit to each pixel P. Note that the scanning line driving circuit and the signal line driving circuit are formed in or connected to the peripheral region of the effective pixel region A. The pixels are formed across multiple layers on the driving substrate 10.

[0102] FIG. 15 is an example of a timing chart illustrating the light emission timing of each row of sub-pixels for one frame in the first embodiment.

[0103] 15 illustrates a timing chart for sequentially causing each sub-pixel to emit light for each row (also called line) for one frame (one vertical period). For ease of explanation, this figure shows the timing chart for the first and last lines.

[0104] In this example, an example will be described in which the subpixel shown in Fig. 7 is applied to the display device 1 shown in Fig. 3. Furthermore, since this subpixel is a P-channel type, the control lines WSL and DSL are in an active state when they are at a low potential, and in an inactive state when they are at a high potential.

[0105] In one vertical period, the sub-pixels connected to the control line WSL in each row start emitting light when the potential of the control line DSL becomes low during the corresponding horizontal period, and stop emitting light when the potential of the control line DSL becomes high according to a predetermined duty setting.

[0106] For example, a sub-pixel connected to the first control line WSL starts emitting light when the control line DSL goes low during a certain horizontal period. Similarly, sub-pixels belonging to the second, third, and so on repeat the light-emitting operation until the final line is reached. Furthermore, the sub-pixel connected to the first control line WSL stops emitting light when the control line DSL goes high at a timing determined by the duty setting. Similarly, the sub-pixels connected to the second, third, and so on, final control line WSL also stop emitting light when the control line DSL goes high at a timing determined by the duty setting. A detailed timing chart of each horizontal period will be described below.

[0107] FIG. 16 is a timing chart example 1 showing sub-pixel light emission in the first embodiment.

[0108] In this example, as in the above, an example in which the subpixels shown in FIG. 7 are applied to the display device 1 shown in FIG. 3 will be described. This timing chart shows horizontal periods H and H+1 for two subpixels, illustrating an example in which the subpixels connected to the control line WSL are caused to emit light for each horizontal period. In this figure, the portion surrounded by a dashed dotted line represents the timing chart for the horizontal period H for the subpixels connected to the control line WSL in the Nth row, and the portion surrounded by a dashed two-dotted line represents the timing chart for the horizontal period H+1 for the subpixels connected to the control line WSL in the N+1th row. This subpixel will be described assuming that the timing of its horizontal periods (H and H+1) is controlled by pulses such as a horizontal synchronization signal supplied from a control line XHL (not shown).

[0109] In addition, to distinguish between the control lines WSL, DSL, and AZSL connected to the subpixels in the Nth row or the subpixels in the N+1th row, the control line WSL in the N+1th row is referred to as control line WSL', the control line DSL is referred to as control line DSL', and the control line AZSL is referred to as control line AZSL'.

[0110] At time T1, the potential of the control line XHD changes from a high potential to a low potential, and at time T2, the potential of the control line XHD changes to a high potential, marking the start of one horizontal period H. At time T2, the potential of the control line DSL changes from a high potential to a low potential, marking the start of a Vth correction preparation period. This Vth correction preparation period continues until time T5.

[0111] At time T5, the potential of the control line DSL changes from low to high, entering a Vth correction period. At time T6, the potential of the control line WSL changes from high to low, ending the Vth correction period and entering a signal write period. At time T7, the potential of the control line WSL changes from low to high, ending the signal write period.

[0112] At time T8, the potential of the control line AZSL changes from low to high, completing the initialization of the light-emitting element EL. At time T9, the potential of the control line DSL changes from high to low, entering a light-emitting period. This light-emitting period continues until the potential of the control line DSL changes from low to high.

[0113] The timing chart for horizontal period H+1 (time T1' to time T9') is the same as that for horizontal period H+1, and therefore will not be described here. In horizontal period H+1, each corresponding subpixel emits light at time T9'.

[0114] FIG. 17 is a second example of a timing chart showing sub-pixel light emission in the first embodiment.

[0115] In this example, the control line WSL and the control line DSL connected to each subpixel in the Nth row and each subpixel in the N+1th row are described as different control lines. The control line WSL in the N+1th row is referred to as control line WSL′, and the control line DSL is referred to as control line DSL′.

[0116] This timing chart shows an example in which the light emission timing of each sub-pixel is synchronized in horizontal periods H and H+1. In the timing of horizontal period H, the display device 1 does not provide a timing that becomes a light emission period.

[0117] At time T8', the potential of the control line AZSL changes from low to high, completing the initialization of the light-emitting element EL. At time T9', the potentials of the control lines DSL and DSL' change from high to low, entering the light-emitting period. As a result, at time T9', which is the end of the horizontal periods H and H+1, the sub-pixels simultaneously emit light.

[0118] FIG. 18 is a timing chart example 3 showing sub-pixel light emission in the first embodiment.

[0119] In this timing chart, in addition to the operation described in Figure 17, an example is described in which a horizontal crosstalk improvement pulse is inserted to prevent the effects (horizontal crosstalk) caused by potential fluctuations in one of the electrodes when writing pixel signals to sub-pixels.

[0120] In this example, the control line WSL, control line DSL, and control line AZSL connected to each subpixel in the Nth row and each subpixel in the N+1th row will be described as being different control lines. The control line WSL in the N+1th row will be referred to as control line WSL′, the control line DSL as control line DSL′, and the control line AZSL as control line AZSL′.

[0121] In this example, in the horizontal period H, the potential of the control line AZSL changes from a low potential to a high potential before the timing of the signal write period at time T6, which is the start of a horizontal crosstalk improvement period. This horizontal crosstalk improvement period ends before the end of the signal write period at time T7.

[0122] Furthermore, in the horizontal period H+1, before the timing of time T6' which is the start of the signal write period, the potential of the control line AZSL' changes from low to high, entering a horizontal crosstalk improvement period, which ends before the end of the signal write period at time T7'.

[0123] 17 , in order to synchronize the light emission timing of each sub-pixel in the horizontal periods H and H+1, at time T9′ the potentials of the control lines DSL and DSL′ change from high to low, entering the light emission period, whereby each sub-pixel emits light simultaneously at time T9′, which is the end of the horizontal periods H and H+1.

[0124] FIG. 19 is a fourth example of a timing chart showing sub-pixel light emission in the first embodiment.

[0125] In this timing chart, an example in which a horizontal crosstalk improving pulse is inserted in addition to the operation explained in FIG. 17 will be explained.

[0126] In this example, the control line WSL connected to each sub-pixel in the Nth row and the control line WSL connected to each sub-pixel in the N+1th row are assumed to be different control lines. The control line WSL in the N+1th row is denoted as control line WSL′.

[0127] In this example, in the horizontal period H, the potential of the control line AZSL changes from a low potential to a high potential before the timing of the signal write period at time T6, which is the start of a horizontal crosstalk improvement period. This horizontal crosstalk improvement period ends before the end of the signal write period at time T7.

[0128] Furthermore, in the horizontal period H+1, before the timing of time T6′ which is the start of the signal write period, the potential of the control line AZSL changes from low to high, entering a horizontal crosstalk improvement period, which ends before the end of the signal write period at time T7′.

[0129] 16 to 19 described above show an example in which different control lines are used for the control lines in the Nth row and the control lines in the N+1th row, but the method of connecting the control lines is not limited to the above example. For example, the control lines in the Nth row and the control lines in the N+1th row do not need to be different control lines, or they may all be different control lines. Furthermore, the control lines in the Nth row and the control lines in the N+1th row may be connected using a connection method with a combination different from that in the above example.

[0130] Furthermore, when the display device 1 simultaneously emits light from each sub-pixel, it is possible to temporarily hold the pixel signal in a holding circuit that holds charge until the light-emitting period has elapsed. For example, the holding circuit may be provided as a capacitor in the sub-pixel circuit, or may be provided as a separate SRAM in the display device 1. When the timing of writing the pixel signal is shifted by one horizontal period, the display device 1 only needs to include a holding circuit that holds the charge of the pixel signal for one horizontal period.

[0131] According to this embodiment, in the display device 1, at least one of the sub-pixels constituting one pixel 15 is connected to a different control line WSL. As a result, the sub-pixels constituting each pixel 15 are not simultaneously written in the same row, and the writing is shifted in horizontal period units, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0132] Furthermore, according to this embodiment, the display device 1 does not experience large fluctuations in luminance even when there are variations in voltage, and can achieve high efficiency.

[0133] Second Embodiment FIG. 20 is a diagram showing an example of the configuration of a pixel array unit 11 according to a second embodiment.

[0134] In this embodiment, a set of pixels 15, which is a unit for forming a color image, is made up of sub-pixels of a plurality of colors, and these sub-pixels are arranged in a matrix in the pixel array section 11.

[0135] Furthermore, although one set of pixels is configured to include sub-pixels of the three primary colors of red, green, and blue, the types of sub-pixels are not limited to this, and may include, for example, a white sub-pixel.

[0136] In this embodiment, the sub-pixels constituting each pixel 15 are connected to either a control line WSL in an odd-numbered row (the Nth row and the N+2th row will be used for explanation) or a control line WSL in an even-numbered row (the N+1th row and the N+3th row will be used for explanation) for each pixel 15. Furthermore, among the sub-pixels constituting a set of pixels 15 connected to the control lines WSL in the odd-numbered or even-numbered rows, the sub-pixels of one color are connected to a control line WSL in an odd-numbered or even-numbered row that is different from the sub-pixels of the other colors.

[0137] Furthermore, the subpixels constituting a given pixel 15 are connected to a different control line WSL than the subpixels of the same color constituting the adjacent pixel 15 in the row direction. For example, for the pixel 15 on the left side of the Nth row, the red subpixel 42 is connected to the control line WSL of the Nth row, whereas the red subpixel 42'' of the pixel 15 adjacent to the right side of the pixel 15 is connected to the control line WSL of the N+2th row.

[0138] In this example, the blue subpixel is connected to a control line WSL different from that of the red and green subpixels in one set of pixels 15. The method of connecting the control lines WSL is not limited to this, and it is sufficient that at least one of the subpixels constituting one set of pixels 15 is connected to a different control line WSL.

[0139] For example, for pixel 15 shown on the left side of the Nth row, the red subpixel 42 connected to the signal line SGL in the Mth column and the green subpixel 44 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43" connected to the signal line SGL in the (M+1)th column is connected to the control line WSL in the (N+2)th row. Also, for pixel 15 shown on the right side of the Nth row, the red subpixel 42" connected to the signal line SGL in the (M+3)th column and the green subpixel 44" connected to the signal line SGL in the (M+5)th column are connected to the control line WSL in the (N+2)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+4)th column is connected to the control line WSL in the Nth row.

[0140] For the pixel 15 shown on the left side of the N+1th row, the red subpixel 42' connected to the signal line SGL in the Mth column and the green subpixel 44' connected to the signal line SGL in the M+2th column are connected to the control line WSL in the N+1th row, and the blue subpixel 43''' connected to the signal line SGL in the M+1th column is connected to the control line WSL in the N+3th row. For the pixel 15 shown on the right side of the N+1th row, the red subpixel 42''' connected to the signal line SGL in the M+3th column and the green subpixel 44''' connected to the signal line SGL in the M+5th column are connected to the control line WSL in the N+3th row, and the blue subpixel 43' is connected to the control line WSL in the N+1th row.

[0141] Similarly, the pixel 15 shown on the left side of the N+2th row has the same connection configuration with respect to the control line WSL as the pixel 15 on the right side arranged in the Nth row. Also, the pixel 15 shown on the right side of the N+2th row has the same connection configuration with respect to the control line WSL as the pixel 15 on the left side arranged in the Nth row.

[0142] The pixel 15 arranged in the (N+3)th row shown on the left has the same connection configuration with respect to the control line WSL as the pixel 15 on the right side arranged in the (N+1)th row. The pixel 15 on the right side arranged in the (N+3)th row has the same connection configuration with respect to the control line WSL as the pixel 15 on the left side arranged in the (N+1)th row.

[0143] The connection configuration of the Nth to N+3th rows is a repetition of the connection configuration shown by the two pixels 15 (six sub-pixels) on the left and right sides of each row. This connection configuration may also be provided in a part of the pixel array unit 11.

[0144] For a set of pixels 15 arranged in the Nth row (here, we consider a pixel 15 consisting of a red subpixel 42, a blue subpixel 43'', and a green subpixel 44 on the left side), if the timing at which a pixel signal is supplied to the red subpixel 42 and the green subpixel 44 from the signal output unit 18 via the signal line SGL is H, then the pixel signal is supplied to the blue subpixel 43'' at timing H+2, that is, with a delay of two horizontal periods.

[0145] For a set of pixels 15 arranged in the N+2th row (here, we consider the pixel 15 consisting of the red subpixel 42″, blue subpixel 43, and green subpixel 44″ on the left side), if the timing at which a pixel signal is supplied to the red subpixel 42″ and the green subpixel 44″ from the signal output unit 18 via the signal line SGL is H+2, then the pixel signal is supplied to the blue subpixel 43 at the timing of H, which is two horizontal periods earlier.

[0146] The sub-pixels constituting each pixel 15 may have the configurations shown in FIGS. 6 to 14, or may have other configurations.

[0147] FIG. 21 is another example of a configuration diagram of the pixel array unit 11 according to the second embodiment.

[0148] In this example, a set of pixels is configured to include red, green, and blue subpixels as well as a white subpixel, which is an example of a fourth subpixel.

[0149] Furthermore, without being limited to the examples described in the following embodiments, different colors may be adopted for the first to fourth sub-pixels.

[0150] In this example, the blue and white subpixels of one set of pixels 15 are connected to different control lines WSL than the red and green subpixels.

[0151] Furthermore, each subpixel constituting a pixel 15 is connected to the same control line WSL as a subpixel of the same color constituting an adjacent pixel 15 in the row direction. For example, for the pixel 15 on the left side of the Nth row, the red subpixel 42'' is connected to the control line WSL in the N+2th row, while the red subpixel 42'' of the pixel 15 adjacent to the pixel 15 on the right side is also connected to the control line WSL in the N+2th row.

[0152] For example, as shown in the pixel 15 shown on the left side of the Nth row, the red subpixel 42'' connected to the signal line SGL in the (M+1)th column and the green subpixel 44'' connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the (N+2)th row, and the white subpixel 45 connected to the signal line SGL in the Mth column and the blue subpixel 43 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row. The pixel 15 shown on the right side of the Nth row is connected in the same manner as the pixel on the left side.

[0153] Furthermore, for the pixel 15 shown on the left side of the N+1th row, the red subpixel 42''' connected to the signal line SGL in the M+1th column and the green subpixel 44''' connected to the signal line SGL in the M+3th column are connected to the control line WSL in the N+3th row, and the white subpixel 45' connected to the signal line SGL in the Mth column and the blue subpixel 43' connected to the signal line SGL in the M+2th column are connected to the control line WSL in the N+1th row. The pixel 15 shown on the right side of the N+1th row is connected in a similar manner.

[0154] Furthermore, for the pixel 15 shown on the left side of the N+2th row, the red subpixel 42 connected to the signal line SGL in the (M+1)th column and the green subpixel 44 connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the Nth row, and the white subpixel 45" connected to the signal line SGL in the Mth column and the blue subpixel 43" connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+2)th row. The pixel 15 shown on the right side of the N+2th row is connected in a similar manner.

[0155] Furthermore, for the pixel 15 shown on the left side of the N+3 row, the red subpixel 42' connected to the signal line SGL in the (M+1)th column and the green subpixel 44' connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the (N+1)th row, and the white subpixel 45''' connected to the signal line SGL in the Mth column and the blue subpixel 43''' connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+3)th row. The pixel 15 shown on the right side of the N+3 row is connected in a similar manner.

[0156] The connection configuration of the Nth to N+3th rows is a repetition of the connection configuration shown for one pixel 15 (four sub-pixels) on the left side of each row. This connection configuration may also be provided in a part of the pixel array unit 11.

[0157] For a set of pixels 15 arranged in the Nth row (here, we consider a pixel 15 consisting of a red subpixel 42'', a blue subpixel 43, a green subpixel 44'', and a white subpixel 45 on the left side), if the timing at which a pixel signal is supplied from the signal output unit 18 to the white subpixel 45 and the blue subpixel 43 via the signal line SGL is H, then the pixel signal is supplied to the red subpixel 42'' and the green subpixel 44'' at timing H+2, that is, with a delay of two horizontal periods.

[0158] For a set of pixels 15 arranged in the N+2th row (here, we consider a pixel 15 consisting of a red subpixel 42, a blue subpixel 43'', a green subpixel 44, and a white subpixel 45'' on the left side), if the timing at which a pixel signal is supplied to the red subpixel 42 and the green subpixel 44 from the signal output unit 18 via the signal line SGL is H, then the pixel signal is supplied to the white subpixel 45'' and the blue subpixel 43'' at timing H+2, which is two horizontal periods earlier.

[0159] Similarly, for a set of pixels 15 arranged in the (N+1)th and (N+3)th rows, pixel signals are supplied to the sub-pixels with a shift of two horizontal periods.

[0160] FIG. 22 is yet another example of a configuration diagram of the pixel array unit 11 according to the second embodiment.

[0161] In this example, unlike the example of FIG. 21, sub-pixels constituting a given pixel 15 are connected to a different control line WSL than sub-pixels of the same color constituting adjacent pixels 15 in the row direction.

[0162] For example, for a pixel 15 shown on the left side of the Nth row, the red subpixel 42" connected to the signal line SGL in the (M+1)th column and the green subpixel 44" connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the (N+2)th row, and the white subpixel 45 connected to the signal line SGL in the Mth column and the blue subpixel 43 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row. Also, for a set of pixels 15 shown on the right side of the Nth row, the red subpixel 42 connected to the signal line SGL in the (M+5)th column and the green subpixel 44 connected to the signal line SGL in the (M+7)th column are connected to the control line WSL in the Nth row, and the white subpixel 45" connected to the signal line SGL in the (M+4)th column and the blue subpixel 43" connected to the signal line SGL in the (M+6)th column are connected to the control line WSL in the (N+2)th row.

[0163] For the pixel 15 shown on the left side of the N+1th row, the red subpixel 42''' connected to the signal line SGL in the (M+1)th column and the green subpixel 44''' connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the (N+3)th row, and the white subpixel 45' connected to the signal line SGL in the (M+2)th column and the blue subpixel 43' connected to the signal line SGL in the (M+1)th column are connected to the control line WSL in the (N+1)th row. For the pixel 15 shown on the right side of the N+1th row, the red subpixel 42' connected to the signal line SGL in the (M+5)th column and the green subpixel 44' connected to the signal line SGL in the (M+7)th column are connected to the control line WSL in the (N+1)th row, and the white subpixel 45''' connected to the signal line SGL in the (M+4)th column and the blue subpixel 43''' connected to the signal line SGL in the (M+6)th column are connected to the control line WSL in the (N+3)th row.

[0164] For the pixel 15 shown on the left side of the N+2th row, the red subpixel 42 connected to the signal line SGL in the (M+1)th column and the green subpixel 44 connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the Nth row, and the white subpixel 45" connected to the signal line SGL in the Mth column and the blue subpixel 43" connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+2)th row. For the pixel 15 shown on the right side of the N+2th row, the red subpixel 42" connected to the signal line SGL in the (M+5)th column and the green subpixel 44" connected to the signal line SGL in the (M+7)th column are connected to the control line WSL in the (N+2)th row, and the white subpixel 45 connected to the signal line SGL in the (M+4)th column and the blue subpixel 43 connected to the signal line SGL in the (M+6)th column are connected to the control line WSL in the Nth row.

[0165] For the pixel shown on the left side of the N+3 row, the red subpixel 42' connected to the signal line SGL in the (M+1)th column and the green subpixel 44' connected to the signal line SGL in the (M+3)th column are connected to the control line WSL in the (N+1)th row, and the white subpixel 45''' connected to the signal line SGL in the (M+2)th column and the blue subpixel 43''' connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+3)th row. For the pixel 15 shown on the right side of the N+3 row, the red subpixel 42''' connected to the signal line SGL in the (M+5)th column and the green subpixel 44''' connected to the signal line SGL in the (M+7)th column are connected to the control line WSL in the (N+3)th row, and the white subpixel 45' connected to the signal line SGL in the (M+4)th column and the blue subpixel 43' connected to the signal line SGL in the (M+6)th column are connected to the control line WSL in the (N+1)th row.

[0166] The connection configuration of the Nth to N+3th rows is a repetition of the connection configuration shown by the two pixels 15 (eight sub-pixels) on the left and right sides of each row. This connection configuration may also be provided in a part of the pixel array unit 11.

[0167] FIG. 23 is a timing chart example 1 showing sub-pixel light emission in the second embodiment.

[0168] In this example, an example will be described in which the sub-pixels shown in Fig. 7 are applied to the display device 1 shown in Fig. 3. This timing chart also shows an example in which the sub-pixels connected to the control line WSL are caused to emit light for each horizontal period from horizontal period H to horizontal period H+3. This figure shows the timing chart for horizontal periods H to H+3, from left to right, for the area surrounded by the dashed dotted line.

[0169] Furthermore, since this subpixel is a P-channel type, the control lines WSL and DSL are in an active state when they are at a low potential, and in an inactive state when they are at a high potential.

[0170] In this example, the control lines WSL, DSL, and AZSL connected to the pixels in the Nth to N+3th rows will be described as being different control lines. The control lines WSL in the N+1th to N+3th rows will be referred to as control line WSL', control line WSL", and control line WSL'", respectively, the control lines DSL will be referred to as control line DSL', control line DSL", and control line DSL'", respectively, and the control lines AZSL will be referred to as control line AZSL', control line AZSL", and control line AZSL'".

[0171] The timing chart of the horizontal period H (time T1 to time T9) can be the same as the timing chart of the time T1 to time T9 shown in Fig. 16. The timing chart of the horizontal period H+1 (time T1' to time T9'), the timing chart of the horizontal period H+2 (time T1" to time T9"), and the timing chart of the horizontal period H+3 (time T1'" to time T9'") can be the same as the timing chart of the horizontal period H.

[0172] FIG. 24 is a second example of a timing chart showing sub-pixel light emission in the second embodiment.

[0173] This example is a timing chart in which the light emission timing of each sub-pixel is synchronized in horizontal period H to horizontal period H+3.

[0174] In this example, the control lines WSL and DSL connected to the pixels in the Nth to N+3th rows will be described as different control lines. The control lines WSL in the N+1th to N+3th rows will be referred to as control line WSL', control line WSL'', and control line WSL''', respectively, and the control lines DSL will be referred to as control line DSL', control line DSL'', and control line DSL''', respectively.

[0175] The timing chart of the horizontal period H (time T1 to time T7) can be the same as the timing chart of time T1 to time T7 shown in FIG. 17. The timing chart of the horizontal period H+1 (time T1' to time T7'), the timing chart of the horizontal period H+2 (time T1" to time T7"), and the timing chart of the horizontal period H+3 (time T1'" to time T7'") can be the same as the timing chart of the horizontal period H. The timing chart of the horizontal period H+3 (time T8'" to time T9'") can be the same as the timing chart of time T8' to time T9' shown in FIG.

[0176] FIG. 25 is a timing chart example 3 for when sub-pixels emit light in the second embodiment.

[0177] In this timing chart, in addition to the operation of the display device 1 described with reference to FIG. 24, an operation of inserting a horizontal crosstalk reducing pulse will be described.

[0178] In this example, the control lines WSL, DSL, and AZSL connected to the pixels in the Nth to N+3th rows will be described as being different control lines. The control lines WSL in the N+1th to N+3th rows will be referred to as control line WSL', control line WSL", and control line WSL'", respectively, the control lines DSL will be referred to as control line DSL', control line DSL", and control line DSL'", respectively, and the control lines AZSL will be referred to as control line AZSL', control line AZSL", and control line AZSL'".

[0179] The timing chart of the horizontal period H (time T1 to time T7) can be the same as the timing chart of time T1 to time T7 shown in FIG. 18. The timing chart of the horizontal period H+1 (time T1' to time T7'), the timing chart of the horizontal period H+2 (time T1" to time T7"), and the timing chart of the horizontal period H+3 (time T1'" to time T7'") can be the same as the timing chart of the horizontal period H. The timing chart of the horizontal period H+3 (time T8'" to time T9'") can be the same as the timing chart of time T8' to time T9' shown in FIG.

[0180] FIG. 26 is a fourth example of a timing chart showing sub-pixel light emission in the second embodiment.

[0181] In this timing chart, in addition to the operation of the display device 1 described with reference to FIG. 24, another example of the operation of inserting a horizontal crosstalk reducing pulse will be described.

[0182] In this example, the control lines WSL connected to the pixels in the Nth to N+3th rows are described as different control lines. The control lines WSL in the Nth to N+3th rows are denoted as control line WSL', control line WSL'', and control line WSL''', respectively.

[0183] The timing chart of the horizontal period H (time T1 to time T7) can be the same as the timing chart of time T1 to time T7 shown in FIG. 19. The timing chart of the horizontal period H+1 (time T1' to time T7'), the timing chart of the horizontal period H+2 (time T1" to time T7"), and the timing chart of the horizontal period H+3 (time T1'" to time T7'") can be the same as the timing chart of the horizontal period H. The timing chart of the horizontal period H+3 (time T8'" to time T9'") can be the same as the timing chart of time T8' to time T9' shown in FIG.

[0184] Furthermore, when the display device 1 simultaneously emits light from each sub-pixel, it is possible to temporarily hold the pixel signal in a holding circuit that holds the charge until the light-emitting period has elapsed. For example, the holding circuit may be provided as a capacitor in the sub-pixel circuit, or may be provided as a separate SRAM in the display device 1. When the timing of writing the pixel signal is shifted by two horizontal periods, the display device 1 may be provided with a holding circuit that holds the charge of the pixel signal for three horizontal periods.

[0185] In the above-described embodiment, the write timing of pixel signals for sub-pixels arranged in the same row is shifted by one or two horizontal periods, but the shift timing of pixel signal write is not limited to this. For example, the write timing of sub-pixels arranged in the same row may be shifted by any timing, such as three or four horizontal periods. For example, when the write timing of sub-pixels arranged in the same row is shifted by L horizontal periods (L is an integer greater than or equal to 1), the sub-pixels whose write timing is shifted are connected to the control line WSL of the Lth row.

[0186] According to this embodiment, in the display device 1, at least one of the sub-pixels constituting one pixel 15 is connected to a different control line WSL. As a result, the sub-pixels constituting each pixel 15 are not simultaneously written in the same row, and the writing is shifted in horizontal period units, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0187] Furthermore, according to this embodiment, the display device 1 does not experience large fluctuations in luminance even when there are variations in voltage, and can achieve high efficiency.

[0188] Furthermore, according to this embodiment, the display device 1 connects the green subpixel and the white subpixel, which affect the luminance, to different control lines WSL, thereby making horizontal stripes less visible.

[0189] Third Embodiment FIG. 27 shows an example of the configuration of a display device 1 according to a third embodiment.

[0190] In this embodiment, unlike the first embodiment, the display device 1 includes a first signal output unit 19 and a second signal output unit 20 .

[0191] The first signal output unit 19 supplies pixel signals to a plurality of pixels 15 belonging to a predetermined column. The second signal output unit 20 supplies pixel signals to a plurality of pixels 15 belonging to a column different from the signal line SGL of the predetermined column to which the first signal output unit 19 is connected. The display device 1 causes a target sub-pixel in a row selected by the write scanning unit 16 to emit light based on the pixel signals output from the first signal output unit 19 and the second signal output unit 20.

[0192] FIG. 28 shows an example of the connection relationship of the display device 1 according to the third embodiment.

[0193] The first signal output unit 19 and the second signal output unit 20 are connected to a signal line SGL that transmits pixel signals to each sub-pixel, for example, alternately for each pixel 15. For example, the first signal output unit 19 may output pixel signals for the pixels 15 in odd-numbered columns, and the second signal output unit 20 may output pixel signals for the pixels 15 in even-numbered columns.

[0194] In this example, the signal lines connected to the first signal output unit 19 are referred to as signal lines SGL, and the signal lines connected to the second signal output unit 20 are referred to as signal lines SGL'. The signal lines SGL connected to the first signal output unit 19 are also collectively referred to as a first group of signal lines, and the signal lines SGL' connected to the second signal output unit 20 are also collectively referred to as a second group of signal lines.

[0195] The display device 1 also includes a switch 46 that electrically connects or disconnects the signal line SGL connected to the first signal output unit 19 and the signal line SGL′ connected to the second signal output unit 20 by conducting the signal line SGL.

[0196] In this example, for two sets of adjacent pixels 15, the pixel 15 connected to the first signal output unit 19 and the pixel 15 connected to the second signal output unit 20 have sub-pixels of the same color connected via switches 46.

[0197] 28A , in the normal state, the pixels 15 connected to the control lines WSL driven by the write scanning unit 16 emit light with appropriate intensity in response to pixel signals output from the first signal output unit 19 and the second signal output unit 20. In this way, in the normal state, the display device 1 transmits pixel signals from the first signal output unit 19 and the second signal output unit 20 to the pixels 15 without thinning out the pixel signals.

[0198] On the other hand, by connecting the switch 46, the display device 1 can perform horizontal doubling processing to output the same pixel signal. For example, as shown in FIG. 28B , by connecting the switch 46, the display device 1 can supply the same pixel signal output from the first signal output unit to two pixels 15 in the column direction. This allows the display device 1 to output an image or video with half the resolution. The display device 1 can reduce the power consumption of the entire circuit by, for example, stopping the second signal output unit 20 and thinning out pixel signals in a predetermined region by horizontal doubling processing.

[0199] FIG. 29 is an example of a configuration diagram of the pixel array unit 11 in the third embodiment.

[0200] In this example, a set of pixels is configured to include sub-pixels of the three primary colors of red, green, and blue, but the types of sub-pixels are not limited to this and may include, for example, white sub-pixels.

[0201] Figure 29A shows a configuration diagram of the pixel array section 11 when the switch 46 is in a non-conducting state, i.e., in a normal state, and Figure 29B shows the state of the pixel array section 11 when the switch 46 is in a conducting state, i.e., in a state in which horizontal doubling processing is being performed.

[0202] Furthermore, for a certain row, thinning of pixel signals by horizontal doubling processing is performed between a pixel 15 connected to the first signal output unit 19 and a pixel 15 adjacent to that pixel and connected to the second signal output unit 20.

[0203] In this embodiment, of the multiple subpixels arranged in each row, at least one subpixel is connected to a control line WSL that is different from the control lines WSL to which the other subpixels are connected. In this example, the blue subpixel of one set of pixels 15 is connected to a control line WSL that is different from the control lines WSL to which the red and green subpixels are connected. Furthermore, the method of connecting the control lines WSL is not limited to this, and at least one subpixel of a certain color among the subpixels constituting one set of pixels 15 may be connected to a control line WSL that is different from the control lines WSL to which the subpixels of the other colors are connected.

[0204] For example, for the pixel 15 shown first from the left in the Nth row, the red subpixel 42 connected to the signal line SGL in the Mth column and the green subpixel 44 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43′ connected to the signal line SGL in the (M+1)th column is connected to the control line WSL in the (N+1)th row. Also, for the pixel 15 shown second from the left in the Nth row, the red subpixel 42′ connected to the signal line SGL in the (M+3)th column and the green subpixel 44′ connected to the signal line SGL in the (M+5)th column are connected to the control line WSL in the (N+1)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+4)th column is connected to the control line WSL in the Nth row.

[0205] 29B , in the horizontal doubling process, each sub-pixel constituting the pixel 15 shown first from the left in the Nth row and the sub-pixel of the same color constituting the pixel 15 shown second from the left in the Nth row are connected by switches 46. After the second signal output unit 20 stops, the pixel signal is supplied from the first signal output unit 19 to the corresponding sub-pixel.

[0206] For the pixel 15 shown on the left side of the N+1th row, the red subpixel 42′ connected to the signal line SGL in the Mth column and the green subpixel 44′ connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the (N+1)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+2)th column is connected to the control line WSL in the Nth row. For the pixel 15 shown second from the left in the N+1th row, the red subpixel 42 connected to the signal line SGL in the (M+3)th column and the green subpixel 44 connected to the signal line SGL in the (M+5)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43′ connected to the signal line SGL in the (M+4)th column is connected to the control line WSL in the (N+1)th row.

[0207] Furthermore, the connection configuration of the pixels in the (M+6)th and (N+1)th rows and beyond is similar to the connection configuration of the subpixels in the (M+5)th to (M+6)th columns described above. For example, the connection configuration of the subpixels in the (M+6)th to (M+8)th columns is similar to the connection configuration of the subpixels in the (M+2)th to (M+2)th columns, and the connection configuration of the subpixels in the (M+9)th to (M+11)th columns is similar to the connection configuration of the subpixels in the (M+3) to (M+5)th columns. The connection configuration of the (N+1)th and (N+1)th rows is a repetition of the connection configuration shown for the two leftmost pixels 15 (six subpixels). This connection configuration may also be provided in a portion of the pixel array section 11.

[0208] Red subpixels are connected to the signal line SGL in the Mth column and the signal line SGL' in the (M+3)th column, and the signal line SGL in the (M+6)th column and the signal line SGL' in the (M+9)th column when the switch 46 is turned on. Blue subpixels are connected to the signal line SGL in the (M+1)th column and the signal line SGL' in the (M+4)th column, and the signal line SGL in the (M+7)th column and the signal line SGL' in the (M+10)th column when the switch 46 is turned on. Green subpixels are connected to the signal line SGL in the (M+2)th column and the signal line SGL' in the (M+5)th column, and the signal line SGL' in the (M+8)th column and the signal line SGL' in the (M+11)th column when the switch 46 is turned on. For example, the first signal output unit 19 performs thinning by supplying pixel signals to the respective signal lines connected thereto.

[0209] FIG. 30 is another example of a configuration diagram of the pixel array unit 11 according to the third embodiment.

[0210] 29B , when performing horizontal doubler processing, a subpixel in the Nth row and a subpixel in the N+1th row, which is supplied with the same pixel signal as the subpixel in the Nth row via the switch 46, are in different rows but have the same data, which may cause jerky images in the displayed image. In this example, an example will be described in which subpixels of the same color arranged in the same row are connected by the switch 46.

[0211] 30A , in this example, the blue subpixel of a set of pixels 15 is connected to a different control line WSL from the red and green subpixels. The method of connecting the control lines WSL is not limited to this; it is sufficient that at least one subpixel of a certain color among the subpixels constituting a set of pixels 15 is connected to a different control line WSL from the other subpixels. Although not shown in this figure, each subpixel is connected to the write scanning unit 16 by a control line WSL and a control line AZSL.

[0212] For example, for the pixel 15 shown first from the left in the Nth row, the red subpixel 42 connected to the signal line SGL in the Mth column and the green subpixel 44 connected to the signal line SGL in the (M+2)th column are connected to the control line WSL in the Nth row, and the blue subpixel 43′ connected to the signal line SGL in the (M+1)th column is connected to the control line WSL in the (N+1)th row. The pixel 15 shown second from the left in the Nth row has a similar connection configuration.

[0213] Furthermore, for the pixel 15 shown third from the left in the Nth row, the red subpixel 42′ connected to the signal line SGL in the (M+6)th column and the green subpixel 44′ connected to the signal line SGL in the (M+8)th column are connected to the control line WSL in the (N+1)th row, and the blue subpixel 43 connected to the signal line SGL in the (M+7)th column is connected to the control line WSL in the Nth row. The pixel 15 shown fourth from the left in the Nth row has a similar connection configuration.

[0214] The connection configuration of the entire Nth row is a repetition of the connection configuration shown by the four pixels 15 (12 sub-pixels) from the left. This connection configuration may also be provided in a part of the pixel array unit 11.

[0215] Furthermore, for the pixel 15 shown first from the left in the N+1 row, the red sub-pixel 42′ connected to the signal line SGL in the Mth column and the green sub-pixel 44′ connected to the signal line SGL in the M+2th column are connected to the control line WSL in the N+1th row, and the blue sub-pixel 43 connected to the signal line SGL in the M+2th column is connected to the control line WSL in the Nth row. The pixel 15 shown second from the left in the N+1 row has a similar connection configuration.

[0216] In addition, for the pixel 15 shown third from the left in the N+1 row, the red subpixel 42 connected to the signal line SGL in the (M+6) column and the green subpixel 44 connected to the signal line SGL in the (M+8) column are connected to the control line WSL in the N row, and the blue subpixel 43′ connected to the signal line SGL in the (M+7) column is connected to the control line WSL in the (N+1) row. A similar connection configuration is also configured for a set of pixels 15 in the fourth column from the left arranged in the N+1 row.

[0217] The connection configuration of the entire N+1th row is a repetition of the connection configuration shown by the four pixels 15 (12 sub-pixels) from the left. This connection configuration may also be provided in a part of the pixel array unit 11.

[0218] 30B , in the horizontal doubling process, each sub-pixel constituting the pixel 15 shown first from the left in the Nth row and the sub-pixel of the same color constituting the pixel 15 shown second from the left in the Nth row are connected by switches 46. Furthermore, after the second signal output unit 20 stops, the pixel signal is supplied from the first signal output unit 19 to the corresponding sub-pixel.

[0219] Since horizontal doubling is performed on sub-pixels belonging to the same row, the display device 1 can output a display image with less jerky images.

[0220] FIG. 31 is a diagram showing yet another example of the configuration of the pixel array unit 11 according to the third embodiment.

[0221] In this example, the connection configuration of the control lines WSL is different from that of FIG.

[0222] 31A , in this example, the subpixels constituting a set of pixels 15 are connected to the same control line WSL. Also, as shown in the figure, the subpixel constituting the pixel 15 shown first from the left in the Nth row and the subpixel constituting the pixel 15 shown second from the left in the Nth row are connected to the same control line WSL. Also, the subpixel constituting the pixel 15 shown third from the left in the Nth row and the subpixel constituting the pixel 15 shown fourth from the left in the Nth row are connected to the same control line WSL. Furthermore, the control line WSL to which the first and second pixels 15 are connected is different from the control line WSL to which the third and fourth pixels 15 are connected.

[0223] For example, for the pixel 15 shown first from the left on the Nth row, the red subpixel 42 connected to the signal line SGL on the Mth column, the blue subpixel 43 connected to the signal line SGL on the (M+1)th column, and the green subpixel 44 connected to the signal line SGL on the (M+2)th column are connected to the control line WSL on the Nth row. The pixel 15 shown second from the left on the Nth row has a similar connection configuration.

[0224] For the pixel 15 shown third from the left in the Nth row, the red subpixel 42' connected to the signal line SGL in the (M+6)th column, the blue subpixel 43' connected to the signal line SGL in the (M+7)th column, and the green subpixel 44' connected to the signal line SGL in the (M+8)th column are connected to the control line WSL in the (N+1)th row. The pixel 15 shown fourth from the left in the Nth row has a similar connection configuration.

[0225] The connection configuration of the entire Nth row is a repetition of the connection configuration shown by the four pixels 15 (12 sub-pixels) from the left. This connection configuration may also be provided in a part of the pixel array unit 11.

[0226] For the pixel 15 shown first from the left in the N+1 row, the red subpixel 42' connected to the signal line SGL in the Mth column, the blue subpixel 43' connected to the signal line SGL in the M+1th column, and the green subpixel 44' connected to the signal line SGL in the M+2th column are connected to the control line WSL in the N+1th row. The pixel 15 shown second from the left in the N+1th row has a similar connection configuration.

[0227] Furthermore, for the pixel 15 shown third from the left in the N+1th row, the red subpixel 42 connected to the signal line SGL in the (M+6)th column, the blue subpixel 43 connected to the signal line SGL in the (M+7)th column, and the green subpixel 44 connected to the signal line SGL in the (M+8)th column are connected to the control line WSL in the Nth row. A similar connection configuration is also configured for a set of pixels 15 in the fourth column from the left arranged in the Nth row.

[0228] The connection configuration of the entire N+1th row is a repetition of the connection configuration shown by the four pixels 15 (12 sub-pixels) from the left. This connection configuration may also be provided in a part of the pixel array unit 11.

[0229] Since horizontal report doubler processing is performed on sub-pixels belonging to the same row, the display device 1 can output a display image with less jerky images.

[0230] According to this embodiment, in the display device 1, at least one of the sub-pixels constituting one set of pixels 15 is connected to a different control line WSL, or the sub-pixels constituting one set of pixels 15 are connected to different control lines WSL in a predetermined repeating unit. As a result, the writing of the sub-pixels constituting each pixel 15 in the same row is shifted by a horizontal period, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0231] Furthermore, according to this embodiment, the display device 1 does not experience large fluctuations in luminance even when there are variations in voltage, and can achieve high efficiency.

[0232] Furthermore, according to this embodiment, the display device 1 can perform horizontal doubling processing by connecting the sub-pixels that make up each pixel 15 to the above-mentioned control line WSL, thereby reducing power consumption.

[0233] Fourth Embodiment FIG. 32 is a diagram illustrating an example of a light emitting method of the pixel array section 11 according to a fourth embodiment.

[0234] In this example, a light emission method will be described in which the write scanning unit 16 outputs drive signals to two rows in a vertical doubler process. In the vertical doubler process, two control lines WSL are treated as one pair, and the signal output unit 18 supplies pixel signals to each sub-pixel connected to each selected pair.

[0235] In the vertical doubler, during the first and second horizontal periods of the first frame (first vertical period), the signal output unit 18 supplies pixel signals of an odd field (odd rows) to each sub-pixel connected to each selected set of control lines WSL. Also, during the first and second horizontal periods of the second frame (second vertical period), the signal output unit 18 supplies pixel signals of an even field (even rows) to each sub-pixel connected to each selected set of control lines WSL. The odd field is an example of the first field, and the even field is an example of the second field.

[0236] In this embodiment, the connection configuration of the control lines WSL is the same as that in the example of FIG.

[0237] In a normal state, no vertical doubling process is performed, and the display device 1 operates in the same manner as in the example of Fig. 3. That is, pixel signals are supplied to the sub-pixels connected to the control line WSL in the Nth row one horizontal period earlier than the sub-pixels connected to the control line WSL in the (N+1)th row.

[0238] If, in vertical doubling processing, the display device 1 supplies the same pixel signal to the sub-pixels in the Nth row and the sub-pixels in the N+1th row, the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig are not dispersed.

[0239] Therefore, in vertical doubling processing, the signal output unit 18 supplies the same pixel signal to the sub-pixel connected to the control line WSL in the (N+1)th row and the sub-pixel connected to the control line WSL in the (N+2)th row. The signal output unit 18 also supplies the same pixel signal to the sub-pixel connected to the control line WSL in the (N+3)th row and the sub-pixel connected to the control line WSL in the (N+4)th row. For example, as shown by the circle in the figure, the same pixel signal is supplied from the signal output unit 18 to the blue sub-pixel 43' connected to the control line WSL in the (N+1)th row and the blue sub-pixel 43' connected to the control line WSL in the (N+2)th row.

[0240] For the sake of explanation, the operations of the pixel 15 shown on the left side of the N+1th row and the pixel 15 shown on the left side of the N+2th row in the first horizontal period and the second horizontal period in the first frame will be described. That is, pixel signals of the ODD field are supplied to each sub-pixel connected to each set of control lines WSL.

[0241] For example, the red sub-pixel 42′ arranged in the N+1th row and connected to the Mth column signal line SGL and the red sub-pixel 42′ arranged in the N+2th row and connected to the Mth column signal line SGL are supplied with the pixel signal during the first horizontal period based on the control of the N+1th and N+2th row control lines WSL. Similarly, the green sub-pixel 44′ arranged in the N+1th row and connected to the M+2th column signal line and the green sub-pixel 44′ arranged in the N+2th row and connected to the M+2th column signal line are supplied with the pixel signal during the first horizontal period.

[0242] In addition, the pixel signal is supplied to the blue sub-pixel 43′ arranged in the Nth row and connected to the signal line SGL in the (M+1)th column, and the blue sub-pixel 43′ arranged in the (N+3)th row and connected to the signal line SGL in the (M+1)th column, in the same manner as described above, during the first horizontal period.

[0243] A pixel signal is supplied to the red sub-pixel 42 arranged in the N+3 row and connected to the signal line of the Mth column, and the red sub-pixel 42 arranged in the N+4 row and connected to the signal line of the Mth column, during the second horizontal period, based on the control of the control lines WSL in the N+3 and N+4 rows. Similarly to the above, the pixel signal is supplied to the green sub-pixel 44 arranged in the N+3 row and connected to the signal line of the M+2th column, and the green sub-pixel 44 arranged in the N+4 row and connected to the signal line of the M+2th column, during the second horizontal period.

[0244] In addition, pixel signals are supplied to the blue sub-pixel 43 arranged in the N+2th row and connected to the signal line in the M+1th column, and the blue sub-pixel 43 arranged in the N+5th row and connected to the signal line in the M+1th column, in the same manner as described above, during the second horizontal period.

[0245] In the first and second horizontal periods of the second frame, as in the first frame, pixel signals of the EVEN field are supplied from the signal output unit 18 to the sub-pixels connected to the signal lines SGL of the Mth to (M+5th)th columns.

[0246] According to this embodiment, in the display device 1, at least one of the sub-pixels constituting one pixel 15 is connected to a different control line WSL. As a result, the sub-pixels constituting each pixel 15 are not simultaneously written in the same row, and the writing is shifted in horizontal period units, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0247] Furthermore, according to this embodiment, the display device 1 does not experience large fluctuations in luminance even when there are variations in voltage, and can achieve high efficiency.

[0248] Furthermore, according to this embodiment, the display device 1 can perform vertical doubling processing and reduce power consumption by simultaneously writing sub-pixels of the same color to sub-pixels connected to control lines WSL in the N+1th row, N+2th row, etc.

[0249] Fifth Embodiment FIG. 33 is a diagram illustrating an example of a light emitting method in a normal state of the pixel array unit 11 according to a fifth embodiment.

[0250] In the fifth embodiment, the display device 1 supplies the same pixel signal to the subpixels connected to the N+1th row and the subpixels connected to the N+2th row during vertical doubler processing, so that, for example, the subpixels indicated by circles in Figure 32 are supplied with the same pixel signal as subpixels in distant rows, which may result in a visually undesirable displayed image. Therefore, in this embodiment, an example will be described in which the display device 1 outputs pixel signals to subpixels arranged in adjacent rows.

[0251] In this embodiment, the configuration of the display device 1 is the same as that in Fig. 27, and therefore description thereof will be omitted. In this example, the operation in a normal state will be described using a connection configuration of the control lines WSL similar to that of the pixel array unit 11 described in Fig. 20.

[0252] In this example, for each row, two pixels 15 (six sub-pixels) shown in the figure form a repeating unit of the connection configuration, and each sub-pixel is connected to the signal output unit 18 via a signal line SGL in this unit. This connection configuration may also be provided in a part of the pixel array unit 11.

[0253] In the normal state, among the pixels 15 arranged in the Nth row, pixel signals are supplied to the sub-pixels connected to the control line WSL in the Nth row and the sub-pixels connected to the control line WSL in the N+2th row with a delay of two horizontal periods, similar to the operation described in Fig. 20. The operations of the sub-pixels in the N+1th, N+2th, and N+3th rows are the same as those described in Fig. 20.

[0254] FIG. 34 is a diagram for explaining a light emission method during doubler processing in the vertical direction of the pixel array section 11 in the fifth embodiment.

[0255] 34A shows the light emission method during doubler processing in the first frame (first vertical period), and FIG. 34B shows the light emission method during doubler processing in the second frame (second vertical period). The doubler processing in the first frame and the doubler processing in the second frame are alternately performed after these frames.

[0256] In vertical doubling processing, the signal output unit 18 supplies the same pixel signal to the subpixels of the same color connected to the control line WSL in the Nth row and the subpixels connected to the control line WSL in the N+1th row, and supplies the same pixel signal to the subpixels of the same color connected to the control line WSL in the N+2th row and the subpixels of the same color connected to the control line WSL in the N+3th row. If the display device 1 supplies the same pixel signal to the subpixels in the N+1th row and the subpixels in the N+2th row, as shown in the circled portion, the same pixel signal will be supplied to subpixels in distant rows, and the displayed image may not be desirable.

[0257] 34A shows an example of performing vertical doubling processing on pixel signals of an ODD field output from the signal output unit 18 in the first frame, and FIG. 34B shows an example of performing vertical doubling processing on pixel signals of an EVEN field output from the signal output unit 18 in the second frame. As described above, in the pixel array unit 11, two pixels 15 form a repeating unit of the connection configuration of the control lines WSL for each row. This connection configuration may also be provided in a part of the pixel array unit 11.

[0258] The connection configuration of the control lines WSL in the sub-pixels in the Mth to M+5th columns is the same as that in FIG.

[0259] The red subpixel 42, which is arranged in the Nth row and connected to the signal line in the Mth column, is connected to the control line WSL in the Nth row, and the blue subpixel 43'', which is connected to the signal line in the M+1th column, is connected to the control line WSL in the N+2th row.

[0260] Furthermore, the green subpixel 44 arranged in the Nth row and connected to the signal line in the M+2th column is connected to the control line WSL in the Nth row, and the red subpixel 42'' connected to the signal line in the M+3th column is connected to the control line WSL in the N+2th row.

[0261] Furthermore, the blue subpixel 43, which is arranged in the Nth row and connected to the signal line in the (M+4)th column, is connected to the control line WSL in the Nth row, and the green subpixel 44'', which is connected to the signal line in the (M+5)th column, is connected to the control line WSL in the (N+2)th row.

[0262] In addition, the red subpixel 42' arranged in the N+1th row and connected to the signal line in the Mth column is connected to the control line WSL in the N+1th row, and the blue subpixel 43''' connected to the signal line in the M+1th column is connected to the control line WSL in the N+3th row.

[0263] Furthermore, the green sub-pixel 44' arranged in the N+1th row and connected to the signal line in the M+2th column is connected to the control line WSL in the N+1th row, and the red sub-pixel 42''' connected to the signal line in the M+3th column is connected to the control line WSL in the N+3th row.

[0264] Furthermore, the blue subpixel 43' arranged in the N+1th row and connected to the signal line in the M+4th column is connected to the control line WSL in the N+1th row, and the green subpixel 44''' connected to the signal line in the M+5th column is connected to the control line WSL in the N+3th row.

[0265] In addition, the red subpixel 42'' arranged in the N+2th row and connected to the signal line in the Mth column is connected to the control line WSL in the N+2th row, and the blue subpixel 43 connected to the signal line in the M+1th column is connected to the control line WSL in the Nth row.

[0266] Furthermore, the green subpixel 44'' arranged in the N+2th row and connected to the signal line in the M+2th column is connected to the control line WSL in the N+2th row, and the red subpixel 42 connected to the signal line in the M+3th column is connected to the control line WSL in the Nth row.

[0267] Furthermore, the blue subpixel 43'' arranged in the N+2th row and connected to the signal line in the M+4th column is connected to the control line WSL in the N+2th row, and the green subpixel 44 connected to the signal line in the M+5th column is connected to the control line WSL in the Nth row.

[0268] The red subpixel 42''', which is arranged in the N+3 row and connected to the signal line in the Mth column, is connected to the control line WSL in the N+3 row, and the blue subpixel 43', which is connected to the signal line in the M+1th column, is connected to the control line WSL in the N+1th row.

[0269] Furthermore, the green subpixel 44''' arranged in the N+3 row and connected to the signal line in the M+2 column is connected to the control line WSL in the N+3 row, and the red subpixel 42' connected to the signal line in the M+3 column is connected to the control line WSL in the N+1 row.

[0270] Furthermore, the blue sub-pixel 43''', which is arranged in the N+3 row and connected to the signal line in the M+4 column, is connected to the control line WSL in the N+3 row, and the green sub-pixel 44', which is connected to the signal line in the M+5 column, is connected to the control line WSL in the N+1 row.

[0271] For example, as shown in FIG. 34A , during the horizontal period H of the first frame, the signal output unit 18 supplies pixel signals of the ODD field to the red subpixels 42, green subpixels 44, and blue subpixels 43 arranged in the Nth and N+2th rows based on the drive signal output from the control line WSL of the Nth row. At the same timing, the signal output unit 18 supplies pixel signals of the ODD field to the red subpixels 42′, green subpixels 44′, and blue subpixels 43′ arranged in the N+1th and N+3th rows based on the drive signal output from the control line WSL of the N+1th row. In other words, the same ODD field pixel signals are supplied to pixels of the same color arranged in the Nth and N+1th rows. The same ODD field pixel signals are also supplied to pixels of the same color arranged in the N+2th and N+3th rows.

[0272] 34A , the signal output unit 18 supplies pixel signals of the ODD field to the red subpixels 42'', the green subpixels 44'', and the blue subpixels 43'' arranged in the Nth and N+2th rows based on the drive signal output from the control line WSL in the N+2th row at the timing of the horizontal period H+1 of the first frame. Furthermore, the signal output unit 18 supplies pixel signals of the ODD field to the red subpixels 42''', the green subpixels 44''', and the blue subpixels 43''' arranged in the N+1th and N+3th rows based on the drive signal output from the control line WSL in the N+3th row at the same timing.

[0273] 34B , during the horizontal period H of the second frame, the signal output unit 18 supplies even-field pixel signals to the red sub-pixels 42, green sub-pixels 44, and blue sub-pixels 43 arranged in the Nth and N+2th rows based on the drive signal output from the control line WSL of the Nth row. At the same timing, the signal output unit 18 supplies even-field pixel signals to the red sub-pixels 42′, green sub-pixels 44′, and blue sub-pixels 43′ arranged in the N+1th and N+3th rows based on the drive signal output from the control line WSL of the N+1th row. That is, the same even-field pixel signals are supplied to pixels of the same color arranged in the Nth and N+1th rows. The same even-field pixel signals are also supplied to pixels of the same color arranged in the N+2th and N+3th rows.

[0274] 34B , the signal output unit 18 supplies pixel signals to the red subpixels 42'', green subpixels 44'', and blue subpixels 43'' arranged in the Nth and N+2th rows based on the drive signal output from the control line WSL in the N+2th row at the timing of the horizontal period H+1 of the second frame. Furthermore, the signal output unit 18 supplies pixel signals to the red subpixels 42''', green subpixels 44''', and blue subpixels 43''' arranged in the N+1th and N+3th rows based on the drive signal output from the control line WSL in the N+3th row at the same timing.

[0275] Horizontal period H to horizontal period H+1 are examples of the first and second horizontal periods, respectively. The first and second horizontal periods only need to be different on the time axis. The order of the first and second horizontal periods may be reversed on the time axis.

[0276] According to this embodiment, in the display device 1, at least one of the sub-pixels constituting one pixel 15 is connected to a different control line WSL. As a result, the sub-pixels constituting each pixel 15 are not simultaneously written in the same row, and the writing is shifted in horizontal period units, which distributes the voltage variations in the Vth correction voltage Vofs or the write voltage Vsig, making horizontal stripes less visible.

[0277] Furthermore, according to this embodiment, the display device 1 does not experience large fluctuations in luminance even when there are variations in voltage, and can achieve high efficiency.

[0278] Furthermore, according to this embodiment, the display device 1 can perform vertical doubling processing by connecting the sub-pixels that make up each pixel 15 to the control line WSL described above, thereby reducing power consumption.

[0279] Furthermore, according to this embodiment, during vertical doubler processing, the signal output unit 18 supplies the same pixel signal to the sub-pixel connected to the Nth row and the sub-pixel connected to the N+1th row, thereby supplying the same pixel signal to sub-pixels adjacent in the column direction, thereby reducing jerky images displayed.

[0280] Next, application examples of the display systems described in the above embodiments and modifications will be described.

[0281] 35 shows an example of the appearance of a head-mounted display 110. The head-mounted display 110 has, for example, ear hooks 112 for wearing on the user's head on both sides of a glasses-shaped display unit 111. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 110.

[0282] (Application Example 2) FIG. 36 shows an example of the appearance of another head-mounted display 120. The head-mounted display 120 is a see-through head-mounted display having a main body 121, an arm 122, and a lens barrel 123. This head-mounted display 120 is attached to eyeglasses 128. The main body 121 has a control board and a display unit for controlling the operation of the head-mounted display 120. The display unit emits image light of a display image. The arm 122 connects the main body 121 to the lens barrel 123 and supports the lens barrel 123. The lens barrel 123 projects the image light supplied from the main body 121 via the arm 122 toward the user's eyes via lenses 129 of the eyeglasses 128. The techniques according to the above-described embodiments and the like can be applied to such a head-mounted display 120.

[0283] The head-mounted display 120 is a so-called light guide plate type head-mounted display, but is not limited to this and may be, for example, a so-called birdbath type head-mounted display. The birdbath type head-mounted display includes, for example, a beam splitter and a partially transparent mirror. The beam splitter outputs light encoded with image information toward the mirror, and the mirror reflects the light toward the user's eyes. Both the beam splitter and the partially transparent mirror are partially transparent. This allows light from the surrounding environment to reach the user's eyes.

[0284] (Application Example 3) Figures 37A and 37B show an example of the appearance of a digital still camera 130, with Figure 37A showing a front view and Figure 37B showing a rear view. This digital still camera 130 is a single-lens reflex camera with interchangeable lenses and includes a camera body 131, a photographing lens unit 132, a grip 133, a monitor 134, and an electronic viewfinder 135. The photographing lens unit 132 is an interchangeable lens unit and is provided near the center of the front of the camera body 311. The grip 133 is provided on the left side of the front of the camera body 311, and is held by the photographer. The monitor 134 is provided to the left of the center of the back of the camera body 131. The electronic viewfinder 135 is provided above the monitor 134 on the back of the camera body 131. By looking through this electronic viewfinder 135, the photographer can visually confirm the optical image of the subject guided by the photographing lens unit 132 and determine the composition. The techniques according to the above-described embodiments and the like can be applied to the electronic viewfinder 135.

[0285] 38 shows an example of the appearance of a television device 140. The television device 140 has an image display screen unit 141 including a front panel 142 and a filter glass 143. The techniques according to the above-described embodiments and the like can be applied to this image display screen unit 141.

[0286] 39 shows an example of the appearance of a smartphone 150. The smartphone 150 has a display unit 151 that displays various information and an operation unit 152 that includes buttons and the like that accept operation inputs from the user. The techniques according to the above-described embodiments and the like can be applied to this display unit 151.

[0287] (Application Example 6) Figures 40A and 40B show an example configuration of a vehicle to which the technology of the present disclosure is applied, where Figure 40A shows an example of the interior of the vehicle as seen from the rear of vehicle 200, and Figure 40B shows an example of the interior of the vehicle as seen from the left rear of vehicle 200.

[0288] The vehicle in Figures 40A and 40B has a center display 201, a console display 202, a head-up display 203, a digital rearview mirror 204, a steering wheel display 205, and a rear entertainment display 206.

[0289] The center display 201 is disposed on the dashboard 261 in a position facing the driver's seat 262 and the passenger's seat 263. While FIG. 40A illustrates an example of a horizontally elongated center display 201 extending from the driver's seat 262 side to the passenger's seat 263 side, the screen size and location of the center display 201 are not limited to this. The center display 201 can display information detected by various sensors. As a specific example, the center display 201 can display an image captured by an image sensor, a distance image to obstacles in front of or to the side of the vehicle measured by a ToF sensor, and the body temperature of an occupant detected by an infrared sensor. The center display 201 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0290] The safety-related information includes information based on sensor detection results, such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger is abandoned. The operation-related information includes gesture information related to passenger operations detected by sensors. The gestures may include operations of various vehicle equipment, such as air conditioning, navigation, audiovisual (AV) equipment, and lighting. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior. By acquiring and storing the life log, it is possible to determine the condition of the passengers at the time of an accident. The health-related information includes the passenger's body temperature detected using a temperature sensor and information on the passenger's health condition estimated based on the detected body temperature. Alternatively, the passenger's health condition information may be estimated based on the passenger's face captured by an image sensor. Furthermore, the passenger's health condition information may be estimated based on the passenger's responses obtained through an automated voice conversation with the passenger. The authentication / identification-related information includes information on a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes information on AV device operations by occupants detected by the sensor, and information on content to be displayed that is appropriate for the occupants detected and recognized by the sensor.

[0291] The console display 202 can be used to display, for example, life log information. The console display 202 is disposed near a shift lever 265 on a center console 264 between a driver's seat 262 and a passenger seat 263. The console display 202 can also display information detected by various sensors. The console display 202 may also display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0292] The head-up display 203 is virtually displayed behind a windshield 266 in front of the driver's seat 262. The head-up display 203 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 203 is often virtually disposed in front of the driver's seat 262, it is suitable for displaying information directly related to vehicle operation, such as the vehicle speed, the remaining fuel level, and the remaining battery level.

[0293] The digital rearview mirror 204 can not only display the rear of the vehicle, but also display the state of passengers in the rear seats, and can therefore be used to display life log information of passengers in the rear seats, for example.

[0294] The steering wheel display 205 is disposed near the center of the vehicle's steering wheel 267. The steering wheel display 205 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 205 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information related to the operation of AV equipment, air conditioning equipment, etc.

[0295] The rear entertainment display 206 is attached to the rear side of the driver's seat 262 and the passenger seat 263 and is intended for viewing by rear seat passengers. The rear entertainment display 206 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 206 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 206. The rear entertainment display 206 may display, for example, information related to the operation of an AV device or an air conditioning system, or may display the results of measurements such as the body temperature of the rear seat passengers using a temperature sensor.

[0296] The techniques according to the above-described embodiments can be applied to the center display 201, the console display 202, the head-up display 203, the digital rearview mirror 204, the steering wheel display 205, and the rear entertainment display 206.

[0297] (Application Example 7) The liquid crystal projector 300 shown in Figure 41 is a so-called three-panel projector that separates light from a light source into the three primary colors of red, blue, and green and uses one liquid crystal display panel for each color to display a color image. Hereinafter, for convenience, the liquid crystal display panel 10 onto which red light is incident will be referred to as liquid crystal display device 325R, the liquid crystal display panel 10 onto which green light is incident will be referred to as liquid crystal display device 325G, and the liquid crystal display panel 10 onto which blue light is incident will be referred to as liquid crystal display device 325B. The liquid crystal display devices 325R, 325G, and 325B are liquid crystal display panels, and all three have approximately the same structure. These liquid crystal display devices 325R, 325G, and 325B are controlled by a control circuit 220.

[0298] The liquid crystal projector 300 in Figure 41 includes a light source 311 that emits light, a first lens array 312 that is arranged on the side from which the light from the light source 311 exits, a mirror 314 that reflects the light emitted from the first lens array 312 and changes the optical path (optical axis 310) of the emitted light by 90 degrees, and a second lens array 313 onto which the reflected light from the mirror 314 enters.

[0299] Mirror 314 is preferably a fully reflective mirror.

[0300] A plurality of microlenses 312M and 313M are arranged two-dimensionally in the first lens array 312 and the second lens array 313. The first lens array 312 and the second lens array 313 are intended to homogenize the illuminance distribution of light, and have the function of dividing incident light into a plurality of small beams.

[0301] A UV (Ultra Violet) / IR (Infrared) cut filter (not shown) may be installed between the light source 311 and the first lens array 312 .

[0302] The light source 311 emits white light containing red, blue, and green light, which are necessary for color image display. The light source 311 includes a light emitter (not shown) that emits white light, and a reflector that reflects and collects the light emitted from the light emitter.

[0303] The light source may be, for example, an ultra-high pressure mercury lamp, a halogen lamp, a metal halide lamp, or a xenon lamp. The reflector preferably has a shape that provides good light collection efficiency, such as a rotationally symmetric concave shape such as an ellipsoid or a paraboloid. The light source's light emission point is located at the focal point of the concave reflector.

[0304] White light emitted from the light emitter of light source 311 is converted into approximately parallel light by the reflector, passes through first lens array 312, and enters total reflection mirror 314. The white light, whose optical axis 310 has been bent by 90° by total reflection mirror 314, enters second lens array 313.

[0305] The liquid crystal projector 300 illustrated in FIG. 41 has a PS combining element 315 , a condenser lens 316 , and a dichroic mirror 317 on the side where light from the second lens array 313 is emitted.

[0306] The PS combining element 315 has a plurality of retardation plates 315A provided at positions corresponding to the spaces between adjacent microlenses in the second lens array 313. Half-wave plates are an example of the retardation plates 315A.

[0307] The PS combining element 315 separates the incident light into a P-polarized component and an S-polarized component. The PS combining element 315 outputs one of the two separated polarized light components from the polarization conversion element 315 while maintaining its polarization direction (for example, P-polarized component), and converts the other polarized light component (for example, S-polarized component) into the other polarized component (for example, P-polarized component) by the action of the half-wave plate 315A and outputs the converted light.

[0308] The light emitted from the PS combining element 315 is collected by a condenser lens 316 and enters a dichroic mirror 317 .

[0309] The dichroic mirror 317 reflects, for example, red light LR out of the incident light and transmits light of other colors, thereby separating the incident light into red light LR and other colors.

[0310] Furthermore, the liquid crystal projector 300 has, along the optical path of the red light LR color-separated by the dichroic mirror 317, a mirror 318, a field lens 324R, an incident-side polarizer 330I, a liquid crystal display device 325R, and an exit-side polarizer 330S.

[0311] A total reflection mirror is preferably used as the mirror 318. The total reflection mirror 318 reflects the red light LR color-separated by the dichroic mirror 317 toward the incident-side polarizing plate 330I and the liquid crystal display device 325R.

[0312] As described above, incident-side polarizing plate 330I transmits the red light LR incident from total reflection mirror 318 in a direction that coincides with polarization axis 330a.

[0313] The liquid crystal display device 325R spatially modulates the red light LR incident via the incident-side polarizing plate 330I in accordance with the input image data. The exit-side polarizing plate 330S transmits the modulated red light LR from the liquid crystal display panel 325R, but only in a direction that coincides with the polarization axis 330b.

[0314] The liquid crystal projector 300 has a dichroic mirror 319 along the optical path of the light of the other colors color-separated by the dichroic mirror 317. The dichroic mirror 319 color-separates the incident light into green light LG and blue light LB by, for example, reflecting green light LG and transmitting blue light LB of the incident light.

[0315] In the optical path of the green light LG color-separated by the dichroic mirror 319, a field lens 324G, an incident-side polarizing plate 330I, a liquid crystal display panel 325G, and an exit-side polarizing plate 330S are provided.

[0316] The incident-side polarizing plate 330I transmits, of the green light LG incident from the dichroic mirror 319, light in a direction that coincides with the polarization axis 330a.

[0317] The liquid crystal display device 325G spatially modulates the green light LG incident via the incident-side polarizing plate 330I in accordance with input image data.

[0318] The exit-side polarizing plate 330S transmits the modulated green light LG from the liquid crystal display panel 325G, the light of which direction coincides with the polarization axis 330b.

[0319] Furthermore, along the optical path of the blue light LB color-separated by the dichroic mirror 319, there are provided a relay lens 320, a mirror 321, a relay lens 322, a mirror 323, a field lens 324B, an incident-side polarizing plate 330I, a liquid crystal display device 325B, and an exit-side polarizing plate 330S.

[0320] Mirrors 321 and 323 are preferably total reflection mirrors. Total reflection mirror 321 reflects blue light LB incident via relay lens 320 toward total reflection mirror 323. Total reflection mirror 323 reflects blue light LB, which has been reflected by total reflection mirror 321 and incident via relay lens 322, toward incident-side polarizing plate 330I and liquid crystal display panel 325B.

[0321] The incident-side polarizing plate 330I transmits the green light LG incident from the total reflection mirror 323, the light having a direction that coincides with the polarization axis 330a.

[0322] Liquid crystal display device 325B spatially modulates blue light LB that has been reflected by total reflection mirror 323 and has entered through field lens 324B and incident-side polarizing plate 330I, in accordance with input image data.

[0323] The exit-side polarizing plate 330S transmits the modulated blue light LB from the liquid crystal display panel 325B, but only in a direction that coincides with the polarization axis 330b. At the position where the optical paths of the red light LR, the green light LG, and the blue light LB intersect, a cross prism 326 is installed, which has the function of combining these three colored lights.

[0324] As an example, the cross prism 326 is constructed by joining four right-angle prisms, each having an entrance surface 326R, 326G, 326B onto which the red light LR, the green light LG, and the blue light LB are respectively incident, and an exit surface 326T from which the light synthesized from the red light LR, the green light LG, and the blue light LB exits.

[0325] In the liquid crystal projector 300, a dichroic film is coated on the joint surface of each rectangular prism so that the green light LG incident on the cross prism 326 is transmitted toward the exit surface 326T side, and the red light LR and blue light LB incident on the cross prism 326 are reflected toward the exit surface 326T side.

[0326] As described above, the cross prism 326 combines the three colored lights incident on the entrance surfaces 326R, 326G, and 326B, and emits the combined light from the exit surface 326T.

[0327] The liquid crystal projector 300 also has a projection lens 327 for projecting the combined light emitted from the cross prism 326 onto a screen 328. The projection lens 327 preferably comprises a plurality of lenses, and has a zoom function for adjusting the size of the image projected onto the screen 328 and a focusing function.

[0328] The present disclosure has been described above by way of embodiments, their modifications, application examples, and applied examples. However, the present disclosure is not limited to the above-described embodiments, etc., and various modifications are possible. Note that the effects described in this specification are merely examples. The effects of the present disclosure are not limited to the effects described in this specification. The present disclosure may have effects other than those described in this specification.

[0329] Furthermore, for example, the present disclosure can be configured as follows.

[0330] (1) A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in a row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels; and a plurality of signal lines extending in a column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to the scanning line different from the scanning line to which the other subpixels are connected.

[0331] (2) The display device according to (1), wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.

[0332] (3) The display device according to (1), wherein the first to third subpixels included in the pixel are connected to the scanning line different from the scanning line to which subpixels of the same color included in the pixel adjacent in the row direction are connected.

[0333] (4) The display device according to (3), wherein the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+5th signal lines (M is an integer of 1 or more), the first subpixel arranged in the Nth row and connected to the Mth signal line and the second subpixel connected to the M+2th signal line are connected to the Nth scan line, the third subpixel arranged in the Nth row and connected to the M+1th signal line are connected to the N+1th scan line, the first subpixel arranged in the Nth row and connected to the M+3rd signal line and the second subpixel connected to the M+5th signal line are connected to the N+1th scan line, and the third subpixel arranged in the Nth row and connected to the M+4th signal line is connected to the Nth scan line.

[0334] (5) The display device according to (4), wherein the first subpixel arranged in the N+1th row and connected to the M signal line and the second subpixel connected to the M+2th signal line are connected to the N+1th scanning line; the third subpixel arranged in the N+1th row and connected to the M+1th signal line are connected to the Nth scanning line; the first subpixel arranged in the N+1th row and connected to the M+3rd signal line and the second subpixel connected to the M+5th signal line are connected to the Nth scanning line; and the third subpixel arranged in the N+1th row and connected to the M+4th signal line are connected to the N+1th scanning line.

[0335] (6) The display device according to (3), wherein the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+2th signal lines (M is an integer of 1 or more), the first subpixel arranged in the Nth row and connected to the Mth signal line and the second subpixel connected to the M+2th signal line are connected to the Nth scan line, the third subpixel arranged in the Nth row and connected to the M+1th signal line are connected to the N+2nd scan line, the first subpixel arranged in the N+2th row and connected to the Mth signal line and the second subpixel connected to the M+2nd signal line are connected to the N+2nd scan line, and the third subpixel arranged in the N+2th row and connected to the M+1st signal line is connected to the Nth scan line.

[0336] (7) The display device according to (6), wherein the plurality of signal lines further include M+3 to M+5 signal lines (M is an integer of 1 or more), and the first subpixel arranged in an Nth row and connected to the M+3 signal line and the second subpixel connected to the M+5 signal line are connected to an N+2 scan line, the third subpixel arranged in an Nth row and connected to the M+4 signal line are connected to the N scan line, the first subpixel arranged in an N+2 row and connected to the M+3 signal line and the second subpixel connected to the M+5 signal line are connected to the N scan line, and the third subpixel arranged in an N+2 row and connected to the M+4 signal line is connected to the N+2 scan line.

[0337] (8) The display device according to (1), wherein each pixel further includes a fourth subpixel, the first subpixel being a red subpixel, the second subpixel being a green subpixel, the third subpixel being a blue subpixel, and the fourth subpixel being a white subpixel.

[0338] (9) The display device according to (8), wherein, of the first to fourth subpixels, the third subpixel and the fourth subpixel are connected to the scanning line different from the scanning line to which the first subpixel and the second subpixel are connected.

[0339] (10) The display device according to (1), wherein each pixel further includes a fourth subpixel, wherein the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), wherein the plurality of signal lines include Mth to M+3th signal lines (M is an integer of 1 or more), wherein the fourth subpixel arranged in the Nth row and connected to the Mth signal line and the third subpixel connected to the M+2th signal line are connected to the Nth scan line, wherein the first subpixel arranged in the Nth row and connected to the M+1th signal line and the second subpixel connected to the M+3rd signal line are connected to the N+2nd scan line, wherein the fourth subpixel arranged in the Nth row and connected to the Mth signal line and the third subpixel connected to the M+2nd signal line are connected to the N+2nd scan line, and wherein the first subpixel arranged in the Nth row and connected to the M+1st signal line and the second subpixel connected to the M+3rd signal line are connected to the Nth scan line.

[0340] (11) The display device according to (10), wherein the plurality of signal lines further include M+4th to M+7th signal lines (N is an integer of 1 or more), and the fourth subpixel arranged in an Nth row and connected to the M+4th signal line and the third subpixel connected to the M+6th signal line are connected to the N+2nd scanning line, the first subpixel arranged in an Nth row and connected to the M+5th signal line and the second subpixel connected to the M+7th signal line are connected to the Nth scanning line, the fourth subpixel arranged in an N+2nd row and connected to the M+4th signal line and the third subpixel connected to the M+6th signal line are connected to the Nth scanning line, and the first subpixel arranged in an N+2nd row and connected to the M+5th signal line and the second subpixel connected to the M+7th signal line are connected to the Nth scanning line.

[0341] (12) A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in a row direction of the pixel array section and supplying drive signals to the first to third subpixels; a first group of signal lines extending in a column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a predetermined column; a second group of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a column different from the predetermined column; and a plurality of switches switching electrical connections between the first group of signal lines and the second group of signal lines, wherein at least one of the subpixels arranged in each row is connected to the scanning line different from the scanning line to which the other subpixels are connected.

[0342] (13) The display device according to (12), wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.

[0343] (14) The display device according to (12), wherein the first group of signal lines includes M to M+2 signal lines and M+6 to M+8 signal lines (N is an integer of 1 or more), the second group of signal lines includes M+3 to M+5 signal lines and M+9 to M+11 signal lines (M is an integer of 1 or more), the first subpixels are connected to the M signal line and the M+3 signal line and the M+6 signal line and the M+9 signal line by conduction of the switches, the third subpixels are connected to the M+1 signal line and the M+4 signal line and the M+7 signal line and the M+10 signal line by conduction of the switches, and the second subpixels are connected to the M+2 signal line and the M+5 signal line and the M+8 signal line and the M+11 signal line by conduction of the switches.

[0344] (15) The plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), and each of the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the M+3rd signal line is connected to the Nth scan line, each of the third sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the second sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the third sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, and each of the second sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line. (14) A display device according to (14).

[0345] (16) The plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), and the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the M+3rd signal line are connected to the Nth scanning line, the third sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth signal line, the second sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth signal line, the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth signal line, the first sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth scanning line, the third sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth scanning line, and the second sub-pixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line are connected to the Nth scanning line. (14) A display device according to (14).

[0346] (17) A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in a row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels; and a plurality of signal lines extending in a column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to a scanning line different from the scanning line to which the other subpixels are connected; and a plurality of sets of scanning lines, each set consisting of two of the plurality of scanning lines, supply the drive signals in each horizontal period.

[0347] (18) The plurality of scanning lines include Nth to N+4th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+2nd signal lines (M is an integer of 1 or more), and the pixel signal is supplied to the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1th scanning line, and the first sub-pixel arranged in the N+2th row and connected to the Mth signal line, during a first horizontal period; the pixel signal is supplied to the second sub-pixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1st scanning line, and the second sub-pixel arranged in the N+2th row and connected to the M+2nd signal line and the N+2nd scanning line, during the first horizontal period; the pixel signal is supplied to the third sub-pixel arranged in the Nth row and connected to the M+1st signal line and the N+1st scanning line, and the third sub-pixel arranged in the N+3th row and connected to the M+1st signal line and the N+2nd scanning line, during the first horizontal period; the pixel signal is supplied in a second horizontal period to the first subpixel arranged in the N+3 row and connected to the M signal line and the N+3 scanning line, and the first subpixel arranged in the N+4 row and connected to the M signal line and the N+4 scanning line; the pixel signal is supplied in the second horizontal period to the second subpixel arranged in the N+3 row and connected to the M+2 signal line and the N+3 scanning line, and the second subpixel arranged in the N+4 row and connected to the M+2 signal line and the N+4 scanning line; and the pixel signal is supplied in the second horizontal period to the third subpixel arranged in the N+2 row and connected to the M+1 signal line and the N+3 scanning line, and the third subpixel arranged in the N+5 row and connected to the M+1 signal line and the N+4 scanning line.

[0348] (19) The plurality of scanning lines include Nth to N+3th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+5th signal lines (N is an integer of 1 or more), and the pixel signal of a first field is supplied to the first sub-pixel arranged in the Nth row and connected to the Mth signal line and the Nth scanning line, and the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1th scanning line, during a first horizontal period of a first vertical period, and the pixel signal of the first field is supplied to the third sub-pixel arranged in the Nth row and connected to the M+1th signal line and the N+2th scanning line, and the third sub-pixel arranged in the N+1th row and connected to the M+1st signal line and the N+3th scanning line, during a second horizontal period of the first vertical period, The display device according to (17), wherein the pixel signal of the first field is supplied to the second sub-pixel arranged in the Nth row and connected to the M+2 signal line and the N scanning line, and the second sub-pixel arranged in the N+1th row and connected to the M+2 signal line and the N+1 scanning line, during the first horizontal period of the first vertical period.

[0349] (20) The display device according to (19), wherein the pixel signal of the second field is supplied to the first subpixel arranged in the Nth row and connected to the M signal line and the N scan line, and the first subpixel arranged in the N+1th row and connected to the M signal line and the N+1th scan line, during a first horizontal period of a second vertical period; the pixel signal of the second field is supplied to the third subpixel arranged in the Nth row and connected to the M+1th signal line and the N+2th scan line, and the third subpixel arranged in the N+1th row and connected to the M+1st signal line and the N+3th scan line, during a second horizontal period of the second vertical period; and the pixel signal of the second field is supplied to the second subpixel arranged in the Nth row and connected to the M+2nd signal line and the N scan line, and the second subpixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1th scan line, during the first horizontal period of the second vertical period.

[0350] 1: Display device, 2: Display system, 3: Display controller, 4: Timing controller, 5: Data input / output I / F unit, 11: Pixel array unit, 12: V-DRV unit, 13: H-DRV unit 13, 14: Signal processing unit, 15: Pixel, 16: Write scanning unit, 17: Drive scanning unit, 18: Signal output unit, 19 First signal output unit, 20 Second signal output unit, 21: HLOGIC unit, 22 VLOGIC unit, 23: Clock generator, 24: Timing generator, 25: Image processing unit, 31: Image I / F unit 31, 32: Data S / P unit, 33: Clock control unit 33, 34: H / V synchronization unit, 42: Red subpixel, 42': Red subpixel, 42'': Red subpixel, 42''': Red subpixel, 43: Blue subpixel, 43': Blue subpixel, 43": blue subpixel, 43'": blue subpixel, 44: green subpixel, 44': green subpixel, 44": green subpixel, 44'": green subpixel, 45: white subpixel, 45': white subpixel, 45": white subpixel, 45'": white subpixel, 46: switch, 110: head mounted display, 111: display unit, 112: ear hook unit, 120: head mounted display, 121: main body unit, 122: arm unit, 123: lens barrel unit 123, 128: glasses, 129: lens, 130: digital still camera, 131: camera main body unit, 132: photographing lens unit, 133: grip unit, 134: monitor, 135: electronic viewfinder, 140: television device, 141: video display screen unit, 142: front panel, 143: filter glass, 150: smartphone, 151: display unit, 152: operation unit, 200: vehicle, 201: center display, 202: console display, 203: head-up display, 204: digital rearview mirror, 205: steering wheel display, 206: rear entertainment display, 261: dashboard, 262: driver's seat, 263: passenger seat, 264: center console, 265: shift lever, 266: windshield, 267: steering wheel

Claims

1. A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels; and a plurality of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to a scanning line that is different from the scanning lines to which the other subpixels are connected.

2. The display device according to claim 1, wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.

3. The display device according to claim 1, wherein the first to third subpixels included in the pixel are connected to the scanning line different from the subpixels of the same color included in the pixel adjacent in the row direction.

4. The display device according to claim 3, wherein the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+5th signal lines (M is an integer of 1 or more), the first subpixel arranged in the Nth row and connected to the Mth signal line and the second subpixel connected to the M+2th signal line are connected to the Nth scan line, the third subpixel arranged in the Nth row and connected to the M+1st signal line are connected to the N+1th scan line, the first subpixel arranged in the Nth row and connected to the M+3rd signal line and the second subpixel connected to the M+5th signal line are connected to the N+1st scan line, and the third subpixel arranged in the Nth row and connected to the M+4th signal line is connected to the Nth scan line.

5. The display device according to claim 4, wherein the first subpixel arranged in the N+1th row and connected to the M signal line and the second subpixel connected to the M+2th signal line are connected to the N+1th scanning line; the third subpixel arranged in the N+1th row and connected to the M+1th signal line is connected to the Nth scanning line; the first subpixel arranged in the N+1th row and connected to the M+3rd signal line and the second subpixel connected to the M+5th signal line are connected to the Nth scanning line; and the third subpixel arranged in the N+1th row and connected to the M+4th signal line is connected to the N+1th scanning line.

6. The display device according to claim 3, wherein the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+2th signal lines (M is an integer of 1 or more), the first sub-pixel arranged in the Nth row and connected to the Mth signal line and the second sub-pixel connected to the M+2th signal line are connected to the Nth scan line, the third sub-pixel arranged in the Nth row and connected to the M+1th signal line are connected to the N+2nd scan line, the first sub-pixel arranged in the N+2th row and connected to the Mth signal line and the second sub-pixel connected to the M+2nd signal line are connected to the N+2nd scan line, and the third sub-pixel arranged in the N+2th row and connected to the M+1st signal line is connected to the Nth scan line.

7. The display device according to claim 6, wherein the plurality of signal lines further include M+3 to M+5 signal lines (M is an integer of 1 or more), wherein the first subpixel arranged in the Nth row and connected to the M+3 signal line and the second subpixel connected to the M+5 signal line are connected to the N+2 scan line, the third subpixel arranged in the Nth row and connected to the M+4 signal line is connected to the N scan line, the first subpixel arranged in the N+2 row and connected to the M+3 signal line and the second subpixel connected to the M+5 signal line are connected to the N scan line, and the third subpixel arranged in the N+2 row and connected to the M+4 signal line is connected to the N+2 scan line.

8. The display device of claim 1, wherein each pixel further includes a fourth subpixel, wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, the third subpixel is a blue subpixel, and the fourth subpixel is a white subpixel.

9. The display device according to claim 8, wherein, of the first to fourth subpixels, the third subpixel and the fourth subpixel are connected to a scanning line different from that to which the first subpixel and the second subpixel are connected.

10. The display device according to claim 1, wherein each pixel further includes a fourth subpixel, the plurality of scanning lines include Nth to N+2th scanning lines (N is an integer of 1 or more), the plurality of signal lines include Mth to M+3th signal lines (M is an integer of 1 or more), the fourth subpixel arranged in the Nth row and connected to the Mth signal line and the third subpixel connected to the M+2nd signal line are connected to the Nth scan line, the first subpixel arranged in the Nth row and connected to the M+1st signal line and the second subpixel connected to the M+3rd signal line are connected to the N+2nd scan line, the fourth subpixel arranged in the N+2nd row and connected to the Mth signal line and the third subpixel connected to the M+2nd signal line are connected to the N+2nd scan line, and the first subpixel arranged in the N+2nd row and connected to the M+1st signal line and the second subpixel connected to the M+3rd signal line are connected to the Nth scan line.

11. The display device according to claim 10, wherein the plurality of signal lines further include M+4th to M+7th signal lines (N is an integer of 1 or more), wherein the fourth subpixel arranged in the Nth row and connected to the M+4th signal line and the third subpixel connected to the M+6th signal line are connected to the N+2nd scanning line, the first subpixel arranged in the Nth row and connected to the M+5th signal line and the second subpixel connected to the M+7th signal line are connected to the Nth scanning line, the fourth subpixel arranged in the N+2nd row and connected to the M+4th signal line and the third subpixel connected to the M+6th signal line are connected to the Nth scanning line, and the first subpixel arranged in the N+2nd row and connected to the M+5th signal line and the second subpixel connected to the M+7th signal line are connected to the N+2nd scanning line.

12. A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the first to third subpixels; a first group of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a predetermined column; a second group of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the first to third subpixels arranged in a column different from the predetermined column; and a plurality of switches for switching the electrical connections of the first group of signal lines and the second group of signal lines, wherein at least one subpixel arranged in each row is connected to a scanning line different from the scanning line to which the other subpixels are connected.

13. The display device of claim 12, wherein the first subpixel is a red subpixel, the second subpixel is a green subpixel, and the third subpixel is a blue subpixel.

14. The display device according to claim 12, wherein the first group of signal lines includes Mth to M+2th signal lines and M+6th to M+8th signal lines (N is an integer of 1 or more), the second group of signal lines includes M+3rd to M+5th signal lines and M+9th to M+11th signal lines (M is an integer of 1 or more), the first subpixel is connected to the Mth signal line and the M+3rd signal line and the M+6th signal line and the M+9th signal line when the switch is conductive, the third subpixel is connected to the M+1st signal line and the M+4th signal line and the M+7th signal line and the M+10th signal line when the switch is conductive, and the second subpixel is connected to the M+2nd signal line and the M+5th signal line and the M+8th signal line and the M+11th signal line when the switch is conductive.

15. The display device according to claim 14, wherein the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer greater than or equal to 1), and wherein each of the first subpixels arranged in the Nth row and connected to the Mth signal line and the M+3rd signal line is connected to the Nth scan line, each of the third subpixels arranged in the Nth row and connected to the Mth signal line and the M+4th signal line is connected to the Nth scan line, each of the second subpixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the first subpixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the first subpixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, each of the third subpixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line, and each of the second subpixels arranged in the Nth row and connected to the Mth signal line and the Mth signal line is connected to the Nth scan line.

16. The display device according to claim 14, wherein the plurality of scanning lines include Nth to N+1th scanning lines (N is an integer greater than or equal to 1), and wherein each of the first subpixels arranged in the Nth row and connected to the Mth signal line and the M+3rd signal line is connected to the Nth scan line, each of the third subpixels arranged in the Nth row and connected to the M+1st signal line and the M+4th signal line is connected to the Nth scan line, each of the second subpixels arranged in the Nth row and connected to the M+2nd signal line and the M+5th signal line is connected to the Nth scan line, each of the first subpixels arranged in the Nth row and connected to the M+6th signal line and the M+9th signal line is connected to the N+1st scan line, each of the third subpixels arranged in the Nth row and connected to the M+7th signal line and the M+10th signal line is connected to the N+1st scan line, and each of the second subpixels arranged in the Nth row and connected to the M+8th signal line and the M+11th signal line is connected to the N+1st scan line.

17. A display device comprising: a pixel array section in which a plurality of pixels, each including a first subpixel, a second subpixel, and a third subpixel having different colors, are arranged in a matrix; a plurality of scanning lines extending in the row direction of the pixel array section and supplying drive signals to the plurality of first to third subpixels; and a plurality of signal lines extending in the column direction of the pixel array section and supplying pixel signals to the plurality of first to third subpixels, wherein at least one of the subpixels arranged in each row is connected to a scanning line different from the scanning lines to which the other subpixels are connected, and a plurality of sets of scanning lines, each set consisting of two of the plurality of scanning lines, supply the drive signals in each horizontal period.

18. The plurality of scanning lines include Nth to N+4th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+2nd signal lines (M is an integer of 1 or more), and the pixel signal is supplied to the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1st scanning line, and the first sub-pixel arranged in the N+2th row and connected to the Mth signal line, during a first horizontal period; the pixel signal is supplied to the second sub-pixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1st scanning line, and the second sub-pixel arranged in the N+2th row and connected to the M+2nd signal line and the N+2nd scanning line, during the first horizontal period; the pixel signal is supplied to the third sub-pixel arranged in the Nth row and connected to the M+1st signal line and the N+1st scanning line, and the third sub-pixel arranged in the N+3th row and connected to the M+1st signal line and the N+2nd scanning line, during the first horizontal period; 18. The display device according to claim 17, wherein the pixel signal is supplied to the first subpixel arranged in the N+3 row and connected to the M signal line and the N+3 scanning line, and the first subpixel arranged in the N+4 row and connected to the M signal line and the N+4 scanning line, during a second horizontal period; the pixel signal is supplied to the second subpixel arranged in the N+3 row and connected to the M+2 signal line and the N+3 scanning line, and the second subpixel arranged in the N+4 row and connected to the M+2 signal line and the N+4 scanning line, during the second horizontal period; and the pixel signal is supplied to the third subpixel arranged in the N+2 row and connected to the M+1 signal line and the N+3 scanning line, and the third subpixel arranged in the N+5 row and connected to the M+1 signal line and the N+4 scanning line, during the second horizontal period.

19. The plurality of scanning lines include Nth to N+3th scanning lines (N is an integer of 1 or more), and the plurality of signal lines include Mth to M+5th signal lines (N is an integer of 1 or more), and the pixel signal of a first field is supplied to the first sub-pixel arranged in the Nth row and connected to the Mth signal line and the Nth scanning line, and the first sub-pixel arranged in the N+1th row and connected to the Mth signal line and the N+1th scanning line, during a first horizontal period of a first vertical period, and the pixel signal of the first field is supplied to the third sub-pixel arranged in the Nth row and connected to the M+1st signal line and the N+2th scanning line, and the third sub-pixel arranged in the N+1th row and connected to the M+1st signal line and the N+3th scanning line, during a second horizontal period of the first vertical period, 18. The display device according to claim 17, wherein the pixel signal of the first field is supplied to the second sub-pixel arranged in an Nth row and connected to the (M+2) signal line and the (N+1) scanning line, and the second sub-pixel arranged in an (N+1)th row and connected to the (M+2) signal line and the (N+1) scanning line, during the first horizontal period of the first vertical period.

20. The display device according to claim 19, wherein the pixel signal of the second field is supplied to the first subpixel arranged in the Nth row and connected to the M signal line and the N scan line, and the first subpixel arranged in the N+1th row and connected to the M signal line and the N+1th scan line, during a first horizontal period of a second vertical period; the pixel signal of the second field is supplied to the third subpixel arranged in the Nth row and connected to the M+1th signal line and the N+2th scan line, and the third subpixel arranged in the N+1th row and connected to the M+1st signal line and the N+3th scan line, during a second horizontal period of the second vertical period; and the pixel signal of the second field is supplied to the second subpixel arranged in the Nth row and connected to the M+2nd signal line and the N scan line, and the second subpixel arranged in the N+1th row and connected to the M+2nd signal line and the N+1th scan line, during the first horizontal period of the second vertical period.

Images