Tile computing system and tile chip node therefor

Abstract

The present invention relates to: a tile computing system and a tile chip node therefor, the tile computing system interconnecting a plurality of tile chip nodes so that it is unnecessary to add a connection with a new tile chip node to a host node even if the new tile chip node is connected, thereby enabling modularity and expandability to be improved, wherein the host node is connected to at least one tile chip node from among the plurality of tile chip nodes and includes a communication interface for performing communication with the connected tile chip node, each of the plurality of tile chip nodes includes a communication interface for one-to-one communication with each other in the four directions of up, down, left and right, and the communication interface of each of the plurality of tile chip nodes performs communication by using an index, which is location information for each tile chip node allocated by the host node.

Description

Tile computing system and tile chip node therefor

[0001] The present invention relates to a tile computing system, which has improved modularity and expandability by interconnecting a plurality of tile chip nodes, and a tile chip node therefor.

[0002] Deep learning technology is a very important element in AI, and hardware accelerators are being applied to process the massive amount of data generated by deep learning technology. However, there is a problem in that it is difficult to apply in edge device environments.

[0003] Here, edge devices include devices such as intelligent IoT, smartphones, and autonomous driving devices. The types of lightweight deep learning models for these edge devices are continuously increasing, and it is difficult to develop an artificial intelligence hardware accelerator suitable for each deep learning model.

[0004] Accordingly, a technology has been introduced recently to improve data reuse by introducing a tile computing system based on a large-scale parallel structure, which processes detailed tasks through tile chip nodes, which are each tile processing devices.

[0005] However, the SPI (Serial Peripheral Interface) communication system applied to embedded systems such as artificial intelligence hardware accelerators to date has the problem that multiple slave chips are each connected to a single host, making mutual communication between multiple slave chips impossible and making it difficult to expand new slave chips, making it difficult to apply to tile computing systems based on parallel structures.

[0006] [Patent Document]

[0007] Korean Patent No. 10-2262463, registered on June 2, 2021 (Title: Large-scale sensor data collection device and method for a sensor mat for people counting)

[0008] The technical problem of the present invention is proposed to solve such problems, and the purpose is to provide a tile computing system with improved modularity and expandability by interconnecting a plurality of tile chip nodes, and a tile chip node therefor.

[0009] In particular, the present invention aims to provide a tile computing system and a tile chip node therefor with improved modularity and expandability by supporting communication between tile chip nodes through a communication interface capable of communication based on an index included in each tile chip node.

[0010] However, the purpose of the present invention is not limited to the above purpose, and other purposes not mentioned can be clearly understood from the description below.

[0011] In order to achieve the above-described object, according to an embodiment of the present invention, a tile computing system including a host node and a plurality of tile chip nodes interconnected in a tree structure, wherein the host node is connected to at least one tile chip node among the plurality of tile chip nodes and includes a communication interface for performing communication with the connected tile chip node, and each of the plurality of tile chip nodes includes a communication interface for one-to-one communication in four directions: up, down, left, and right, and the communication interface of each of the plurality of tile chip nodes can perform communication using an index, which is location information for each tile chip node allocated by the host node.

[0012] At this time, the host node includes a first communication interface and a second communication interface in the opposite direction of the first communication interface, and a first tile chip node connected to the first communication interface and a second tile chip node connected to the second communication interface can perform one-to-one communication, respectively.

[0013] At this time, the host node can determine, based on its own location, whether the connected first depth tile chip node is connected to the first communication interface located in one direction or the second communication interface located in the opposite direction of the one direction, and assign an even or odd index corresponding to the first communication interface or the second communication interface to the connected first depth tile chip node.

[0014] At this time, each of the plurality of tile chip nodes is interconnected in a ternary tree structure including three child nodes, and the host node can sequentially assign an index that increases in consideration of the number of child nodes and the direction of the tile chip node based on an even or odd index assigned to the tile chip node of the first depth to each of the tile chip nodes of the second depth having the tile chip node of the first depth as a parent node.

[0015] At this time, the host node can sequentially assign an index that increases in the left, upper, and right directions of the tile chip node based on its own position.

[0016] Each of the above tile chip nodes can check an index included in data transmitted through the communication interface, and if the data is not transmitted to itself, can check a transmission path for the index using a predefined index search algorithm, and transmit the data to a connected tile chip node corresponding to the confirmed transmission path.

[0017] At this time, the tile chip node that receives data through the communication interface, if the data is not transmitted to itself, checks the index assigned to itself, and if the assigned index is even, subtracts the even-numbered identification index from the index included in the data, divides it by the number of child nodes parameter, and performs a search according to a predefined index search algorithm until the index included in the data becomes the index value of the first depth, thereby confirming the transmission path; if the assigned index is odd, subtracts the odd-numbered identification index from the index included in the data, divides it by the number of child nodes parameter, and performs a search according to a predefined index search algorithm until the index included in the data becomes the index value of the first depth, thereby confirming the transmission path.

[0018] In order to achieve the above-described purpose, in accordance with an embodiment of the present invention, a host node and a plurality of tile chip nodes interconnected to the host node in a tree structure, each of the plurality of tile chip nodes includes a communication interface for one-to-one communication in four directions: up, down, left, and right, and the communication interface includes a data communication line and a CS communication line, and when the CS communication line is in a low signal state, data is transmitted and received through the data communication line, and the transmitted and received data may include an index, which is location information for each tile chip node allocated by the host node.

[0019] At this time, the command includes a buffer-related command, and the buffer-related command may include the same maximum number of bytes and buffer size for managing memory access in the host node.

[0020] At this time, the clock (CLK) speed of the communication interface may be slower than the memory data transfer speed of the host node.

[0021] At this time, the index may include a starting index, which is location information of the starting node, and a destination index, which is location information of the destination node.

[0022] At this time, the communication interface may include a decoding circuit for searching a transmission path for the index using a predefined index search algorithm.

[0023] According to the tile computing system of the present invention and the tile chip node therefor, by interconnecting a plurality of tile chip nodes, even if a new tile chip node is connected, there is no need to add a connection to the host node with a new tile chip node, so modularity and expandability can be improved.

[0024] In addition, the present invention supports communication between tile chip nodes through a communication interface capable of communication based on an index included in each tile chip node, so that each tile chip node can actively identify its own location, and when the transmitted data is not data transmitted to itself, it can confirm the transmission direction using the index and transmit data corresponding to the confirmed transmission direction.

[0025] In addition, various effects other than the above-described effects may be disclosed directly or implicitly in the detailed description according to the embodiments of the present invention to be described later.

[0026] Figure 1 is a drawing for explaining an SPI communication system according to the prior art.

[0027] FIG. 2 is an exemplary diagram illustrating a tile computing system according to an embodiment of the present invention.

[0028] FIG. 3 is an exemplary diagram for explaining a communication method in a tile computing system according to an embodiment of the present invention.

[0029] FIG. 4 is an exemplary diagram for explaining TSPI according to an embodiment of the present invention.

[0030] FIG. 5 is a diagram illustrating a tile computing system of various structures according to an embodiment of the present invention.

[0031] FIG. 6 is a diagram illustrating the main configuration of a host node according to an embodiment of the present invention.

[0032] FIG. 7 is an exemplary diagram illustrating memory management in a host node according to an embodiment of the present invention.

[0033] FIG. 8 and FIG. 9 are diagrams for explaining a process of allocating an index in a host node according to an embodiment of the present invention.

[0034] FIG. 10 and FIG. 11 are diagrams for explaining an index search process according to an embodiment of the present invention.

[0035] In order to more clearly explain the features and advantages of the problem-solving means of the present invention, the present invention will be described in more detail with reference to specific embodiments of the present invention illustrated in the attached drawings.

[0036] However, detailed descriptions of known functions or components that may obscure the gist of the present invention in the following description and attached drawings are omitted. It should also be noted that, where possible, identical components are indicated with identical reference numerals throughout the drawings.

[0037] The terms and words used in the following description and drawings should not be interpreted as limited to their conventional or dictionary meanings, but should be interpreted with meanings and concepts that conform to the technical idea of ​​the present invention based on the principle that the inventor can appropriately define the concept of the term to best describe his or her invention. Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical idea of ​​the present invention. Therefore, it should be understood that there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0038] Additionally, terms containing ordinal numbers, such as "first," "second," etc., are used to describe various components, and are only used to distinguish one component from another, not to limit said components. For example, without departing from the scope of the present invention, a second component could be referred to as a "first component," and similarly, a first component could also be referred to as a "second component."

[0039] Additionally, when a component is referred to as being "connected" or "connected" to another component, this means that the component can be connected or connected logically or physically. In other words, while a component may be directly connected or connected to another component, it should be understood that other components may exist in between, and that the component may be connected or connected indirectly.

[0040] In addition, the terminology used in this specification is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In addition, it should be understood that the terms "comprises" or "has" described in this specification are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0041] Now, before describing a tile computing system and a tile chip node therefor according to an embodiment of the present invention, a conventional SPI (Serial Peripheral Interface) communication system will first be described.

[0042] Figure 1 is a drawing for explaining an SPI communication system according to the prior art.

[0043] In Fig. 1, an SPI (Serial Peripheral Interface, hereinafter referred to as SPI) communication system used in an embedded system such as a conventional artificial intelligence hardware accelerator is configured to include one host SPI (10) and multiple slave SPIs (20). Communication between the host SPI (10) and multiple slave SPIs (20) is performed through the SPI, and the SPI includes a data communication line and a CS communication line. In the drawing, the data communication line is indicated by a solid line, and the CS (Chip Select) communication line is indicated by a dotted line, and a serial clock (SCK), master output, slave input (MOSI), and master input-slave output (MISO) can be designated and used through the data communication line.

[0044] In the SPI communication system of the prior art, in order for the host SPI (10) to select one slave SPI among a plurality of slave SPIs (2), for example, the first slave SPI (21), the CS signal of the first slave SPI (21) connected to the SPI is output as a LOW signal to activate the first slave SPI (21), and then data is transmitted and received through the MOSI, MISO pins, etc. while the CS signal is in a LOW signal state. At this time, the data transmitted and received includes a command and data.

[0045] In this conventional SPI system, the host SPI (10) can only perform one-to-one communication between the host SPI (10) and the slave SPI (20), and direct one-to-one communication between the slave SPIs (20) is not possible. Even when data is to be transmitted from the first slave SPI (21) to the second slave SPI (22), it must pass through the root node, the host SPI (10). Therefore, since the currents of all data lines cross, unnecessary switching may continuously occur, which increases current consumption. In addition, since a new CS communication line must be newly connected every time a new slave SPI (20) is added, there is a problem that the I / O power consumption increases rapidly when it is to be applied to a tile computing system based on a parallel structure.

[0046] Accordingly, the present invention proposes a new communication interface that can operate more effectively in a parallel structure-based tile computing system by improving the SPI.

[0047] Hereinafter, for convenience of explanation, the novel communication interface proposed in the present invention will be referred to as TSPI (Tile Chip Serial Peripheral Interface). Unlike the conventional SPI, TSPI is an interface that performs mutual communication based on an index. It is a communication interface that can greatly increase the scalability of nodes because it does not require individual CS communication lines for each node to be connected to the host node.

[0048] In addition, each node connected to the host node of the present invention is an independent node capable of communicating with each other, and is named a tile chip node to distinguish it from the slave node of the conventional SPI.

[0049] Hereinafter, a tile computing system including a TSPI according to an embodiment of the present invention and a tile chip node therefor will be described in more detail.

[0050] FIG. 2 is an exemplary diagram for explaining a tile computing system according to an embodiment of the present invention, FIG. 3 is an exemplary diagram for explaining a communication method in a tile computing system according to an embodiment of the present invention, FIG. 4 is an exemplary diagram for explaining TSPI according to an embodiment of the present invention, and FIG. 5 is a diagram illustrating tile computing systems of various structures according to an embodiment of the present invention.

[0051] First, referring to FIG. 2, a tile computing system (500) according to an embodiment of the present invention may be configured to include a host node (100) and a plurality of tile chip nodes (200). Here, the host node (100) and the tile chip node (200) may be implemented as chip nodes, and the chip nodes may be semiconductor chips such as a system on chip or a network on chip. In addition, the tile chip node (200) refers to a chip node in which a plurality of semiconductor chips can be modularized like tiles.

[0052] The host node (100) may include a controller unit (Micro Controller Unit, MCU) as a general-purpose core node, and performs the role of transmitting and receiving data and control signals through the TSPI physical layer (PHY). In particular, unlike a conventional SPI host, the host node (100) according to an embodiment of the present invention is not connected to each of a plurality of tile chip nodes (200) constituting a tile computing system, but can communicate only with an adjacent tile chip node, i.e., the first tile chip node (210) in the drawing.

[0053] A plurality of tile chip nodes (200) each include a communication interface, i.e., TSPI, for one-to-one communication with each other in the four directions of up, down, left, and right, and can communicate with a host node (100) or another tile node (200) connected through the TSPI.

[0054] That is, since the first tile chip node (210) is connected to the host node (100) via TSPI and is connected to the second tile chip node (220) via TSPI, the first tile chip node (210) can communicate one-to-one with the host node (100) and the second tile chip node (220). In addition, since the second tile chip node (220) is connected to the first tile chip node (210) and the third tile chip node (230) via TSPI, the second tile chip node (220) can communicate one-to-one with the first tile chip node (210) and the third tile chip node (230), and since the first tile chip node (210) is not directly connected to the third tile chip node (230), direct communication is impossible.

[0055] In this way, the plurality of tile chip nodes (200) constituting the tree structure array of the present invention include TSPIs in four directions, and can freely connect new tile chip nodes in each direction. Even if a new tile chip node is connected, there is no need to add a connection with a new tile chip node to the host node (100), so that the expansion of the tile computing system (500) is easier, and more efficient management is possible by reducing excessive I / O ports in the host node (100).

[0056] The TSPI communication interface according to an embodiment of the present invention that supports the above-described process performs communication using an index for one-to-one communication. Here, the index means location information for each node allocated by the host node (100). For example, the index of the first tile chip node (210) may be allocated as 1, the index of the second tile chip node (22) may be allocated as 7, and the TSPI communication interface may transmit data using the index.

[0057] In other words, more specifically, referring to FIGS. 3 and 4, as illustrated in FIG. 3, each TSPI communication interface includes a data communication line and a CS communication line, and whenever the CS communication line becomes a LOW signal state, data can be transmitted through the data communication line. At this time, the data transmitted through the data communication line includes a command, an index, and data, as illustrated in FIG. 4, and the index includes a source index, which is location information for a source node, and a destination index, which is location information for a destination node.

[0058] The TSPI communication interface checks the index included in the data when transmitting data through the data communication line when the CS communication line is in a LOW signal state. If the source index is index 1 and the destination index is index 7, data can be transmitted from the first tile chip node (210) to the second tile chip node (220).

[0059] A method of allocating a more specific index and transmitting data using the index will be described later, and commands included in the data of the present invention may include RESET OPERATION, WRITE ID OPERATION, READ STATUS OPERATION, READ BUFFER OPERATION, WRITE ENABLE OPERATION, and WRITE BUFFER OPERATION, as shown in (b) of FIG. 4.

[0060] RESET OPERATION is a command to initialize all registers, and WRITE ID OPERATION is a command to sequentially assign IDs to all nodes. READ STATUS OPERATION is a command to determine the current status of all nodes and can be controlled through polling, and READ BUFFER OPERATION is a command to read the value stored in the buffer (SRAM). WRITE ENABLE OPERATION is a command to enable writing to the buffer value and can protect the buffer from arbitrary data writing, and WRITE BUFFER OPERATION is a command to perform a write operation on the buffer within the accelerator.

[0061] Among these, the buffer-related commands READ BUFFER OPERATION, WRITE ENABLE OPERATION, and WRITE BUFFER OPERATION include commands for the same maximum number of bytes and buffer size, which will be described in more detail with reference to FIG. 6.

[0062] In addition, data included in data transmitted and received through the TSPI of the present invention may include, for example, weights, biases, feature maps, etc. for artificial intelligence operations.

[0063] In this way, the TSPI communication interface included in each of the host node (100) and the plurality of tile chip nodes (200) of the present invention performs communication using an index, which is location information of each tile chip node (200), so that if it is a node that includes TSPI in the physical layer, a new tile chip node can be freely connected in the corresponding direction, and even if a new tile chip node is connected, there is no need to add a connection with the new tile chip node to the host node (100), so that the expansion of the tile computing system (500) can be easier than in the conventional SPI system.

[0064] That is, as illustrated in (a) of Fig. 5, it can be expanded in various directions through the TSPI communication interface, and as illustrated in (b), multiple chips can be interconnected through 3D packaging technology via wire bonding, and tile chips can be stacked and expanded through modularization of ports. According to this structure, when the tile computing system including the TSPI communication interface of the present invention is applied to a hardware accelerator for artificial intelligence, it can solve problems such as bandwidth, power consumption, and scalability for artificial intelligence operations.

[0065] Below, a host node according to an embodiment of the present invention will be described in more detail.

[0066] FIG. 6 is a diagram illustrating the main configuration of a host node according to an embodiment of the present invention, and FIG. 7 is an exemplary diagram for explaining memory management in a host node according to an embodiment of the present invention.

[0067] Referring to FIG. 6, the host node (100) of the present invention is a processor adapted to execute one or more machine-executable instruction sets, and may be a CPU processor operating based on, for example, an ARM Cortext-MO core.

[0068] Additionally, the host node (100) includes two 64KB SRAMs (memory for storing data) and a 12KB ROM cache (for storing code), and can load code and data into the cache using an external 32MB NOR flash memory. The host node (100) can operate similarly to retrieving data from an external DRAM to the on-chip memory of the embedded chip.

[0069] In particular, the host node (100) according to an embodiment of the present invention includes a TSPI communication interface according to an embodiment of the present invention adjacent to a core, and when the host node (100) according to an embodiment of the present invention includes two TSPI communication interfaces per core pair, one-to-one communication with two tile chip nodes (200) is possible, respectively.

[0070] That is, the host node (100) according to an embodiment of the present invention may include a first TSPI communication interface (TSPI1 PHY) and a second TSPI communication interface (TSPI2 PHY), wherein the first TSPI communication interface (TSPI1 PHY) and the second TSPI communication interface (TSPI2 PHY) may be positioned in opposite directions, for example, in the up-down and left-right directions.

[0071] Thereafter, the host node (100) is connected to two tile chip nodes via each TSPI communication interface, thereby enabling one-to-one communication. In this way, the host node (100) of the present invention includes a dual structure that controls two tile chip nodes per core pair, thereby preventing core or DMA performance from being aligned toward the slow side due to data movement.

[0072] In addition, the host node (100) of the present invention includes DMA (Direct Memory Access) and can perform data buffering for transmission between RAM and TSPI. At this time, if the host node (100) of the present invention has a dual structure that controls two tile chip nodes (200) per core pair as described above, a problem may arise in which access to RAM conflicts between both the core and DMA.

[0073] To solve these problems, the host node (100) according to an embodiment of the present invention includes a hold function in the control bus (e.g., AHB BUS), and when DMA accesses data in RAM while using the AHB bus, the operation can be temporarily stopped based on the finite state of the DMA and a conflict signal of the core.

[0074] To this end, the TSPI of the host node (100) needs to carefully adjust the number of bytes for data transmission between tile chip nodes (200) to align them with the buffer size, and therefore, the TSPI interfaces included in all nodes constituting the tile computing system can further optimize resources by setting the maximum number of bytes that can be transmitted and the buffer size to be the same.

[0075] In addition, as illustrated in (a) of FIG. 7, the core of the host node (100) of the present invention can coordinate the movement of data from the ROM cache to the RAM. Since the core cannot access the ROM cache memory area while the DMA interacts with the ROM cache, it remains inactive during this period. That is, as illustrated in (b) of FIG. 7, the clock (CLK) speed of the TSPI communication interface of the present invention is implemented to be twice as slow as the data transfer speed from the ROM to the RAM of the host node (100), so that the core of the host node (100) can perform additional tasks while the TSPI transfers data to the tile chip node (200).

[0076] Meanwhile, a plurality of tile chip nodes (200) of the present invention are interconnected in a tree structure, and an index, which is location information for each tile chip node (200), is assigned by the host node (100). Hereinafter, a process in which the host node (100) assigns an index to a tile chip node (200) according to an embodiment of the present invention will be described.

[0077] FIG. 8 and FIG. 9 are diagrams for explaining a process of allocating an index in a host node according to an embodiment of the present invention.

[0078] First, referring to FIG. 8, the CPU, which represents the host node (100), maintains its position at a fixed position to form a tree-connected network of tile chip nodes (200). The tree-connected network plays a role in enabling expansion of the tile chip node (200) of the present invention. However, since the number of tile chips and the shape of the entire tree cannot be known in advance due to expandability, the position of the tile chip node (200) is determined based on the host node (100), which is the CPU, rather than the absolute position, considering the modular nature of this structure.

[0079] To determine the location of multiple tile chip nodes (200), the host node (100) of the present invention can utilize the relationships of vertical, horizontal, and diagonal connections.

[0080] To this end, the host node (100) can determine the location of a specific tile chip node by assigning indices to a plurality of tile chip nodes (200) based on its own location. First, the host node (100) assigns indices to the first depth tile chip nodes (A, B) connected based on its own location. An even index of 0 can be assigned to tile chip node A connected in the first direction, for example, the left direction, and an odd index of 1 can be assigned to tile chip node B connected in the right direction. Depending on the implementation method, tile chip node A may be connected to the top of the host node (100), and tile chip node B may be connected to the bottom, and even and odd indices may be assigned according to the top and bottom directions.

[0081] When an index is assigned to a tile chip node of the first depth (d=1) connected to a host node (100), the host node (100) can assign an index to a tile chip node corresponding to the next depth. If an even index is assigned to a tile chip node A of the first depth, all child nodes that are subordinate nodes of tile chip node A are assigned even indexes, and if an odd index is assigned to a tile chip node B, all child nodes that are subordinate nodes of tile chip node B are assigned odd indexes.

[0082] In addition, the host node (100) of the present invention sequentially assigns increased indexes to tile chip nodes corresponding to the same depth, taking into account the number of child nodes (N) and the direction of the tile chip nodes. That is, if tile chip node A has three child nodes, tile chip node A is located on the left of the host node (100), and assigns even indexes of 2, 4, and 6 to tile chip nodes of the second depth, which correspond to child nodes in the left (LL), left upper (LU), and left right (LR) directions with respect to the host node (100).

[0083] In addition, if tile chip node B has three child nodes, tile chip node B is located to the right of the host node (100), and odd indices of 3, 5, and 7 are assigned to each of the tile chip nodes of the second depth corresponding to the child nodes in the left (RL), right upper (RU), and right right (RR) directions with respect to the host node (100).

[0084] This indexing process is illustrated in Figure 9.

[0085] Through this index assignment process, each tile chip node (200) can actively identify its own location based on the index input from the upper node, and if the data transmitted through the communication interface is not data transmitted to itself, it can use an index search algorithm to check the transmission direction and transmit data to the connected tile chip node in response to the confirmed transmission direction.

[0086] The index search algorithm will be described with reference to FIGS. 10 and 11.

[0087] FIG. 10 and FIG. 11 are diagrams for explaining an index search process according to an embodiment of the present invention.

[0088] First, by utilizing the characteristics of the ternary tree in Fig. 10, the number of nodes per depth is N d It is expressed as -1, and the cumulative number according to depth is calculated using a geometric formula. can be given as . If we multiply this cumulative number by 2, This can be the starting index of the (d+1)th depth. By utilizing this characteristic, we can determine the depth from the index. The difference between child nodes sharing the same parent node is 2 x N at each depth. d-2 can increase by as much as 2 x N , and similarly the difference between the first node values ​​of three adjacent subnodes is 2 x N . d-3For example, in the 4th depth, the initial values ​​of the three adjacent child nodes are 26, 32, and 38, which is 2 x 3. 1 =6 difference can be seen.

[0089] For example, if a host node (100) wants to transmit data to a tile chip node at index 56, first, since the index is even, the data is transmitted to the TSPI located to the left of the CPU. The tile chip node A at index 0 that receives this determines at what depth index 56 is located.

[0090] Specifically, if (d+1)=5, We use the formula to calculate the depth, which could mean that index 56 exists at the 4th depth.

[0091] After that, the index difference of child nodes sharing the same parent node is 2xN d-2 = 2x3 2 = 18, we subtract 18 from 56 until it becomes greater than or equal to the minimum (starting index) in the 4th depth. That is, if we subtract 18 from 56 once, we get 38, and if we subtract it twice, we get 20. Since 20 is less than the minimum in the 4th depth, we subtract 6 (the difference in the 4th depth) from 38 until it becomes greater than or equal to the minimum (26) of the 4th depth, which becomes 26. This can indicate that the index 56 belongs to the index 2 tile chip node in the 2nd depth. If the result were 28, it would have belonged to the index 4 tile chip node in the 2nd depth. This method indicates that the index should move towards position 2 in the 1st depth, which means left direction for data transmission.

[0092] Also, if you want to find a path from a tile chip node with index 0 to a tile chip node with index 2, you don't need to consider the paths to other nodes (4, 6) in the second depth. If you classify 56 by depth using the properties explained above, 56 = 1 x 2 x 30 + 3 x 2 x 3 1 + 2 x 2 x 3 2 Here, the exponent of 3 in each term represents d-1, and the multiplication by 2 is because 56 is an even number, and 2 x 3 d-1 The coefficients in front of the silver represent the path.

[0093] Specifically, coefficient 1 corresponds to the left, coefficient 2 corresponds to the top, and coefficient 3 corresponds to the right, so 56 follows the left, left, right, top (LLRU) path. It is difficult to implement this factorization all at once in hardware, but it can be easily performed through the algorithm of the present invention. In addition, all nodes under index 2 can maintain the same node configuration by subtracting 2, nodes under index 4 can subtract 4, and all nodes under index 6 can subtract 6. By utilizing this, if 2 is subtracted from the factored 56 and divided by 3, 18 (= 3 x 2 x 3) is obtained. 0 + 2 x 2 x 3 1 , RU) will be formed.

[0094] Therefore, when the upper tile chip node receives data, it checks the index of the data, and if its index value is even, it subtracts the even identification index 2, and since it is a ternary tree, it divides it by the child node number parameter 3, and then it can recursively search the path until it reaches the index value of the first depth (0) as shown in Figure 10.

[0095] Also, if its index value is odd, the odd identification index 1 is subtracted, and since it is a ternary tree, the path can be recursively searched until it reaches the index value of the first depth (1) after dividing it by the child node number parameter 3.

[0096] This algorithm can be repeated until the index reaches 0, providing a transmission path for tile chip nodes. Essentially, this recursive algorithm can enhance the modularity and scalability of tile chips, and its standardized structure facilitates automation of the design process.

[0097] The index search algorithm of the present invention described above is illustrated through FIG. 11.

[0098] The tile computing system and the tile chip node therefor according to an embodiment of the present invention have been described above.

[0099] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the patent claims.

[0100] The present invention relates to a tile computing system, which has improved modularity and expandability by interconnecting a plurality of tile chip nodes, and a tile chip node therefor.

[0101] According to the present invention, by interconnecting a plurality of tile chip nodes, even if a new tile chip node is connected, there is no need to add a connection to the host node with a new tile chip node, thereby improving modularity and expandability, thereby contributing to the development of the embedded system industry, such as artificial intelligence hardware accelerators, and having sufficient potential for industrial use.

[0102] [Explanation of symbols]

[0103] 100: Host node

[0104] 200: Tile chip node

[0105] 500: Tile Computing System

Claims

1. In a tile computing system including a host node and a plurality of tile chip nodes interconnected in a tree structure, The above host node is A communication interface connected to at least one tile chip node among the plurality of tile chip nodes and configured to communicate with the connected tile chip node, Each of the above plurality of tile chip nodes Each of the four directions, up, down, left, and right, includes a communication interface for one-to-one communication. A tile computing system characterized in that each communication interface of the plurality of tile chip nodes performs communication using an index, which is location information for each tile chip node allocated by the host node.

2. In paragraph 1, The above host node A first communication interface and a second communication interface in the opposite direction of the first communication interface are included, A tile computing system characterized in that each of a first tile chip node connected to the first communication interface and a second tile chip node connected to the second communication interface performs one-to-one communication.

3. In paragraph 1, The above host node is Based on its own position, it determines whether the connected first depth tile chip node is connected to the first communication interface located in one direction or the second communication interface located in the opposite direction of the one direction. A tile computing system characterized in that an even or odd index corresponding to a first communication interface or a second communication interface is assigned to a connected first depth tile chip node.

4. In paragraph 3, Each of the above plurality of tile chip nodes It is interconnected in a ternary tree structure containing three child nodes, The above host node is A tile computing system characterized in that, to each of the tile chip nodes of the second depth having the tile chip node of the first depth as a parent node, an index is sequentially increased based on an even or odd index assigned to the tile chip node of the first depth, taking into account the number of child nodes and the direction of the tile chip node.

5. In paragraph 4, The above host node is A tile computing system characterized in that, based on its own position, it sequentially assigns an index that increases in the left, upper, and right directions of the tile chip node.

6. In paragraph 1, Each of the above tile chip nodes is A tile computing system characterized in that it checks an index included in data transmitted through the communication interface, and if the data is not transmitted to itself, it checks a transmission path for the index using a predefined index search algorithm, and transmits the data to a tile chip node connected in response to the confirmed transmission path.

7. In paragraph 6, A tile chip node that receives data through the above communication interface checks the index assigned to it if the data is not transmitted to it. If the assigned index is even, The even-numbered identification index is subtracted from the index included in the above data, divided by the number of child nodes parameter, and then a search is performed according to a predefined index search algorithm until the index included in the above data becomes the index value of the first depth to determine the transmission path. If the assigned index is odd, A tile computing system characterized in that it checks the transmission path by subtracting odd identification indices from the indices included in the above data, dividing by the number of child nodes parameter, and then performing a search according to a predefined index search algorithm until the indices included in the above data become the index value of the first depth.

8. In a host node and a plurality of tile chip nodes interconnected to the host node in a tree structure, Each of the above plurality of tile chip nodes Each of the four directions, up, down, left, and right, includes a communication interface for one-to-one communication. The above communication interface is Includes data communication lines and CS communication lines, When the above CS communication line becomes a low signal state, data is transmitted and received through the data communication line. A tile chip node, characterized in that the data transmitted and received includes an index, which is location information for each tile chip node allocated by the host node.

9. In paragraph 8 The above command is Contains buffer-related commands, A tile chip node, wherein the buffer-related commands include the same maximum number of bytes and buffer size for managing memory access in the host node.

10. In paragraph 8 A tile chip node characterized in that the clock (CLK) speed of the communication interface is slower than the memory data transfer speed of the host node.

11. In paragraph 8 The above index is A tile chip node characterized by including a source index, which is location information of a source node, and a destination index, which is location information of a destination node.

12. In paragraph 8 The above communication interface is A tile chip node characterized by comprising a decoding circuit for searching a transmission path for the index using a predefined index search algorithm.

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