Display panel and display device

Abstract

A display panel (PNL) and a display device. The display panel (PNL) comprises at least two sub-panels (SPNL) sequentially tiled in a column direction; any sub-panel (SPNL) comprises sub-pixels (PIX) distributed in an array and scan lines (GL) in one-to-one correspondence to sub-pixel rows; and the sub-panel (SPNL) is provided with a plurality of gate drive circuits (GOA) for driving the scan lines (GL), wherein among two adjacent sub-panels (SPNL), the timing of a start signal of the gate drive circuit (GOA) electrically connected to the last row of scan line (GL) of the preceding sub-panel (SPNL) is the same as the timing of a start signal of the gate drive circuit (GOA) electrically connected to the first row of scan line (GL) of the subsequent sub-panel (SPNL). The problem of screen tearing of the tiled display panels (PNL) can be solved.

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] At present, the gate drive circuit GOA drive scanning mode of the AM (active drive) Mini / Micro LED (mini light-emitting diode or micro light-emitting diode) spliced ​​display screen starts scanning for each splicing module at the same time. This causes the time difference between the scanning moments of the two rows of pixels at the seam of the upper and lower modules (the last row of pixels of the upper module and the first row of pixels of the lower module) to reach the duration of one scanning cycle (1Frame). Therefore, the time difference between the image display of the two rows of pixels at the seam of the upper and lower modules is also the duration of one scanning cycle. When playing fast-moving pictures, the upper and lower modules are prone to the phenomenon of picture asynchrony (picture tearing), affecting the display quality.

[0003] It is understood that one frame includes one scanning period (1Frame) and one blank period (1blank). Specifically, one Frame is the time it takes for the gate drive circuit GOA of the module to scan from the first row to the last row.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0005] Summary of the Invention

[0006] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a display panel and a display device so as to solve the problem of screen tearing of spliced ​​display panels.

[0007] According to one aspect of the present disclosure, there is provided a display panel comprising at least two sub-panels sequentially spliced ​​along a column direction;

[0008] Any of the sub-panels includes sub-pixels distributed in an array and scan lines corresponding to each sub-pixel row;

[0009] The sub-panel has a plurality of gate driving circuits for driving the respective scan lines;

[0010] Among them, in two adjacent sub-panels, the starting signal of the gate drive circuit electrically connected to the last row of scan lines of the previous sub-panel is at the same time as the starting signal of the gate drive circuit electrically connected to the first row of scan lines of the next sub-panel.

[0011] In one embodiment of the present disclosure, the display panel includes two sub-panels.

[0012] In one embodiment of the present disclosure, the sub-panel includes two gate driving circuits.

[0013] In one embodiment of the present disclosure, m gate driving circuits are provided on the sub-panel; m is a positive integer greater than 1;

[0014] The scan lines are divided into a plurality of sequentially adjacent scan line groups, each scan line group comprising m sequentially adjacent scan lines;

[0015] The m scan lines in the same scan line group are respectively driven by m gate driving circuits.

[0016] In one embodiment of the present disclosure, the gate driving circuits each include a plurality of shift registers cascaded in sequence;

[0017] The jth scan line in the i-th scan line group is electrically connected to the i-th shift register of the j-th gate driving circuit; j is a positive integer between 1 and m.

[0018] In one embodiment of the present disclosure, the gate driving circuit includes a plurality of shift registers cascaded in sequence;

[0019] The first reference gate driving circuit of the sub-panel is a gate driving circuit that drives the last row of scan lines of the sub-panel; the second reference gate driving circuit of the sub-panel is a gate driving circuit that drives the first row of scan lines of the sub-panel;

[0020] In two adjacent sub-panels, the input end of the first stage shift register of the first reference gate driving circuit of the former sub-panel is electrically connected to the input end of the first stage shift register of the second reference gate driving circuit of the latter sub-panel.

[0021] In one embodiment of the present disclosure, the display panel includes a first sub-panel and a second sub-panel sequentially spliced ​​along a column direction;

[0022] The first sub-panel has a first gate driving circuit and a second gate driving circuit for driving each of the scan lines; the first gate driving circuit is used to drive the odd-numbered scan lines of the first sub-panel, and the second gate driving circuit is used to drive the even-numbered scan lines of the first sub-panel;

[0023] The second sub-panel has a third gate driving circuit and a fourth gate driving circuit for driving each of the scan lines; the third gate driving circuit is used to drive the odd-numbered scan lines of the second sub-panel, and the fourth gate driving circuit is used to drive the even-numbered scan lines of the second sub-panel.

[0024] In one embodiment of the present disclosure, the number of scan lines of the sub-panel is an even number; the start signal of the second gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are at the same time.

[0025] In one embodiment of the present disclosure, the number of scan lines of the sub-panel is an odd number; the start signal of the first gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are at the same time.

[0026] In one embodiment of the present disclosure, a start time of the start signal of the first gate driving circuit is earlier than a start time of the start signal of the second gate driving circuit by half a scanning cycle.

[0027] In one embodiment of the present disclosure, the sub-panel has a light emitting control trace corresponding to each sub-pixel row, and the light emitting control trace is used to load a light emitting control signal to the pixel driving circuit;

[0028] The light-emitting control wirings are electrically connected to each other.

[0029] In one embodiment of the present disclosure, the display panel is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel or an LCD display panel.

[0030] According to another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel.

[0031] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0033] FIG1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0034] FIG2 is a schematic diagram of a sub-panel in one embodiment of the present disclosure.

[0035] FIG3 is a schematic diagram of a film layer of a sub-panel in one embodiment of the present disclosure.

[0036] FIG4 is a schematic diagram of a film layer of a sub-panel in one embodiment of the present disclosure.

[0037] FIG5 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.

[0038] FIG6 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.

[0039] FIG7 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.

[0040] FIG8 is a schematic diagram of a film layer of a sub-pixel in one embodiment of the present disclosure.

[0041] FIG9 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0042] FIG. 10 is a timing diagram corresponding to scan lines of each sub-pixel row of the display panel in FIG. 9 in one embodiment of the present disclosure.

[0043] FIG11 is a schematic structural diagram of a display panel in one embodiment of the present disclosure.

[0044] FIG. 12 is a timing diagram corresponding to scan lines of each sub-pixel row of the display panel in FIG. 11 in one embodiment of the present disclosure.

[0045] FIG13 is a timing diagram of a start signal in one embodiment of the present disclosure.

[0046] FIG14 is a timing diagram of simultaneously loading light-emitting control signals on each sub-pixel row in one embodiment of the present disclosure.

[0047] 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 , 11 , 12 , 13 , 14 , 15 , 16 , 17 , 18 , 19 , 20 , 21 , 22 , 23 , 24 , 25 , 26 , 27 , 28 , 29 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 40 , 41 , 42 , 39 , 50 , 51 , 52 , 53 , 39 , 30 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 51 , 52 , 53 , 39 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 , 39 , 51 , 52 , 53 , 39 , 31 , 32 , 33 , 34 , 35 , 36 , 37 , 38 L, hole injection layer; HTL, hole transport layer; IJP, organic encapsulation layer; ILD, interlayer dielectric layer; PDC, pixel driving circuit; PDL, pixel definition layer; PE, pixel electrode; PEL, pixel electrode layer; PIX, sub-pixel; PIXL, pixel layer; PLN, planarization layer; PNL, display panel; QDL, quantum dot layer; SBT, substrate; SCL, semiconductor layer; SD, source and drain metal layer; SPNL, sub-panel; SPNL1, first sub-panel; SPNL2, second sub-panel; SR, shift register; TFE, thin film encapsulation layer; TFT, thin film transistor; TSL, touch function layer; SR1, first shift register; SR2, second shift register; SR3, third shift register; SR89, ​​eighty-ninth shift register; SR90, ninetieth shift register; DETAILED DESCRIPTION

[0048] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0049] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0050] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0051] In the embodiments of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiments of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiments of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor. In an embodiment of the present disclosure, at least part of the signal has a high level and a low level; one of the high level and the low level can be used as the on-level of the signal, and the on-level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the off-level of the signal, and the off-level of the signal can turn off the controlled transistor. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its on-level is a low level, and its off-level is a high level. For another example, for a signal that controls an N-type transistor (the signal can be loaded to the control terminal of the N-type transistor), its on-level is a high level, and its off-level is a low level.

[0052] Structural layer A is located on the side of structural layer B facing away from the substrate SBT. This means that structural layer A is formed on the side of structural layer B facing away from the substrate SBT. When structural layer B is a patterned structure, part of structural layer A may be located at the same physical height as structural layer B or lower than the physical height of structural layer B, with the substrate SBT serving as a height reference.

[0053] The present disclosure provides a display device, including a display panel PNL. The display device can be any product or component with a display function, such as a TV, an all-in-one conference machine, or an advertising screen. In one example, the display panel PNL is a display panel PNL with a display size of not less than 80 inches, and in particular, a display panel PNL with a display size of not less than 100 inches. Of course, the display panel PNL can also be a small or medium-sized display panel PNL, such as a direct-display Mini LED display panel or a direct-display Micro LED display panel.

[0054] 1 , the display panel PNL includes at least two sub-panels SPNL sequentially spliced ​​along a column direction. In this way, a larger display panel PNL can be formed using smaller sub-panels SPNL, thereby reducing the cost of the display panel PNL.

[0055] In one embodiment of the present disclosure, referring to FIG. 2 , the sub-panel SPNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. Within the display area AA, the sub-panel SPNL is provided with an array of display units, each of which includes sub-pixels PIX and a pixel driving circuit PDC that drives the sub-pixels PIX. The sub-panel SPNL does not have a display unit in the peripheral area BB, or the display unit that is provided is not used for displaying images.

[0056] Referring to Figure 2, the sub-panel SPNL is provided with a plurality of scan lines GL extending along the row direction DH in the display area AA, and each scan line GL is provided in a one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The sub-panel SPNL is also provided with a plurality of data lines DL extending along the column square DV in the display area AA, and each data line DL is provided in a one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to one scan line GL and one data line DL. When a scan signal is loaded on the scan line GL, the driving voltage loaded on the data line DL can be written into the pixel driving circuit PDC, thereby causing the sub-pixel PIX to emit light.

[0057] Optionally, the pixel drive circuit PDC includes at least a data write transistor, a drive transistor and a storage capacitor, and the control terminal of the drive transistor can be electrically connected to an electrode plate of the storage capacitor. The source of the data write transistor can be electrically connected to the data line DL, and the control terminal of the data write transistor can be electrically connected to the scan line GL. The pixel drive circuit PDC is configured so that when a scan signal is loaded on the scan line GL, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the control terminal and storage capacitor of the drive transistor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor. The drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its control terminal. It is understandable that the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors to enable the pixel drive circuit PDC to have better driving performance. For example, the pixel drive circuit PDC can be a pixel drive circuit of 7T1C (7 thin film transistors TFT and a storage capacitor), 8T1C (8 thin film transistors TFT and a storage capacitor) or other architectures.

[0058] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of the light-emitting elements such as OLED, QLED, Micro LED, Mini LED, etc. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel for emitting red light, a blue sub-pixel for emitting green light, and a green sub-pixel for emitting green light. It is understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also have sub-pixels PIX of other colors (for example, a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0059] In one embodiment of the present disclosure, referring to FIG3 , the sub-panel SPNL may include a base substrate SBT, a driving layer DRL, and a pixel layer PIXL stacked in sequence. Sub-pixels PIX are provided in the pixel layer PIXL, and the driving layer DRL is provided with a pixel driving circuit PDC for driving the sub-pixels PIX; each sub-pixel PIX can emit light to display a picture under the drive of the pixel driving circuit PDC. In the example of FIG3 , the sub-pixel PIX is a thin-film self-luminous element, such as an OLED, QLED, PLED or other light-emitting element. In the example of FIG3 , the sub-panel SPNL further includes an encapsulation layer located on the side of the pixel layer PIXL away from the base substrate SBT, which can encapsulate and protect the pixel layer PIXL. In one example, the encapsulation layer is a thin-film encapsulation layer TFE.

[0060] It is understood that in the embodiments of the present disclosure, the display panel PNL may also be another type of panel. For example, the display panel PNL may also be a Mini LED display panel, a Micro LED display panel, or other display panel. In such a display panel PNL, the film layer structure of the sub-panel SPNL may differ from that shown in FIG3 . The PNL may also be an LCD display panel; in such an LCD display panel PNL, the structure of the sub-panel SPNL may also differ from that shown in FIG3 .

[0061] As follows, the film structure and spacing of the sub-panel SPNL are exemplarily described by taking the sub-pixel PIX of the display panel PNL as a thin-film self-luminous element as an example.

[0062] In this example, the substrate substrate SBT can be a substrate substrate SBT of an inorganic material, or a substrate substrate SBT of an organic material; of course, it can also be a composite substrate formed by stacking a substrate substrate SBT of an inorganic material and a substrate substrate SBT of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, or a combination thereof. In some other embodiments of the present disclosure, the substrate substrate SBT can also be a flexible substrate substrate SBT, for example, the material of the substrate substrate SBT can include polyimide.

[0063] Optionally, in the drive layer DRL, any pixel drive circuit PDC may include a thin film transistor TFT and a storage capacitor. Furthermore, the thin film transistor TFT may be selected from a top-gate thin film transistor TFT, a bottom-gate thin film transistor TFT, or a dual-gate thin film transistor TFT; the material of the active layer of the thin film transistor TFT may be an amorphous silicon semiconductor material, a low-temperature polysilicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor TFT may be an N-type thin film transistor TFT or a P-type thin film transistor TFT.

[0064] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistor TFT is a low-temperature polysilicon transistor. In some other embodiments of the present disclosure, some thin film transistors TFT are low-temperature polysilicon transistors, and some thin film transistors TFT are metal oxide transistors.

[0065] Optionally, the driving layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor TFT and the storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, the source / drain metal layer SD, etc. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor TFT. Furthermore, the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be formed into partial wiring or conductive structure by conductorization when necessary. The gate layer may be used to form one or more gate layer wirings such as scan wiring, reset control wiring, and light emission control wiring, may also be used to form the control terminal of the transistor, and may also be used to form part or all of the electrode plates of the storage capacitor. The source / drain metal layer may be used to form source / drain metal layer wirings such as data wiring and drive power supply voltage wiring, and may also be used to form part of the electrode plates of the storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, the source / drain metal layer SD, etc. may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0066] Optionally, the driving layer DRL may further include a passivation layer. The passivation layer may be provided on a surface of the source / drain metal layer SD away from the substrate SBT, so as to protect the source / drain metal layer SD.

[0067] As an example, referring to FIG3 , the driving layer DRL may include an inorganic buffer layer Buff, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked in sequence, and the thin film transistor TFT formed in this way is a top-gate thin film transistor TFT.

[0068] In one embodiment of the present disclosure, referring to FIG. 4 and FIG. 5 , the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional unit EFU sandwiched between the two electrodes.

[0069] For example, referring to FIG4 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML, which are stacked in sequence. The pixel electrode layer PEL includes multiple pixel electrodes PE in the display area of ​​the sub-panel SPNL. The portion of the light-emitting functional layer EFL connected to the pixel electrodes PE serves as the light-emitting functional unit EFU of the sub-pixel PIX. The common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional unit EFU of each sub-pixel PIX.

[0070] Furthermore, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting functional layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode PE (the area directly connected to the light-emitting functional unit EFU), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PIX. The light-emitting functional layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting functional layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting functional layer EFL, so that the light-emitting functional layer EFL emits light. The portion of the light-emitting functional layer EFL located between the pixel electrode PE and the common electrode layer COML can serve as a light-emitting functional unit EFU. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit EFU form a sub-pixel PIX, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0071] In one example, the pixel electrode PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0072] It is understandable that the types of light-emitting elements are different, and the materials and film layers of the light-emitting functional units EFU are different.

[0073] For example, referring to FIG5 , when the light-emitting element is an OLED, the light-emitting functional unit (EFU) may include an organic light-emitting layer (EML), and may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the organic light-emitting layer (EML) may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material. Referring to FIG6 , when the OLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the light-emitting functional layer (EFL).

[0074] For another example, referring to FIG7 , when the light-emitting element is a QLED, the light-emitting functional unit EFU may include a quantum dot layer QDL, and may include one or more of a hole injection layer HIL, an electron transport layer ETL, an electron blocking layer EBL, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL. Furthermore, the quantum dot layer QDL may include quantum dot particles, which may be interconnected via surface modification groups. Referring to FIG8 , when the QLED adopts a stacked structure, a charge generation layer CGL may also be provided in the light-emitting functional unit EFU.

[0075] In the embodiments of the present disclosure, referring to Figures 5 to 8 , the light-emitting functional unit EFU may include a single light-emitting stack structure ELS, or may include a stack of multiple light-emitting stack structures ELS. When the light-emitting functional unit EFU includes multiple light-emitting stack structures ELS, a charge generation layer CGL may be provided between two adjacent light-emitting stack structures ELS. Each light-emitting stack structure ELS is provided with one or more light-emitting layers, which may be either an organic light-emitting layer EML or a quantum dot layer QDL.

[0076] 3 , the thin film encapsulation layer TFE may be provided on the surface of the pixel layer PIXL away from the base substrate SBT, which may include an inorganic encapsulation layer and an organic encapsulation layer alternately stacked. The inorganic encapsulation layer can effectively block external moisture and oxygen, preventing water and oxygen from invading the pixel layer PIXL and causing aging of the material in the pixel layer PIXL. Optionally, the edge of the inorganic encapsulation layer may be located in the peripheral area. The organic encapsulation layer is located between two adjacent inorganic encapsulation layers to achieve planarization and reduce the stress between the inorganic encapsulation layers. The edge of the organic encapsulation layer may be located between the edge of the display area and the edge of the inorganic encapsulation layer. Exemplarily, the thin film encapsulation layer TFE includes a first inorganic encapsulation layer CVD1, an organic encapsulation layer IJP, and a second inorganic encapsulation layer CVD2 sequentially stacked on the side of the pixel layer PIXL away from the base substrate SBT. Of course, in other embodiments of the present disclosure, the sub-panel SPNL may not be provided with a thin film encapsulation layer, but may use other methods to encapsulate and protect the pixel layer.

[0077] In some embodiments of the present disclosure, referring to FIG. 3 , the sub-panel SPNL may further include a touch function layer TSL. The touch function layer TSL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP, so that the sub-panel SPNL has a touch function.

[0078] In some embodiments of the present disclosure, referring to FIG. 3 , the sub-panel SPNL may further include a color filter layer CFL. The color filter layer CFL may be disposed on a side of the thin film encapsulation layer TFE away from the driving backplane DBP to reduce reflection of ambient light and improve display quality.

[0079] In one embodiment of the present disclosure, referring to FIG9 , the display panel PNL includes at least two sub-panels SPNL sequentially spliced ​​along the column direction. Any one of the sub-panels SPNL includes array-distributed sub-pixels PIX and scan lines GL corresponding to each sub-pixel row. The sub-pixels PIX are provided with the above-mentioned pixel driving circuit PDC, and the pixel driving circuit PDC is used to drive the sub-pixels PIX; the sub-panel SPNL has a plurality of gate driving circuits GOA for driving each of the scan lines GL. Among them, in two adjacent sub-panels SPNL, the start signal of the gate driving circuit GOA electrically connected to the scan line GL in the last row of the previous sub-panel SPNL is the same as the start signal of the gate driving circuit GOA electrically connected to the scan line GL in the first row of the next sub-panel SPNL.

[0080] It is understood that the "previous" and "next" in this embodiment refer to the upper and lower positional relationship between two adjacent sub-panels SPNL. For example, the previous sub-panel SPNL may refer to the sub-panel SPNL located at the top, and the next sub-panel SPNL may refer to the sub-panel SPNL located at the bottom, and the two sub-panels SPNL are spliced ​​in sequence. In one example, the timing of the start signals being the same may mean that the input terminals of the two gate drive circuits GOA share the same start signal or that the timing of the start signals respectively connected to the input terminals of the two gate drive circuits GOA is the same.

[0081] In two adjacent sub-panels SPNL, by setting the start signal of the gate drive circuit GOA electrically connected to the last row of scan line GL of the previous sub-panel SPNL and the start signal of the gate drive circuit GOA electrically connected to the first row of scan line GL of the next sub-panel SPNL to be the same, when driving the scan lines GL of the two adjacent sub-panels SPNL, the odd and even row scan lines GL of the sub-panel SPNL can be driven separately, thereby reducing the scanning time difference between the last row of scan line GL of the previous sub-panel SPNL and the first row of scan line GL of the next sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced ​​display panel PNL, so as to improve the display quality and facilitate application in display products with customizable splicing sizes.

[0082] In one embodiment of the present disclosure, referring to FIG. 9 , the display panel PNL includes two sub-panels SPNL. In other words, two sub-panels SPNL spliced ​​along a column direction together constitute the display panel PNL of this embodiment.

[0083] In one embodiment of the present disclosure, referring to FIG. 9 , the sub-panel SPNL includes two gate driving circuits GOA, which drive the scan lines GL, thereby facilitating separate scanning of odd and even rows of the scan lines GL of the sub-panel SPNL.

[0084] In one embodiment of the present disclosure, m gate drive circuits GOA are set on the sub-panel SPNL; m is a positive integer greater than 1, for example, m can be a positive integer such as 2, 3, 4, etc.; the scan line GL is divided into a plurality of sequentially adjacent scan line groups GLS, and the scan line group GLS includes m sequentially adjacent scan lines GL; the m scan lines GL in the same scan line group GLS are respectively driven by m gate drive circuits GOA.

[0085] Optionally, the number of gate driving circuits GOA on the same sub-panel SPNL may be two, three, four, etc.

[0086] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially connected along the column direction. The first sub-panel SPNL1 and the second sub-panel SPNL2 each have 180 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, the first sub-panel SPNL1 and the second sub-panel SPNL2 each have two gate drive circuits GOA. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 adjacent scan line groups GLS. Each scan line group GLS includes two adjacent scan lines GL. In other words, the scan line group GLS includes a first scan line GL1 and a second scan line GL2. Among them, the two scan lines GL in the same scan line group GLS are driven by two gate driving circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate driving circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate driving circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate driving circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate driving circuit GOA4, so as to realize the separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through the two gate driving circuits GOA, so that the scanning time difference between the 180th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL, so as to improve the display quality.

[0087] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially spliced ​​along the column direction. The number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, the first sub-panel SPNL1 and the second sub-panel SPNL2 are each provided with two gate drive circuits GOA. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 sequentially adjacent scan line groups GLS, the first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are sequentially adjacent; the 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes a first scan line GL1. Among them, except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the second gate drive circuit GOA2. It is driven by the third gate driving circuit GOA3, and the second scanning line GL2 in the same scanning line group GLS is driven by the fourth gate driving circuit GOA4; and in the first sub-panel SPNL1, the first scanning line GL1 in the 90th scanning line group GLS is driven by the first gate driving circuit GOA1; in the second sub-panel SPNL2, the first scanning line GL1 in the 90th scanning line group GLS is driven by the third gate driving circuit GOA3, so as to realize the separate scanning of the odd and even row scanning lines GL of the same sub-panel SPNL through the two gate driving circuits GOA, so that the scanning time difference between the 179th row scanning line GL of the first sub-panel SPNL1 and the first row scanning line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL, so as to improve the display quality.

[0088] In other examples, by analogy, m can be 3. In this case, three gate drive circuits GOA can be used to achieve independent scanning of the odd and even scan lines GL of the same sub-panel SPNL. That is, each scan line group GLS includes three scan lines GL, and the three scan lines GL are driven by three gate drive circuits GOA, respectively. As a result, the scanning time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is one-third of the scanning period of the sub-panel SPNL. m can be 4. In this case, four gate drive circuits GOA can be used to achieve independent scanning of the odd and even scan lines GL of the same sub-panel SPNL. As a result, the scanning time difference between the last scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is one-quarter of the scanning period of the sub-panel SPNL.

[0089] In one embodiment of the present disclosure, the gate drive circuits GOA each include a plurality of shift registers SR cascaded in sequence. The j-th scan line GL in the i-th scan line group GLS is electrically connected to the i-th shift register SR of the j-th gate drive circuit GOA; i is a positive integer, for example, i can be a positive integer of 1, 2, 3, etc.; j is a positive integer between 1 and m, for example, j can be a positive integer of 1, 2, 3, ..., m. The multiple gate drive circuits GOA on the sub-panel SPNL operate in sequence according to a preset order; wherein the output end of the last shift register SR of the gate drive circuit GOA that works first is connected to the input end of the first shift register SR of the gate drive circuit GOA that works subsequently.

[0090] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially connected along the column direction. The first sub-panel SPNL1 and the second sub-panel SPNL2 each have 180 scan lines GL, and the first sub-panel SPNL1 is positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, the first sub-panel SPNL1 and the second sub-panel SPNL2 are each provided with two gate drive circuits GOA. Each gate drive circuit GOA includes 90 shift registers SR connected in cascade, i.e., each gate drive circuit GOA includes a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., and a ninetieth shift register SR90 connected in cascade. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 scan line groups GLS that are adjacent to each other in sequence. The scan line group GLS includes two scan lines GL that are adjacent to each other in sequence. In other words, the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are adjacent to each other in sequence. The two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2. The second shift register SR2 of the gate drive circuit GOA2 is electrically connected, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2,…, the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the fourth gate drive circuit GOA4. In this way, the odd and even scan lines GL of the same sub-panel SPNL can be scanned separately by the two gate drive circuits GOA, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced ​​display panel PNL and improving the display quality.

[0091] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially spliced ​​along the column direction. The number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, the first sub-panel SPNL1 and the second sub-panel SPNL2 are each provided with two gate drive circuits GOA.The first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include 90 shift registers SR connected in cascade, that is, the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 connected in cascade, and the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include 89 shift registers SR connected in cascade, that is, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 connected in cascade. Register SR1, the second shift register SR2, the third shift register SR3, ..., the eighty-ninth shift register SR89; the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 sequentially adjacent scan line groups GLS, the first 89 scan line groups GLS include two sequentially adjacent scan lines GL, in other words, the first 89 scan line groups GLS include the first scan line GL1 and the second scan line GL2 that are sequentially adjacent; the 90th scan line group GLS includes one scan line GL, in other words, the 90th scan line group GLS includes the first scan line GL1; In the embodiment, except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2, and the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR1 of the first gate drive circuit GOA1. The first scan line GL1 in the 90th scan line group GLS is electrically connected to the ninetieth shift register SR90 of the first gate drive circuit GOA1.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4,…, the first scan line GL1 in the 90th scan line group GLS is electrically connected to the ninetieth shift register SR90 of the third gate drive circuit GOA3. In order to realize separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL through two gate drive circuits GOA, the scanning time difference between the 179th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0092] In one embodiment of the present disclosure, the gate drive circuit GOA includes a plurality of shift registers SR cascaded in sequence; in two adjacent sub-panels SPNL, the input end of the first-stage shift register SR of the first reference gate drive circuit of the former sub-panel SPNL is electrically connected to the input end of the first-stage shift register SR of the second reference gate drive circuit of the latter sub-panel SPNL; the first reference gate drive circuit of the sub-panel SPNL is the gate drive circuit GOA that drives the last row of scan lines GL of the sub-panel SPNL; the second reference gate drive circuit of the sub-panel SPNL is the gate drive circuit GOA that drives the first row of scan lines GL of the sub-panel SPNL.

[0093] In one example, the first reference gate drive circuit is the second gate drive circuit GOA2, the second reference gate drive circuit is the third gate drive circuit GOA3, and the input end of the first shift register SR1 of the second gate drive circuit GOA2 is electrically connected to the input end of the first shift register SR1 of the third gate drive circuit GOA3, so that the start signal of the second gate drive circuit GOA2 is multiplexed as the start signal of the third gate drive circuit GOA3. Compared with loading the start signal separately in the third gate drive circuit GOA3, the number of wiring is reduced, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0094] In another example, the first reference gate drive circuit is the first gate drive circuit GOA1, the second reference gate drive circuit is the third gate drive circuit GOA3, and the input end of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input end of the first shift register SR1 of the third gate drive circuit GOA3, so that the start signal of the first gate drive circuit GOA1 is multiplexed as the start signal of the third gate drive circuit GOA3. Compared with loading the start signal separately in the third gate drive circuit GOA3, the number of wiring is reduced, so that the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, and the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned at the same time, so that the scanning time difference between the 179th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0095] In one embodiment of the present disclosure, referring to Figures 9 and 11, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced ​​along the column direction; the first sub-panel SPNL1 has a first gate drive circuit GOA1 and a second gate drive circuit GOA2 for driving each of the scan lines GL; the first gate drive circuit GOA1 is used to drive the odd-numbered scan lines GL of the first sub-panel SPNL1, and the second gate drive circuit GOA2 is used to drive the even-numbered scan lines GL of the first sub-panel SPNL1; the second sub-panel SPNL2 has a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4 for driving each of the scan lines GL; the third gate drive circuit GOA3 is used to drive the odd-numbered scan lines GL of the second sub-panel SPNL2, and the fourth gate drive circuit GOA4 is used to drive the even-numbered scan lines GL of the second sub-panel SPNL2.

[0096] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 that are sequentially spliced ​​along the column direction. The number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 sequentially adjacent scan line groups GLS. The scan line group GLS includes two sequentially adjacent scan lines GL. In other words, the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are sequentially adjacent. Among them, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively, that is, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4.

[0097] In another example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially connected along the column direction. The first sub-panel SPNL1 and the second sub-panel SPNL2 each have 179 scan lines GL, with the first sub-panel SPNL1 positioned above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, while the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are each divided into 90 adjacent scan line groups GLS. The first 89 scan line groups GLS include two adjacent scan lines GL. In other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2. The 90th scan line group GLS includes a single scan line GL. In other words, the 90th scan line group GLS includes the first scan line GL1. Among them, except for the 90th scan line group GLS, in the first sub-panel SPNL1, the first scan line GL1 in the same scan line group GLS is driven by the first gate drive circuit GOA1, and the second scan line GL2 in the same scan line group GLS is driven by the second gate drive circuit GOA2; in the second sub-panel SPNL2, the first scan line GL1 in the same scan line group GLS is driven by the third gate drive circuit GOA3, and the second scan line GL2 in the same scan line group GLS is driven by the fourth gate drive circuit GOA4; and in the first sub-panel SPNL1, the first scan line GL1 in the 90th scan line group GLS is driven by the first gate drive circuit GOA1; in the second sub-panel SPNL2, the first scan line GL1 in the 90th scan line group GLS is driven by the third gate drive circuit GOA3.

[0098] In one embodiment of the present disclosure, the number of rows of the scan lines GL is an even number, for example, the number of rows of the scan lines GL may be 2, 4, 100, 180, etc. The start signal of the second gate driving circuit GOA2 of the first sub-panel SPNL1 and the start signal of the third gate driving circuit GOA3 of the second sub-panel SPNL2 are generated at the same time.

[0099] In one example, referring to Figures 9 and 10, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2, which are sequentially spliced ​​along the column direction. The number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 180 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, the first sub-panel SPNL1 and the second sub-panel SPNL2 are each provided with two gate drive circuits GOA. Each gate drive circuit GOA includes 90 shift registers SR cascaded in sequence, that is, each gate drive circuit GOA includes a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 cascaded in sequence; the scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 adjacent scan line groups GLS, and the scan line group GLS includes two adjacent scan lines GL. In other words, the scan line group GLS includes a first scan line GL1 and a second scan line GL2 that are adjacent to each other. Among them, the two scan lines GL in the same scan line group GLS are driven by two gate drive circuits GOA respectively. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2. The second shift register SR2 of the gate drive circuit GOA2 is electrically connected, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2,…, the first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the first gate drive circuit GOA1, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the second gate drive circuit GOA2.In the second sub-panel SPNL2, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4,…, the first scan line GL1 in the 90th scan line group GLS is electrically connected to the ninetieth shift register SR90 of the third gate drive circuit GOA3, and the second scan line GL2 in the 90th scan line group GLS is electrically connected to the ninetieth shift register SR90 of the fourth gate drive circuit GOA4. The input end of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input end of the first shift register SR1 of the fourth gate drive circuit GOA4, so that the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the fourth gate drive circuit GOA4 are loaded with the start signal at the same time, so that the odd-numbered scan line GL of the first sub-panel SPNL1 and the even-numbered scan line GL of the second sub-panel SPNL2 are scanned at the same time, which takes half the duration of the scan cycle; thereafter, the even-numbered scan line GL of the first sub-panel SPNL1 and the odd-numbered scan line GL of the second sub-panel SPNL2 are scanned at the same time, and this process also takes half the duration of the scan cycle; in short, the scanning time difference from the 180th row scan line GL of the first sub-panel SPNL1 to the first row scan line GL of the second sub-panel SPNL2 is half the duration of the scan cycle. In this way, the two gate drive circuits GOA can realize separate scanning of the odd and even row scan lines GL of the same sub-panel SPNL, so that the scanning time difference between the 180th row scan line GL of the first sub-panel SPNL1 and the first row scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0100] In another example, the even-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are first scanned simultaneously, and then the odd-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, so that the odd and even-numbered scan lines GL of the same sub-panel SPNL can be scanned separately through two gate drive circuits GOA, so that the scanning time difference between the 180th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced ​​display panel PNL and improving the display quality.

[0101] 9 and 13 , the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the first gate drive circuit GOA1, the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the second gate drive circuit GOA2, the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the third gate drive circuit GOA3, and the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the fourth gate drive circuit GOA4. Furthermore, the on-level start time of the first start signal GSTV1 is 1 / 2 of a scanning cycle earlier than the on-level start time of the second start signal GSTV2. In this embodiment, the on-level of the first start signal GSTV1 and the second start signal GSTV2 is low, and the off-level is high. In other embodiments of the present disclosure, the on-level of the first start signal GSTV1 and the second start signal GSTV2 is high, and the off-level is low.

[0102] In one embodiment of the present disclosure, the number of rows of the scan lines GL is an odd number; the start signal of the first gate driving circuit GOA1 of the first sub-panel SPNL1 and the start signal of the third gate driving circuit GOA3 of the second sub-panel SPNL2 are at the same time.

[0103] In one example, referring to Figures 11 and 12, the display panel PNL includes a first sub-panel SPNL1 and a second sub-panel SPNL2 sequentially spliced ​​along a column direction. The number of scan lines GL in the first sub-panel SPNL1 and the second sub-panel SPNL2 is 179 rows, and the first sub-panel SPNL1 is located above the second sub-panel SPNL2. The first sub-panel SPNL1 is provided with a first gate drive circuit GOA1 and a second gate drive circuit GOA2, and the second sub-panel SPNL2 is provided with a third gate drive circuit GOA3 and a fourth gate drive circuit GOA4. In other words, two gate drive circuits GOA are provided on the first sub-panel SPNL1 and the second sub-panel SPNL2, and the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include 90 shift registers SR cascaded in sequence, that is, the first gate drive circuit GOA1 and the third gate drive circuit GOA3 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., a ninetieth shift register SR90 cascaded in sequence, and the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include 89 shift registers SR cascaded in sequence, that is, the second gate drive circuit GOA2 and the fourth gate drive circuit GOA4 both include a first shift register SR1, a second shift register SR2, a third shift register SR3, ..., an eighty-ninth shift register SR89 cascaded in sequence. The scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are respectively divided into 90 adjacent scan line groups GLS. The first 89 scan line groups GLS include two adjacent scan lines GL. In other words, the first 89 scan line groups GLS include a first scan line GL1 and a second scan line GL2 that are adjacent to each other. The 90th scan line group GLS includes one scan line GL. In other words, the 90th scan line group GLS includes the first scan line GL1.Among them, except for the 90th scan line group GLS, the two scan lines GL in the same scan line group GLS are respectively driven by two gate drive circuits GOA. In other words, in the first sub-panel SPNL1, the first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the first gate drive circuit GOA1, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the second gate drive circuit GOA2, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the first gate drive circuit GOA1, the second scan line GL2 in the second scan line group GLS is electrically connected to the second shift register SR2 of the second gate drive circuit GOA2, the first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the first shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2, ..., the first scan line GL1 in the 90th scan line group GLS is electrically connected to the first shift register SR3 of the first gate drive circuit GOA1, the second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the second gate drive circuit GOA2, ..., The first scan line GL1 in the first scan line group GLS is electrically connected to the first shift register SR1 of the third gate drive circuit GOA3, the second scan line GL2 in the first scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4, the first scan line GL1 in the second scan line group GLS is electrically connected to the second shift register SR2 of the third gate drive circuit GOA3, and the second scan line GL2 in the second scan line group GLS is electrically connected to the first shift register SR1 of the fourth gate drive circuit GOA4. The second scan line GL2 in the line group GLS is electrically connected to the second shift register SR2 of the fourth gate drive circuit GOA4. The first scan line GL1 in the third scan line group GLS is electrically connected to the third shift register SR3 of the third gate drive circuit GOA3. The second scan line GL2 in the third scan line group GLS is electrically connected to the third shift register SR3 of the fourth gate drive circuit GOA4. ... The first scan line GL1 in the 90th scan line group GLS is electrically connected to the 90th shift register SR90 of the third gate drive circuit GOA3. The input end of the first shift register SR1 of the first gate drive circuit GOA1 is electrically connected to the input end of the first shift register SR1 of the third gate drive circuit GOA3, so that the first shift register SR1 of the first gate drive circuit GOA1 and the first shift register SR1 of the third gate drive circuit GOA3 are loaded with the same start signal.The odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, which takes half the duration of a scan cycle. Thereafter, the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, which also only takes half the duration of a scan cycle. In short, the scanning time difference from the 179th scan line GL of the first sub-panel SPNL1 to the first scan line GL of the second sub-panel SPNL2 is half the duration of a scan cycle. In this way, the odd and even scan lines GL of the same sub-panel SPNL can be scanned separately through the two gate drive circuits GOA, so that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half the duration of the sub-panel SPNL scan cycle, which helps to solve the screen tearing phenomenon of the spliced ​​display panel PNL and improve the display quality.

[0104] In another example, the even-numbered scan lines GL of the first sub-panel SPNL1 and the even-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously, and then the odd-numbered scan lines GL of the first sub-panel SPNL1 and the odd-numbered scan lines GL of the second sub-panel SPNL2 are scanned simultaneously; so that the odd and even-numbered scan lines GL of the same sub-panel SPNL can be scanned separately through two gate drive circuits GOA, so that the scanning time difference between the 179th scan line GL of the first sub-panel SPNL1 and the first scan line GL of the second sub-panel SPNL2 is half of the scanning period of the sub-panel SPNL, which is beneficial to solving the screen tearing phenomenon of the spliced ​​display panel PNL, so as to improve the display quality.

[0105] 11 and 13 , the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the first gate drive circuit GOA1, the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the second gate drive circuit GOA2, the first start signal GSTV1 is loaded at the input of the first shift register SR1 of the third gate drive circuit GOA3, and the second start signal GSTV2 is loaded at the input of the first shift register SR1 of the fourth gate drive circuit GOA4. Furthermore, the on-level start time of the first start signal GSTV1 is 1 / 2 of a scan cycle earlier than the on-level start time of the second start signal GSTV2. In this embodiment, the on-level of the first start signal GSTV1 and the second start signal GSTV2 is low, and the off-level is high. In other embodiments of the present disclosure, the on-level of the first start signal GSTV1 and the second start signal GSTV2 is high, and the off-level is low.

[0106] In one embodiment of the present disclosure, the display panel PNL is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel, or an LCD display panel. In one example, the display panel PNL is a Mini LED. In another example, the display panel PNL is a Micro LED.

[0107] In one embodiment of the present disclosure, the sub-panel SPNL has light-emitting control lines corresponding to each sub-pixel row, and the light-emitting control lines are used to load light-emitting control signals EM to the pixel driving circuit PDC; and each of the light-emitting control lines is electrically connected to each other.

[0108] Specifically, referring to FIG14 , the conduction level of the light-emitting control signal EM begins to take effect after all rows of scan lines GL have been scanned. In other words, the conduction level of the light-emitting control signal EM begins to take effect after all gate drive circuits GOA have been scanned. That is, the conduction level of the light-emitting control signal EM begins to take effect after the first gate drive circuit GOA1, the second gate drive circuit GOA2, the third gate drive circuit GOA3, and the fourth gate drive circuit GOA4 have been scanned, so that each sub-pixel PIX emits light simultaneously. It should be noted that in this embodiment, the first gate drive circuit GOA1, the second gate drive circuit GOA2, the third gate drive circuit GOA3, and the fourth gate drive circuit GOA4 shown in FIG14 are the gate drive circuits GOA corresponding to each of the four sub-panels SPNL. For example, the first sub-panel SPNL corresponds to the first gate drive circuit GOA1, the second sub-panel SPNL corresponds to the second gate drive circuit GOA2, the third sub-panel SPNL corresponds to the third gate drive circuit GOA3, and the fourth sub-panel SPNL corresponds to the fourth gate drive circuit GOA4. After all the gate drive circuits GOA of the entire display panel PNL are scanned, the light-emitting control signal EM lights up all sub-pixels PIX of the display panel PNL at the same time; the on-level of the light-emitting control signal EM is a low level, and the off-level is a high level.

[0109] In one example, after the 180 scan lines GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 are scanned, the conduction level of the light-emitting control signal EM is connected to light up all the sub-pixels PIX. In this way, there is no lighting time difference between the sub-pixels PIX of the 180th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.

[0110] In another example, after the 179th scanning line GL of the first sub-panel SPNL1 and the second sub-panel SPNL2 is scanned, the conduction level of the light-emitting control signal EM is connected to light up all the sub-pixels PIX. In this way, there is no lighting time difference between the sub-pixels PIX of the 179th row of the first sub-panel SPNL1 and the first row of the second sub-panel SPNL2, which can effectively solve the screen tearing phenomenon.

[0111] It should be noted that the method of controlling the lighting time of the sub-pixel PIX needs to be used when the scanning frequency is high, that is, it needs to be used when the display panel PNL is scanned quickly, such as a scanning frequency of 120Hz or 144Hz, etc., to avoid the shutdown time of each sub-panel SPNL in each frame being too long, which causes the human eye to recognize screen flickering.

[0112] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A display panel comprising at least two sub-panels sequentially spliced ​​along a column direction; Any of the sub-panels includes sub-pixels distributed in an array and scan lines corresponding to each sub-pixel row; The sub-panel has a plurality of gate driving circuits for driving the respective scan lines; in, In two adjacent sub-panels, the start signal of the gate drive circuit electrically connected to the last row of scan lines of the previous sub-panel is at the same time as the start signal of the gate drive circuit electrically connected to the first row of scan lines of the next sub-panel.

2. The display panel according to claim 1, wherein The display panel includes two sub-panels.

3. The display panel according to claim 1, wherein: The sub-panel includes two gate driving circuits.

4. The display panel according to claim 1, wherein: The sub-panel is provided with m gate drive circuits; m is a positive integer greater than 1; The scan lines are divided into a plurality of sequentially adjacent scan line groups, each scan line group comprising m sequentially adjacent scan lines; The m scan lines in the same scan line group are respectively driven by m gate driving circuits.

5. The display panel according to claim 4, wherein: The gate drive circuits each include a plurality of shift registers cascaded in sequence; The jth scan line in the i-th scan line group is electrically connected to the i-th shift register of the j-th gate driving circuit; j is a positive integer between 1 and m. The display panel according to claim 1 , wherein: The gate driving circuit includes a plurality of shift registers cascaded in sequence; The first reference gate driving circuit of the sub-panel is a gate driving circuit that drives the last row of scan lines of the sub-panel; the second reference gate driving circuit of the sub-panel is a gate driving circuit that drives the first row of scan lines of the sub-panel; In two adjacent sub-panels, the input end of the first stage shift register of the first reference gate driving circuit of the former sub-panel is connected to the input end of the second stage shift register of the latter sub-panel. The first stage shift register of the driving circuit is electrically connected to the input terminal.

7. The display panel according to claim 1, wherein: The display panel includes a first sub-panel and a second sub-panel sequentially spliced ​​along a column direction; The first sub-panel has a first gate driving circuit and a second gate driving circuit for driving each of the scan lines; the first gate driving circuit is used to drive the odd-numbered scan lines of the first sub-panel, and the second gate driving circuit is used to drive the even-numbered scan lines of the first sub-panel; The second sub-panel has a third gate driving circuit and a fourth gate driving circuit for driving each of the scan lines; the third gate driving circuit is used to drive the odd-numbered scan lines of the second sub-panel, and the fourth gate driving circuit is used to drive the even-numbered scan lines of the second sub-panel.

8. The display panel according to claim 7, wherein: The number of rows of scan lines of the sub-panel is an even number; the start signal of the second gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are generated at the same time.

9. The display panel according to claim 7, wherein: The number of rows of scan lines of the sub-panel is an odd number; the start signal of the first gate driving circuit of the first sub-panel and the start signal of the third gate driving circuit of the second sub-panel are generated at the same time.

10. The display panel according to any one of claims 8 to 9, wherein: A start time of the start signal of the first gate driving circuit is earlier than a start time of the start signal of the second gate driving circuit by half a scanning cycle.

11. The display panel according to any one of claims 1 to 9, wherein: The sub-panel has a light-emitting control line corresponding to each sub-pixel row, and the light-emitting control line is used to load a light-emitting control signal to the pixel driving circuit; The light-emitting control wirings are electrically connected to each other.

12. The display panel according to any one of claims 1 to 9, wherein: The display panel is a Mini LED display panel, a Micro LED display panel, an OLED display panel, a QLED display panel or an LCD display panel.

13. A display device, wherein: The display panel comprises the display panel according to any one of claims 1 to 12.

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