Level shift circuit for improving Anti-noise capability of high-voltage gate driver chip

Abstract

The present invention relates to the field of power integrated circuits, and disclosed is a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. When a high-voltage domain power rail rises rapidly, a feedback control module detects that common-mode noise is present in a signal transmission path, and outputs a feedback signal to control the load impedance of a level shift branch to be reduced, thereby reducing the amplitude and time of impact of the noise, and filtering out residual noise by a rear-stage filter circuit can ensure that the noise would not cause logic function disorder of a high-voltage domain circuit. Moreover, the time of impact of the noise can be greatly shortened due to the action of a dynamic load structure and the feedback control module, and the noise can be thoroughly filtered out by the rear-stage filter circuit. Therefore, the allowed minimum pulse width of an input signal can be effectively reduced, and a signal transmission delay can be greatly reduced.

Description

Level shift circuit improves noise immunity of high-voltage gate driver chips Technical Field

[0001] The present invention relates to the technical field of power integrated circuits, and in particular to a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip. Background Art

[0002] High-voltage gate driver chips are integrated circuits specifically designed to control high-power semiconductor devices such as high-voltage MOSFETs and IGBTs. The gate driver chip processes the low-power control signal output by the microcontroller and converts it into a high-power drive signal, effectively controlling the on and off of high-power devices. Furthermore, some gate driver chips with integrated auxiliary function modules can improve the switching performance and reliability of the driven devices. High-voltage gate driver chips are widely used in products such as motor drives, inverters, electric vehicles, and LED drivers, playing a vital role in the power electronics field.

[0003] Figure 1 shows a typical application diagram of a high-voltage gate driver chip. As a signal transmission bridge between different voltage domains, the high-voltage level shifter circuit not only transmits logic control signals from the low-voltage domain to the high-voltage domain but also ensures the integrity of the output signal. Improving the level shifter's immunity to transient noise (dV / dt noise) is a major challenge in designing a level shifter circuit. dV / dt noise is generated by sudden changes in the floating ground VSSH during the switching of the high-voltage power transistor. This noise is coupled to the high-voltage domain power rail VDDH through the bootstrap capacitor C1, and then to the internal nodes of the level shifter circuit. If appropriate measures are not taken, the level shifter circuit, affected by dV / dt noise, will output erroneous logic signals, causing overall chip failure.

[0004] Figure 2 shows a conventional level shift circuit, comprising a narrow pulse generation circuit 003, a low-voltage to high-voltage level shift branch 001, and a signal processing circuit 002. The input signals IN_S and IN_R of the low-voltage to high-voltage level shift branch 001 are two non-in-phase narrow pulse signals output by the narrow pulse generation circuit. After entering the low-voltage to high-voltage level shift branch 001, the input signals are converted to the high-voltage power rail. The output signals Set and Reset have a voltage range of VSSH to VDDH and are inverted relative to the input signals. After being shaped by the buffer circuit formed by inverters INV1 and INV2, they are input to the filtering module, where an RS flip-flop restores the signal.

[0005] However, when high-side power device T1 in Figure 1 is turned on, the VSSH and VDDH voltages rise rapidly. Due to the large drain-source parasitic capacitance of high-voltage NMOS devices HMN1 and HMN2, large parasitic capacitance exists at the output port of low-voltage-to-high-voltage level shifter branch 001. VDDH voltage transients couple noise currents through the parasitic capacitance, generating a voltage drop across resistors R1 and R2. This causes the output signals Set and Reset, which should otherwise remain high, to exhibit a common-mode negative pulse relative to VDDH. If the amplitude of the noise pulse falls below the input thresholds of inverters INV1 and INV2, inverters INV1 and INV2 will simultaneously output two positive pulse signals, causing the RS flip-flop to enter an indeterminate state. Due to semiconductor manufacturing process limitations, it is difficult to achieve perfect matching between the two branches of low-voltage-to-high-voltage level shifter branch 001. Consequently, there is a phase difference between the input signals of the RS flip-flop, ultimately leading to output errors. The specific waveforms are shown in Figure 3.

[0006] Summary of the Invention

[0007] The present invention provides a level shift circuit for improving the noise resistance of a high-voltage gate driver chip, which can effectively eliminate the problem of false triggering caused by noise, while minimizing the filtering delay and improving the reliability of the high-voltage gate driver chip.

[0008] An embodiment of the present invention provides a level shift circuit for improving the noise immunity of a high-voltage gate driver chip, comprising:

[0009] Narrow pulse generation circuit, dynamic load level shift branch, inverter, feedback control module, filter module, RS trigger;

[0010] The narrow pulse generating circuit is used to generate two narrow pulse signals according to the overall input signal IN;

[0011] The dynamic load level shifting branch is inputted with the two narrow pulse signals and the feedback control signal outputted by the feedback control module, and is used to convert the levels of the two input narrow pulse signals from the low voltage domain to the high voltage domain, and output two output signals to the feedback control module and the filtering module;

[0012] The inverter connects the dynamic load level shift branch with the feedback control module and the filtering module for waveform shaping and logic control;

[0013] The feedback control module receives input signals from the two output signals of the dynamic load level shifting branch after being processed by a first-stage inverter. The output feedback control signal is connected to the dynamic load level shifting branch. The feedback control module is configured to adjust the load impedance of the dynamic load level shifting branch using the generated feedback control signal, thereby reducing the load impedance of the dynamic load level shifting branch in the presence of noise current and thereby reducing interference of the noise current on the output voltage of the dynamic load level shifting branch.

[0014] The input signal of the filtering module is the two output signals Reset and Set of the dynamic load level shift branch respectively processed by two stages of inverters. The two output signals are connected to the RS trigger. The filtering module is used to filter out noise in the signal;

[0015] The RS trigger is used to restore two narrow pulse input signals into level signals.

[0016] In one embodiment of the present invention, the dynamic load level shifting branch includes: a first high-voltage-resistant NMOS transistor HMN1, a second high-voltage-resistant NMOS transistor HMN2, a first clamping diode Q1, a second clamping diode Q2, a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third resistor R3, and a fourth resistor R4. The dynamic load structure formed by the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first PMOS transistor MP1, and the second PMOS transistor MP2 dynamically adjusts the load impedance according to the feedback control signal FB of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2.

[0017] The connection relationship of the dynamic load level shift branch is as follows: the gate of the first high-voltage-resistant NMOS transistor HMN1 is connected to an output signal of the narrow pulse generating circuit of the previous stage, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the first clamping diode Q1, one end of the first resistor R1, one end of the third resistor R3, and the input of the first inverter INV1; the anode of the first clamping diode Q1 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the first resistor R1 is connected to the power signal VDDH of the high-voltage domain power rail; the drain of the first PMOS transistor MP1 is connected to the other end of the third resistor R3, the source is connected to the power signal VDDH of the high-voltage domain power rail, and the gate is connected to the second PMOS transistor MP 2 and the output port of the feedback control module to receive the feedback control signal of the feedback control module; the gate of the second high-voltage-resistant NMOS transistor HMN2 is connected to another output signal of the previous-stage narrow pulse generating circuit, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the second clamping diode Q2, one end of the second resistor R2, one end of the fourth resistor R4, and the input of the second inverter INV2; the anode of the clamping diode Q2 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the second resistor R2 is connected to the power supply signal VDDH of the high-voltage domain power rail; the drain of the second PMOS transistor MP2 is connected to the other end of the fourth resistor R4, and the source is connected to the power supply signal VDDH of the high-voltage domain power rail.

[0018] In one embodiment of the present invention, the feedback control module is used to detect whether common-mode noise exists in the output signals of the first inverter INV1 and the second inverter INV2. When common-mode noise exists, the feedback control module outputs a feedback control signal FB to control the gate potentials of the first PMOS transistor MP1 and the second PMOS transistor MP2 to dynamically adjust the load of the level shift branch, thereby reducing the impact of the common-mode noise current generated in the main signal path when VDDH rises rapidly on the circuit output.

[0019] The connection relationship of the feedback control module is as follows: one input port of the logic gate is connected to the output port of the first inverter INV1 and the input port of the third inverter INV3, and the other input port is connected to the output port of the second inverter INV2 and the input port of the fourth inverter INV4; the output port of the logic gate is used to output a feedback control signal, and the output port is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the ground signal VSSH of the high-voltage domain power rail; the current source port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail.

[0020] In one embodiment of the present invention, the filtering module includes two filtering circuits with identical structures. The two groups of input ports and output ports of the filtering module correspond to the input ports and output ports of the two filtering circuits, respectively. The two input ports of the filtering module are respectively connected to the output port of the third inverter INV3 and the output port of the fourth inverter INV4, and the output ports are respectively connected to the S port and R port of the RS trigger. The filtering module is used to filter out common-mode noise in the output signals of the third inverter INV3 and the fourth inverter INV4, and ensure that useful narrow pulse signals can be output normally, so that the subsequent RS trigger can correctly restore the main path signal.

[0021] In one embodiment of the present invention, the S port and R port of the RS trigger are respectively connected to the two output ports of the filtering module, the Q end serves as the output port OUT of the overall circuit, the power port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail. The RS trigger is used to convert two narrow pulse signals into a single output signal OUT, one narrow pulse signal controls the OUT signal to rise from a low level to a high level, and the other narrow pulse signal controls the OUT signal to fall from a high level to a low level. The period and pulse width of the OUT signal are consistent with the input signal IN of the narrow pulse generating circuit.

[0022] In one embodiment of the present invention, the input port of the narrow pulse generating circuit is connected to the overall circuit input signal IN, the two output ports are respectively connected to the gate of the first high-voltage-resistant NMOS transistor HMN1 and the gate of the second high-voltage-resistant NMOS transistor HMN2, the power port is connected to the power signal VDDL of the low-voltage domain power rail, and the ground port is connected to the ground signal VSSL of the low-voltage domain power rail. The narrow pulse generating circuit generates corresponding narrow pulse signals at the two output ports according to the rising edge and falling edge of the input signal IN.

[0023] In one embodiment of the present invention, the inverter includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The connection relationship is as follows: an input port of the first inverter INV1 is connected to the drain of the first high-voltage-resistant NMOS transistor HMN1, the cathode of the first clamping diode Q1, one end of the first resistor R1, and one end of the third resistor R3, and an output port is connected to the input port of the third inverter INV3 and one input port of the feedback control module; an input port of the second inverter INV2 is connected to the drain of the second high-voltage-resistant NMOS transistor HMN2, the cathode of the second clamping diode Q2, one end of the second resistor R2, and one end of the fourth resistor R4, and an output port is connected to the input port of the fourth inverter INV4 and another input port of the feedback control module; the output port of the third inverter INV3 is connected to one input port of the filter module, and the output port of the fourth inverter INV4 is connected to another input port of the filter module.

[0024] The level shift circuit for improving the noise immunity of a high-voltage gate driver chip according to an embodiment of the present invention has the following beneficial effects:

[0025] (1) Improve the anti-noise capability of the level shift circuit. When the high-voltage domain power rail rises rapidly, the feedback control module detects the presence of common-mode noise in the signal transmission path, and outputs a feedback signal to control the load impedance of the level shift branch to reduce, thereby reducing the amplitude and impact time of the noise. The remaining noise is then filtered out by the post-stage filter circuit to ensure that the noise does not affect the effective signal transmission. Compared with the traditional solution, under the premise of the same anti-noise capability, the present invention can use a filter circuit with a smaller filter width, so the delay of the level shift circuit can be greatly reduced;

[0026] (2) It can respond to input signals with smaller pulse widths. In traditional level shift circuits, when the input signal pulse width is very narrow and is smaller than the rise time of the high-voltage domain power rail power signal, the useful narrow pulse signal will be submerged in the common-mode noise. The subsequent circuit cannot distinguish whether it is a useful signal or a noise signal, so the RS trigger output signal cannot guarantee the correct restoration of the input signal. Due to the dynamic load structure and feedback control module of the present invention, the noise impact time will be greatly shortened, and the noise can be completely filtered out after passing through the subsequent filter circuit, so the minimum allowable input signal pulse width can be effectively reduced.

[0027] Additional aspects and advantages of the present invention will be set forth in part in the description which follows and, in part, will be obvious from the description which follows, or may be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the following description of the embodiments in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a typical application diagram of a high-voltage gate driver chip;

[0030] FIG2 is a structural diagram of a conventional level shift circuit;

[0031] FIG3 is a diagram showing the operating waveforms and false triggering principle of a conventional level shift circuit;

[0032] 4 is a schematic diagram of a level shift circuit structure for improving the noise immunity of a high-voltage gate driver chip according to an embodiment of the present invention;

[0033] 5 is a diagram showing a specific example of a level shift circuit for improving the noise immunity of a high-voltage gate driver chip according to an embodiment of the present invention;

[0034] FIG6 is a diagram showing a specific example of a narrow pulse generating circuit according to an embodiment of the present invention;

[0035] FIG7 is a schematic diagram of operating waveforms of a level shift circuit for improving the anti-noise capability of a high-voltage gate driver chip according to an embodiment of the present invention. DETAILED DESCRIPTION

[0036] The following describes embodiments of the present invention in detail, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present invention, and are not to be construed as limiting the present invention.

[0037] FIG4 is a schematic diagram of a level shift circuit structure for improving the anti-noise capability of a high-voltage gate driver chip according to an embodiment of the present invention.

[0038] As shown in FIG4 , the level shift circuit for improving the noise immunity of the high-voltage gate driver chip includes: a narrow pulse generating circuit 005 , a dynamic load level shift branch 001 , an inverter, a feedback control module 002 , a filtering module 003 , and an RS trigger 004 .

[0039] The narrow pulse generating circuit is used to generate two narrow pulse signals according to the overall input signal IN;

[0040] The dynamic load level shifting branch is inputted with two narrow pulse signals and the feedback control signal outputted by the feedback control module, and is used to convert the levels of the two input narrow pulse signals from the low voltage domain to the high voltage domain, and output two output signals to the feedback control module and the filtering module;

[0041] The inverter connects the dynamic load level shift branch with the feedback control module and the filtering module for waveform shaping and logic control;

[0042] The input signal of the feedback control module is a signal obtained by processing the two output signals of the dynamic load level shifting branch through a first-stage inverter. The output feedback control signal is connected to the dynamic load level shifting branch. The feedback control module is used to adjust the load impedance of the dynamic load level shifting branch using the generated feedback control signal. When a noise current exists, the load impedance of the dynamic load level shifting branch is reduced to reduce the interference of the noise current on the output voltage of the dynamic load level shifting branch.

[0043] The input signal of the filter module is the two output signals Reset and Set of the dynamic load level shift branch, which are processed by two stages of inverters. The two output signals are connected to the RS trigger. The filter module is used to filter out noise in the signal.

[0044] The RS trigger is used to restore two narrow pulse input signals to level signals.

[0045] As shown in FIG5 , in one embodiment of the present invention, a dynamic load level shifting branch includes: a first high-voltage-resistant NMOS transistor HMN1, a second high-voltage-resistant NMOS transistor HMN2, a first clamping diode Q1, a second clamping diode Q2, a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third resistor R3, and a fourth resistor R4. The dynamic load structure formed by the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first PMOS transistor MP1, and the second PMOS transistor MP2 dynamically adjusts the magnitude of the load impedance according to a feedback control signal FB of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2. When noise current interference exists, the load impedance will decrease, thereby reducing the interference of the noise current on the output voltage of the dynamic load level shifting branch.

[0046] The connection relationship of the dynamic load level shift branch is as follows: the gate of the first high-voltage-resistant NMOS transistor HMN1 is connected to an output signal of the previous-stage narrow pulse generating circuit, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the first clamping diode Q1, one end of the first resistor R1, one end of the third resistor R3, and the input of the first inverter INV1; the anode of the first clamping diode Q1 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the first resistor R1 is connected to the power signal VDDH of the high-voltage domain power rail; the drain of the first PMOS transistor MP1 is connected to the other end of the third resistor R3, the source is connected to the power signal VDDH of the high-voltage domain power rail, and the gate is connected to the second PMOS transistor MP2 and the output port of the feedback control module to receive the feedback control signal of the feedback control module; the gate of the second high-voltage-resistant NMOS transistor HMN2 is connected to another output signal of the previous-stage narrow pulse generating circuit, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the second clamping diode Q2, one end of the second resistor R2, one end of the fourth resistor R4, and the input of the second inverter INV2; the anode of the clamping diode Q2 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the second resistor R2 is connected to the power signal VDDH of the high-voltage domain power rail; the drain of the second PMOS transistor MP2 is connected to the other end of the fourth resistor R4, and the source is connected to the power signal VDDH of the high-voltage domain power rail.

[0047] In one embodiment of the present invention, the feedback control module is used to detect whether common-mode noise exists in the output signals of the first inverter INV1 and the second inverter INV2. When common-mode noise exists, the feedback control module outputs a feedback control signal FB to control the gate potentials of the first PMOS transistor MP1 and the second PMOS transistor MP2 to dynamically adjust the load of the level shift branch, thereby reducing the impact of the common-mode noise current generated in the main signal path when VDDH rises rapidly on the circuit output.

[0048] The connection relationship of the feedback control module is as follows: one input port of the logic gate is connected to the output port of the first inverter INV1 and the input port of the third inverter INV3, and the other input port is connected to the output port of the second inverter INV2 and the input port of the fourth inverter INV4; the output port of the logic gate is used to output the feedback control signal, and the output port is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the ground signal VSSH of the high-voltage domain power rail; the current source port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail.

[0049] In one embodiment of the present invention, the filtering module includes two filtering circuits with identical structures. The two groups of input ports and output ports of the filtering module correspond to the input ports and output ports of the two filtering circuits, respectively. The two input ports of the filtering module are respectively connected to the output port of the third inverter INV3 and the output port of the fourth inverter INV4, the output ports are respectively connected to the S port and R port of the RS trigger, the power port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail. The filtering module is used to filter out common-mode noise in the output signals of the third inverter INV3 and the fourth inverter INV4, and ensure that useful narrow pulse signals can be output normally, so that the subsequent RS trigger can correctly restore the main path signal.

[0050] In one embodiment of the present invention, the S port and R port of the RS trigger are respectively connected to the two output ports of the filtering module, the Q end serves as the output port OUT of the overall circuit, the power port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail. The RS trigger is used to convert two narrow pulse signals into a single output signal OUT, one narrow pulse signal controls the OUT signal to rise from a low level to a high level, and the other narrow pulse signal controls the OUT signal to fall from a high level to a low level. The period and pulse width of the OUT signal are consistent with the input signal IN of the narrow pulse generating circuit.

[0051] In one embodiment of the present invention, the input port of the narrow pulse generating circuit is connected to the overall circuit input signal IN, the two output ports are respectively connected to the gate of the first high-voltage-resistant NMOS transistor HMN1 and the gate of the second high-voltage-resistant NMOS transistor HMN2, the power port is connected to the power signal VDDL of the low-voltage domain power rail, and the ground port is connected to the ground signal VSSL of the low-voltage domain power rail. The narrow pulse generating circuit generates corresponding narrow pulse signals at the two output ports according to the rising edge and falling edge of the input signal IN.

[0052] In one embodiment of the present invention, the inverter includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The connection relationship is as follows: the input port of the first inverter INV1 is connected to the drain of the first high-voltage-resistant NMOS transistor HMN1, the cathode of the first clamping diode Q1, one end of the first resistor R1, and one end of the third resistor R3, and the output port is connected to the input port of the third inverter INV3 and one input port of the feedback control module; the input port of the second inverter INV2 is connected to the drain of the second high-voltage-resistant NMOS transistor HMN2, the cathode of the second clamping diode Q2, one end of the second resistor R2, and one end of the fourth resistor R4, and the output port is connected to the input port of the fourth inverter INV4 and another input port of the feedback control module; the output port of the third inverter INV3 is connected to one input port of the filter module, and the output port of the fourth inverter INV4 is connected to another input port of the filter module.

[0053] As shown in Figures 4 and 5, the level shift circuit is used to convert signals in the low-voltage domain to the high-voltage domain. The low-voltage domain power rail is ground signal VSSL-power signal VDDL, and the high-voltage domain power rail is floating ground signal VSSH-floating power signal VDDH.

[0054] The level shift circuit that improves the noise resistance of the high-voltage gate driver chip adds a feedback control structure 002 and a filter circuit 003 on the basis of the traditional level shift circuit, and changes the fixed impedance load of the low-voltage-high-voltage level shift branch 001 in Figure 2 to the dynamic impedance load of the dynamic load level shift branch 001 in Figure 4. The operating principle is as follows: an input signal IN enters the input port of a narrow pulse generating circuit 005. A specific embodiment of the narrow pulse generating circuit is shown in FIG6 , and comprises inverters INV11-INV16, PMOS transistors MP5 and MP6, NMOS transistors MN3 and MN4, resistors R7 and R8, capacitors C4 and C8, Schmitt triggers SMIT3 and SMIT4, and NAND gates NAND2 and NAND3. The narrow pulse generating circuit outputs two narrow pulse signals, IN_S and IN_R, corresponding to the rising and falling edges of the input signal IN, respectively. The amplitudes vary from the ground signal VSSL to the power supply signal VDDL. The IN_S and IN_R signals are then input to two input ports of a dynamic load level shifting branch 001, which are the gates of the high-voltage transistors HMN1 and HMN2, respectively. Dynamic load level-shifting branch 001 includes high-voltage NMOS transistors HMN1 and HMN2, clamping diodes Q1 and Q2, resistors R1 and R2, PMOS transistors MP1 and MP2, resistors R3 and R4. After the IN_S and IN_R signals are input to dynamic load level-shifting branch 001, the outputs are Set and Reset signals, which are inversely proportional to the IN_S and IN_R signals, respectively. The amplitudes of the Set and Reset signals range from the floating ground signal VSSH to the floating power supply signal VDDH. The dynamic load structure consists of resistors R1, R2, R3, R4, PMOS transistors MP1 and MP2.

[0055] A specific embodiment of feedback control structure 002 comprises a two-input NAND gate NAND1, a capacitor C1, and a current source I1. One input port of the two-input NAND gate NAND1 is connected to the output port of inverter INV1 and the input port of inverter INV3, while the other input port is connected to the output port of inverter INV2 and the input port of inverter INV4. The output port of NAND gate NAND1 is connected to one end of capacitor C1, the gates of PMOS transistors MP1 and MP2. NAND gate NAND1 is powered by current source I1, and the ground line of NAND gate NAND1 and the other end of capacitor C1 are connected to a floating ground signal VSSH. Adjusting the output current of current source I1 and the capacitance of capacitor C1 can adjust the speed of the rising edge of NAND gate NAND1. When there is no common-mode noise in the output signals Set and Reset of the dynamic load level shift branch 001, one of the two inputs of the NAND gate NAND1 is at a high level VDDH, the other is at a low level VSSH, or both are at a low level VSSH. At this time, the FB signal is at a high level VDDH, and the PMOS transistors MP1 and MP2 are in the off state. At this time, the two loads of the level shift branch are equal to the resistance values ​​of R1 and R2, respectively. The Set and Reset signals are transmitted normally, pass through the two-stage inverter and the filter circuit 003, and enter the RS trigger 005. The final signal is restored to the output signal OUT. However, in the actual application of high-voltage gate driver chips, when the output signal OUT becomes high, the high-side transistor T1 of the half-bridge circuit shown in Figure 1 is turned on, and the high-voltage domain power rail will rise rapidly. Due to the presence of parasitic capacitance at Set and Reset, a common-mode negative pulse (dV / dt noise) relative to VDDH will be generated at Set and Reset. At this time, both inputs of the NAND gate NAND1 are high-level VDDH, so the FB signal is low-level VSSH, and the PMOS transistors MP1 and MP2 are in the on state. As long as the resistance values ​​of R3 and R4 and the on-resistance of the PMOS transistors MP1 and MP2 are sufficiently small, the load impedance of the level shift branch will be greatly reduced, and the amplitude variation range of the common-mode negative pulse will be reduced to less than the threshold of the subsequent inverters INV1 and INV2. From the perspective of the filter module input, the erroneous common-mode negative pulse will no longer persist. Furthermore, adjusting the output current of current source I1 and the size of capacitor C1 in the feedback control structure can control the rise time of the FB signal. As long as the time it takes for the FB signal to rise from the low level VSSH to the turn-on threshold of PMOS transistors MP1 and MP2 is greater than the rise time of VDDH, the Set and Reset signals will only experience a very brief dV / dt noise during the rise of VDDH. Under these conditions, the duration of this noise is approximately equal to the response time of the feedback control module.

[0056] The Set and Reset signals, which contain extremely short dV / dt noise, are shaped by two inverters before entering filter circuit 003. This filter circuit comprises inverters INV5-INV10, PMOS transistors MP3 and MP4, NMOS transistors MN1 and MN2, resistors R5 and R6, capacitors C2 and C3, and Schmitt triggers SMIT1 and SMIT2. By employing a relatively short filter width, the filter circuit effectively filters out dV / dt noise while ensuring that valid signals pass through with low latency. Finally, the filter circuit's output signals, OUT_R and OUT_S, enter the RS flip-flop and are ultimately converted to the output signal OUT. The output signal OUT has essentially the same pulse width as the input signal IN, with a slight timing delay difference. Its amplitude ranges from the floating ground signal VSSH to the floating power supply signal VDDH, effectively converting the input signal IN from a low-voltage domain to a high-voltage domain.

[0057] Figure 7 illustrates the operating waveforms of a level shifter circuit designed to enhance the noise immunity of a high-voltage gate driver chip. As shown, the input signal IN is a pulse-width modulated signal with a relatively wide pulse width. Upon entering the narrow pulse generation circuit 005, it first outputs a narrow pulse signal IN_S corresponding to the rising edge of the input signal IN. When the IN_S pulse is generated, the high-voltage domain power rail signal VDDH rapidly rises, generating dV / dt noise at both the Set and Reset terminals. The feedback control module then responds by generating an FB signal with a pulse width greater than or equal to the VDDH rise time, adjusting the load impedance of the dynamic load level shifter branch 001. This reduces the noise width at the Set and Reset terminals, resulting in a short duration of noise input to the filter circuit 003. At nodes A1 and A2 of the filter circuit 003, the signal rises faster than it falls due to the effects of resistors R5, R6, capacitors C2, and C3. During the noise duration, the voltages at nodes A1 and A2 rise slowly. By selecting appropriate resistor and capacitor values, the voltages at nodes A1 and A2 can be prevented from rising to the rising thresholds V of the subsequent Schmitt triggers SMIT1 and SMIT2. th+ , the noise ends, and the voltages at nodes A1 and A2 drop rapidly. Therefore, during the duration of the dV / dt noise, the Schmitt triggers SMIT1 and SMIT2 still output a constant high signal and do not flip, which means that the dV / dt noise is filtered out. For valid signals, because the pulse width of the valid signal is large, at nodes A1 and A2, the signal has enough time to rise to the rising threshold V of the subsequent Schmitt trigger. th+, so the Schmitt trigger output flips, allowing the valid signal to pass normally. Finally, the filter module outputs a valid OUT_S signal, which enters the set terminal of the RS flip-flop. The RS flip-flop's output signal OUT flips from a low level, VSSH, to a high level, VDDH, corresponding to the rising edge of the input signal, IN. The analysis of the output signal OUT flipping from a high level, VDDH, to a low level, VSSH, is similar to the above analysis. Finally, the pulse widths of the output signal OUT and the input signal, IN, are essentially the same, with a slight delay difference in timing. The amplitude ranges from the floating ground signal, VSSH, to the floating power supply signal, VDDH, achieving signal conversion from the low-voltage domain to the high-voltage domain.

[0058] According to an embodiment of the present invention, a level shifting circuit for improving the noise immunity of a high-voltage gate driver chip is proposed. When the high-voltage domain power rail rises rapidly, the feedback control module detects the presence of common-mode noise in the signal transmission path and outputs a feedback signal to control the load impedance of the level shifting branch to decrease, thereby reducing the amplitude and duration of the noise impact. The remaining noise is then filtered out by a post-stage filtering circuit to ensure that the noise does not disrupt the logical function of the high-voltage domain circuit. Due to the dynamic load structure and the effects of the feedback control module, the noise impact time is greatly shortened. The noise is then completely filtered out by the post-stage filtering circuit, effectively reducing the minimum allowable input signal pulse width and significantly reducing signal transmission delay.

[0059] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any one or N embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification and features of different embodiments or examples without contradiction.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "N" means at least two, such as two, three, etc., unless otherwise specifically defined.

Claims

1. A level shift circuit for improving the noise immunity of a high-voltage gate driver chip, characterized in that: include: Narrow pulse generation circuit, dynamic load level shift branch, inverter, feedback control module, filter module, RS trigger; The narrow pulse generating circuit is used to generate two narrow pulse signals according to the overall input signal IN; The dynamic load level shifting branch is inputted with the two narrow pulse signals and the feedback control signal outputted by the feedback control module, and is used to convert the levels of the two input narrow pulse signals from the low voltage domain to the high voltage domain, and output two output signals to the feedback control module and the filtering module; The inverter connects the dynamic load level shift branch with the feedback control module and the filtering module for waveform shaping and logic control; The feedback control module receives input signals from the two output signals of the dynamic load level shifting branch after being processed by a first-stage inverter. The output feedback control signal is connected to the dynamic load level shifting branch. The feedback control module is configured to adjust the load impedance of the dynamic load level shifting branch using the generated feedback control signal, thereby reducing the load impedance of the dynamic load level shifting branch in the presence of noise current and thereby reducing interference of the noise current on the output voltage of the dynamic load level shifting branch. The input signal of the filtering module is the two output signals Reset and Set of the dynamic load level shift branch respectively processed by two stages of inverters. The two output signals are connected to the RS trigger. The filtering module is used to filter out noise in the signal; The RS trigger is used to restore two narrow pulse input signals into level signals.

2. The circuit according to claim 1, wherein: The dynamic load level shifting branch includes: a first high-voltage-resistant NMOS transistor HMN1, a second high-voltage-resistant NMOS transistor HMN2, a first clamping diode Q1, a second clamping diode Q2, a first resistor R1, a second resistor R2, a first PMOS transistor MP1, a second PMOS transistor MP2, a third resistor R3, and a fourth resistor R4. The dynamic load structure formed by the first resistor R1, the second resistor R2, the third resistor R3, the fourth resistor R4, the first PMOS transistor MP1, and the second PMOS transistor MP2 dynamically adjusts the load impedance according to the feedback control signal FB of the gates of the first PMOS transistor MP1 and the second PMOS transistor MP2. The connection relationship of the dynamic load level shift branch is as follows: the gate of the first high-voltage-resistant NMOS transistor HMN1 is connected to an output signal of the narrow pulse generating circuit of the previous stage, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the first clamping diode Q1, one end of the first resistor R1, one end of the third resistor R3, and the input of the first inverter INV1; the anode of the first clamping diode Q1 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the first resistor R1 is connected to the power signal VDDH of the high-voltage domain power rail; the first PMOS The drain of transistor MP1 is connected to the other end of the third resistor R3, the source is connected to the power supply signal VDDH of the high-voltage domain power rail, and the gate is connected to the gate of the second PMOS transistor MP2 and the output port of the feedback control module to receive the feedback control signal of the feedback control module; the gate of the second high-voltage-resistant NMOS transistor HMN2 is connected to another output signal of the preceding narrow pulse generating circuit, the source is connected to the ground signal VSSL of the low-voltage domain power rail, and the drain is connected to the cathode of the second clamping diode Q2, one end of the second resistor R2, one end of the fourth resistor R4, and the input of the second inverter INV2; the anode of the clamping diode Q2 is connected to the ground signal VSSH of the high-voltage domain power rail; the other end of the second resistor R2 is connected to the power supply signal VDDH of the high-voltage domain power rail; the drain of the second PMOS transistor MP2 is connected to the other end of the fourth resistor R4, and the source is connected to the power supply signal VDDH of the high-voltage domain power rail.

3. The circuit according to claim 2, characterized in that The feedback control module is used to detect whether common-mode noise exists in the output signals of the first inverter INV1 and the second inverter INV2. When common-mode noise exists, the feedback control module outputs a feedback control signal FB to control the gate potentials of the first PMOS transistor MP1 and the second PMOS transistor MP2, so as to dynamically adjust the load of the level shift branch, thereby reducing the impact of the common-mode noise current generated in the main signal path when VDDH rises rapidly on the circuit output; The connection relationship of the feedback control module is as follows: one input port of the logic gate is connected to the output port of the first inverter INV1 and the input port of the third inverter INV3, and the other input port is connected to the output port of the second inverter INV2 and the input port of the fourth inverter INV4; the output port of the logic gate is used to output a feedback control signal, and the output port is connected to the gate of the first PMOS transistor MP1, the gate of the second PMOS transistor MP2 and one end of the first capacitor C1, and the other end of the first capacitor C1 is connected to the ground signal VSSH of the high-voltage domain power rail; the current source port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail.

4. The circuit according to claim 3, characterized in that The filtering module includes two filtering circuits with identical structures. The two groups of input ports and output ports of the filtering module correspond to the input ports and output ports of the two filtering circuits, respectively. The two input ports of the filtering module are respectively connected to the output port of the third inverter INV3 and the output port of the fourth inverter INV4, and the output ports are respectively connected to the S port and R port of the RS trigger. The filtering module is used to filter out common-mode noise in the output signals of the third inverter INV3 and the fourth inverter INV4, and ensure that useful narrow pulse signals can be output normally, so that the subsequent RS trigger can correctly restore the main path signal.

5. The circuit according to claim 1, wherein: The S port and R port of the RS trigger are respectively connected to the two output ports of the filtering module, the Q end serves as the output port OUT of the overall circuit, the power port is connected to the power signal VDDH of the high-voltage domain power rail, and the ground port is connected to the ground signal VSSH of the high-voltage domain power rail. The RS trigger is used to convert two narrow pulse signals into a single output signal OUT, one narrow pulse signal controls the OUT signal to rise from a low level to a high level, and the other narrow pulse signal controls the OUT signal to fall from a high level to a low level. The period and pulse width of the OUT signal are consistent with the input signal IN of the narrow pulse generating circuit.

6. The circuit according to claim 2, characterized in that The input port of the narrow pulse generating circuit is connected to the overall circuit input signal IN, the two output ports are respectively connected to the gate of the first high-voltage-resistant NMOS transistor HMN1 and the gate of the second high-voltage-resistant NMOS transistor HMN2, the power port is connected to the power signal VDDL of the low-voltage domain power rail, and the ground port is connected to the ground signal VSSL of the low-voltage domain power rail. The narrow pulse generating circuit generates corresponding narrow pulse signals at the two output ports according to the rising edge and falling edge of the input signal IN.

7. The circuit according to claim 2, characterized in that The inverter includes a first inverter INV1, a second inverter INV2, a third inverter INV3, and a fourth inverter INV4. The connection relationship is as follows: the input port of the first inverter INV1 is connected to the drain of the first high-voltage-resistant NMOS transistor HMN1, the cathode of the first clamping diode Q1, one end of the first resistor R1, and one end of the third resistor R3, and the output port is connected to the input port of the third inverter INV3 and one input port of the feedback control module; the input port of the second inverter INV2 is connected to the drain of the second high-voltage-resistant NMOS transistor HMN2, the cathode of the second clamping diode Q2, one end of the second resistor R2, and one end of the fourth resistor R4, and the output port is connected to the input port of the fourth inverter INV4 and another input port of the feedback control module; the output port of the third inverter INV3 is connected to one input port of the filter module, and the output port of the fourth inverter INV4 is connected to another input port of the filter module.

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