Transmission network chip, network device, and bit stream processing method

Abstract

The present disclosure belongs to the technical field of communication, and provides a transmission network chip, a network device, and a bit stream processing method. The transmission network chip comprises multiple reconfigurable modules, the multiple reconfigurable modules having a specified connection relationship, each reconfigurable module being used for executing sub-processing in protocol processing, and each reconfigurable module comprising a control unit and a data processing unit. The control unit is used to, on the basis of transmission protocols and contexts of various service flows in a currently received bit stream, generate control parameters corresponding to the various service flows, and send the control parameters to the data processing unit. The data processing unit is used to receive the bit stream, perform specified sub-processing on the various service flows on the basis of the control parameters corresponding to the various service flows, to obtain a processed bit stream, and output the processed bit stream. In the present disclosure, an overall processing function of a reconfigurable module dynamically changes, so that bit streams of multiple transmission protocols share a circuit, thereby supporting transmission protocol evolution.

Description

Transmission network chip, network device and method for processing bit stream

[0001] This application claims priority to a Chinese patent application filed on February 29, 2024, with application number 202410235729.0 and entitled “Transmission network chip, network device and method for processing bit stream”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of communication technology, and in particular to a transmission network chip, a network device, and a method for processing a bit stream. Background Art

[0003] In transmission networks, network devices process continuous bit streams, placing high demands on real-time processing and accuracy. Application-specific integrated circuit (ASIC) chips typically offer excellent functionality, performance, and area, making them the preferred chips for network devices.

[0004] In transport networks, multiple transport protocols coexist. The ASIC chips in network equipment (called transport network chips) must be hardened with functional circuits corresponding to each transport protocol to support these multiple protocols. Therefore, when an existing transport protocol is improved or a new one is added, the ASIC chip may not have the corresponding functional circuits, so the chip must be replaced. Summary of the Invention

[0005] The present disclosure provides a transmission network chip, a network device, and a method for processing a bit stream, which can eliminate the need to replace the transmission network chip when the original transmission protocol is improved or a new transmission protocol is added.

[0006] In the first aspect, the present disclosure provides a transmission network chip, which includes multiple reconfigurable modules, and the multiple reconfigurable modules have a specified connection relationship. Each reconfigurable module is used to perform sub-processing in protocol processing, and the protocol processing is the protocol processing performed by the transmission network chip on the input bit stream. Each reconfigurable module includes a control unit and a data processing unit. The control unit is used to generate control parameters corresponding to various business flows in the bit stream currently received by the reconfigurable module based on the transmission protocol and context of the various business flows, and send the control parameters to the data processing unit in the reconfigurable module. For each business flow, the control parameters corresponding to the business flow are used to indicate to perform specified sub-processing on the business flow. The data processing unit in the reconfigurable module is used to receive the bit stream, perform specified sub-processing on the various business flows based on the control parameters corresponding to the various business flows, obtain a processed bit stream, and output the processed bit stream.

[0007] In the solution disclosed herein, the transmission network chip includes multiple reconfigurable modules, each of which performs sub-processing within the protocol processing. Each reconfigurable module includes a control unit and a data processing unit. Within each reconfigurable module, bitstream processing is broken down into two parts: the data processing action itself and the calculation of control parameters for the processing action. The control unit dynamically changes the overall processing function of the reconfigurable module by recalculating the control parameters in real time, combining the functions of the data processing unit. This enables bitstreams of multiple transmission protocols to share circuits, supports transmission protocol evolution, and reduces chip area and cost.

[0008] In an optional manner, the multiple reconfigurable modules include at least one first reconfigurable module, a second reconfigurable module, at least one group of third reconfigurable modules, a fourth reconfigurable module and at least one fifth reconfigurable module. The first reconfigurable module is connected to the input interface of the transmission network chip, different first reconfigurable modules are connected to different input interfaces, the first reconfigurable module is connected to the second reconfigurable module, the second reconfigurable module is connected to at least one group of third reconfigurable modules, the third reconfigurable modules in each group of third reconfigurable modules are connected in series, each group of third reconfigurable modules is connected to another group of third reconfigurable modules, or is connected to the fourth reconfigurable module, the fourth reconfigurable module is connected to the fifth reconfigurable module, the fifth reconfigurable module is connected to the output interface of the transmission network chip, different fifth reconfigurable modules are connected to different output interfaces, the sub-processing used to execute by the first reconfigurable module and the second reconfigurable module belongs to input interface side processing, the sub-processing used to execute by each group of third reconfigurable modules belongs to data path processing, and the sub-processing used to execute by the fourth reconfigurable module and the fifth reconfigurable module belongs to output interface side processing.

[0009] In the solution shown in the present disclosure, multiple reconfigurable modules are divided into three categories, and the three categories of reconfigurable modules respectively perform input interface side processing, data path processing and output interface side processing.

[0010] In an optional manner, the at least one first reconfigurable module includes multiple first reconfigurable modules, the at least one fifth reconfigurable module includes multiple fifth reconfigurable modules, and the transmission network chip also includes a first serial-to-parallel converter and a second serial-to-parallel converter, the first serial-to-parallel converter is connected to each first reconfigurable module and to the second reconfigurable module; the second serial-to-parallel converter is connected to each fifth reconfigurable module and to the fourth reconfigurable module; the first serial-to-parallel converter is used to receive multiple bit streams from the multiple first reconfigurable modules, merge the multiple bit streams into one bit stream, and output it to the second reconfigurable module; the second serial-to-parallel converter is used to receive a bit stream from the fourth reconfigurable module and distribute it to the multiple fifth reconfigurable modules.

[0011] In the solution disclosed herein, a first serial-to-parallel converter is used to combine the bit streams input from multiple input interfaces into a single bit stream, thereby converging the multiple input interfaces onto a single data bus. A second serial-to-parallel converter is used to distribute the single bit stream to multiple output interfaces for output.

[0012] In an optional embodiment, the transmission network chip also includes a first bus adapter, a second bus adapter and a bus; the first bus adapter and the second bus adapter are both connected to the bus, the first bus adapter is connected to the second reconfigurable module, the second bus adapter is connected to the fourth reconfigurable module, and each group of third reconfigurable modules is connected to the bus; the first bus adapter is used to distribute each business flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules through the bus; the second bus adapter is used to receive the bit stream from the at least one group of third reconfigurable modules through the bus, merge the received bit streams into one bit stream, and output it to the fourth reconfigurable module.

[0013] In the solution shown in the present disclosure, the transmission network chip also includes a bus adapter, so that the bit stream output by the second reconfigurable module is transmitted to the third reconfigurable module through the bus, and the bit stream output by the third reconfigurable module is transmitted to the fourth reconfigurable module through the bus to perform output interface side processing.

[0014] In an optional manner, the first bus adapter is used to determine the target group number corresponding to the number of each business flow in the first bit stream in the correspondence between the business flow number and the group number, and distribute each business flow in the first bit stream to the third reconfigurable module corresponding to the target group number through the bus.

[0015] In the solution shown in the present disclosure, the first bus adapter distributes the received service flows to the corresponding third reconfigurable modules using the correspondence between the service flow numbers and the group numbers.

[0016] In an optional embodiment, the transmission network chip also includes at least one group of bus adapters, which correspond one-to-one to the at least one group of third reconfigurable modules, and each group of bus adapters includes a third bus adapter and a fourth bus adapter; in each group of third reconfigurable modules, the third bus adapter is connected to the first third reconfigurable module and the bus respectively, and the fourth bus adapter is connected to the last third reconfigurable module and the bus respectively; the third bus adapter is used to obtain a bit stream sent to the first third reconfigurable module from the bus and send it to the first third reconfigurable module; the fourth bus adapter is used to receive a bit stream from the last third reconfigurable module and send it to the bus.

[0017] In the solution shown in the present disclosure, the transmission network chip also includes a bus adapter, so that the bit stream output by the second reconfigurable module is transmitted to the third reconfigurable module through the bus, and the bit stream output by the third reconfigurable module is transmitted to the fourth reconfigurable module through the bus to perform output interface side processing.

[0018] In an optional manner, the control unit is used to determine, for each service flow in the currently received bit stream, a processing instruction corresponding to the transmission protocol of the service flow, and determine a control parameter corresponding to the service flow based on the processing instruction and the context of the service flow.

[0019] In the solution shown in the present disclosure, the control unit uses the transmission protocol of the business flow to drive the replacement of different processing instructions, thereby generating control parameters corresponding to the business flow.

[0020] In an optional manner, the control unit is further configured to update the context of the various service flows, so that the latest context can be obtained when the same service flow is received next time.

[0021] In an optional manner, different service flows have different target attributes, and the target attribute includes one or more of a user, a port, or an Ethernet virtual local area network (VLAN) identifier.

[0022] In an optional manner, the control unit is also used to receive control information output by the control unit of the previous reconfigurable module, where the control information includes the transmission protocol and numbering of the various business flows; and determine the context of the various business flows based on the numbers of the various business flows.

[0023] In the solution shown in the present disclosure, the reconfigurable module stores the correspondence between the service flow number and the context, and the context of each service flow is determined in the correspondence based on the number in the control information output by the previous reconfigurable module.

[0024] In an optional manner, the transmission network chip also includes a management module and a bus, and the management module is connected to each reconfigurable module through the bus; the management module is used to send service flow division indication information to each reconfigurable module through the bus; the control unit is also used to determine the various service flows in the currently received bit stream based on the service flow division indication information.

[0025] In the solution shown in the present disclosure, the transmission network chip further includes a management module and a bus, and the management module controls each reconfigurable module through the bus.

[0026] In an optional manner, for the reconfigurable module for performing data path processing among the multiple reconfigurable modules, the control unit is also used to send the first overhead in the currently received bit stream to the management module through the bus; the management module is also used to determine the status of the currently received bit stream based on the first overhead.

[0027] In the solution shown in the present disclosure, when performing protocol processing, it is possible to extract the overhead in the bit stream and determine the status of the bit stream.

[0028] In an optional manner, for the reconfigurable module for performing data path processing among the multiple reconfigurable modules, the control unit is further used to, when determining to perform encapsulation processing on the currently received bit stream, send an overhead acquisition request to the management module through the bus; the management module is further used to receive the overhead acquisition request, generate a second overhead, and send the second overhead to the control unit through the bus; the control unit is further used to send the second overhead and an insertion position to the data processing unit of the reconfigurable module to which it belongs; the data processing unit of the reconfigurable module is further used to insert the second overhead into the currently received bit stream at the insertion position.

[0029] In the solution shown in the present disclosure, when encapsulating a bitstream, the reconfigurable module can obtain overhead from the management module, insert the overhead into a specified position in the bitstream, and encapsulate the bitstream.

[0030] In a second aspect, the present disclosure provides a network device, which includes the transmission network chip as described in the first aspect and the optional manner.

[0031] In a third aspect, the present disclosure provides a method for processing a bitstream, which is applied to a transmission network chip. The transmission network chip includes multiple reconfigurable modules, the multiple reconfigurable modules have a specified connection relationship, each reconfigurable module is used to perform a sub-processing in a protocol processing, the protocol processing is the protocol processing performed by the transmission network chip on the input bitstream, and each reconfigurable module includes a control unit and a data processing unit;

[0032] The control unit generates control parameters corresponding to various service flows in a bit stream currently received by the reconfigurable module based on the transmission protocols and contexts of the various service flows, and sends the control parameters to the data processing unit in the reconfigurable module. For each service flow, the control parameter corresponding to the service flow is used to instruct to perform a specified sub-processing on the service flow;

[0033] The data processing unit in the reconfigurable module receives the bit stream, performs specified sub-processing on the various service flows based on the control parameters corresponding to the various service flows, obtains a processed bit stream, and outputs the processed bit stream.

[0034] In an optional manner, the plurality of reconfigurable modules include at least one first reconfigurable module, a second reconfigurable module, at least one group of third reconfigurable modules, a fourth reconfigurable module and at least one fifth reconfigurable module;

[0035] The first reconfigurable module is connected to the input interface of the transmission network chip, different first reconfigurable modules are connected to different input interfaces, the first reconfigurable module is connected to the second reconfigurable module, the second reconfigurable module is connected to at least one group of third reconfigurable modules, the third reconfigurable modules in each group of third reconfigurable modules are connected in series, each group of third reconfigurable modules is connected to another group of third reconfigurable modules, or is connected to the fourth reconfigurable module, the fourth reconfigurable module is connected to the fifth reconfigurable module, the fifth reconfigurable module is connected to the output interface of the transmission network chip, and different fifth reconfigurable modules are connected to different output interfaces;

[0036] The sub-processing executed by the first reconfigurable module and the second reconfigurable module belongs to the input interface side processing;

[0037] The sub-processing executed by each group of third reconfigurable modules belongs to data path processing;

[0038] The sub-processing executed by the fourth reconfigurable module and the fifth reconfigurable module belongs to output interface side processing.

[0039] In an optional manner, the at least one first reconfigurable module includes a plurality of first reconfigurable modules, the at least one fifth reconfigurable module includes a plurality of fifth reconfigurable modules, and the transmission network chip further includes a first serial-to-parallel converter and a second serial-to-parallel converter;

[0040] The first serial-to-parallel converter is connected to each first reconfigurable module and to the second reconfigurable module;

[0041] The second serial-to-parallel converter is connected to each fifth reconfigurable module and to the fourth reconfigurable module;

[0042] The method further includes:

[0043] The first serial-to-parallel converter receives a plurality of bit streams from the plurality of first reconfigurable modules, combines the plurality of bit streams into one bit stream, and outputs the bit stream to the second reconfigurable module;

[0044] The second serial-to-parallel converter receives a bit stream from the fourth reconfigurable module and distributes the bit stream to the plurality of fifth reconfigurable modules.

[0045] In an optional manner, the transmission network chip further includes a first bus adapter, a second bus adapter and a bus;

[0046] The first bus adapter and the second bus adapter are both connected to the bus, the first bus adapter is connected to the second reconfigurable module, the second bus adapter is connected to the fourth reconfigurable module, and each group of third reconfigurable modules is connected to the bus;

[0047] The method further includes:

[0048] The first bus adapter distributes each service flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules via the bus;

[0049] The second bus adapter receives bit streams from the at least one group of third reconfigurable modules through the bus, merges the received bit streams into one bit stream, and outputs the bit stream to the fourth reconfigurable module.

[0050] In an optional manner, the first bus adapter distributes each service flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules via the bus, including:

[0051] The first bus adapter determines, in the correspondence between the service flow numbers and the group numbers, a target group number corresponding to the number of each service flow in the first bit stream from the second reconfigurable module;

[0052] Each service flow in the first bit stream is distributed to the third reconfigurable module corresponding to the target group number through the bus.

[0053] In an optional manner, the control unit generates control parameters corresponding to various service flows based on the transmission protocols and contexts of the various service flows in the bit stream currently received by the reconfigurable module, including:

[0054] The control unit determines, for each service flow in the currently received bit stream, a processing instruction corresponding to the transmission protocol of the service flow, and determines a control parameter corresponding to the service flow based on the processing instruction and the context of the service flow.

[0055] In an optional manner, the method further includes:

[0056] The control unit receives control information output by the control unit of the previous reconfigurable module, where the control information includes the transmission protocols and numbers of the various service flows;

[0057] Based on the numbers of the various service flows, the contexts of the various service flows are determined.

[0058] In an optional manner, the transmission network chip further includes a management module and a bus, and the management module is connected to each reconfigurable module via the bus;

[0059] The method further includes:

[0060] The management module sends service flow division indication information to each reconfigurable module via the bus;

[0061] The control unit determines various service flows in the currently received bit stream based on the service flow division indication information. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic structural diagram of a transmission network chip provided by an exemplary embodiment of the present disclosure;

[0063] FIG2 is a schematic diagram of a structure in which a control plane and a data plane are separated in a reconfigurable module according to an exemplary embodiment of the present disclosure;

[0064] FIG3 is a schematic structural diagram of a control unit provided by an exemplary embodiment of the present disclosure;

[0065] FIG4 is a schematic diagram of a data processing operator provided by an exemplary embodiment of the present disclosure;

[0066] FIG5 is another schematic diagram of the structure of a transmission network chip provided by an exemplary embodiment of the present disclosure;

[0067] FIG6 is another schematic diagram of the structure of a transmission network chip provided by an exemplary embodiment of the present disclosure;

[0068] FIG7 is a schematic diagram of an optical channel data unit (ODU) frame structure provided by an exemplary embodiment of the present disclosure;

[0069] FIG8 is a schematic structural diagram of a management module provided by an exemplary embodiment of the present disclosure;

[0070] FIG9 is a schematic diagram of the structure of an input processing component provided by an exemplary embodiment of the present disclosure;

[0071] FIG10 is a schematic diagram of the structure of a data path processing component provided by an exemplary embodiment of the present disclosure;

[0072] FIG11 is a schematic diagram of the structure of an output processing component provided by an exemplary embodiment of the present disclosure;

[0073] FIG12 is a schematic diagram of a small bandwidth topology connection of a transmission network chip provided by an exemplary embodiment of the present disclosure;

[0074] FIG13 is a schematic diagram of a high-bandwidth topological link of a transmission network chip provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0075] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0076] In transport networks, transport layer services are processed on continuous bit streams, placing extremely high demands on real-time and deterministic processing. This is often implemented using ASIC chips (i.e., transport network chips) or field-programmable gate arrays (FPGAs). ASIC chips typically offer excellent functionality, performance, and area, making them the preferred choice for network equipment. However, the coexistence of multiple transport protocols in transport networks requires ASIC chips to have hardened functional circuits corresponding to these protocols to support them. Consequently, when existing or new transport protocols are improved, the ASIC chips must be replaced because the corresponding functional circuits do not exist, hindering the evolution of transport protocols. FPGA chips, based on bit-level programmability, enable arbitrary gate-level programmability, offering greater flexibility. However, they typically utilize an area more than seven times larger than ASIC chips to achieve the same functionality, resulting in a higher cost.

[0077] Based on this, an embodiment of the present disclosure provides a transmission network chip, which is implemented based on a reconfigurable module. The reconfigurable module includes a control unit and a data processing unit. In the reconfigurable module, the processing of the bit stream is decomposed into two parts, the processing action of the data itself and the calculation of the processing action control parameters. The control unit dynamically changes the overall processing function of the reconfigurable module by real-time recalculation of the control parameters combined with the functions of the data processing unit, enabling the bit streams of multiple transmission protocols to share circuits, support the evolution of transmission protocols, and reduce the area and cost of the chip.

[0078] In an embodiment of the present disclosure, a transmission network chip is provided, which is applied to network equipment of a transmission network, including optical transport network (OTN) equipment, etc. The transmission protocols include but are not limited to OTN protocol, synchronous digital hierarchy (SDH) protocol, optical service unit (OSU) protocol and fine grain OTN protocol, etc. The transmission network chip mainly schedules the received bit stream, converts and encapsulates the protocol. For example, when entering the OTN network, the bit stream is loaded into the frame structure defined by the ONT protocol, so that the bit stream can be transmitted in the ONT network. When transmitting in the OTN network, the service flow in the bit stream is scheduled, overhead monitoring is performed, and bit error monitoring is performed.

[0079] Figure 1 provides a schematic diagram of the structure of a transmission network chip. Referring to Figure 1, the transmission network chip includes multiple reconfigurable modules, and the multiple reconfigurable modules have a specified connection relationship. The processing performed by the transmission network chip on the bit stream input to itself is called protocol processing. Each reconfigurable module is used to perform sub-processing in the protocol processing. For example, protocol processing includes but is not limited to data sliding, interleaving, multiplexing, demultiplexing, and overhead processing, and sub-processing is interleaving, multiplexing, demultiplexing, or overhead extraction and insertion processing. Among the multiple reconfigurable modules, there may be reconfigurable modules that perform the same sub-processing, or there may not be reconfigurable modules that perform the same sub-processing. Each reconfigurable module includes a control unit and a data processing unit. The control unit is electrically connected to the data processing unit, and the control unit can be a highly flexible processor.

[0080] For each reconfigurable module, the control unit determines the various service flows in the bit stream currently received by the reconfigurable module, and then determines the transmission protocol and context of the various service flows. For each service flow, based on the transmission protocol and context of the service flow, it generates control parameters corresponding to the service flow. The control unit sends the control parameters corresponding to the various service flows to the data processing unit. The data processing unit receives the bit stream input into the reconfigurable module and receives the control parameters corresponding to the various service flows sent by the control unit. For each service flow, the data processing unit performs specified sub-processing on the service flow based on the control parameters corresponding to the service flow, obtains a processed bit stream, and outputs the processed bit stream to the next reconfigurable module, or outputs the processed bit stream from the transmission network chip.

[0081] It should be noted that different reconfigurable modules execute different sub-processes, and the same reconfigurable module also executes different sub-processes based on different control parameters. For example, for the same reconfigurable module, if a bit is shifted and the control parameter is a first value, the sub-process executed is a 3-bit shift, while the sub-process executed is a 4-bit shift when the control parameter is a second value.

[0082] In an optional manner, referring to FIG2 , the bit stream received by the reconfigurable module is directly sent to the data processing unit without passing through the control unit, and the control information between the reconfigurable modules is sent to the control unit without passing through the data processing unit, which is equivalent to separating the control plane from the data plane.

[0083] In an optional manner, a service flow refers to a stream composed of bits having a certain specified attribute (such as a target attribute), and the target attributes of different service flows are different. The target attribute includes one or more of the user, the port, the Ethernet VLAN identifier, and the specified logical identifier. The user may include a sending user and / or a receiving user. The port may be the input interface of the transmission network chip, or the port of the upstream device of the network device to which the transmission network chip belongs, or the port of the downstream device of the network device. For example, if the target attribute includes the user and the port, then the sending user and / or the receiving user of different service flows are different, or the sending port and / or the receiving port of different service flows are different.

[0084] It should be noted that, when the port is an input interface of a transmission network chip, the bit stream received by one input port is one service flow.

[0085] In an optional manner, the control unit determines the control parameters corresponding to the service flow in the following process:

[0086] In general, the control unit is programmable based on processing instructions, is responsible for the real-time calculation of control parameters, and calls different processing instructions based on the transmission protocol. For each reconfigurable module, the control unit is configured with processing instructions corresponding to the transmission protocol. For example, the control unit is configured with a correspondence between the transmission protocol and the processing instructions, or the control unit is configured with a processing instruction set, and each processing instruction in the processing instruction set corresponds to a transmission protocol. Assuming that the reconfigurable module receives a target bit stream, for each service flow in the target bit stream, the processing instruction corresponding to the transmission protocol of the service flow is determined from the stored processing instructions, and then the control parameters corresponding to the service flow are determined using the processing instruction and the context of the service flow.

[0087] Optionally, Figure 3 provides a structural schematic diagram of the control unit. Referring to Figure 3, the control unit includes an instruction memory, a context memory and an arithmetic and logic unit (ALU) array. The instruction memory is used to store configured processing instructions, and the context memory is used to store the context of various business flows. For a certain business flow, the ALU array is used to use the processing instructions and the context of the business flow to calculate the control parameters corresponding to the business flow.

[0088] Alternatively, the control parameter may be a vector or the like.

[0089] Optionally, the control unit receives control information output by the control unit of the previous reconfigurable module, where the control information includes information such as the transmission protocol and number of the service flow processed by the previous reconfigurable module. A context memory stores a correspondence between the number and the context. For each service flow, the control unit uses the service flow number to determine the context of the service flow in the context memory.

[0090] Optionally, the context includes configuration information and state information from the previous processing. For example, configuration information includes constant parameters such as the length of the frame structure and the length of the overhead area during framing. This configuration information can be configured by the management module described later. In some cases, no configuration information may exist. If the previous processing was a shift to bit 50, the next processing will start from bit 50.

[0091] Optionally, after determining the control parameters corresponding to the service flow, the control unit also updates the state information of the last processing in the context to the state information of the current processing, and stores the updated context in the context memory. In this way, the latest context can be obtained every time.

[0092] Optionally, the transmission network chip further includes a management module connected to each reconfigurable module, and the management module can issue a transmission protocol and corresponding processing instructions to the control unit of each reconfigurable module. The structure of the management module will be described later.

[0093] In an optional manner, for each reconfigurable module, the data processing unit is implemented using domain-specific circuits, which not only avoids the high cost of fully flexible bit-level circuit programming, but also covers all transmission protocols in the application field of the transmission network chip. Specifically, in each reconfigurable module, the data processing unit is implemented by one or more data processing operators. When the data processing unit is implemented by multiple data processing operators, the multiple data processing operators may be the same data processing operators or may be completely different. The data processing operators in different reconfigurable modules are the same or different. For example, referring to Figure 4, the data processing unit supports but is not limited to insertion operators, shift operators, aggregation operators, scatter operators, interleaving operators, concatenation operators, and zero-taking operators. Among them, the insertion operator is used to insert overhead, etc. in the bit stream, the shift operator is used to move the position of bits in the bit stream, the gathering operator is used to aggregate the positions of bits in the bit stream, the scattering operator is used to disperse the aggregated bit streams in the bit stream, the interleaving operator is used to interleave the bit stream, the splicing operator is used to multiplex the bit stream, and the zero-taking operator is used to demultiplex the bit stream. All processing of each service flow may use one or more of the above-mentioned data processing operators. For example, the demultiplexing process will use the shift operator, interleaving operator, scattering operator and splicing operator.

[0094] It should be noted that in the data processing unit, the data processing operator uses customized domain-specific circuits, avoiding the high-cost fully flexible bit-level circuit programming or low-performance full-instruction data processing, and can cover all business function processing in the application field of the transmission network chip.

[0095] In an optional manner, Figure 5 provides a connection diagram of multiple reconfigurable modules. Referring to Figure 5, the multiple reconfigurable modules include at least one first reconfigurable module, a second reconfigurable module, at least one group of third reconfigurable modules, a fourth reconfigurable module and at least one fifth reconfigurable module. The sub-processing performed by the first reconfigurable module and the second reconfigurable module belongs to the input interface side processing. For example, the processing performed by the first reconfigurable module includes but is not limited to interface framing and deinterleaving, and the processing performed by the second reconfigurable module includes physical coding sublayer (PCS) processing, and PCS processing includes but is not limited to interface decoding and forward error correction (FEC) decoding. Each group of third reconfigurable modules includes one third reconfigurable module or multiple third reconfigurable modules connected in series, and the third reconfigurable module focuses on general processing of bit streams, that is, performing data path processing. For example, the processing performed by the third reconfigurable module includes but is not limited to multiplexing, demultiplexing, encapsulation mapping, channel switching and overhead extraction and insertion. The sub-processing performed by the fourth reconfigurable module and the fifth reconfigurable module belongs to the interface side inverse processing. For example, the processing performed by the fourth reconfigurable module includes but is not limited to interface coding and FEC coding, and the processing performed by the fifth reconfigurable module includes but is not limited to interleaving.

[0096] The transport network chip also includes at least one input interface and at least one output interface. The number of input interfaces and output interfaces may be the same or different. Both the input interface and the output interface may include, but are not limited to, an optical transform unit (OTU) interface, an OTU exceeding 100G (OTUCn) interface, a flexible optical transport network (FlexO) interface, a synchronous transport module level n (STM-n) interface, a 100 Gigabit Ethernet (GE) interface, a 200GE interface, a 400GE interface, and an intra-device switching interface. Assuming that the transport network chip includes multiple input ports and multiple output ports, the transport network chip dispatches the bit stream received by each input interface to the corresponding output interface. During this process, the bit stream input by the same input interface may be output from different output interfaces. For example, among the bit streams received from the OUT interface, some bit streams are output from the 200GE interface and the 400GE interface, and some other bit streams are output from the 100GE interface.

[0097] Each first reconfigurable module is connected to an input interface of the transmission network chip, and different first reconfigurable modules are connected to different input interfaces. Each first reconfigurable module is connected to a second reconfigurable module, and the second reconfigurable module is connected to at least one group of third reconfigurable modules. Each group of third reconfigurable modules is connected to another group of third reconfigurable modules, or to a fourth reconfigurable module. The fourth reconfigurable module is connected to each fifth reconfigurable module. Each fifth reconfigurable module is connected to an output interface of the transmission network chip, and different fifth reconfigurable modules are connected to different output interfaces.

[0098] The process of bit stream transmission in the transmission network chip is as follows: a certain input interface of the transmission network chip receives the bit stream, the bit stream is transmitted to the connected first reconfigurable module, the first reconfigurable module processes the bit stream and outputs it to the second reconfigurable module, the second reconfigurable module processes the received bit stream and outputs it to at least one group of third reconfigurable modules, the at least one group of third reconfigurable modules processes the received bit stream and outputs it to another group or multiple groups of third reconfigurable modules until it is output to the fourth reconfigurable module, or directly output to the fourth reconfigurable module, the fourth reconfigurable module processes the received bit stream and outputs it to the fifth reconfigurable module, the fifth reconfigurable module processes the received bit stream and outputs it to the output port for output.

[0099] It should be noted that when the bit stream is processed in each group of third reconfigurable modules, it passes through each third reconfigurable module in the group of third reconfigurable modules in turn. However, each third reconfigurable module may process the received bit stream, or some third reconfigurable modules may transparently transmit the received bit stream without processing the received bit stream.

[0100] In an optional embodiment, the transmission network chip includes multiple input interfaces and multiple output interfaces, and the bit streams of the multiple interfaces are time-division multiplexed with the second reconfigurable module and the fourth reconfigurable module. At least one first reconfigurable module includes multiple first reconfigurable modules, and at least one fifth reconfigurable module includes multiple fifth reconfigurable modules. The transmission network chip also includes a first serial-to-parallel converter and a second serial-to-parallel converter. The first serial-to-parallel converter is connected to each first reconfigurable module and to the second reconfigurable module. The second serial-to-parallel converter is connected to each fifth reconfigurable module and to the fourth reconfigurable module, see Figure 5.

[0101] The bitstream transmission process in the transmission network chip is as follows: each input interface receives a bitstream, and multiple input interfaces receive multiple bitstreams. Each input interface inputs a bitstream to the connected first reconfigurable module. Each first reconfigurable module processes the received bitstream and inputs the processed bitstream to the first serial-to-parallel converter. The first serial-to-parallel converter receives multiple bitstreams, each of which comes from a first reconfigurable module. The first serial-to-parallel converter is configured with a merging order. According to the merging order, the multiple bitstreams are merged into a single bitstream and input to the second reconfigurable module. The second reconfigurable module receives the single bitstream, processes it, and outputs it to at least one group of third reconfigurable modules. The at least one group of third reconfigurable modules processes the received bitstream and outputs it to another group or multiple groups of third reconfigurable modules, until it outputs it to the fourth reconfigurable module, or directly to the fourth reconfigurable module. The fourth reconfigurable module processes the received bitstream and outputs it to the second serial-to-parallel converter. The second serial-to-parallel converter is configured with a distribution order. According to the distribution order, a single bitstream is input to each of the multiple fifth reconfigurable modules. Each fifth reconfigurable module processes the received bit stream and outputs it to the connected output port for output.

[0102] It should be noted that the bit stream output by each first reconfigurable module is equivalent to a small-bit-width bit stream, and multiple first reconfigurable modules can output multiple small-bit-width bit streams. The first serial-to-parallel converter is equivalent to a hardened bus conversion module, converting multiple small-bit-width parallel bit streams into a large-bit-width time-division bit stream. For example, the merging order is the cyclic order of multiple input interfaces. After merging, the bits in a bit stream cyclically circulate from the first to the last input interface, and the number of bits for each input interface during each cycle is a first value. For another example, the merging order is the cyclic order of all service flows. After merging, the bits in a bit stream cyclically circulate from the first to the last service flow of all input ports, and the number of bits for each service flow during each cycle is a first value. For another example, the merging order is the cyclic order of all transmission protocols. After merging, the bits in a bit stream cyclically circulate from the first to the last transmission protocol, and the number of bits for each transmission protocol during each cycle is a first value, which can be 256. The second serial-to-parallel converter acts as a hardened bus conversion module, converting the large-bit-width time-division bit stream into multiple smaller-bit-width parallel bit streams. The distribution order is the reverse of the merging order.

[0103] Optionally, the transmission protocols of the bit streams received by the multiple input interfaces may be the same or different, and the transmission protocols of the bit streams output by the multiple output interfaces may be the same or different.

[0104] In an optional embodiment, the second reconfigurable module is connected to the third reconfigurable module via a bus, the first and last third reconfigurable modules in each group of third reconfigurable modules are connected to the bus, and the third reconfigurable module is connected to the fourth reconfigurable module via a bus. In this case, the transmission network chip further includes a first bus adapter, a second bus adapter, at least one group of bus adapters, and a bus, as shown in FIG5 . The first bus adapter and the second bus adapter are both connected to the bus, the first bus adapter is connected to the second reconfigurable module, and the second bus adapter is connected to the fourth reconfigurable module. Each group of bus adapters corresponds to a group of third reconfigurable modules, and different groups of bus adapters correspond to different groups of third reconfigurable modules. Each group of bus adapters includes a third bus adapter and a fourth bus adapter. In each group of third reconfigurable modules, the third bus adapter is connected to the first third reconfigurable module and to the bus, and the fourth bus adapter is connected to the last third reconfigurable module and to the bus.

[0105] As described above, the first serial-to-parallel converter outputs a bit stream, the second reconfigurable module receives the bit stream, processes the bit stream, and inputs the processed bit stream to the first bus adapter. The first bus adapter sends each business stream in the bit stream to the bus. For each group of third reconfigurable modules, the third bus adapter obtains the bit stream processed by the group of third reconfigurable modules from the bus and inputs the bit stream to the first third reconfigurable module. In the group of third reconfigurable modules, after the last third reconfigurable module processes the bit stream, it inputs the processed bit stream to the fourth bus adapter. If the data path processing of the bit stream has been completed, the fourth bus adapter inputs the bit stream to the bus. The second bus adapter obtains the bit streams processed by multiple groups of third reconfigurable modules from the bus, merges the bit streams from the multiple groups of third reconfigurable modules into one bit stream, and outputs it to the fourth reconfigurable module.

[0106] Optionally, the first bus adapter distributes the service flow as follows: assuming that the bit stream input by the second reconfigurable module to the first bus adapter is called the first bit stream, the first bus adapter obtains the correspondence between the configured service flow number and the group number, determines the group number corresponding to each service flow number in the first bit stream, which is called the target group number, adds the target group number to the service flow, and outputs it to the bus. Each group of third reconfigurable modules corresponds to a unique group number, and each group of third reconfigurable modules obtains a bit stream from the bus and determines whether it is its own group number based on the target group number carried in the bit stream. If so, it processes the bit stream; otherwise, it does not process the bit stream. Alternatively, the first bus adapter obtains the correspondence between the configured service flow number and the identifier of the third bus adapter, determines the identifier of the third bus adapter corresponding to each service flow number in the first bit stream, adds the identifier of the third bus adapter to the service flow, and outputs it to the bus. The identifier of the third bus adapter corresponding to each group of third reconfigurable modules is unique. Each group of third reconfigurable modules obtains a bit stream from the bus and determines whether it is the identifier of its own third bus adapter based on the identifier of the third bus adapter carried in the bit stream. If so, it is processed; otherwise, it is not processed.

[0107] Optionally, the first bus adapter obtains the service flow number in the following manner:

[0108] The data processing unit in each reconfigurable module outputs a processed bitstream, and the control unit also outputs control information, which includes information such as the numbers and transmission protocols of each service flow in the bitstream. In this way, the second reconfigurable module inputs the control information to the first bus adapter, and the second reconfigurable module can obtain the numbers of each service flow in the first bitstream from the control information.

[0109] Alternatively, the first bus adapter is configured with numbers of the service flows in the first bit stream.

[0110] Optionally, for each group of third reconfigurable modules, the third bus adapter and the fourth bus adapter process the service flow as follows: the third bus adapter obtains a bit stream from the bus and determines whether the target number present in the bit stream corresponds to the group number to which it belongs. If so, the bit stream is input to the first third reconfigurable module; otherwise, the bit stream is not processed. In the group of third reconfigurable modules, after the last third reconfigurable module completes processing the bit stream, the processed bit stream is input to the fourth bus adapter. The fourth bus adapter receives the bit stream and is configured with a correspondence between service flow numbers and destinations. If data path processing for a service flow has been completed, the destination of the service flow is the identifier of the second bus adapter or a designated identifier. If data path processing for a service flow is not completed, the destination of the service flow is the group number of the next group of third reconfigurable modules, or the identifier of the third bus adapter corresponding to the next group of third reconfigurable modules. The fourth bus adapter adds the destination corresponding to each service flow to the bus input.

[0111] Optionally, the second bus adapter processes the service flow as follows: after the bit stream is processed in the third reconfigurable module, the processed bit stream is input into the bus, and the bit stream carries the number of the second bus adapter, or other specified identifier. The second bus adapter recognizes its own number or specified identifier, merges the bit streams from multiple groups of third reconfigurable modules into one bit stream, and outputs it to the fourth reconfigurable module.

[0112] Optionally, the manner in which the multiple reconfigurable modules identify the service flow is as follows:

[0113] For the first reconfigurable module, the first reconfigurable module is configured with a method for identifying business flows, and the control unit of the first reconfigurable module can identify various business flows based on this method. For example, the first reconfigurable module is configured with the bit positions of various business flows, and the control unit can identify various business flows based on the bit positions. For another example, the first reconfigurable module is configured with designated identifiers of various business flows, and the bit stream carries the designated identifier. The control unit identifies various business flows by identifying the designated identifier. When the target attribute includes the user to which it belongs, the designated identifier can be the address of the user to which it belongs. When the target attribute includes the port to which it belongs, the designated identifier can be the port number of the port. When the target attribute includes the VLAN identifier of Ethernet, the designated identifier can be the VLAN identifier.

[0114] For the reconfigurable modules other than the first reconfigurable module among the multiple reconfigurable modules, if the reconfigurable module does not add a new business flow when processing the business flow, its control unit can obtain the business flow number from the previous reconfigurable module to identify the business flow. If the reconfigurable module adds a new business flow when processing the business flow (that is, the business flow may be divided into multiple business flows when passing through the next reconfigurable module, that is, different reconfigurable modules may have different standards for dividing the business flows), a business flow identification method is configured, which is the same as the method for the first reconfigurable module to identify the business flow, and will not be repeated here.

[0115] Optionally, the transmission network chip also includes a management module, which is connected to each reconfigurable module. The management module can send service flow division indication information to each reconfigurable module. For each reconfigurable module, the service flow division indication information received by the reconfigurable module includes an identification method for the service flow in the bit stream received by the reconfigurable module.

[0116] In an optional manner, the manner in which the multiple reconfigurable modules obtain the transmission protocol of the service flow is as follows:

[0117] For the first reconfigurable module, the first reconfigurable module is configured with a correspondence between the input interface and the transmission protocol of the outermost encapsulation of the bit stream, and is also configured with the transmission protocol of the new business flow split out of the bit stream. The input interface is the input interface of the transmission network chip. After the first reconfigurable module receives the bit stream from the connected input interface, it obtains the transmission protocol of the outermost encapsulation of the bit stream from the correspondence, processes the bit stream based on the transmission protocol, and if a new business flow is split out during the processing, obtains the transmission protocol of the new business flow. The first reconfigurable module inputs the transmission protocols and numbers of various business flows in the bit stream to the next reconfigurable module. For example, the bit stream received from the same input interface may contain bit streams of different users, or bit streams of different ports, etc.

[0118] For the reconfigurable modules other than the first reconfigurable module among the multiple reconfigurable modules, if the reconfigurable module does not add a new business flow when processing the business flow, the transmission protocol of the business flow can be obtained from the previous reconfigurable module. If the reconfigurable module adds a new business flow when processing the business flow, a business flow identification method and a transmission protocol are configured. This method is the same as the method for the first reconfigurable module to obtain the transmission protocol, and will not be repeated here.

[0119] Optionally, the transmission network chip further includes a management module, which is connected to each reconfigurable module. The management module can issue a transmission protocol of a service flow to each reconfigurable module.

[0120] In an optional manner, referring to FIG6 , the transmission network chip further includes a management module, which is configured to determine the status of the bitstream based on the overhead in the bitstream, for example, to determine whether the bitstream is a malicious bitstream.

[0121] The management module obtains the overhead in the following way:

[0122] In certain third reconfigurable modules that perform data path processing, a control unit extracts overhead from the bit stream received from the data processing unit, referred to as first overhead, and sends the first overhead to the management module. Figure 7 shows the ODU frame structure, which includes an overhead area and a payload area. The management module receives the first overhead and determines the status of the bit stream based on it.

[0123] Optionally, the control unit can extract the overhead in the bit stream received from the data processing unit based on the overhead extraction notification issued by the management module, or can extract the overhead in the bit stream received from the data processing unit based on the original configuration information.

[0124] Optionally, when the bit stream forms a new frame structure, the management module is further configured to generate an overhead of the frame structure. The processing process is as follows:

[0125] In certain third reconfigurable modules performing data path processing, the control unit determines that a new frame structure needs to be generated and sends an overhead acquisition request to the management module. The management module receives the overhead acquisition request, generates a second overhead, and inputs the second overhead to the control unit. The control unit receives the second overhead and sends the second overhead and its insertion position to the data processing unit. The data processing unit inserts the second overhead into the bitstream at the insertion position. The insertion position may be the mth bit, meaning the second overhead is inserted at the mth bit position.

[0126] Optionally, the management module is connected to the bus, each reconfigurable module is connected to the bus, and the management module communicates with each reconfigurable module via the bus. In this way, the management module communicates with the control unit via the bus.

[0127] In this way, the architecture of the existence management module is adopted, and data processing and overhead processing are handled separately.

[0128] Optionally, FIG8 provides a schematic structural diagram of the management module. Referring to FIG8 , the management module includes a memory, a switching unit (SU), a bus adapter, a bus, and at least one reduced-instruction processing unit (RPU). The switching unit is connected to the memory, the switching unit is connected to the BA, the switching unit is also connected to the RPU, the switching unit is also connected to the bus, and the bus is connected to each RPU. The memory is on-chip storage for storing bitstreams, configuration management entries, temporary data, etc. The RPU uses a reduced instruction set computer (RSIC) core with a custom or general instruction set, responsible for overhead processing and configuration management functions for transmitting bitstreams. Different RPUs can perform different processing. For example, the first RPU determines the state of the bitstream based on the first overhead, the second RPU generates the second overhead, and the third RPU recalculates the transmission path for a bitstream after determining the transmission path. For another example, multiple RPUs can communicate via a bus. When executing a function, multiple RPUs execute different sub-functions within the function, thereby executing the function.

[0129] In an optional manner, the management module can be one or more management modules. When there are multiple management modules, each management module is responsible for managing the third reconfigurable module of the partial group. The first reconfigurable module and the second reconfigurable module can be managed by a management module specified among the multiple management modules. The fourth reconfigurable module and the fifth reconfigurable module can be managed by a management module specified among the multiple management modules.

[0130] In one optional embodiment, a logical unit consisting of a plurality of first reconfigurable modules, a first serial-to-parallel converter, a second reconfigurable module, and a first bus adapter is referred to as an input processing component, as shown in Figure 9 . A logical unit consisting of a set of third reconfigurable modules and corresponding third and fourth bus adapters is referred to as a data path processing component, as shown in Figure 10 . A logical unit consisting of a second bus adapter, a fourth reconfigurable module, a second serial-to-parallel converter, and a plurality of fifth reconfigurable modules is referred to as an output processing component, as shown in Figure 11 .

[0131] In an optional approach, a transmission network chip is used in scenarios where processing bandwidth is not particularly high. The transmission network chip adopts a ring bus interconnection architecture. As shown in Figure 12, the transmission network chip includes an input processing component, multiple data path processing components, an output processing component, and at least one management module, using a connection topology that minimizes interconnect lines. In this transmission network chip, each management module is responsible for managing at least one group of third reconfigurable modules. The first and second reconfigurable modules can be managed by any of the multiple management modules, and the fourth and fifth reconfigurable modules can be managed by any of the multiple management modules.

[0132] In another optional manner, the transmission network chip is used to process large bandwidth scenarios. The transmission network chip adopts a parallel multi-channel and cross-bar interconnection architecture, see the connection topology shown in Figure 13. The transmission network chip includes multiple input processing components, multiple output processing components, multiple groups of data path processing components, multiple management modules, a first cross-bar switch matrix, a second cross-bar switch matrix and a third cross-bar switch matrix. The multiple groups of data path processing components include one or more data path processing components, and Figure 13 shows that it includes 4 data path processing components. The multiple groups of data path processing components correspond one-to-one to the multiple management modules, each management module is responsible for managing a group of data path processing components, and different management modules are responsible for managing different groups of data path processing components. Multiple input processing components can be managed by a management module specified in multiple management modules, and multiple output processing components can be managed by a management module specified in multiple management modules.

[0133] Each first input port is connected to an input processing component, different first input ports are connected to different input processing components, each first output port is connected to a group of data path processing components, and different first output ports are connected to different groups of data path processing components. The first crossbar switch matrix is ​​managed by a management module designated by a plurality of modules. The management module can flexibly control the paths between the plurality of first input ports and the plurality of first output ports, so that the bit stream input from any first input port can be output to any first output port for output. Therefore, the bit stream output by each input processing component can be flexibly dispatched to any data path processing component for processing.

[0134] The second crossbar switch matrix includes multiple second input ports and multiple second output ports. Each second input port is connected to a group of data path processing components, and different second input ports are connected to different groups of data path processing components. Each second output port is connected to a group of data path processing components, and different second output ports are connected to different groups of data path processing components. The second crossbar switch matrix is ​​managed by a management module designated by a plurality of modules. The management module can flexibly control the paths between the plurality of first input ports and the plurality of first output ports, so that a bit stream input from any second input port can be output to any second output port for output. Therefore, the bit stream output by each group of data path processing components can be flexibly dispatched to any data path processing component for processing.

[0135] The third crossbar switch matrix includes multiple third input ports and multiple third output ports. Each third input port is connected to a group of data path processing components, and different third input ports are connected to different groups of data path processing components. Each third output port is connected to an output processing component, and different third output ports are connected to different output processing components. The third crossbar switch matrix is ​​managed by a management module designated by the multiple modules. The management module can flexibly control the paths between the multiple third input ports and the multiple third output ports, so that a bit stream input from any third input port can be output to any third output port for output. Therefore, the bit stream output by each group of data path processing components can be flexibly dispatched to any output processing component for processing and output.

[0136] In addition, the management module can also control the output rate of the bit stream in the three crossbar switch matrices to reduce congestion of components connected to the output ports of the three crossbar switch matrices.

[0137] It should be noted that the number of data path processing components in each group of data path processing components can be set according to actual needs.

[0138] In an optional manner, the bit stream in the embodiment of the present disclosure can be considered as an L0 bit stream and an L1 bit stream.

[0139] In the present disclosure, the terms "first" and "second" and the like are used to distinguish between identical or similar items having substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first" and "second", nor is there a limitation on quantity and order of execution. It should also be understood that although the following description uses the terms first and second, etc. to describe various elements, these elements should not be limited by the terms. These terms are simply used to distinguish one element from another. For example, without departing from the scope of the various examples, the first reconfigurable module may be referred to as the second reconfigurable module, and similarly, the second reconfigurable module may be referred to as the first reconfigurable module. Both the first reconfigurable module and the second reconfigurable module may be reconfigurable modules, and in some cases, may be separate and different reconfigurable modules.

[0140] The term "at least one" in the present disclosure means one or more, and the term "plurality" in the present disclosure means two or more.

[0141] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present disclosure, and such modifications or substitutions should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A transmission network chip, characterized in that: The system comprises a plurality of reconfigurable modules, wherein the plurality of reconfigurable modules have a specified connection relationship, each reconfigurable module is used to perform a sub-processing in a protocol processing, wherein the protocol processing is the protocol processing performed by the transmission network chip on an input bit stream, and each reconfigurable module includes a control unit and a data processing unit; The control unit is configured to generate control parameters corresponding to various service flows in a bit stream currently received by the reconfigurable module based on the transmission protocols and contexts of the various service flows, and send the control parameters to the data processing unit in the reconfigurable module. For each service flow, the control parameter corresponding to the service flow is used to instruct execution of a specified sub-processing on the service flow. The data processing unit in the reconfigurable module is used to receive the bit stream, perform specified sub-processing on the various business flows based on the control parameters corresponding to the various business flows, obtain a processed bit stream, and output the processed bit stream.

2. The transmission network chip according to claim 1, characterized in that: The plurality of reconfigurable modules include at least one first reconfigurable module, a second reconfigurable module, at least one group of third reconfigurable modules, a fourth reconfigurable module and at least one fifth reconfigurable module; The first reconfigurable module is connected to an input interface of the transmission network chip, different first reconfigurable modules are connected to different input interfaces, the first reconfigurable module is connected to the second reconfigurable module, the second reconfigurable module is connected to at least one group of third reconfigurable modules, the third reconfigurable modules in each group of third reconfigurable modules are connected in series, each group of third reconfigurable modules is connected to another group of third reconfigurable modules, or is connected to the fourth reconfigurable module, the fourth reconfigurable module is connected to the fifth reconfigurable module, the fifth reconfigurable module is connected to an output interface of the transmission network chip, and different fifth reconfigurable modules are connected to different output interfaces; The sub-processing executed by the first reconfigurable module and the second reconfigurable module belongs to input interface side processing; The sub-processing executed by each group of third reconfigurable modules belongs to data path processing; The sub-processing executed by the fourth reconfigurable module and the fifth reconfigurable module belongs to output interface side processing.

3. The transmission network chip according to claim 2, characterized in that: The at least one first reconfigurable module includes a plurality of first reconfigurable modules, the at least one fifth reconfigurable module includes a plurality of fifth reconfigurable modules, and the transmission network chip further includes a first serial-to-parallel converter and a second serial-to-parallel converter; The first serial-to-parallel converter is connected to each first reconfigurable module and is connected to the second reconfigurable module; The second serial-to-parallel converter is connected to each fifth reconfigurable module and to the fourth reconfigurable module; The first serial-to-parallel converter is configured to receive a plurality of bit streams from the plurality of first reconfigurable modules, merge the plurality of bit streams into one bit stream, and output the bit stream to the second reconfigurable module; The second serial-to-parallel converter is used to receive a bit stream from the fourth reconfigurable module and distribute it to the multiple fifth reconfigurable modules.

4. The transmission network chip according to claim 2 or 3, characterized in that: The transmission network chip further includes a first bus adapter, a second bus adapter and a bus; The first bus adapter and the second bus adapter are both connected to the bus, the first bus adapter is connected to the second reconfigurable module, the second bus adapter is connected to the fourth reconfigurable module, and each group of third reconfigurable modules is connected to the bus; The first bus adapter is used to distribute each service flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules via the bus; The second bus adapter is configured to receive bit streams from the at least one group of third reconfigurable modules via a bus, merge the received bit streams into one bit stream, and output the bit stream to the fourth reconfigurable module.

5. The transmission network chip according to claim 4, characterized in that: The first bus adapter is configured to determine, in a correspondence between service flow numbers and group numbers, a target group number corresponding to the number of each service flow in the first bit stream; Each service flow in the first bit stream is distributed to a third reconfigurable module corresponding to the target group number via the bus.

6. The transmission network chip according to claim 4 or 5, characterized in that: The transmission network chip further includes at least one group of bus adapters, the at least one group of bus adapters corresponding to the at least one group of third reconfigurable modules on a one-to-one basis, and each group of bus adapters includes a third bus adapter and a fourth bus adapter; In each group of third reconfigurable modules, the third bus adapter is connected to the first third reconfigurable module and the bus respectively, and the fourth bus adapter is connected to the last third reconfigurable module and the bus respectively; The third bus adapter is configured to obtain a bit stream addressed to the first third reconfigurable module from the bus, and send the bit stream to the first third reconfigurable module; The fourth bus adapter is used to receive a bit stream from the last third reconfigurable module and send the bit stream to the bus.

7. The transmission network chip according to any one of claims 1 to 6, characterized in that: The control unit is used to determine, for each service flow in the currently received bit stream, a processing instruction corresponding to the transmission protocol of the service flow, and determine a control parameter corresponding to the service flow based on the processing instruction and the context of the service flow.

8. The transmission network chip according to any one of claims 1 to 7, characterized in that: The control unit is further configured to update the contexts of the various service flows.

9. The transmission network chip according to any one of claims 1 to 8, characterized in that: Different service flows have different target attributes, and the target attributes include one or more of a user, a port, or an Ethernet virtual local area network identifier.

10. The transmission network chip according to any one of claims 1 to 9, characterized in that: The control unit is further configured to receive control information output by the control unit of the previous reconfigurable module, wherein the control information includes the transmission protocols and numbers of the various service flows; Based on the numbers of the various service flows, contexts of the various service flows are determined.

11. The transmission network chip according to any one of claims 1 to 10, characterized in that: The transmission network chip further includes a management module and a bus, wherein the management module is connected to each reconfigurable module via the bus; The management module is used to send service flow division indication information to each reconfigurable module through the bus; The control unit is further configured to determine various service flows in the currently received bit stream based on the service flow division indication information.

12. The transmission network chip according to claim 11, characterized in that: For a reconfigurable module for performing data path processing among the multiple reconfigurable modules, the control unit is further configured to send a first overhead in the currently received bit stream to the management module through the bus; The management module is further configured to determine a status of the currently received bit stream based on the first overhead.

13. The transmission network chip according to claim 11 or 12, characterized in that: For a reconfigurable module for performing data path processing among the multiple reconfigurable modules, the control unit is further configured to, when determining to perform encapsulation processing on a currently received bit stream, send an overhead acquisition request to the management module through the bus; The management module is further configured to receive the overhead acquisition request, generate a second overhead, and send the second overhead to the control unit via the bus; The control unit is further configured to send the second overhead and the insertion position to the data processing unit of the corresponding reconfigurable module; The data processing unit of the reconfigurable module is further configured to insert the second overhead into the currently received bit stream at the insertion position.

14. A network device, characterized in that: The network device includes the transmission network chip according to any one of claims 1 to 13.

15. A method for processing a bit stream, characterized in that: Applied to a transmission network chip, the transmission network chip includes a plurality of reconfigurable modules, the plurality of reconfigurable modules have a specified connection relationship, each reconfigurable module is used to perform a sub-processing in a protocol processing, the protocol processing is the protocol processing performed by the transmission network chip on an input bit stream, and each reconfigurable module includes a control unit and a data processing unit; The control unit generates control parameters corresponding to various service flows in a bit stream currently received by the reconfigurable module based on the transmission protocols and contexts of the various service flows, and sends the control parameters to the data processing unit in the reconfigurable module. For each service flow, the control parameter corresponding to the service flow is used to instruct to perform a specified sub-processing on the service flow. The data processing unit in the reconfigurable module receives the bit stream, performs specified sub-processing on the various service flows based on the control parameters corresponding to the various service flows, obtains a processed bit stream, and outputs the processed bit stream.

16. The method according to claim 15, characterized in that The plurality of reconfigurable modules include at least one first reconfigurable module, a second reconfigurable module, at least one group of third reconfigurable modules, a fourth reconfigurable module and at least one fifth reconfigurable module; The first reconfigurable module is connected to an input interface of the transmission network chip, different first reconfigurable modules are connected to different input interfaces, the first reconfigurable module is connected to the second reconfigurable module, the second reconfigurable module is connected to at least one group of third reconfigurable modules, the third reconfigurable modules in each group of third reconfigurable modules are connected in series, each group of third reconfigurable modules is connected to another group of third reconfigurable modules, or is connected to the fourth reconfigurable module, the fourth reconfigurable module is connected to the fifth reconfigurable module, the fifth reconfigurable module is connected to an output interface of the transmission network chip, and different fifth reconfigurable modules are connected to different output interfaces; The sub-processing executed by the first reconfigurable module and the second reconfigurable module belongs to input interface side processing; The sub-processing executed by each group of third reconfigurable modules belongs to data path processing; The sub-processing executed by the fourth reconfigurable module and the fifth reconfigurable module belongs to output interface side processing.

17. The method according to claim 16, characterized in that The at least one first reconfigurable module includes a plurality of first reconfigurable modules, the at least one fifth reconfigurable module includes a plurality of fifth reconfigurable modules, and the transmission network chip further includes a first serial-to-parallel converter and a second serial-to-parallel converter; The first serial-to-parallel converter is connected to each first reconfigurable module and is connected to the second reconfigurable module; The second serial-to-parallel converter is connected to each fifth reconfigurable module and to the fourth reconfigurable module; The method further comprises: The first serial-to-parallel converter receives a plurality of bit streams from the plurality of first reconfigurable modules, combines the plurality of bit streams into one bit stream, and outputs the bit stream to the second reconfigurable module; The second serial-to-parallel converter receives a bit stream from the fourth reconfigurable module and distributes the bit stream to the plurality of fifth reconfigurable modules.

18. The method according to claim 16 or 17, characterized in that The transmission network chip further includes a first bus adapter, a second bus adapter and a bus; The first bus adapter and the second bus adapter are both connected to the bus, the first bus adapter is connected to the second reconfigurable module, the second bus adapter is connected to the fourth reconfigurable module, and each group of third reconfigurable modules is connected to the bus; The method further comprises: The first bus adapter distributes each service flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules via the bus; The second bus adapter receives bit streams from the at least one group of third reconfigurable modules through a bus, merges the received bit streams into one bit stream, and outputs the bit stream to the fourth reconfigurable module.

19. The method according to claim 18, characterized in that The first bus adapter distributes each service flow in the first bit stream from the second reconfigurable module to at least one group of third reconfigurable modules via the bus, including: The first bus adapter determines, in the correspondence between the service flow numbers and the group numbers, a target group number corresponding to the number of each service flow in the first bit stream; Each service flow in the first bit stream is distributed to a third reconfigurable module corresponding to the target group number via the bus.

20. The method according to any one of claims 15 to 19, characterized in that The control unit generates control parameters corresponding to various service flows based on the transmission protocols and contexts of the various service flows in the bit stream currently received by the reconfigurable module, including: The control unit determines, for each service flow in the currently received bit stream, a processing instruction corresponding to the transmission protocol of the service flow, and determines a control parameter corresponding to the service flow based on the processing instruction and the context of the service flow.

21. The method according to any one of claims 15 to 20, characterized in that The method further comprises: The control unit receives control information output by the control unit of the previous reconfigurable module, wherein the control information includes the transmission protocols and numbers of the various service flows; Based on the numbers of the various service flows, contexts of the various service flows are determined.

22. The method according to any one of claims 15 to 21, characterized in that The transmission network chip further includes a management module and a bus, wherein the management module is connected to each reconfigurable module via the bus; The method further comprises: The management module sends service flow division indication information to each reconfigurable module via the bus; The control unit determines various service flows in the currently received bit stream based on the service flow division indication information.

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