Communication method and communication apparatus based on LDPC code

Abstract

A communication method and a communication apparatus based on an LDPC code. In the method and apparatus, encoding or decoding can be performed on the basis of an LDPC check matrix. The LDPC check matrix is determined on the basis of an LDPC base matrix, a lifting value Zc, a shift value corresponding to each first element in the base matrix, and the number k of shift values corresponding to each first element, k being an integer greater than or equal to 1, k that corresponds to at least one first element in the base matrix being an integer greater than 1, and Zc being an integer greater than 1. Zc and the k shift values for each first element are used for indicating that a corresponding first element is replaced with k cyclic shift matrices of Zc*Zc. The cyclic shift matrices are obtained by performing cyclic shift on an identity matrix of Zc*Zc, and the k shift values are the number of cyclic shifts corresponding to the k cyclic shift matrices, respectively. According to the method, the decoding performance of an LDPC code can be improved.

Description

Communication method and communication device based on LDPC code

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 1, 2024, with application number 202410251136.3 and application name “Communication method and communication device based on LDPC code”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to a communication method and a communication device based on LDPC codes. Background Art

[0003] In the field of channel coding, low-density parity check (LDPC) codes are one of the most mature and widely used channel coding schemes. Quasi-cyclic low-density parity check (QC-LDPC) codes are a type of structured LDPC code. Due to the unique structure of their parity check matrix, they can be encoded using a simple feedback shift register, reducing the coding complexity of LDPC codes.

[0004] Currently, the decoding threshold and decoding complexity of QC-LDPC codes are primarily determined by the basis matrix (or basis graph). Small-scale basis matrices have significant limitations on the degree distribution of LDPC codes, preventing optimal decoding thresholds. LDPC performance suffers severely at extremely high code rates. The degree distribution of LDPC codes indicates the column redistribution of the parity check matrix. One possible implementation approach is to increase the decoding threshold by expanding the basis matrix. However, without good orthogonality, large-scale basis matrices have low parallelism and complex hardware implementation. Summary of the Invention

[0005] The embodiments of the present application provide a communication method and a communication device based on LDPC codes, which help to improve the decoding performance of LDPC codes.

[0006] On the first aspect, a communication method based on LDPC code is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the transmitting device.

[0007] The method comprises: obtaining an information bit sequence; determining an LDPC check matrix, wherein the LDPC check matrix is ​​based on an LDPC base matrix, a lifting value Z c , the translation value corresponding to each 1 element in the basis matrix, and the number k of translation values ​​corresponding to each 1 element, k is an integer greater than or equal to 1 and k corresponding to at least one 1 element in the basis matrix is ​​an integer greater than 1, where Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k Z c *Z c The cyclic shift matrix of Z c *Z c The k shift values ​​are the number of cyclic shifts corresponding to the k cyclic shift matrices; the information bit sequence is encoded according to the LDPC check matrix to obtain a codeword sequence; and the codeword sequence is output.

[0008] In this technical solution, multiple shift values ​​are assigned to a single element in the base matrix, and based on these shift values, the corresponding single element is expanded into multiple cyclic shift matrices. Compared to the expansion scheme where each element in the base matrix corresponds to a single shift value, this expanded parity check matrix supports larger column weights and has a better decoding threshold. Furthermore, while optimizing the decoding threshold, it does not require expanding the base matrix, thereby reducing hardware implementation complexity.

[0009] On the second aspect, a communication method based on LDPC code is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0010] The method comprises: obtaining a codeword sequence; determining an LDPC check matrix, wherein the LDPC check matrix is ​​based on an LDPC base matrix, a lifting value Z c , the translation value corresponding to each 1 element in the basis matrix, and the number k of translation values ​​corresponding to each 1 element, k is an integer greater than or equal to 1 and k corresponding to at least one 1 element in the basis matrix is ​​an integer greater than 1, where Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k Z c *Z c The cyclic shift matrix of Z c *Z cThe k shift values ​​are the number of cyclic shifts corresponding to the k cyclic shift matrices. The codeword sequence is decoded according to the LDPC check matrix to obtain the information bit sequence.

[0011] For the beneficial effects of the second aspect, please refer to the description of the first aspect and will not be repeated here.

[0012] In certain implementations of the first and second aspects, the method further includes: determining a first index α(i) associated with the i-th row of the basis matrix, and a second index b(j) associated with the j-th column of the basis matrix, wherein the number k of translation values ​​corresponding to the 1 element located in the i-th row and the j-th column of the basis matrix is ​​equal to α(i)*b(j), α(i) is an integer greater than or equal to 1, and b(j) is an integer greater than or equal to 1.

[0013] In certain implementations of the first and second aspects, the first index associated with any row in the basis matrix is ​​1, or the first index associated with any column in the basis matrix is ​​1.

[0014] In certain implementations of the first and second aspects, determining the LDPC check matrix includes replacing the first element in the base matrix with α(i1)*b(j1) Z c *Z c Circular shift matrix, α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the second element in the basis matrix with α(i2)*b(j2) Z c *Z c The LDPC check matrix is ​​obtained by using the all-0 matrix, where the first element is the 1 element located at row i1 and column j1, the second element is the 0 element located at row i2 and column j2, and α(i1)*b(j1) Z c *Z c The cyclic shift matrix forms a (α(i1)*Z c )*(b(j1)*Z c ) matrix, α(i2)*b(j2) Z c *Z c The full 0 matrix forms a (α(i2)*Z c )*(b(j2)*Z c ) is an all-zero matrix.

[0015] In certain implementations of the first and second aspects, determining an LDPC check matrix includes: replacing a first element with an all-1 matrix of α(i1)*b(j1), and replacing a second element with an all-0 matrix of α(i2)*b(j2), wherein the first element is a 1 element located in the i1 row and j1 column, and the second element is a 0 element located in the i2 row and j2 column; replacing each 1 in the all-1 matrix of α(i1)*b(j1) with Z c *Z c The cyclic shift matrix of the replaced α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix of α(i2)*b(j2) and replacing the 0 in the all-0 matrix of α(i2)*b(j2) with Z c *Z c The LDPC check matrix is ​​obtained by replacing the all-0 matrix with the LDPC check matrix.

[0016] In certain implementations of the first and second aspects, the α(i1)*b(j1) translation values ​​of the first element are aligned with the α(i1)*b(j1) Z values ​​in the order of row first and column later. c *Z c The cyclic shift matrix of α(i1)*b(j1) corresponds to the cyclic shift matrix of α(i1)*b(j1) in the order of columns first and rows. c *Z c The cyclic shift matrices of are in one-to-one correspondence.

[0017] In certain implementations of the first and second aspects, determining a first indicator α(i) associated with the i-th row of a basis matrix and a second indicator b(j) associated with the j-th column of the basis matrix includes: determining a first indicator associated with each row of the basis matrix based on first indication information, the first indication information indicating the first indicators associated with all rows in the basis matrix; determining a second indicator associated with each column of the basis matrix based on second indication information, the second indication information indicating the second indicators associated with all columns in the basis matrix.

[0018] In certain implementations of the first and second aspects, determining a first indicator α(i) associated with the i-th row of the basis matrix and a second indicator b(j) associated with the j-th column of the basis matrix includes: determining a first indicator associated with each row of the basis matrix and a second indicator associated with each column of the basis matrix based on first indication information and the number k of translation values ​​corresponding to 1 element in the basis matrix, wherein the first indication information indicates the first indicator associated with all rows in the basis matrix; or determining a first indicator associated with each row of the basis matrix and a second indicator associated with each column of the basis matrix based on second indication information and the number k of translation values ​​corresponding to 1 element in the basis matrix, wherein the second indication information indicates the second indicator associated with all columns in the basis matrix.

[0019] In the above technical solution, only the first indication information can be indicated, and the device (transmitting device or receiving device) can determine the second indicator associated with the column where the element is located based on the number k of translation values ​​corresponding to 1 element in the base matrix. Similarly, only the second indication information can be indicated, and the device (transmitting device or receiving device) can determine the first indicator associated with the row where the element is located based on the number k of translation values ​​corresponding to 1 element in the base matrix.

[0020] In certain implementations of the first and second aspects, the first indication information is a first sequence, and / or the second indication information is a second sequence.

[0021] For example, the protocol may define a first sequence and / or a second sequence.

[0022] In certain implementations of the first and second aspects, the number k of translation values ​​corresponding to all 1 elements in the information column of the base matrix is ​​equal to 2 or 3 or 4 or 6.

[0023] In certain implementations of the first and second aspects, the storage matrix indicates k translation values ​​corresponding to each 1 element in the base matrix and the LDPC base matrix.

[0024] In certain implementations of the first and second aspects, the storage matrix includes a first translation value and a first function corresponding to the first element in the basis matrix, the first element is a 1 element in the basis matrix, and the number of translation values ​​k corresponding to the first element is greater than 1, and the method also includes: determining the other k-1 translation values ​​corresponding to the first element based on the first translation value and the first function.

[0025] On the third aspect, a communication method based on LDPC code is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the transmitting device.

[0026] The method comprises: obtaining an information bit sequence; determining an LDPC check matrix, wherein the LDPC check matrix is ​​based on an LDPC base matrix, a lifting value Z c , the translation value corresponding to each 1 element in the basis matrix, and the number of translation values ​​corresponding to each 1 element are determined, the number of translation values ​​corresponding to each 1 element is k, k is an integer greater than 1, the k translation values ​​corresponding to at least one 1 element in the basis matrix include at least one first-class translation value and at least one second-class translation value, the k translation values ​​corresponding to the remaining 1 elements in the basis matrix except for at least one 1 element are all first-class translation values, and the first-class translation value is greater than or equal to 0 and less than or equal to Z max An integer of -1 indicates that the second translation value is not equal to the first translation value. max Z c The corresponding maximum improvement value, where Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k1 Z c *Z c The cyclic shift matrix and k2 Z c *Z c The total 0 matrix, k1 and k2 are the number of first-class translation values ​​and the number of second-class translation values ​​in the corresponding k translation values ​​of 1 element, and the sum of k1 and k2 is equal to k, k1 Z c *Z c The cyclic shift matrix is ​​Z c *Z c The k1 first-class translation values ​​are k1 Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix of ; according to the LDPC check matrix, the information bit sequence is encoded to obtain a codeword sequence; and the codeword sequence is output.

[0027] In this technical solution, multiple shift values ​​are assigned to a single element in the base matrix, and based on these shift values, the corresponding single element is expanded into multiple cyclic shift matrices. Compared to the expansion scheme where each element in the base matrix corresponds to a single shift value, this expanded parity check matrix supports larger column weights and has a better decoding threshold. Furthermore, while optimizing the decoding threshold, it does not require expanding the base matrix, thereby reducing hardware implementation complexity.

[0028] It can be understood that in the scheme shown in the first aspect, the number of translation values ​​corresponding to 1 element in the base matrix may be different, but when the number of translation values ​​is different, the decoding threshold cannot reach the optimal level, the actual performance is impaired, and the hardware implementation complexity is high. In this scheme, the second type of translation value is used to make the number of translation values ​​of each 1 element in the base matrix the same, which can reduce the hardware implementation complexity and optimize the decoding threshold.

[0029] Fourthly, a deinterleaving method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0030] The method includes: obtaining a codeword sequence; determining an LDPC check matrix, wherein the LDPC check matrix is ​​based on an LDPC base matrix, a lifting value Z c , the translation value corresponding to each 1 element in the basis matrix, and the number of translation values ​​corresponding to each 1 element are determined, the number of translation values ​​corresponding to each 1 element is k, k is an integer greater than 1, the k translation values ​​corresponding to at least one 1 element in the basis matrix include at least one first-class translation value and at least one second-class translation value, the k translation values ​​corresponding to the remaining 1 elements in the basis matrix except for at least one 1 element are all first-class translation values, and the first-class translation value is greater than or equal to 0 and less than or equal to Z max -1, the second type of translation value is not equal to the first type of translation value, Z max Z c The corresponding maximum improvement value, where Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k1 Z c *Z c The cyclic shift matrix and k2 Z c *Z c The total 0 matrix, k1 and k2 are the number of first-class translation values ​​and the number of second-class translation values ​​in the corresponding k translation values ​​of 1 element, and the sum of k1 and k2 is equal to k, k1 Z c *Z c The cyclic shift matrix is ​​Z c *Z c The k1 first-class translation values ​​are k1 Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix of ; according to the LDPC check matrix, the codeword sequence is decoded to obtain the information bit sequence.

[0031] For the beneficial effects of the fourth aspect, please refer to the description of the third aspect and will not be repeated here.

[0032] In certain implementations of the third and fourth aspects, the second-type translation value is equal to -1.

[0033] In certain implementations of the third and fourth aspects, the method further includes: determining a first index α associated with each row of the basis matrix, and a second index b associated with each column of the basis matrix, wherein the number k of translation values ​​corresponding to any 1 element in the basis matrix is ​​equal to α*b, α is an integer greater than or equal to 1, and b is an integer greater than or equal to 1.

[0034] In certain implementations of the third and fourth aspects, the first index associated with any row in the basis matrix is ​​1, or the first index associated with any column in the basis matrix is ​​1.

[0035] In certain implementations of the third and fourth aspects, determining the LDPC check matrix includes: replacing the 1 element in the base matrix with k1 Z c *Z c The cyclic shift matrix, and k2 Z c *Z c All zero matrices, k1 Z c *Z c The cyclic shift matrices are k1 translation value pairs Z corresponding to 1 element c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the 0 elements in the basis matrix with α*b Z c *Z c The LDPC check matrix is ​​obtained by the all-0 matrix, where k1 Z c *Z c Circular shift matrix and k2 Z c *Z c The full 0 matrix forms a (α*Z c )*(b*Z c ) matrix, α*b Z c *Z c The full 0 matrix forms a (a*Z c )*(b*Z c ) is an all-zero matrix.

[0036] In certain implementations of the third and fourth aspects, determining the LDPC check matrix includes: replacing the 1 element in the base matrix with an α*b matrix, wherein the k translation values ​​corresponding to the 1 element in the base matrix correspond one-to-one to the positions of the k elements of the α*b matrix, wherein if the translation value corresponding to the first position of the α*b matrix is ​​a first type of translation value, the element corresponding to the first position is 1, and if the translation value corresponding to the first position is a second type of translation value, the element corresponding to the first position is 0, and replacing each 0 element in the base matrix with an all-0 matrix of α*b; replacing each 1 in the α*b matrix with a Z c *Z c The cyclic shift matrix is ​​based on the translation value pair Z corresponding to each 1 position in the matrix of α*b c *Z c The matrix obtained by cyclic shifting the identity matrix of α*b is replaced by Z c *Z c 's all-0 matrix, and replace each 0 in the all-0 matrix of α*b with Z c *Z c The LDPC check matrix is ​​obtained by replacing the all-0 matrix with the LDPC check matrix.

[0037] In certain implementations of the third and fourth aspects, the k1 translation values ​​of the element 1 are compared with the (α*Z c )*(b*Z c ) in the matrix Z c *Z c The matrices correspond one to one, or the k1 translation values ​​of 1 element are in the order of column first and row second and the (α*Z c )*(b*Z c ) in the matrix Z c *Z c The matrices are in one-to-one correspondence.

[0038] In certain implementations of the third and fourth aspects, determining a first indicator α associated with each row of the basis matrix and a second indicator b associated with each column of the basis matrix includes: determining the first indicator associated with each row of the basis matrix based on first indication information, the first indication information indicating the first indicator associated with all rows in the basis matrix; determining the second indicator associated with each column of the basis matrix based on second indication information, the second indication information indicating the second indicator associated with all columns in the basis matrix.

[0039] In certain implementations of the third and fourth aspects, determining a first indicator α associated with each row of the basis matrix and a second indicator b associated with each column of the basis matrix includes: determining the first indicator associated with each row of the basis matrix and the second indicator associated with each column of the basis matrix based on first indication information and the number k of translation values ​​corresponding to 1 element in the basis matrix, the first indication information indicating the first indicator associated with all rows in the basis matrix; or determining the first indicator associated with each row of the basis matrix and the second indicator associated with each column of the basis matrix based on second indication information and the number k of translation values ​​corresponding to 1 element in the basis matrix, the second indication information indicating the second indicator associated with all columns in the basis matrix.

[0040] In certain implementations of the third aspect and the fourth aspect, the first indication information is a first sequence, and / or the second indication information is a second sequence.

[0041] In certain implementations of the third and fourth aspects, k is equal to 2 or 3 or 4 or 6.

[0042] In certain implementations of the third and fourth aspects, the storage matrix indicates a base matrix and k translation values ​​corresponding to each 1 element in the base matrix.

[0043] In certain implementations of the third and fourth aspects, the storage matrix includes a first translation value and a first function corresponding to a first element in the basis matrix, the first element is a 1 element in the basis matrix, and the number k1 of first-type translation values ​​corresponding to the first element is greater than 1. The method further includes:

[0044] Based on the first translation value and the first function, other k1-1 first-category translation values ​​corresponding to the first element are determined.

[0045] In a fifth aspect, a communication device is provided, which is configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0046] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0047] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0048] In a sixth aspect, a communication device is provided, which includes: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0049] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0050] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0051] In a seventh aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0052] In one implementation, the device further includes the memory.

[0053] In an eighth aspect, a processor is provided for executing the methods provided in the above aspects.

[0054] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0055] In a ninth aspect, a computer-readable storage medium is provided, which stores a program code for execution by a device, wherein the program code includes a method for executing any one of the above aspects or its implementation.

[0056] In a tenth aspect, a computer program product comprising instructions is provided, which, when run on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0057] In an eleventh aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0058] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0059] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0060] In a twelfth aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above.

[0061] In a thirteenth aspect, a computer program is provided, which, when executed on a computer, enables the method provided by any one of the above aspects or its implementation to be executed. BRIEF DESCRIPTION OF THE DRAWINGS

[0062] FIG1 is a schematic diagram of a network architecture to which embodiments of the present application can be applied.

[0063] FIG2 is a schematic diagram of an LDPC check matrix H.

[0064] FIG3 is a Tanner graph of an LDPC check matrix H.

[0065] FIG4 is a schematic diagram of the structure of a check matrix.

[0066] FIG5 is a schematic diagram of the information transmission process.

[0067] FIG6 is a schematic flowchart of a communication method 500 based on LDPC codes provided in this application.

[0068] FIG7 is a schematic diagram of α(i) corresponding to each row and b(j) corresponding to each column in the basis matrix.

[0069] FIG8 is a performance simulation diagram of the LDPC code proposed in this application and the LDPC code based on BG1.

[0070] FIG9 is a schematic diagram of a multi-edge LDPC code.

[0071] FIG10 is a schematic block diagram of a communication device 1000 provided in an embodiment of the present application.

[0072] FIG11 is a schematic block diagram of a communication device 1100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] To facilitate understanding of the embodiments of the present application, the following explanations are made before introducing the embodiments of the present application.

[0074] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various digital numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. The present application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the field of communications, for example, it may include the long term evolution (LTE) protocol, the new radio (NR) protocol and related protocols used in future communication systems. The present application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0075] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0076] A communication system to which the embodiments of the present application can be applied is described below.

[0077] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0078] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0079] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of the present application. As shown in Figure 1, the embodiment of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0080] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0081] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0082] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0083] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0084] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, a URLLC (ultra reliable low latency communication) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0085] To facilitate understanding of the embodiments of the present application, several concepts or terms involved in the embodiments of the present application are briefly explained. The concepts or terms introduced below are explained based on the concepts or terms specified in the reference protocol, but this does not mean that the embodiments of the present application can only be applied to existing systems. The concepts or terms involved in the embodiments of the present application can be applied to future systems. The specific names of the concepts or terms (for example, concepts or terms involving functional descriptions) can be adjusted as future systems develop.

[0086] 1. LDPC Code

[0087] LDPC codes are linear block codes that divide the information sequence to be encoded into groups of q bits. The encoder then performs linear operations on these q information bits to obtain m parity bits. These q information bits and the m parity bits are then combined to form a codeword of length n = q + m. The mapping from q information bits to codewords of length n is typically represented by a corresponding parity check matrix H. Based on the parity check matrix H, a codeword sequence is generated to complete the encoding process. After the codeword sequence is transmitted over the channel, the receiving device decodes the received signal and determines the original information bits.

[0088] The LDPC parity check matrix H is a sparse matrix. The number of zero elements in H is far greater than the number of nonzero elements. In other words, the row weight (or column weight) of the parity check matrix is ​​much smaller than the number of elements in each row (or column) of the LDPC matrix. An LDPC code with an information bit sequence length equal to q and a code length equal to n can be uniquely determined by its parity check matrix H.

[0089] In 1981, Tanner represented the check matrix H using a graph. This type of graph is now called a Tanner graph, and there is a one-to-one correspondence between a Tanner graph and a check matrix. A Tanner graph consists of two types of vertices: one type represents codeword bits, called variable nodes, and the other type is a check node, representing a check constraint. Each check node represents a check constraint. This is explained below with reference to Figures 2 and 3.

[0090] FIG2 is a schematic diagram of an LDPC check matrix H.

[0091] In Figure 2, {V i} represents the variable node (VN) set, {C i} represents the set of check nodes (CN). Each row of the check matrix H represents a check equation, each check equation corresponds to a check node, and each column represents a codeword bit, each codeword bit corresponds to a variable node. In Figure 2, there are eight variable nodes and four check nodes. If a codeword bit is included in the corresponding check equation, a line is connected between the variable node and the check node involved, resulting in a Tanner graph.

[0092] FIG3 is a Tanner graph of an LDPC check matrix H.

[0093] As shown in Figure 3, the Tanner graph represents the LDPC parity check matrix. For example, for a parity check matrix H with m rows and n columns, the Tanner graph contains two types of nodes: n variable nodes and m check nodes. The n variable nodes correspond to the n columns of the parity check matrix H, and the m check nodes correspond to the m rows of the parity check matrix H. A cycle in a Tanner graph consists of interconnected vertices. The cycle begins and ends at a vertex in this group and passes through each node only once. The length of a cycle is defined as the number of edges it contains, while the girth of a graph, also known as its perimeter, is defined as the minimum cycle length in the graph. In Figure 3, the girth is 4, as indicated by the black lines. The variable nodes in the Tanner graph correspond to each column of the parity check matrix H, which in turn corresponds to each codeword bit of the LDPC codeword. The check nodes in the Tanner graph correspond to each row of the parity check matrix H, which in turn corresponds to each parity bit of the LDPC codeword. The connections between the two types of nodes correspond to the values ​​of the elements in the H matrix. If there is a connection between the i-th check node and the j-th variable node, the value of the element (i, j) in the H matrix is ​​1. If there is no connection, the corresponding element is 0. The connection between the variable node and the check node can also be called an edge. The connection between the check node and the variable node can also be described as: there is a connection or edge between the check node and the variable node. The edge relationship between the check node and the variable node can include two situations: the existence of an edge or the absence of an edge. In addition, in the Tanner graph, a cycle refers to a closed loop consisting of variable nodes, check nodes and edges connected end to end.

[0094] 2. QC-LDPC code

[0095] Quasi-cyclic low density parity check (QC-LDPC) code is a type of structured LDPC code. Due to the unique structure of its check matrix, a simple feedback shift register can be used for encoding, reducing the coding complexity of the LDPC code. The QC-LDPC code actually used is represented by a base graph (BG), where the elements in BG are 0 or 1. The 1 and 0 in BG are expanded, and the check matrix H obtained after the expansion is completed can be used for encoding or decoding. In the embodiment of the present application, BG can be written in matrix form, which can be referred to as the base matrix H in this application. BG . Basis matrix H BGAn element in the matrix 0 indicates that there is no edge in the base graph, while a value of 1 indicates that there is an edge in the base graph (or that the corresponding checksum is associated with the corresponding variable). NR LDPC codes involve the selection of multiple base graphs. The current standard stores two base graphs, BG1 and BG2. When the message length is less than or equal to 292 characters, or when the message length is less than or equal to 3824 characters and the code rate is less than or equal to 2 / 3, or when the code rate is less than or equal to 0.25, BG2 is used; otherwise, BG1 is used. The following describes the expansion process of the base matrix.

[0096] Based on the basis matrix and the lift value Z c (lifting size), the base matrix can be expanded into a complete check matrix for encoding or decoding. c It can also be called expansion factor, lifting factor, expansion value, expansion coefficient, lifting size, etc. The expansion process is to lift all elements of the basis matrix into a Z c ×Z c A square matrix, where 0 is promoted to Z c ×Z c 0 matrix, promote 1 to a unit matrix and perform a cyclic shift on the unit matrix based on the shifting value (SV) corresponding to 1. The cyclic shift can be to the left or right, which is not limited in this application. It can be understood that each 1 in the base matrix corresponds to a shift value. Taking a 4*4 unit matrix as an example, if the shift values ​​are 0, 1, and 3 respectively, the cyclic shift matrix after the right cyclic shift is as shown:

[0097] (1) When the translation value is 0 (i.e. remains unchanged), the corresponding cyclic shifted matrix is

[0098] (2) When the translation value is 1, the corresponding cyclic shift matrix is

[0099] (3) When the translation value is 3, the corresponding cyclic shift matrix is

[0100] It can also be understood that the complete check matrix H can be represented by an exponential matrix H b Indicates that H b Each element in corresponds to a Z c ×Z c Each element of the submatrix identifies the number of times the corresponding submatrix is ​​cyclically shifted by the identity matrix. As a result, the storage space required for the complete check matrix H is greatly reduced. b The elements in can also be called QC blocks.

[0101] For example, the exponential matrix H of the QC-LDPC code bAs shown below:

[0102] It can be seen that the exponential matrix H b The size of the exponential matrix H is 4 rows and 24 columns. b Each element i in represents a Z c square matrix of order represents the cyclic shift matrix, i represents the cyclic shift value of the cyclic shift matrix, and i is an integer. In addition, the exponential matrix H b The "-1" in represents an all-zero matrix, and "0" represents an identity matrix.

[0103] For example, As shown below:

[0104] Optional, exponential matrix H b In addition to "-1", the zero elements in can also have other representations, such as using "-" or null values ​​to represent an all-zero matrix.

[0105] It can be understood that the above exponential matrix H b The matrix corresponding to the position greater than or equal to 0 is changed to 1, and the position -1 is changed to 0 is the basis matrix. The 1 in the basis matrix is ​​expanded into a cyclic shift matrix based on the elements at the corresponding positions of the exponential matrix, and the 0 is expanded into a 0 matrix of the corresponding scale. After the expansion is completed, the check matrix is ​​obtained.

[0106] 3. Improvement value Z c (Lifting Size) and (Shifting Value)

[0107] The storage contents of the shifting values ​​of the 5G LDPC code include: (1) a lifting size list; and (2) a shifting value list that corresponds one-to-one to the rows of the lifting size list.

[0108] For example, the Lifting Size list is shown in Table 1.

[0109] Table 1

[0110] The jth row of the Lifting Size list contains where a j ∈{2,3,5,7,9,11,13,15}, max(k j)∈{7,7,6,5,5,5,4,4}; the row labels of Lifting Size correspond one-to-one with the column labels of Shifting Value, that is, the lifting size in each row of the Lifting Size list corresponds to a set of Shifting Value.

[0111] For example, the Shifting Value list is shown in Table 2.

[0112] Table 2

[0113] For fixed lift index, a non-zero position in the basis matrix corresponds to a translation value. For example, H BG The translation value of row 0 and column 0 in the lifting index = 0 is 211, H BG The translation value of the 1st row and 6th column in the lifting value index = 3 is 66, H BG The corresponding translation value of the 2nd row and 9th column when the lifting value index = 7 is 206.

[0114] It can be understood that when performing LDPC coding, it is necessary to first determine the boost value, and then determine the corresponding translation value based on the selected boost value to construct the check matrix. For example, if the determined boost value is 40, and the corresponding boost value index of 40 in Table 1 is 2, then the check matrix can be constructed based on the translation value in the column corresponding to the boost value index = 2 in Table 2.

[0115] 4. Column weight and row weight

[0116] For a column of a matrix, column weight can refer to the number of non-zero elements contained in that column. For a row of a matrix, row weight can refer to the number of non-zero elements contained in that row. It can be understood that the matrix involved in the description of row weight and column weight is the check matrix H.

[0117] 5. Structure of the check matrix

[0118] FIG4 is a schematic diagram of the structure of a check matrix.

[0119] As shown in Figure 4 (a), the parity check matrix may include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region may include parts A and B, as shown in Figure 4 (b). Part A corresponds to information bits (also known as information bits, systematic bits, etc.), and part B is a square matrix corresponding to core parity bits (also known as core check bits). The core check bits may be the check bits corresponding to the highest code rate, or may be checks with degrees greater than or equal to 2, or may be check nodes corresponding to the set of rows with the highest row weight (row weight significantly higher than other rows). The all-zero region may correspond to part C in Figure 4 (b), an all-zero matrix. The incremental redundancy region may correspond to part D in Figure 4 (b). The raptor-like region may correspond to part E in Figure 4 (b), a unit matrix corresponding to the parity bits for low-rate extension.

[0120] The parity check matrix of the LDPC code shown in Figure 4 employs a "raptor-like" structure, allowing for gradual expansion to lower code rates using a high-rate core matrix. In practice, as shown in Figure 4 (a), the first X rows and Y columns of the parity check matrix can be truncated. As the code rate decreases, X and Y gradually increase, and the matrix area used also expands.

[0121] It should be noted that the check matrix can be represented by the LDPC base matrix, so the structure of the LDPC base matrix is ​​similar to that of the check matrix, which will not be described in detail here.

[0122] 6. Information column and check column

[0123] The columns of the LDPC basis matrix consist of information columns and check columns.

[0124] Information column: corresponds to the information bit (also called information bit, system bit, etc.), which is the column corresponding to part A.

[0125] Parity column: corresponds to the parity bit (or check digit), and can include a core parity column and an extended parity column. The core parity column is the column corresponding to part B, and the extended parity column is the column corresponding to part C or part E. The extended parity column is also called a raptor-like column.

[0126] 7. Information transmission process

[0127] Figure 5 is a schematic diagram of the information transmission process applicable to the present application. As shown in Figure 5, information is sent by the source, and after processing such as source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, and source recovery, it reaches the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 5 (including source coding, channel coding, and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding, and source recovery shown in Figure 5.

[0128] Currently, the decoding threshold and decoding complexity of QC-LDPC codes are primarily determined by the basis graph (i.e., the basis matrix). A small-scale basis matrix has significant limitations on the degree distribution of LDPC codes, preventing optimal decoding thresholds. This severely impairs the performance of NR LDPC at extremely high code rates. The degree distribution of LDPC codes indicates the column redistribution of the parity check matrix. One possible implementation approach is to increase the decoding threshold by expanding the basis matrix. However, without good orthogonality, large-scale basis matrices have low parallelism and complex hardware implementation.

[0129] In view of this, the present application provides a communication method and a communication device based on LDPC codes, which can effectively solve the above technical problems.

[0130] FIG6 is a schematic flow chart of a communication method 600 based on LDPC codes provided by the present application. The method includes the following steps.

[0131] It is understood that method 600 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or the receiving device itself, or can refer to a device that supports the transmitting device or the receiving device to implement the function. For convenience of description, the following description uniformly uses the transmitting device and the receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0132] S601: A transmitting device obtains an information bit sequence.

[0133] It can be understood that if the transmitting device needs to communicate with the receiving device, that is, the transmitting device needs to send a signal to the receiving device, the transmitting device needs to first obtain the information bit sequence corresponding to the signal to be sent to the receiving device.

[0134] Among them, the transmitting device obtains the information bit sequence, which may refer to: the transmitting device performs source encoding on the source symbols to generate the information bit sequence, or the transmitting device obtains the information bit sequence, which may also refer to: the transmitting device receives the information bit sequence from other communication devices. This application does not limit the method of obtaining the information bit sequence.

[0135] S602: The transmitting end device determines an LDPC check matrix.

[0136] In a possible implementation, the LDPC check matrix is ​​based on the LDPC base matrix, the lifting value Z c , the translation value corresponding to each 1 element in the basis matrix, and the number k of translation values ​​corresponding to each 1 element, where k is an integer greater than or equal to 1 and k corresponding to at least one 1 element in the basis matrix is ​​an integer greater than 1, Z c is an integer greater than 1. The following describes in detail the characteristics of each part used to determine the parity check matrix.

[0137] (1) Basis matrix

[0138] It can be understood that the elements in the basis matrix include 0 and 1, that is, all elements are either 0 or 1.

[0139] Alternatively, a table can be used to store all rows of the basis matrix and the columns associated with each row. When there is an associated column, the value corresponding to that position in the basis matrix is ​​1, otherwise it is 0. For example, the basis matrix can be stored as shown in the first two columns of Table 3 and Table 4.

[0140] Table 3

[0141] (2) Improvement value Z c

[0142] For example, Z c is a boost value in the boost value set shown in Table 1.

[0143] (3) The translation value corresponding to each 1 element in the basis matrix

[0144] Optionally, one element in the basis matrix may correspond to multiple sets of translation values, and the transmitting device can be based on Z c Determine a set of shift values ​​to use. For example, if one element in the base matrix has eight sets of shift values ​​as shown in Table 3 (i.e., one lifting value index corresponds to one set of shift values), and if the determined lifting value is 56, and the lifting value index corresponding to 56 in Table 1 is 3, the transmitting device determines to use the shift values ​​in the column corresponding to the lifting value index = 3 in Table 3 to construct the parity check matrix.

[0145] It is understandable that if based on Z cA set of translation values ​​to be used is determined, and any translation value in the set of translation values ​​is greater than or equal to 0 and less than or equal to Z max -1, where Z max Z c The maximum improvement value in the corresponding group, each row in Table 1 corresponds to a group, that is, Z max is Z in Table 1 c The maximum boost value in the boost value set. For example, Z c is 56, then Z max It is 224.

[0146] Optionally, each set of translation values ​​can be stored based on the format in Table 1, that is, one row number, one column number, and one boost value index correspond to multiple positions (three positions in Table 1), and each position stores a translation value; or, one row number, one column number, and one boost value index in Table 1 correspond to one position, and the one position stores multiple translation values. This application does not limit the storage format of the translation value. For example, one row number, one column number, and one boost value index correspond to one position, and the multiple translation values ​​stored in one position can be written as (SV1, SV2, ...).

[0147] Optionally, an LDPC storage matrix may be defined in the protocol, which indicates the base matrix and the k translation values ​​corresponding to each 1 element in the base matrix. For example, the storage format of the LDPC storage matrix may be as shown in Table 3.

[0148] Optionally, when a certain 1 element in the base matrix corresponds to k translation values ​​greater than 1, a translation value and a function corresponding to the 1 element can be stored in the storage matrix, and the remaining k-1 translation values ​​can be determined based on the stored translation value and the function. (4) The number k of translation values ​​corresponding to each 1 element is based on the above description. The number k of 1 elements in the base matrix is ​​an integer greater than or equal to 1 and the k corresponding to at least one 1 element in the base matrix is ​​an integer greater than 1. It can be seen that each 1 element in the base matrix has a corresponding translation value, and at least one 1 element corresponds to 2 or more translation values. For example, when the lifting value index = 3 in Table 3, the translation values ​​corresponding to the 0th row and 0th column of the base matrix are 216, 211, and 221.

[0149] Optionally, the number k of translation values ​​corresponding to all 1 elements in the information column of the basis matrix is ​​equal to 2 or 3 or 4 or 6.

[0150] The above-mentioned improvement value Z c The k translation values ​​of each 1 element in the and basis matrix are used to indicate that the corresponding 1 element is replaced by k Z c *Z c The cyclic shift matrix of Z c *Z cThe k translation values ​​are k Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix (i.e., k translation values ​​and k Z c *Z c Circular shift matrices correspond one to one).

[0151] The following describes a possible expansion process (or lifting process) for determining a check matrix based on a base matrix, a lifting value, and a translation value.

[0152] Step 1: Before expansion, it is necessary to determine the first index associated with each row in the basis matrix, for example, the first index associated with the i-th row is α(i), and the second index associated with each column in the basis matrix, for example, the second index associated with the j-th column is b(j), where α(i) is an integer greater than or equal to 1, and b(j) is an integer greater than or equal to 1. Then, based on the row i and column j of the basis matrix where the element 1 is located, determine the α(i) and b(j) corresponding to the element 1, where α(i)*b(j) equals the number k of translation values ​​for the element 1. For example, if α(i) = 1 and b(j) = 2 for the element 1, then the number k of translation values ​​for the element 1 is 2. For another example, if α(i) = 1 and b(j) = 3 for the element 1, then the number k of translation values ​​for the element 1 is 3. The transmitting device then constructs a check matrix based on the α(i) and b(j) corresponding to each element 1.

[0153] It can be understood that when α(i) corresponding to all rows of the basis matrix are the same, and b(i) corresponding to all columns of the basis matrix are the same, the number of translation values ​​of all 1 elements in the basis matrix are the same.

[0154] Optionally, the transmitting device can determine α(i) and b(j) on its own. For example, when the number k of translation values ​​of all 1 elements in the basis matrix is ​​the same, α(i) can be assumed to be 1, thereby determining b(i), that is, b(i) is equal to k. For example, when the number k of translation values ​​of all 1 elements in the basis matrix is ​​the same, b(i) can be assumed to be 1, thereby determining a(i), that is, a(i) is equal to k.

[0155] Optionally, the transmitting device can determine α(i) associated with each row in the basis matrix based on the first indication information, where the first indication information indicates α(i) associated with all rows in the basis matrix; and determine b(j) associated with each column in the basis matrix based on the second indication information, where the second indication information indicates b(j) associated with all columns in the basis matrix.

[0156] Optionally, the transmitting device can determine the α(i) associated with each row in the base matrix and the b(j) associated with each column in the base matrix based on the first indication information and the number k of translation values ​​corresponding to 1 element in the base matrix; or, the transmitting device can determine the α(i) associated with each row in the base matrix and the b(j) associated with each column in the base matrix based on the second indication information and the number k of translation values ​​corresponding to 1 element in the base matrix, and the second indication information indicates the second indicator associated with all columns in the base matrix.

[0157] For example, the first indication information is a first sequence, and the length of the first sequence is the same as the total number of rows of the basis matrix. For example, if the basis matrix includes M rows, the first sequence is {α(0), α(1), ..., α(M-1)}, where α(0), α(1), ..., α(M-1) are first indicators associated with the 0th row, the 1st row, ..., and the M-1th row, respectively.

[0158] For example, the second indication information is a second sequence, and the length of the second sequence is the same as the total number of columns of the base matrix. For example, the base matrix includes N columns, and the first sequence is {b(0), b(1), ..., b(N-1)}, where b(0), b(1), ..., b(N-1) are the second indicators associated with the 0th column, the 1st column, ..., and the N-1th row, respectively.

[0159] For example, the first sequence and the second sequence can be predetermined by the protocol. The first sequence and the second sequence are illustrated by example. The base matrix is ​​shown in FIG7 . In the base matrix, α(0), α(1), and α(2) corresponding to the 0th to 2nd rows are 1, 3, and 4, respectively. In the base matrix, b(0), b(1), and b(2) corresponding to the 0th to 2nd columns are 1, 2, and 2, respectively. Then, the first sequence is {1, 3, 4}, and the second sequence is {1, 3, 5}. It can be understood that 1 element in the 0th row and 0th column of the base matrix corresponds to 1 translation value, 1 element in the 1st row and 1st column corresponds to 6 translation values, and 1 element in the 2nd row and 1st column corresponds to 8 translation values.

[0160] Step 2: Construct a check matrix based on the basis matrix, the lifting value, the translation value, α(i), and b(j). Two possible extensions of constructing the check matrix are given below.

[0161] Expansion method 1: segmented expansion

[0162] 1) First expansion stage: Replace the first element of the basis matrix with an all-one matrix of α(i1)*b(j1), and replace the second element of the basis matrix with an all-zero matrix of α(i2)*b(j2), where the first element is a 1 element located in row i1 and column j1, and the second element is a 0 element located in row i2 and column j2.

[0163] 2) Second expansion stage: Replace each 1 in the all-1 matrix of α(i1)*b(j1) corresponding to the first element with Z c *Z c The cyclic shift matrix of the replaced α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix of α(i2)*b(j2) and replacing the 0 in the all-0 matrix of α(i2)*b(j2) with Z c *Z c The LDPC check matrix is ​​obtained by replacing the all-0 matrix with the LDPC check matrix.

[0164] The first extension method is illustrated in conjunction with Table 4. The base matrix determined based on the first two columns of Table 4 is shown in Table 5. The third column of Table 4 is the translation value required for the extension of the base matrix shown in Table 5, where each 1 element includes k=3 translation values. For example, the number of translation values ​​corresponding to the first element in the base matrix is ​​k=α(i1)*b(j1)=1*3, Z c =3.

[0165] Table 4

[0166] Table 5

[0167] Then, based on the description of expansion method 1, first, each first element in the base matrix shown in Table 5 is expanded to a 1*3 all-1 matrix (i.e., a 1-row, 3-column all-1 matrix), and at the same time, each second element in the base matrix is ​​expanded to a 1*3 all-0 matrix (i.e., a 1-row, 3-column all-0 matrix). After the first expansion, the matrix shown in Table 6 is obtained.

[0168] Table 6

[0169] Then, replace each 1 element in each 1*3 all-1 matrix in Table 6 with Z c *Z c (i.e. 3*3) cyclic shift matrix, where the 1*3 Z matrix is ​​obtained by replacing the first element of each matrix with all 1s. c *Z c The cyclic shift matrix is ​​based on the 3 translation value pairs Z of the first element c *Z c The identity matrix is ​​obtained by cyclic shift, and each 0 element in each 1*3 all-0 matrix in Table 6 is replaced by Z c *Z cThe check matrix obtained after the second expansion is shown in Table 7.

[0170] Table 7

[0171] Expansion method 2: direct expansion method

[0172] Replace the first element in the basis matrix with α(i1)*b(j1) Z c *Z c The cyclic shift matrix of α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the second element in the basis matrix with α(i2)*b(j2) Z c *Z c The LDPC check matrix is ​​obtained by converting the all-0 matrix into an LDPC check matrix, in which the first element is the 1 element located at the i1 row and j1 column, and the second element is the 0 element located at the i2 row and j2 column.

[0173] It can be understood that in this expansion method, the α(i1)*b(j1) Z after the first element is expanded c *Z c The cyclic shift matrix forms a (α(i1)*Z c )*(b(j1)*Z c ) matrix, that is, the α(i1)*b(j1) Z c *Z c The cyclic shift matrix places b(j1) Z in each row c *Z c The cyclic shift matrix of , with a(j1) rows in total. Similarly, the second element is expanded into α(i2)*b(j2) Z c *Z c The full 0 matrix forms a (α(i2)*Z c )*(b(j2)*Z c ) is a full 0 matrix, that is, the expanded α(i2)*b(j2) Z c *Z c The full 0 matrix places b(j2) Z in each row c *Z c A matrix of all zeros, with a(j2) rows in total.

[0174] It can be understood that, compared with the first expansion method, the second expansion method can be regarded as directly expanding the check matrix without the first expansion stage, but the final check matrices obtained based on the two expansion methods are the same.

[0175] For example, the α(i1)*b(j1) translation values ​​of the first element in the above expansion method 1 and expansion method 2 are compared with the α(i1)*b(j1) Z values ​​in the order of row first and column later. c *Z c The cyclic shift matrix of α(i1)*b(j1) corresponds to the cyclic shift matrix of α(i1)*b(j1) in the order of columns first and rows. c *Z c For example, the first element corresponds to 6 translation values ​​(SV1, SV2, SV3, SV4, SV5, SV6), and the α(i1)*b(j1) corresponding to the first element is 2*3, so the α(i1)*b(j1) after the first element is expanded is 6 Z c *Z c The cyclic shift matrix of Z is placed in each row. c *Z c The cyclic shift matrix has 2 rows in total. If we follow the corresponding relationship of rows first and columns later, then the 6 Z c *Z c The translation value corresponding to the cyclic shift matrix is If we follow the corresponding relationship of columns first and rows later, then the 6 Z c *Z c The translation value corresponding to the cyclic shift matrix is

[0176] The second extension method is illustrated in conjunction with Table 4. The base matrix determined based on the first two columns of Table 4 is shown in Table 5. The third column of Table 4 is the translation value required for the extension of the base matrix shown in Table 5, where each 1 element includes k=3 translation values. For example, the number of translation values ​​corresponding to the first element in the base matrix is ​​k=α(i1)*b(j1)=1*3, Z c =3.

[0177] Specifically, based on the second extension method, each 1 element in the basis matrix is ​​directly replaced by 1*3 Z c *Z c Circular shift matrix, 1*3 Z c *Z c The cyclic shift matrices are the three translation value pairs Z corresponding to the corresponding first elements. c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the second element in the basis matrix with 1*3 Z c*Z c The LDPC check matrix obtained is shown in Table 7.

[0178] It can be understood that in the above example, the number of translation values ​​corresponding to all 1 elements in the basis matrix is ​​the same, and α(i1) corresponding to the first element is 1. For example, if the number of translation values ​​corresponding to all 1 elements in the basis matrix is ​​12, k = α(i1)*b(j1) = 3*4, then the method of expanding the check matrix is ​​the same. It is only necessary to replace k in the above example with 12, α(i1) with 3, and b(i1) with 4. No further details are given here.

[0179] Similarly, the above extension method is also applicable to the scenario where the number of translation values ​​corresponding to one element in the basis matrix is ​​different. As shown in Table 8, the number of translation values ​​corresponding to one element in the basis matrix is ​​different.

[0180] Table 8

[0181] For ease of understanding, the following example illustrates extended verification in a scenario where the number of translation values ​​corresponding to 1 element in the base matrix is ​​different.

[0182] An example is given in conjunction with Table 9. The basis matrix determined based on the first two columns of Table 9 is shown in Table 5. The third column of Table 4 is the translation value required for the expansion of the basis matrix shown in Table 10, wherein 1 element in the 0th row and 0th column of the basis matrix corresponds to 1 translation value, 1 element in the 1st row and 0th column corresponds to 2 translation values, and 1 element in the 1st row and 1st column corresponds to 4 translation values. For example, α(0)=1 corresponding to the 0th row of the basis matrix, α(1)=2 corresponding to the 1st row, b(0)=1 corresponding to the 0th column, and b(1)=2 corresponding to the 1st row of the basis matrix, then 1 element in the 0th row and 0th column corresponds to 1 translation value number=α(0)*b(0), 1 element in the 1st row and 0th column corresponds to 1 translation value number=α(1)*b(0), 1 element in the 1st row and 1st column corresponds to 1 translation value number=α(1)*b(1), Z c =3.

[0183] Table 9

[0184] Table 10

[0185] For example, the expansion process of determining the check matrix based on the first expansion method is described here. First, each first element in the basis matrix shown in Table 10 is expanded to an all-1 matrix of α(i1)*b(j1), and at the same time, each second element in the basis matrix is ​​expanded to an all-0 matrix of α(i2)*b(j2), where the first element is the 1 element located at the i1 row and j1 column of the basis matrix, and the second element is the 0 element located at the i2 row and j2 column of the basis matrix. After the first expansion, the matrix shown in Table 11 is obtained.

[0186] Table 11

[0187] Then, replace each 1 in the all-1 matrix corresponding to each first element in Table 11 with Z c *Z c (i.e., a 3*3) cyclic shift matrix, where the corresponding α(i1)*b(j1) Z are obtained by replacing the all-1 matrix corresponding to each first element. c *Z c The cyclic shift matrix is ​​based on the α(i1)*b(j1) translation value pairs Z of the first element c *Z c The unit matrix is ​​obtained by cyclic shifting (the k shift values ​​of the first element and the expanded k cyclic shift matrices correspond to each other in the row-first and column-later manner in Table 12), and each 0 element in the all-0 matrix corresponding to each second element in Table 11 is replaced by Z c *Z c (i.e., a 3*3) all-0 matrix, the check matrix obtained after the second expansion is shown in Table 12.

[0188] Table 12

[0189] The above-mentioned method for determining the LDPC check matrix can be applied to scenarios where the number of shift values ​​corresponding to one element in the base matrix is ​​different. However, when the number of shift values ​​is different, the decoding threshold cannot be optimized, and the actual performance is impaired. Therefore, this application proposes another implementation method. When the number of shift values ​​corresponding to one element in the base matrix is ​​different, the number of shift values ​​corresponding to all elements is padded to the same number, and then the check matrix is ​​expanded. This implementation method is described in detail below.

[0190] In another possible implementation, the LDPC check matrix is ​​based on the LDPC base matrix, the lifting value Z c, the translation value corresponding to each 1 element in the basis matrix, and the number of translation values ​​corresponding to each 1 element, wherein the number of translation values ​​corresponding to each 1 element is k, k is an integer greater than 1, the k translation values ​​corresponding to at least one 1 element in the basis matrix include at least one first-class translation value and at least one second-class translation value, and the k translation values ​​corresponding to the remaining 1 elements in the basis matrix except the at least one 1 element are all first-class translation values, and the first-class translation value is greater than or equal to 0 and less than or equal to Z max -1, the second type of translation value is not equal to the first type of translation value, Z max Z c The maximum improvement value in the corresponding group, Z c is an integer greater than 1. The following describes in detail the characteristics of each part used to determine the parity check matrix.

[0191] Regarding (1) the basis matrix and (2) the lift value, please refer to the description in the first implementation method, which will not be repeated here.

[0192] (3) The translation value corresponding to each 1 element in the basis matrix

[0193] Optionally, one element in the basis matrix may correspond to multiple sets of translation values, and the transmitting device can be based on Z c Determine the set of translation values ​​to use. The determination method is described above and will not be repeated here.

[0194] For example, the second type of translation value is equal to -1. As shown in Table 13, 1 element in the base matrix has 8 groups of translation values ​​(i.e., 1 lifting value index corresponds to a group of translation values). For example, when the lifting value index in Table 13 is 3, the translation values ​​corresponding to row 0 and column 0 of the base matrix are -1, 211, and 221, where 211 and 221 are first type of translation values ​​and -1 is second type of translation value.

[0195] Table 13

[0196] (4) The number of translation values ​​k corresponding to each 1 element

[0197] Based on the above description, the number of translation values ​​corresponding to each 1 element is k, where k is an integer greater than 1. The k translation values ​​corresponding to at least one 1 element in the base matrix include at least one first-category translation value and at least one second-category translation value. The k translation values ​​corresponding to the remaining 1 elements in the base matrix except the at least one 1 element are all first-category translation values. It can be seen that each 1 element in the base matrix corresponds to the same number of translation values, and the k translation values ​​corresponding to some of the 1 elements include second-category translation values.

[0198] Optionally, k is equal to 2 or 3 or 4 or 6.

[0199] The above Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k1 Z c *Z c The cyclic shift matrix and k2 Z c *Z c The total 0 matrix, k1 and k2 are the number of the first type of translation values ​​and the number of the second type of translation values ​​in the k translation values, respectively. The sum of k1 and k2 is equal to k, k1 Z c *Z c The cyclic shift matrix is ​​Z c *Z c The k1 first-class translation values ​​are k1 Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix.

[0200] It can be understood that k2 can be equal to 0. When k2=0, it means that the k translation values ​​of element 1 are all first-category translation values.

[0201] It can also be understood that the main difference from the first implementation method is that the k translation values ​​corresponding to some 1 elements in this implementation method include second-type translation values. When the second-type translation values ​​exist, the expansion method corresponding to 1 element is different from the expansion method of 1 element in the first implementation method.

[0202] The following describes a possible expansion process of determining a check matrix based on a base matrix, a lifting value, and a translation value in this implementation.

[0203] Step 1: Before expansion, determine the first index α associated with each row in the basis matrix and the second index b associated with each column in the basis matrix, where α is an integer greater than or equal to 1, and b is an integer greater than or equal to 1. It can be understood that the number of translation values ​​for any 1 element in the basis matrix is ​​k = α(i) * b(j). The transmitting device then constructs a parity check matrix based on α and b corresponding to each 1 element.

[0204] Regarding the method for determining the first indicator α and the second indicator b, please refer to the description in the first implementation method, which will not be repeated here.

[0205] Step 2: Construct a check matrix based on the basis matrix, the lifting value, the translation value, α, and b. Two possible extended methods for constructing the check matrix are given below.

[0206] Expansion method 1: segmented expansion

[0207] 1) The first expansion stage: replace the 1 element in the basis matrix with a matrix of α*b, wherein the k translation values ​​corresponding to the 1 element in the basis matrix correspond one-to-one to the positions of the k elements of the matrix of α*b, wherein if the translation value corresponding to the first position of the matrix of α*b is a first-type translation value, then the element corresponding to the first position is 1; if the translation value corresponding to the first position is a second-type translation value, then the element corresponding to the first position is 0; and, replace each 0 element in the basis matrix with an all-0 matrix of α*b.

[0208] 2) Second expansion stage: Replace each 1 in the matrix of α*b with Z c *Z c The cyclic shift matrix is ​​based on the translation value pair Z corresponding to each 1 position in the matrix of α*b c *Z c The matrix obtained by cyclic shifting the identity matrix of α*b is replaced by Z c *Z c 's all-0 matrix, and replace each 0 in the all-0 matrix of α*b with Z c *Z c The LDPC check matrix is ​​obtained by replacing the all-0 matrix with the LDPC check matrix.

[0209] The first extension method is illustrated with Table 14. The base matrix determined based on the first two columns of Table 14 is shown in Table 15. The third column of Table 14 is the translation value required for the extension of the base matrix shown in Table 15, where each 1 element includes k=3 translation values. For example, the number of translation values ​​corresponding to 1 element in the base matrix is ​​k=α*b=1*3, and Z c =3.

[0210] Table 14

[0211] Table 15

[0212] Then, based on the description of expansion method one, first, each 1 element in the basis matrix shown in Table 15 is expanded to a corresponding 1*3 matrix (i.e., a matrix with 1 row and 3 columns). Taking the 1 element in the 0th row and 0th column of the basis matrix in Table 15 as an example, the three translation values ​​corresponding to the 1 element are -1, 1, and 2. Then, the element ratios in the 1*3 matrix after the expansion of the 1 element are 0, 1, and 1; at the same time, each 0 element in the basis matrix is ​​expanded to a 1*3 matrix of all 0s (i.e., a matrix of all 0s with 1 row and 3 columns). After the first expansion, the matrix shown in Table 16 is obtained.

[0213] Table 16

[0214] After that, each 1 element in each 1*3 matrix in Table 16 is replaced by Z based on the corresponding translation value.c *Z c (i.e. 3*3) cyclic shift matrix, each 0 element replaces Z c *Z c (i.e., a 3*3) all-0 matrix, and replace each 0 element in each 1*3 all-0 matrix in Table 16 with Z c *Z c The check matrix obtained after the second expansion is shown in Table 17.

[0215] Table 17

[0216] Expansion method 2: direct expansion method

[0217] Replace the 1 element in the basis matrix with k1 Z c *Z c The cyclic shift matrix, and k2 Z c *Z c All zero matrices, k1 Z c *Z c The cyclic shift matrices are k1 translation value pairs Z corresponding to 1 element c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the 0 elements in the basis matrix with α*b Z c *Z c The LDPC check matrix is ​​obtained by replacing the all-0 matrix with the LDPC check matrix.

[0218] It can be understood that in this implementation, 1 element corresponds to k1 Z c *Z c Circular shift matrix and k2 Z c *Z c The full 0 matrix forms a (α*Z c )*(b*Z c ), that is, the k1 cyclic shift matrices and the k2 all-0 matrices are placed in b matrices per row, with a total of a rows. Similarly, the α*b Z corresponding to the 0 element c *Z c The full 0 matrix forms a (a*Z c )*(b*Z c ) is a full 0 matrix, that is, the expanded α*b Z c *Z c The full 0 matrix places b Z in each row c *Z c A matrix of all 0s, with a total of a rows.

[0219] It is understandable that compared to the first expansion method, the second expansion method can be regarded as directly expanding the check matrix without the first expansion stage, but the final check matrices obtained based on the two expansion methods are the same. No examples will be given here.

[0220] About Z after 1 element is expanded to k c *Z c The corresponding relationship between the matrix and its k translation values ​​can be found in the description of the first implementation method, which will not be repeated here.

[0221] S603: The transmitting end device encodes the information bit sequence according to the LDPC check matrix to obtain a codeword sequence.

[0222] S604: The transmitting device sends a codeword sequence to the receiving device. Correspondingly, the receiving device receives the codeword sequence from the transmitting device.

[0223] It should be noted that since the codeword sequence may introduce channel noise signals during the transmission process, the LDPC codeword sequence output or sent by the transmitting device may be different from the LDPC codeword sequence received by the receiving device.

[0224] S605: The receiving end device decodes the codeword sequence according to the LDPC check matrix to obtain an information bit sequence.

[0225] The LDC check matrix used by the receiving device for decoding is the same as the LDPC check matrix used by the transmitting device for encoding. The specific method for the receiving device to determine the LDPC check matrix can be referred to the description on the transmitting device side and will not be described in detail here.

[0226] In this technical solution, multiple shift values ​​are assigned to a single element in the base matrix, and based on these shift values, the corresponding single element is expanded into multiple cyclic shift matrices. Compared to the expansion scheme where each element in the base matrix corresponds to a single shift value, this expanded parity check matrix supports larger column weights and has a better decoding threshold. Furthermore, while optimizing the decoding threshold, it does not require expanding the base matrix, thereby reducing hardware implementation complexity.

[0227] FIG8 is a performance simulation diagram of the LDPC code proposed in this application and the LDPC code based on BG1. The horizontal axis of FIG8 is the number of iterations, and the vertical axis is the block error rate (BLER) at 10 -2 The signal to noise ratio (SNR) when .

[0228] In Figure 8, the performance of the LDPC code proposed in this application is used as a benchmark, and a throughput efficiency comparison is made on the basis of the performance of BG1. As shown in Figure 8, it includes 4 lines #1 and 4 lines #2, among which, lines #1 and line #2 with the same shape correspond to a set of simulation results. The code rates used in the four sets of simulation figures are 44 / 47, 11 / 12, 7 / 8, and 3 / 4 from top to bottom, among which line #2 is the performance that can be achieved by the LDPC code proposed in this application after 4 iterations, and line #1 is the performance that can be achieved by 5G BG1 under the number of iterations corresponding to the horizontal axis. It can be seen that the performance of the LDPC code proposed in this application under the four code rates is close to the performance of 8, 7, 7, and 6 rounds of iterations of BG1, respectively.

[0229] For the QC block parallel decoding architecture, the throughput is calculated as:

[0230] where N ldpc is the code length, N frame is the number of packets decoded simultaneously, f clk is the operating frequency, N iteration is the number of decoding iterations, N Zc is the number of QC blocks using the decoding matrix, C layer is the number of decoding clocks for the decoding line. The part that mainly affects the throughput is N Zc , that is, the non-zero number of the decoding matrix during a round of decoding iterations.

[0231] Therefore, combined with hardware evaluation, at different code rates, the final throughput gain of the LDPC code proposed in this application is more than 2 times compared to BG1.

[0232] Currently, there is also a multi-edge (ME) QC-LDPC code. Each 1 element in the base matrix corresponding to this ME LDPC code also corresponds to multiple translation values. However, the expansion method of this ME LDPC code is different from the expansion method proposed in this application. The expansion method of the ME LDPC code is described below with reference to Figure 9.

[0233] Figure 9 is a schematic diagram of a multi-edge LDPC code. In current multi-edge LDPC codes, since each element in the base matrix can be an integer greater than or equal to 2, it means that the position can be expanded into multiple cyclic shift matrices, which are further added to obtain the LDPC check matrix.

[0234] Among them, the number of multiple edges in this application is the sum of the positions in the basis matrix where the element values ​​are greater than or equal to 2, that is, as shown in Figure 9, there are 5 positions with multiple edges, namely: row 1 and column 1, row 1 and column 2, row 1 and column 3, row 1 and column 5, and row 2 and column 1, that is, the number of multiple edges included in the basis matrix shown in Figure 9 is 5.

[0235] The multiplicity of the heavy edge in this application is the specific value of the basis matrix at a position. As shown in Figure 9, the multiplicity of the heavy edge in the first column and the first row is 3; the multiplicity of the heavy edge in the first column and the second row is 2; the multiplicity of the heavy edge in the second column and the first row is 2; the multiplicity of the heavy edge in the third column and the first row is 2; and the multiplicity of the heavy edge in the fifth column and the first row is 2. In the multi-edge LDPC code shown in Figure 9, the maximum value of the heavy edge multiplicity is the maximum value of the aforementioned heavy edge multiplicity, that is, 3.

[0236] It can be understood that multi-edge QC-LDPC codes have a larger degree distribution design space than single-edge QC-LDPC codes (where the base matrix corresponding to single-edge QC-LDPC codes contains both 0 and 1 elements, with 1 elements corresponding to a shift value). Currently, the design goal of LDPC codes is often to ensure an optimal decoding threshold. However, density evolution theory determines the column weight distribution, which is the most important factor affecting the decoding threshold. Therefore, the degree distribution of LDPC codes is a hot topic in code construction research. While multi-edge LDPC codes have the same matrix size as single-edge LDPC codes, they support larger column weights, meaning they have a better decoding threshold. However, in current wireless communication systems, due to the correlation within each QC block in multi-edge LDPC codes, these codes cannot be read, calculated, and stored in parallel. Furthermore, they suffer from high latency, low hardware utilization, and uneven hardware utilization, which impacts the decoding efficiency and performance of LDPC codes. The method proposed in this application can solve the problems of limited degree distribution and small design space of single-sided LDPC by configuring multiple translation values ​​for one element in the basis matrix; at the same time, the expansion method proposed in this application can maintain orthogonality, so that the hardware decoding complexity does not increase compared with single-sided QC-LDPC code, but is greatly reduced compared with multi-sided QC-LDPC code.

[0237] Optionally, in the present application, a generator matrix may be determined first, and LDPC encoding may be performed on the information bit sequence based on the generator matrix. The extended method for determining the generator matrix is ​​the same as the extended method proposed in the present application, and will not be described in detail here.

[0238] It is understood that the steps in the above figures are merely illustrative and not intended to be strict limitations. Furthermore, the sequence numbers of the above processes do not necessarily indicate the order in which they are to be executed. The order in which each process is to be executed should be determined by its function and inherent logic, and should not constitute any limitation on the implementation of the embodiments of this application.

[0239] It can also be understood that some optional features in the various embodiments of the present application may not depend on other features in certain scenarios, and may also be combined with other features in certain scenarios, without limitation.

[0240] It can also be understood that in the above-mentioned various method embodiments, the methods and operations implemented by a device (a transmitting device or a receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0241] The above text, in conjunction with Figures 1 to 9, describes in detail the method embodiments provided by the present application. The following text, in conjunction with Figures 10 and 11, describes the device embodiments of the present application. It will be understood that in order to implement the functions in the above embodiments, the devices in Figures 10 and 11 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily appreciate that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. It will be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0242] Figures 10 and 11 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0243] Figure 10 is a schematic block diagram of a communication device 1000 provided in an embodiment of the present application. As shown in Figure 10 , the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used to process data. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0244] In one possible design, the device 1000 can implement steps or processes corresponding to those performed by the sending end device in the above method embodiment, wherein the processing unit 1020 is used to perform processing-related operations of the sending end device in the above method embodiment, and the communication unit 1010 is used to perform sending-related operations of the sending end device in the above method embodiment.

[0245] In another possible design, the device 1000 can implement steps or processes corresponding to those performed by the receiving device in the above method embodiment, wherein the communication unit 1010 is used to perform reception-related operations of the receiving device in the above method embodiment, and the processing unit 1020 is used to perform processing-related operations of the receiving device in the above method embodiment.

[0246] It can be understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the device 1000 can be specifically the sending end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the sending end device in the above method embodiment, or the device 1000 can be specifically the receiving end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiment. To avoid repetition, it will not be repeated here.

[0247] The apparatus 1000 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the transmitting end device in the above-mentioned method, or the apparatus 1000 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the receiving end device in the above-mentioned method. The functions can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, respectively performing the transmitting and receiving operations and related processing operations in each method embodiment.

[0248] In addition, the above-mentioned communication unit can also be a transceiver circuit (for example, it can include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In an embodiment of the present application, the device in Figure 10 can be the receiving end device or the transmitting end device in the aforementioned embodiment, or it can be a chip or a chip system, such as a system on chip (SoC). Among them, the communication unit can be an input and output circuit, a communication interface; the processing unit is a processor or microprocessor or integrated circuit integrated on the chip. This is not limited here.

[0249] Figure 11 is a schematic block diagram of a communication device 1100 provided in an embodiment of the present application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other via an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0250] Optionally, the apparatus 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 is used to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the apparatus 1100 is used to implement the various processes and steps corresponding to the transmitting end device in the above-mentioned method embodiment. In another possible implementation, the apparatus 1100 is used to implement the various processes and steps corresponding to the receiving end device in the above-mentioned method embodiment.

[0251] It is understood that apparatus 1100 may specifically be the transmitting device or receiving device in the above-described embodiments, or may be a chip or chip system. Correspondingly, transceiver 1120 may be the transceiver circuit of the chip, without limitation herein. Specifically, apparatus 1100 may be used to execute the various steps and / or processes corresponding to the transmitting device or receiving device in the above-described method embodiments.

[0252] Optionally, the memory 1130 may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may include a non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be configured to execute instructions stored in the memory. When the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform the various steps and / or processes of the above-described method embodiments corresponding to the transmitting device or the receiving device.

[0253] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0254] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or by software instructions. The above-mentioned processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The processor in the embodiments of the present application can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0255] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0256] Optionally, the memory (eg, 1130 ) in the embodiment of the present application may be integrated into the processor (eg, 1110 ).

[0257] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the operations and / or processes performed by the sending device or the receiving device in each method embodiment of the present application are executed.

[0258] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending device or the receiving device in the various method embodiments of the present application are executed.

[0259] In addition, the present application further provides a chip, the chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processing performed by the transmitting device or the receiving device in any method embodiment are performed.

[0260] Furthermore, the chip may further include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may further include a memory.

[0261] In addition, the present application also provides a communication system, including a transmitting device and a receiving device in the embodiments of the present application.

[0262] It should also be noted that the memory described herein is intended to comprise, but not be limited to, these and any other suitable types of memory.

[0263] Those skilled in the art will appreciate that the various exemplary units and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented using hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for ease of description and brevity, the specific operating processes of the systems, devices, and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units described is merely a logical functional division. In actual implementation, other divisions may be used, such as multiple units or components being combined or integrated into another system, or some features being omitted or not implemented. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interface, or indirect coupling or communication connection between devices or units, which may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0264] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0265] It should be understood that references to "embodiments" throughout this specification mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, various embodiments throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0266] It can also be understood that in this application, "when", "if" and "if" all mean that the network element will make corresponding processing under certain objective circumstances, which is not a time limit, and does not require the network element to have a judgment action when implementing it, nor does it mean that there are other limitations.

[0267] It is also understood that in each embodiment of the present application, "A corresponds to B" means that B is associated with A, and B can be determined based on A. However, it is also understood that determining B based on A does not mean determining B based solely on A, and B can also be determined based on A and / or other information.

Claims

1. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: obtaining an information bit sequence; Determine an LDPC check matrix, wherein the LDPC check matrix is ​​based on the LDPC base matrix, the lifting value Z c , the translation value corresponding to each 1 element in the base matrix, and the number k of translation values ​​corresponding to each 1 element, where k is an integer greater than or equal to 1 and k corresponding to at least one 1 element in the base matrix is ​​an integer greater than 1, wherein, The Zc and the k shift values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k Zc*Zc cyclic shift matrices, where the cyclic shift matrix is ​​obtained by cyclic shifting the Zc*Zc identity matrix, and the k shift values ​​are respectively the number of cyclic shifts corresponding to the k cyclic shift matrices; Encoding the information bit sequence according to the LDPC check matrix to obtain a codeword sequence; Output the codeword sequence.

2. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Obtain codeword sequence; Determine an LDPC check matrix, wherein the LDPC check matrix is ​​determined based on an LDPC base matrix, a lifting value Zc, a translation value corresponding to each 1 element in the base matrix, and the number k of translation values ​​corresponding to each 1 element, wherein k is an integer greater than or equal to 1 and k corresponding to at least one 1 element in the base matrix is ​​an integer greater than 1, wherein, The Zc and the k shift values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k Zc*Zc cyclic shift matrices, where the cyclic shift matrix is ​​obtained by cyclic shifting the Zc*Zc identity matrix, and the k shift values ​​are respectively the number of cyclic shifts corresponding to the k cyclic shift matrices; The codeword sequence is decoded according to the LDPC check matrix to obtain an information bit sequence.

3. The method according to claim 1 or 2, characterized in that The method further comprises: Determine a first index α(i) associated with the i-th row of the basis matrix, and a second index b(j) associated with the j-th column of the basis matrix, wherein the number k of translation values ​​corresponding to the 1 element located in the i-th row and the j-th column of the basis matrix is ​​equal to α(i)*b(j), wherein α(i) is an integer greater than or equal to 1, and b(j) is an integer greater than or equal to 1.

4. The method according to claim 3, characterized in that The first index associated with any row in the base matrix is ​​1, or the first index associated with any column in the base matrix is ​​1.

5. The method according to claim 3 or 4, characterized in that Determining the LDPC check matrix includes: Replace the first element in the basis matrix with α(i1)*b(j1) Z c *Z c The cyclic shift matrix, the α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix of , and replacing the second element in the basis matrix with α(i2)*b(j2) Z c *Z c The LDPC check matrix is ​​obtained by using the all-0 matrix. The first element is the 1 element located at row i1 and column j1, the second element is the 0 element located at row i2 and column j2, and the α(i1)*b(j1) Z c *Z c The cyclic shift matrix forms a (α(i1)*Z c )*(b(j1)*Z c ) matrix, the α(i2)*b(j2) Z c *Z c The full 0 matrix forms a (α(i2)*Z c )*(b(j2)*Z c ) is an all-zero matrix.

6. The method according to claim 3 or 4, characterized in that Determining the LDPC check matrix includes: Replace the first element with an all-one matrix of α(i1)*b(j1), and replace the second element with an all-zero matrix of α(i2)*b(j2), where the first element is a 1 element located in row i1 and column j1, and the second element is a 0 element located in row i2 and column j2; Replace each 1 in the all-1 matrix of α(i1)*b(j1) with Z c *Z c The cyclic shift matrix of the replaced α(i1)*b(j1) Z c *Z c The cyclic shift matrices are based on the α(i1)*b(j1) translation value pairs Z corresponding to the first element c *Z c The matrix obtained by cyclic shifting the identity matrix of α(i2)*b(j2) is replaced by Z c *Z c The LDPC check matrix is ​​obtained by using an all-0 matrix.

7. The method according to claim 5 or 6, characterized in that The α(i1)*b(j1) translation values ​​of the first element are aligned with the α(i1)*b(j1) Z values ​​in the order of row first and column later. c *Z c The cyclic shift matrix of is in one-to-one correspondence, or, The α(i1)*b(j1) translation values ​​of the first element are aligned with the α(i1)*b(j1) Z values ​​in the order of column first and row later. c *Z c The cyclic shift matrices of are in one-to-one correspondence.

8. The method according to any one of claims 3 to 7, characterized in that The determining of a first index α(i) associated with the i-th row of the basis matrix and a second index b(j) associated with the j-th column of the basis matrix comprises: determining a first index associated with each row of the basis matrix based on first indication information, where the first indication information indicates the first index associated with all rows of the basis matrix; A second index associated with each column of the base matrix is ​​determined based on second indication information, where the second indication information indicates second indices associated with all columns of the base matrix.

9. The method according to any one of claims 3 to 7, characterized in that The determining of a first index α(i) associated with the i-th row of the basis matrix and a second index b(j) associated with the j-th column of the basis matrix comprises: Determine a first index associated with each row of the base matrix and a second index associated with each column of the base matrix based on first indication information and the number k of translation values ​​corresponding to 1 element in the base matrix, wherein the first indication information indicates the first index associated with all rows of the base matrix; or, Based on the second indication information and the number k of translation values ​​corresponding to 1 element in the base matrix, the first indicator associated with each row of the base matrix and the second indicator associated with each column of the base matrix are determined, and the second indication information indicates the second indicators associated with all columns of the base matrix.

10. The method according to claim 8 or 9, characterized in that The first indication information is a first sequence, and / or the second indication information is a second sequence.

11. The method according to any one of claims 1 to 10, characterized in that The number k of translation values ​​corresponding to all 1 elements in the information column of the base matrix is ​​equal to 2, 3, 4 or 6.

12. The method according to any one of claims 1 to 11, characterized in that The storage matrix indicates k translation values ​​corresponding to each 1 element in the base matrix and the LDPC base matrix.

13. The method according to claim 12, characterized in that The storage matrix includes a first translation value and a first function corresponding to a first element in the base matrix, the first element is a 1 element in the base matrix, and the number k of translation values ​​corresponding to the first element is greater than 1, and the method further includes: Other k-1 translation values ​​corresponding to the first element are determined based on the first translation value and the first function.

14. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: obtaining an information bit sequence; Determine an LDPC check matrix, wherein the LDPC check matrix is ​​based on the LDPC base matrix, the lifting value Z c , the translation value corresponding to each 1 element in the base matrix, and the number of translation values ​​corresponding to each 1 element are determined, the number of translation values ​​corresponding to each 1 element is k, and k is an integer greater than 1. The k translation values ​​corresponding to at least one 1 element in the base matrix include at least one first-category translation value and at least one second-category translation value. The k translation values ​​corresponding to the remaining 1 elements in the base matrix except the at least one 1 element are all the first-category translation values, and the first-category translation values ​​are greater than or equal to 0 and less than or equal to Z. max -1, the second type of translation value is not equal to the first type of translation value, the Z max For the Z c The corresponding maximum improvement value, where The Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k1 Z c *Z c The cyclic shift matrix and k2 Z c *Z c The k1 and k2 are the number of the first type of translation values ​​and the number of the second type of translation values ​​in the k translation values ​​of the corresponding 1 element, respectively. The sum of the k1 and the k2 is equal to the k. The k1 Z c *Z c The cyclic shift matrix is ​​Z c *Z c The k1 first-class translation values ​​are the k1 Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix; Encoding the information bit sequence according to the LDPC check matrix to obtain a codeword sequence; Output the codeword sequence.

15. A communication method based on low-density parity check (LDPC) codes, characterized in that: The method comprises: Get LDPC codeword sequence; Determine an LDPC check matrix, wherein the LDPC check matrix is ​​based on the LDPC base matrix, the lifting value Z c , the translation value corresponding to each 1 element in the base matrix, and the number of translation values ​​corresponding to each 1 element are determined, the number of translation values ​​corresponding to each 1 element is k, and k is an integer greater than 1. The k translation values ​​corresponding to at least one 1 element in the base matrix include at least one first-category translation value and at least one second-category translation value. The k translation values ​​corresponding to the remaining 1 elements in the base matrix except the at least one 1 element are all the first-category translation values, and the first-category translation values ​​are greater than or equal to 0 and less than or equal to Z. max -1, the second type of translation value is not equal to the first type of translation value, the Z max For the Z c The corresponding maximum improvement value, where The Z c The k translation values ​​of each 1 element are used to indicate that the corresponding 1 element is replaced by k1 Z c *Z c The cyclic shift matrix and k2 Z c *Z c The k1 and k2 are the number of the first type of translation values ​​and the number of the second type of translation values ​​in the k translation values ​​of the corresponding 1 element, respectively. The sum of the k1 and the k2 is equal to the k. The k1 Z c *Z c The cyclic shift matrix is ​​Z c *Z c The k1 first-class translation values ​​are the k1 Z c *Z c The number of cyclic shifts corresponding to the cyclic shift matrix; The codeword sequence is decoded according to the LDPC check matrix to obtain an information bit sequence.

16. The method according to claim 14 or 15, characterized in that The second type translation value is equal to -1.

17. The method according to any one of claims 14 to 16, characterized in that The method further comprises: Determine a first index α associated with each row of the basis matrix and a second index b associated with each column of the basis matrix, wherein the number k of translation values ​​corresponding to any 1 element in the basis matrix is ​​equal to α*b, α is an integer greater than or equal to 1, and b is an integer greater than or equal to 1.

18. The method according to claim 17, characterized in that The first index associated with any row in the base matrix is ​​1, or the first index associated with any column in the base matrix is ​​1.

19. The method according to claim 17 or 18, characterized in that Determining the LDPC check matrix includes: Replace the 1 element in the basis matrix with k1 Z c *Z c The cyclic shift matrix, and k2 Z c *Z c The all-zero matrix, the k1 Z c *Z c The cyclic shift matrices are k1 translation value pairs Z corresponding to the 1 element c *Z c The matrix obtained by cyclic shifting the identity matrix, and replacing the 0 elements in the basis matrix with α*b Z c *Z c The LDPC check matrix is ​​obtained by using the all-0 matrix. Among them, the k1 Z c *Z c Circular shift matrix and k2 Z c *Z c The full 0 matrix forms a (α*Z c )*(b*Z c ) matrix, the α*b Z c *Z c The full 0 matrix forms a (a*Z c )*(b*Z c ) is an all-zero matrix.

20. The method according to claim 17 or 18, characterized in that Determining the LDPC check matrix includes: Replacing 1 element in the base matrix with an α*b matrix, wherein the k translation values ​​corresponding to the 1 element in the base matrix correspond one-to-one to the positions of the k elements of the α*b matrix, wherein if the translation value corresponding to the first position of the α*b matrix is ​​the first type of translation value, then the element corresponding to the first position is 1; if the translation value corresponding to the first position is the second type of translation value, then the element corresponding to the first position is 0, and replacing each 0 element in the base matrix with an all-0 matrix of α*b; Replace each 1 in the α*b matrix with Z c *Z c The cyclic shift matrix is ​​based on the translation value pair Z corresponding to the position of each 1 in the matrix of α*b c *Z c The matrix obtained by cyclic shifting the identity matrix of α*b is replaced by Z c *Z c , and replace each 0 in the α*b all-zero matrix with Z c *Z c The LDPC check matrix is ​​obtained by using an all-0 matrix.

21. The method according to claim 19 or 20, characterized in that The k1 translation values ​​of the element are compared with the (α*Z c )*(b*Z c ) in the matrix Z c *Z c The matrices are in one-to-one correspondence. or, The k1 translation values ​​of the element are compared with the (α*Z c )*(b*Z c ) in the matrix Z c *Z c The matrices are in one-to-one correspondence.

22. The method according to any one of claims 17 to 21, characterized in that The determining of a first index α associated with each row of the basis matrix and a second index b associated with each column of the basis matrix comprises: determining a first index associated with each row of the basis matrix based on first indication information, where the first indication information indicates the first index associated with all rows of the basis matrix; A second index associated with each column of the base matrix is ​​determined based on second indication information, where the second indication information indicates second indices associated with all columns of the base matrix.

23. The method according to any one of claims 17 to 21, characterized in that The determining of a first index α associated with each row of the basis matrix and a second index b associated with each column of the basis matrix comprises: Determine a first index associated with each row of the base matrix and a second index associated with each column of the base matrix based on first indication information and the number k of translation values ​​corresponding to 1 element in the base matrix, wherein the first indication information indicates the first index associated with all rows of the base matrix; or, Based on the second indication information and the number k of translation values ​​corresponding to 1 element in the base matrix, the first indicator associated with each row of the base matrix and the second indicator associated with each column of the base matrix are determined, and the second indication information indicates the second indicators associated with all columns of the base matrix.

24. The method according to claim 22 or 23, characterized in that The first indication information is a first sequence, and / or the second indication information is a second sequence.

25. The method according to any one of claims 14 to 24, characterized in that The k is equal to 2 or 3 or 4 or 6.

26. The method according to any one of claims 14 to 25, characterized in that The storage matrix indicates the base matrix and k translation values ​​corresponding to each 1 element in the base matrix.

27. The method according to claim 26, characterized in that The storage matrix includes a first translation value and a first function corresponding to a first element in the base matrix, the first element is a 1 element in the base matrix, and the number k1 of first-type translation values ​​corresponding to the first element is greater than 1, and the method further includes: Based on the first translation value and the first function, other k1-1 first-category translation values ​​corresponding to the first element are determined.

28. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 27 through a logic circuit or executing computer instructions.

29. The communication device according to claim 28, wherein: Also included is a memory for storing the computer instructions.

30. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction, and when the computer program or instruction is executed by the communication device, the method according to any one of claims 1 to 27 is implemented.

31. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 27.

32. A communication device, characterized in that: The method comprises modules or units for performing the method according to any one of claims 1 to 27.

33. A communication system, characterized in that: It includes a sending end device and a receiving end device, the sending end device is used to execute the method as described in any one of claims 1 or 3-13, or the method as described in any one of claims 14 or 16-27; the receiving end device is used to execute the method as described in any one of claims 2-13, or the method as described in any one of claims 15-27.

Images