Memory operation method and apparatus, and device, storage medium and program product

Abstract

Provided in the present disclosure are a memory operation method and apparatus, and a device, a storage medium and a program product. The method may comprise: acquiring a memory operation request for a memory, wherein the memory operation request is used for requesting memory allocation or requesting memory release, the memory comprises a plurality of memory blocks, and the plurality of memory blocks correspond to at least two memory granularities; determining memory block information that corresponds to at least one memory granularity, wherein the memory block information comprises a memory granularity value, a memory block state and memory block usage information; and processing the memory operation request on the basis of the memory block information that corresponds to the at least one memory granularity, so as to perform memory allocation or memory release. The method of the present disclosure improves the flexibility of an operation for a memory.

Description

[0001] Memory Operation Method, Apparatus, Device, Storage Medium, and Program Product This disclosure claims priority to Chinese patent application number 202410211042.3, filed with the China Patent Office on February 26, 2024, entitled "Memory Operation Method, Apparatus, Device, Storage Medium, and Program Product," the entire contents of which are incorporated herein by reference. Technical Field This disclosure relates to the field of storage, and more particularly to a memory operation method, apparatus, device, storage medium, and program product. Background: Electronic devices may be provided with memory. In electronic devices, memory may be managed according to memory granularity. In related art, in some scenarios, memory may be divided into multiple memory blocks according to a first memory granularity (e.g., 4K (kilo) granularity) for memory operations; in other scenarios, memory may be divided into multiple memory blocks according to a second memory granularity (e.g., 2M (mega) granularity) for memory operations. However, in the two aforementioned approaches, when operating memory at the first memory granularity, scenarios requiring the second memory granularity cannot be accommodated; and when operating memory at the second memory granularity, scenarios requiring the first memory granularity cannot be accommodated. As can be seen from the above, the flexibility of memory operations in the related art is poor. SUMMARY OF THE INVENTION Various aspects of the present disclosure provide a memory operation method, apparatus, device, storage medium, and program product to improve the flexibility of memory operations. In a first aspect, an embodiment of the present disclosure provides a memory operation method, comprising: obtaining a memory operation request for a memory, the memory operation request being used to request memory allocation or memory release, the memory including multiple memory blocks corresponding to at least two memory granularities; determining memory block information corresponding to at least one memory granularity, the memory block information including a memory granularity value, a memory block status, and memory block usage information; and processing the memory operation request based on the memory block information corresponding to the at least one memory granularity to allocate or release memory.In one possible embodiment, the memory operation request is used to request memory allocation, and the memory operation request includes a requested memory granularity and a memory request amount corresponding to the requested memory granularity. Processing the memory operation request based on memory block information corresponding to at least one memory granularity to perform memory allocation includes: determining memory block information corresponding to the requested memory granularity; determining a target memory block corresponding to the requested memory granularity based on the memory block information corresponding to the requested memory granularity and the memory request amount, wherein the memory granularity of the target memory block is the requested memory granularity and the memory block status of the target memory block is free; and allocating the target memory block corresponding to the requested memory granularity. In one possible embodiment, the requested memory granularity is smaller than a maximum memory granularity; determining memory block information corresponding to the requested memory granularity includes: determining a previous-level memory granularity corresponding to the requested memory granularity, wherein the memory block corresponding to the previous-level memory granularity is divided into multiple memory blocks corresponding to the requested memory granularity; determining a first linked list address in the memory block information corresponding to the previous-level memory granularity; and determining the memory block information corresponding to the requested memory granularity based on the first linked list address. In a possible implementation, determining the target memory block based on the memory block information corresponding to the applied memory granularity and the memory application amount includes: judging whether the applied memory granularity is the maximum memory granularity; if so, determining the target memory block in at least one memory block corresponding to the applied memory granularity when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount; if not, determining the target memory block in at least one memory block corresponding to the applied memory granularity when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount; and updating the at least one memory block when the total amount of memory corresponding to the applied memory granularity is less than the memory application amount, and determining the target memory block in the at least one updated memory block. In one possible implementation, updating the at least one memory block includes: determining a first memory block based on the requested memory granularity, where the memory granularity of the first memory block is greater than the requested memory granularity, and the memory block state of the first memory block is an idle state; splitting the first memory block to obtain multiple second memory blocks, where the memory granularity of the second memory block is the requested memory granularity; and determining that the at least one updated memory block includes the at least one memory block and the multiple second memory blocks.In one possible embodiment, the method further includes: determining a first memory granularity corresponding to the first memory block, determining first memory block information corresponding to the first memory granularity, and updating the first memory block information based on the first memory block; determining second memory block information corresponding to the requested memory granularity, and updating the second memory block information based on the plurality of second memory blocks. In one possible embodiment, determining the target memory block in at least one memory block corresponding to the requested memory granularity includes: determining a first number of target memory blocks based on the requested memory amount and the requested memory granularity; determining whether a first number of contiguous memory blocks exists in the at least one memory block; if so, determining the first number of contiguous memory blocks as the target memory block; if not, when the memory operation request indicates that discontinuous memory allocation is permitted, determining the first number of discontinuous memory blocks in the at least one memory block as the target memory block, where the sum of the memory of the discontinuous memory blocks is greater than or equal to the requested memory amount. In one possible embodiment, the method further includes: updating the memory block information corresponding to the requested memory granularity based on the target memory block. In one possible embodiment, the memory operation request is used to request memory release; the memory operation request includes a memory granularity to be released and a memory address corresponding to each memory granularity to be released; and processing the memory operation request based on memory block information corresponding to at least one memory granularity to release memory includes: determining at least one to-be-released memory block corresponding to the memory granularity based on the memory block information corresponding to the memory granularity to be released and the memory address; and clearing the at least one to-be-released memory block to release the at least one memory block. In one possible embodiment, the method further includes: updating memory block information corresponding to the memory granularity to be released based on the at least one memory block. In one possible embodiment, the method further includes: if the memory granularity to be released is smaller than the maximum memory granularity, and if the memory block status in third memory block information corresponding to the memory granularity is all in an idle state, merging multiple memory blocks based on the third memory block information to obtain a third memory block, where the memory granularity of the third memory block is the maximum memory granularity; updating the memory block information corresponding to the maximum memory granularity based on the third memory block, and deleting the third memory block information.In a second aspect, an embodiment of the present disclosure provides a memory operation device, comprising: an acquisition module, a determination module, and a processing module, wherein the acquisition module is configured to acquire a memory operation request for a memory, where the memory operation request is used to request memory allocation or memory release, and the memory includes multiple memory blocks, and the multiple memory blocks correspond to at least one memory granularity; the determination module is configured to determine memory block information corresponding to the at least one memory granularity, where the memory block information includes a memory granularity value, a memory block status, and memory block usage information; and the processing module is configured to process the memory operation request based on the memory block information corresponding to the at least one memory granularity to allocate or release memory. In one possible embodiment, the memory operation request is used to request memory allocation, and the memory operation request includes a requested memory granularity and a memory request amount corresponding to the requested memory granularity; the processing module is specifically configured to: determine memory block information corresponding to the requested memory granularity; determine a target memory block corresponding to the requested memory granularity based on the memory block information and the memory request amount corresponding to the requested memory granularity, wherein the memory granularity of the target memory block is the requested memory granularity, and the memory block status of the target memory block is an idle state; and allocate the target memory block corresponding to the requested memory granularity. In one possible embodiment, the requested memory granularity is smaller than the maximum memory granularity; the processing module is specifically configured to: determine a previous-level memory granularity corresponding to the requested memory granularity, wherein the memory block corresponding to the previous-level memory granularity is divided into multiple memory blocks corresponding to the requested memory granularity; determine a first linked list address in the memory block information corresponding to the previous-level memory granularity; and determine the memory block information corresponding to the requested memory granularity based on the first linked list address. In a possible implementation, the processing module is specifically used to: determine whether the applied memory granularity is the maximum memory granularity; if so, when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount, determine the target memory block in at least one memory block corresponding to the applied memory granularity; if not, when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount, determine the target memory block in at least one memory block corresponding to the applied memory granularity; when the total amount of memory of at least one memory block corresponding to the applied memory granularity is less than the memory application amount, update the at least one memory block and determine the target memory block in the at least one updated memory block.In one possible embodiment, the processing module is specifically configured to: determine a first memory block based on the requested memory granularity, wherein the memory granularity of the first memory block is greater than the requested memory granularity, and the memory block state of the first memory block is an idle state; split the first memory block to obtain multiple second memory blocks, wherein the memory granularity of the second memory block is the requested memory granularity; and determine that at least one updated memory block includes the at least one memory block and the multiple second memory blocks. In one possible embodiment, the device further includes: an update module, wherein the update module is configured to: determine a first memory granularity corresponding to the first memory block, determine first memory block information corresponding to the first memory granularity, and update the first memory block information based on the first memory block; determine second memory block information corresponding to the requested memory granularity, and update the second memory block information based on the multiple second memory blocks. In one possible embodiment, the processing module is specifically configured to: determine a first number of target memory blocks based on the memory request amount and the requested memory granularity; determine whether a first number of contiguous memory blocks exists in the at least one memory block; if so, determine the first number of contiguous memory blocks as the target memory blocks; if not, when the memory operation request indicates that discontinuous memory allocation is permitted, determine the first number of discontinuous memory blocks in the at least one memory block as the target memory blocks, where the sum of the memory of the discontinuous memory blocks is greater than or equal to the memory request amount. In one possible embodiment, the updating module is further configured to: update memory block information corresponding to the requested memory granularity based on the target memory blocks. In one possible embodiment, the memory operation request is used to request memory release; the memory operation request includes a memory release granularity and a memory address corresponding to the memory release granularity; the processing module is specifically configured to: determine at least one to-be-released memory block corresponding to the memory release granularity based on the memory block information corresponding to the memory release granularity and the memory address; and clear the at least one to-be-released memory block to release the at least one memory block. In a possible implementation, the updating module is further configured to: update the memory block information corresponding to the released memory granularity according to the at least one memory block.In one possible implementation, the processing module is further configured to, if the released memory granularity is smaller than the maximum memory granularity and if the memory block states in the third memory block information corresponding to the released memory granularity are all in the idle state, merge multiple memory blocks according to the third memory block information to obtain a third memory block, wherein the memory granularity of the third memory block is the maximum memory granularity; and the updating module is further configured to update the memory block information corresponding to the maximum memory granularity according to the third memory block and delete the third memory block information. In a third aspect, an embodiment of the present disclosure provides an electronic device comprising: a memory and a processor; the memory storing computer-executable instructions; the processor executing the computer-executable instructions stored in the memory, causing the processor to perform any of the methods described in the first aspect. In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, which, when executed by the processor, are used to implement any of the methods described in the first aspect. In a fifth aspect, an embodiment of the present disclosure provides a computer program product comprising a computer program, which, when executed by the processor, implements any of the methods described in the first aspect. Embodiments of the present disclosure provide a memory operation method, apparatus, device, storage medium, and program product. An electronic device can obtain a memory operation request for memory and determine memory block information corresponding to at least one memory granularity. The electronic device can then process the memory operation request based on the memory block information corresponding to the at least one memory granularity to allocate or release memory. Because the memory can include multiple memory blocks corresponding to at least two memory granularities, and each memory granularity has corresponding memory block information, when allocating or releasing memory, operations can be performed on multiple memory blocks corresponding to any memory granularity in the memory based on the memory block information, as needed. This improves the flexibility of memory operations compared to prior art methods that include multiple memory blocks corresponding to only one memory granularity and perform operations based on only that one memory granularity. BRIEF DESCRIPTION OF THE DRAWINGS The drawings described herein are provided to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their description are provided to explain the present disclosure and are not intended to unduly limit the present disclosure.In the accompanying drawings: FIG1 is a schematic diagram of a scenario provided by an exemplary embodiment of the present disclosure; FIG2 is a schematic diagram of a memory operation flow provided by an exemplary embodiment of the present disclosure; FIG3 is a schematic diagram of memory block information corresponding to at least one memory granularity provided by an exemplary embodiment of the present disclosure; FIG4 is a schematic diagram (I) of a first linked list and a second linked list provided by an exemplary embodiment of the present disclosure; FIG5 is a schematic diagram of a flow chart of another memory operation method provided by an exemplary embodiment of the present disclosure; FIG6 is a schematic diagram (II) of a first linked list and a second linked list provided by an exemplary embodiment of the present disclosure; FIG7 is a schematic diagram of a flow chart of yet another memory operation method provided by an exemplary embodiment of the present disclosure; FIG8 is a schematic diagram of the structure of a memory operation device provided by an exemplary embodiment of the present disclosure; FIG9 is a schematic diagram of the structure of another memory operation device provided by an exemplary embodiment of the present disclosure; FIG10 is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, storage, and display, etc.) involved in this disclosure are all information and data authorized by the user or fully authorized by all parties. The collection, use, and processing of the relevant data must comply with relevant laws, regulations, and standards, and corresponding operation portals are provided for the user to choose to authorize or reject. To further clarify the objectives, technical solutions, and advantages of the present disclosure, the technical solutions of the present disclosure will be described clearly and completely below in conjunction with specific embodiments of the present disclosure and the corresponding drawings. Obviously, the described embodiments represent only some, and not all, embodiments of the present disclosure. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present disclosure without inventive effort are within the scope of protection of the present disclosure. FIG1 is a schematic diagram of a scenario provided by an exemplary embodiment of the present disclosure. Referring to FIG1 , a memory may include multiple memory blocks. The multiple memory blocks may be memory block 1, memory block 2, ..., memory block n. The multiple memory blocks may correspond to at least one memory granularity. For example, the at least one memory granularity may include at least one of the following: 1G (giga) granularity, 2M granularity, 16K granularity, 4K granularity, and so on. For example, the memory granularity corresponding to memory block 1 and memory block 2 may be 2M, i.e., the size of memory block 1 and memory block 2 is 2M; the memory granularity corresponding to memory block 3 may be 4K, i.e., the size of memory block 3 is 4K. The electronic device may receive a memory operation request and, based on the memory operation request, perform memory allocation or memory release on multiple memory blocks corresponding to at least one memory granularity.For example, if a memory operation request requests allocation of 1GB of memory and the memory granularity is 2MB, 512 memory blocks of 2MB granularity can be determined in the memory based on the memory operation request to allocate the 512 memory blocks. In related art, in some scenarios, memory operations can be performed by dividing the memory into multiple memory blocks according to a first memory granularity (e.g., 4KB granularity); in other scenarios, memory operations can be performed by dividing the memory into multiple memory blocks according to a second memory granularity (e.g., 2MB granularity). However, in these two approaches, when operating the memory at the first memory granularity, scenarios requiring the use of the second memory granularity cannot be accommodated; and when operating the memory at the second memory granularity, scenarios requiring the use of the first memory granularity cannot be accommodated. Therefore, in related art, memory operations lack flexibility. In embodiments of the present disclosure, the memory can include multiple memory blocks corresponding to at least two memory granularities. After receiving a memory operation request, the electronic device can process the memory operation request based on memory block information corresponding to at least one memory granularity to perform operations such as allocating or releasing memory. Because the memory may include multiple memory blocks corresponding to at least two memory granularities, and each memory granularity has corresponding memory block information, when allocating or releasing memory, operations can be performed on multiple memory blocks corresponding to any memory granularity in the memory based on the memory block information as needed. This improves the flexibility of memory operations compared to the prior art, where the memory includes multiple memory blocks corresponding to only one memory granularity and operations are performed based only on that memory granularity. The technical solutions disclosed herein are described in detail below through specific embodiments. It should be noted that the following embodiments may exist independently or in combination, and identical or similar content will not be repeated in different embodiments. Figure 2 is a schematic flow diagram of a memory operation provided by an exemplary embodiment of the present disclosure. Referring to Figure 2, the method may include:

[0002] S201. Obtain a memory operation request for a memory. The execution subject of the embodiments of the present disclosure may be an electronic device or a memory operation device provided in the electronic device. The memory operation device may be implemented via software or a combination of software and hardware. The memory operation device may be a processor in the electronic device. For ease of understanding, the following description uses the electronic device as an example. A memory may include multiple memory blocks, each of which may correspond to at least one memory granularity. For example, as shown in FIG1 , the memory may include n memory blocks (n is an integer greater than or equal to 2), where the memory granularity of memory block 1 and memory block 2 may be 2M, and the memory granularity of memory block 3 may be 4K. The memory operation request may be used to request memory allocation or memory release. The electronic device may obtain the memory operation request for the memory in response to a user operation on the memory. For example, memory operation request 1 may request to allocate 1.5G memory with a memory granularity of 2M, memory operation request 2 may request to allocate 2.5M memory with a memory granularity of 4K; memory operation request 3 may request to release a memory block with a memory address of address B with a granularity of 2M.

[0003] S202. Determine memory block information corresponding to at least one memory granularity. Since the memory may include multiple memory blocks corresponding to at least one memory granularity, information about the multiple memory blocks can be recorded according to the memory granularity to obtain memory block information corresponding to at least one memory granularity. The memory block information corresponding to at least one memory granularity is described below with reference to FIG3 . FIG3 is a schematic diagram of memory block information corresponding to at least one memory granularity according to an exemplary embodiment of the present disclosure. Referring to FIG3 , if the memory includes n memory blocks of 2M granularity, namely, memory block 1, memory block 2, ..., memory block n, then memory block information 1 corresponding to the 2M granularity may include information about these n memory blocks. If memory block 2 is divided into multiple memory blocks of 4K granularity, then memory block information 2 corresponding to the 4K granularity may include information about the multiple 4K memory blocks corresponding to memory block 2. Similarly, memory block information 3 may include information about the multiple 4K memory blocks corresponding to memory block 5. Memory block information 4 may include information about the multiple 4K memory blocks corresponding to memory block 8. Therefore, as shown in Figure 3, a 2M granularity may correspond to memory block information 1, and a 4K granularity may correspond to three memory block information items: memory block information 2, memory block information 3, and memory block information 4. Memory block information may include memory granularity value, memory block status, and memory block usage information. Optionally, memory block information may also include memory range, current allocation address, and so on. For any memory block, a corresponding memory block status may be assigned, including idle state, used state, error state, reserved state, and split state. Each memory block status may be represented by a corresponding number. For example, the idle state may be represented by "0," the used state by "1," the error state by "2," the reserved state by "3," and the split state by "4." Since any memory block status can be represented by a number, the memory block status of multiple memory blocks corresponding to any memory granularity may be represented by an array. For example, as shown in FIG3 , if there are n memory blocks of 2M granularity in the memory, the memory block status of these n memory blocks of 2M granularity can be represented as an array [1, 4, 0, 0, 4, 0, 2, 4, 0, 3, 0, 0, 0, 2, … , where the first bit is 1, indicating that the memory block status of memory block 1 is in use, and the second bit is 4, indicating that the memory block status of memory block 2 is split. The memory block usage information may include the number of memory blocks corresponding to each memory block status.A memory range can be represented by the memory's starting address and ending address. For example, the starting address of memory 1 can be 0x00000000, and the ending address can be 0x40000000. Alternatively, a memory range can also be represented by the memory's starting address and memory length. For example, the starting address of memory 1 can be 0x00000000, and the memory length can be 1GB. The currently allocated address can be used to record the starting address of a free memory block. The current allocated address is initially 0 and changes as memory is allocated or released. Optionally, memory block information can be presented in a data table. Optionally, if the memory granularity is the minimum memory granularity, the memory block information corresponding to that memory granularity can also include the address of the next memory block information corresponding to the next level of memory granularity, as well as an index number. The index number can be used to indicate the memory block identifier corresponding to the previous level of memory granularity corresponding to the multiple memory blocks corresponding to the memory block information. For example, if the memory granularity is 4K and the minimum memory granularity is 4K, the memory block information 2 corresponding to the 4K granularity can be shown in Table 1: Table 1. Address 3 may be the address of memory block information 3. Optionally, if the memory granularity is not the minimum memory granularity, the memory block information corresponding to the memory granularity may further include a first linked list address and a second linked list address. The first linked list address may be used to determine a first linked list. The first linked list may include at least one memory block information corresponding to the next level of memory granularity. In the first linked list, each memory block information item has an idle state, that is, there is an idle memory block among the multiple memory blocks corresponding to each memory block information item. For example, the first linked list may be a partial linked list. The second linked list address may be used to determine a second linked list. The second linked list may include at least one memory block information corresponding to the next level of memory granularity. In the second linked list, each memory block information item has no idle state, that is, there is no idle memory block among the multiple memory blocks corresponding to each memory block information item. For example, the second linked list may be a full linked list. For example, if the memory granularity is 2M and the minimum memory granularity is 4K, then the memory block information 1 corresponding to the 2M granularity may be as shown in Table 2: Table 2 The first linked list and the second linked list are described below with reference to FIG4 . FIG4 is a schematic diagram of the first and second linked lists provided in an exemplary embodiment of the present disclosure. For example, as shown in FIG4 , if there is memory block information 1 corresponding to a 2M granularity, memory block information 2, memory block information 3, and memory block information 4 corresponding to a 4K granularity, as shown in FIG3 , if memory block information 1 includes the first linked list address as address 1 and the second linked list address as address 2; memory block information 2 includes the address of the next memory block information as address 3, then the addresses of the next memory block information included in memory block information 3 and memory block information 4 are empty. If the memory block status in memory block information 2 and memory block information 3 is in an idle state, then the first linked list address in memory block information 1, i.e., address 1, may be the address of memory block information 2, and the address of the next memory block information in memory block information 2, i.e., address 3, may be the address of memory block information 3. The first linked list may include memory block information 2 and memory block information 3. If the memory block status in memory block information 4 is not in an idle state, then the second linked list address in memory block information 1, i.e., address 2, may be the address of memory block information 4. The second linked list may include memory block information 4. For example, if memory operation request 1 requests allocation of 1.5 GB of memory with a memory granularity of 2 MB, and memory operation request 2 requests allocation of 2.5 MB of memory with a memory granularity of 4 KB, the electronic device may determine memory block information 1 corresponding to the 2 MB granularity based on memory operation request 1; and may determine memory block information 2, memory block information 3, and memory block information 4 corresponding to the 4 KB granularity based on memory operation request 2.

[0004] S203: Process the memory operation request based on the memory block information corresponding to at least one memory granularity to allocate memory or release memory. Because the memory block information corresponding to any memory granularity includes memory block statuses of multiple memory blocks, the electronic device can read the memory block information and process the memory operation request based on the memory block statuses of the multiple memory blocks to allocate memory or release memory. For example, if memory operation request 1 requests allocation of 1.5GB of memory with a memory granularity of 2MB, and memory operation request 2 requests allocation of 2.5MB of memory with a memory granularity of 4KB, and assuming that there is memory block information 1 corresponding to the 2MB granularity, and memory block information 2, memory block information 3, and memory block information 4 corresponding to the 4KB granularity, the electronic device may determine 768 2MB memory blocks in the free state from memory block information 1 and allocate these 768 2MB memory blocks to process memory operation request 1. Furthermore, if 640 4KB memory blocks in the free state are determined from memory block information 2, memory block information 3, and memory block information 4, the electronic device may allocate these 640 4KB memory blocks to process memory operation request 2. In embodiments of the present disclosure, the electronic device may obtain a memory operation request for a memory and determine memory block information corresponding to at least one memory granularity. Furthermore, the electronic device may process the memory operation request based on the memory block information corresponding to the at least one memory granularity to allocate or release memory. Since the memory may include multiple memory blocks corresponding to at least two memory granularities, and each memory granularity has corresponding memory block information, when allocating or releasing memory, operations can be performed on multiple memory blocks corresponding to any memory granularity in the memory according to actual needs based on the memory block information. Compared with the prior art in which the memory only includes multiple memory blocks corresponding to one memory granularity and the memory is only operated based on this memory granularity, the flexibility of memory operations is improved. Below, based on the embodiment shown in Figure 2, in conjunction with Figure 5, the process of requesting memory allocation is described in detail; in conjunction with Figure 7, the process of requesting memory release is described in detail. Figure 5 is a flow chart of another memory operation method provided by an exemplary embodiment of the present disclosure. Referring to Figure 5, the method may include:

[0005] S501. Obtain a memory operation request for a memory. The memory operation request can be used to request memory allocation. The memory operation request includes a memory application granularity and a memory application amount corresponding to the memory application granularity. For example, the memory application granularity can be any of the following: 1G granularity, 2M granularity, 16K granularity, 4K granularity, etc. The electronic device can obtain a memory operation request in response to a user's operation on the memory. For example, the electronic device can obtain a memory operation request 1 requesting the allocation of 1.5G memory with a memory granularity of 2M, and a memory operation request 2 requesting the allocation of 2.5M memory with a memory granularity of 4K. Then, the memory application granularity in the memory operation request 1 is 2M granularity, and the memory application amount is 1.5G; the memory application granularity in the memory operation request 2 is 4K granularity, and the memory application amount is 2.5Mo.

[0006] S502: Determine memory block information corresponding to at least one memory granularity. It should be noted that the execution process of step S502 can refer to step S202 and will not be repeated here.

[0007] S503. Determine the memory block information corresponding to the requested memory granularity. Optionally, determining the memory block information corresponding to the requested memory granularity may include the following two cases: Case 1: The requested memory granularity is the maximum memory granularity. For example, if the memory includes two memory granularities, 2MB and 4KB, the maximum memory granularity is 2MB, and memory block information 1 corresponding to the 2MB granularity exists (as shown in Table 2), if the requested memory granularity is 2MB, the electronic device may determine that the memory block information corresponding to the requested memory granularity 2MB is memory block information 1. Case 2: The requested memory granularity is smaller than the maximum memory granularity. In this case, the memory block information corresponding to the requested memory granularity may be determined in the following manner: determining the upper-level memory granularity corresponding to the requested memory granularity; determining a first linked list address in the memory block information corresponding to the upper-level memory granularity; and determining the memory block information corresponding to the requested memory granularity based on the first linked list address. For example, if the memory includes two memory granularities, 2M and 4K, the maximum memory granularity is 2M, and the requested memory granularity is 4K, then for the requested memory granularity of 4K, the previous memory granularity is 2M. Among the multiple memory blocks corresponding to the previous memory granularity, some memory blocks are divided into multiple memory blocks corresponding to the requested memory granularity. For example, as shown in FIG3 , among the multiple memory blocks corresponding to the 2M granularity, memory block 3, memory block 5, and memory block 8 are divided into multiple memory blocks corresponding to the 4K granularity. For example, if, as shown in FIG4 , there is memory block information 1 corresponding to the 2M granularity, and memory block information 2, memory block information 3, and memory block information 4 corresponding to the 4K granularity, if the requested memory granularity is 4K, the electronic device can determine the first linked list address, i.e., address 1, from memory block information 1, then determine memory block information 2 corresponding to the requested memory granularity of 4K based on address 1, and further determine memory block information 3 based on address 3 in memory block information 2. It should be noted that, since the memory operation request is a request for memory allocation, and there are idle memory blocks among the multiple memory blocks corresponding to each piece of memory block information in the first linked list, it is sufficient to determine the multiple memory block information in the first linked list based on the first linked list address; and since there are no idle memory blocks among the multiple memory blocks corresponding to each piece of memory block information in the second linked list, there is no need to determine the multiple memory block information in the second linked list based on the second linked list address.

[0008] S504. Determine whether the requested memory granularity is the maximum memory granularity. If so, execute S505; if not, execute S506. For example, if the memory includes two memory granularities, 2M and 4K, and if the requested memory granularity is 2M, it can be determined that the requested memory granularity is the maximum memory granularity of 2M, and execute S505; if the requested memory granularity is 4K, it can be determined that the requested memory granularity of 4K is smaller than the maximum memory granularity of 2M, and execute S506.

[0009] S505: When the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount, determine a target memory block from at least one memory block corresponding to the requested memory granularity. Since the memory includes at least one memory granularity, and the at least one memory granularity includes the requested memory granularity, the total amount of memory corresponding to the requested memory granularity can be determined in the memory. When the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount, determine the target memory block from at least one memory block corresponding to the requested memory granularity. The memory granularity of the target memory block can be the requested memory granularity, and the memory block status of the target memory block can be idle. For example, if the requested memory granularity is 2MB, and the memory granularity of memory block 3 and memory block 4 is 2MB, and the memory block status is idle, then memory block 3 and memory block 4 can be determined as the target memory blocks. For example, if the requested memory granularity is the maximum memory granularity of 2M and the requested memory amount is 1.5G, and the total memory amount corresponding to 2M is 5G, then because the total memory amount of 5G corresponding to the 2M granularity is greater than the requested memory amount of 1.5G, multiple target memory blocks can be determined in at least one memory block corresponding to the 2M granularity. Optionally, determining the target memory block in at least one memory block corresponding to the requested memory granularity may include the following two cases: Case 11: If the memory operation request indicates that memory be allocated according to an aligned mode. In an aligned mode, the current allocation address and memory length must be aligned when allocating memory. In this case, the electronic device may determine the current allocation address from the memory block information corresponding to the requested memory granularity and determine whether the current allocation address is aligned. If so, then the memory block status of each memory block can be traversed starting from the current allocation address. Multiple target memory blocks corresponding to the requested memory granularity can then be determined from at least one memory block corresponding to the requested memory granularity based on the memory block status. If not, then an aligned allocation address can be determined. Starting from the aligned allocation address, the memory block status of each memory block can be traversed. Multiple target memory blocks corresponding to the requested memory granularity can then be determined from at least one memory block corresponding to the requested memory granularity based on the memory block status. Optionally, the at least one target memory block can correspond to at least one memory length, and at least one memory length is aligned. If not, that is, the current allocation address is not aligned, and if there is no aligned allocation address and / or aligned memory length, then the memory operation request cannot be satisfied, and the allocation result can be determined as an allocation failure.In an optional embodiment, target memory blocks may be determined in at least one memory block corresponding to the memory application granularity in the following manner: determining a first number of target memory blocks based on the memory application amount and the memory application granularity; determining whether a first number of contiguous memory blocks exists in the at least one memory block; if so, determining the first number of contiguous memory blocks as target memory blocks; if not, when the memory operation request indicates that discontinuous memory allocation is permitted, determining the first number of discontinuous memory blocks in the at least one memory block as target memory blocks, where the sum of the memory of the discontinuous memory blocks is greater than or equal to the memory application amount. Optionally, the first number may be represented by M, which may be a positive integer. Specifically, when determining the M target memory blocks corresponding to the memory application granularity, the M target memory blocks may be predetermined to include, based on the memory application amount, K contiguous first target memory blocks corresponding to the first memory length and / or Mk second target memory blocks corresponding to the second memory length. The electronic device may determine the K contiguous first target memory blocks corresponding to the first memory length, and then determine the Mk second target memory blocks corresponding to the second memory length. The MK second target memory blocks and the K consecutive first target memory blocks may be consecutive or discontinuous. K is an integer greater than or equal to 0. For example, if the requested memory granularity is 2M, and memory block information 1 corresponding to the 2M granularity exists as shown in Table 2, if memory operation request 1 requests allocation of 1.5GB of memory with a memory granularity of 2M, and indicates that the memory is allocated according to an alignment mode and that the allocated memory is continuous, then the electronic device may predetermine, based on the memory request amount of 1.5GB, that 768 target memory blocks are required. The 768 target memory blocks include 512 consecutive first target memory blocks corresponding to a first memory length of 1GB and 256 second target memory blocks corresponding to a second memory length of 2MB. The electronic device may then determine in memory block information 1 that the current allocated address is address A and determine whether address A is aligned to 1GB. If the memory blocks are aligned, the memory block status of the n 2M memory blocks can be traversed starting from address A. If the memory blocks are not aligned, the alignment allocation address 1 can be determined. Assuming that the alignment allocation address 1 is address A1, the memory block status of the n 2M memory blocks can be traversed starting from address A1. The electronic device can preferentially determine 512 free, contiguous first target memory blocks based on the memory block status of the n 2M memory blocks, and determine the 512 first target memory blocks as the 512 target memory blocks. The memory length corresponding to the 512 target memory blocks is aligned to 1G.Next, because the memory lengths corresponding to the other 256 target memory blocks are less than 1GB, and because the memory operation request indicates that the memory allocation should be continuous, the electronic device can continue to determine 256 free, continuous second target memory blocks based on the memory block status of the n 2MB memory blocks, based on the current allocation address A2 after determining the 521 target memory blocks. The electronic device can determine a total of 768 continuous 2MB target memory blocks. If the memory operation request indicates that discontinuous memory allocation is permitted, the electronic device can also prioritize determining a total of 512 continuous first target memory blocks corresponding to the first memory length of 1GB, and then determine 256 2MB target memory blocks. When determining any of the 256 target memory blocks, the electronic device can determine whether the current allocation address is 2MB aligned. If aligned, the electronic device can traverse the memory block status of n 2M memory blocks starting from the current allocation address. If not aligned, the electronic device can determine the aligned allocation address and traverse the memory block status of n 2M memory blocks starting from the aligned allocation address to determine 256 free memory blocks, which are then identified as 256 target memory blocks. These 256 target memory blocks may be discontinuous. The memory length of each memory block is aligned to 2M. Therefore, the electronic device can determine a total of 768 target memory blocks. Of these 768 target memory blocks, 512 may be contiguous, while 256 may be discontinuous. Case 12: If the memory operation request indicates that alignment is not required. In this case, the electronic device can determine the current allocation address from the memory block information corresponding to the requested memory granularity, traverse the memory block status of each memory block starting from the current allocation address, and then determine at least one target memory block corresponding to the requested memory granularity based on the memory block status. Similarly, the target memory block can be determined in the at least one memory block corresponding to the memory application granularity in the following manner: determining a first number M of target memory blocks according to the memory application amount and the memory application granularity; judging whether there are M consecutive memory blocks in the at least one memory block; if so, determining the M consecutive memory blocks as the target memory blocks; if not, when the memory operation request indicates that discontinuous memory allocation is allowed, determining M discontinuous memory blocks in the at least one memory block as the target memory blocks, and the sum of the memory of the discontinuous memory blocks is greater than or equal to the memory application amount.For example, if the requested memory granularity is 2M, and there is memory block information 1 corresponding to the 2M granularity as shown in Table 2, if the memory operation request 1 requests allocation of 1.5G memory with a memory granularity of 2M and indicates that the memory does not need to be allocated according to the alignment mode, if the memory operation request 1 indicates that the memory allocation needs to be continuous, the electronic device can determine address A based on the memory block information 1, and traverse the memory block status of n 2M memory blocks starting from address A to determine 768 free continuous memory blocks, and determine the 768 free continuous memory blocks as 768 target memory blocks; if the memory operation request 1 indicates that discontinuous memory allocation is allowed, the electronic device can determine address A based on the memory block information 1, and traverse the memory block status of n 2M memory blocks starting from address A to determine 768 free, discontinuous memory blocks, and determine the 768 free, discontinuous memory blocks as the 768 target memory blocks. Optionally, if M consecutive memory blocks do not exist in the at least one target memory block, and if the memory operation request indicates that discontinuous memory allocation is not permitted, then the allocation may be determined to have failed. It should be noted that when determining the M discontinuous memory blocks in the at least one target memory block, the process may start from the current allocation address and traverse backward through multiple consecutive memory blocks; then, move from the current allocation address to the next suitable allocation address, and continue traversing backward through multiple consecutive memory blocks from the current allocation address; until M memory blocks are determined.

[0010] S506: When the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount, determine a target memory block from at least one memory block corresponding to the requested memory granularity. When the total amount of memory corresponding to the requested memory granularity is less than the requested memory amount, update at least one memory block and determine the target memory block from the updated memory block. Optionally, when the requested memory granularity is less than the maximum memory granularity, determining the target memory block from at least one memory block corresponding to the requested memory granularity may include the following two cases: Case 21: The total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount. In this case, the target memory block may be determined from at least one memory block corresponding to the requested memory granularity. Optionally, contiguous memory blocks may be preferentially determined from the at least one memory block corresponding to the requested memory granularity. If contiguous memory blocks are insufficient, discontiguous memory blocks may be determined as the target memory blocks. For example, if the requested memory granularity is 4K and the requested memory amount is 2.5MB, and the total memory amount corresponding to the 4K granularity is 10MB, then because the total memory amount 10MB corresponding to the 4K granularity is greater than the requested memory amount 2.5MB, multiple target memory blocks can be determined in at least one memory block corresponding to the 4K granularity. Case 22: The total memory amount corresponding to the requested memory granularity is less than the requested memory amount. In this case, at least one memory block can be updated, and the target memory block can be determined in the updated at least one memory block. In an optional embodiment, the at least one memory block can be updated in the following manner: determining a first memory block based on the requested memory granularity; dividing the first memory block to obtain multiple second memory blocks; and determining that the updated at least one memory block includes at least one memory block and multiple second memory blocks. The memory block status of the first memory block is idle. The memory granularity of the first memory block is greater than the requested memory granularity. For example, the memory granularity of the first memory block can be the memory granularity at the next higher level corresponding to the requested memory granularity. The memory granularity of the second memory block is the requested memory granularity. For example, if the requested memory granularity is 4K, and if the total memory amount corresponding to the requested memory granularity of 4K is 2M, which is less than the total memory amount of 2.5M, a first memory block can be determined based on the requested memory granularity of 4K. The memory granularity of the first memory block can be 2M, and the first memory block is in an idle state. The first memory block with a granularity of 2M can be split to obtain 512 second memory blocks with a granularity of 4K. It can be determined that the at least one updated memory block includes multiple memory blocks corresponding to the total memory amount of 2M and 512 second memory blocks with a granularity of 4K. Therefore, 640 target memory blocks can be determined from the at least one updated memory block, that is, the 1024 memory blocks.Optionally, after the first memory block is segmented, a first memory granularity corresponding to the first memory block can be determined, first memory block information corresponding to the first memory granularity can be determined, and the first memory block information can be updated based on the first memory block. Second memory block information corresponding to the requested memory granularity can be determined, and the second memory block information can be updated based on the multiple second memory blocks. For example, if the first memory block is memory block 6 with a 2M granularity, the first memory block information corresponding to the 2M granularity, i.e., memory block information 1, can be determined. Since the first memory block is segmented into multiple second memory blocks with a 4K granularity, the memory block status corresponding to the first memory block, i.e., memory block 6, can be updated to the segmented state in memory block information 1. Since multiple second memory blocks corresponding to the first memory block are newly added, memory block information 5 corresponding to the multiple second memory blocks can be newly added based on the multiple second memory blocks. The index number in memory block information 5 can be 6, and the memory block status can all be in the idle state. It should be noted that, regardless of whether the target memory block is determined in the at least one memory block corresponding to the requested memory granularity in case 21, or the target memory block is determined in the at least one updated memory block in case 22, the process of determining the target memory block corresponding to the requested memory granularity of 4K is substantially the same as the process of determining the target memory block corresponding to the 2M granularity in step 505. Specifically, if the memory operation request indicates that memory is allocated according to the aligned mode, the electronic device may determine the current allocation address in the memory block information corresponding to the requested memory granularity, and determine whether the current allocation address is aligned. If so, the electronic device may traverse the memory block status of each memory block starting from the current allocation address, and then determine multiple target memory blocks corresponding to the requested memory granularity in the at least one memory block corresponding to the requested memory granularity based on the memory block status. If not, the electronic device may determine an aligned allocation address, traverse the memory block status of each memory block starting from the aligned allocation address, and then determine multiple target memory blocks corresponding to the requested memory granularity in the at least one memory block corresponding to the requested memory granularity based on the memory block status. If not, that is, the current allocation address is not aligned, and if there is no aligned allocation address and / or aligned memory length, the memory operation request may not be satisfied, and the allocation result may be determined to be an allocation failure.In an optional embodiment, a target memory block can be determined in at least one memory block corresponding to the memory application granularity in the following manner: determining a first number M of target memory blocks based on the memory application amount and the memory application granularity; determining whether M contiguous memory blocks exist in the at least one memory block; if so, determining the M contiguous memory blocks as target memory blocks; if not, when the memory operation request indicates that discontinuous memory allocation is permitted, determining M discontinuous memory blocks in the at least one memory block as target memory blocks, where the sum of the memory sizes of the discontinuous memory blocks is greater than or equal to the memory application amount. Specifically, when determining the M target memory blocks corresponding to the memory application granularity, the M target memory blocks can be predetermined to include K contiguous first target memory blocks corresponding to the first memory length and / or Mk second target memory blocks corresponding to the second memory length based on the memory application amount. The electronic device can determine the K contiguous first target memory blocks corresponding to the first memory length, and then determine Mk second target memory blocks corresponding to the second memory length. The Mk second target memory blocks can be contiguous or discontinuous with the K contiguous first target memory blocks. For example, if the requested memory granularity is 4KB, and memory block information 2, memory block information 3, and memory block information 5 corresponding to the 4KB granularity exist, and if memory operation request 2 requests allocation of 2.5MB of memory with a 4KB memory granularity, and indicates that the memory is allocated according to an aligned mode and that discontinuous memory allocation is permitted, the electronic device may predetermine, based on the requested memory size of 2.5MB, that 640 target memory blocks are required. These 640 target memory blocks include 512 target memory blocks corresponding to the first memory length of 2MB and 128 target memory blocks corresponding to the second memory length of 4MB. The electronic device may then determine in memory block information 2 that the current allocation address is address C, and determine whether address C is aligned with 2MB. If so, the electronic device may traverse multiple memory block states in memory block information 2 starting from address C. If not, the electronic device may determine an aligned allocation address C1, and traverse multiple memory block states in memory block information 2 starting from address C1. The electronic device may prioritize 512 free, contiguous first target memory blocks based on the states of multiple memory blocks in memory block information 2, and determine the 512 first target memory blocks as the 512 target memory blocks. The memory lengths corresponding to the 512 target memory blocks are aligned to 2MB. If the 512 first target memory blocks do not exist in memory block information 2, the 512 target memory blocks may be prioritized in the same manner based on memory block information 3 or memory block information 5.Assuming that the electronic device can determine 512 target memory blocks based on memory block information 5, then, since the memory lengths corresponding to the other 128 target memory blocks are less than 2MB, the electronic device can determine 128 4KB target memory blocks based on memory block information 2 and / or memory block information 3. When determining any of these 128 target memory blocks, the electronic device can determine whether the current allocation address is 4KB aligned. If so, the electronic device can traverse the memory block status in memory block information 2 starting from the current allocation address. If not, the electronic device can determine the aligned allocation address and traverse the memory block status in memory block information 2 starting from the aligned allocation address to determine multiple free memory blocks, which are then identified as multiple target memory blocks. Assuming that the electronic device can determine 60 target memory blocks based on memory block information 2, the electronic device can similarly determine the remaining 68 target memory blocks based on memory block information 3 in the same manner. The memory length of each memory block is 4KB aligned. Therefore, the electronic device can determine a total of 512 + 128 = 640 target memory blocks. If the memory operation request indicates that alignment is not required, the electronic device may determine the current allocation address from the memory block information corresponding to the requested memory granularity. Starting from the current allocation address, the electronic device may traverse the memory block status of each memory block, and then determine at least one target memory block corresponding to the requested memory granularity based on the memory block status. For example, if the requested memory granularity is 4KB, and memory block information 2, memory block information 3, and memory block information 5 corresponding to 4KB granularity exist, if memory operation request 2 requests allocation of 2.5MB of memory at a 4KB memory granularity and indicates that alignment is not required for memory allocation, and if memory operation request 2 indicates that discontinuous memory allocation is permitted, the electronic device may determine a total of 640 free, discontinuous memory blocks based on memory block information 2, memory block information 3, and memory block information 5, and determine these 640 free, discontinuous memory blocks as the 640 target memory blocks. S507: Allocate target memory blocks corresponding to the requested memory granularity. For example, if memory operation request 1 requests allocation of 1.5 GB of memory with a memory granularity of 2 MB, and if the electronic device can determine 768 consecutive 2 MB target memory blocks, then the electronic device can allocate the 768 consecutive 2 MB target memory blocks; if the electronic device determines 768 discontinuous 2 MB target memory blocks, including 512 consecutive 2 MB target memory blocks and 256 consecutive 2 MB target memory blocks, then the 512 consecutive 2 MB target memory blocks can be allocated first, and then the 256 consecutive 2 MB target memory blocks can be allocated.For example, if memory operation request 2 requests allocation of 2.5MB of memory with a memory granularity of 4KB, and if the electronic device has determined 640 non-contiguous 4KB target memory blocks, including 512 contiguous 4KB target memory blocks and 128 non-contiguous 4KB target memory blocks, the electronic device may first allocate the 512 contiguous 4KB target memory blocks, and then allocate the 128 non-contiguous 4KB target memory blocks. It should be noted that if the memory operation request indicates that memory should be allocated according to an alignment mode, the returned allocation end address may be checked for each allocation to determine whether the allocation end address meets the alignment requirement. If the alignment requirement is met, the target memory block is allocated.

[0011] S508. Update the memory block information corresponding to each requested memory granularity based on the target memory block. Optionally, for each requested memory granularity, since the electronic device allocates multiple target memory blocks based on the memory block information corresponding to the requested memory granularity, the memory block information corresponding to the requested memory granularity can be updated based on the target memory block. Specifically, the memory block status, memory usage information, and current allocation address in the memory block information can be updated. For example, if the requested memory granularity is 2MB, and the electronic device allocates 768 memory blocks of 2MB granularity based on memory block information 1, then based on these 768 memory blocks, the corresponding memory block status in memory block information 1 can be updated to a used state, and the memory usage information and current allocation address can be updated to address B. For example, if the requested memory granularity is 4 KB, and if the electronic device allocates 60 target memory blocks of 4 KB granularity according to memory block information 2, then the corresponding memory block status of the 60 target memory blocks in memory block information 2 may be updated to a used status, and the memory usage information and the currently allocated address may be updated to address D. Similarly, if the electronic device allocates 68 target memory blocks of 4 KB granularity according to memory block information 3, then the memory block status corresponding to the 68 target memory blocks may be updated to a used status, and the memory usage information and the currently allocated address may be updated to address F in memory block information 3. If 512 target memory blocks of 4 KB granularity are allocated according to memory block information 5, then the memory block status corresponding to the 512 target memory blocks may be updated to a used status, and the memory usage information and the currently allocated address may be updated to address H in memory block information 5. Optionally, after allocating the target memory block with a 4KB granularity, a determination can be made as to whether the memory block status in any memory block information corresponding to the 4KB granularity indicates an idle state. If not, the memory block information can be moved to the second linked list. If newly added memory block information exists and the memory block information indicates an idle state, the memory block information can be added to the first linked list. The following describes the movement of memory block information with reference to FIG6 . FIG6 is a second schematic diagram of the first and second linked lists provided in an exemplary embodiment of the present disclosure.Referring to FIG6 , after the electronic device allocates a total of 640 4KB target memory blocks based on memory block information 2, memory block information 3, and memory block information 5, if the first linked list and the second linked list are as shown in FIG4 , it can be determined whether any free state exists in memory block information 2. If not, memory block information 2 can be moved to the second linked list, and the address of the next memory block information in memory block information 4 can be updated to address 1. If any free state exists in memory block information 3, there is no need to move memory block information 3 to the second linked list; memory block information 3 remains in the first linked list. Since memory block information 2 has been moved to the second linked list, the first linked list address in memory block information 1 can be updated to address 3. If no free state exists in memory block information 5, memory block information 5 can be added to the second linked list, and the address of the next memory block information in memory block information 2 can be updated to address 5, resulting in a new first linked list and a new second linked list, as shown in FIG6 . It should be noted that if the memory operation request includes a specified memory node, steps S502 to S508 may be performed in the specified memory node. If the memory operation request does not include a specified memory node, and if the electronic device includes multiple memory nodes, it may be determined whether the remaining capacity of the first memory node is greater than or equal to the total memory request (the sum of the memory request capacities corresponding to the requested memory granularities). If not, a memory node that is closer to the first memory node and has a remaining capacity greater than or equal to the total memory request may be preferentially selected based on the distance between different memory nodes, and steps S502 to S508 may be performed in this memory node. In an embodiment of the present disclosure, an electronic device may obtain a memory operation request for a memory and determine memory block information corresponding to at least one memory granularity. The electronic device may determine the memory block information corresponding to the requested memory granularity and determine whether the requested memory granularity is the maximum memory granularity. If so, when the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount, a target memory block can be determined from at least one memory block corresponding to the requested memory granularity. If not, when the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount, a target memory block can be determined from at least one memory block corresponding to the requested memory granularity. When the total amount of memory corresponding to the requested memory granularity is less than the requested memory amount, at least one memory block is updated, and the target memory block is determined from the updated memory block. The electronic device can allocate a target memory block corresponding to the requested memory granularity and, based on the target memory block, update the memory block information corresponding to each requested memory granularity. Since the memory may include multiple memory blocks corresponding to at least two memory granularities, and each memory granularity has corresponding memory block information.When allocating memory, operations can be performed on multiple memory blocks corresponding to any memory granularity in the memory based on memory block information as needed. This improves the flexibility of memory operations compared to the prior art, where the memory only includes multiple memory blocks corresponding to one memory granularity and the memory is operated based on this single memory granularity. FIG7 is a flow chart illustrating another memory operation method provided in an exemplary embodiment of the present disclosure. Referring to FIG7 , the method may include:

[0012] S701: Obtain a memory operation request for memory. The memory operation request is used to request the release of memory. The memory operation request may include the memory granularity to be released and the memory address corresponding to the memory granularity. For example, the memory granularity to be released may be any of the following: 1G granularity, 2M granularity, 16K granularity, 4K granularity, etc. Optionally, the memory address may include at least one set of a release start address and a release end address. The electronic device may obtain a memory operation request in response to a user operation on the memory. For example, the electronic device may obtain memory operation request 3 requesting the release of a 2M granularity memory block with memory addresses A to B, and memory operation request 4 requesting the release of a 4K granularity memory block with memory addresses C to D, E to F, and G to H.

[0013] S702: Determine memory block information corresponding to at least one memory granularity. It should be noted that the execution process of step S702 may refer to step S202 and will not be repeated here.

[0014] S703: Determine at least one memory block to be released corresponding to the released memory granularity based on the memory block information and memory address corresponding to the released memory granularity. For the released memory granularity, the electronic device may determine the memory block information corresponding to the released memory granularity and, based on the memory block information and memory address, determine at least one memory block to be released corresponding to the released memory granularity. For example, if the released memory granularity is 2MB, if there is memory block information 1 corresponding to the 2MB granularity, and if the memory address is from address A to address B, the electronic device may determine memory block information 1 and, based on memory block information 1 and addresses A to address B, determine at least one memory block to be released. Assume that 768 memory blocks to be released with a 2MB granularity can be determined. For example, if the memory release granularity is 4KB, if memory block information 2, memory block information 3, memory block information 4, and memory block information 5 corresponding to the 4KB granularity exist, and if the memory addresses are from address C to address D, from address E to address F, and from address G to address H, then the electronic device can determine at least one memory block to be released based on the four pieces of memory block information and the three memory addresses. Assume that 60 memory blocks to be released with a 4KB granularity can be determined in memory block information 2 based on addresses C to address D; 68 memory blocks to be released with a 4KB granularity can be determined in memory block information 3 based on addresses E to address F; and 512 memory blocks to be released with a 4KB granularity can be determined in memory block information 5 based on addresses G to address H. For a total of 640 memory blocks to be released with a 4KB granularity,

[0015] S704. Clear at least one memory block to be released to release the at least one memory block. For example, if the electronic device determines 768 memory blocks to be released with a granularity of 2M, then clear the 768 memory blocks to be released with a granularity of 2M to release to release the 768 memory blocks with a granularity of 2M. For example, if the electronic device determines 640 memory blocks to be released with a granularity of 4K to release, then clear the 640 memory blocks to be released with a granularity of 4K to release to release the 640 memory blocks with a granularity of 4K.

[0016] S705. Update memory block information corresponding to the released memory granularity based on the at least one memory block. Optionally, for any released memory granularity, after at least one memory block is released, because the memory block status of the at least one memory block changes, the memory block information corresponding to the released memory granularity may be updated based on the at least one memory block. Specifically, the memory block status, memory usage information, and current allocation address in the memory block information may be updated. For example, if the released memory granularity is 2MB, and the electronic device releases 768 memory blocks of 2MB granularity based on memory block information 1 and addresses A to B, then based on these 768 memory blocks, the corresponding memory block status in memory block information 1 may be updated to an idle state, and the memory usage information and current allocation address may be updated to address A. For example, if the released memory granularity is 4 KB, and if the electronic device releases 60 memory blocks of 4 KB granularity according to memory block information 2 and address C to address D, then the corresponding memory block status in memory block information 2 may be updated to an idle state based on the 60 memory blocks, and the memory usage information and the currently allocated address may be updated to address C. Similarly, if the electronic device releases 68 memory blocks of 4 KB granularity to be released according to memory block information 3 and address E to address F, then the corresponding memory block status in memory block information 3 may be updated to an idle state, and the memory usage information and the currently allocated address may be updated to address E. If 512 memory blocks of 4 KB granularity to be released according to memory block information 5 and address G to address H are released, then the corresponding memory block status in memory block information 5 may be updated to an idle state, and the memory usage information and the currently allocated address may be updated to address G.

[0017] S706. If the released memory granularity is smaller than the maximum memory granularity, and if the memory block states in the third memory block information corresponding to the released memory granularity are all in the idle state, then multiple memory blocks are merged according to the third memory block information to obtain a third memory block. The memory granularity of the third memory block is the maximum memory granularity. For example, if the released memory granularity is 4 KB, which is smaller than the maximum memory granularity of 2 MB, and if the electronic device releases 512 memory blocks of 4 KB granularity according to memory block information 5 and addresses G to H, and if the memory block states in memory block information 5 are all in the idle state after the memory blocks are released, then memory block information 5 is the third memory block information. Then, based on memory block information 5, the multiple 4 KB memory blocks corresponding to memory block information 5 can be merged to obtain the third memory block. Assume that the third memory block is a memory block of 2 MB granularity.

[0018] S707: Update the memory block information corresponding to the maximum memory granularity based on the third memory block, and delete the third memory block information. Since the memory block status of the third memory block has changed and the memory granularity of the third memory block is the maximum memory granularity, the memory block information corresponding to the maximum memory granularity can be updated based on the third memory block. Optionally, since the multiple memory blocks corresponding to the released memory granularity no longer exist after merging, the memory block information corresponding to the multiple memory blocks can be deleted. For example, if the third memory block is memory block 6 with a 2M granularity, memory block information 1 corresponding to the 2M granularity can be updated based on the third memory block. In memory block information 1, the memory block status corresponding to the third memory block, i.e., memory block 6, is updated to an idle state, and the memory usage information in memory block information 1 is updated. Since the multiple 4K memory blocks used to merge the third memory block no longer exist, memory block information 5 can be deleted. Optionally, if the released memory granularity is smaller than the maximum memory granularity, and before releasing a memory block, any memory block information corresponding to the released memory granularity is in the second linked list, then after releasing the memory block, if the memory block information contains an idle state, the memory block information can be moved to the first linked list. For example, for a released memory granularity of 4KB, if memory block information 2 and memory block information 5 are in the second linked list, as shown in FIG6 , after releasing 60 4KB memory blocks according to memory block information 2, 60 idle states are found in the memory block status of memory block information 2. Therefore, memory block information 2 can be moved to the first linked list. If the first and second linked lists are as shown in FIG6 , after deleting memory block information 5 and moving memory block information 2 to the first linked list, the first and second linked lists shown in FIG4 can be obtained. In embodiments of the present disclosure, an electronic device can obtain a memory operation request for a memory and determine the memory block information corresponding to at least one memory granularity. The electronic device may determine at least one to-be-released memory block corresponding to the released memory granularity based on the memory block information and memory address corresponding to the released memory granularity, and clear the at least one to-be-released memory block to release the at least one memory block. The electronic device may update the memory block information corresponding to the released memory granularity based on the at least one memory block. If the released memory granularity is smaller than the maximum memory granularity, and if the memory block states in the third memory block information corresponding to the released memory granularity are all idle, the electronic device may merge the multiple memory blocks based on the third memory block information to obtain a third memory block, update the memory block information corresponding to the maximum memory granularity based on the third memory block, and delete the third memory block information. Since the memory may include multiple memory blocks corresponding to at least two memory granularities, and each memory granularity has corresponding memory block information.When releasing memory, operations can be performed on multiple memory blocks corresponding to any memory granularity in the memory based on memory block information, as needed. This improves the flexibility of memory operations compared to the prior art, where the memory only includes multiple memory blocks corresponding to one memory granularity and operations are performed based on this memory granularity. FIG8 is a schematic structural diagram of a memory operation device according to an embodiment of the present disclosure. Referring to FIG8 , the memory operation device 10 may include an acquisition module 11, a determination module 12, and a processing module 13. The acquisition module 11 is configured to acquire a memory operation request for a memory, wherein the memory operation request is for requesting memory allocation or memory release, and the memory includes multiple memory blocks corresponding to at least one memory granularity. The determination module 12 is configured to determine memory block information corresponding to at least one memory granularity, wherein the memory block information includes a memory granularity value, memory block status, and memory block usage information. The processing module 13 is configured to process the memory operation request based on the memory block information corresponding to at least one memory granularity to allocate or release memory. The memory operation device provided in the embodiments of the present disclosure can implement the technical solutions shown in the above-described method embodiments. Its implementation principles and beneficial effects are similar and will not be further described here. In one possible implementation, the memory operation request is used to request memory allocation, and the memory operation request includes a requested memory granularity and a memory request amount corresponding to the requested memory granularity. The processing module 13 is specifically configured to: determine memory block information corresponding to the requested memory granularity; determine a target memory block corresponding to the requested memory granularity based on the memory block information and the memory request amount corresponding to the requested memory granularity, wherein the memory granularity of the target memory block is the requested memory granularity and the memory block state of the target memory block is an idle state; and allocate the target memory block corresponding to the requested memory granularity. In one possible implementation, the applied memory granularity is smaller than the maximum memory granularity; the processing module 13 is specifically used to: determine the previous level memory granularity corresponding to the applied memory granularity, and the memory block corresponding to the previous level memory granularity is divided into multiple memory blocks corresponding to the applied memory granularity; determine a first linked list address in the memory block information corresponding to the previous level memory granularity; determine the memory block information corresponding to the applied memory granularity according to the first linked list address.In one possible embodiment, the processing module 13 is specifically configured to: determine whether the requested memory granularity is the maximum memory granularity; if so, determine the target memory block in at least one memory block corresponding to the requested memory granularity when the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount; if not, determine the target memory block in at least one memory block corresponding to the requested memory granularity when the total amount of memory corresponding to the requested memory granularity is greater than or equal to the requested memory amount; and if the total amount of memory corresponding to the requested memory granularity is less than the requested memory amount, update the at least one memory block and determine the target memory block in the updated at least one memory block. In one possible embodiment, the processing module 13 is specifically configured to: determine a first memory block based on the requested memory granularity, wherein the memory granularity of the first memory block is greater than the requested memory granularity and the memory block status of the first memory block is idle; split the first memory block to obtain multiple second memory blocks, wherein the memory granularity of the second memory block is the requested memory granularity; and determine that the updated at least one memory block includes the at least one memory block and the multiple second memory blocks. The memory operation device provided in the embodiments of the present disclosure can implement the technical solutions shown in the above-mentioned method embodiments. Its implementation principles and beneficial effects are similar and will not be further described here. FIG. 9 is a schematic structural diagram of another memory operation device provided in the embodiments of the present disclosure. Referring to FIG. 9 , based on the embodiment shown in FIG. 8 , the memory operation device 10 may further include: an update module 14 configured to determine a first memory granularity corresponding to the first memory block, determine first memory block information corresponding to the first memory granularity, and update the first memory block information based on the first memory block; and an update module 14 configured to determine second memory block information corresponding to the requested memory granularity and update the second memory block information based on the multiple second memory blocks. The memory operation device provided in the embodiments of the present disclosure can implement the technical solutions shown in the above-mentioned method embodiments. Its implementation principles and beneficial effects are similar and will not be further described here.In one possible embodiment, the processing module 13 is specifically configured to: determine a first number of target memory blocks based on the memory request amount and the memory request granularity; determine whether a first number of contiguous memory blocks exist in the at least one memory block; if so, determine the first number of contiguous memory blocks as the target memory blocks; if not, when the memory operation request indicates that discontinuous memory allocation is permitted, determine the first number of discontinuous memory blocks in the at least one memory block as the target memory blocks, and the sum of the memory of the discontinuous memory blocks is greater than or equal to the memory request amount. In one possible embodiment, the update module 14 is further configured to: update the memory block information corresponding to the memory request granularity based on the target memory block. In one possible embodiment, the memory operation request is used to request memory release; the memory operation request includes a memory granularity to be released and a memory address corresponding to the memory granularity to be released; the processing module 13 is specifically configured to: determine at least one memory block to be released corresponding to the memory granularity to be released based on the memory block information corresponding to the memory granularity to be released and the memory address; and clear the at least one memory block to be released to release the at least one memory block. In one possible embodiment, the updating module 14 is further configured to: update the memory block information corresponding to the memory granularity to be released based on the at least one memory block. In one possible embodiment, the processing module 13 is further configured to: if the memory granularity to be released is smaller than the maximum memory granularity and if the memory block status in the third memory block information corresponding to the memory granularity is all idle, merge multiple memory blocks based on the third memory block information to obtain a third memory block, where the memory granularity of the third memory block is the maximum memory granularity; and the updating module 14 is further configured to update the memory block information corresponding to the maximum memory granularity based on the third memory block and delete the third memory block information. The memory operation device provided in the embodiments of the present disclosure can implement the technical solutions shown in the above-described method embodiments. Its implementation principles and beneficial effects are similar and will not be further described here. The exemplary embodiments of the present disclosure provide a schematic structural diagram of an electronic device. See FIG10 . The electronic device 20 may include a processor 21 and a memory 22. Exemplarily, the processor 21 and the memory 22 are interconnected via a bus 23. The memory 22 stores computer-executable instructions; the processor 21 executes the computer-executable instructions stored in the memory 22, causing the processor 21 to perform the method shown in the above-described method embodiments.Accordingly, embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions. When executed by a processor, the computer-executable instructions are used to implement the methods described in the above method embodiments. Accordingly, embodiments of the present disclosure may also provide a computer program product, including a computer program. When executed by a processor, the computer program can implement the methods described in the above method embodiments. Those skilled in the art will appreciate that embodiments of the present disclosure may be provided as methods, systems, or computer program products. Therefore, the present disclosure may take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, the present disclosure may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code. The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to embodiments of the present disclosure. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes of the flowchart and / or one or more blocks of the block diagram. These computer program instructions can also be stored in a computer-readable memory that can guide the computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the functions specified in one or more processes of the flowchart and / or one or more blocks of the block diagram. These computer program instructions can also be loaded onto a computer or other programmable data processing device, so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, so that the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes of the flowchart and / or one or more blocks of the block diagram. In a typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.Memory may include non-permanent storage in computer-readable media, random access memory (RAM), and / or non-volatile memory such as read-only memory (ROM) or flash RAM. Memory is an example of computer-readable media. Computer-readable media, including both permanent and non-permanent, removable and non-removable media, can be implemented using any method or technology for information storage. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change RAM (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassettes, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information accessible by a computing device. As defined herein, computer-readable media does not include transitory computer-readable media, such as modulated data signals and carrier waves. It should also be noted that the terms "comprise," "include," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, product, or apparatus comprising a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, product, or apparatus. Without further limitation, the phrase "comprises a..." does not preclude the presence of additional identical elements in the process, method, product, or apparatus comprising the recited elements. The foregoing description is merely an example of the present disclosure and is not intended to limit the present disclosure. Various modifications and variations of the present disclosure will be apparent to those skilled in the art. Any modifications, equivalent substitutions, improvements, and the like made within the spirit and principles of the present disclosure are intended to be encompassed by the claims of the present disclosure.

Claims

1. A memory operation method, wherein: include: Obtaining a memory operation request for a memory, where the memory operation request is used to request memory allocation or memory release, where the memory includes multiple memory blocks, and the multiple memory blocks correspond to at least two memory granularities; Determine memory block information corresponding to at least one memory granularity, where the memory block information includes a memory granularity value, a memory block state, and memory block usage information; The memory operation request is processed according to memory block information corresponding to at least one memory granularity to allocate memory or release memory.

2. The method according to claim 1, wherein: The memory operation request is used to request memory allocation, and the memory operation request includes a memory application granularity and a memory application amount corresponding to the memory application granularity; Processing the memory operation request according to memory block information corresponding to at least one memory granularity to perform memory allocation includes: determining memory block information corresponding to the requested memory granularity; Determine, based on memory block information and memory request amount corresponding to the requested memory granularity, a target memory block corresponding to the requested memory granularity, wherein the memory granularity of the target memory block is the requested memory granularity and the memory block state of the target memory block is an idle state; and allocate the target memory block corresponding to the requested memory granularity.

3. The method according to claim 2, wherein: The memory granularity requested is smaller than the maximum memory granularity; Determining the memory block information corresponding to the applied memory granularity includes: determining the upper-level memory granularity corresponding to the applied memory granularity, the memory block corresponding to the upper-level memory granularity being divided into multiple memory blocks corresponding to the applied memory granularity; determining a first linked list address in the memory block information corresponding to the upper-level memory granularity; and determining the memory block information corresponding to the applied memory granularity based on the first linked list address.

4. The method according to claim 2 or 3, wherein: Determining the target memory block according to the memory block information corresponding to the applied memory granularity and the memory application amount includes: judging whether the applied memory granularity is the maximum memory granularity; if so, determining the target memory block in at least one memory block corresponding to the applied memory granularity when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount; if not, determining the target memory block in at least one memory block corresponding to the applied memory granularity when the total amount of memory corresponding to the applied memory granularity is greater than or equal to the memory application amount; updating the at least one memory block when the total amount of memory corresponding to the applied memory granularity is less than the memory application amount, and determining the target memory block in the at least one updated memory block.

5. The method according to claim 4, wherein: Updating the at least one memory block includes: determining a first memory block according to the applied memory granularity, wherein the memory granularity of the first memory block is greater than the applied memory granularity, and the memory block state of the first memory block is an idle state; dividing the first memory block into a plurality of second memory blocks, wherein the memory granularity of the second memory block is 25 The memory granularity is applied for; and the at least one updated memory block is determined to include the at least one memory block and the plurality of second memory blocks.

6. The method according to claim 5, wherein: The method also includes: determining a first memory granularity corresponding to the first memory block, determining first memory block information corresponding to the first memory granularity, and updating the first memory block information based on the first memory block; determining second memory block information corresponding to the applied memory granularity, and updating the second memory block information based on the multiple second memory blocks.

7. The method according to any one of claims 4 to 6, wherein: Determining the target memory block in at least one memory block corresponding to the applied memory granularity includes: determining a first number of the target memory blocks according to the memory application amount and the applied memory granularity; judging whether there are a first number of continuous memory blocks in the at least one memory block; if so, determining the first number of continuous memory blocks as the target memory block; if not, when the memory operation request indicates that discontinuous memory allocation is allowed, determining a first number of discontinuous memory blocks in the at least one memory block as the target memory block, and the sum of the memory of the discontinuous memory blocks is greater than or equal to the memory application amount.

8. The method according to any one of claims 2 to 7, wherein: The method further includes: updating memory block information corresponding to the requested memory granularity according to the target memory block.

9. The method according to any one of claims 1 to 8, wherein: The memory operation request is used to request memory release; the memory operation request includes a memory release granularity and a memory address corresponding to the memory release granularity; Processing the memory operation request according to memory block information corresponding to at least one memory granularity to release memory includes: determining at least one to-be-released memory block corresponding to the released memory granularity according to the memory block information corresponding to the released memory granularity and the memory address; Clearing the at least one memory block to be released to release the at least one memory block.

10. The method according to claim 9, wherein: The method further includes: updating memory block information corresponding to the released memory granularity according to the at least one memory block.

11. The method according to claim 9 or 10, wherein: The method also includes: if the released memory granularity is smaller than the maximum memory granularity, and if the memory block states in the third memory block information corresponding to the released memory granularity are all in idle state, merging multiple memory blocks according to the third memory block information to obtain a third memory block, and the memory granularity of the third memory block is the maximum memory granularity; updating the memory block information corresponding to the maximum memory granularity according to the third memory block, and deleting the third memory block information.

12. A memory operation device, wherein: include: An acquisition module, a determination module, and a processing module, wherein the acquisition module is used to acquire a memory operation request for a memory, wherein the memory operation request is used to request allocation of memory or request release of memory, wherein the memory includes multiple memory blocks, and the multiple memory blocks correspond to at least one memory granule. the determining module is used to determine memory block information corresponding to at least one memory granularity, where the memory block information includes memory granularity, memory block status, and memory block usage information; the processing module is used to process the memory operation request according to the memory block information corresponding to at least one memory granularity to allocate memory or release memory.

13. An electronic device, wherein: include: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the electronic device to perform the method according to any one of claims 1 to 11.

14. A computer-readable storage medium, wherein: The computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the method according to any one of claims 1 to 11 is implemented.

15. A computer program product, comprising a computer program, wherein: When the computer program is executed by a processor, the method according to any one of claims 1 to 11 is implemented.

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