Display device

Abstract

[Problem] To make it possible to change a display mode according to the location of a pixel array unit. [Solution] This display device comprises: a pixel array unit that has a plurality of pixels arranged in a first direction and a second direction crossing each other; and a plurality of drive circuits that drive, by two or more drive modes, a plurality of pixel regions disposed in the pixel array unit and each including two or more pixels.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] Recent display devices, such as wearable display devices (head-mounted displays) used for augmented reality (AR) or virtual reality (VR) applications and display devices used as electronic viewfinders for digital cameras and the like, are required to have higher resolution and a larger number of pixels because they allow users to view a close-up display device in a magnified manner. Meanwhile, wearable display devices and electronic viewfinders are also required to have high-speed display (high frame rate) so as to more naturally follow the movement of a displayed object or electronic device. Furthermore, low power consumption is also required for battery operation.

[0003] In view of this, a technique has been proposed in which a display unit is divided into a plurality of pixel regions, and each pixel region is driven by a separate driver (see Patent Document 1).

[0004] Japanese Patent Application Laid-Open No. 2020-187186

[0005] In Patent Document 1, multiple driving units are associated with multiple pixel regions, so the number of pixels driven by one driving unit can be reduced, allowing for high-resolution pixel display without reducing the frame rate.

[0006] However, in Patent Document 1, all pixel regions are the same size, and when a focus region exists in a part of the pixel array, it is not easy to display the focus region in a way that highlights it. For example, in a head-mounted display, since attention is focused on the center in many usage scenarios, it is desirable to display a higher resolution and frame rate in the focus region, while the peripheral areas rarely require the same resolution or frame rate as the focus region. However, in Patent Document 1, the display format (e.g., pixel region size) cannot be changed between the focus region and other areas, so it is not possible to freely change the drive of areas other than the focus region.

[0007] Therefore, the present disclosure provides a display device capable of changing the display mode depending on the location of the pixel array section.

[0008] In order to solve the above problems, one embodiment of the present disclosure provides a display device comprising: a pixel array section having a plurality of pixels arranged in a first direction and a second direction that intersect with each other; and a plurality of drive circuits arranged in the pixel array section and driving a plurality of pixel regions each including two or more pixels using two or more drive methods.

[0009] The plurality of pixel regions may include two or more pixel regions that are different in at least one of display mode, arrangement, shape, and size.

[0010] The plurality of pixel regions may have one or more first pixel regions each having two or more of the pixels arranged along a third direction and a fourth direction that intersect with each other, the third direction being the same as or different from the first direction, the fourth direction being the same as or different from the second direction, and the drive circuit that drives the first pixel region may drive the two or more pixels in the first pixel region along the third direction and the fourth direction.

[0011] The plurality of pixel regions may include a second pixel region having two or more of the pixels arranged along the first direction and the second direction, and the drive circuit that drives the second pixel region may drive the two or more pixels in the second pixel region along the first direction and the second direction.

[0012] The first pixel region may be disposed in the central portion of the pixel array portion, and the second pixel region may be disposed around the first pixel region.

[0013] A plurality of the first pixel regions may be arranged near a center of the pixel array unit, and the plurality of first pixel regions may differ from each other in at least one of shape, size, and orientation.

[0014] The third direction in each of the plurality of first pixel regions may be different, the fourth direction in each of the plurality of first pixel regions may be different, and the plurality of drive circuits that drive the plurality of first pixel regions may change at least one of the drive order or drive direction of the two or more pixels included in the plurality of first pixel regions for each of the first pixel regions.

[0015] Three of the plurality of first pixel regions may be arranged at an angle of 60 degrees each, one of the plurality of first pixel regions different from the three first pixel regions may be arranged in a location surrounded by the three first pixel regions, and each of the plurality of drive circuits that drive the plurality of first pixel regions may drive the two or more pixels included in the corresponding first pixel region along the longitudinal direction and the lateral direction of the corresponding first pixel region.

[0016] The display device may further include a pixel correction section that corrects the display form of the second pixel region to a display form different from that of the first pixel region.

[0017] The pixel correction section may make the first pixel region and the second pixel region different in at least one of resolution, luminance, chromaticity, and display update cycle.

[0018] The pixel correction section may reduce the luminance of the second pixel region to be lower than that of the first pixel region.

[0019] When a pixel having a higher brightness than surrounding pixels is present in the second pixel region, the pixel correction unit may reduce the brightness of the surrounding pixels without reducing the brightness of the pixel having the higher brightness.

[0020] The pixel correction section may perform a binning process in the second pixel region, which writes the same pixel signal to a pixel group including two or more adjacent pixels.

[0021] The pixel correction unit may adjust the luminance of the two or more pixels included in the pixel group so that a luminance difference between a maximum luminance and an average luminance of the two or more pixels included in the pixel group is equal to or greater than a predetermined threshold value.

[0022] The pixel correction unit may adjust the chromaticity of the two or more pixels included in the pixel group so that the maximum value of the difference between the average chromaticity of the two or more pixels and the chromaticity of each pixel is equal to or greater than a predetermined threshold value.

[0023] The drive circuit that drives the first pixel region may alternately perform a first display drive in which the first pixel region is divided into a plurality of pixel groups, each including two or more of the pixels, and a pixel signal is supplied to each of the pixel groups, and a second display drive in which the first pixel region is divided into a new plurality of pixel groups, each shifted by one pixel in the third direction and the fourth direction, and a pixel signal different from that of the first display drive is supplied to each of the pixel groups; and the drive circuit that drives the second pixel region may divide the second pixel region into a plurality of pixel groups and supply a pixel signal to each of the pixel groups, without distinguishing between the first display drive and the second display drive.

[0024] the drive circuit that drives the first pixel region sequentially repeats the following: a first display drive in which the first pixel region is divided into a plurality of pixel groups each including two or more of the pixels and a pixel signal is supplied to each of the pixel groups; a second display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the third direction with respect to the first display drive and a pixel signal different from that of the first display drive is supplied to each of the pixel groups; a third display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the fourth direction with respect to the first display drive and a pixel signal different from that of the second display drive is supplied to each of the pixel groups; and a fourth display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel each in the third direction and the fourth direction with respect to the first display drive and a pixel signal different from that of the third display drive is supplied to each of the pixel groups, The drive circuit that drives the second pixel region may divide the second pixel region into a plurality of pixel groups and supply pixel signals to each pixel group, regardless of the first to fourth display drives.

[0025] The pixel array may include a first substrate on which the pixel array section is arranged, and a second substrate stacked on the first substrate and having the plurality of drive circuits, wherein each of the plurality of drive circuits may be arranged so as to overlap at least a portion with the corresponding pixel region when the first substrate and the second substrate are viewed in a plane.

[0026] The display device may further include an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of pixel selection circuits provided corresponding to the plurality of drive circuits, and each of the plurality of pixel selection circuits may supply a drive signal output from a corresponding drive circuit to one or more pixels selected from the corresponding pixel region.

[0027] The display device may further include an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of area selection circuits provided corresponding to the plurality of drive circuits, and each of the plurality of area selection circuits may perform at least one of selecting one or more of the plurality of pixel areas and making minor adjustments to the shape or size of the selected pixel area based on a drive signal output from the corresponding drive circuit.

[0028] 16 is a block diagram showing a schematic configuration of a display system including a display device and a host device according to a first embodiment. FIG. 17 is a diagram showing a stacked structure of the display device according to the first embodiment. FIG. 18 is a diagram showing a stacked structure of the display device according to the second embodiment. FIG. 19 is a diagram showing details of a first pixel region in the second embodiment. FIG. 20 is a diagram showing a stacked structure of the display device according to the third embodiment. FIG. 21 is a diagram showing an example of a specific configuration of a plurality of pixel selection circuits 24. FIG. 22 is a diagram showing a stacked structure of the display device according to the fourth embodiment. FIG. 23 is a diagram explaining the operation of the region selection circuit 25. FIG. 24 is a diagram showing an example of a specific configuration of a plurality of region selection circuits 25. A flowchart showing a processing operation according to a first example of a pixel correction unit. A flowchart showing a processing operation according to a second example of a pixel correction unit. A plan view showing the outer shapes of a first pixel region and a second pixel region displayed on a display unit by a display device according to a sixth embodiment. A diagram showing an example of an optical system of a microdisplay. FIG. 24 is a diagram showing a stacked structure of the display device according to the seventh embodiment. A cross-sectional view of a display device according to an eighth embodiment. A flowchart showing a processing operation of a display device according to a ninth embodiment. A diagram explaining the processing of steps S21 and S22 of FIG. 14. A flowchart showing the processing operation of a display device according to a modification of the ninth embodiment. A diagram explaining the binning process of the first pixel region in the flowchart of FIG. 16. 1. Circuit diagram of a pixel circuit according to a first example. 2. Circuit diagram of a pixel circuit according to a second example. 3. Circuit diagram of a pixel circuit according to a third example. 4. Circuit diagram of a pixel circuit according to a fifth example. 5. Circuit diagram of a pixel circuit according to a sixth example. 7. Circuit diagram of a pixel circuit according to a seventh example. 8. Circuit diagram of a pixel circuit according to an eighth example. A diagram showing the interior of a vehicle from the rear to the front of the vehicle. A diagram showing the interior of a vehicle from diagonally rear to diagonally front of the vehicle. A front view of a digital camera which is a second application example of the electronic device. A rear view of a digital camera. An external view of an HMD which is a third application example of the electronic device. An external view of smart glasses. An external view of a TV which is a fourth application example of the electronic device. An external view of a smartphone which is a fifth application example of the electronic device.

[0029] Hereinafter, an embodiment of a display device will be described with reference to the drawings. The following description will focus on the main components of the display device, but the display device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0030] 1 is a block diagram showing a schematic configuration of a display system 3 including a display device 1 and a host device 2 according to a first embodiment. As shown in FIG. 1, the display device 1 according to one embodiment includes a display unit 4 and a plurality of drive circuits 5. The display device 1 performs display on the display unit 4 based on a video signal output from the host device 2.

[0031] The display unit 4 has a pixel array unit 4a including a plurality of pixels arranged in a first direction (e.g., row direction) X and a second direction (e.g., column direction) Y. Each pixel has a light-emitting element and a pixel circuit. The light-emitting element is, for example, an organic EL element or an LED (Light Emitting Diode). Each pixel is a liquid crystal display element. The display unit 4 may be viewed directly by a user, or may be a microdisplay that displays an image obtained by enlarging the image displayed on the display unit 4 using an optical element (not shown). One example of a microdisplay is a micro OLED (Organic Light Emitting Diode) that uses an organic EL element.

[0032] The display unit 4 is divided into a plurality of pixel regions. The plurality of pixel regions includes two or more pixel regions that differ in at least one of display form, shape, or size. Another example includes two or more pixel regions that differ in at least one of pixel size, resolution, layout, shape, and subpixel configuration. The display form is, for example, the resolution of the pixel region. The shape is the outer shape of the pixel region. The size is the area of ​​the pixel region. The display unit 4 may have two or more pixel regions of the same size and shape provided at different pixel positions. The type of pixel region provided in the display unit 4 is arbitrary. This specification mainly describes an example in which the display unit 4 has one or more first pixel regions that are pixel regions of interest and one or more second pixel regions arranged around the first pixel region.

[0033] The first pixel region and the second pixel region differ from each other in at least one of the display mode, arrangement, shape, and size. Furthermore, the first pixel region and the second pixel region differ from each other in at least one of pixel size, resolution, layout, shape, and subpixel configuration. Each pixel may be composed of multiple subpixels of any color combination, such as RGB or RGBW, or subpixel rendering may be performed. Furthermore, the first pixel region and the second pixel region may differ from each other in arrangement direction. For example, the first pixel region may be arranged in a direction inclined from the row and column directions of the display unit 4, and the second pixel region may be arranged parallel to the row and column directions of the display unit 4.

[0034] The multiple drive circuits 5 are provided corresponding to the multiple pixel regions. Each of the multiple drive circuits 5 drives a corresponding pixel region. The first pixel region and the second pixel region, which differ from each other in at least one of display mode, arrangement, shape, and size, are driven by different drive circuits 5. The drive circuit 5 that drives the first pixel region and the drive circuit 5 that drives the second pixel region use different drive methods. The drive method may refer to, for example, the order in which each pixel in the pixel region is driven, the direction in which each pixel is driven, the period in which each pixel is driven, or the resolution of the pixel region. In this way, the multiple drive circuits 5 drive the multiple pixel regions arranged in the display unit 4 using two or more drive methods.

[0035] Each of the multiple drive circuits 5 has a gate driver 7, a source driver 8, a timing controller 9, a storage unit 10, and an interface (I / F) circuit 11. The pixel correction unit 6, the gate driver 7, and the source driver 8 are sometimes collectively referred to as a display controller 12. Some of these functions may be omitted, or may be set in common with other drive circuit units.

[0036] The pixel correction unit 6 corrects the display mode of the second pixel region to a display mode different from that of the first pixel region corresponding to the pixel region of interest. The display mode refers to the resolution, luminance, chromaticity, or display update cycle of the pixel region. For example, the pixel correction unit 6 performs correction to reduce the luminance or chromaticity of the second pixel region below that of the first pixel region. Alternatively, the pixel correction unit 6 reduces the resolution of the second pixel region below that of the first pixel region by performing a binning process in which the same pixel data is written to multiple adjacent pixels in the second pixel region. Alternatively, the pixel correction unit 6 makes the display update cycle of the second pixel region longer than that of the first pixel region. Note that, if a pixel in the second pixel region IR2 has a higher luminance than surrounding pixels, the pixel correction unit 6 may reduce the luminance of the surrounding pixels without reducing the luminance of the higher-luminance pixel.

[0037] The gate driver 7 and the source driver 8 drive the pixels in the first pixel region and the second pixel region in accordance with the correction content of the pixel correction unit 6 .

[0038] The gate driver 7 includes a gate logic unit 7a and a gate analog unit 7b. The gate logic unit 7a includes a shift register that generates pulse signals for driving two or more pixels arranged in one direction within the corresponding pixel region based on signals from the timing controller 9. The gate analog unit 7b generates, based on the pulse signals generated by the gate logic unit 7a, multiple pixel group selection signals for driving multiple pixel group selection lines arranged in one direction within the corresponding pixel region. The gate analog unit 7b includes, for example, a level shift circuit and a buffer circuit (not shown). The level shift circuit converts the signal level of the pulse signals output from the gate logic unit 7a. The buffer circuit enhances the drive capability of the multiple pixel group selection signals in consideration of the load on the multiple pixel group selection lines (e.g., row selection lines). When the pixel region is arranged parallel to the row and column directions, the pixel group selection lines are called row selection lines, and the pixel group selection signals are called row selection signals. When the pixel region is arranged in a direction oblique to the row and column directions, the pixel group selection lines are arranged in a direction oblique to the row direction.

[0039] The gate driver 7 outputs a plurality of pixel group selection signals to a plurality of pixel group selection lines, each of which goes high at a different timing. This allows the gate driver 7 to drive the plurality of pixel groups line-sequentially, one pixel group at a time. As a rule, the same pixel group selection signal is supplied to the plurality of pixels included in the same pixel group (e.g., a pixel row). Therefore, normally, the plurality of pixels included in the same pixel group are driven at the same timing.

[0040] The source driver 8 has a source logic unit 8a and a source analog unit 8b. The source driver 8 drives a plurality of signal lines. Each signal line is connected to a plurality of pixels in the corresponding pixel region. The source logic unit 8a has a shift register that distributes pixel data from the timing controller 9 to the plurality of signal lines. The source analog unit 8b generates a plurality of pixel signals to be supplied to the plurality of signal lines based on the pixel data from the source logic unit 8a.

[0041] When the corresponding pixel regions are arranged parallel to each other in the row and column directions, a plurality of pixel signals output from the source driver 8 are supplied to each pixel via a plurality of vertical signal lines.

[0042] As described above, in this specification, the multiple wirings that are output from the gate driver 7 and extend in a first direction X (e.g., the row direction) within the pixel region are referred to as pixel group selection signals or row selection signals, and the multiple wirings that are output from the source driver 8 and extend in a second direction Y (e.g., the column direction) within the pixel region are referred to as signal lines or vertical signal lines.

[0043] The timing controller 9 includes a clock generator 13 , a timing generator 14 , and an image processing unit 15 .

[0044] The clock generator 13 generates a vertical synchronization clock and a horizontal synchronization clock for the display unit 4 and supplies them to the source driver 8. The timing generator 14 generates a signal that controls the operation timing of the display controller 12 and supplies it to the display controller 12. The image processing unit 15 performs various image processing on image data input from the host device 2 via the I / F circuit 11, and supplies the processed image data to the gate driver 7. The specific content of the image processing performed by the image processing unit 15 is not important. The image data supplied to the gate driver 7 includes a plurality of pixel data to be supplied to a plurality of pixels.

[0045] The storage unit 10 stores instruction information from the host device 2, information such as the display format, shape, size, or pixel position of a plurality of pixel regions on the display unit 4, and the like.

[0046] The I / F circuit 11 includes an image I / F unit 16 , a clock control unit 17 , an H / V synchronization unit 18 , and a data S / P conversion unit 19 .

[0047] The image I / F unit 16 receives image data transmitted from the host device 2. The image data is serial digital data. The clock control unit 17 generates a clock that matches the display frequency of the display device 1 and supplies it to the clock generator 13. The H / V synchronization unit 18 determines the horizontal synchronization timing and vertical synchronization timing of the display device 1 and transmits them to the timing generator 14. The data S / P conversion unit 19 converts the image data into parallel data and supplies it to the image processing unit 15.

[0048] 1 is a device that sends a video signal to the display device 1, and is, for example, a computer, a camera, or a TV. The host device 2 sends image data and a display control signal to the image I / F unit 16. The host device 2 does not necessarily have to be located near the display device 1. For example, the host device 2 may be located at a location remote from the display device 1, and may send the image data and the display control signal to the display device 1 via a wired or wireless network line.

[0049] The display device 1 according to this embodiment has a stacked structure in which multiple substrates are stacked. The substrates can also be called layers, and are, for example, silicon substrates or silicon layers. The stacked substrates may be physically separated substrates or may be semiconductor material layers newly provided on a single substrate. The specific material of the substrates is not limited. It is also possible to use materials other than silicon, such as metal oxides, as the semiconductor layer.

[0050] Fig. 2 is a diagram showing the layered structure of the display device 1 according to the first embodiment. The display device 1 according to this embodiment shown in Fig. 2 includes a first substrate 21 and a second substrate 22 that are layered together. The first substrate 21 has a display unit 4. The first substrate 21 is disposed on the front side of the display device 1, and the second substrate 22 is disposed on the back side of the display device 1. The second substrate 22 has a plurality of drive circuits 5.

[0051] As described above, the display unit 4 is divided into a plurality of pixel regions. A plurality of drive circuits 5 are provided on the second substrate 22 corresponding to the plurality of pixel regions on the first substrate 21. One or more drive circuits 5 are arranged for each pixel region. A corresponding drive circuit 5 is arranged on the second substrate 22 immediately below each pixel region on the first substrate 21. More specifically, each of the plurality of drive circuits 5 is arranged so as to at least partially overlap with the corresponding first pixel region IR1 or second pixel region IR2 when the first substrate 21 and the second substrate 22 are viewed in plan. This shortens the signal transmission distance between each pixel region and the corresponding drive circuit 5, improves noise resistance, and shortens signal propagation time.

[0052] Signals sent and received between each pixel region and the corresponding drive circuit 5 are transmitted through vias, contacts, bumps, Cu-Cu joints, and the like that connect the first substrate 21 and the second substrate 22 .

[0053] A pixel region of interest is often located, for example, in the center of the display unit 4. In this specification, the pixel region of interest is referred to as a first pixel region IR1. The first pixel region IR1 is not necessarily located in the center of the display unit 4, but the following description will mainly focus on an example in which the first pixel region IR1 is located in the center of the display unit 4.

[0054] In this specification, the pixel regions arranged around the first pixel region IR1 are referred to as second pixel regions IR2. In the example of Fig. 2, one first pixel region IR1 and eight second pixel regions IR2 are provided in the display unit 4, but the display form, shape, size, and number of the first pixel region IR1 and the second pixel region IR2 are arbitrary.

[0055] 2 shows an example in which the first pixel region IR1 and the second pixel region IR2 are the same size. In the example of FIG. 2, the size of each pixel in the first pixel region IR1 is approximately ¼ of the size of each pixel in the second pixel region IR2. As a result, the first pixel region IR1 has four times the number of pixels as the second pixel region IR2, and the first pixel region IR1 has four times the resolution of the second pixel region IR2. FIG. 2 is just an example, and the sizes of the first pixel region IR1 and the second pixel region IR2 and the size of each pixel in each pixel region are arbitrary.

[0056] Four drive circuits 5 for driving one first pixel region IR1 and eight drive circuits 5 for driving eight second pixel regions IR2 are arranged on the second substrate 22. The number of pixels driven by each drive circuit 5 on the second substrate 22 is the same.

[0057] In the display device 1 of the first embodiment, the drive circuit 5 for driving the first pixel region IR1 and the drive circuit 5 for driving the second pixel region IR2 are separated, so that the first pixel region IR1 and the second pixel region IR2 can be driven using different drive methods.

[0058] More specifically, in the display device 1 according to the first embodiment, the size of each pixel in the first pixel region IR1 is smaller than the size of each pixel in the second pixel region IR2, so that the first pixel region IR1 can be displayed at a higher resolution than the second pixel region IR2. Furthermore, because the first pixel region IR1 is driven by more drive circuits 5 than the second pixel region IR2, even if the number of pixels in the first pixel region IR1 is greater than the number of pixels in the second pixel region IR2, the display speeds of the first pixel region IR1 and the second pixel region IR2 can be made approximately the same.

[0059] As described above, the display device 1 according to the first embodiment can display each pixel region without creating a sense of incongruity and can display the first pixel region IR1 prominently, even when the first pixel region IR1 and the second pixel region IR2 are mixed in the display unit 4. Furthermore, it is possible to display only the pixel region of interest (the first pixel region IR1) in the display unit at high resolution, which allows a display method that directs the human gaze to the pixel region of interest and reduces power consumption.

[0060] Furthermore, in the first embodiment, the frame rate can be improved because multiple drive circuits 5 can be operated in parallel and the number of pixels driven by one drive circuit 5 is limited. Furthermore, power consumption can be further reduced by driving only the drive circuit 5 that drives the first pixel region IR1 and stopping display updates of the drive circuit 5 that drives the second pixel region IR2 or lengthening the display update cycle.

[0061] Second Embodiment FIG. 3 is a diagram showing the stacked structure of a display device 1 according to a second embodiment, and FIG. 4 is a diagram showing details of the first pixel regions IR1 in the second embodiment. The display device 1 according to the second embodiment differs from the first embodiment in the shape and number of the first pixel regions IR1. In the second embodiment, as shown in FIG. 4, four first pixel regions IR1 are provided near the center of the display unit 4. Of the four first pixel regions IR1, three first pixel regions IR1a have the same shape and size, while the remaining first pixel region IR1b has a different shape and size from the three first pixel regions IR1a. The three first pixel regions IR1a are arranged in different directions relative to the row and column directions of the display unit 4. For example, the three first pixel regions IR1a are arranged in directions that differ by 60 degrees from each other. The longitudinal directions of two of the three first pixel regions IR1a are inclined with respect to the column direction of the display unit 4, and the lateral directions of these two first pixel regions IR1a are inclined with respect to the row direction of the display unit 4. The longitudinal direction of the remaining first pixel region IR1a is the first direction X, and the lateral direction is the second direction Y. The first pixel region IR1b is arranged so as to be surrounded by the three first pixel regions IR1a. This first pixel region IR1b is arranged, for example, in the center of the display unit 4. Note that in the second embodiment, the first pixel region IR1 and the second pixel region IR2 differ from each other in at least one of pixel size, resolution, layout, shape, and subpixel configuration. Each pixel may be composed of multiple subpixels of any color combination, such as RGB or RGBW, or subpixel rendering may be performed.

[0062] In this specification, the short-side direction of the three first pixel regions IR1a according to the second embodiment is referred to as the third direction, and the long-side direction is referred to as the fourth direction. The three first pixel regions IR1a have different third directions and different fourth directions. The first pixel region IR1 disposed in the center of the display unit 4 has a substantially circular shape. The third direction may be the same as or different from the row direction of the display unit 4, and the fourth direction may be the same as or different from the column direction of the display unit 4.

[0063] The second substrate 22 has four drive circuits 5 that drive four first pixel regions IR1. As described above, the four first pixel regions IR1 have different arrangement directions, and therefore the arrangement directions of the pixel group selection lines output from the gate driver 7 in the four drive circuits 5 and the arrangement directions of the signal lines output from the source driver 8 are also different. For example, three drive circuits 5 that drive three first pixel regions IR1a drive two or more pixels in the three first pixel regions IR1a along the third and fourth directions described above. A plurality of second pixel regions IR2 extending in the row and column directions are arranged around the first pixel region IR1. The drive circuit 5 that drives the second pixel region IR2 drives two or more pixels px in the second pixel region IR2 along the row and column directions.

[0064] Of the four first pixel regions IR1, three first pixel regions IR1a have the same number of pixels, but the remaining first pixel region IR1b may have a different number of pixels. In this case, the four drive circuits 5 will not drive the same number of pixels, but even if there is a slight difference in the number of pixels, this does not affect the display quality.

[0065] In the second embodiment, the number of pixels in the four first pixel regions IR1 combined is increased compared to the number of pixels in the surrounding second pixel regions IR2, thereby enabling the pixel region of interest to be displayed at high resolution. Furthermore, the four first pixel regions IR1 that constitute the pixel region of interest are driven by four drive circuits 5, enabling the high-resolution pixel region of interest to be driven at high speed. Furthermore, by arranging the four first pixel regions IR1 in different directions, the combined outline of the four first pixel regions IR1 can be formed into a shape other than a rectangle.

[0066] 5 is a diagram showing the layered structure of a display device 1 according to a third embodiment. As shown in FIG. 5, the display device 1 according to the third embodiment includes an intermediate substrate 23 layered between a first substrate 21 and a second substrate 22. A plurality of pixel selection circuits 24 are arranged on the intermediate substrate 23. The intermediate substrate 23 may be a substrate physically separated from the first substrate 21 and the second substrate 22, or may be a semiconductor material layer newly provided on the first substrate 21 or the second substrate 22.

[0067] Each of the plurality of pixel selection circuits 24 controls the supply of one or more drive signals output from the corresponding drive circuit 5 on the second substrate 22 to any pixel in the corresponding pixel region on the first substrate 21 .

[0068] For example, each of the plurality of pixel selection circuits 24 selects to which row selection line in the corresponding pixel region a row selection signal output from the gate driver 7 in the corresponding drive circuit 5 is to be supplied. Each pixel selection circuit 24 may supply the same row selection signal to two or more selected row selection lines. Alternatively, each pixel selection circuit 24 may supply multiple row selection signals output from the corresponding drive circuit 5 to two or more selected row selection lines.

[0069] Each of the pixel selection circuits 24 selects a vertical signal line in the corresponding pixel region to which the pixel signal output from the source driver 8 in the corresponding drive circuit 5 is to be supplied. Each pixel selection circuit 24 may supply the same pixel signal to two or more selected vertical signal lines. Alternatively, each pixel selection circuit 24 may supply multiple pixel signals output from the corresponding drive circuit 5 to two or more selected vertical signal lines.

[0070] The plurality of pixel selection circuits 24 can arbitrarily switch at least one of the types of row selection lines that supply row selection signals output from the gate driver 7 and the types of vertical signal lines that supply pixel signals output from the source driver 8, for example, in response to an instruction from the host device 2.

[0071] FIG. 6 is a diagram showing an example of a specific configuration of the plurality of pixel selection circuits 24. The plurality of pixel selection circuits 24 each have, for example, a plurality of switches SW1 that switch which row selection line a row selection signal output from the corresponding drive circuit 5 is to be supplied to. Each switch SW1 can simultaneously select multiple row selection lines. The pixel selection circuit 24 may also have a plurality of switches SW1 that switch which vertical signal line a pixel signal is to be supplied to. Each switch SW1 can simultaneously select multiple vertical signal lines. This allows the pixel selection circuit 24 to simultaneously select multiple pixels as needed. This facilitates changing the resolution.

[0072] As described above, in the third embodiment, by disposing the intermediate substrate 23 having the plurality of pixel selection circuits 24 between the first substrate 21 and the second substrate 22, the plurality of pixel regions on the first substrate 21 can be driven by any driving method. Furthermore, each pixel selection circuit 24 can easily switch the resolution and display update cycle of each pixel region. As a means for switching these drives, it is possible to analyze the contents of the image signal sent from the host device 2, or to have the display device independently change the selection of the drive circuit based on gaze information from an imaging device, posture information, an eye tracking device, or the like.

[0073] 7 is a diagram showing the layered structure of a display device 1 according to a fourth embodiment. As shown in FIG. 6 , the display device 1 according to the fourth embodiment includes an intermediate substrate 23a layered between a first substrate 21 and a second substrate 22, and a plurality of region selection circuits 25 are arranged on the intermediate substrate 23a. The plurality of region selection circuits 25 are provided corresponding to the plurality of drive circuits 5 on the second substrate 22. The intermediate substrate 23a may be a substrate physically separated from the first substrate 21 and the second substrate 22, or may be a semiconductor material layer newly provided on the first substrate 21 or the second substrate 22.

[0074] For example, each of the multiple region selection circuits 25, in response to instructions from the host device 2, selects one or more of the multiple pixel regions and / or slightly adjusts the shape or size of the selected pixel region based on the drive signal output from the corresponding drive circuit 5. This allows multiple pixel regions to be driven by a single drive circuit 5, and allows at least one of the shape or size of the driven pixel region to be arbitrarily switched. As a means for switching these drives, the display device can analyze the contents of the image signal sent from the host device 2, or it can independently change the selection of the drive circuit based on gaze information from an imaging device, posture information, or an eye-tracking device.

[0075] 8 is a diagram illustrating the operation of the region selection circuit 25. Each of the plurality of region selection circuits 25 selects a pixel region having at least one of an arbitrary shape and size, for example, in response to an instruction from the host device 2. Then, each region selection circuit 25 sequentially drives a plurality of row selection lines of the selected pixel region with row selection signals output from a gate driver 7 in a corresponding drive circuit 5 on the second substrate 22, and supplies pixel signals output from a source driver 8 in a corresponding drive circuit 5 on the second substrate 22 to a plurality of vertical signal lines of the selected pixel region.

[0076] 9 is a diagram showing an example of a specific configuration of multiple area selection circuits 25. Each area selection circuit 25 has multiple switches SW2 that select one or multiple pixel areas in the display unit 4 and supply row selection signals from the corresponding drive circuits 5 to the selected pixel areas. This allows one or multiple drive circuits 5 to be assigned to one pixel area. If high-resolution display is not required, one or more drive circuits 5 may be stopped to reduce power consumption. Furthermore, if high-resolution display is required, one pixel area is driven by multiple drive circuits 5.

[0077] As a result, according to the fourth embodiment, it is possible to easily set a pixel area of ​​interest of any shape and size at any pixel position within the display unit 4, and to change the driving method between the pixel area of ​​interest and the pixel areas surrounding it.

[0078] A display device 1 may be provided that includes both the pixel selection circuit 24 according to the third embodiment and the region selection circuit 25 according to the fourth embodiment. In this case, the pixel selection circuit 24 and the region selection circuit 25 may be disposed on a single intermediate substrate 23, or a first intermediate substrate and a second intermediate substrate may be provided that are stacked between the first substrate 21 and the second substrate 22, with the pixel selection circuit 24 disposed on one of the first intermediate substrate and the region selection circuit 25 disposed on the other.

[0079] Fifth Embodiment The pixel correction unit 6 shown in FIG. 1 can make the display modes of the first pixel region IR1 and the second pixel region IR2 different from each other by performing any correction.

[0080] 10 is a flowchart showing the processing operation according to the first example of the pixel correction unit 6. First, it is determined whether or not to bin the pixel data of m rows x n columns (step S1). Here, binning refers to the process of writing the same pixel data to pixels of m rows x n columns. Binning is performed on the second pixel region IR2 arranged around the pixel region of interest.

[0081] If step S1 is NO, i.e., for the first pixel region IR1, the processing in Fig. 10 is terminated. In this case, an individual pixel signal is supplied to each pixel for display. If step S1 is YES, the maximum luminance value L_max of the pixels included in the pixel group of m rows x n columns to be binned and the average luminance value L_ave of the pixel group of m rows x n columns are calculated (step S2).

[0082] Next, it is determined whether L_max≧L_ave×1.3 (Step S3). Note that the value 1.3 is just an example and may be changed as desired. In Step S3, it is determined whether the average luminance value of the pixel group is equal to or greater than a predetermined threshold.

[0083] If step S3 is NO, the pixel group of m rows x n columns is corrected to the average luminance value L_ave (step S4).

[0084] If step S3 is YES, the luminance of each pixel included in the pixel group of m rows x n columns is corrected to a corrected luminance value L_cor so that L_max ≥ L_cor > L_ave (step S5). By performing the correction in step S4, it is possible to display at the required luminance without destroying the luminance information for each pixel group to be binned.

[0085] The pixel correction unit 6 may perform correction processing other than that shown in FIG. 10 . FIG. 11 is a flowchart showing a second example of the processing operation of the pixel correction unit 6. First, it is determined whether or not to bin the pixel data of m rows by n columns (step S11). If step S11 is NO, the processing of FIG. 11 is terminated. If step S11 is YES, the average chromaticity value uv_ave of each pixel included in the pixel group of m rows by n columns to be binned is calculated (step S12). Next, the maximum difference Δuv_max between the chromaticity of each pixel included in the pixel group of m rows by n columns and the average chromaticity value uv_ave is calculated (step S13). Next, it is determined whether or not the maximum difference uv_max is ≥ 0.1 (step S14). The value 0.1 is an example and may be changed as desired. In step S14, it is determined whether or not the maximum difference between the chromaticity of each pixel included in the pixel group and the average chromaticity value is equal to or greater than a predetermined threshold.

[0086] If step S14 is NO, the pixel group of m rows x n columns is corrected to the average chromaticity value uv_ave (step S15).

[0087] If step S14 is YES, the chromaticity of each pixel included in the pixel group of m rows by n columns is corrected to the corrected chromaticity uv_cor so that uv_max≧uv_cor>uv_ave (step S16). By performing the correction in step S16, the chromaticity information for each pixel group to be binned is not lost, and the necessary chromaticity information can be maintained.

[0088] In this way, in the fifth embodiment, when binning the second pixel region IR2 arranged around the pixel region of interest, at least one of the luminance and chromaticity of the pixel group to be binned is corrected in accordance with the processing operation of Figure 10 or Figure 11. Therefore, when used for applications such as games, in-vehicle applications, and aircraft applications, if data that should be focused on occurs outside the focus region, correction can be made without destroying the features.

[0089] Sixth Embodiment The first pixel region IR1 and the second pixel region IR2 corresponding to the pixel region of interest in the first to fifth embodiments described above may have any shape and size, and may take various shapes and sizes.

[0090] 12 is a plan view showing the outer shapes of the first pixel region IR1 and the second pixel region IR2 displayed on the display unit 4 of the display device 1 according to the sixth embodiment. As shown in Fig. 12, the first pixel region IR1 and the second pixel region IR2 in the sixth embodiment are composed of a plurality of regular hexagonal pixels px, and the outer shapes of the first pixel region IR1 and the second pixel region IR2 are nearly circular.

[0091] 12 shows an example in which a first pixel region IR1 is arranged in the center of the display unit 4, and multiple second pixel regions IR2 having the same size as the first pixel region IR1 are arranged around it, but the first pixel region IR1 and the second pixel region IR2 may have different sizes. Furthermore, two or more first pixel regions IR1 may be arranged in the display unit 4.

[0092] As shown in Figure 12, by making the outer shapes of the first pixel region IR1 and the second pixel region IR2 approximately circular, it is possible to make the display light from the display device 1 incident on the optical system, like a microdisplay, and to project the enlarged display light emitted from the optical system onto a predetermined projection surface.

[0093] Fig. 13 is a diagram showing an example of an optical system of a microdisplay. The optical system in Fig. 13 shows a lens with a short lens length called a pancake lens 26. By arranging the pancake lens 26 as shown in Fig. 13 on the front side of the display unit 4, the size of the displayed image can be adjusted while keeping the thickness of the display device 1 small.

[0094] The pancake lens 26 can focus the display light near the optical axis, but distortion often occurs in the display light away from the optical axis. In this case, the first pixel region IR1 located in the center of the display unit 4 is clearly visible to the human eye 27, while the second pixel region IR2 located around the first pixel region IR1 is perceived as having reduced brightness and distorted. Therefore, even if the resolution of the second pixel region IR2 is reduced or the display update cycle of the second pixel region IR2 is slowed, the human eye 27 does not perceive any discomfort.

[0095] In this way, by delivering the display light from the display device 1 to the human eye 27 through an optical system such as a pancake lens 26, only the first pixel region IR1 can be displayed clearly at high resolution, so that even if the resolution of the second pixel region IR2 is lowered or the display update cycle of the second pixel region is lengthened, it will not be noticeable, and power consumption can be reduced.

[0096] Seventh Embodiment In the first to sixth embodiments, an example was shown in which a second substrate 22 having a plurality of drive circuits 5 is stacked on a first substrate 21 having a display unit 4, but the drive circuits 5 may be arranged separately on a plurality of substrates (layers).

[0097] 14 is a diagram showing the layered structure of a display device 1 according to the seventh embodiment. The display device 1 according to the seventh embodiment has a structure in which a first substrate 21 on which a display unit 4 is arranged, a second substrate 22 on which a plurality of gate drivers 7 and a plurality of source drivers 8 in a plurality of drive circuits 5 are arranged, a third substrate 28 on which a plurality of timing controllers 9 in a plurality of drive circuits 5 are arranged, and a fourth substrate 29 on which a plurality of memory units 10 and a plurality of I / F circuits 11 in a plurality of drive circuits 5 are arranged, etc. are arranged.

[0098] The first to fourth substrates 21, 22, 28, and 29 may be called first to fourth layers, and may be formed of, for example, a silicon substrate or silicon layer as a base material. The first to fourth substrates 21, 22, 28, and 29 may be bonded to each other using vias, contacts, bumps, Cu-Cu bonding, or the like.

[0099] In addition, at least one of an intermediate substrate 23 on which a pixel selection circuit 24 similar to that in FIG. 5 is arranged and an intermediate substrate 23a on which a region selection circuit 25 similar to that in FIG. 6 is arranged may be stacked between the first substrate 21 and the second substrate 22 in FIG. 14.

[0100] In this way, by dividing the drive circuit 5 into multiple substrates and stacking them, there is more room for the layout of each circuit arranged on each substrate, which makes it easier to design the layout of each substrate and improves manufacturing yield.In addition, since the size of each substrate can be reduced, the chip size can be made smaller.

[0101] 15 is a cross-sectional view of a display device 1 according to an eighth embodiment. The display device 1 according to the eighth embodiment has a structure in which a second substrate 22 on which a plurality of drive circuits 5 are arranged is stacked on a first substrate 21 on which a display unit 4 is arranged. The display device 1 according to the eighth embodiment is an organic electroluminescent device (OLED).

[0102] The display device 1 according to the eighth embodiment has a configuration in which a pad section 20 is arranged around a display section 4. A first substrate 21 and a second substrate 22 are stacked. The first substrate 21 is arranged on the front side of the display device 1, and the second substrate 22 is arranged on the back side of the display device 1.

[0103] The second substrate 22 includes a semiconductor material layer 31, an interlayer insulating layer 32, and pad electrodes 33. As shown in FIG. 2, a plurality of drive circuits 5 are arranged on the second substrate 22. A plurality of transistors 34 constituting the plurality of drive circuits 5 are arranged on the semiconductor material layer 31. The semiconductor material layer 31 is, for example, a silicon layer. A plurality of wiring layers 35 and second connection electrodes 36 are arranged on the interlayer insulating layer 32. The plurality of transistors 34 are electrically connected to the plurality of wiring layers 35 by vias or contacts (not shown).

[0104] The first substrate 21 includes a semiconductor material layer 41 and an interlayer insulating layer 42. The interlayer insulating layer 42 of the first substrate 21 is disposed opposite the interlayer insulating layer 32 of the second substrate 22. A plurality of wiring layers 43 and first connection electrodes 44 are disposed on the interlayer insulating layer 42.

[0105] The first substrate 21 and the second substrate 22 are in contact at a bonding surface SF, and the first connection electrode 44 of the first substrate 21 and the second connection electrode 36 of the second substrate 22 are bonded by, for example, Cu--Cu bonding.

[0106] Pad electrodes 33 are arranged on the periphery of the second substrate 22. The plurality of drive circuits 5 transmit and receive various signals to and from the first substrate 21 via the plurality of transistors 34, the plurality of wiring layers 35, and the plurality of second connection electrodes 36.

[0107] On the side of the first substrate 21 opposite the contact surface of the semiconductor material layer 41 with the interlayer insulating layer 42, an insulating layer 45, a first electrode 46, an organic layer 47, a second electrode 48, a protective film 49, a color filter 50, a microlens 51, a sealing resin layer 52, and an opposing substrate 53 are stacked in this order.

[0108] A first electrode 46 is disposed for each pixel px. An organic layer 47 is disposed between the first electrode 46 and the second electrode 48, and adjusting the voltage applied to the first electrode 46 enables gradation display for each pixel px. The first electrode 46 is connected to the wiring layer 43 via a contact 54. The wiring layer 43 is connected to the corresponding drive circuit 5 on the second substrate 22 side via a contact (not shown) and a first connection electrode 44.

[0109] A pad section 20 is provided around the display section 4 on the first substrate 21. A pad opening 55 is provided in the first substrate 21 in the pad section 20. A pad electrode 33 on the second substrate 22 is exposed in the pad opening 55. A bonding wire (not shown) is connected to the pad electrode 33.

[0110] The cross-sectional structure of the display device 1 according to the eighth embodiment shown in Fig. 15 is applicable to the display devices 1 according to the first to seventh embodiments described above. The display devices 1 according to the first to seventh embodiments may have a cross-sectional structure different from that shown in Fig. 15. For example, the cross-sectional structure of a microdisplay may be adopted. Alternatively, the display device 1 may be configured with a liquid crystal display device instead of an OLED.

[0111] In this way, in the eighth embodiment, the first substrate 21 and the second substrate 22 are joined by Cu-Cu bonding, so that a stacked structure can be easily realized in which the display unit 4 is arranged on the first substrate 21 and multiple drive circuits 5 are arranged on the second substrate 22.

[0112] Ninth Embodiment A display device 1 according to a ninth embodiment has the same block configuration as that shown in FIG. 1, but is characterized in that the apparent resolution is increased.

[0113] In the display device 1 according to the ninth embodiment, the display unit 4 includes a first pixel region IR1, which is a pixel region of interest, and a second pixel region IR2 surrounding the first pixel region IR1. The first pixel region IR1 and the second pixel region IR2 are displayed using a binning process. Specifically, the same pixel signal is supplied to each of the first pixel region IR1 and the second pixel region IR2 for each pixel group consisting of 2 × 2 = 4 pixels. As a result, the first pixel region IR1 and the second pixel region IR2 can only achieve a resolution that is ¼ of the resolution achieved by the actual pixel arrangement.

[0114] 16 is a flowchart showing the processing operation of the display device 1 according to the ninth embodiment. A pixel signal is supplied to the first pixel region IR1, which is a pixel region of interest, for each pixel group pxg to perform pixel display (step S21).

[0115] Next, at a display update speed twice as fast as normal, the division of pixel groups pxg in the first pixel region IR1 is shifted by one pixel in the row and column directions, and pixel signals are supplied to each pixel group pxg to perform pixel display (step S22). In this way, the pixel groups pxg in step S22 are shifted by one pixel in the row and column directions from the pixel groups pxg in step S21, and in step S22, binning processing is performed for each pixel group pxg shifted by one pixel in the row and column directions.

[0116] Before and after the processes of steps S21 and S22, pixel signals are supplied to the second pixel region IR2 for each pixel group pxg at a normal display update speed to perform pixel display (step S23). While the first pixel region IR1 has undergone binning processing twice at high speed, the second pixel region IR2 has undergone binning processing once without shifting the pixel groups pxg.

[0117] Fig. 17 is a diagram illustrating the processing of steps S21 and S22 in Fig. 16. In the first pixel region IR1, pixel signals are supplied to each pixel group pxg consisting of 2 × 2 pixels to perform pixel display, and then pixel signals are supplied to each new pixel group pxg shifted by one pixel in the row and column directions to perform pixel display, which appears to be equivalent to pixel display at four times the resolution.

[0118] The pixel group pxg can be easily shifted by one pixel in the row and column directions by the drive circuit 5. This can be achieved by shifting the timing at which the gate driver 7 drives the row selection lines and the timing at which the source driver 8 drives the vertical signal lines by one pixel.

[0119] 16 shows an example in which the same pixel signal is supplied to a pixel group pxg consisting of 2×2 pixels, but the number of pixels included in the pixel group pxg is arbitrary. Also, multiple types of binning processes may be combined.

[0120] Fig. 18 is a flowchart showing the processing operation of the display device 1 according to a modified example of the ninth embodiment, and Fig. 19 is a diagram explaining the binning process of the first pixel region IR1 in the flowchart of Fig. 18. Pixel signals are supplied to the first pixel region IR1, which is the pixel region of interest, for each pixel group pxg consisting of 2 × 2 pixels, to perform pixel display (step S31).

[0121] Next, pixel signals are supplied to each pixel group pxg newly generated by shifting one pixel in the row direction for the first pixel region IR1 in step S31, thereby performing pixel display (step S32).

[0122] Next, pixel signals are supplied to each pixel group pxg newly generated by shifting one pixel in the column direction for the first pixel region IR1 in step S31, thereby performing pixel display (step S33).

[0123] Next, pixel signals are supplied to each pixel group pxg newly generated by shifting one pixel at a time in the row and column directions for the first pixel region IR1 in step S31, thereby performing pixel display (step S34).

[0124] The processes of steps S31 to S34 are repeated in order. The binning process of steps S31 to S34 is performed at high speed.

[0125] Before or after the processing of steps S31 to S34, pixel signals are supplied to the second pixel region IR2 for each pixel group pxg at a normal display update rate to perform pixel display (step S35).

[0126] As such, in Figure 18, for the first pixel region IR1, binning processing is performed four times at high speed while shifting the division of the pixel group pxg, while for the second pixel region IR2, binning processing is performed once without changing the division of the pixel group pxg.

[0127] The display processing of the first pixel region IR1 shown in Fig. 17 and Fig. 18 may be performed only on pixels of a specific color, for example, the processing of Fig. 16 or Fig. 18 may be performed only on green pixels in the first pixel region IR1, which have the highest luminosity.

[0128] As described above, in the ninth embodiment, when displaying the first pixel region IR1, which is the pixel region of interest, the binning process is repeated while shifting the pixel group pxg, which is made up of multiple pixels, by one pixel at a time, thereby increasing the apparent resolution of the first pixel region IR1. Furthermore, by setting the display update rate of the binning process in the first pixel region IR1 higher than the display update rate of the binning process in the second pixel region IR2, the first pixel region IR1 can be displayed at high resolution while the first pixel region IR1 and the second pixel region IR2 are displayed seamlessly. Furthermore, by repeating the binning process while shifting the pixel group pxg by one pixel only for color pixels with high luminosity, the first pixel region IR1 can be displayed at high resolution while reducing power consumption.

[0129] (Specific Circuit Configuration of Pixel Circuit) Each pixel PX arranged in the pixel array section 4a of the display device 1 according to this embodiment has a pixel circuit 4b that drives an organic EL element, which is a self-luminous element. The specific circuit configuration of the pixel circuit 4b is arbitrary. Representative circuit configurations will be described below in order.

[0130] FIG. 20A is a circuit diagram of a pixel circuit 4b according to a first example. As shown in FIG. 20A, the pixel circuit 4b according to the first example includes NMOS transistors Q11 and Q12 and a capacitor C11. The gate of the transistor Q1 is connected to a control line WSL that supplies a write control signal for a grayscale voltage, the drain is connected to a signal line SGL, and the source is connected to the gate of the transistor Q12. The drain of the transistor Q12 is connected to a power supply line VCCP. A capacitor C11 is connected between the gate and source of the transistor Q12. The source of the transistor Q12 is connected to the anode of the light-emitting element EL, and the cathode is connected to the power supply line Vcat. The power supply line VCCP supplies a voltage for light emission quenching control, and the voltage level of the power supply line VCCP is switched appropriately to a first voltage or a second voltage lower than the first voltage.

[0131] In FIG. 20A , when transistor Q11 is turned on, the voltage across capacitor C11 is set based on the pixel signal supplied from signal line SGL. During a period when the voltage of power supply line VCCP is at a first voltage, transistor Q12 passes a current corresponding to the voltage across capacitor C11 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q12. In this manner, pixel PX emits light at a luminance corresponding to the pixel signal. During a period when power supply line VCCP is at a second voltage, light-emitting element EL is extinguished. In FIG. 20A , at least one of the light-emitting pattern and light-emitting duty can be controlled by controlling the voltage of power supply line VCCP, for example. Specifically, during light emission, the power supply line VCCP is set higher than the cathode voltage Vcath of the light-emitting element EL, and during extinguishing, VCCP≦Vcath.

[0132] FIG. 20B is a circuit diagram of a pixel circuit 4b according to the second example. As shown in FIG. 20B, the pixel circuit 4b according to the second example includes PMOS transistors Q11 to Q14 and capacitors C11 and C12. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor Q12. Capacitors C11 and C12 are connected in series between the drain of transistor Q11 (the gate of transistor Q12) and a power supply line VCCP. The drain of transistor Q13 is connected to the source of transistor Q12. The source of transistor Q13 is connected to the power supply line VCCP, and its gate is connected to a control line DSL. The voltage level of the control line DSL switches between when the light-emitting element EL is emitting light and when it is not emitting light. The control line DSL is also used to control the correction voltage. The control line WSL is used to control the writing of the grayscale voltage. The drain of transistor Q12 is connected to the anode of the light-emitting element EL and the source of transistor Q14. The drain of transistor Q14 is connected to the power supply line VSS, and the gate is connected to control line AZSL. The control line AZSL controls whether the anode of the light-emitting element EL is set to a reset voltage.

[0133] When the transistor Q11 is turned on, the voltage across the capacitor C11 is set based on the pixel signal supplied from the signal line SGL. The transistor Q13 is turned on and off based on the signal on the control line DSL. While the transistor Q13 is in the on state, the transistor Q12 passes a current corresponding to the voltage across the capacitor C11 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor Q12. In this way, the pixel PX emits light at a luminance corresponding to the pixel signal. The transistor Q14 is turned on and off based on the signal on the control line AZSL. While the transistor Q14 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0134] 20C is a circuit diagram of a pixel circuit 4b according to the third example. As shown in FIG. 20C, the pixel circuit 4b according to the third example includes NMOS transistors Q11 to Q14 and a capacitor C11. The gate of transistor Q11 is connected to a control line WSL, the drain is connected to a signal line SGL, and the source is connected to the gate of transistor Q12. The drain of transistor Q12 is connected to the source of transistor Q13. The gate of transistor Q13 is connected to a control line DSL, and the drain is connected to a power supply line VCCP. The source of transistor Q12 is connected to the anode of the light-emitting element EL and the drain of transistor Q14. The source of transistor Q14 is connected to the power supply line VSS, and the gate is connected to a control line AZSL.

[0135] When the transistor Q13 is turned on, the voltage across the capacitor C11 is set based on the pixel signal supplied from the signal line SGL. The transistor Q13 is turned on and off based on the signal on the control line DSL. While the transistor Q13 is on, the transistor Q12 passes a current corresponding to the voltage across the capacitor C11 through the light-emitting element EL. The light-emitting element EL emits light based on the current supplied from the transistor Q12. In this way, the pixel PX emits light at a luminance corresponding to the pixel signal. The transistor Q14 is turned on and off based on the signal on the control line AZSL. While the transistor Q14 is on, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0136] FIG. 20D is a circuit diagram of a pixel circuit 4b according to the fourth example. As shown in FIG. 20D, the pixel circuit 4b according to the fourth example includes PMOS transistors Q11, Q12, Q14, Q15, and Q16, and a capacitor C13. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a signal line SGL, and its drain is connected to the gate of transistor Q12 and the source of transistor Q15. The source of transistor Q12 is connected to a power supply line VCCP, and its drain is connected to the drain of transistor Q15 and the source of transistor Q16. Capacitor C13 is connected between the gate of transistor Q12 and the power supply line VCCP. The gate of transistor Q15 is connected to a control line AXSL1. The gate of transistor Q16 is connected to a control line DSL, and its drain is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of transistor Q14 is connected to a control line AZSL2, and its drain is connected to the power supply line VSS.

[0137] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied from signal line SGL. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q12 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q12. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor Q15 is turned on and off based on the signal on control line AZSL1. While transistor Q15 is on, the drain and gate of transistor Q12 are connected to each other. Transistor Q14 is turned on and off based on the signal on control line AZSL2. While transistor Q14 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0138] 20E is a circuit diagram of a pixel circuit 4b according to a fifth example. The pixel circuit 4b according to the fifth example includes PMOS transistors Q11, Q13, Q14, Q15, Q16, and Q17, and capacitors C13, C14, and C15. The gate of transistor Q11 is connected to a control line WSL1, its source is connected to a signal line SGL2, and its drain is connected to the gate of transistor Q13. The source of transistor Q13 is connected to a power supply line VCCP, and its drain is connected to the drain of transistor Q15 and the source of transistor Q16. Capacitor C13 is connected between the gate of transistor Q13 and the power supply line VCCP. The gate of transistor Q15 is connected to a control line AZSL1. Capacitors C14 and C15 are connected in series between the source of transistor Q15 and the power supply line VSS. The gate of transistor Q16 is connected to a control line DSL, and its drain is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of the transistor Q14 is connected to the control line AZSL2, and the drain is connected to the power supply line VSS.

[0139] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied from signal line SGL1 via capacitor C14. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor Q15 is turned on and off based on the signal on control line AZSL1. While transistor Q15 is on, the drain of transistor Q13 and signal line SGL2 are connected to each other. Transistor MP66 is turned on and off based on the signal on control line AZSL2. While transistor Q16 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line VSS.

[0140] 20F is a circuit diagram of a pixel circuit 4b according to the sixth example. The pixel circuit 4b according to the sixth example is disposed between the first control unit 40 and the second control unit 61. The first control unit 40 and the second control unit 61 are shared by multiple pixels PX in the pixel array unit 4a.

[0141] The pixel circuit 4b of each pixel PX includes PMOS transistors Q11, Q15, Q16, and Q18, and a capacitor C13. The gate of the PMOS transistor Q11 is connected to the control line WSL, its source is connected to the signal line 63, and its drain is connected to the gate of the transistor Q13. The capacitor C13 is connected between the gate of the transistor Q13 and the power supply line Vel. The drain of the transistor Q13 is connected to the drain of the transistor Q15 and the source of the transistor Q16. The source of the transistor Q15 is connected to the signal line 63. The gate of the transistor Q16 is connected to the control line DSL, and its drain is connected to the anode of the light-emitting element EL and the drain of the transistor Q18. The gate of the transistor Q18 is connected to the gate of the transistor Q15 and the control line AZSL. The source of the transistor Q18 is connected to the power supply line Vorst.

[0142] The first control unit 40 has transfer gates TG11 and TG12, PMOS transistors Q19 and Q20, and a capacitor C16. The transfer gate TG11 switches whether or not a pixel signal is transmitted to a signal line 62. The transfer gate TG12 switches whether or not a signal line 63 is connected to the source of transistor Q18. The gate of transistor Q19 is connected to a control line INIL, its source is connected to a power supply line Vini, and its drain is connected to the signal line 63. The gate of transistor Q20 is connected to a control line ELL, its source is connected to a power supply line Vel, and its drain is connected to the signal line 63.

[0143] The second control unit 61 has a transfer gate TG13, a PMOS transistor Q21, and a capacitor C17. The transfer gate TG13 switches whether or not the signal line 62 is connected to one end of the capacitor C17. The gate of the transistor Q21 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to one end of the capacitor C17. The other end of the capacitor C17 is connected to the signal line 63.

[0144] When transistor Q11 is turned on, the voltage across capacitor C13 is set based on the pixel signal supplied via transmission gate TG11, signal line 62, transmission gate TG13, capacitor C17, and signal line 63. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitor C13 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistors Q15 and Q18 are turned on and off based on the signal on control line AZSL. While transistor Q15 is on, the drain of transistor Q13 and the source of transistor Q16 are connected to signal line 63. While transistor Q18 is on, the anode voltage of light-emitting element EL is initialized by being set to the voltage of power supply line Vorst. Furthermore, transistor Q19 is turned on and off based on the signal on control line INIL, transistor Q20 is turned on and off based on the signal on control line ELL, and transistor Q21 is turned on and off based on the signal on control line REFL. When transistor Q19 is turned on, signal line 63 is set to the voltage of power supply line Vini, and when transistor Q20 is turned on, signal line 63 is set to the voltage of power supply line Vel. When transistor Q21 is turned on, one end of capacitor C17 is initialized by being set to the voltage of power supply line Vref.

[0145] FIG. 20G is a circuit diagram of a pixel circuit 4b according to the seventh example. The pixel circuit 4b according to the seventh example includes PMOS transistors Q11, Q13, Q14, Q16, Q22, Q23, Q24, Q24, and Q26, and a capacitor C18. The gate of transistor Q11 is connected to a control line WSL, its source is connected to a control line SGL, and its drain is connected to the drain of transistor Q13 and the source of transistor Q22. The source of transistor Q13 is connected to a power supply line VCCP, and its gate is connected to a control line DSL. The gate of transistor Q22 is connected to the sources of transistors Q23, Q25, and one end of capacitor C18. The other end of capacitor C18 is connected to the power supply line VCCP. The drain of transistor Q22 is connected to the source of transistor Q16 and the drain of transistor Q26. The drain of transistor Q23 is connected to the source of transistor Q24. The gates of transistors Q23 and Q24 are connected to a control line AZSL1. The drain of transistor Q24 is connected to the power supply line VSS. The gates of transistors Q25 and Q26 are connected to the control line WSL. The drain of transistor Q16 is connected to the anode of the light-emitting element EL and the source of transistor Q14. The gate of transistor Q14 is connected to the control line AZSL2, and the drain is connected to the power supply line VSS.

[0146] When transistors Q11, Q22, Q26, and Q25 are turned on, the voltage across capacitor C18 is set based on the pixel signal supplied from signal line SGL. Transistors Q13 and Q16 are turned on and off based on the signal on control line DSL. While transistors Q13 and Q16 are on, transistor Q22 passes a current corresponding to the voltage across capacitor C18 through light-emitting element EL. The light-emitting element EL emits light based on the current supplied from transistor Q22. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistors Q23 and Q24 are turned on and off based on the signal on control line AZSL1. While transistors Q23 and Q24 are on, the gate voltage of transistor Q22 is initialized by being set to the voltage of power supply line VSS. Transistor Q14 is turned on and off based on the signal on control line AZSL2. During the period in which the transistor Q14 is in the on state, the anode voltage of the light-emitting element EL is initialized by being set to the voltage of the power supply line VSS.

[0147] FIG. 20H is a circuit diagram of a pixel circuit 4b according to an eighth example. The pixel circuit 4b according to the eighth example includes NMOS transistors Q13, Q14, and Q16, capacitors C19 and C20, and a transfer gate TG14. The transfer gate TG14 includes an NMOS transistor Q27 and a PMOS transistor Q28 connected in parallel. The transfer gate TG14 switches between connecting and disconnecting the control line SGL and the gate of transistor Q13. One end of each of capacitors C19 and C20 is connected to the gate of transistor Q13, and the other end is connected to a power supply line VSS2. The drain of transistor Q13 is connected to a power supply line VCCP, and the source is connected to the drains of transistors Q14 and Q16. The gate of transistor Q14 is connected to a control line AZL, and the source is connected to a power supply line VSS1. The gate of transistor Q16 is connected to a control line DSL, and the source is connected to the anode of the light-emitting element EL. The gate of the transistor Q27 constituting the transfer gate TG14 is connected to a control line WSNL, and the gate of the transistor Q28 is connected to a control line WSPL.

[0148] When at least one of transistors Q27 and Q28 is turned on, the voltage across capacitors C19 and C20 is set based on the pixel signal supplied from signal line SGL. Transistor Q16 is turned on and off based on the signal on control line DSL. While transistor Q16 is on, transistor Q13 passes a current corresponding to the voltage across capacitors C19 and C20 through light-emitting element EL. Light-emitting element EL emits light based on the current supplied from transistor Q13. In this way, pixel PX emits light at a luminance corresponding to the pixel signal. Transistor MN66 may be turned on and off based on the signal on control line AZL. Transistor Q14 may also function as a resistor element having a resistance value corresponding to the signal on control line AZL. In this case, transistors Q13 and Q14 form a so-called source follower circuit.

[0149] The pixel circuits 4b according to the first to eighth examples shown in Figures 20A to 20H are representative examples of pixel circuits 4b according to the present disclosure, and the display device 1 according to the present disclosure can be applied to pixel circuits 4b having circuit configurations other than those shown in Figures 20A to 20H.

[0150] In this manner, in this embodiment, when each pixel row is scanned in sequence to display the display area, at least one of the light emission pattern and the light emission duty is made different in two or more consecutive display frames, so that it is possible to suppress a decrease in brightness around the image displayed in the display area and improve display quality. Although the light emission pattern in which a decrease in brightness is more noticeable varies depending on the shape and size of the image displayed in the display area, by, for example, switching the light emission pattern for each display frame, it is possible to suppress a decrease in brightness around the image, regardless of the shape and size of the image.

[0151] According to each of the embodiments described above, by varying the number of pixels in one or more pixel regions among a plurality of pixel regions, it is possible to provide optimal driving for the pixel regions. For example, in a region of interest near the center, higher resolution pixels can be formed than in other regions, enabling smooth display. Furthermore, by driving the region of interest at a higher frame rate, it is possible to provide a more faithful display without delay and a display that does not cause VR sickness.

[0152] Furthermore, in one embodiment of the present invention, a region not of interest is set to drive a different number of pixels (for example, a larger number of pixels) than that of the region of interest, thereby making it possible to further reduce power consumption.

[0153] (Application examples of the display device 1 and electronic device according to the present disclosure) (First application example) The display device 1 according to the present disclosure and an electronic device incorporating the display device 1 can be used for various purposes. Figures 21A and 21B are diagrams showing the internal configuration of a vehicle 100, which is a first application example of an electronic device equipped with a display device 1 according to the present disclosure. Figure 21A is a diagram showing the interior of the vehicle 100 from the rear to the front of the vehicle 100, and Figure 21B is a diagram showing the interior of the vehicle 100 from diagonally rear to diagonally front of the vehicle 100.

[0154] The vehicle 100 of Figures 21A and 21B has a center display 101, a console display 102, a head-up display 103, a digital rearview mirror 104, a steering wheel display 105, and a rear entertainment display 106.

[0155] The center display 101 is disposed on the dashboard 107 in a position facing the driver's seat 108 and the passenger's seat 109. FIG. 21 shows an example of a horizontally elongated center display 101 extending from the driver's seat 108 to the passenger's seat 109, but the screen size and location of the center display 101 are arbitrary. The center display 101 can display information detected by various sensors. As a specific example, the center display 101 can display an image captured by an image sensor, a distance image to obstacles in front of or on the side of the vehicle measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 101 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0156] The safety-related information includes information such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger has been abandoned. For example, this information is detected by a sensor disposed on the rear side of the center display 101. The operation-related information is obtained by detecting gestures related to passenger operations using a sensor. The detected gestures may include operations of various equipment within the vehicle 100. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's behavior while on board. By acquiring and storing the life log, the condition of the passenger at the time of the accident can be confirmed. The health-related information is obtained by detecting the passenger's body temperature using a temperature sensor and inferring the passenger's health condition based on the detected body temperature. Alternatively, the passenger's face may be captured using an image sensor and the passenger's health condition may be inferred from the facial expression captured in the image. Furthermore, the passenger may be spoken to by an automated voice and the passenger's health condition may be inferred based on the passenger's responses. The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by an occupant, a function that recognizes the occupant's face with a sensor and provides content suitable for the occupant via the AV device, etc.

[0157] The console display 102 can be used to display, for example, life log information. The console display 102 is disposed near a shift lever 111 on a center console 110 between a driver's seat 108 and a passenger seat 109. Information detected by various sensors can also be displayed on the console display 102. In addition, the console display 102 may display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0158] The head-up display 103 is virtually displayed behind the windshield 112 in front of the driver's seat 108. The head-up display 103 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 103 is often virtually located in front of the driver's seat 108, it is suitable for displaying information directly related to the operation of the vehicle 100, such as the speed of the vehicle 100 and the remaining fuel (battery) level.

[0159] The digital rearview mirror 104 can not only display the rear of the vehicle 100 but also display the status of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 104, it can be used to display life log information, for example.

[0160] The steering wheel display 105 is disposed near the center of the steering wheel 113 of the vehicle 100. The steering wheel display 105 can be used to display at least one of, for example, safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 105 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information regarding the operation of AV equipment, air conditioning equipment, etc.

[0161] The rear entertainment display 106 is attached to the back side of the driver's seat 108 and the passenger seat 109 and is intended for viewing by rear seat passengers. The rear entertainment display 106 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 106 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 106. For example, the rear entertainment display 106 may display information related to the operation of an AV device or an air conditioning system, or may display the results of measurements such as the body temperature of the rear seat passengers using a temperature sensor.

[0162] As described above, by arranging a sensor on the rear side of the display device 1, the distance to surrounding objects can be measured. Optical distance measurement methods are broadly divided into passive and active types. Passive types measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive types include the lens focusing method, the stereo method, and the monocular vision method. Active types measure distance by projecting light onto an object and receiving reflected light from the object with a sensor. Active types include the optical radar method, the active stereo method, the photometric stereo method, the moire topography method, and the interferometry method. The display device 1 according to the present disclosure can be applied to any of these distance measurement methods. By using a sensor arranged on the rear side of the display device 1 according to the present disclosure, the above-mentioned passive or active distance measurement can be performed.

[0163] Second Application Example The display device 1 according to the present disclosure is not only applicable to various displays used in vehicles, but also to displays mounted on various electronic devices.

[0164] Fig. 22A is a front view of a digital camera 120 that is a second application example of the electronic device, and Fig. 22B is a rear view of the digital camera 120. The digital camera 120 in Fig. 22A and Fig. 22B shows an example of a single-lens reflex camera with an interchangeable lens 121, but the digital camera 120 can also be applied to a camera in which the lens 121 cannot be interchangeable.

[0165] 22A and 22B, when the photographer holds the grip 123 of the camera body 122, looks through the electronic viewfinder 124, decides on the composition of the shot, adjusts the focus, and presses the shutter 125, the photographed data is saved in the camera's internal memory. As shown in Fig. 22B, the rear side of the camera is provided with a monitor screen 126 that displays photographed data, live images, etc., and the electronic viewfinder 124. In addition, a sub-screen that displays setting information such as shutter speed and exposure value may be provided on the top surface of the camera.

[0166] By arranging a sensor on the back side of a monitor screen 126, an electronic viewfinder 124, a sub-screen, or the like used in a camera, it can be used as a display device 1 according to the present disclosure.

[0167] (Third Application Example) The display device 1 according to the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The HMD can be used for virtual reality (VR), augmented reality (AR), mixed reality (MR), substitutional reality (SR), or the like.

[0168] Fig. 23A is an external view of an HMD 130, which is a third application example of an electronic device. The HMD 130 in Fig. 23A has a mounting member 131 for being worn over a person's eyes. This mounting member 131 is secured by hooking it onto a person's ear, for example. A display device 132 is provided inside the HMD 130, and the wearer of the HMD 130 can view a 3D image or the like on this display device 132. The HMD 130 is equipped with, for example, a wireless communication function and an acceleration sensor, and can switch the 3D image or the like displayed on the display device 132 according to the wearer's posture, gestures, etc.

[0169] Alternatively, a camera may be provided in the HMD 130 to capture an image of the wearer's surroundings, and an image obtained by combining the image captured by the camera with an image generated by a computer may be displayed on the display device 132. For example, a camera may be placed on the back side of the display device 132 that is viewed by the wearer of the HMD 130, and the camera may capture an image of the area around the wearer's eyes. The captured image may then be displayed on another display provided on the outer surface of the HMD 130, allowing people around the wearer to grasp the wearer's facial expressions and eye movements in real time.

[0170] Various types of HMDs 130 are possible. For example, as shown in FIG. 23B , the display device 1 according to the present disclosure can also be applied to smart glasses 130a that display various information on glasses 134. The smart glasses 130a in FIG. 23B include a main body 135, an arm 136, and a lens barrel 137. The main body 135 is connected to the arm 136. The main body 135 is detachable from the glasses 134. The main body 135 incorporates a control board and a display unit for controlling the operation of the smart glasses 130a. The main body 135 and the lens barrel 137 are connected to each other via the arm 136. The lens barrel 137 emits image light emitted from the main body 135 via the arm 136 toward the lenses 138 of the glasses 134. This image light enters the human eye through the lens 138. A wearer of the smart glasses 130a in FIG. 23B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel 137, just like with regular glasses.

[0171] (Fourth Application Example) The display device 1 according to the present disclosure can also be applied to a television device (hereinafter referred to as a TV). Recent TVs tend to have as small a frame as possible from the viewpoints of miniaturization and design. For this reason, when a camera for photographing viewers is installed in a TV, it is desirable to place the camera on the back side of the TV's display panel.

[0172] Fig. 24 is an external view of a TV 140, which is a fourth application example of an electronic device. The TV 140 in Fig. 24 has a minimized frame, and almost the entire front side is the display area. The TV 140 may have a built-in sensor such as a camera for capturing images of viewers.

[0173] (Fifth Application Example) The display device 1 according to the present disclosure can also be applied to smartphones and mobile phones. FIG. 25 is an external view of a smartphone 150, which is a fifth application example of an electronic device. In the example of FIG. 25 , the display surface 1z extends to nearly the outer size of the electronic device, and the width of the bezel 1y surrounding the display surface 1z is set to a few millimeters or less. Typically, a front camera is often mounted on the bezel 1y. However, in FIG. 25 , as shown by the dashed line, an image sensor module functioning as a front camera is disposed on the rear side of the display surface 1z, for example, approximately in the center. By providing the front camera on the rear side of the display surface 1z in this way, there is no need to place the front camera in the bezel 1y, and the width of the bezel 1y can be narrowed.

[0174] The present technology may be configured as follows: (1) A display device including: a pixel array unit having a plurality of pixels arranged in a first direction and a second direction intersecting each other; and a plurality of drive circuits configured to drive a plurality of pixel regions arranged in the pixel array unit and each including two or more pixels, using two or more drive methods. (2) The display device according to (1), wherein the plurality of pixel regions include two or more pixel regions that differ in at least one of display mode, arrangement, shape, or size. (3) The display device according to (1) or (2), wherein the plurality of pixel regions include one or more first pixel regions having two or more of the pixels arranged along a third direction and a fourth direction intersecting each other, wherein the third direction is the same as or different from the first direction, and the fourth direction is the same as or different from the second direction, and the drive circuit that drives the first pixel region drives the two or more pixels in the first pixel region along the third direction and the fourth direction. (4) The display device according to (3), wherein the plurality of pixel regions includes a second pixel region having two or more of the pixels arranged along the first direction and the second direction, and the drive circuit that drives the second pixel region drives the two or more pixels in the second pixel region along the first direction and the second direction. (5) The display device according to (4), wherein the first pixel region is arranged in the center of the pixel array unit, and the second pixel region is arranged around the first pixel region. (6) The display device according to (5), wherein a plurality of the first pixel regions are arranged near the center of the pixel array unit, and the plurality of first pixel regions differ from each other in at least one of shape, size, and orientation. (7) The display device described in (6), wherein the third direction in each of the plurality of first pixel regions is different, the fourth direction in each of the plurality of first pixel regions is different, and the plurality of drive circuits that drive the plurality of first pixel regions change at least one of the drive order or drive direction of the two or more pixels included in the plurality of first pixel regions for each of the first pixel regions.(8) The display device according to (7), wherein three of the plurality of first pixel regions are arranged at an angle of 60 degrees, one of the plurality of first pixel regions different from the three first pixel regions is arranged in a location surrounded by the three first pixel regions, and each of the plurality of drive circuits that drive the plurality of first pixel regions drives the two or more pixels included in the corresponding first pixel region along the longitudinal direction and the lateral direction of the corresponding first pixel region. (9) The display device according to any one of (4) to (8), further comprising a pixel correction unit that corrects a display mode of the second pixel region to a display mode different from that of the first pixel region. (10) The display device according to (9), wherein the pixel correction unit makes at least one of resolution, luminance, chromaticity, or display update cycle different between the first pixel region and the second pixel region. (11) The display device according to (10), wherein the pixel correction unit reduces the luminance of the second pixel region to be lower than that of the first pixel region. (12) The display device according to (11), wherein, when a pixel having a higher brightness than surrounding pixels is present in the second pixel region, the pixel correction unit reduces the brightness of the surrounding pixels without reducing the brightness of the pixel with the higher brightness. (13) The display device according to any one of (10) to (12), wherein, in the second pixel region, the pixel correction unit performs a binning process of writing the same pixel signal to a pixel group including two or more adjacent pixels. (14) The display device according to (13), wherein the pixel correction unit adjusts the brightness of the two or more pixels included in the pixel group so that a brightness difference between a maximum brightness and an average brightness of the two or more pixels included in the pixel group is equal to or greater than a predetermined threshold. (15) The display device according to (13), wherein the pixel correction unit adjusts the chromaticity of the two or more pixels so that a maximum value of a difference between an average chromaticity of the two or more pixels included in the pixel group and the chromaticity of each pixel is equal to or greater than a predetermined threshold.(16) The display device described in any one of (4) to (15), wherein the drive circuit that drives the first pixel region alternately performs a first display drive in which the first pixel region is divided into a plurality of pixel groups, each including two or more of the pixels, and a pixel signal is supplied to each of the pixel groups, and a second display drive in which the first pixel region is divided into a new plurality of pixel groups, each shifted by one pixel in the third direction and the fourth direction, and a pixel signal different from that of the first display drive is supplied to each of the pixel groups; and the drive circuit that drives the second pixel region divides the second pixel region into a plurality of pixel groups and supplies a pixel signal to each of the pixel groups, without distinguishing between the first display drive and the second display drive. (17) The drive circuit that drives the first pixel region sequentially repeats the following operations: a first display drive in which the first pixel region is divided into a plurality of pixel groups each including two or more of the pixels and a pixel signal is supplied to each of the pixel groups; a second display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the third direction with respect to the first display drive and a pixel signal different from that of the first display drive is supplied to each of the pixel groups; a third display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the fourth direction with respect to the first display drive and a pixel signal different from that of the second display drive is supplied to each of the pixel groups; and a fourth display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel each in the third direction and the fourth direction with respect to the first display drive and a pixel signal different from that of the third display drive is supplied to each of the pixel groups. The display device according to any one of (4) to (15), wherein the drive circuit that drives the second pixel region divides the second pixel region into a plurality of pixel groups and supplies a pixel signal to each of the pixel groups, regardless of the first to fourth display drives.(18) The display device according to any one of (3) to (17), comprising: a first substrate on which the pixel array unit is arranged; and a second substrate stacked on the first substrate and having the plurality of drive circuits, wherein each of the plurality of drive circuits is arranged to overlap at least a portion of the corresponding pixel region when the first substrate and the second substrate are viewed in plan. (19) The display device according to (18), comprising: an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of pixel selection circuits provided corresponding to the plurality of drive circuits, wherein each of the plurality of pixel selection circuits supplies a drive signal output from the corresponding drive circuit to one or more pixels selected from the corresponding pixel region. (20) The display device according to (18), comprising: an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of region selection circuits provided corresponding to the plurality of drive circuits, wherein each of the plurality of region selection circuits selects one or more of the plurality of pixel regions and / or makes minor adjustments to the shape or size of the selected pixel region based on the drive signal output from the corresponding drive circuit.

[0175] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0176] 1 Display device, 1y Bezel, 1z Display surface, 2 Host device, 3 Display system, 4 Display unit, 4a Pixel array unit, 4b Pixel circuit, 5 Drive circuit, 6 Pixel correction unit, 7 Gate driver, 7a Gate logic unit, 7b Gate analog unit, 8 Source driver, 8a Source logic unit, 8b Source analog unit, 9 Timing controller, 10 Memory unit, 11 I / F circuit, 12 Display controller, 13 Clock generator, 14 Timing generator, 15 Image processing unit, 16 Image I / F unit, 17 Clock control unit, 18 H / V synchronization unit, 19 Data S / P conversion unit, 20 Pad unit, 21 First substrate, 22 Second substrate, 23 Intermediate substrate, 23a Intermediate substrate, 24 Pixel selection circuit, 25 Area selection circuit, 26 Pancake lens, 27 Human eye, 28 Third substrate, 29 Fourth substrate, 31 Semiconductor material layer, 32 Interlayer insulating layer, 33 Pad electrode, 34 Transistor, 35 Wiring layer, 36 Second connection electrode, 40 First control unit, 41 Semiconductor material layer, 42 Interlayer insulating layer, 43 Wiring layer, 44 First connection electrode, 45 Insulating layer, 46 First electrode, 47 Organic layer, 48 Second electrode, 49 Protective film, 50 Color filter, 51 Microlens, 52 Sealing resin layer, 53 Counter substrate, 54 Contact, 55 Pad opening, 61 Second control unit, 62 Signal line, 63 Signal line, 100 Vehicle, 101 Center display, 102 Console display, 103 Head-up display, 104 Digital rearview mirror, 105 Steering wheel display, 106 Rear entertainment display, 107 Dashboard, 108 Driver's seat, 109 Passenger seat, 110 Center console, 111 Shift lever, 112 Windshield, 113 Handle, 120 Digital camera, 121 Lens, 122 Camera body, 123 Grip, 124 Electronic viewfinder, 125 Shutter, 126 Monitor screen, 130a Smart glasses, 131 Mounting member, 132 Display device, 134 Glasses, 135 Main body, 136 Arm, 137 Lens barrel, 138 Lens, 150 Smartphone

Claims

1. A display device comprising: a pixel array section having a plurality of pixels arranged in a first direction and a second direction that intersect with each other; and a plurality of drive circuits arranged in the pixel array section and driving a plurality of pixel regions each including two or more pixels using two or more drive methods.

2. The display device according to claim 1, wherein the plurality of pixel regions include two or more pixel regions that differ in at least one of display mode, arrangement, shape, or size.

3. The display device of claim 1, wherein the plurality of pixel regions have one or more first pixel regions each having two or more of the pixels arranged along a third direction and a fourth direction that intersect with each other, the third direction being the same as or different from the first direction, the fourth direction being the same as or different from the second direction, and the drive circuit that drives the first pixel region drives the two or more pixels in the first pixel region along the third direction and the fourth direction.

4. The display device according to claim 3, wherein the plurality of pixel regions include a second pixel region having two or more of the pixels arranged along the first direction and the second direction, and the drive circuit that drives the second pixel region drives the two or more pixels in the second pixel region along the first direction and the second direction.

5. The display device according to claim 4, wherein the first pixel region is disposed in the central portion of the pixel array portion, and the second pixel region is disposed around the first pixel region.

6. The display device according to claim 5, wherein a plurality of the first pixel regions are arranged near the center of the pixel array section, and each of the plurality of first pixel regions differs in at least one of shape, size, and orientation.

7. The display device according to claim 6, wherein the third direction in each of the plurality of first pixel regions is different, the fourth direction in each of the plurality of first pixel regions is different, and the plurality of drive circuits that drive the plurality of first pixel regions change at least one of the drive order or drive direction of the two or more pixels included in the plurality of first pixel regions for each of the first pixel regions.

8. The display device according to claim 7, wherein three of the plurality of first pixel regions are arranged at an angle of 60 degrees each, one of the plurality of first pixel regions different from the three first pixel regions is arranged in a location surrounded by the three first pixel regions, and each of the plurality of drive circuits that drive the plurality of first pixel regions drives the two or more pixels included in the corresponding first pixel region along the longitudinal direction and lateral direction of the corresponding first pixel region.

9. The display device according to claim 4, further comprising a pixel correction section that corrects the display mode of the second pixel region to a display mode different from that of the first pixel region.

10. The display device according to claim 9, wherein the pixel correction section makes at least one of resolution, luminance, chromaticity, or display update cycle different between the first pixel region and the second pixel region.

11. The display device according to claim 10, wherein the pixel correction section reduces the luminance of the second pixel region to be lower than that of the first pixel region.

12. The display device according to claim 11, wherein, when a pixel in the second pixel region has a higher brightness than surrounding pixels, the pixel correction unit reduces the brightness of the surrounding pixels without reducing the brightness of the pixel with the higher brightness.

13. The display device according to claim 10, wherein the pixel correction section performs a binning process in the second pixel region, writing the same pixel signal to a pixel group including two or more adjacent pixels.

14. The display device according to claim 13, wherein the pixel correction unit adjusts the luminance of the two or more pixels included in the pixel group so that the luminance difference between the maximum luminance and the average luminance of the two or more pixels included in the pixel group is equal to or greater than a predetermined threshold value.

15. The display device according to claim 13, wherein the pixel correction unit adjusts the chromaticity of the two or more pixels included in the pixel group so that the maximum value of the difference between the average chromaticity of the two or more pixels and the chromaticity of each pixel is equal to or greater than a predetermined threshold value.

16. The display device according to claim 4, wherein the drive circuit that drives the first pixel region alternately performs a first display drive in which the first pixel region is divided into a plurality of pixel groups, each including two or more of the pixels, and a pixel signal is supplied to each of the pixel groups, and a second display drive in which the first pixel region is divided into a new plurality of pixel groups, each shifted by one pixel in the third direction and the fourth direction, and a pixel signal different from that of the first display drive is supplied to each of the pixel groups; and the drive circuit that drives the second pixel region divides the second pixel region into a plurality of pixel groups and supplies a pixel signal to each of the pixel groups, without distinguishing between the first display drive and the second display drive.

17. The drive circuit that drives the first pixel region sequentially repeats the following operations: a first display drive in which the first pixel region is divided into a plurality of pixel groups each including two or more of the pixels and a pixel signal is supplied to each of the pixel groups; a second display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the third direction relative to the first display drive and a pixel signal different from that in the first display drive is supplied to each of the pixel groups; a third display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel in the fourth direction relative to the first display drive and a pixel signal different from that in the second display drive is supplied to each of the pixel groups; and a fourth display drive in which the first pixel region is divided into new plurality of pixel groups in a state where the first pixel region is shifted by one pixel each in the third direction and the fourth direction relative to the first display drive and a pixel signal different from that in the third display drive is supplied to each of the pixel groups; 5. The display device according to claim 4, wherein the drive circuit that drives the second pixel region divides the second pixel region into a plurality of pixel groups and supplies a pixel signal to each of the pixel groups, regardless of whether the first display drive is performed or the fourth display drive.

18. A display device according to claim 3, comprising: a first substrate on which the pixel array section is arranged; and a second substrate stacked on the first substrate and having the plurality of drive circuits, wherein each of the plurality of drive circuits is arranged so as to overlap at least a portion with the corresponding pixel region when the first substrate and the second substrate are viewed in a plane.

19. The display device according to claim 18, further comprising an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of pixel selection circuits provided corresponding to the plurality of drive circuits, each of the plurality of pixel selection circuits supplying a drive signal output from the corresponding drive circuit to one or more pixels selected from the corresponding pixel region.

20. A display device as described in claim 18, further comprising an intermediate substrate stacked between the first substrate and the second substrate and having a plurality of area selection circuits provided corresponding to the plurality of drive circuits, each of the plurality of area selection circuits selecting one or more of the plurality of pixel areas and / or making minor adjustments to the shape or size of the selected pixel area based on a drive signal output from the corresponding drive circuit.

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