Display device

Abstract

[Problem] To suppress flickering. [Solution] This display device comprises light-emitting elements, a pixel array, and a control circuit. In the pixel array, the light-emitting elements are arranged in a two-dimensional array. When switching to a second frame rate occurs during light emission of the light-emitting elements belonging to the pixel array at a first frame rate, the control circuit controls extinction at a first frequency corresponding to the first frame rate until the light emission at the first frame rate is completed across the pixel array, and controls extinction at a second frequency corresponding to the second frame rate after the light emission at the first frame rate is completed.

Description

display device

[0001] The present disclosure relates to a display device.

[0002] The frame rate of a display device may change even when displaying a series of images due to the input data reception environment, mounting conditions, and other reasons. If the frame rate changes while the light-emitting element is emitting light, the light-emitting time will vary, and there is a high probability that flicker will occur on the screen.

[0003] Patent Publication No. 2021-076828

[0004] Therefore, one of the non-limiting problems that the embodiments of the present disclosure aim to solve is to suppress variations in light emission time when switching frame rates. As some further non-limiting examples, the problems that the embodiments of the present disclosure aim to solve can also be problems corresponding to the effects described in the embodiments. In other words, the problems that the present disclosure aims to solve can be problems corresponding to at least one of the effects described in the description of the embodiments of the present disclosure.

[0005] According to one embodiment, a display device includes a light-emitting element, a pixel array, and a control circuit. The pixel array has the light-emitting elements arranged in a two-dimensional array. When a switch to a second frame rate occurs while the light-emitting elements belonging to the pixel array are emitting light at a first frame rate, the control circuit controls the light to be extinguished at a first frequency corresponding to the first frame rate until light emission at the first frame rate is completed across the pixel array, and controls the light to be extinguished at a second frequency corresponding to the second frame rate after light emission at the first frame rate is completed.

[0006] The control circuit may perform control for each frame so that the light emitting elements belonging to the pixel array have equal light emitting times.

[0007] The control circuit may output, via a control line, a signal for controlling the timing at which each of the light-emitting elements in the pixel array emits light and a signal for controlling the timing at which each of the light-emitting elements turns off light.

[0008] The control circuit may control a power supply line connected to each of the light emitting elements of the pixel array at a timing to emit light and a timing to extinguish light.

[0009] When the frame rate is switched, the control circuit may detect that the light-emitting elements belonging to the pixel array have completed lighting and extinguishing for the final line, and switch the frequency at which the light-emitting elements are driven.

[0010] The control circuit may control light emission at the second frequency after the timing at which the frame rate is switched.

[0011] The control circuit may include a first logic circuit that performs extinction control at the first frame rate and a second logic circuit that performs extinction control at the second frame rate, and may select the first logic circuit or the second logic circuit for each frame and output a signal that performs extinction control.

[0012] When the pixel array includes light-emitting elements that emit light at the same timing for each block, the control circuit may control the light emission drive frequency and the extinction drive frequency for each block.

[0013] 1 is a block diagram schematically showing an example of a display device according to an embodiment. FIG. 1 is a diagram schematically showing an example of light emission and quenching of a display device according to an embodiment. FIG. 2 is a block diagram schematically showing an example of a display device according to an embodiment. FIG. 3 is a block diagram schematically showing an example of a display device according to an embodiment. FIG. 4 is a diagram schematically showing an example of light emission and quenching of a display device according to an embodiment. FIG. 5 is a diagram schematically showing an example of light emission and quenching of a display device according to an embodiment. FIG. 6 is a diagram schematically showing an example of light emission and quenching of a display device according to an embodiment. FIG. 7 is a circuit diagram schematically showing an example of a pixel according to an embodiment. FIG. 8 is a circuit diagram schematically showing an example of a pixel according to an embodiment. FIG. 9 is a circuit diagram schematically showing an example of a pixel according to an embodiment. FIG. 10 is a circuit diagram schematically showing an example of a pixel according to an embodiment. FIG. 11 is a circuit diagram schematically showing an example of a pixel according to an embodiment. FIG. 12 is a circuit diagram schematically showing an example of a pixel according to an embodiment. 1 is a diagram showing the interior of a vehicle from diagonally rear to diagonally front of the vehicle; a front view of a digital camera which is a second application example of the electronic device; a rear view of the digital camera; an external view of an HMD which is a third application example of the electronic device; an external view of smart glasses; an external view of a TV which is a fourth application example of the electronic device; and an external view of a smartphone which is a fifth application example of the electronic device.

[0014] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. The drawings are used for explanation purposes, and the shape, size, and size ratio of each component in an actual device do not necessarily have to be the same as those shown in the drawings. Furthermore, since the drawings are simplified, components necessary for implementation other than those shown in the drawings are also assumed to be appropriately provided.

[0015] 1 is a block diagram schematically illustrating an example of a display device according to an embodiment. The display device 1 includes a pixel array 10, a control circuit 12, a vertical scanning circuit 14, and a horizontal driving circuit 16. The display device 1 appropriately processes and displays input image information (including video information; the same applies hereinafter). The display device 1 also includes other necessary components, such as an interface for receiving the image information and a power supply for supplying power to each of the components.

[0016] The pixel array 10 is an area where pixels having light-emitting elements that emit light to display image information are arranged in the display device 1. The pixel array 10 has pixels arranged in a two-dimensional array in a first direction (e.g., a line direction) and a second direction (e.g., a column direction) that intersects with the first direction, forming a display area that displays an input image.

[0017] The first and second directions are given for convenience of explanation, and the embodiments of the present disclosure are not limited to these directions. For example, the first direction may be the column direction and the second direction may be the line direction, or they may be defined in other ways.

[0018] The pixel array 10 may form a display area using all pixels arranged therein, or may form a display area using pixels belonging to a predetermined region among the arranged pixels. The pixels located near the periphery of the pixel array 10 may be, for example, dummy pixels, and in this case, the display area can be formed by the pixels excluding these dummy pixels.

[0019] The control circuit 12 is a circuit that appropriately processes input image information, distributes the information appropriately to the light-emitting elements belonging to the pixel array 10, and controls the emission and extinction of these light-emitting elements. The control circuit 12 controls the emission and extinction of light, for example, by outputting appropriate drive signals to the vertical scanning circuit 14 and the horizontal drive circuit 16.

[0020] The vertical scanning circuit 14 selects a line in the pixel array 10 and outputs a signal for driving the light emitting elements for each line. The vertical scanning circuit 14 outputs a control signal to the pixels belonging to each line of the pixel array 10 via a control line 140.

[0021] The horizontal drive circuit 16 selects a column in the pixel array 10 and outputs, for each column, a signal containing information such as the light emission intensity of the light-emitting element in the line selected by the vertical scanning circuit 14. The horizontal drive circuit 16 outputs a control signal to the pixels belonging to each column of the pixel array 10 via a control line 160.

[0022] The vertical scanning circuit 14 and horizontal driving circuit 16 work together to cause the pixels located at their respective positions to emit light containing appropriate intensity and color information, resulting in a display based on the input image information in the display area.

[0023] In the present disclosure, an example will be described in which the frame rate is switched midway through display on the display device 1. Below, an example will be described in which the frame rate is switched from a first frame rate driven at a first frequency to a second frame rate driven at a second frequency. The height of the first frequency and the second frequency is not predetermined, and the first frequency may be higher than the second frequency (the first frame rate is a higher frame rate), or conversely, the second frequency may be higher than the first frequency (the second frame rate is a higher frame rate).

[0024] When the light emission of the light-emitting elements in the pixel array 10 is switched to the second frame rate while the elements are emitting light at the first frame rate, the control circuit 12 controls the extinction at the first frequency until the light emission and extinction processes at the first frame rate are completed, and then controls the extinction at the second frequency after the completion of the processes. By controlling in this manner, the timing of the extinction is shifted, and the period from light emission to extinction of each pixel in the pixel array 10 is made uniform, thereby preventing screen flicker.

[0025] 2 is a diagram showing an example of the display timing of the display device 1 when switching from a high frame rate to a low frame rate, where the horizontal axis indicates time and the vertical axis indicates the line scanning direction.

[0026] The timings of light emission and extinction are shown as straight lines, for example. The straight lines indicating light emission indicate that light emission control is performed on the line corresponding to the vertical axis at this timing, and the straight lines indicating extinction indicate that extinction control is performed on the line corresponding to the vertical axis at this timing. In other words, between the light emission timing and the extinction timing, the light-emitting elements belonging to each line emit light, displaying image information within the display area.

[0027] As shown in the figure, when the frame rate is switched from a high state to a low state at a certain timing and the driving clock frequency is lowered, there is a possibility that the timing of extinction will be delayed for the lines that have already been emitting light from that timing but have not yet been extinguished, as shown by the dotted lines. To eliminate such delays, the control circuit 12 controls the clock frequency for the extinction timing so that it does not change from before the frame rate was switched.

[0028] As another example, Figure 3 shows the display timing of the display device 1 when switching from a low frame rate to a high frame rate. Contrary to Figure 2, if a line that is emitting light but not yet extinguished at the time the frame rate is switched is controlled using a higher clock frequency after the switch, the time until extinguishing may be shortened, as shown by the dotted line. To prevent this extinguishing timing from becoming earlier, the control circuit 12 controls the clock frequency for the extinguishing timing so that it does not change from before the frame rate switch, as described above.

[0029] As can be seen with reference to Figures 2 and 3, the control circuit 12 controls the light emitting periods to be of equal length in the frame, i.e., to have equal light emitting times across the light emitting elements belonging to the pixel array 10 for each frame.

[0030] 4 is a block diagram showing in more detail a display device according to one embodiment, particularly circuits from the control circuit 12 to the vertical scanning circuit 14. The vertical scanning circuit 14 can include, by way of example and not limitation, a write / light-emission control unit 142, a CLK control unit 144, a light-off control unit 146, and a transfer detection unit 148.

[0031] The writing / light-emission control unit 142 is a driving circuit for controlling the writing of pixel values ​​and light emission on a selected line via the horizontal driving circuit 16. For pixels belonging to a line selected and driven by the writing / light-emission control unit 142, a signal indicating an appropriate pixel value is input from the horizontal driving circuit 16, and the light-emitting element in the pixel is controlled to emit light at an appropriate timing.

[0032] The CLK control unit 144 is a circuit that controls the clock frequency and outputs a clock signal that drives the extinction control unit 146 .

[0033] The extinction control unit 146 is a circuit that controls the extinction of pixels that belong to a selected line. For a line whose light emission is controlled by the writing / light-emission control unit 142, the extinction control unit 146 controls the extinction, thereby extinguishing the light-emitting elements of the pixels that belong to that line.

[0034] Transfer detection unit 148 is a circuit that detects whether extinction control has been completed up to the last line. When extinction of all lines in the light emitting area is completed, transfer detection unit 148 outputs a signal to CLK control unit 144 indicating that signal transfer has been completed.

[0035] For example, when a request to switch the frame rate is made in the middle of a frame, the control circuit 12 outputs a clock signal having the second frequency as the clock frequency after the timing at which the request to switch the frame rate is made to the writing / light-emitting control unit 142. By this control, the writing / light-emitting control unit 142 starts clock control using the second frequency, i.e., processing at the second frame rate after switching.

[0036] On the other hand, the control circuit 12 outputs, at the same timing, a clock signal having the first frequency as the clock frequency to the CLK control unit 144 via the CLK control unit 144 until the transfer of the final line is completed. After receiving a signal from the transfer detection unit 148 indicating that the transfer up to the final line has been completed, the CLK control unit 144 switches the clock frequency of the extinction control unit 146 to the second frequency.

[0037] By controlling in this way, even when the frame rate is switched at a timing when there is a line that is currently emitting light, the light will be driven at the first frame rate before the switch until it is turned off, and after the final line has been turned off, all control including the turning off of the light will be driven at the second frame rate after the switch.

[0038] By using this control, even if the frame rate is switched midway through a frame, it is possible to execute the extinction control at the clock frequency before the switch, and it is possible to maintain an equal time from light emission to extinction for each line.

[0039] Although not shown in the figure, the vertical scanning circuit 14 can output signals via an analog circuit after the processing of the writing / light emitting control unit 142 and the CLK control unit 144. In other words, the vertical scanning circuit 14 can further have an analog circuit for output.

[0040] The vertical scanning circuit 14 can write to each pixel at the appropriate timing via a control line 140 that outputs a control signal and output a drive signal for controlling light emission and transfer. As another example, the vertical scanning circuit 14 can apply signals corresponding to the light emission timing and extinction timing to a power supply line instead of a control line. In this way, the control circuit 12 can control the driving of the pixels via the vertical scanning circuit 14, or can control the driving of the pixels by turning the power supply line on and off.

[0041] 5 is a diagram showing another non-limiting example of the control circuit 12 and vertical scanning circuit 14. The vertical scanning circuit 14 may include two first quenching control units 150 and a second quenching control unit 152 instead of the above-described quenching control unit 146. In other words, the vertical scanning circuit 14 may have a configuration different from that shown in FIG. 4, and may be configured without the above-described CLK control unit 144 or transfer detection unit 148, for example.

[0042] The control circuit 12 can also perform pixel extinction control by switching, for each frame, between a first extinction control unit 150 that performs extinction control at a first frame rate and a second extinction control unit 152 that performs extinction control at a second frame rate.

[0043] The first quenching control unit 150 and the second quenching control unit 152 may both be configured as logic circuits. When the frame rate is switched between frames, the control circuit 12 switches the frame rate of the writing and light-emitting control output to the writing / light-emitting control unit 142 from the subsequent timing, while switching the clock signal related to the quenching control for each frame.

[0044] The control circuit 12 can select, for each frame, either the first quenching control unit 150 that uses the first frequency as the clock frequency or the second quenching control unit 152 that uses the second frequency as the clock frequency, and perform quenching control via the selected circuit.

[0045] By selecting a frame rate for each frame, even if the frame rate is switched during frame processing, the extinction control continues to be executed at the frame rate before the switch. As a result, it is possible to equalize the light-emitting duration of light-emitting elements within the same frame, as in the case of Figure 4, and similarly to reduce screen flickering, etc.

[0046] 6 is a diagram showing another example of the timing of light emission and extinction according to an embodiment. As shown in this diagram, the frame rate that can be switched is not limited to two types, and even when switching occurs between frame rates that are driven at three or more different frequencies, extinction control can be similarly driven at the frame rate before switching.

[0047] 7 is a diagram showing another example of the timing of turning on and off the light according to an embodiment. As shown in this diagram, the light emission duty ratio does not have to be 50%. For example, as shown in FIG. 7, in the case of a duty ratio higher than 50%, or even in the case of a duty ratio lower than 50%, which is not shown in the diagram, it is possible to suppress screen flickering and the like by performing the same process.

[0048] FIG. 8 is a diagram showing another example of the timing of light emission and extinction according to an embodiment. Depending on its configuration, the display device 1 may control light emission and extinction at the same timing for each block, which groups together multiple lines. Of course, the method disclosed herein can also operate in the same way when such block control is performed. By outputting an appropriate control signal from the vertical scanning circuit 14 via the control line 140, as shown in FIG. 8, it is possible to suppress variations in light emission time and thus flicker, even when block control is realized.

[0049] FIG. 9 is a diagram showing another example of the timing of light emission and extinction according to one embodiment. In addition to the above, the display device 1 may output on a line-by-line basis in a predetermined area. Also, blocks of various sizes may be mixed. As shown in FIG. 9, the operation of the present disclosure can be performed in such a case as well. In this case, it is also possible to suppress variations in light emission time and thereby suppress flickering.

[0050] As described above, according to this embodiment, even if the frame rate is switched during frame processing, it is possible to appropriately suppress variations in light emission time and suppress flickering on the screen.

[0051] Next, several examples of pixel circuits will be described. The techniques of the present disclosure can also be applied to the pixel circuits shown below as non-limiting examples. The pixel array 10 includes pixels 100 each having a light-emitting element L arranged in a two-dimensional array.

[0052] 10 shows an example of the configuration of a pixel 100. The pixel 100 has a capacitor C01, transistors MN02 and MN03, and a light-emitting element L.

[0053] The transistors MN02 and MN03 are n-type MOSFETs. The gate of the transistor MN02 is connected to the control line WS, the drain is connected to the control line SIG, and the source is connected to the gate of the transistor MN03 and the capacitor C01.

[0054] One end of the capacitor C01 is connected to the source of the transistor MN02 and the gate of the transistor MN03, and the other end is connected to the source of the transistor MN03 and the anode of the light-emitting element L.

[0055] The gate of the transistor MN03 is connected to the source of the transistor MN02 and one end of the capacitor C01, the drain is connected to the power supply line VCCP, and the source is connected to the other end of the capacitor C01 and the anode of the light-emitting element L.

[0056] The light-emitting element L is, for example, an organic EL light-emitting element, and its anode is connected to the source of the transistor MN03 and the other end of the capacitor C01, and its cathode is connected to the power supply line Vcath. The voltage of the power supply line VCCP is switched between a first voltage and a second voltage lower than the first voltage as appropriate.

[0057] With this configuration, in pixel 100, transistor MN02 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C01 is set based on the pixel signal supplied from control line SIG. While the voltage of power supply line VCCP is at the first voltage, transistor MN03 passes a current corresponding to the voltage across capacitor C01 through light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MN03. In this way, pixel 100 emits light at a brightness corresponding to the pixel signal.

[0058] During the period when the voltage of the power supply line VCCP is the second voltage, the light emitting element L is turned off.

[0059] The vertical scanning circuit 14 can perform the above processing on the control line WS as the control line 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0060] 11 shows another example of the configuration of the pixel 100. This pixel 100 has capacitors C11 and C12, transistors MP12 to MP15, and a light-emitting element L.

[0061] Transistors MP12 to MP15 are P-type MOSFETs. The gate of transistor MP12 is connected to control line WS, the source is connected to control line SIG, and the drain is connected to the gate of transistor MP14 and capacitor C12.

[0062] One end of capacitor C11 is connected to the power supply line VCCP, the other end is connected to capacitor C12, the drain of transistor MP13, and the source of transistor MP14, one end of capacitor C12 is connected to the other end of capacitor C11, the drain of transistor MP13, and the source of transistor MP14, and the other end is connected to the drain of transistor MP12 and the gate of transistor MP14.

[0063] The gate of the transistor MP13 is connected to the control line DS, the source is connected to the power supply line VCCP, and the drain is connected to the source of the transistor MP14, the other end of the capacitor C11, and one end of the capacitor C12.

[0064] The gate of transistor MP14 is connected to the drain of transistor MP12 and the other end of capacitor C12, the source is connected to the drain of transistor MP13, the other end of capacitor C11, and one end of capacitor C12, and the drain is connected to the anode of light-emitting element L and the source of transistor MP15.

[0065] The gate of the transistor MP15 is connected to the control line AZ, the source is connected to the drain of the transistor MP14 and the anode of the light-emitting element L, and the drain is connected to the power supply line VSS.

[0066] With this configuration, in pixel 100, transistor MP12 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C12 is set based on the pixel signal supplied from control line SIG. Transistor MP13 is turned on and off based on signal Vds on control line DS. While transistor MP13 is on, transistor MP14 passes a current to light-emitting element L that corresponds to the voltage across capacitor C12.

[0067] The light-emitting element L emits light based on the current supplied from the transistor MP14. In this way, the pixel 100 emits light at a brightness corresponding to the pixel signal. The transistor MP15 turns on and off based on the signal Vaz on the control line AZ. While the transistor MP15 is in the on state, the anode voltage of the light-emitting element L is initialized by being set to the voltage of the power supply line VSS.

[0068] Note that the transistors MP12 to MP15 may be transistors using low temperature polysilicon (LTPS), and at least one of the transistors MP12 and MP15 may be a transistor using an oxide semiconductor.

[0069] In adjacent pixels 100, the nodes Na may be connected to each other via a switch, and the connection state of the nodes Na may be switched. As another example, the nodes Nb may be connected to each other via a switch, and the connection state of the nodes Nb may be switched.

[0070] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines DS and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0071] 12 shows another example of the configuration of the pixel 100. This pixel 100 has a capacitor C21, transistors MN22 to MN25, and a light-emitting element L. In the circuit shown below, the voltage applied to the power supply line VCCP can also be a fixed voltage.

[0072] The transistors MN22 to MN25 are N-type MOSFETs. The gate of the transistor MN22 is connected to the control line WS, the drain is connected to the control line SIG, and the source is connected to the gate of the transistor MN24 and the capacitor C21.

[0073] One end of the capacitor C21 is connected to the source of the transistor MN22 and the gate of the transistor MN24, and the other end is connected to the source of the transistor MN24, the drain of the transistor MN25, and the anode of the light-emitting element L.

[0074] The gate of transistor MN23 is connected to the control line DS, the drain is connected to the power supply line VCCP, and the source is connected to the drain of transistor MN24.

[0075] The gate of transistor MN24 is connected to the source of transistor MN22 and one end of capacitor C21, the drain is connected to the source of transistor MN23, and the source is connected to the other end of capacitor C21, the drain of transistor MN25, and the anode of light-emitting element L.

[0076] The gate of transistor MN25 is connected to control line AZ, the drain is connected to the source of transistor MN24, the other end of capacitor C21 and the anode of light-emitting element L, and the source is connected to power supply line VSS.

[0077] With this configuration, in pixel 100, transistor MN22 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C21 is set based on the pixel signal supplied from control line SIG.

[0078] Transistor MN23 turns on and off based on signal Vds on control line DS. While transistor MN23 is on, transistor MN24 passes a current corresponding to the voltage across capacitor C21 to light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MN24.

[0079] In this way, pixel 100 emits light at a brightness corresponding to the pixel signal. Transistor MN25 is turned on and off based on signal Vaz on control line AZ. While transistor MN25 is in the on state, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0080] Note that the transistors MN22 to MN25 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MN22 and MN25 may be a transistor using an oxide semiconductor.

[0081] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0082] 13 shows another example of the configuration of the pixel 100. This pixel 100 has a capacitor C31, transistors MP32 to MP36, and a light-emitting element L. The transistors MP32 to MP36 are P-type MOSFETs.

[0083] The gate of transistor MP32 is connected to control line WS, the source is connected to control line SIG, and the drain is connected to the gate of transistor MP33, the drain of transistor MP34, and capacitor C31.

[0084] One end of the capacitor C31 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP32, the gate of the transistor MP33, and the drain of the transistor MP34.

[0085] The gate of transistor MP34 is connected to control line AZ1, the source is connected to the drain of transistor MP33 and the source of transistor MP35, and the drain is connected to the drain of transistor MP32, the gate of transistor MP33, and the other end of capacitor C31.

[0086] The gate of the transistor MP35 is connected to the control line DS, the source is connected to the drain of the transistor MP33 and the source of the transistor MP34, and the drain is connected to the source of the transistor MP36 and the anode of the light-emitting element L.

[0087] The gate of the transistor MP36 is connected to the control line AZ2, the source is connected to the drain of the transistor MP35 and the anode of the light-emitting element L, and the drain is connected to the power supply line VSS.

[0088] With this configuration, in pixel 100, transistor MP32 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C31 is set based on the pixel signal supplied from control line SIG.

[0089] The transistor MP35 is turned on and off based on the signal Vds on the control line DS. While the transistor MP35 is in the on state, the transistor MP33 passes a current corresponding to the voltage across the capacitor C31 to the light-emitting element L. The light-emitting element L emits light based on the current supplied from the transistor MP33.

[0090] In this way, pixel 100 emits light at a brightness corresponding to the pixel signal. Transistor MP34 is turned on and off based on signal Vaz1 on control line AZ1. While transistor MP34 is on, the drain and gate of transistor MP33 are connected to each other. Transistor MP36 is turned on and off based on signal Vaz2 on control line AZ2. While transistor MP36 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0091] Note that the transistors MP32 to MP36 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MP32, MP34, and MP36 may be a transistor using an oxide semiconductor.

[0092] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0093] FIG. 14 shows another example of the configuration of the pixel 100.

[0094] One end of the capacitor C48 is connected to the control line SIG1, and the other end is connected to the power supply line VSS.

[0095] One end of the capacitor C49 is connected to the control line SIG1, and the other end is connected to the control line SIG2.

[0096] The transistor MP49 is a P-type MOSFET, with its gate connected to the control line WS2, its source connected to the control line SIG1, and its drain connected to the control line SIG2.

[0097] The pixel 100 includes a capacitor C41, transistors MP42 to MP46, and a light-emitting element L.

[0098] The transistors MP42 to MP46 are P-type MOSFETs. The gate of the transistor MP42 is connected to the control line WS1, the source is connected to the control line SIG2, and the drain is connected to the gate of the transistor MP43 and the capacitor C41.

[0099] One end of the capacitor C41 is connected to the power supply line VCCP, and the other end is connected to the drain of the transistor MP42 and the gate of the transistor MP43.

[0100] The gate of the transistor MP43 is connected to the drain of the transistor MP42 and the other end of the capacitor C41, the source is connected to the power supply line VCCP, and the drain is connected to the sources of the transistors MP44 and MP45.

[0101] The gate of transistor MP44 is connected to control line AZ1, the source is connected to the drain of transistor MP43 and the source of transistor MP45, and the drain is connected to control line SIG2. The gate of transistor MP45 is connected to control line DS, the source is connected to the drain of transistor MP43 and the source of transistor MP44, and the drain is connected to the source of transistor MP46 and the anode of light-emitting element L.

[0102] The gate of the transistor MP46 is connected to the control line AZ2, the source is connected to the drain of the transistor MP45 and the anode of the light-emitting element L, and the drain is connected to the power supply line VSS.

[0103] With this configuration, in pixel 100, transistor MP42 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C41 is set based on the pixel signal supplied from control line SIG1 via capacitor C49.

[0104] Transistor MP45 is turned on and off based on the signal Vds on control line DS. While transistor MP45 is on, transistor MP43 passes a current corresponding to the voltage across capacitor C41 to light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP43.

[0105] In this way, the pixel 100 emits light at a brightness corresponding to the pixel signal. The transistor MP44 is turned on and off based on the signal Vaz1 on the control line AZ1. While the transistor MP44 is in the on state, the drain of the transistor MP43 and the control line SIG2 are connected to each other.

[0106] The transistor MP46 is turned on and off based on the signal Vaz2 on the control line AZ2. During the period when the transistor MP46 is in the on state, the anode voltage of the light-emitting element L is initialized by being set to the voltage of the power supply line VSS.

[0107] Note that the transistors MP42 to MP46 and MP49 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MP42, MP46 and MP49 may be a transistor using an oxide semiconductor.

[0108] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0109] 15 shows another example of the configuration of the pixel 100. A plurality of pixels 100 are arranged in a matrix in a display area 102, and the display area 102 is provided between a first control unit 40 and a second control unit 70.

[0110] The first control unit 40 has transmission gates TG45 and TG46, transistors MP56 and MP57, and a capacitor C61.

[0111] Transistors MP56 and MP57 are P-type MOSFETs.

[0112] A pixel signal is supplied to the input terminal of the transmission gate TG45, and the output terminal of the transmission gate TG45 is connected to one end of the control line 14a.

[0113] The input terminal of the transmission gate TG46 is connected to the control line 14b, and the output terminal of the transmission gate TG46 is connected to the power supply line Vorst.

[0114] One end of the capacitor C61 is connected to the control line 14a, and the other end is connected to the power supply line VSS1.

[0115] The gate of the transistor MP56 is connected to the control line INIL, the source is connected to the power supply line Vini, and the drain is connected to the control line 14b.

[0116] The gate of transistor MP57 is connected to control line ELL, the source is connected to control line Vel, and the drain is connected to control line 14b.

[0117] The second control unit 70 has a transmission gate TG72, a transistor MP73, and a capacitor C82.

[0118] The transistor MP73 is a P-type MOSFET. The input terminal of the transmission gate TG72 is connected to the other end of the control line 14a, and the output terminal is connected to the drain of the transistor MP73 and one end of the capacitor C82.

[0119] The gate of the transistor MP73 is connected to the control line REFL, the source is connected to the power supply line Vref, and the drain is connected to the output terminal of the transmission gate TG72 and one terminal of the capacitor C82.

[0120] One end of the capacitor C82 is connected to the output terminal of the transmission gate TG72 and the drain of the transistor MP73, and the other end is connected to one end of the control line 14b.

[0121] The pixel 100 includes a capacitor C132, transistors MP121 to MP125, and a light-emitting element L.

[0122] The transistors MP121 to MP125 are P-type MOSFETs. The gate of the transistor MP122 is connected to the control line WS, the source is connected to the control line 14b, and the drain is connected to the gate of the transistor MP121 and the capacitor C132.

[0123] One end of the capacitor C132 is connected to the control line Vel, and the other end is connected to the drain of the transistor MP122 and the gate of the transistor MP121.

[0124] The gate of the transistor MP121 is connected to the drain of the transistor MP122 and the other end of the capacitor C132, the source is connected to the control line Vel, and the drain is connected to the sources of the transistors MP123 and MP124.

[0125] The gate of transistor MP123 is connected to control line AZ, the source is connected to the drain of transistor MP121 and the source of transistor MP124, and the drain is connected to control line 14b. The gate of transistor MP124 is connected to control line DS, the source is connected to the drain of transistor MP121 and the source of transistor MP123, and the drain is connected to the drain of transistor MP125 and the anode of light-emitting element L.

[0126] The gate of the transistor MP125 is connected to the control line AZ, the source is connected to the power supply line Vorst, and the drain is connected to the drain of the transistor MP124 and the anode of the light emitting element L.

[0127] With this configuration, in pixel 100, transistor MP122 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C132 is set based on the pixel signal supplied via transmission gate TG45, control line 14a, transmission gate TG72, capacitor C82, and control line 14b.

[0128] Transistor MP124 turns on and off based on the signal Vds on control line DS. While transistor MP124 is on, transistor MP121 passes a current corresponding to the voltage across capacitor C132 to light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP121.

[0129] In this way, the pixel 100 emits light with a brightness according to the pixel signal.

[0130] Transistors MP123 and MP125 are turned on and off based on a signal Vaz on a control line AZ. While transistor MP123 is on, the drain of transistor MP121 and the source of transistor MP124 are connected to control line 14b. While transistor MP125 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of the power supply line Vorst.

[0131] Furthermore, transistor MP56 is turned on and off based on the signal Vinil on the control line INIL, transistor MP57 is turned on and off based on the signal Vell on the control line ELL, and transistor MP73 is turned on and off based on the signal Vrefl on the control line REFL. When transistor MP56 is turned on, control line 14b is set to the voltage of the power supply line Vini, and when transistor MP57 is turned on, control line 14b is set to the voltage of the control line Vel.

[0132] When transistor MP73 is turned on, one end of capacitor C82 is initialized by being set to the voltage of the power supply line Vref.

[0133] The transistors MP121 to MP125, MP56, and MP57 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MP122 and MP125 may be a transistor using an oxide semiconductor.

[0134] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0135] 16 shows another example of the configuration of the pixel 100. This pixel 100 has a capacitor C51, transistors MP52 to MP60, and a light-emitting element L.

[0136] Transistors MP52 to MP60 are P-type MOSFETs. The gate of transistor MP52 is connected to control line WS, the source is connected to control line SIG, and the drain is connected to the drain of transistor MP53 and the source of transistor MP54.

[0137] The gate of the transistor MP53 is connected to the control line DS, the source is connected to the power supply line VCCP, and the drain is connected to the drain of the transistor MP52 and the source of the transistor MP54.

[0138] The gate of transistor MP54 is connected to the source of transistor MP55, the drain of transistor MP57, and capacitor C51, the source is connected to the drains of transistors MP52 and MP53, and the drain is connected to the sources of transistors MP58 and MP59.

[0139] One end of capacitor C51 is connected to the power supply line VCCP, and the other end is connected to the gate of transistor MP54, the source of transistor MP55, and the drain of transistor MP57. Capacitor C51 may include two capacitors connected in parallel with each other.

[0140] The gate of transistor MP55 is connected to control line AZ1, the source is connected to the gate of transistor MP54, the drain of transistor MP57 and the other end of capacitor C51, and the drain is connected to the source of transistor MP56.

[0141] The gate of transistor MP56 is connected to control line AZ1, its source is connected to the drain of transistor MP55, its drain is connected to power supply line VSS, the gate of transistor MP57 is connected to control line WS, its drain is connected to the gate of transistor MP54, the source of transistor MP55, and the other end of capacitor C51, and its source is connected to the drain of transistor MP58.

[0142] The gate of transistor MP58 is connected to control line WS, the drain is connected to the source of transistor MP57, and the source is connected to the drain of transistor MP54 and the source of transistor MP59.

[0143] The gate of transistor MP59 is connected to control line DS, the source is connected to the drain of transistor MP54 and the source of transistor MP58, and the drain is connected to the source of transistor MP60 and the anode of light-emitting element L.

[0144] The gate of the transistor MP60 is connected to the control line AZ2, the source is connected to the drain of the transistor MP59 and the anode of the light-emitting element L, and the drain is connected to the power supply line VSS.

[0145] With this configuration, in pixel 100, transistors MP52, MP54, MP58, and MP57 are turned on in response to a control signal supplied from control line WS, and the voltage across capacitor C51 is set based on the pixel signal supplied from control line SIG.

[0146] Transistors MP53 and MP59 are turned on and off based on the signal Vds on control line DS. While transistors MP53 and MP59 are on, transistor MP54 passes a current corresponding to the voltage across capacitor C51 to light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MP54.

[0147] In this way, pixel 100 emits light at a brightness corresponding to the pixel signal. Transistors MP55 and MP56 are turned on and off based on the signal Vaz1 on control line AZ1. While transistors MP55 and MP56 are on, the gate voltage of transistor MP54 is initialized by being set to the voltage of power supply line VSS. Transistor MP60 is turned on and off based on the signal Vaz2 on control line AZ2. While transistor MP60 is on, the anode voltage of light-emitting element L is initialized by being set to the voltage of power supply line VSS.

[0148] Note that the transistors MP52 to MP60 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MP55 to MP58 and MP60 may be a transistor using an oxide semiconductor.

[0149] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0150] 17 shows another example of the configuration of the pixel 100. The signal Vsnl of the control line WSNL and the signal Vspl of the control line WSPL are mutually inverted signals.

[0151] The pixel 100 includes capacitors C61 and C62, transistors MN63, MN64, MN65 to MN67, and a light-emitting element L.

[0152] Transistors MN63, MN65 to MN67 are N-type MOSFETs, and transistor MP64 is a P-type MOSFET. The gate of transistor MN63 is connected to control line WSNL, the drain is connected to control line SIG and the source of transistor MP64, and the source is connected to the drain of transistor MP64, capacitors C61 and C62, and the gate of transistor MN65.

[0153] The gate of transistor MP64 is connected to control line WSPL, the source is connected to control line SIG and the drain of transistor MN63, and the drain is connected to the source of transistor MN63, capacitors C61 and C62, and the gate of transistor MN65.

[0154] Capacitor C61 is configured using, for example, a MOM (Metal Oxide Metal) capacitor, and one end is connected to the source of transistor MN63, the drain of transistor MP64, capacitor C62, and the gate of transistor MN65, and the other end is connected to power supply line VSS2. Note that capacitor C61 may also be configured using, for example, a MOS capacitor or an MIM (Metal Insulator Metal) capacitor.

[0155] Capacitor C62 is configured using, for example, a MOS capacitor, and one end is connected to the source of transistor MN63, the drain of transistor MP64, one end of capacitor C61, and the gate of transistor MN65, and the other end is connected to power supply line VSS2. Capacitor C62 may also be configured using, for example, a MOM capacitor or an MIM capacitor. The other end of capacitor C62 may also be connected to power supply line VSS3 (not shown).

[0156] The gate of transistor MN65 is connected to the source of transistor MN63, the drain of transistor MP64, and one end of capacitors C61 and C62, the drain is connected to power supply line VCCP, and the source is connected to the drains of transistors MN66 and MN67.

[0157] The gate of transistor MN66 is connected to control line AZL, the drain is connected to the source of transistor MN65 and the drain of transistor MN67, and the source is connected to power supply line VSS1.

[0158] The gate of transistor MN67 is connected to control line DS, the drain is connected to the source of transistor MN65 and the drain of transistor MN66, and the source is connected to the anode of light-emitting element L. Note that transistor MN67 and control line DS may not be provided, and the source of transistor MN65 may be connected to the drain of transistor MN66 and the anode of light-emitting element L.

[0159] With this configuration, in pixel 100, at least one of transistors MN63 and MP64 is turned on in response to a control signal supplied from control line WS, and the voltage across capacitors C61 and C62 is set based on the pixel signal supplied from control line SIG.

[0160] Transistor MN67 turns on and off based on signal Vds on control line DS. While transistor MN67 is on, transistor MN65 passes a current corresponding to the voltage across capacitors C61 and C62 to light-emitting element L. Light-emitting element L emits light based on the current supplied from transistor MN65.

[0161] In this way, pixel 100 emits light at a brightness corresponding to the pixel signal. Transistor MN66 may be turned on and off based on signal Vazl on control line AZL. Transistor MN66 may also function as a resistive element having a resistance value corresponding to signal Vazl on control line AZL. In this case, transistors MN65 and MN66 form a so-called source follower circuit.

[0162] Note that the transistors MN63, MP64, and MN65 to MN67 may be transistors using low-temperature polycrystalline silicon, and at least one of the transistors MN63, MP64, and MN66 may be a transistor using an oxide semiconductor.

[0163] The vertical scanning circuit 14 can perform the above processing on at least one of the control lines WS, DS, and AZ as the control lines 140, or can perform the above processing by controlling the voltage applied to the power supply line VCCP.

[0164] Hereinafter, some non-limiting examples of application of the display device 1 according to the present disclosure will be described.

[0165] (First application example)

[0166] The display device 1 according to the present disclosure can be used for various purposes. Figures 18A and 18B are diagrams showing the internal configuration of a vehicle 360, which is a first application example of the display device 1 according to the present disclosure. Figure 18A is a diagram showing the interior of the vehicle 360 ​​from the rear to the front of the vehicle 360, and Figure 18B is a diagram showing the interior of the vehicle 360 ​​from diagonally rear to diagonally front of the vehicle 360.

[0167] Vehicle 360 ​​of FIGS. 18A and 18B includes a center display 361, a console display 362, a head-up display 363, a digital rearview mirror 364, a steering wheel display 365, and a rear entertainment display 366.

[0168] The center display 361 is disposed on the dashboard 367 in a position facing the driver's seat 368 and the passenger's seat 369. FIG. 18 shows an example of a horizontally elongated center display 361 extending from the driver's seat 368 side to the passenger's seat 369 side, but the screen size and location of the center display 361 are arbitrary. The center display 361 can display information detected by various sensors. As a specific example, the center display 361 can display an image captured by an image sensor, a distance image to obstacles in front of or on the side of the vehicle measured by a ToF sensor, and the body temperature of a passenger detected by an infrared sensor. The center display 361 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information.

[0169] The safety-related information includes information such as detection of drowsiness, distraction, child mischief, whether a seatbelt is fastened, and whether a passenger has been abandoned. This information is detected, for example, by a sensor placed on the back side of the center display 361. The operation-related information is obtained by detecting gestures related to passenger operations using a sensor. The detected gestures may include operations of various equipment within the vehicle 360. For example, operations of the air conditioning system, navigation system, AV system, lighting system, etc. are detected. The life log includes life logs of all passengers. For example, the life log includes a record of each passenger's actions while on board. By acquiring and storing the life log, the passenger's condition at the time of an accident can be confirmed. The health-related information is obtained by detecting the passenger's body temperature using a temperature sensor and inferring the passenger's health condition based on the detected body temperature. Alternatively, the passenger's face may be captured using an image sensor and the passenger's health condition may be inferred from the facial expression in the captured image. Furthermore, the passenger may be spoken to by an automated voice and the passenger's health condition may be inferred based on the passenger's responses. The authentication / identification-related information includes a keyless entry function that uses a sensor to perform facial authentication, a function that automatically adjusts the seat height and position by facial recognition, etc. The entertainment-related information includes a function that uses a sensor to detect operation information of an AV device by an occupant, a function that recognizes the occupant's face with a sensor and provides content suitable for the occupant via the AV device, etc.

[0170] Console display 362 can be used to display, for example, life log information. Console display 362 is disposed near a shift lever 371 on a center console 370 between a driver's seat 368 and a passenger seat 369. Information detected by various sensors can also be displayed on console display 362. Furthermore, console display 362 may display an image of the vehicle's surroundings captured by an image sensor, or an image showing the distance to an obstacle around the vehicle.

[0171] The head-up display 363 is virtually displayed behind a windshield 372 in front of the driver's seat 368. The head-up display 363 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 363 is often virtually located in front of the driver's seat 368, it is suitable for displaying information directly related to the operation of the vehicle 360, such as the speed of the vehicle 360 ​​and the remaining fuel (battery) level.

[0172] The digital rearview mirror 364 can not only display the rear of the vehicle 360, but also the status of passengers in the rear seats. Therefore, by placing a sensor on the back side of the digital rearview mirror 364, it can be used to display life log information, for example.

[0173] Steering wheel display 365 is disposed near the center of steering wheel 373 of vehicle 360. Steering wheel display 365 can be used to display at least one of, for example, safety-related information, operation-related information, life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because steering wheel display 365 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, and for displaying information regarding the operation of AV equipment, air conditioning equipment, etc.

[0174] The rear entertainment display 366 is attached to the back of the driver's seat 368 and the passenger seat 369 and is intended for viewing by rear seat passengers. The rear entertainment display 366 can be used to display, for example, at least one of safety-related information, operation-related information, a life log, health-related information, authentication / identification-related information, and entertainment-related information. In particular, since the rear entertainment display 366 is located directly in front of the rear seat passengers, information related to the rear seat passengers is displayed on the rear entertainment display 366. For example, the rear entertainment display 366 may display information related to the operation of an AV device or an air conditioning system, or may display the results of measurements such as the body temperature of the rear seat passengers using a temperature sensor.

[0175] As described above, by arranging a sensor on the rear side of the display device 1, the distance to surrounding objects can be measured. Optical distance measurement methods can be broadly divided into passive and active types. Passive methods measure distance by receiving light from an object without projecting light from the sensor onto the object. Passive methods include the lens focusing method, the stereo method, and the monocular vision method. Active methods measure distance by projecting light onto an object and receiving the light reflected from the object with a sensor. Active methods include the optical radar method, the active stereo method, the photometric stereo method, the moire topography method, and the interferometry method. The display device 1 according to the present disclosure can be applied to any of these distance measurement methods. By using a sensor arranged on the rear side of the display device 1 according to the present disclosure, the above-mentioned passive or active distance measurement can be performed.

[0176] (Second application example)

[0177] The display device 1 according to the present disclosure is applicable not only to various displays used in vehicles but also to displays mounted on various electronic devices.

[0178] Fig. 19A is a front view of a digital camera 310 which is a second application example of the display device 1, and Fig. 19B is a rear view of the digital camera 310. The digital camera 310 in Fig. 19A and Fig. 19B shows an example of a single-lens reflex camera with an interchangeable lens 121, but the digital camera 310 can also be applied to a camera in which the lens 121 cannot be interchangeable.

[0179] 19A and 19B, when the photographer holds the grip 313 of the camera body 311, looks through the electronic viewfinder 315, decides on the composition of the shot, adjusts the focus, and presses the shutter, the captured data is saved in the camera's internal memory. As shown in Fig. 19B, the rear side of the camera is provided with a monitor screen 314 that displays the captured data, live images, etc., and the electronic viewfinder 315. In addition, a sub-screen that displays setting information such as the shutter speed and exposure value may be provided on the top surface of the camera.

[0180] By arranging the sensor on the back side of a monitor screen 314, an electronic viewfinder 315, a sub-screen, or the like used in a camera, it can be used as a display device 1 according to the present disclosure.

[0181] (Third application example)

[0182] The display device 1 according to the present disclosure can also be applied to a head-mounted display (hereinafter referred to as an HMD). The HMD can be used for VR, AR, MR (Mixed Reality), SR (Substitutional Reality), or the like.

[0183] Fig. 20A is an external view of an HMD 320, which is a third application example of the display device 1. The HMD 320 in Fig. 20A has a mounting member 322 for being worn over a person's eyes. This mounting member 322 is secured by hooking it onto a person's ear, for example. A display device 321 is provided inside the HMD 320, and a person wearing the HMD 320 can view 3D images and the like on this display device 321. The HMD 320 is equipped with, for example, a wireless communication function and an acceleration sensor, and can switch the 3D images and the like displayed on the display device 321 according to the posture, gestures, and the like of the wearer.

[0184] Alternatively, a camera may be provided in the HMD 320 to capture an image of the wearer's surroundings, and an image obtained by combining the image captured by the camera with an image generated by a computer may be displayed on the display device 321. For example, a camera may be placed on the back side of the display device 321, which is viewed by the wearer of the HMD 320, to capture an image of the area around the wearer's eyes, and the captured image may be displayed on another display provided on the outer surface of the HMD 320, allowing people around the wearer to grasp the wearer's facial expressions and eye movements in real time.

[0185] Various types of HMD 320 are possible. For example, as shown in FIG. 20B , the display device 1 according to the present disclosure can also be applied to smart glasses 340 that display various information on glasses 344. The smart glasses 340 in FIG. 20B include a main body 341, an arm 342, and a lens barrel 343. The main body 341 is connected to the arm 342. The main body 341 is detachable from the glasses 344. The main body 341 incorporates a control board and a display unit for controlling the operation of the smart glasses 340. The main body 341 and the lens barrel are connected to each other via the arm 342. The lens barrel 343 emits image light emitted from the main body 341 via the arm 342 toward lenses 345 of the glasses 344. This image light enters the human eye through the lens 345. A wearer of the smart glasses 340 in FIG. 20B can visually recognize not only the surrounding situation but also various pieces of information emitted from the lens barrel portion 343, just like with regular glasses.

[0186] (Fourth application example)

[0187] The display device 1 according to the present disclosure can also be applied to a television device (hereinafter referred to as a TV). Recent TVs tend to have as small a frame as possible from the viewpoints of miniaturization and design. For this reason, if a camera for capturing images of viewers is installed in the TV, it is desirable to place the camera on the back side of the display panel 331 of the TV.

[0188] FIG. 21 is an external view of a TV 330, which is a fourth application example of the display device 1. The TV 330 in FIG. 21 has a minimized frame, with almost the entire front side being the display area. The TV 330 has a built-in sensor, such as a camera, for capturing images of the viewer. The sensor in FIG. 21 is disposed on the back side of a portion of the display panel 331 (for example, the area enclosed by the dashed line). The sensor may be an image sensor module, or various other sensors such as a face authentication sensor, a distance measurement sensor, or a temperature sensor may be used, and multiple types of sensors may be disposed on the back side of the display panel 331 of the TV 330.

[0189] As described above, according to the display device 1 of the present disclosure, the image sensor module can be placed on top of the back side of the display panel 331, which eliminates the need to place a camera or the like in the frame, allowing the TV 330 to be made smaller, and there is no risk of the frame compromising the design.

[0190] (5th application example)

[0191] The display device 1 according to the present disclosure can also be applied to smartphones and mobile phones. FIG. 22 is an external view of a smartphone 350, which is a fifth application example of the display device 1. In the example of FIG. 22, a display surface 350z extends to nearly the outer size of the display device 1, and the width of a bezel 350y surrounding the display surface 350z is set to a few millimeters or less. Typically, a front camera is mounted in the bezel 350y. However, in FIG. 22, as shown by the dashed line, an image sensor module 351 functioning as a front camera is disposed on the rear side of the display surface 2z, for example, in the approximate center thereof. By providing the front camera on the rear side of the display surface 2z in this way, there is no need to dispose the front camera in the bezel 350y, and the width of the bezel 350y can be narrowed.

[0192] The above-described embodiment may be modified as follows.

[0193] (1) A display device comprising: light-emitting elements; a pixel array in which the light-emitting elements are arranged in a two-dimensional array; and a control circuit that, when a switch to a second frame rate occurs while the light-emitting elements belonging to the pixel array are emitting light at a first frame rate, controls extinction at a first frequency corresponding to the first frame rate until light emission at the first frame rate is completed across the pixel array, and controls extinction at a second frequency corresponding to the second frame rate after light emission at the first frame rate is completed.

[0194] (2) The display device according to (1), wherein the control circuit controls the light emitting elements belonging to the pixel array to have equal light emitting times for each frame.

[0195] (3) The display device according to (1) or (2), wherein the control circuit outputs a signal for controlling the timing of light emission and a signal for controlling the timing of extinction to each of the light-emitting elements of the pixel array via a control line.

[0196] (4) The display device according to (1) or (2), wherein the control circuit controls a power supply line connected to each of the light-emitting elements of the pixel array at a timing to emit light and a timing to extinguish light.

[0197] (5) The display device according to any one of (1) to (4), wherein the control circuit, when switching the frame rate, detects that the final line of the light-emitting elements belonging to the pixel array has been turned on and off, and switches the frequency at which the light-emitting elements are driven.

[0198] (6) The display device according to any one of (1) to (5), wherein the control circuit controls light emission at the second frequency after the frame rate is switched.

[0199] (7) The display device according to any one of (1) to (6), wherein the control circuit comprises: a first logic circuit that performs extinction control at the first frame rate; and a second logic circuit that performs extinction control at the second frame rate; and selects the first logic circuit and the second logic circuit for each frame and outputs a signal that performs extinction control.

[0200] (8) The display device according to any one of (1) to (7), wherein, when the pixel array includes light-emitting elements that emit light at the same timing for each block, the control circuit controls the drive frequency for light emission and the drive frequency for extinction for each block.

[0201] The aspects of the present disclosure are not limited to the above-described embodiments and include various conceivable modifications, and the effects of the present disclosure are not limited to the above-described contents. The components in each embodiment may be appropriately combined and applied. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and intent of the present disclosure, which is derived from the content defined in the claims and their equivalents.

[0202] 1: display device, 10: pixel array, 100: pixel, 12: control circuit, 14: vertical scanning circuit, 140: control line, 142: write / light-emission control unit, 144: CLK control unit, 146: extinction control unit, 148: transfer detection unit, 150: first extinction control unit, 152: second extinction control unit, 16: horizontal drive circuit, 160: control line

Claims

1. A display device comprising: light-emitting elements; a pixel array in which the light-emitting elements are arranged in a two-dimensional array; and a control circuit that, when a switch to a second frame rate occurs while the light-emitting elements belonging to the pixel array are emitting light at a first frame rate, controls extinction at a first frequency corresponding to the first frame rate until emission at the first frame rate is completed across the pixel array, and controls extinction at a second frequency corresponding to the second frame rate after emission at the first frame rate is completed.

2. The display device according to claim 1, wherein the control circuit controls the light emitting elements belonging to the pixel array for each frame so that the light emitting times are equalized.

3. The display device according to claim 1, wherein the control circuit outputs a signal for controlling the timing of light emission and a signal for controlling the timing of extinction to each of the light-emitting elements of the pixel array via a control line.

4. The display device according to claim 1, wherein the control circuit controls a power supply line connected to each of the light-emitting elements of the pixel array at a timing to emit light and a timing to extinguish light.

5. The display device according to claim 1, wherein, when the frame rate is switched, the control circuit detects that the final line of the light-emitting elements belonging to the pixel array has been turned on and off, and switches the frequency at which the light-emitting elements are driven.

6. The display device according to claim 1, wherein the control circuit controls light emission at the second frequency after the frame rate is switched.

7. The display device according to claim 1, wherein the control circuit comprises: a first logic circuit that performs extinction control at the first frame rate; and a second logic circuit that performs extinction control at the second frame rate; and selects the first logic circuit or the second logic circuit for each frame and outputs a signal that performs extinction control.

8. The display device according to claim 1, wherein, when the pixel array includes light-emitting elements that emit light at the same timing for each block, the control circuit controls the light emission drive frequency and the extinction drive frequency for each block.

Images