Diagnosis points for scan chain failure diagnosis using controllable inverter in scan chain shift path

Abstract

A scan chain comprises two neighboring scan cells (K + 1) and K and a controllable inverting device inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K. The selection of the scan cell K for the insertion of the controllable inverting device (diagnosis point insertion) is determined based on a diagnosis coverage analysis process. The scan cell K is configured to operate in one of a plurality of test-related modes based on a regular scan enable signal and a diagnosis mode signal. The plurality of test-related modes comprises a diagnosis capture mode in which the scan cell K is configured to capture the inverted version of a bit received at the data input of the controllable inverting device. The diagnosis mode signal may be provided by a storage device.

Description

[0001] DIAGNOSIS POINTS FOR SCAN CHAIN FAILURE DIAGNOSIS USING CONTROLLABLE INVERTER IN SCAN CHAIN SHIFT PATH

[0002] FIELD OF THE DISCLOSED TECHNOLOGY

[0003]

[0001] The present disclosed technology relates to the field of circuit test and diagnosis. Various implementations of the disclosed technology may be particularly useful for scan chain diagnosis.

[0004] BACKGROUND OF THE DISCLOSED TECHNOLOGY

[0005]

[0002] Modem integrated circuits are complex. At leading technology nodes, feature sizes have shrunk to a few nm wide. Non-planar or “three-dimensional” transistors (FinFET and GAA (gate-all-around)) are being used to achieve higher performance with lower power consumption. The non-planar transistors and transistor connections have more complicated structures with more layers and thus require more process steps. More process steps and smaller feature sizes can result in more root causes of defects. For these integrate circuits to be commercially viable, the manufacture yield needs to reach and maintain above a certain threshold. Therefore, accurately identifying yield-limiting root causes becomes highly critical. In the past, bitmapping static random-access memories (SRAMs) has been employed as a “yield learning vehicle”. For leading technology nodes, however, being capable of manufacturing these regular structures does not guarantee that a product with irregular structures can be successfully manufactured.

[0006]

[0003] Software-based diagnosis of scan test failures has proven to be of enormous value for yield learning. Scan testing is commonly used in a manufacturing process to ensure that integrated circuits are fabricated correctly. Diagnosis uses failure data from scan testing along with circuit design information to determine the most likely defect locations and mechanisms for failing circuits (dies). The diagnosis results can guide physical failure analysis (PF A) to focus on a much smaller area in a failing circuit, leading to higher success rates of PFA with reduced turnaround time and costs. Based on the yield loss mechanism obtained by PFA, circuit design or manufacture process can be adjusted to improve manufacture yields.

[0004] The PFA process is destructive to integrated circuits. It is thus important for diagnosis to provide a target area for PFA that is as precise as possible. The resolution or diagnosis coverage of a diagnostic tool is related to the number of suspected defect locations identified. The larger the number of suspect locations reported, the larger the area for PFA to work on. The demand for diagnosis resolution / coverage has increased, especially for chain diagnosis, where, due to the complexity of scan cell structures, PFA needs a diagnosis tool to report a single scan cell for PFA to work on. Recent data shows that diagnosis based directly on manufacture test patterns does not consistently achieve the required diagnostic quality. Even using test patterns specifically generated for diagnosis cannot pinpoint specific faulty scan cells in many cases.

[0007] BRIEF SUMMARY OF THE DISCLOSED TECHNOLOGY

[0008]

[0005] Various aspects of the present disclosed technology relate to techniques for diagnosis point insertion for improving diagnosis coverage. In one aspect, there is a circuit comprising: scan chains, one of the scan chains comprising a pair of neighboring scan cells formed by a scan cell (K + 1) and a scan cell K and a controllable inverting device inserted into a shift path of the one of the scan chains and between a serial output of the scan cell K + 1) and a serial input of the scan cell A, numbers (A + 1) and A being scan cell indices, wherein the scan cell A being selected for the insertion of the controllable inverting device is determined based on a diagnosis coverage analysis process, wherein a modified scan enable signal serves as a scan enable signal for at least the scan cell A, the modified scan enable signal being derived based on a diagnosis mode signal and a regular scan enable signal, wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal, and wherein the scan cell A is configured to operate in one of a plurality of test-related modes based on the regular scan enable signal and the diagnosis mode signal while the circuit is being tested, the plurality of test-related modes comprising a diagnosis capture mode in which the scan cell A is configured to capture the inverted version of a bit received at the data input of the controllable inverting device. The controllable inverting device may be an XOR gate.

[0009] The scan cell K and the controllable inverting device may be in a single device.

[0010]

[0006] The diagnosis mode signal may be provided by a storage device in the circuit. The storage device may be implemented using a state element such as a flip-flop. With various implementations of the disclosed technology, the storage device may be a scan cell or a shadow register of a scan cell in one of the scan chains. The diagnosis coverage analysis process may comprise design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

[0011]

[0007] The modified scan enable signal may further serve as a scan enable signal for a scan cell that is a downstream neighboring scan cell for the scan cell K on the one of the scan chains. The modified scan enable signal may further serve as a scan enable signal for all scan cells of the scan chains except a scan cell configured to store the diagnosis mode signal. The modified scan enable signal may be derived by a logical OR operation of the diagnosis mode signal and the regular scan enable signal.

[0012]

[0008] The inversion-control signal may be derived by inverting the regular scan enable signal. Alternatively, the inversion-control signal may be derived by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the regular scan enable signal.

[0013]

[0009] In another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into a scan cell (K + 1) in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of a scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K+ 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for one clock cycle, the scan cell K being configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by the controllable inverting device, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least a scan enable input of the scan cell K is coupled to a modified scan enable signal, and wherein the modified scan enable signal and the inversion-control signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out the bit of “1 - v” captured by the scan cell K to determine whether the scan cell K has a stuck-at-v fault at output side.

[0014]

[0010] In still another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for each of two clock cycles, wherein for each of the two clock cycles, the scan cell K and a scan cell (K - 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K- 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least scan enable inputs of the scan cells K and K - 1) are coupled to a modified scan enable signal, and wherein the modified scan enable signal and the inversion-control signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles to determine whether the scan cell K has a slow-to-fall / rise fault at output side.

[0015]

[0011] In still another aspect, there is a method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for one clock cycle, wherein the scan cell K and a scan cell (K - 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K- 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least scan enable inputs of the scan cells K and (K - 1) are coupled to a modified scan enable signal, and wherein the modified scan enable signal and the inversion-control signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out a bit captured by the scan cell (K- 1) at the one clock cycle to determine whether the scan cell K has a fast-to-fall / rise fault at output side.

[0016]

[0012] Certain inventive aspects are set out in the accompanying independent and dependent claims. Features from the dependent claims may be combined with features of the independent claims and with features of other dependent claims as appropriate and not merely as explicitly set out in the claims.

[0017]

[0013] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosed technology. Thus, for example, those skilled in the art will recognize that the disclosed technology may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein.

[0018] BRIEF DESCRIPTION OF THE DRAWINGS

[0019]

[0014] Figure 1 illustrates an example of a circuit having inserted diagnosis points that may be implemented according to various embodiments of the disclosed technology.

[0020]

[0015] Figure 2 illustrates an example of a scan cell.

[0016] Figure 3A illustrates an example of a controllable inverting device that may be implemented according to various embodiments of the disclosed technology.

[0021]

[0017] Figure 3B illustrates another example of a controllable inverting device that may be implemented according to various embodiments of the disclosed technology.

[0022]

[0018] Figure 4 illustrates an example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0023]

[0019] Figure 5 illustrates another example of a control signal generation device that may be implemented according to various embodiments of the disclosed technology.

[0024]

[0020] Figure 6A illustrates an example of two neighboring scan cells forming a part or a whole of a shift register.

[0025]

[0021] Figure 6B illustrates another example of two neighboring scan cells forming a part or a whole of a shift register.

[0026]

[0022] Figure 7 illustrates an example of diagnosis point insertion for a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0027]

[0023] Figure 8 illustrates another example of diagnosis point insertion for a scan chain that may be implemented according to various embodiments of the disclosed technology.

[0028]

[0024] Figure 9 illustrates an example of a scan cell that can be used to implement a storage device for storing the diagnosis mode signal according to various embodiments of the disclosed technology.

[0029]

[0025] Figure 10 illustrates a table that shows a chain pattern and chain pattern responses of a faulty scan chain for eight permanent fault models.

[0030]

[0026] Figure 11A illustrates a flowchart showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology.

[0027] Figure 1 IB illustrates a diagram showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology.

[0031]

[0028] Figure 12A illustrates a flowchart showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0032]

[0029] Figure 12B illustrates a diagram showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0033]

[0030] Figure 13A illustrates a flowchart showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0034]

[0031] Figure 13B illustrates a diagram showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology.

[0035]

[0032] Figure 14 illustrates an example of a computing device that may be used to implement various embodiments of the disclosed technology.

[0036] DETAILED DESCRIPTION OF THE DISCLOSED TECHNOLOGY

[0037] General Considerations

[0038]

[0033] Various aspects of the present disclosed technology relate to techniques for diagnosis point insertion for improving diagnosis coverage. In the following description, numerous details are set forth for the purpose of explanation. However, one of ordinary skill in the art will realize that the disclosed technology may be practiced without the use of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present disclosed technology.

[0034] Some of the techniques described herein can be implemented in software instructions stored on a computer-readable medium, software instructions executed on a computer, or some combination of both. Some of the disclosed techniques, for example, can be implemented as part of an electronic design automation (EDA) tool. Such methods can be executed on a single computer or on networked computers.

[0039]

[0035] Although the operations of the disclosed methods are described in a particular sequential order for convenient presentation, it should be understood that this manner of description encompasses rearrangements, unless a particular ordering is required by specific language set forth below. For example, operations described sequentially may in some cases be rearranged or performed concurrently. The detailed description sometimes uses terms like “perform”, “insert,” “load,” “invert,” and “capture” to describe the disclosed methods / systems. Such terms are high-level descriptions of the actual operations that are performed. The actual operations that correspond to these terms will vary depending on the particular implementation and are readily discernible by one of ordinary skill in the art.

[0040]

[0036] As used in this disclosure, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly dictates otherwise. Additionally, the term “includes” means “comprises.” Moreover, unless the context dictates otherwise, the term “coupled” means electrically or electromagnetically connected or linked and includes both direct connections or direct links and indirect connections or indirect links through one or more intermediate elements not affecting the intended operation of the circuit.

[0041]

[0037] Also, as used herein, the term “design” is intended to encompass data describing an entire integrated circuit device. This term also is intended to encompass a smaller group of data describing one or more components of an entire device, however, such as a portion of an integrated circuit device. Still further, the term “design” also is intended to encompass data describing more than one microdevice, such as data to be used to form multiple microdevices on a single wafer.

[0042] Design For Test, Test Patern Generation, Testing And Diagnosis

[0038] The reduction in feature size increases the probability that a manufacture defect in an integrated circuit will result in a faulty chip. A very small defect can result in a faulty transistor or interconnecting wire. Even a single faulty transistor or wire can cause the entire chip to function improperly. Manufacture defects are unavoidable nonetheless, no matter whether the manufacturing process is at the prototype stage or the high-volume manufacturing stage. It is thus necessary to test chips during the manufacturing process. Diagnosing faulty chips is also needed to ramp up and to maintain the manufacturing yield.

[0043]

[0039] Testing typically includes applying a set of test stimuli (test patterns) to the circuit-under- test and then analyzing responses generated by the circuit-under-test. Functional testing attempts to validate that the circuit-under-test operates according to its functional specification while structural testing tries to ascertain that the circuit-under-test has been assembled correctly from some low-level building blocks as specified in a structural netlist and that these low-level building blocks and their wiring connections have been manufactured without defect. For structural testing, it is assumed that if functional verification has shown the correctness of the netlist and structural testing has confirmed the correct assembly of the structural circuit elements, then the circuit should function correctly. Structural testing has been widely adopted at least in part because it enables the test (test pattern) generation to focus on testing a limited number of relatively simple circuit elements rather than having to deal with an exponentially exploding multiplicity of functional states and state transitions.

[0044]

[0040] To make it easier to develop and apply test patterns, certain testability features are added to circuit designs, which is referred to as design for test or design for testability (DFT). Scan testing is the most common DFT method. In a basic scan testing scheme, all or most of internal sequential state elements (latches, flip-flops, et al.) in a circuit design are made controllable and observable via a serial interface. These functional state elements are usually replaced with dual-purpose state elements called scan cells. Scan cells are connected together to form scan chains - serial shift registers for shifting in test patterns and shifting out test responses. A scan cell can operate as originally intended for functional purposes (functional / mission mode) and as a unit in a scan chain for scan testing (scan mode). A widely used type of scan cell includes an edge-trigged flip-flop with two-way multiplexer for the data input. The two-way multiplexer is typically controlled by a single control signal called scan_enable, which selects the input signal for a scan cell from either a scan signal input port or a system signal input port. The scan signal input port is typically connected to an output of another scan cell while the system signal input port is connected to the functional logic. Scan cells can serve as both a control point and an observation point. Control points can be used to set certain logic values at some locations of the circuit-under-test, exciting (activating) a fault and propagating the incorrect value to an observation point. Scan testing allows the test equipment to access gates deeply embedded through the primary inputs / outputs and / or some physical test points and can remove the need for complicated state transition sequences when trying to control or observe what is happening at some internal circuit element.

[0045]

[0041] In a typical scan test, a series of known values (test stimuli or test pattern) are shifted-in (or loaded into) scan cells through their sequential inputs. The shifting-in occurs by placing the integrated circuit in a special mode, known as shift mode, and then applying a series of clock pulses, called “shift pulses” or “shift clock pulses.” Each shift clock pulse pushes a bit of test stimuli into a scan cell in each of the scan chains. This continues until all scan cells in the scan chains are filled with test pattern bits. Then, one or more clock pulses, called “capture pulses” or “capture clock pulses,” are applied to the circuit as they would be in normal operation. This is referred to as capture mode. After the test pattern bits are injected into the circuit, the results of the test (test responses) are “captured” and stored in the scan cells. The circuit then returns to shift mode, and with each additional clock pulse, a bit of the test responses is pushed or shifted out as each bit of new test pattern is pushed or shifted in. The shifted-out test responses are then compared with expected results to determine and locate any errors. Shift mode and capture mode together may be referred to as test mode.

[0046]

[0042] Test patterns for scan testing are typically generated through an automatic test pattern generation (ATPG) process. ATPG usually focuses on a set of faults derived from a gate- level fault model. A defect is a flaw or physical imperfection caused in a device during the manufacturing process. A fault model (or briefly a fault) is a description of how a defect alters design behavior. For a given target fault, ATPG comprises two phases: fault activation and fault propagation. Fault activation establishes a signal value at the fault site opposite that produced by the fault (e g., for a stuck-at-0 fault, the fault activation process will try to establish a logic T' at that site). Fault propagation propagates the fault effect (e.g., stuck at 0) forward by sensitizing a path from a fault site to a scan cell or a primary output. A fault at a site is said to be detected by a test pattern if a test response value captured by a scan cell or a primary output is different than the expected value. The objective of ATPG is to find a test pattern that, when applied to the circuit, enables testers to distinguish between the correct circuit behavior and the faulty circuit behavior caused by one or more particular faults. Effectiveness of ATPG is measured by the fault coverage achieved for the fault model and the number of generated vectors (test pattern counts), which should be directly proportional to test application time. Here, the fault coverage is defined as a ratio of the number of detected faults vs. the total number of faults.

[0047]

[0043] A popular fault model used in practice is the single stuck-at fault model. In this model, one of the signal lines in a circuit is assumed to be stuck at a fixed logic value, regardless of what inputs are supplied to the circuit. The stuck-at fault model is a logical fault model because no delay information is associated with the fault definition. Delay faults cause errors in the functioning of a circuit based on its timing. They are caused by the finite rise and fall time periods of the signals in the gates, as well as the propagation delay of interconnects between the gates. Transition faults are used for their simplicity in modeling spot defects that affect delays at inputs or outputs of gates. Under scan-based tests, the transition faults are associated with an extra delay that is large enough to cause the delay of any path through the fault site to exceed the clock period. Cell internal fault models can be derived using transistor-level circuit simulations (analog simulations). This approach can pinpoint the defect location within a cell for various cell internal defects.

[0044] During the circuit design and manufacturing process, a manufacturing test screens out chips (dies) containing defects. The test itself, however, does not identify the reason for the unacceptable low or fluctuating yield that may be observed. Physical failure analysis (PF A) can inspect the faulty chip to locate the defect location(s) and to discover the root cause. The process usually includes etching away certain layers and then imaging the silicon surface by scanning electronic microscopy or focused ion beam systems. This PFA process is laborious and time consuming. To facilitate the PFA process, diagnosis (also referred to as scan diagnosis) is often employed to narrow down possible locations of the defect(s) based on analyzing the fail log (fail file, failure file). The fail log typically contains information about when (e.g., tester cycle), where (e.g., at what tester channel), and how (e.g., at what logic value) the test failed and which test patterns generate expected test responses. The layout information of the circuit design may also be employed to further reduce the number of defect suspects.

[0048]

[0045] Diagnosis includes logic diagnosis (sometimes referred to as scan diagnosis) and chain diagnosis. Logic diagnosis may employ a fault dictionary or directly examine the syndrome (i.e., the effect) of the failing chip to determine likely defect locations (defect suspects). The latter approach may include structural pruning (back tracing), fault injection and evaluation (fault simulation for both failing and passing test patterns).

[0049]

[0046] Chain diagnosis determines scan cells that are likely to be defective. Scan elements and related clocking circuitry can take up about 30% of silicon area of an IC chip. It has been reported that scan chain failures account for almost 50% of chip failure in some cases. Chain diagnosis is thus important to guide physical failure analysis and yield learning process. In a chain diagnosis process, two types of test patterns may be used. The first type is called chain patterns. A chain pattern is a pattern used in a process comprising shift-in and shift-out without pulsing capture clocks. The other type is often referred to as scan patterns. A scan pattern is a pattern used in a process comprising shift-in, one or multiple capture clock cycles, and shift-out, and the scan patterns include patterns generated by ATPG for testing system logic, special chain diagnostic patterns generated only for scan chain diagnosis purpose and some special functional patterns. Chain patterns can be used to test the integrity of scan chains and / or determine fault models associated with faulty scan chains while scan patterns can be used to inject certain values to some scan cells for locating defective scan cells.

[0050]

[0047] The quality of diagnosis can be measured by diagnostic resolution (the number of the real defects vs. the number of the defect suspects). Diagnostic resolution is linked not only to the algorithm used for diagnosis but also to the test patterns used for the manufacturing test (manufacturing test patterns). The quality of diagnosis can also be measured by diagnosis coverage. Diagnosis coverage may be determined in several ways. A simple way is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group cannot be separated or distinguished under a certain condition by a diagnosis technique. To enhance the quality of diagnosis, a diagnostic test pattern generation process may be employed. This process generates test patterns that can increase the number of equivalent fault groups or reduce the average number of faults in the equivalent fault groups.

[0051]

[0048] Test application in chip manufacturing test is normally performed by automatic test equipment (ATE) (a type of testers). Scan-based tests consume significant amounts of storage and test time on ATE. The data volume increases with the number of logic gates on the chip and the same holds for the number of scan cells. Yet, practical considerations and ATE specifications often limit both the number of pins available for scan in / out and the maximum scan frequency. It is highly desirable to reduce the amount of test data that need to be loaded onto ATE and ultimately to the circuit under test. Fortunately, test patterns are compressible mainly because only 1% to 5% of test pattern bits are typically specified bits (care bits) while the rest are unspecified bits (don't-care bits). Unspecified bits can take on any values with no impact on the fault coverage. Test compression may also take advantage of the fact that test cubes tend to be highly correlated. A test cube is a deterministic test pattern in which the don't-care bits are not filled by ATPG. The correlation exists because faults are structurally related in the circuit.

[0052]

[0049] Various test compression techniques have been developed. In general, additional on-chip hardware before and after scan chains is inserted. The hardware (decompressor) added before scan chains is configured to decompress test stimulus coming from ATE, while the hardware (compactor) added after scan chains is configured to compact test responses captured by the scan chains. The decompressor expands the data from n tester channels to fill greater than n scan chains. The increase in the number of scan chains shortens each scan chain and thus reduces the number of clock cycles needed to shift in each test pattern. Thus, test compression can not only reduce the amount of data stored on the tester but also reduce the test time for a given test data bandwidth.

[0053] Diagnosis-Point-1 nserted Circuits

[0054]

[0050] Fig. 1 illustrates an example of a circuit 100 having inserted diagnosis points that may be implemented according to various embodiments of the disclosed technology. The circuit 100 comprises scan chains 110. The scan chains 110 are formed by stitching scan cells together. Typically, a scan cell can be configured to operate in either a shift mode (normal shift mode) or a capture mode (normal capture mode) based on a scan enable signal. Fig. 2 illustrates an example of a scan cell 200. The scan cell 200 comprises a state element 210 and a two-way multiplexer 220. The state element 210 can be implemented using an edge-trigged flip-flop. The two-way multiplexer 220 selects a signal from either a serial input port 230 or a parallel input port 240 of the scan cell 200 as the data input signal for the state element 210. The selection is based on a scan enable signal supplied from a scan enable port 250 of the scan cell 200. The serial input port 230 can be coupled to an output of another scan cell in the same scan chain and the parallel input port 240 can be coupled to functional circuitry 270.

[0055]

[0051] When the scan enable signal 250 is asserted, the serial input port 230 is coupled to the data input for the state element 210. As a result, the scan cell 200 operates in the shift mode. When the scan enable signal 250 is deasserted, the parallel input port 240 is coupled to the data input for the state element 210. As a result, the scan cell 200 operates in the capture mode. The scan cell 200 fans out into two outputs: a serial output 260 and a parallel output 280. The serial output 260 can be coupled to the serial input port of the next scan cell in the same scan chain. The parallel output 280 can be coupled to the functional circuitry 270. In this setup which has no shadow register, the data bit stored in the state element 110 is being applied to the functional circuitry 270 continuously even in the shift mode. During a test, scan chains can shift in test stimuli bits of a test pattern in the shift mode, capture test response bits for the test pattern from the functional circuitry in the capture mode, and shift out the test response bits again in the shift mode.

[0056]

[0052] It should be noted that one or more scan cells in a scan chain may not have parallel inputs coupled to the functional circuitry in some cases. Such a scan cell may serve as a shift register. It should also be noted that a scan cell may not have a built-in multiplexer, but its input can be coupled to an output of a multiplexer placed outside of the scan cell. A combination of the scan cell and the multiplexer can function as a typical scan cell.

[0057]

[0053] Referring back to Fig. 1, a scan chain 120 in the scan chains 110 comprises a pair of neighboring scan cells 130 and 140, and a controllable inverting device 150 inserted into the shift path of the scan chain 120 and between a serial output of the scan cell 130 and a serial input of the scan cell 140. In some situations, the controllable inverting device 150 may be placed on an overlap portion of the shift path and the capture path (from functional circuitry to the data input of the state element) of the scan cell 140. In the present disclosure, the scan cells 130 and 140 are also referred to as scan cells (K + 1) and K, respectively. The indices of (K + 1) and K show scan cell positions on the scan chains 110. In this disclosure, scan cells in a scan chain are numbered incrementally from the scan output to the scan input, with the first scan cell assigned an index of 0, the second assigned an index of 1, and so on. This convention is widely used in the industry. The scan cells between the scan input of the scan chain and the serial input of a scan cell are called “upstream scan cells” of the scan cell, while the scan cells between the scan output of the scan chain and the serial output of the scan cell are called “downstream scan cells” of the scan cell.

[0058]

[0054] The controllable inverting device 150 is configured to output an inverted version (“v”) or an original version (“1 - v”) of a bit (“v”) received at its data input based on an inversioncontrol signal 170. The inversion-control signal 170 is coupled to the control input of the controllable inverting device 150. Fig. 3 A illustrates an example of a controllable inverting device 300 that may be implemented according to various embodiments of the disclosed technology. The controllable inverting device 300 is an XOR gate. The two inputs 310 and 320 of the XOR gate serve as the data input and the control input of the controllable inverting device 300, respectively. When an inversion-control signal 330 is asserted, the bit at the output 315 of the controllable inverting device 300 is the inverted version (“1 - v”) of the bit (“v”) at the input 310. When the inversion-control signal 330 is deasserted, the bit at the output 315 of the controllable inverting device 300 is the original version (“v”) of the bit (“v”) at the input 310. Fig. 3B illustrates another example of a controllable inverting device 340 that may be implemented according to various embodiments of the disclosed technology. The controllable inverting device 340 comprises a multiplexer 350 and an inverter 360. The select input 380 of the multiplexer 350 is coupled to the control input of the controllable inverting device 340. When an inversion-control signal 390 is asserted, the multiplexer 350 selects the output of the inverter 360 as its output and thus the bit at the output 375 of the controllable inverting device 340 is the inverted version (“1 - v”) of the bit (“v”) at the input 370. When the inversion-control signal 390 is deasserted, the multiplexer 350 selects the input 370 as its output and thus the bit at the output 375 of the controllable inverting device 340 is the original version (“v”) of or the same as the bit (“v”) at the input 370.

[0059]

[0055] Referring back to Fig. 1, the scan enable input of the scan cell 140 (scan cell K) is coupled to a modified scan enable signal 160. A control signal generation device 195 is configured to derive the modified scan enable signal 160 based on a diagnosis mode signal 190 and a regular scan enable signal 180. In addition, the control signal generation device 195 can also generate the inversion-control signal 170. The regular scan enable signal 180 is the conventional scan enable signal that is typically used to control in which mode, the conventional shift mode or the conventional capture mode, a scan cell operates. By using the modified scan enable signal 160 along with the inversion-control signal 170, the scan cell 140 can operate in at least one additional mode, diagnosis capture mode. In the diagnosis capture mode, the scan cell 140 is configured to capture the inverted version (“1 - v”) of a bit (“v”) received at the data input of the controllable inverting device 150. If the controllable inverting device 150 is implemented using the controllable inverting device 300 shown in Fig. 3A or the controllable inverting device 340 shown in Fig. 3B, the diagnosis capture mode can be activated by asserting not only the inversion-control signal 170 but also the modified scan enable signal 160 since the controllable inverting device 150 is placed on the shift path of the scan cell 140.

[0060]

[0056] Fig. 4 illustrates an example of a control signal generation device 400 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 400 comprises an inverter 410 and an OR gate 420. The inverter 410 is configured to generate an inversion-control signal 450 by inverting a regular scan enable signal 430. The OR gate 420 is configured to generate a modified scan enable signal 460 by performing a logical OR operation of the regular scan enable signal 430 and a diagnosis mode signal 440. When the regular scan enable signal 430 is asserted and the diagnosis mode signal 440 is deasserted, the modified scan enable signal 460 is asserted and the inversion-control signal 450 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 430 and the diagnosis mode signal 440 are deasserted, the modified scan enable signal 460 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 430 and the diagnosis mode signal 440 are asserted, the modified scan enable signal 460 is asserted and the inversion-control signal 450 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 430 is deasserted and the diagnosis mode signal 440 is asserted, both the modified scan enable signal 460 and the inversion-control signal 450 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the scan cell is to capture the inverted version (“ 1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 470 in Fig. 4 summarizes the above-described four test-related modes in which a scan cell can operate based on the regular scan enable signal 430 and the diagnosis mode signal 440.

[0061]

[0057] Fig. 5 illustrates another example of a control signal generation device 500 that may be implemented according to various embodiments of the disclosed technology. The control signal generation device 500 comprises an inverter 510, an OR gate 520 and an AND gate 580. Similar to the OR gate 420 in Fig. 4, the OR gate 520 is configured to generate a modified scan enable signal 560 by performing a logical OR operation of a regular scan enable signal 530 and a diagnosis mode signal 540. Also similar to the inverter 410 in Fig. 4, the inverter 510 is configured to invert a regular scan enable signal 530. Unlike the control signal generation device 400 in Fig. 4, however, the output of the inverter 510 is not the output of the control signal generation device 500. Rather, the AND gate 580 is configured to combine the output of the inverter 510 with the diagnosis mode signal 540 to generate the inversion-control signal 550. When the regular scan enable signal 530 is asserted and the diagnosis mode signal 540 is deasserted, the modified scan enable signal 560 is asserted and the inversion-control signal 550 is deasserted, activating the normal shift mode for the scan cell. When both the regular scan enable signal 530 and the diagnosis mode signal 540 are deasserted, the modified scan enable signal 560 is deasserted, activating the normal capture mode for the scan cell. When both the regular scan enable signal 530 and the diagnosis mode signal 540 are asserted, the modified scan enable signal 560 is asserted and the inversion-control signal 550 is deasserted, activating the diagnosis shift mode for the scan cell. It should be noted that the diagnosis shift mode is essentially the same as the normal shift mode. When the regular scan enable signal 530 is deasserted and the diagnosis mode signal 540 is asserted, both the modified scan enable signal 560 and the inversion-control signal 550 are asserted, activating the diagnosis capture mode for the scan cell. In the diagnosis capture mode, the scan cell is to capture the inverted version (“ 1 - v”) of a bit (“v”) received at the data input of the controllable inverting device. A table 570 in Fig. 5 summarizes the above-described four test-related modes in which a scan cell can operate based on the regular scan enable signal 530 and the diagnosis mode signal 540.

[0062]

[0058] A comparison of the table 570 in Fig. 5 with the table 470 in Fig. 4 shows one difference between them. In the normal capture mode: the inversion-control signal is deasserted in the table 570 but asserted in the table 470. The assertion of the inversion-control signal in the normal capture mode may not matter in many cases since the inversion happens on the shift path of the scan cell and should not affect the capture operation. In some situations, however, the inserted controllable inverting devices may impact the circuit behavior in capture cycles. As noted previously, a scan cell may serve as a part or a whole of a shift register. When the controllable inverting device is placed on the shift path and in front of the scan cell to improve diagnosis coverage, such a scan cell can capture the inverted version rather than the original version of the bit that it is supposed to capture in the normal capture mode. The same problem may also exist when the controllable inverting device is inserted into a common section of the shift path and the capture path of a scan cell. This placement may occur when the multiplexer for mode controlling is not inside the scan cell or when there no clear separation between shift path and capture path. The unwanted inversion during the normal capture mode can be avoided using the control signal generation device 500 in Fig. 5. The inversion-control signal 550 is produced by a logical AND operation (performed by the AND gate 580) of the inversion of the regular scan enable signal 530 and the diagnosis mode signal 540. The deassertion of the diagnosis mode signal 540 during the normal capture mode ensures that the inversion-control signal 550 is also deasserted and no inversion can occur.

[0063]

[0059] Referring back to Fig. 1, the scan cell K being selected for the insertion of the controllable inverting device 150 can be determined based on a diagnosis coverage analysis process. The diagnosis coverage analysis process may comprise design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof. The diagnosis coverage can be calculated based on how many equivalent fault groups have a single fault. A simple way to compute the diagnosis coverage is to divide the number of equivalent fault groups by the number of faults. Faults in an equivalent fault group are faults that cannot be separated or distinguished under a certain condition or using one or more specific diagnosis techniques. In chain diagnosis, two equivalent faults are often associated with two scan cells, particularly two neighboring ones.

[0064]

[0060] When the production test patterns are insufficient to achieve 100% diagnosis coverage, additional test patterns may be generated for diagnosis to ensure as many faults as possible to have unique failing bits. This type of ATPG may be referred to as diagnosis ATPG or diagnosis (test) pattern generation. Two diagnosis test pattern generation algorithms may be employed to create two kinds of test patterns for separating faults at two neighboring scan cells, namely scan cell K and scan cell (K + 1). One is referred to as observe-unload test patterns and the other is referred to as observe-load test patterns. To distinguish whether the scan cell K or the scan cell (K + 1) has the stuck-at-v fault, for example, the observe-unload test generation algorithm tries to create a test pattern to determine specifically whether the scan cell K has the stuck-at-v fault. In this algorithm, each of scan cells (K + 1), K, (K - 1), .. ., 0 is constrained to a bit value v and an ATPG process is performed to ensure that the scan cell K can capture a bit value (1 - v). If the unloaded test response bit for the scan cell A is (1 - v), then the scan cell K does not have the stuck-at-v fault. Otherwise, the scan cell K has the stuck-at-v fault. The captured value (1 - v) is referred to as clean bit data. For a scan pattern, scan loading operations are performed before the capture operations. To ensure the capture data is clean, each of the scan cells from cell (K + 1) to its downstream scan cells in the same scan chain is loaded with a value v to ensure no loading failures due to the stuck-at-v fault in either of the scan cells (K + 1) and K. The diagnosis ATPG process decides how to supply the clean bit data. Without loading errors due to the constraints, the capture value (1 - v) at the scan cell K can be guaranteed to be clean. The unloaded value at scan cell K is referred to as an output care bit because its value indicates whether or not the scan cell K has the stuck- at-v fault.

[0065]

[0061] On the other hand, to distinguish whether the scan cell K or the scan cell (K + 1) has the stuck-at-v fault, the observe-load test generation algorithm tries to create a test pattern to determine specifically whether the scan cell (K+ 1) has the stuck-at-v fault. In this algorithm, the scan cell (K + 1) is loaded with a value (1 - v) and each of scan cells K, (K - 1), . .. , 0 is constrained to a value v; and a diagnosis ATPG process is performed to propagate the fault effect at the scan cell (K + 1) output, which should excite the fault at the scan cell (K + 1) due to the last load cycle having a value (1 - v) at the scan cell (K + 1) but not the fault at the scan cell K due to its load value v, to a clean observation value. The clean observation value should be captured by either a scan cell in other good scan chains or any scan cell downstream of the scan cell K, referring to as a clean observation point. This algorithm constrains the scan cell K and its downstream scan cells to value v. These constraints ensure that all these loading values are unaffected by the fault in either of the scan cells (K + 1) and K. If the fault is at the scan cell (K + 1), this test pattern can observe a failing bit at the clean observation point. If the fault is at the scan cell K, this pattern cannot have a failing bit at the clean observation point. This clean observation point is the output care bit that needs to be observed.

[0066]

[0062] For design with test response compaction, it is necessary' to ensure that unknown values from other chains do not mask the output care bit. Both ob serve-unl oad and observe-load patterns have one output care bit each.

[0067]

[0063] There are several reasons why diagnosis ATPG cannot always generate the abovedescribed two types of test patterns. One reason is that diagnosis ATPG cannot find a test pattern that can distinguish the two scan cells under the abovementioned constraints. Scan cells can be used to control circuit behavior, such as scan wrapper cells in core boundaries for hierarchical tests, low-power clock management scan cells, and on-chip clock generator control scan cells. When these scan cells are faulty, it significantly impacts circuit behavior, complicating chain diagnosis. As described in the requirements to generate ob serve-unl oad and observe-load test patterns for a target cell, scan cells downstream of the target cell need to be constrained to ensure clean data. These constraints may shut off hierarchical test capability or capture clock operations. Without proper capture operations, neither of the two types of test patterns can be created.

[0068]

[0064] Another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that the test generation program can reach a user-defined CPU (central processing unit) time limit or backtracking limit. Due to constraints on loading values, scan cells do not have complete controllability, such that more capture clock cycles may be needed to get specific values at certain scan cells. Using more capture clock cycles increases ATPG complexity exponentially. In other words, some test patterns are expected to fail to be created due to sequential depth limits. In modern designs, it is impractical to expect ATPG to use more than four capture clock cycles in its test generation search space. For designs with test compression, since there are many constraints on loading value, many input care bits may exceed the test compression capacity.

[0065] Still another reason why diagnosis ATPG cannot always generate the above-described two types of test patterns is that two neighboring scan cells are in a shift register. For example, some scan cells are often added to test chips without functional usage. Fig. 6A illustrates an example of two neighboring scan cells 610 and 620 forming a part or a whole of a shift register. All failing bits created from the shift register are independent of fault location. As such, the two neighboring scan cells 610 and 620 are not distinguishable using any test patterns. Fig. 6B illustrates another example of two neighboring scan cells 630 and 640 forming a part or a whole of a shift register. They are also not distinguishable using any test patterns even through each of the two neighboring scan cells 630 and 640 has a parallel input and a scan enable input.

[0069]

[0066] To overcome the limitations of diagnosis test pattern generation like those described above and to further increase the diagnosis coverage, controllable inverting devices like the controllable inverting device 150 in Fig. 1 may be inserted into scan paths as clean bit data sources. Here, an inserted controllable inverting device can be referred to as a diagnosis point. By adding a diagnosis point between a pair of scan cells (K + 1) and an ob serve-unl oad test pattern can be created successfully for the scan cell K so that the scan cells (K + 1) and K can be distinguished. For the stuck-at-0 fault, for example, value 0 are loaded to both the scan cells (K + 1) and K As such, the scan cell (K + 1) loading value 0 will provide the clean bit value 1 at the scan cell K after the capture cycle in the diagnosis capture mode due to the inversion at the shift path of the scan cell K. Diagnosis points can also be employed to solve diagnosis coverage problems associated with other types of chain faults which will be discussed in detail below.

[0070]

[0067] As noted previously, one approach to determine locations of diagnosis points is based on diagnosis test pattern generation (test pattern generation for diagnosis). According to various embodiments of the disclosed technology, diagnosis simulation is first performed for production test patterns to identify equivalent fault groups. Then, ob serve-unl oad or observe-load test patterns are generated to break up neighboring equivalent fault groups. Upon the test patterns being generated, diagnosis simulation is incrementally performed with these new test patterns to break up equivalent fault groups further. Next, diagnosis test patterns may be generated for non-neighboring equivalent faults left and diagnosis simulation is performed incrementally with these new test patterns to break up equivalent fault groups still further. Based on the remaining equivalent fault groups that have more than one fault, locations of diagnosis points can be determined. Some equivalent faults may not exist in two neighboring scan cells, but a controllable inverting device may still be placed on the shift path between the two scan cells associated with two equivalent faults and in front of the downstream one of the two scan cells.

[0071]

[0068] Alternatively or additionally, locations of diagnosis points may be determined using a design rule checking (DRC) tool. For example, the design rule checking tool may be configured to search for scan cells that are in or serve as shift registers like the scan cells 610 - 640 in Figs. 6A-6B.

[0072]

[0069] Another method for determining locations of diagnosis points is based on diagnosability analysis. Diagnosability analysis of two neighboring scan cells (K+ 1) and K with respect to stuck-at-v faults may comprise: determining (1 - v)-controllability of a data input of the scan cell X, and determining observability of a data output of the scan cell (X + 1). The (1 - v)-controllability is defined as the difficulty of setting a particular logic signal to a logic value of (1 - v), and the observability is defined as the difficulty of observing the state of a logic signal. SCOAP (Sandia controllability / observability analysis program) testability measures may be employed for determining the (1 - v)-controllability and the observability.

[0073]

[0070] The above three approaches for determining locations of diagnosis points may be used individually or in any combination. If an XOR gate is added in front of each scan cell to increase diagnosis coverage, it will also increase silicon area overhead significantly. If one XOR gate is added to every N scan cells, the silicon area overhead may be reduced, but the diagnosis coverage will suffer as a result. By contrast, the disclosed technology can significantly reduce the silicon area overhead while maintaining high diagnosis coverage by inserting diagnosis points only at locations where insertions are necessary. Moreover, diagnosis test patterns can be generated more easily due to a much smaller number of care-bits needed in the disclosed technology. This is especially beneficial in a test compression environment. One input-care-bit test pattern may be generated for each diagnosable scan cell (scan cells with XOR gates added in front are called diagnosable scan cells). There is no need to worry about compression capacity to support test patterns with one input-care-bit. In general, ATPG supports dynamic compaction to merge test patterns such that one pattern can target multiple faults. Since each diagnosis point pattern only needs one input care bit, many test patterns may be merged.

[0074]

[0071] It should be noted that the controllable inverting device 150 and the scan cell 140 in Fig. 1 can be treated as a single device: a scan cell having a built-in controllable inverting device. Diagnosis point insertion can be either inserting a controllable inverting device into a shift path of a normal scan cell or replacing a normal scan cell with a scan cell having a built-in controllable inverting device according to various embodiments of the disclosed technology.

[0075]

[0072] Fig. 7 illustrates an example of diagnosis point insertion for a scan chain 700 that may be implemented according to various embodiments of the disclosed technology. Stuck- at faults associated with scan cells 710, 711 and 712 are in an equivalent fault group, and stuck-at faults associated with scan cells 713 and 715 are in another equivalent fault group. Controllable inverting devices 720 and 730 are inserted in front of the scan cells

[0076] 710 and 711, respectively, to make the stuck-at faults associated with the scan cells 710,

[0077] 711 and 712 unique. A controllable inverting device 740 is inserted in front of the scan cell 713 to make the stuck-at faults associated with the scan cells 713 and 715 unique. The three controllable inverting devices 720, 730 and 740 are controlled by an inversioncontrol signal 770, scan enable inputs of the three corresponding diagnosable scan cells 710, 711 and 713 are coupled to a modified scan enable signal 750, and scan enable inputs of the rest of scan cells are coupled to a regular scan enable signal 760. The modified scan enable signal 750 and the inversion-control signal 770 can be generated locally based on the regular scan enable signal 760 and a diagnosis mode signal 780. As will be discussed below, the diagnosis mode signal 780 can be a static signal provided by a scan cell such as the first one counted from the input of the scan chain 700. This kind of setup can reduce area overhead and makes the diagnosis-related mode control flexible. In circuit designs with low power management, scan cells may not have a capture clock, which is needed to have proper ob serve-unl oad patterns even with diagnosis points added. Typically, these clocks must be active when the regular scan enable signal 760 is asserted to ensure proper normal shift operation. To fix this problem, the modified scan enable signal 750 can be used to activate the shift clock.

[0078]

[0073] Fig. 8 illustrates another example of diagnosis point insertion for a scan chain 800 that may be implemented according to various embodiments of the disclosed technology. Stuck-at faults associated with scan cells 810, 811 and 812 are in an equivalent fault group, and stuck-at faults associated with scan cells 813 and 815 are in another equivalent fault group. Controllable inverting devices 820 and 830 are inserted in front of the scan cells 810 and 811, respectively, to make the stuck-at faults associated with the scan cells 810, 811 and 812 unique. A controllable inverting device 840 is inserted in front of the scan cell 813 to make the stuck-at faults associated with the scan cells 813 and 815 unique. The diagnosis point insertion in Fig. 8 is similar to the one shown in Fig. 7. Also similar is the controlling of the three controllable inverting devices 820, 830 and 840 by an inversion-control signal 870. A difference between Fig. 8 and Fig. 7 is that scan enable inputs of the scan cells in the scan chain 800 are all coupled to a modified scan enable signal 850 whereas only the diagnosable scan cells 710, 711, and 713 in the scan chain 700 are controlled by the modified scan enable signal 760. This arrangement is beneficial to scan cells that do not have clear separation between shift path and capture path and it is challenging to locate scan enable inputs for diagnosable scan cells. Moreover, the clocks of all scan cells are activated during the diagnosable capture mode, the problem of missing capture clocks will not occur due to the assertion of the modified scan enable signal 850. The downside is that even regular scan cells stay in shift and don’t capture from their functional inputs, which does not provide benefit to logic fault detection. However, considering that the special diagnosis test patterns are generated for breaking remaining equivalent faults, this should not have a big impact.

[0079]

[0074] Referring back to Fig. 1, two control signals, the regular scan enable signal 180 and the diagnosis mode signal 190, are needed for activating various modes of the scan chains. The circuit typically has an input pin for or can locally generate the regular scan enable signal 180. The regular scan enable signal 180 may be referred to as a dynamic signal as it changes during the period of applying a test pattern: causing scan chains to change from the shift mode to the capture mode and then change back to the shift mode. If the diagnosis mode signal 190 needs to be changed as well, an additional input pin or an additional locally generated active signal is required. If the diagnosis mode signal 190 can be made as a static signal, i.e., no need to change during the period of applying a test pattern, it can be provided by a storage device and thus no extra pin is required. The control signal generation device 400 in Fig. 4 and the control signal generation device 500 in Fig. 5 are examples in which the diagnosis mode signal is a static signal as shown by the tables 470 and 570. The storage device may be implemented using a state element such as a register. With various implementations of the disclosed technology, the storage device may be a scan cell or a shadow register of a scan cell in the scan chains 110 or a test data register in an IJTAG network (IEEE Pl 687 Internal JTAG). If a scan cell in the scan chains 110 is used, the diagnosis mode signal 190 can be loaded with a test pattern. A scan cell can be used for this purpose because the diagnosis mode signal typically has no effect during the loading of the scan chain. In either the table 470 in Fig. 4 or the table 570 in Fig. 5, no matter what the value of the diagnosis mode signal is, the other three signals are the same for either the normal shift mode or the diagnosis shift mode.

[0080]

[0075] Fig. 9 illustrates an example of a scan cell 900 that can be used to implement a storage device for storing the diagnosis mode signal according to various embodiments of the disclosed technology. Like the scan cell 200 in Fig. 2, the scan cell 900 comprises a state element 910 and a two-way multiplexer 920. To make the scan cell 900 stable during the functional mode and the normal capture mode, the parallel output 960 of the scan cell 900 is connected to the parallel input 940. To avoid the stored diagnosis mode signal 980 being changed during the diagnosis capture mode if a circuit configuration like the one shown in Fig. 8 is used, the scan enable input 990 of the scan cell 900 is coupled to the output of an XOR gate 930 rather directly to a modified scan enable signal 950. The two inputs of the XOR gate 930 are the modified scan enable signal 950 and an inversioncontrol signal 970. Another way to avoid the problem is to let the scan cell 900 be controlled by a regular scan enable signal. Another way to avoid the stored diagnosis mode signal 980 being changed during either the functional mode or the normal capture mode or the diagnosis capture mode is to use a shadow register for the scan cell 900. The shadow register can be loaded with a bit “0” in both the functional mode and the normal test mode, can change to a bit “1” after being loading loaded with the first diagnosis test pattern, and then can change back to a bit “0” after the capture operation for the last diagnosis test pattern.

[0081] Chain Diagnosis Using Diagnosis Point Insertion

[0082]

[0076] As noted previously, the analysis of chain pattern responses not only can identify faulty scan chains but also may determine the fault model associated with each of the faulty scan chains. The fault models for scan chains can include stuck-at faults (stuck-at- 0 / stuck-at-l), slow faults (slow-to-rise / slow-to-fall / slow) and fast faults (fast-to-rise / fast- to-fall / fast). Slow faults are normally caused by setup-time violations while fast faults are normally caused by hold-time violations. The fault models often include a fault model reserved for those that can be assigned to none of the above fault models. With a specific fault model, a scan chain defect can also be modeled as a permanent fault (the fault happens for all shift cycles) or an intermittent fault (the fault only happens for a subset of shift cycles). Note that the defect itself is still permanent, but the fault model used to represent the defect is intermittent. An intermittent fault may be used to describe some characteristics for an un-modeled defect. For example, an intermittent stuck-at-0 fault refers to a defect that can cause some shift operations to fail as if a stuck-at-0 fault intermittently appears while which shift cycles may fail is not known. Fig. 10 illustrates a table 1000 that shows a chain pattern and chain pattern responses of a faulty scan chain for the above eight permanent fault models. The faulty scan chain has 12 scan cells and the chain pattern is 001100110011 where the leftmost bit is loaded into scan cell No. 11 and the rightmost bit is loaded into scan cell No. 0. By comparing unloaded chain pattern responses with those listed in the table 1000, one can identify the fault model associated with the faulty scan chain. Fig. 10 is just an example. Other types of fault models may also be included in the table.

[0077] Fig. 11 A illustrates a flowchart 1100 showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a stuck-at-v fault that may be implemented according to various examples of the disclosed technology. Fig. 1 IB illustrates a diagram 1105 corresponding to the process shown by the flowchart 1100. Here, the number “v” can be “0” or “1”.

[0083]

[0078] In operation 1110, a test pattern is shifted into scan chains to load a bit of “v” into a scan cell (K + 1) in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of a scan cell K. A controllable inverting device 1145 is inserted between a serial output of the scan cell K+ 1) and a serial input of the scan cell K and is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal 1155.

[0084]

[0079] In operation 1120, a capture operation is performed for one clock cycle. Here, the scan cell K is configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by the controllable inverting device 1145. The diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig. 1 IB. At least a scan enable input of the scan cell K is coupled to a modified scan enable signal 1165. The scan enable input of the scan cell K + 1) can be coupled to the modified scan enable signal 1165 as shown in Fig. 8 or to the regular scan enable signal as shown in Fig 7. The modified scan enable signal 1165 and the inversion-control signal 1155 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig. 4 or Fig. 5.

[0085]

[0080] In operation 1130, the bit of “1 - v” captured by the scan cell AT is shifted out to determine whether the scan cell K has a stuck-at-v fault at output side. If the shifted-out bit is “ 1 - v”, no stuck-at-v fault is at output side of the scan cell K and the stuck-at-v fault should be at output side of an upstream scan cell for the scan cell K. Otherwise, the stuck-at-v fault is at the output side of the scan cell K. It should be noted that the process shown by the flowchart 1100 can be used to determine whether the scan cell K has a stuck-at-v fault at input side. This is equivalent to determining whether the scan cell (K + 1) has a stuck-at- v fault at output side. In such a case, the controllable inverting device 1145 is inserted in front of the scan cell (K + 1) instead of the scan cell K.

[0086]

[0081] Fig. 12A illustrates a flowchart 1200 showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a slow-to-fall / rise fault that may be implemented according to various examples of the disclosed technology. Fig. 12B illustrates a diagram 1205 corresponding to the process shown by the flowchart 1200. To save space, the diagram 1205 does not include the unloading operation in the diagnosis shift mode. A bit captured by a downstream scan cell for the scan cell at issue will not be changed after being unloaded because all downstream scan cells should be fault-free (assuming only one scan cell is faulty in one scan chain). Here, the number “v” can be “0” or “1”. If the number “v” is “0”, the fault to be located is a slow-to-rise fault. Otherwise, the fault to be located is a slow-to-fall fault.

[0087]

[0082] In operation 1210, a test pattern is shifted into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of the scan cell K. A controllable inverting device 1245 is inserted between a serial output of the scan cell K + 1) and a serial input of the scan cell K and is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal 1255.

[0088]

[0083] In operation 1220, a capture operation is performed for each of two clock cycles. The scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode for each of two clock cycles - the scan cell K capturing the inverted version of a bit received by the controllable inverting device 1245 while the scan cell (K- 1) capturing a bit outputted by the scan cell K. The diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig. 12B. At least scan enable inputs of the scan cells K and (K - 1) are coupled to a modified scan enable signal 1265. The scan enable input of the scan cell (K + 1) can be coupled to the modified scan enable signal 1265 as shown in Fig. 8 or to the regular scan enable signal as shown in Fig 7. The modified scan enable signal 1265 and the inversion-control signal 1255 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig. 4 or Fig. 5.

[0089]

[0084] In operation 1230, a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles is shifted out to determine whether the scan cell K has a slow-to-fall / rise fault at output side. If the shifted-out bit is “1 - v”, no slow-to-fall / rise fault is at output side of the scan cell K and the slow-to-fall / rise fault should be at output side of a upstream scan cell for the scan cell K. If the shifted-out bit is “v”, the scan cell K has a slow-to- fall / rise fault (y = 1, slow-to-fall fault; v = 0, slow-to-rise fault) at output side. It should be noted that the process shown by the flowchart 1200 can be used to determine whether the scan cell K has a slow-to-fall / rise fault at input side, which is equivalent to determining whether the scan cell (K + 1) has a slow-to-fall / rise fault at output side. In such a case, the controllable inverting device 1245 is inserted in front of the scan cell (K + 1), rather than the scan cell K.

[0090]

[0085] Fig. 13A illustrates a flowchart 1300 showing a process of using diagnosis point insertion to determine whether a scan cell or its upstream scan cells has a fast-to-fall / rise fault that may be implemented according to various examples of the disclosed technology. Fig. 13B illustrates a diagram 1305 corresponding to the process shown by the flowchart 1300. To save space, the diagram 1305 does not include the unloading operation in the diagnosis shift mode. A bit captured by a downstream scan cell for the scan cell at issue will not be changed after being unloaded because all downstream scan cells should be fault-free (assuming only one scan cell is faulty in one scan chain). Here, the number “v” can be “0” or “1”. If the number “v” is “0”, the fault to be located is a fast-to-rise fault. Otherwise, the fault to be located is a fast-to-fall fault.

[0091]

[0086] In operation 1310, a test pattern is shifted into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains. The scan cell (K + 1) is an upstream neighboring scan cell of the scan cell K. A controllable inverting device 1345 is inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal 1355.

[0087] In operation 1320, a capture operation is performed for one clock cycle. The scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K - 1) capturing a bit outputted by the scan cell K. The diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, both of which are not shown in Fig. 13B. At least scan enable inputs of the scan cells K and (K - 1) are coupled to a modified scan enable signal 1365. The scan enable input of the scan cell (K + 1) can be coupled to the modified scan enable signal 1365 as shown in Fig. 8 or to the regular scan enable signal as shown in Fig 7. The modified scan enable signal 1365 and the inversion-control signal 1355 are derived based on the regular scan enable signal and the diagnosis mode signal like the examples shown in Fig. 4 or Fig. 5.

[0092]

[0088] In operation 1330, a bit captured by the scan cell (K- 1) at the one second clock cycle in the two clock cycles is shifted out to determine whether the scan cell K has a fast-to- fall / rise fault at output side. If the shifted-out bit is “v”, no fast-to-fall / rise fault is at output side of the scan cell K and the fast-to-fall / rise fault should be at output side of a upstream scan cell for the scan cell K. If the shifted-out bit is “ 1 - v”, the scan cell K has a fast-to-fall / rise fault (v = 1, fast-to-fall fault; v = 0, fast-to-rise fault) at output side. It should be noted that the process shown by the flowchart 1300 can be used to determine whether the scan cell K has a fast-to-fall / rise fault at input side, which is equivalent to determining whether the scan cell (K + 1) has a fast-to-fall / rise fault at output side. In such a case, the controllable inverting device 1345 is inserted in front of the scan cell (K + 1), rather than the scan cell K.

[0093]

[0089] The methods illustrated in Figs. 11A-B, 12A-B, 13A-B are applicable when the controllable inverting device (1145, 1245, 1345) and the scan cell K are in a single device. One or both of the scan cells (X- 1), (K + 1) may be included in the single device as well to form a multi-bit scan cell. These methods are also applicable if one or both of the scan cells (K - 1), (K + 1) have a controllable inverting device placed in front of them. The only difference is a switch between the good-machine bit and the failing bit for the methods described in Figs. 12A-B, 13A-B when a controllable inverting device is placed in front of the scan cell (K - 1) and is controlled by the same inversion-control signal (1255, 1355).

[0094] Illustrative Operating Environment

[0095]

[0090] Various examples of the disclosed technology may be implemented through the execution of software instructions by a computing device, such as a programmable computer. Accordingly, Fig. 14 shows an illustrative example of a computing device 1401. As seen in this figure, the computing device 1401 includes a computing unit 1403 with a processing unit 1405 and a system memory 1407. The processing unit 1405 may be any type of programmable electronic device for executing software instructions, but it will conventionally be a microprocessor. The system memory 1407 may include both a read-only memory (ROM) 1409 and a random access memory (RAM) 1411. As will be appreciated by those of ordinary skill in the art, both the read-only memory (ROM) 1409 and the random access memory (RAM) 1411 may store software instructions for execution by the processing unit 1405.

[0096]

[0091] The processing unit 1405 and the system memory 1407 are connected, either directly or indirectly, through a bus 1413 or alternate communication structure, to one or more peripheral devices. For example, the processing unit 1405 or the system memory 1407 may be directly or indirectly connected to one or more additional memory storage devices, such as a “hard” magnetic disk drive 1415, a removable magnetic disk drive 1417, an optical disk drive 1419, or a flash memory card 1421. The processing unit 1405 and the system memory 1407 also may be directly or indirectly connected to one or more input devices 1423 and one or more output devices 1425. The input devices 1423 may include, for example, a keyboard, a pointing device (such as a mouse, touchpad, stylus, trackball, or joystick), a scanner, a camera, and a microphone. The output devices 1425 may include, for example, a monitor display, a printer and speakers. With various examples of the computer 1401, one or more of the peripheral devices 1415-1425 may be internally housed with the computing unit 1403. Alternately, one or more of the peripheral devices 1415-1425 may be external to the housing for the computing unit 1403 and connected to the bus 1413 through, for example, a Universal Serial Bus (USB) connection.

[0097]

[0092] With some implementations, the computing unit 1403 may be directly or indirectly connected to one or more network interfaces 1427 for communicating with other devices making up a network. The network interface 1427 translates data and control signals from the computing unit 1403 into network messages according to one or more communication protocols, such as the transmission control protocol (TCP) and the Internet protocol (IP). Also, the interface 1427 may employ any suitable connection agent (or combination of agents) for connecting to a network, including, for example, a wireless transceiver, a modem, or an Ethernet connection. Such network interfaces and protocols are well known in the art, and thus will not be discussed here in more detail.

[0098]

[0093] It should be appreciated that the computer 1401 is illustrated as an example only, and it is not intended to be limiting. Various embodiments of the disclosed technology may be implemented using one or more computing devices that include the components of the computer 1401 illustrated in Fig. 14, which include only a subset of the components illustrated in Fig. 14, or which include an alternate combination of components, including components that are not shown in Fig. 14. For example, various embodiments of the disclosed technology may be implemented using a multi-processor computer, a plurality of single and / or multiprocessor computers arranged into a network, or some combination of both.

[0099] Conclusion

[0100]

[0094] Having illustrated and described the principles of the disclosed technology, it will be apparent to those skilled in the art that the disclosed embodiments can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of the disclosed technologies can be applied, it should be recognized that the illustrated embodiments are only preferred examples of the technologies and should not be taken as limiting the scope of the disclosed technology. Rather, the scope of the disclosed technology is defined by the following claims and their equivalents. We therefore claim as our disclosed technology all that comes within the scope and spirit of these claims.

Claims

What is claimed is:

1. A circuit, comprising: scan chains, one of the scan chains comprising a pair of neighboring scan cells formed by a scan cell (K + 1) and a scan cell K and a controllable inverting device inserted into a shift path of the one of the scan chains and between a serial output of the scan cell (K + 1) and a serial input of the scan cell A, numbers (K + 1) and K being scan cell indices, wherein the scan cell K being selected for the insertion of the controllable inverting device is determined based on a diagnosis coverage analysis process, wherein a modified scan enable signal serves as a scan enable signal for at least the scan cell K, the modified scan enable signal being derived based on a diagnosis mode signal and a regular scan enable signal, wherein the controllable inverting device is configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal, and wherein the scan cell K is configured to operate in one of a plurality of test-related modes based on the regular scan enable signal and the diagnosis mode signal while the circuit is being tested, the plurality of test-related modes comprising a diagnosis capture mode in which the scan cell K is configured to capture the inverted version of a bit received at the data input of the controllable inverting device.

2. The circuit recited in claim 1, wherein the diagnosis mode signal is provided by a storage device in the circuit.

3. The circuit recited in claim 2, wherein the storage device is a scan cell or a shadow register of a scan cell in one of the scan chains.

4. The circuit recited in claim 1, wherein the diagnosis coverage analysis process comprises design rule checking, diagnosability analysis, test pattern generation for diagnosis, or any combination thereof.

5. The circuit recited in claim 1, wherein the modified scan enable signal further serves as a scan enable signal for a scan cell that is a downstream neighboring scan cell for the scan cell K on the one of the scan chains.

6. The circuit recited in claim 1, wherein the modified scan enable signal further serves as a scan enable signal for all scan cells of the scan chains except a scan cell configured to store the diagnosis mode signal.

7. The circuit recited in claim 1, wherein the modified scan enable signal is derived by a logical OR operation of the diagnosis mode signal and the regular scan enable signal.

8. The circuit recited in claim 1, wherein the inversion-control signal is derived by inverting the regular scan enable signal.

9. The circuit recited in claim 1, wherein the inversion-control signal is derived by a logical AND operation of the diagnosis mode signal and a signal derived by inverting the regular scan enable signal.

10. The circuit recited in claim 1, wherein the controllable inverting device is an XOR gate.

11. The circuit recited in claim 1, wherein the scan cell K and the controllable inverting device are in a single device.

12. A method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into a scan cell (K + 1) in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of a scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for one clock cycle, the scan cell K being configured to operate in a diagnosis captured mode - capturing a bit of “1 - v” outputted by the controllable inverting device, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least a scan enable input of the scan cell K is coupled to a modified scan enable signal, and wherein themodified scan enable signal and the inversion-control signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out the bit of “ 1 - v” captured by the scan cell K to determine whether the scan cell K has a stuck-at-v fault at output side.

13. A method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for each of two clock cycles, wherein for each of the two clock cycles, the scan cell K and a scan cell (K- 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell K- 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least scan enable inputs of the scan cells K and (K- 1) are coupled to a modified scan enable signal, and wherein the modified scan enable signal and the inversion-control signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out a bit captured by the scan cell (K - 1) at a second clock cycle in the two clock cycles to determine whether the scan cell K has a slow-to-fall / rise fault at output side.

14. A method for scan chain diagnosis, comprising: shifting a test pattern into scan chains to load a bit of “v” into each of scan cells (K + 1) and K in one of the scan chains, the scan cell (K + 1) being an upstream neighboring scan cell of the scan cell K, a controllable inverting device being inserted between a serial output of the scan cell (K + 1) and a serial input of the scan cell K and being configured to output an inverted version or an original version of a bit received at a data input of the controllable inverting device based on an inversion-control signal; performing a capture operation for one clock cycle, wherein the scan cell K and a scan cell K- 1) are configured to operate in a diagnosis captured mode - the scan cell K capturing the inverted version of a bit received by the controllable inverting device while the scan cell (K - 1) capturing a bit outputted by the scan cell K, wherein the diagnosis captured mode is activated based a regular scan enable signal and a diagnosis mode signal that is supplied by a storage device, wherein at least scan enable inputs of the scan cells K and (K- 1) are coupled to a modified scan enable signal, and wherein the modified scan enable signal and the inversioncontrol signal are derived based on the regular scan enable signal and the diagnosis mode signal; and shifting out a bit captured by the scan cell (K - 1) at the one clock cycle to determine whether the scan cell K has a fast-to-fall / rise fault at output side.

Images