Display panel and display device

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display device. The display panel comprises pixel driving circuits and light-emitting units, which are distributed in an array. The display panel further comprises: a base substrate; a fifth conductive layer, which is located on one side of the base substrate; an electrode layer, which is located on the side of the fifth conductive layer facing away from the base substrate and comprises a plurality of electrode portions, wherein the electrode portions are used for forming first electrodes of the light-emitting units; and a pixel definition layer, which is located on the side of the electrode layer facing away from the base substrate, wherein a plurality of pixel openings are formed in the pixel definition layer, the pixel openings are arranged corresponding to the electrode portions, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of corresponding electrode portions on the base substrate. Each pixel driving circuit comprises: a third conductive portion, which is used for providing a high-level power source signal and is located on the fifth conductive layer, wherein the orthographic projection of the third conductive portion on the base substrate at least partially overlapping the orthographic projection of an electrode portion on the base substrate; a first missing portion is formed on the third conductive portion, and the first missing portion is at least partially located in a light-transmitting area of the display panel; and a pattern formed by a combination of the orthographic projection of the first missing portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate is symmetrically arranged relative to a first axis of symmetry, and the orthographic projection of the third conductive portion on the base substrate is asymmetrically arranged relative to the first axis of symmetry. The display panel provided in the present disclosure has relatively high light transmittance. (FIG. 20)

Description

Display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] In the related art, the light transmittance of the display panel is low, which leads to problems such as slow optical fingerprint unlocking speed of the display panel.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a display panel is provided, comprising a pixel driving circuit and a light-emitting unit distributed in an array, and further comprising:

[0006] substrate;

[0007] a fifth conductive layer, located on one side of the base substrate;

[0008] an electrode layer, located on a side of the fifth conductive layer facing away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit;

[0009] a pixel definition layer, located on a side of the electrode layer facing away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings are correspondingly arranged to the electrode portions, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate;

[0010] The pixel driving circuit includes:

[0011] a third conductive portion, the third conductive portion being configured to provide a high-level power signal, the third conductive portion being located in the fifth conductive layer, and an orthographic projection of the third conductive portion on the base substrate at least partially overlapping with an orthographic projection of the electrode portion on the base substrate;

[0012] A first missing portion is formed on the third conductive portion, and the first missing portion is at least partially located in the light-transmitting area of ​​the display panel;

[0013] The figure formed by the orthographic projection of the first missing portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate is symmetrically arranged relative to the first symmetry axis, and the orthographic projection of the third conductive portion on the base substrate is asymmetrically arranged relative to the first symmetry axis.

[0014] In an exemplary embodiment of the present disclosure, the plurality of electrode portions include a first electrode portion, and an orthographic projection of the first electrode portion on the base substrate is located within an orthographic projection of the third conductive portion on the base substrate.

[0015] In an exemplary embodiment of the present disclosure, the first missing portion includes a notch formed on an edge of the third conductive portion and / or a hollow portion formed on the third conductive portion.

[0016] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0017] a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a first power line, the first power line being connected to the third conductive portion through a via;

[0018] In which, a second missing portion is formed on the first power line, and the orthographic projection of the second missing portion on the base substrate and the orthographic projection of the first missing portion on the base substrate at least partially overlap, and the overlapping portion of the orthographic projection of the second missing portion on the base substrate and the orthographic projection of the first missing portion on the base substrate is at least partially located in the light-transmitting area of ​​the display panel.

[0019] In an exemplary embodiment of the present disclosure, a figure formed by a combination of an orthographic projection of the second missing portion on the base substrate and an orthographic projection of the first power line on the base substrate is symmetrically arranged relative to a second symmetry axis, and an orthographic projection of the first power line on the base substrate is asymmetrically arranged relative to the second symmetry axis;

[0020] The second symmetry axis is parallel to or coincides with the first symmetry axis.

[0021] In an exemplary embodiment of the present disclosure, the plurality of electrode portions include a first electrode portion, and an orthographic projection of the first electrode portion on the base substrate is located within an orthographic projection of the first power line on the base substrate.

[0022] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes an oxide transistor, and the display panel further includes:

[0023] a second conductive layer, located between the base substrate and the fifth conductive layer;

[0024] a third conductive layer, located between the second conductive layer and the fifth conductive layer;

[0025] The pixel driving circuit further includes:

[0026] a third gate line located in the second conductive layer, wherein a portion of the third gate line is used to form a bottom gate of the oxide transistor;

[0027] a first gate line located in the third conductive layer, wherein a portion of the first gate line is used to form a top gate of the oxide transistor;

[0028] Wherein, the third gate line includes a first gate line segment and a second gate line segment connected thereto, and the first gate line includes a third gate line segment and a fourth gate line segment connected thereto;

[0029] The orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate extend in the same direction and at least partially overlap, and the orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate extend in the same direction and partially overlap;

[0030] The orthographic projection of the second gate line segment on the base substrate overlaps with the orthographic projection of at least part of other light shielding structures in the display panel except the fourth gate line segment on the base substrate;

[0031] The orthographic projection of the fourth gate line segment on the base substrate overlaps with the orthographic projection of at least part of other light-shielding structures in the display panel except the second gate line segment on the base substrate.

[0032] The orthographic projection of the second gate line segment on the base substrate at least partially overlaps with the orthographic projection of at least part of the light shielding structure in the display panel except the second gate line segment on the base substrate;

[0033] The orthographic projection of the fourth gate line segment on the base substrate at least partially overlaps with the orthographic projection of at least part of the light shielding structure in the display panel except the fourth gate line segment on the base substrate.

[0034] In an exemplary embodiment of the present disclosure, the overlapping portion of the orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate has a size L5 perpendicular to the extension direction of the first gate line segment, and the overlapping portion of the orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate has a size L6 perpendicular to the extension direction of the second gate line segment, and L5 is greater than L6.

[0035] In an exemplary embodiment of the present disclosure, L5 / L6 is greater than 1 and less than or equal to 3 / 2.

[0036] In an exemplary embodiment of the present disclosure, the first gate line segment includes a first side and a second side extending along the extension direction thereof and arranged opposite to each other, the second gate line segment includes a third side and a fourth side extending along the extension direction thereof and arranged opposite to each other, the third gate line segment includes a fifth side and a sixth side extending along the extension direction thereof and arranged opposite to each other, and the fourth gate line segment includes a seventh side and an eighth side extending along the extension direction thereof and arranged opposite to each other;

[0037] The first side and the third side are located on the same side of the third gate line, the second side and the fourth side are located on the same side of the third gate line, the fifth side and the seventh side are located on the same side of the first gate line, and the sixth side and the eighth side are located on the same side of the first gate line;

[0038] The orthographic projection of the seventh side on the substrate is located between the orthographic projection of the third side on the substrate and the orthographic projection of the fourth side on the substrate, and the orthographic projection of the fourth side on the substrate is located between the orthographic projection of the seventh side on the substrate and the orthographic projection of the eighth side on the substrate;

[0039] The orthographic projection of the second side on the substrate is located between the orthographic projection of the fifth side on the substrate and the orthographic projection of the sixth side on the substrate, and the orthographic projection of the fifth side on the substrate is located between the orthographic projection of the first side on the substrate and the orthographic projection of the second side on the substrate;

[0040] The distance between the orthographic projection of the eighth side on the substrate and the orthographic projection of the fourth side on the substrate is L1, the distance between the orthographic projection of the sixth side on the substrate and the orthographic projection of the second side on the substrate is L2, the distance between the orthographic projection of the third side on the substrate and the orthographic projection of the seventh side on the substrate is L3, and the distance between the orthographic projection of the first side on the substrate and the orthographic projection of the fifth side on the substrate is L4;

[0041] Wherein, L1 is greater than L2, and / or L3 is greater than L4.

[0042] In an exemplary embodiment of the present disclosure, L2 / L1 is greater than or equal to 0 and less than or equal to 2 / 3, and / or L4 / L3 is greater than or equal to 0 and less than or equal to 1 / 2.

[0043] In an exemplary embodiment of the present disclosure, the third gate line segment includes a sixth side extending along its extension direction, and an orthographic projection of the sixth side on the substrate does not overlap with an orthographic projection of the first gate line segment on the substrate;

[0044] The distance between the orthographic projection of the sixth side on the substrate and the orthographic projection of the first gate line segment on the substrate is L2, and the size of the overlapping part of the orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate perpendicular to the extension direction of the first gate line segment is L5, and L2 / L5 is greater than or equal to 0 and less than or equal to 1 / 2.

[0045] In an exemplary embodiment of the present disclosure, the orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate are staggered in a direction perpendicular to an extending direction of the second gate line segment;

[0046] The orthographic projection of the first gate line segment on the substrate is located within the orthographic projection of the third gate line segment on the substrate;

[0047] And / or, the orthographic projection of the third gate line segment on the base substrate is located within the orthographic projection of the first gate line segment on the base substrate.

[0048] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0049] a data line, the data line being used to provide a data signal to the pixel driving circuit;

[0050] The orthographic projection of the first gate line segment on the base substrate and the orthographic projection of the third gate line segment on the base substrate are both located between the orthographic projection of the data line on the base substrate and the orthographic projection of the third conductive portion on the base substrate;

[0051] The orthographic projection of the second gate line segment on the base substrate and the orthographic projection of the fourth gate line segment on the base substrate at least partially overlap with the orthographic projection of the data line on the base substrate.

[0052] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate electrode of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor;

[0053] The second transistor forms the oxide transistor.

[0054] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0055] a first conductive layer, located between the base substrate and the fifth conductive layer;

[0056] The pixel driving circuit further includes a second gate line, the second gate line is located in the first conductive layer, the second gate line includes a fifth gate line segment and a sixth gate line segment connected to each other, an orthographic projection of the fifth gate line segment on the base substrate and an orthographic projection of the sixth gate line segment on the base substrate extend along a first direction and are staggered in a second direction, and the first direction and the second direction intersect;

[0057] The fifth gate line segment includes a ninth side, the sixth gate line segment includes a tenth side, the ninth side and the tenth side are located on the same side of the second gate line, and the orthographic projection of the ninth side on the substrate and the orthographic projection of the tenth side on the substrate extend along the first direction and are spaced apart in the second direction;

[0058] The virtual extension line of the orthographic projection of the ninth side on the base substrate in the first direction includes a first virtual line segment, the orthographic projection of the tenth side on the base substrate and the first virtual line segment are arranged relative to each other in the second direction, and the area between the orthographic projection of the tenth side on the base substrate and the first virtual line segment is at least partially located in the light-transmitting area of ​​the display panel.

[0059] In an exemplary embodiment of the present disclosure, the fifth gate line segment further includes an eleventh side opposite to the ninth side, and the sixth gate line segment further includes a twelfth side opposite to the tenth side;

[0060] In the second direction, the orthographic projection of the eleventh side on the base substrate is located between the orthographic projection of the tenth side on the base substrate and the orthographic projection of the twelfth side on the base substrate;

[0061] In the second direction, the orthographic projection of the tenth side on the base substrate is located between the orthographic projection of the ninth side on the base substrate and the orthographic projection of the eleventh side on the base substrate.

[0062] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a fourth transistor and a driving transistor, wherein a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor;

[0063] An orthographic projection of the second gate line on the substrate extends along a first direction, and a portion of the second gate line is used to form a gate of the fourth transistor.

[0064] In an exemplary embodiment of the present disclosure, the first conductive layer further includes:

[0065] A first conductive portion is used to form a gate of the driving transistor, and an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the sixth gate line segment on the base substrate are arranged opposite to each other in the second direction.

[0066] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a driving transistor, a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor;

[0067] The first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the first reset signal line;

[0068] The first electrode of the fifth transistor is connected to the first power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line;

[0069] The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light emitting unit, and the gate is connected to the second reset signal line;

[0070] A first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode is connected to the first electrode of the driving transistor;

[0071] The orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row of pixel driving circuits on the substrate at least partially overlap;

[0072] The orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset signal line in the adjacent next row of pixel driving circuits on the substrate;

[0073] The orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the enable signal line in the pixel driving circuit of the current row on the substrate.

[0074] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes:

[0075] driver transistor;

[0076] a first transistor, a first electrode of which is connected to the first initial signal line, and a second electrode of which is connected to the second electrode of the driving transistor;

[0077] a second transistor, a first electrode of which is connected to the gate electrode of the driving transistor, and a second electrode of which is connected to the second electrode of the driving transistor;

[0078] a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0079] a fifth transistor, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the driving transistor;

[0080] a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit;

[0081] a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the first electrode of the light-emitting unit;

[0082] an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor;

[0083] a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line;

[0084] The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

[0085] In an exemplary embodiment of the present disclosure, the pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes:

[0086] a first active layer, located between the base substrate and the fifth conductive layer, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit;

[0087] a first conductive layer, located between the first active layer and the fifth conductive layer, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit;

[0088] a second conductive layer, located between the first conductive layer and the fifth conductive layer, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit;

[0089] a second active layer, located between the second conductive layer and the fifth conductive layer, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit;

[0090] a third conductive layer, located between the second active layer and the fifth conductive layer, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit;

[0091] The fourth conductive layer is located between the third conductive layer and the fifth conductive layer, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

[0092] In an exemplary embodiment of the present disclosure, the display panel further includes:

[0093] a shielding layer located between the base substrate and the fifth conductive layer, the shielding layer comprising a plurality of shielding portions arrayed along a first direction and a second direction, and a second connecting portion connected between adjacent shielding portions, wherein the first direction and the second direction intersect;

[0094] a first active layer, located between the blocking layer and the fifth conductive layer, the first active layer comprising a third active portion and a seventeenth active portion, the third active portion being configured to form a channel region of the driving transistor, and an orthographic projection of the blocking portion on the base substrate and an orthographic projection of the third active portion on the base substrate at least partially overlapping;

[0095] a second bridging portion connected to the seventeenth active portion through a via hole;

[0096] The second connecting portion includes a first extending portion and a second extending portion, wherein a dimension of an orthographic projection of the second extending portion on the base substrate in a direction perpendicular to the extending direction thereof is greater than a dimension of an orthographic projection of the first extending portion on the base substrate in a direction perpendicular to the extending direction thereof;

[0097] An orthographic projection of a via hole connected between the second bridging portion and the seventeenth active portion on the base substrate is located within an orthographic projection of the second extending portion on the base substrate.

[0098] According to one aspect of the present disclosure, a display panel is provided, comprising a pixel driving circuit and a light-emitting unit distributed in an array, and further comprising:

[0099] substrate;

[0100] a fifth conductive layer, located on one side of the base substrate;

[0101] an electrode layer, located on a side of the fifth conductive layer facing away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit;

[0102] a pixel definition layer, located on a side of the electrode layer facing away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings are correspondingly arranged to the electrode portions, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate;

[0103] The pixel driving circuit includes:

[0104] a third conductive portion, the third conductive portion being configured to provide a high-level power signal, the third conductive portion being located in the fifth conductive layer, and an orthographic projection of the third conductive portion on the base substrate at least partially overlapping with an orthographic projection of the electrode portion on the base substrate;

[0105] The overlapping area of ​​the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of other light shielding structures in the display panel except the third conductive portion on the base substrate is S1, and the area of ​​the orthographic projection of the third conductive portion on the base substrate is S2;

[0106] Among them, S1 / S2 is greater than or equal to 0.9 and less than or equal to 1.

[0107] According to one aspect of the present disclosure, a display device is provided, wherein the display device includes the above-mentioned display panel.

[0108] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0110] FIG1 is a schematic structural diagram of an exemplary embodiment of a pixel driving circuit disclosed herein;

[0111] FIG2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in FIG1 ;

[0112] FIG3 is a structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0113] FIG4 is a structural diagram of the shielding layer in FIG3 ;

[0114] FIG5 is a structural diagram of the first active layer in FIG3;

[0115] FIG6 is a structural diagram of the first conductive layer in FIG3 ;

[0116] FIG7 is a structural diagram of the second conductive layer in FIG3 ;

[0117] FIG8 is a structural diagram of the second active layer in FIG3;

[0118] FIG9 is a structural diagram of the third conductive layer in FIG3 ;

[0119] FIG10 is a structural diagram of the fourth conductive layer in FIG3;

[0120] FIG11 is a structural diagram of the fifth conductive layer in FIG3 ;

[0121] FIG12 is a structural diagram of the sixth conductive layer in FIG3;

[0122] FIG13 is a structural diagram of the electrode layer in FIG3 ;

[0123] FIG14 is a structural diagram of the shielding layer and the first active layer in FIG3;

[0124] FIG15 is a structural layout diagram of the shielding layer, the first active layer, and the first conductive layer in FIG3;

[0125] FIG16 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, and the second conductive layer in FIG3 ;

[0126] FIG17 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ;

[0127] FIG18 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ;

[0128] FIG19 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ;

[0129] FIG20 is a structural layout diagram of the shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ;

[0130] FIG21 is a structural layout diagram of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in FIG3 ;

[0131] FIG22 is a schematic structural diagram of a fifth conductive layer in another exemplary embodiment of the display panel of the present disclosure;

[0132] FIG23 is an enlarged view of a local area D in FIG18 ;

[0133] FIG24 is a partial enlarged view of area E in FIG6 ;

[0134] FIG25 is a partial cross-sectional view of the display panel shown in FIG3 taken along the dotted line FF. DETAILED DESCRIPTION

[0135] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0136] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0137] This exemplary embodiment first provides a pixel driving circuit, as shown in Figures 1 and 2. Figure 1 is a structural diagram of an exemplary embodiment of the pixel driving circuit disclosed in the present invention, and Figure 2 is a timing diagram of some nodes in an exemplary embodiment of the pixel driving circuit shown in Figure 1.

[0138] The pixel driving circuit may include: a driving transistor T3, a first transistor T1, a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a capacitor C. A first electrode of the fourth transistor T4 is connected to the data signal terminal Da, a second electrode of the fourth transistor T4 is connected to the first electrode of the driving transistor T3, and a gate of the fourth transistor T4 is connected to the second gate driving signal terminal G2; a first electrode of the fifth transistor T5 is connected to the first power supply terminal VDD, a second electrode of the fifth transistor T5 is connected to the first electrode of the driving transistor T3, and a gate of the fifth transistor T5 is connected to the enable signal terminal EM; a gate of the driving transistor T3 is connected to a node N; a first electrode of the second transistor T2 is connected to the node N, a second electrode of the second transistor T2 is connected to the second electrode of the driving transistor T3, and a gate of the second transistor T2 is connected to the first gate driving signal terminal G1; a first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and a second electrode of the sixth transistor T6 is connected to the seventh transistor T8. The second electrode of transistor T7 and the gate of the sixth transistor T6 are connected to the enable signal terminal EM, the first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, and the gate of the seventh transistor T7 is connected to the second reset signal terminal Re2; the first electrode of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second electrode of the first transistor T1 is connected to the second electrode of the driving transistor T3, and the gate of the first transistor T1 is connected to the first reset signal terminal Re1; the first electrode of the eighth transistor T8 is connected to the third initial signal terminal Vinit3, the second electrode of the eighth transistor T8 is connected to the first electrode of the driving transistor T3, and the gate of the eighth transistor T8 is connected to the second reset signal terminal Re2; the first electrode of the capacitor C is connected to the node N, and the second electrode of the capacitor C is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive a light-emitting unit OLED. The first electrode of the light-emitting unit OLED can be connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit can be connected to the second power supply terminal VSS. The first electrode of the light-emitting unit can be the anode of the light-emitting unit, and the second electrode of the light-emitting unit can be the cathode of the light-emitting unit. The second transistor T2 may be an N-type transistor, for example, an N-type metal oxide transistor. N-type transistors have a relatively low leakage current, thereby preventing leakage of power from the node N through the second transistor T2 during the light-emitting phase. Meanwhile, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type transistors, for example, P-type low-temperature polysilicon transistors. P-type transistors have a relatively high carrier mobility, thereby facilitating the realization of display panels with high resolution, high response speed, high pixel density, and high aperture ratio.The first initial signal terminal, the second initial signal terminal, and the third initial signal terminal can output the same or different voltage signals according to actual conditions.

[0139] As shown in Figure 2, where G1 represents the timing of the first gate drive signal terminal G1, G2 represents the timing of the second gate drive signal terminal G2, Re2 represents the timing of the second reset signal terminal Re2, Re1 represents the timing of the first reset signal terminal Re1, and EM represents the timing of the enable signal terminal EM, a driving cycle of the pixel driving circuit may include a first reset phase t1, a second reset phase t2, a data writing phase t3, a third reset phase t4, and a light-emitting phase t5.

[0140] During the first reset phase t1, the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 to improve the hysteresis problem of the driving transistor T3. During the second reset phase t2, the first gate drive signal terminal G1 outputs a high-level signal, the first reset signal terminal Re1 outputs a low-level signal, the first transistor T1 and the second transistor T2 are turned on, and the first initial signal terminal Vinit1 inputs the first initial signal to the node N through the first transistor T1 and the second transistor T2. During the data writing phase t3, the second gate drive signal terminal G2 outputs a low-level signal, the first gate drive signal terminal G1 outputs a high-level signal, the fourth transistor T4 and the second transistor T2 are turned on, and the data signal terminal Da writes the compensation voltage Vdata+Vth to the node N through the fourth transistor T4 and the second transistor T2, where Vdata is the voltage of the data signal on the data signal terminal and Vth is the threshold voltage of the driving transistor T3. In the third reset phase t4: the second reset signal terminal RE2 outputs a low-level signal, the seventh transistor T7 and the eighth transistor T8 are turned on, the second initial signal terminal Vinit2 inputs the second initial signal to the first electrode of the light-emitting unit OLED, and the third initial signal terminal Vinit3 inputs the third initial signal to the first electrode of the driving transistor T3. In the light-emitting phase t5: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the compensation voltage Vdata + Vth stored in the capacitor C. The output current formula of the driving transistor is as follows: I = (μWCox / 2L)(Vgs-Vth) 2

[0141] Where I is the output current of the driver transistor; μ is the carrier mobility; Cox is the gate capacitance per unit area, W is the width of the driver transistor channel, L is the length of the driver transistor channel, Vgs is the gate-source voltage difference of the driver transistor, and Vth is the threshold voltage of the driver transistor. The output current of the driver transistor in the above pixel driving circuit is I = (μWCox / 2L)(Vdata+Vth-Vdd-Vth) 2 The pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0142] This exemplary embodiment further provides a display panel, which may include a base substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, and an electrode layer stacked in sequence. Insulating layers may be provided between adjacent layers. As shown in Figures 3-21, Figure 3 is a structural layout of an exemplary embodiment of the display panel disclosed herein, Figure 4 is a structural layout of the blocking layer in Figure 3, Figure 5 is a structural layout of the first active layer in Figure 3, Figure 6 is a structural layout of the first conductive layer in Figure 3, Figure 7 is a structural layout of the second conductive layer in Figure 3, Figure 8 is a structural layout of the second active layer in Figure 3, Figure 9 is a structural layout of the third conductive layer in Figure 3, Figure 10 is a structural layout of the fourth conductive layer in Figure 3, Figure 11 is a structural layout of the fifth conductive layer in Figure 3, Figure 12 is a structural layout of the sixth conductive layer in Figure 3, Figure 13 is a structural layout of the electrode layer in Figure 3, Figure 14 is a structural layout of the blocking layer and the first active layer in Figure 3, Figure 15 is a structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 3, and Figure 16 is a structural layout of the blocking layer, the first active layer, and the first conductive layer in Figure 3. FIG17 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer in FIG3 ; FIG18 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer in FIG3 ; FIG19 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer in FIG3 ; FIG20 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer in FIG3 ; FIG21 is a structural layout of the blocking layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer in FIG3 . The display panel may include a plurality of pixel driving circuits shown in FIG1 . As shown in FIG21 , the display panel may include a plurality of pixel units distributed in a first direction X and a second direction Y. The pixel units may include a first pixel driving circuit Pix1 and a second pixel driving circuit Pix2 adjacently distributed in the first direction X. At least portions of the structures of the first pixel driving circuit Pix1 and the second pixel driving circuit Pix2 may be arranged in mirror symmetry about a mirror symmetry plane AA. The mirror symmetry plane AA may be perpendicular to the substrate. Furthermore, the orthographic projection of the first pixel driving circuit Pix1 and the orthographic projection of the second pixel driving circuit Pix2 on the substrate may be at least partially arranged in symmetry about the intersection of the mirror symmetry plane AA and the substrate as an axis of symmetry. The first direction X and the second direction Y intersect. For example, the first direction X may be a row direction, and the second direction Y may be a column direction.

[0143] As shown in FIG. 3 , 4 and 14 , the shielding layer includes a plurality of shielding portions 81 distributed in an array along the first direction X and the second direction Y, and the shielding portions 81 are connected to each other.

[0144] As shown in Figures 3, 5, and 15, the first active layer may include: a first active portion 71, a third active portion 73, a fourth active portion 74, a fifth active portion 75, a sixth active portion 76, a seventh active portion 77, an eighth active portion 78, a ninth active portion 79, a tenth active portion 710, an eleventh active portion 711, a twelfth active portion 712, a thirteenth active portion 713, a fourteenth active portion 714, a fifteenth active portion 715, a sixteenth active portion 716, a seventeenth active portion 717, and an eighteenth active portion 718. The first active portion 71 is used to form the channel region of the first transistor T1; the third active portion 73 can be used to form the channel region of the driving transistor T3; the fourth active portion 74 can be used to form the channel region of the fourth transistor T4; the fifth active portion 75 can be used to form the channel region of the fifth transistor T5; the sixth active portion 76 can be used to form the channel region of the sixth transistor T6; the seventh active portion 77 can be used to form the channel region of the seventh transistor T7; the eighth active portion 78 can be used to form the channel region of the eighth transistor T8; the ninth active portion 79 is connected between the third active portion 73 and the sixth active portion 76; the tenth active portion 710 and the tenth active portion 720 are connected to each other. The twelfth active portion 712 is connected to both ends of the eighth active portion 78; the eleventh active portion 711 is connected between the fourth active portion 74 and the third active portion 73; the thirteenth active portion 713 is connected to a side of the fourth active portion 74 away from the third active portion 73; the fourteenth active portion 714 is connected to a side of the seventh active portion 77 away from the sixth active portion 76; the fifteenth active portion 715 is connected to a side of the fifth active portion 75 away from the third active portion 73; the sixteenth active portion 716 is connected between the seventh active portion 77 and the sixth active portion 76; and the seventeenth active portion 717 and the eighteenth active portion 718 are connected to both ends of the first active portion 71. The first active layer may be formed of polysilicon material. Accordingly, the first transistor T1, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 may be P-type low-temperature polysilicon thin film transistors.

[0145] The orthographic projection of the shielding portion 81 on the substrate can at least partially overlap with the orthographic projection of the third active portion 73 on the substrate. The shielding portion 81 can shield the third active portion 73 from light, thereby improving the stability of the output characteristics of the driving transistor. The shielding layer can be a conductive structure and can be connected to a stable voltage source to provide signal shielding for the pixel driving circuit.

[0146] As shown in Figures 3, 6, and 15, the first conductive layer may include: a first conductive portion 11, a second gate line G2, an enable signal line EM, a first reset signal line Re1, and a second reset signal line Re2. The second gate line G2 can be used to provide the second gate drive signal terminal in Figure 1; the enable signal line EM can be used to provide the enable signal terminal in Figure 1; the first reset signal line Re1 can be used to provide the first reset signal terminal in Figure 1; and the second reset signal line Re2 can be used to provide the second reset signal terminal in Figure 1. The orthographic projection of the second gate line G2 on the base substrate, the orthographic projection of the enable signal line EM on the base substrate, the orthographic projection of the first reset signal line Re1 on the base substrate, and the orthographic projection of the second reset signal line Re2 on the base substrate can all extend along the first direction X. The orthographic projection of the second gate line G2 on the base substrate covers the orthographic projection of the fourth active portion 74 on the base substrate, and a portion of the structure of the second gate line G2 is used to form the gate of the fourth transistor. The orthographic projection of the enable signal line EM on the substrate overlaps the orthographic projection of the fifth active portion 75 and the orthographic projection of the sixth active portion 76 on the substrate. Portions of the enable signal line EM can be used to form the gates of the fifth transistor T5 and the sixth transistor T6, respectively. The orthographic projection of the first reset signal line Re1 on the substrate overlaps the orthographic projection of the first active portion 71 on the substrate. Portions of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The orthographic projection of the second reset signal line Re2 on the substrate overlaps the orthographic projection of the seventh active portion 77 and the orthographic projection of the eighth active portion 78 on the substrate. Portions of the first reset signal line Re1 can be used to form the gates of the seventh transistor T7 and the eighth transistor T8, respectively. The orthographic projection of the first conductive portion 11 on the substrate overlaps the orthographic projection of the third active portion 73 on the substrate. The first conductive portion 11 can be used to form the gate of the drive transistor T3 and the first electrode of the capacitor C. The display panel can use the first conductive layer as a mask to conduct conductor processing on the first active layer, that is, the area of ​​the first active layer covered by the first conductive layer can form the channel region of the transistor, and the area of ​​the first active layer not covered by the first conductive layer forms a conductor structure.

[0147] As shown in Figures 3, 7, and 16, the second conductive layer may include: a third gate line 2G1 and a second conductive portion 22. The orthographic projection of the third gate line 2G1 on the base substrate extends along the first direction X, and the third gate line 2G1 can be used to provide the first gate drive signal terminal in Figure 1. The orthographic projection of the second conductive portion 22 on the base substrate can at least partially overlap with the orthographic projection of the first conductive portion 11 on the base substrate, and the second conductive portion 22 is used to form a second electrode of the capacitor C. The second conductive layer may also include a first connecting portion 23, and adjacent second conductive portions 22 in the first direction X can be connected by the first connecting portion 23.

[0148] As shown in Figures 3, 8, and 17, the second active layer may include an active portion 9, which may include: a second active portion 902, a nineteenth active portion 919 connected to both ends of the second active portion 902, and a twentieth active portion 920. The second active portion 902 is used to form the channel region of the second transistor T2. The second active layer may be formed of indium gallium zinc oxide, and accordingly, the second transistor T2 may be an N-type metal oxide thin film transistor. The orthographic projection of the third gate line 2G1 on the substrate may cover the orthographic projection of the second active portion 902 on the substrate, and a portion of the structure of the third gate line 2G1 may be used to form the bottom gate of the second transistor T2.

[0149] As shown in Figures 3, 9, and 18, the third conductive layer may include a first gate line 3G1, a first initial signal line Vinit1, a second initial signal line Vinit2, and a third initial signal line Vinit3. The orthographic projection of the first gate line 3G1 on the base substrate, the orthographic projection of the first initial signal line Vinit1 on the base substrate, the orthographic projection of the second initial signal line Vinit2 on the base substrate, and the orthographic projection of the third initial signal line Vinit3 on the base substrate may all extend along the first direction X. The first gate line 3G1 may be used to provide the first gate drive signal terminal in Figure 1, the orthographic projection of the first gate line 3G1 on the base substrate may cover the orthographic projection of the second active portion 902 on the base substrate, and a partial structure of the first gate line 3G1 may be used to form the top gate of the second transistor T2. At the same time, the first gate line 3G1 may be connected to the third gate line 2G1 through a via located in the frame area of ​​the display panel. The first initial signal line Vinit1 can be used to provide the first initial signal terminal in Figure 1, the second initial signal line Vinit2 can be used to provide the second initial signal terminal in Figure 1, and the third initial signal line Vinit3 can be used to provide the third initial signal terminal in Figure 1. The orthographic projection of the first initial signal line Vinit1 on the substrate substrate can at least partially overlap with the orthographic projection of the second reset signal line Re2 in the adjacent previous row of pixel driving circuits on the substrate substrate, the orthographic projection of the second initial signal line Vinit2 on the substrate substrate can at least partially overlap with the orthographic projection of the first reset signal line Re1 in the adjacent next row of pixel driving circuits on the substrate substrate, and the orthographic projection of the third initial signal line Vinit3 on the substrate substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the pixel driving circuit of the current row on the substrate substrate. This arrangement can improve the transmittance and integration of the display panel. In addition, the display panel can use the third conductive layer as a mask to perform conductor processing on the second active layer, that is, the area of ​​the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area of ​​the second active layer not covered by the third conductive layer forms a conductor structure.

[0150] It should be noted that in other exemplary embodiments, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in other conductive layers. For example, the first initial signal line Vinit1, the second initial signal line Vinit2, and the third initial signal line Vinit3 can also be located in the second conductive layer, the fourth conductive layer, etc.

[0151] As shown in Figures 3, 10, and 19, the fourth conductive layer may include a second bridge portion 42, a third bridge portion 43, a fourth bridge portion 44, a fifth bridge portion 45, a sixth bridge portion 46, a seventh bridge portion 47, an eighth bridge portion 48, a ninth bridge portion 49, and a tenth bridge portion 410. The second bridge portion 42 may be connected to the ninth active portion 79, the twentieth active portion 920, and the seventeenth active portion 717 through vias, respectively, to connect the second electrode of the first transistor T1, the second electrode of the second transistor T2, and the second electrode of the driving transistor T3. The third bridge portion 43 may be connected to the eighteenth active portion 718 and the first initial signal line Vinit1 through vias, respectively, to connect the first electrode of the first transistor T1 and the first initial signal terminal. The fourth bridge portion 44 may be connected to the fourteenth active portion 714 and the second initial signal line Vinit2 through vias, respectively, to connect the first electrode and the second initial signal line of the seventh transistor T7. The fifth bridge portion 45 is connected to the thirteenth active portion 713 via a via to connect the first electrode of the fourth transistor T4. The sixth bridge portion 46 is connected to the eleventh active portion 711 and the tenth active portion 710 via vias to connect the second electrode of the eighth transistor T8 and the first electrode of the driving transistor T3. The seventh bridge portion 47 is connected to the first connecting portion 23 and the fifteenth active portion 715 via vias to connect the second electrode of the capacitor C and the first electrode of the fifth transistor T5. The eighth bridge portion 48 is connected to the sixteenth active portion 716 via vias to connect the second electrode of the seventh transistor T7 and the second electrode of the sixth transistor T6. The ninth bridge portion 49 is connected to the nineteenth active portion 919 and the first conductive portion 11 via vias to connect the gate of the driving transistor T3 and the first electrode of the second transistor T2. The second conductive portion 22 may have an opening 221 formed therein, and a via connecting between the ninth bridge portion 41 and the first conductive portion 11 is provided through the opening 221. The tenth bridge portion 410 may be connected to the third initial signal line Vinit3 and the twelfth active portion 712 through vias, respectively, to connect the first electrode of the eighth transistor and the third initial signal line Vinit3 .

[0152] As shown in Figures 3, 11, and 20, the fifth conductive layer may include: a third conductive portion 51, an eleventh bridge portion 511, a twelfth bridge portion 512, a thirteenth bridge portion 513, and a first fan-out line FIPH. The orthographic projection of the first fan-out line FIPH on the substrate may extend along the first direction X, and the first fan-out line FIPH may serve as a row-direction fan-out line connecting the data lines in the FIP (Fanout In Pixel). The third conductive portion 51 may be connected to the seventh bridge portion 47 via a via to connect to the first electrode of the fifth transistor T5. The eleventh bridge portion 511 may be connected to the fifth bridge portion 45 via a via to connect to the first electrode of the fourth transistor. The thirteenth bridge portion 513 may be connected to the eighth bridge portion 48 via a via to connect to the second electrode of the sixth transistor T6. A portion of the twelfth bridge portion 512 may be connected to the same layer as the first fan-out line FIPH, and the first fan-out line FIPH may be connected to the column-direction data fan-out line via the twelfth bridge portion 512. Part of the twelfth bridge portion 512 can be spaced apart from the first fan-out line FIPH, and the column direction data fan-out line is also connected to the part of the twelfth bridge portion 512 through a via. The part of the twelfth bridge portion 512 can make the reflective and light-transmitting properties of different positions of the display panel uniform.

[0153] As shown in Figures 3, 12, and 21, the sixth conductive layer may include: a data line Da, a first power line VDD, a second fan-out line FIPV, and a fourteenth bridge portion 614. The orthographic projections of the data line Da, the first power line VDD, and the second fan-out line FIPV on the base substrate may extend along the second direction Y. The data line Da is used to provide the data signal terminal shown in Figure 1, and the first power line VDD is used to provide the first power terminal shown in Figure 1. The data line Da may be connected to the eleventh bridge portion 511 via a via to connect the data signal terminal and the first electrode of the fourth transistor. There may be multiple first power lines VDD, and the orthographic projections of the multiple first power lines VDD on the base substrate extend along the second direction Y and are spaced apart along the first direction X. Two columns of pixel driving circuits may be provided with a corresponding first power line VDD. The first power line VDD may be connected to the third conductive portion 51, which intersects with its orthographic projection on the base substrate, via a via.

[0154] The second fan-out line FIPV can be used as a column-direction fan-out line connecting the data line in the FIP (Fanout In Pixel), and can be connected to the twelfth bridge portion 512 through a via. The fourteenth bridge portion 614 can be connected to the thirteenth bridge portion 513 through a via.

[0155] As shown in Figures 3 and 13, the electrode layer may include multiple electrode portions: the multiple electrode portions include a first electrode portion G, a second electrode portion R, and a third electrode portion B. Each electrode portion may be connected to the fourteenth bridge portion 614 via a via to connect to the second electrode of the sixth transistor. Among the multiple electrode portions connected to the pixel driving circuit in the same row, the second electrode portion R, the first electrode portion G, the third electrode portion B, and the first electrode portion G are alternately distributed in the row direction. In two adjacent columns of pixel driving circuits, multiple second electrode portions R and multiple third electrode portions B are connected to the same column of pixel driving circuits, and the second electrode portions R and third electrode portions B connected to the same column of pixel driving circuits are alternately distributed in the column direction. Multiple first electrode portions G are connected to the pixel driving circuit in the other column. The orthographic projection of the second electrode portion R on the substrate coincides with the orthographic projection of the corresponding opening on the pixel definition layer on the substrate substrate, the orthographic projection of the first electrode portion G on the substrate coincides with the orthographic projection of the corresponding opening on the pixel definition layer on the substrate substrate, and the orthographic projection of the third electrode portion B on the substrate coincides with the orthographic projection of the corresponding opening on the pixel definition layer on the substrate substrate. The first electrode portion G can serve as the first electrode of the green light-emitting unit, the second electrode portion R can serve as the first electrode of the red light-emitting unit, and the third electrode portion B can serve as the first electrode of the blue light-emitting unit. In addition, as shown in Figure 13, the edges of the first electrode portion G, the second electrode portion R, and the third electrode portion B are all provided with extension portions, which can be provided as redundant portions to form electrode portions that coincide with the pixel opening. The orthographic projection of the third conductive portion 51 on the substrate substrate overlaps with the orthographic projection of the first electrode portion on the substrate substrate.

[0156] As shown in Figures 3 and 20, the orthographic projection of the third conductive portion 51 on the substrate can overlap the orthographic projection of the second active portion 902 on the substrate. The third conductive portion 51 can reduce the impact of light on the characteristics of the second transistor T2. The orthographic projection of the third conductive portion 51 on the substrate can also at least partially overlap with the orthographic projection of the ninth bridge portion 49 on the substrate. The third conductive portion 51 can be used to shield the ninth bridge portion 49 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3.

[0157] In this exemplary embodiment, the fourth conductive layer, the fifth conductive layer, and the sixth conductive layer form three source and drain layers. There are more metal film layers in the display panel, which results in a lower transmittance of the display panel, which is not conducive to the optical sensor inside the display panel to receive external light.

[0158] As shown in Figures 3, 11, and 20, a first missing portion 54 is formed on the third conductive portion 51, and the first missing portion 54 is at least partially located in the light-transmitting area of ​​the display panel; wherein, before the first missing portion 54 is formed, the orthographic projection of the third conductive portion 51 on the base substrate is symmetrically arranged relative to the first symmetry axis BB, and after the first missing portion 54 is formed, the orthographic projection of the third conductive portion 51 on the base substrate is asymmetrically arranged relative to the first symmetry axis BB.

[0159] In this exemplary embodiment, the first missing portion 54 is formed on the third conductive portion 51 . Meanwhile, the first missing portion 54 is located in the transmission area of ​​the display panel. This arrangement can increase the light transmittance of the display panel.

[0160] In this exemplary embodiment, the light-transmitting area of ​​the display panel is the area of ​​the base substrate not blocked by the light-shielding structure. The light-shielding structure in the display panel may include a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an electrode layer, etc. External light can pass through the light-transmitting area and be received by an optical sensor such as an optical fingerprint sensor in the display panel. Increasing the area of ​​the light-transmitting area can improve the optical fingerprint unlocking speed.

[0161] It should be noted that the pixel driving circuit in this exemplary embodiment may also have other structures, and accordingly, the display panel may also have other layout structures. As long as the display panel includes a third conductive portion for providing a high-level power signal, the transmittance of the display panel can be improved by providing the first missing portion.

[0162] As shown in Figures 3, 11, and 20, the first missing portion 54 includes a notch formed on the edge of the third conductive portion 51. As shown in Figure 22, it is a schematic structural diagram of the fifth conductive layer in another exemplary embodiment of the display panel disclosed herein. The first missing portion 54 may also include a hollow portion formed on the third conductive portion 51. It should be understood that in other exemplary embodiments, the first missing portion 54 may include both a notch and a hollow portion formed on the third conductive portion 51. In addition, the notch and / or hollow portion on the third conductive portion 51 may be set at different positions according to the position of the light-transmitting area of ​​the display panel.

[0163] As shown in Figures 3 and 13, the orthographic projection of the first electrode portion G on the base substrate is located within the orthographic projection of the third conductive portion 51 on the base substrate. This arrangement can improve the flatness of the first electrode portion G, thereby improving problems such as color shift caused by uneven electrode portions.

[0164] As shown in Figures 3, 12, and 21, a second missing portion 61 is formed on the first power line VDD. The orthographic projection of the second missing portion 61 on the substrate at least partially overlaps with the orthographic projection of the first missing portion on the substrate. Furthermore, the overlapping portion of the orthographic projection of the second missing portion 61 on the substrate and the orthographic projection of the first missing portion 54 on the substrate at least partially lies within the light-transmitting area of ​​the display panel. The second missing portion 61 and the first missing portion 54 cooperate to increase the light transmittance of the display panel.

[0165] In this exemplary embodiment, as shown in Figures 3, 12, and 21, the orthographic projection of the first power line VDD on the substrate before the second missing portion 61 is formed is symmetrically arranged with respect to the second symmetry axis CC, and the orthographic projection of the first power line VDD on the substrate after the second missing portion 61 is formed is asymmetrically arranged with respect to the second symmetry axis CC; the second symmetry axis CC is parallel to or coincides with the first symmetry axis BB.

[0166] In this exemplary embodiment, as shown in Figures 3 and 13 , the orthographic projection of the first electrode portion G on the base substrate lies within the orthographic projection of the first power line VDD on the base substrate. This arrangement improves the flatness of the first electrode portion G, thereby alleviating issues such as color shift caused by uneven electrode portions.

[0167] It should be noted that in other exemplary embodiments, the display panel may not be provided with a sixth conductive layer, and the first power line and data line in the sixth conductive layer may be provided in other conductive layers. For example, the first power line and data line may be provided in the fifth conductive layer, and the third conductive part may form the first power line.

[0168] In this exemplary embodiment, as shown in Figures 3, 9, 18, and 23, Figure 23 is an enlarged view of a local area D in Figure 18. The third gate line 2G1 includes a first gate line segment 2G11 and a second gate line segment 2G12 connected to each other, and the first gate line 3G1 includes a third gate line segment 3G13 and a fourth gate line segment 3G14 connected to each other; the orthographic projection of the first gate line segment 2G11 on the substrate and the orthographic projection of the third gate line segment 3G13 on the substrate extend in the same direction and at least partially overlap, the orthographic projection of the second gate line segment 2G12 on the substrate and the orthographic projection of the fourth gate line segment 3G14 on the substrate extend in the same direction and partially overlap; the orthographic projection of the first gate line segment 2G11 on the substrate and the orthographic projection of the display panel except for the third gate line segment 3G1 are the same. 3, the orthographic projections of the other shading structures in the display panel except the first gate line segment 2G11 on the substrate do not overlap; the orthographic projection of the third gate line segment 3G13 on the substrate does not overlap with the orthographic projections of the other shading structures in the display panel except the first gate line segment 2G11 on the substrate; the orthographic projection of the second gate line segment 2G12 on the substrate overlaps with the orthographic projections of at least part of the other shading structures in the display panel except the fourth gate line segment 3G14 on the substrate; the orthographic projection of the fourth gate line segment 3G14 on the substrate overlaps with the orthographic projections of at least part of the other shading structures in the display panel except the second gate line segment 2G12 on the substrate. Other light-shielding structures other than the third gate line segment 3G13 may include a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an electrode layer, etc.; other light-shielding structures other than the first gate line segment 2G11 may include a blocking layer, a first active layer, a first conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an electrode layer, etc.; other light-shielding structures other than the fourth gate line segment 3G14 may include a blocking layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an electrode layer, etc.; other light-shielding structures other than the second gate line segment 2G12 may include a blocking layer, a first active layer, a first conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, an electrode layer, etc.

[0169] In this exemplary embodiment, the overlapping portion of the orthographic projection of the first gate line segment 2G11 on the substrate and the orthographic projection of the third gate line segment 3G13 on the substrate has a dimension L5 perpendicular to the direction in which the first gate line segment 2G11 extends, and the overlapping portion of the orthographic projection of the second gate line segment 2G12 on the substrate and the orthographic projection of the fourth gate line segment 3G14 on the substrate has a dimension L6 perpendicular to the direction in which the second gate line extends, and L5 is greater than L6. This exemplary embodiment can reduce the total light-shielding area of ​​the first gate line segment 2G11 and the third gate line segment 3G13 by adjusting the overlapping positional relationship between the first gate line segment 2G11 and the third gate line segment 3G13, thereby improving the light transmittance of the display panel. For example, this exemplary embodiment can fine-tune the third gate line segment 3G13 upward to reduce the total light-shielding area of ​​the first gate line segment 2G11 and the third gate line segment 3G13.

[0170] In this exemplary embodiment, L5 / L6 is greater than 1 and less than or equal to 3 / 2. For example, L5 / L6 may be equal to 1.1, 1.2, 1.3, 1.4, 1.5, etc.

[0171] In this exemplary embodiment, the first gate line segment 2G11 includes a first side 91 and a second side 92 extending along its extension direction and arranged opposite to each other, the second gate line segment 2G12 includes a third side 93 and a fourth side 94 extending along its extension direction and arranged opposite to each other, the third gate line segment 3G13 includes a fifth side 95 and a sixth side 96 extending along its extension direction and arranged opposite to each other, and the fourth gate line segment 3G14 includes a seventh side 97 and an eighth side 98 extending along its extension direction and arranged opposite to each other; the first side 91 and the third side 93 are located on the same side of the third gate line, the second side 92 and the fourth side 94 are located on the same side of the third gate line, the fifth side 95 and the seventh side 97 are located on the same side of the first gate line, and the sixth side 96 and the eighth side 98 are located on the same side of the first gate line; the orthographic projection of the seventh side 97 on the substrate substrate is located between the orthographic projection of the third side 93 on the substrate substrate and the orthographic projection of the fourth side 94 on the substrate substrate, and the fourth side 94 on the substrate substrate The orthographic projection of the eighth side 98 on the substrate is located between the orthographic projection of the seventh side 97 on the substrate and the orthographic projection of the eighth side 98 on the substrate; the orthographic projection of the second side 92 on the substrate is located between the orthographic projection of the fifth side 95 on the substrate and the orthographic projection of the sixth side 96 on the substrate; the orthographic projection of the fifth side 95 on the substrate is located between the orthographic projection of the first side 91 on the substrate and the orthographic projection of the second side 92 on the substrate; the distance between the orthographic projection of the eighth side 98 on the substrate and the orthographic projection of the fourth side 94 on the substrate is L1, the distance between the orthographic projection of the sixth side 96 on the substrate and the orthographic projection of the second side 92 on the substrate is L2, the distance between the orthographic projection of the third side 93 on the substrate and the orthographic projection of the seventh side 97 on the substrate is L3, and the distance between the orthographic projection of the first side 91 on the substrate and the orthographic projection of the fifth side 95 on the substrate is L4; wherein, L1 is greater than L2, and / or L3 is greater than L4. This exemplary embodiment can also reduce the total light shielding area of ​​the first gate line segment 2G11 and the third gate line segment 3G13 by reducing the width of the non-overlapping region along the edges of the first gate line segment 2G11 and / or the third gate line segment 3G13. For example, this exemplary embodiment can adjust the overlapping position relationship between the first gate line segment 2G11 and the third gate line segment 3G13. In addition, this exemplary embodiment can also reduce the width of the first gate line segment 2G11 and / or the third gate line segment 3G13.

[0172] In this exemplary embodiment, L2 / L1 is greater than or equal to 0 and less than or equal to 2 / 3, and / or L4 / L3 is greater than or equal to 0 and less than or equal to 1 / 2. L2 / L1 can be equal to 0, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 2 / 3, etc. L4 / L3 can be equal to 0, 0.1, 0.2, 0.3, 0.4, 0.5, etc.

[0173] In this exemplary embodiment, L2 / L5 may be greater than or equal to 0 and less than or equal to 1 / 2. For example, L2 / L5 may be equal to 0, 0.1, 0.2, 0.3, 0.4, 0.5, etc.

[0174] In other exemplary embodiments, the orthographic projection of the first gate line segment 2G11 on the substrate can be located within the orthographic projection of the third gate line segment 3G13 on the substrate; and / or, the orthographic projection of the third gate line segment 3G13 on the substrate is located within the orthographic projection of the first gate line segment 2G11 on the substrate. This arrangement can also reduce the total light-shielding area of ​​the first gate line segment 2G11 and the third gate line segment 3G13. When the orthographic projection of the first gate line segment 2G11 on the substrate can be located within the orthographic projection of the third gate line segment 3G13 on the substrate, and the orthographic projection of the third gate line segment 3G13 on the substrate is located within the orthographic projection of the first gate line segment 2G11 on the substrate, the orthographic projection of the first gate line segment 2G11 on the substrate and the orthographic projection of the third gate line segment 3G13 on the substrate coincide with each other.

[0175] In this exemplary embodiment, the orthographic projection of the first gate line segment 2G11 on the substrate and the orthographic projection of the third gate line segment 3G13 on the substrate are both located between the orthographic projection of the data line Da on the substrate and the orthographic projection of the third conductive portion 51 on the substrate; the orthographic projection of the second gate line segment 2G12 on the substrate and the orthographic projection of the fourth gate line segment 3G14 on the substrate at least partially overlap with the orthographic projection of the data line Da on the substrate.

[0176] It should be noted that the above-mentioned setting of the first gate line 3G1 and the third gate line 2G1 can also be applied to other display panels. As long as the display panel includes an N-type transistor, the first gate line 3G1 and the third gate line 2G1 that respectively form the top gate and bottom gate of the N-type transistor can improve the transmittance of the display panel through the above-mentioned setting.

[0177] In this exemplary embodiment, as shown in Figures 3, 6, and 24, Figure 24 is a partial enlarged view of area E in Figure 6. The second gate line G2 includes a fifth gate line segment G25 and a sixth gate line segment G26 connected to each other. The orthographic projections of the fifth gate line segment G25 and the sixth gate line segment G26 on the substrate extend along the first direction X and are staggered in the second direction Y. The fifth gate line segment G25 includes a ninth side 99, and the sixth gate line segment G26 includes a tenth side 910. The ninth side 99 and the tenth side 910 are located on the same side of the second gate line G2. The orthographic projections of the ninth side 99 and the tenth side 910 on the substrate extend along the first direction X and are spaced apart in the second direction Y. The virtual extension line of the orthographic projection of the ninth side 99 on the substrate in the first direction includes a first virtual line segment X1. The orthographic projection of the tenth side 910 on the substrate and the first virtual line segment X1 are arranged opposite to each other in the second direction Y. The area between the orthographic projection of the tenth side 910 on the substrate and the first virtual line segment X1 is at least partially located in the light-transmitting area of ​​the display panel. In this exemplary embodiment, structures A and B are arranged relative to each other in a certain direction. This means that the areas covered by structures A and B, if extended infinitely in this direction, at least partially intersect. The first virtual line segment X1 is a virtual extension of the ninth side edge 99, and the display panel does not include the first virtual line segment X1. In this exemplary embodiment, the sixth gate line segment G26 avoids the light-transmitting area of ​​the display panel, thereby increasing the light transmittance of the display panel.

[0178] In this exemplary embodiment, the fifth gate line segment G25 further includes an eleventh side 911 opposite the ninth side 99, and the sixth gate line segment G26 further includes a twelfth side 912 opposite the tenth side 910. In the second direction Y, the orthographic projection of the eleventh side 911 on the substrate is located between the orthographic projections of the tenth side 910 and the twelfth side 912 on the substrate. In the second direction Y, the orthographic projection of the tenth side 910 on the substrate is located between the orthographic projections of the ninth side 99 and the eleventh side 911 on the substrate. The sixth gate line segment G26 can be bent to avoid the light-transmitting area of ​​the display panel.

[0179] In this exemplary embodiment, as shown in FIG. 3 , 6 , and 15 , the orthographic projection of the first conductive portion 11 on the base substrate and the orthographic projection of the sixth gate line segment G26 on the base substrate are arranged opposite to each other in the second direction Y.

[0180] It should be noted that in other exemplary embodiments, the second gate line can also be used to form the gate of other transistors, that is, the gate lines of other transistors can also improve the light transmittance of the display panel by setting the second gate line. In addition, the setting of the second gate line can also be applied to display panels with other structures.

[0181] As shown in Figures 3, 4, and 14, the shielding portion may further include a second connecting portion 82, which connects between adjacent shielding portions 81. The second connecting portion 82 includes a first extending portion 821 and a second extending portion 822. The orthographic projection of the second extending portion 822 on the substrate, perpendicular to its extension direction, is larger than the orthographic projection of the first extending portion 821 on the substrate, perpendicular to its extension direction. The orthographic projection of the via connecting between the second bridging portion 42 and the seventeenth active portion 717 on the substrate is located within the orthographic projection of the second extending portion 822 on the substrate. This arrangement ensures that each via connecting between the second bridging portion 42 and the seventeenth active portion 717 has a uniform exposure effect during the manufacturing exposure process, thereby improving the dimensional uniformity of each via connecting between the second bridging portion 42 and the seventeenth active portion 717.

[0182] In this exemplary embodiment, the second connection portion extending along the second direction Y is provided with a widened second extension portion, and the seventeenth active portion 717 is a via connection portion of the first transistor. It should be understood that in other exemplary embodiments, the seventeenth active portion 717 can be any via connection portion on the first active layer, and the second connection portion can also extend along the first direction X.

[0183] This exemplary embodiment also provides a display panel, which includes a third conductive portion 51 for providing a high-level power signal. The display panel can improve the transmittance of the display panel by providing a missing portion on the third conductive portion 51. Accordingly, the overlapping area of ​​the orthographic projection of the third conductive portion 51 on the base substrate and the orthographic projection of other light-shielding structures in the display panel other than the third conductive portion 51 on the base substrate is S1, and the area of ​​the orthographic projection of the third conductive portion on the base substrate is S2; wherein S1 / S2 is greater than or equal to 0.9 and less than or equal to 1. For example, S1 / S2 can be equal to 0.9, 0.91, 0.92, 0.93, 0.94, 0.95, 0.96, 0.97, 0.98, 0.99, 1, etc. The larger S1 / S2 is, the larger the area of ​​the missing portion on the third conductive portion 51 is. This display panel can include all the technical features of the above-mentioned display panel. Other light-shielding structures other than the third conductive portion 51 may include a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a sixth conductive layer, an electrode layer, and the like. It should be noted that, as shown in Figures 3, 19, 20, and 21, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; the black squares drawn on the side of the sixth conductive layer facing away from the substrate represent vias connecting the sixth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. Different vias represented by black squares in different positions may penetrate different insulating layers.

[0184] FIG25 is a partial cross-sectional view of the display panel shown in FIG3 taken along the dotted line FF. The display panel may further include a buffer layer 101, a second insulating layer 102, a third insulating layer 103, a fourth insulating layer 104, a fifth insulating layer 105, a first dielectric layer 106, a passivation layer 107, a first planar layer 108, and a second planar layer 109. The substrate 100, the shielding layer, the buffer layer 101, the first active layer, the second insulating layer 102, the first conductive layer, the third insulating layer 103, the second conductive layer, the fourth insulating layer 104, the second active layer, the fifth insulating layer 105, the third conductive layer, the first dielectric layer 106, the fourth conductive layer, the passivation layer 107, the first planar layer 108, the fifth conductive layer, the second planar layer 109, the sixth conductive layer, the third planar layer 110, and the electrode layer are stacked in sequence. The buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be a single-layer structure or a multi-layer structure. The materials of the buffer layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, and the fifth insulating layer 105 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride. The first dielectric layer 106 can be a silicon nitride layer. The materials of the first planarizing layer 108, the second planarizing layer 109, and the third planarizing layer 110 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonding structure (SOG), etc. The passivation layer 107 can be a silicon oxide layer. The base substrate 100 can include a glass substrate, a barrier layer, and a polyimide layer stacked in sequence. The barrier layer can be an inorganic material. The first, second, and third conductive layers can be made of molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof. The fourth, fifth, and sixth conductive layers can be made of a metal material, such as molybdenum, aluminum, copper, titanium, or niobium, or an alloy thereof, or a molybdenum / titanium alloy or laminate thereof, or a titanium / aluminum / titanium laminate thereof. The sheet resistance of any of the fourth, fifth, and sixth conductive layers can be less than the sheet resistance of any of the first, second, and third conductive layers.

[0185] It should be noted that the proportions of the drawings in this disclosure can be used as a reference in actual processes, but are not limited to this. For example, the width-to-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematics. In addition, qualifiers such as first and second are only used to limit different structure names, and they do not have a specific order of meaning. The same structural layer can be formed by the same composition process. In this exemplary embodiment, the orthographic projection of a certain structure on the base substrate extends along a certain direction. It can be understood that the orthographic projection of the structure on the base substrate extends straight or bends along this direction.

[0186] This exemplary embodiment also provides a display device, which includes the above-mentioned display panel. The display device can be a mobile phone, a tablet computer, a television, or other display device.

[0187] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0188] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0189] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A display panel, wherein: The display panel includes a pixel driving circuit and a light-emitting unit distributed in an array, and the display panel further includes: substrate; a fifth conductive layer, located on one side of the base substrate; an electrode layer, located on a side of the fifth conductive layer facing away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit; a pixel definition layer located on a side of the electrode layer facing away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings are correspondingly arranged to the electrode portions, and wherein the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The pixel driving circuit includes: a third conductive portion, the third conductive portion being configured to provide a high-level power signal, the third conductive portion being located in the fifth conductive layer, and an orthographic projection of the third conductive portion on the base substrate at least partially overlapping with an orthographic projection of the electrode portion on the base substrate; A first missing portion is formed on the third conductive portion, and the first missing portion is at least partially located in the light-transmitting area of ​​the display panel; The figure formed by the orthographic projection of the first missing portion on the base substrate and the orthographic projection of the third conductive portion on the base substrate is symmetrically arranged relative to the first symmetry axis, and the orthographic projection of the third conductive portion on the base substrate is asymmetrically arranged relative to the first symmetry axis.

2. The display panel according to claim 1, wherein The plurality of electrode portions include a first electrode portion, and an orthographic projection of the first electrode portion on the base substrate is located within an orthographic projection of the third conductive portion on the base substrate.

3. The display panel according to claim 1, wherein: The first missing portion includes a notch formed on an edge of the third conductive portion and / or a hollow portion formed on the third conductive portion.

4. The display panel according to claim 1, wherein: The display panel further includes: a sixth conductive layer, located on a side of the fifth conductive layer facing away from the base substrate, the sixth conductive layer comprising a first power line, the first power line being connected to the third conductive portion through a via; Wherein, a second missing portion is formed on the first power line. The orthographic projection on the base substrate and the orthographic projection of the first missing portion on the base substrate at least partially overlap, and the overlapping portion of the orthographic projection of the second missing portion on the base substrate and the orthographic projection of the first missing portion on the base substrate is at least partially located in the light-transmitting area of ​​the display panel.

5. The display panel according to claim 4, wherein: A figure formed by a combination of an orthographic projection of the second missing portion on the base substrate and an orthographic projection of the first power line on the base substrate is symmetrically arranged relative to a second symmetry axis, and an orthographic projection of the first power line on the base substrate is asymmetrically arranged relative to the second symmetry axis; The second symmetry axis is parallel to or coincides with the first symmetry axis. The display panel according to claim 4 , wherein: The plurality of electrode portions include a first electrode portion, and an orthographic projection of the first electrode portion on the base substrate is located within an orthographic projection of the first power line on the base substrate.

7. The display panel according to claim 1, wherein: The pixel driving circuit includes an oxide transistor, and the display panel further includes: a second conductive layer, located between the base substrate and the fifth conductive layer; a third conductive layer, located between the second conductive layer and the fifth conductive layer; The pixel driving circuit further includes: a third gate line located in the second conductive layer, wherein a portion of the third gate line is used to form a bottom gate of the oxide transistor; a first gate line located in the third conductive layer, wherein a portion of the first gate line is used to form a top gate of the oxide transistor; Wherein, the third gate line includes a first gate line segment and a second gate line segment connected thereto, and the first gate line includes a third gate line segment and a fourth gate line segment connected thereto; The orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate extend in the same direction and at least partially overlap, and the orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate extend in the same direction and partially overlap; The orthographic projection of the first gate line segment on the base substrate and the orthographic projections of other light shielding structures in the display panel except the third gate line segment on the base substrate do not overlap, and the orthographic projection of the third gate line segment on the base substrate and the orthographic projections of other light shielding structures in the display panel except the first gate line segment on the base substrate do not overlap. The orthographic projections of other light-shielding structures other than the above-mentioned light-shielding structures on the substrate do not overlap; The orthographic projection of the second gate line segment on the base substrate overlaps with the orthographic projection of at least part of other light shielding structures in the display panel except the fourth gate line segment on the base substrate; The orthographic projection of the fourth gate line segment on the base substrate overlaps with the orthographic projection of at least part of other light-shielding structures in the display panel except the second gate line segment on the base substrate.

8. The display panel according to claim 7, wherein: The overlapping part of the orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate has a size L5 perpendicular to the extension direction of the first gate line segment, and the overlapping part of the orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate has a size L6 perpendicular to the extension direction of the second gate line segment, and L5 is greater than L6.

9. The display panel according to claim 8, wherein: L5 / L6 is greater than 1 and less than or equal to 3 / 2.

10. The display panel according to claim 7, wherein: The first gate segment includes a first side and a second side extending along the extension direction thereof and arranged opposite to each other; the second gate segment includes a third side and a fourth side extending along the extension direction thereof and arranged opposite to each other; the third gate segment includes a fifth side and a sixth side extending along the extension direction thereof and arranged opposite to each other; and the fourth gate segment includes a seventh side and an eighth side extending along the extension direction thereof and arranged opposite to each other; The first side and the third side are located on the same side of the third gate line, the second side and the fourth side are located on the same side of the third gate line, the fifth side and the seventh side are located on the same side of the first gate line, and the sixth side and the eighth side are located on the same side of the first gate line; The orthographic projection of the seventh side on the substrate is located between the orthographic projection of the third side on the substrate and the orthographic projection of the fourth side on the substrate, and the orthographic projection of the fourth side on the substrate is located between the orthographic projection of the seventh side on the substrate and the orthographic projection of the eighth side on the substrate; The orthographic projection of the second side on the substrate is located between the orthographic projection of the fifth side on the substrate and the orthographic projection of the sixth side on the substrate, and the orthographic projection of the fifth side on the substrate is located between the orthographic projection of the first side on the substrate and the orthographic projection of the second side on the substrate; The orthographic projection of the eighth side on the substrate and the orthographic projection of the fourth side on the substrate The distance between the orthographic projection of the sixth side on the base substrate and the orthographic projection of the second side on the base substrate is L1, the distance between the orthographic projection of the third side on the base substrate and the orthographic projection of the seventh side on the base substrate is L3, and the distance between the orthographic projection of the first side on the base substrate and the orthographic projection of the fifth side on the base substrate is L4; Wherein, L1 is greater than L2, and / or L3 is greater than L4.

11. The display panel according to claim 10, wherein: L2 / L1 is greater than or equal to 0 and less than or equal to 2 / 3, and / or L4 / L3 is greater than or equal to 0 and less than or equal to 1 / 2.

12. The display panel according to claim 7, wherein: The third gate line segment includes a sixth side extending along the extension direction thereof, and an orthographic projection of the sixth side on the substrate does not overlap with an orthographic projection of the first gate line segment on the substrate; The distance between the orthographic projection of the sixth side on the substrate and the orthographic projection of the first gate line segment on the substrate is L2, and the size of the overlapping part of the orthographic projection of the first gate line segment on the substrate and the orthographic projection of the third gate line segment on the substrate perpendicular to the extension direction of the first gate line segment is L5, and L2 / L5 is greater than or equal to 0 and less than or equal to 1 / 2.

13. The display panel according to claim 7, wherein: The orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate are staggered in a direction perpendicular to the extending direction of the second gate line segment; The orthographic projection of the first gate line segment on the substrate is located within the orthographic projection of the third gate line segment on the substrate; And / or, the orthographic projection of the third gate line segment on the base substrate is located within the orthographic projection of the first gate line segment on the base substrate.

14. The display panel according to any one of claims 7 to 13, wherein: The display panel further includes: a data line, the data line being used to provide a data signal to the pixel driving circuit; The orthographic projection of the first gate line segment on the base substrate and the orthographic projection of the third gate line segment on the base substrate are both located between the orthographic projection of the data line on the base substrate and the orthographic projection of the third conductive portion on the base substrate; The orthographic projection of the second gate line segment on the substrate and the orthographic projection of the fourth gate line segment on the substrate are at least partially aligned with the orthographic projection of the data line on the substrate. Overlapping points.

15. The display panel according to any one of claims 7 to 13, wherein: The pixel driving circuit includes a driving transistor and a second transistor, wherein a first electrode of the second transistor is connected to a gate of the driving transistor, and a second electrode of the second transistor is connected to a second electrode of the driving transistor; The second transistor forms the oxide transistor.

16. The display panel according to claim 1, wherein The display panel further includes: a first conductive layer, located between the base substrate and the fifth conductive layer; The pixel driving circuit further includes a second gate line, the second gate line is located in the first conductive layer, the second gate line includes a fifth gate line segment and a sixth gate line segment connected to each other, an orthographic projection of the fifth gate line segment on the base substrate and an orthographic projection of the sixth gate line segment on the base substrate extend along a first direction and are staggered in a second direction, and the first direction and the second direction intersect; The fifth gate line segment includes a ninth side, the sixth gate line segment includes a tenth side, the ninth side and the tenth side are located on the same side of the second gate line, and the orthographic projection of the ninth side on the substrate and the orthographic projection of the tenth side on the substrate extend along the first direction and are spaced apart in the second direction; The virtual extension line of the orthographic projection of the ninth side on the base substrate in the first direction includes a first virtual line segment, the orthographic projection of the tenth side on the base substrate and the first virtual line segment are arranged relative to each other in the second direction, and the area between the orthographic projection of the tenth side on the base substrate and the first virtual line segment is at least partially located in the light-transmitting area of ​​the display panel.

17. The display panel according to claim 16, wherein: The fifth gate line segment further includes an eleventh side opposite to the ninth side, and the sixth gate line segment further includes a twelfth side opposite to the tenth side; In the second direction, the orthographic projection of the eleventh side on the base substrate is located between the orthographic projection of the tenth side on the base substrate and the orthographic projection of the twelfth side on the base substrate; In the second direction, the orthographic projection of the tenth side on the substrate is located between the orthographic projection of the ninth side on the substrate and the orthographic projection of the eleventh side on the substrate. Between the orthographic projections on the board.

18. The display panel according to claim 16, wherein: The pixel driving circuit includes a fourth transistor and a driving transistor, wherein a first electrode of the fourth transistor is connected to a data line, and a second electrode of the fourth transistor is connected to a first electrode of the driving transistor; An orthographic projection of the second gate line on the substrate extends along a first direction, and a portion of the second gate line is used to form a gate of the fourth transistor.

19. The display panel according to claim 18, wherein: The first conductive layer further comprises: A first conductive portion is used to form a gate of the driving transistor, and an orthographic projection of the first conductive portion on the base substrate and an orthographic projection of the sixth gate line segment on the base substrate are arranged opposite to each other in the second direction.

20. The display panel according to claim 1, wherein The pixel driving circuit includes a driving transistor, a first transistor, a fifth transistor, a seventh transistor, and an eighth transistor; The first electrode of the first transistor is connected to the first initial signal line, the second electrode is connected to the second electrode of the driving transistor, and the gate is connected to the first reset signal line; The first electrode of the fifth transistor is connected to the first power line, the second electrode is connected to the first electrode of the driving transistor, and the gate is connected to the enable signal line; The first electrode of the seventh transistor is connected to the second initial signal line, the second electrode is connected to the first electrode of the light emitting unit, and the gate is connected to the second reset signal line; A first electrode of the eighth transistor is connected to the third initial signal line, and a second electrode is connected to the first electrode of the driving transistor; The orthographic projection of the first initial signal line on the substrate and the orthographic projection of the second reset signal line in the adjacent previous row of pixel driving circuits on the substrate at least partially overlap; The orthographic projection of the second initial signal line on the substrate at least partially overlaps with the orthographic projection of the first reset signal line in the adjacent next row of pixel driving circuits on the substrate; The orthographic projection of the third initial signal line on the substrate at least partially overlaps with the orthographic projection of the enable signal line in the pixel driving circuit of the current row on the substrate.

21. The display panel according to claim 1, wherein The pixel driving circuit includes: driver transistors; a first transistor, a first electrode of which is connected to the first initial signal line, and a second electrode of which is connected to the second electrode of the driving transistor; a second transistor, a first electrode of which is connected to the gate electrode of the driving transistor, and a second electrode of which is connected to the second electrode of the driving transistor; a fourth transistor, a first electrode of which is connected to the data line, and a second electrode of which is connected to the first electrode of the driving transistor; a fifth transistor, a first electrode connected to the first power line, and a second electrode connected to the first electrode of the driving transistor; a sixth transistor, a first electrode of which is connected to the second electrode of the driving transistor, and a second electrode of which is connected to the first electrode of the light-emitting unit; a seventh transistor, a first electrode connected to the second initial signal line, and a second electrode connected to the first electrode of the light-emitting unit; an eighth transistor, a first electrode of which is connected to the third initial signal line, and a second electrode of which is connected to the first electrode of the driving transistor; a capacitor, a first electrode of which is connected to the gate of the driving transistor, and a second electrode of which is connected to the first power line; The first transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor are P-type transistors, and the second transistor is an N-type transistor.

22. The display panel according to claim 1, wherein The pixel driving circuit includes a P-type transistor and an N-type transistor, and the display panel further includes: a first active layer, located between the base substrate and the fifth conductive layer, wherein a portion of the first active layer is used to form a channel region of a P-type transistor in the pixel driving circuit; a first conductive layer, located between the first active layer and the fifth conductive layer, wherein a portion of the first conductive layer is used to form a gate of a P-type transistor in the pixel driving circuit; a second conductive layer, located between the first conductive layer and the fifth conductive layer, wherein a portion of the second conductive layer is used to form a bottom gate of an N-type transistor in the pixel driving circuit; a second active layer, located between the second conductive layer and the fifth conductive layer, wherein a portion of the second active layer is used to form a channel region of an N-type transistor in the pixel driving circuit; a third conductive layer, located between the second active layer and the fifth conductive layer, wherein a portion of the third conductive layer is used to form a top gate of an N-type transistor in the pixel driving circuit; The fourth conductive layer is located between the third conductive layer and the fifth conductive layer, and a portion of the structure of the fourth conductive layer is used to form a bridge portion connecting different transistors.

23. The display panel according to claim 1, wherein: The pixel driving circuit includes a driving transistor, and the display panel further includes: a shielding layer located between the base substrate and the fifth conductive layer, the shielding layer comprising a plurality of shielding portions arrayed along a first direction and a second direction, and a second connecting portion connected between adjacent shielding portions, wherein the first direction and the second direction intersect; a first active layer, located between the blocking layer and the fifth conductive layer, the first active layer comprising a third active portion and a seventeenth active portion, the third active portion being configured to form a channel region of the driving transistor, and an orthographic projection of the blocking portion on the base substrate and an orthographic projection of the third active portion on the base substrate at least partially overlapping; a second bridging portion connected to the seventeenth active portion through a via hole; The second connecting portion includes a first extending portion and a second extending portion, wherein a dimension of an orthographic projection of the second extending portion on the base substrate in a direction perpendicular to the extending direction thereof is greater than a dimension of an orthographic projection of the first extending portion on the base substrate in a direction perpendicular to the extending direction thereof; An orthographic projection of a via hole connected between the second bridging portion and the seventeenth active portion on the base substrate is located within an orthographic projection of the second extending portion on the base substrate.

24. A display panel comprising a pixel driving circuit and a light-emitting unit distributed in an array, the display panel further comprising: substrate; a fifth conductive layer, located on one side of the base substrate; an electrode layer, located on a side of the fifth conductive layer facing away from the base substrate, the electrode layer comprising a plurality of electrode portions, the electrode portions being used to form a first electrode of the light-emitting unit; a pixel definition layer, located on a side of the electrode layer facing away from the base substrate, wherein a plurality of pixel openings are formed on the pixel definition layer, wherein the pixel openings are correspondingly arranged to the electrode portions, and the orthographic projections of the pixel openings on the base substrate coincide with the orthographic projections of the corresponding electrode portions on the base substrate; The pixel driving circuit includes: a third conductive portion, the third conductive portion being configured to provide a high-level power signal, the third conductive portion being located in the fifth conductive layer, and an orthographic projection of the third conductive portion on the base substrate at least partially overlapping with an orthographic projection of the electrode portion on the base substrate; The overlapping area of ​​the orthographic projection of the third conductive portion on the base substrate and the orthographic projection of other light shielding structures in the display panel except the third conductive portion on the base substrate is S1, and the area of ​​the orthographic projection of the third conductive portion on the base substrate is S2; Among them, S1 / S2 is greater than or equal to 0.9 and less than or equal to 1.

25. A display device, wherein: The display device comprises the display panel according to any one of claims 1 to 24.

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