Migration system, processing device, and migration method

Abstract

One aspect of the present invention is a migration system comprising a first processing device and a second processing device, said first processing device including: a migration information collection unit that collects migration information of a first circuit provided in the first processing device; a first migration information storage unit that stores the migration information collected by the migration information collection unit; and a migration information transmission unit that transmits the migration information stored by the first migration information storage unit to the second processing device. The second processing device includes a migration information reception unit that receives the migration information transmitted by the migration information transmission unit, and a migration information writing unit that writes the migration information received by the migration information reception unit to a second circuit provided in the second processing device.

Description

Migration system, processing device, and migration method

[0001] The present invention relates to a migration system, a processing device, and a migration method.

[0002] Field programmable gate arrays (FPGAs), which are suitable for low power consumption, low latency, and high-speed processing, are often used for processing such as AI (artificial intelligence), and are also being put to practical use on the cloud. During system maintenance and other such operations, it is necessary to migrate stateful applications running on FPGAs. Non-Patent Document 1 proposes live migration technology for FPGAs (i.e., technology that transfers functions and processing states to another FPGA without stopping the functions and processing running on the FPGA).

[0003] A. Fukuhara, et al. "FPGA context-based live migration maintaining network consistency." 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW). IEEE, 2020.

[0004] In the system described in Non-Patent Document 1, when performing migration from a migration source server to a migration destination server, migration information required for the migration is obtained from the migration source server. The migration source server then performs the migration by transmitting the read migration information to the migration destination server via an external bitstream server.

[0005] In the system described in non-patent document 1, migration information is sent from the source server to the bitstream server, and also from the bitstream server to the destination server, so it takes time to send and save the migration information, which increases the time it takes to complete the migration.

[0006] In view of the above circumstances, an object of the present invention is to provide a migration system, a processing device, and a migration method that can shorten the time required to complete migration.

[0007] One aspect of the present invention is a migration system comprising a first processing device and a second processing device, wherein the first processing device comprises a migration information collection unit that collects migration information of a first circuit provided in the first processing device, a first migration information storage unit that stores the migration information collected by the migration information collection unit, and a migration information transmission unit that transmits the migration information stored in the first migration information storage unit to the second processing device, and the second processing device comprises a migration information receiving unit that receives the migration information transmitted by the migration information transmission unit, and a migration information writing unit that writes the migration information received by the migration information receiving unit to a second circuit provided in the second processing device.

[0008] Another aspect of the present invention is a processing device comprising: a migration information collection unit that collects first migration information of a first circuit provided in the processing device; a first migration information storage unit that stores the first migration information collected by the migration information collection unit; a migration information transmission unit that transmits the first migration information stored in the first migration information storage unit to another processing device; a migration information receiving unit that receives second migration information of a second circuit provided in the other processing device; and a migration information writing unit that writes the second migration information received by the migration information receiving unit to the first circuit.

[0009] Another aspect of the present invention is a migration method using a first processing device and a second processing device, in which the first processing device collects migration information of a first circuit provided in the first processing device, the first processing device stores the collected migration information, the first processing device transmits the migration information stored by the first processing device to the second processing device, the second processing device receives the migration information transmitted by the first processing device, and the second processing device writes the migration information received by the second processing device to a second circuit provided in the second processing device.

[0010] According to the present invention, it is possible to provide a migration system, a processing device, and a migration method that can shorten the time required to complete migration.

[0011] Fig. 1 is a schematic configuration diagram of a migration system according to a first embodiment of the present invention. Fig. 2 is a sequence diagram showing processing in the migration system according to the first embodiment of the present invention. Fig. 3 is a schematic configuration diagram of a migration system according to a modified example of the first embodiment of the present invention. Fig. 4 is a schematic configuration diagram of a migration system according to a second embodiment of the present invention. Fig. 5 is a sequence diagram showing processing in the migration system according to the second embodiment of the present invention. Fig. 6 is a schematic configuration diagram of a migration system according to a modified example of the second embodiment of the present invention.

[0012] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments.

[0013] First Embodiment First, a first embodiment of the present invention will be described.

[0014] 1 is a schematic configuration diagram of a migration system 100A1 according to a first embodiment of the present invention. The migration system 100A1 includes a controller 10A, a migration source server 20A1, and a migration destination server 20A2. The controller 10A, the migration source server 20A1, and the migration destination server 20A2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100A1 according to the first embodiment of the present invention performs live migration, in which an application running on the migration source server 20A1 is moved to the migration destination server 20A2 and executed thereon.

[0015] The controller 10A includes an FPGA migration control unit 11A, an FPGA information collection control unit 12A, an FPGA information management control unit 13A, and an FPGA application writing control unit 14A. The FPGA migration control unit 11A receives a migration instruction from an administrator of the migration system 100A1 or the like, and starts live migration processing by the migration system 100A1.

[0016] The FPGA information collection control unit 12A instructs the FPGA information collection unit 211A1 of the migration source server 20A1 to collect migration information of the FPGA 22A1 of the migration source server 20A1. In the first embodiment, the migration information includes application information (also referred to as circuit information) indicating an application executed by the FPGA 22A1 of the migration source server 20A1.

[0017] The FPGA information management control unit 13A instructs the FPGA information management control unit 21A1 of the migration source server 20A1 to perform live migration processing from the migration source server 20A1 to the migration destination server 20A2. The FPGA application writing control unit 14A instructs the FPGA application writing unit 213A1 of the migration source server 20A1 to write application information of the FPGA 22A1 of the migration source server 20A1 to the FPGA 22A2 of the migration destination server 20A2.

[0018] The migration source server 20A1 includes an FPGA information management control unit 21A1 and an FPGA 22A1. The FPGA information management control unit 21A1 includes an FPGA information collection unit 211A1, an FPGA information communication unit 212A1, an FPGA application writing unit 213A1, and an FPGA information storage unit 215A1.

[0019] The FPGA information collection unit 211A1 collects application information indicating the application 221A1 executed by the FPGA 22A1 of the migration source server 20A1, and stores it in the FPGA information storage unit 215A1 as an FPGA application information DB (Database) 2151A1.

[0020] The FPGA information communication unit 212A1 performs communication between the migration source server 20A1, the controller 10A, and the migration destination server 20A2. For example, the FPGA information communication unit 212A1 receives instructions related to migration from the controller 10A, and transmits application information of the FPGA 22A1 of the migration source server 20A1 directly to the migration destination server 20A2 without going through the controller 10A or another device (for example, a bitstream server).

[0021] The FPGA application writing unit 213A1 transmits application information of the FPGA 22A1 of the migration source server 20A1 to the migration destination server 20A2 via the FPGA information communication unit 212A1, thereby writing the application information to the FPGA 22A2 provided in the migration destination server 20A2.

[0022] The FPGA information storage unit 215A1 is a storage device such as a memory, and stores an FPGA application information DB 2151A1 and the like. The FPGA application information DB 2151A1 stores application information collected by the FPGA information collection unit 211A1, such as application information of the FPGA 22A1 of the migration source server 20A1. The FPGA 22A1 is an integrated circuit whose circuit configuration can be changed by the user after manufacturing. The FPGA 22A1 executes an application 221A1.

[0023] The configuration of the migration destination server 20A2 is the same as the configuration of the migration source server 20A1. That is, the migration destination server 20A2 is provided with an FPGA information management control unit 21A2 and an FPGA 22A2 as components corresponding to the FPGA information management control unit 21A1 and FPGA 22A1 provided in the migration source server 20A1. Therefore, in the first embodiment, only the configuration of the migration source server 20A1 will be described, and a description of the configuration of the migration destination server 20A2 will be omitted. The FPGA 22A2 executes an application 221A2.

[0024] 2 is a sequence diagram showing processing in the migration system 100A1 according to the first embodiment of the present invention. First, the FPGA migration control unit 11A receives a migration instruction from the migration source server 20A1 to the migration destination server 20A2, which is an instruction from an administrator of the migration system 100A1 or the like (step S101).

[0025] When the FPGA migration control unit 11A receives the migration instruction, the FPGA migration control unit 11A outputs an instruction to the FPGA information collection control unit 12A to start collecting application information of the FPGA 22A1 of the migration source server 20A1. The FPGA information collection control unit 12A sends a collection request for application information of the FPGA 22A1 to the migration source server 20A1 (step S102).

[0026] When receiving the application information collection request from the FPGA information collection control unit 12A, the FPGA information collection unit 211A1 of the migration source server 20A1 reads application information indicating the application 221A1 being executed by the FPGA 22A1 of the migration source server 20A1 (step S103). Next, the FPGA information collection unit 211A1 stores the application information read in step S103 in the FPGA application information DB 2151A1 of the FPGA information storage unit 215A1 (step S104).

[0027] When the processing of step S104 is completed, the FPGA information collection unit 211A1 sends a completion notification to the controller 10A notifying that the recording of the application information into the FPGA application information DB 2151A1 is completed (step S105). Next, when the controller 10A receives the completion notification in step S105, the FPGA application write control unit 14A of the controller 10A sends an instruction to write the application information to the migration source server 20A1 (step S106).

[0028] When the migration source server 20A1 receives the instruction to write the application information in step S106, the FPGA application writing unit 213A1 of the migration source server 20A1 reads the application information stored in step S104 from the FPGA application information DB 2151A1 (step S107). Next, the FPGA application writing unit 213A1 of the migration source server 20A1 transmits the application information read in step S107 directly (i.e., without passing through the controller 10A or another bitstream server) to the migration destination server 20A2 via the FPGA information communication unit 212A1 (step S108).

[0029] The FPGA application writing unit 213A2 of the migration destination server 20A2 writes the application information received by the FPGA information communication unit 212A2 of the migration destination server 20A2 in step S108 to the FPGA 22A2 of the migration destination server 20A2 (step S109). This completes the transfer of the application information from the FPGA 22A1 of the migration source server 20A1 to the FPGA 22A2 of the migration destination server 20A2, and the migration process is completed.

[0030] 2, the case where the application information of the FPGA 22A1 of the migration source server 20A1 is stored in the FPGA information storage unit 215A1 in step S104, and then the migration-related processing in steps S106 to S109 is performed is described, but this is not limited to this. For example, in order to shorten the time required for migration, the migration-related processing in steps S106 to S109 may be started before the recording of the application information in the FPGA information storage unit 215A1 is completed in step S104.

[0031] As is clear from the above, the migration system 100A1 according to the first embodiment includes a migration source server 20A1 (also referred to as a first processing device) and a migration destination server 20A2 (also referred to as a second processing device). The migration source server 20A1 also includes an FPGA information collection unit 211A1 (also referred to as a migration information collection unit) that collects application information (also referred to as migration information) of an FPGA 22A1 (also referred to as a first circuit) included in the migration source server 20A1. The migration source server 20A1 also includes an FPGA information storage unit 215A1 (also referred to as a first migration information storage unit) that stores the application information collected by the FPGA information collection unit 211A1. The migration source server 20A1 also includes an FPGA information communication unit 212A1 (also referred to as a migration information transmission unit) that transmits application information stored in the FPGA information storage unit 215A1 to the migration destination server 20A2. The migration destination server 20A2 also includes an FPGA information communication unit 212A2 (also referred to as a migration information reception unit) that receives the application information transmitted by the FPGA information communication unit 212A1. The migration destination server 20A2 also includes an FPGA application writing unit 213A2 (also referred to as a migration information writing unit) that writes the application information received by the FPGA information communication unit 212A2 to an FPGA 22A2 (also referred to as a second circuit) provided in the migration destination server 20A2.

[0032] According to the first embodiment described above, when migration is performed to move application information indicating an application 221A1 running on the FPGA 22A1 of the migration source server 20A1 to the migration destination server 20A2, the application information is sent directly from the migration source server 20A1 to the migration destination server 20A2 without going through the controller 10A or another bitstream server, thereby shortening the time until the migration is completed. Therefore, the user can continue to use the application that was being used on the migration source server 20A1 on the migration destination server 20A2.

[0033] In the first embodiment, the migration source server 20A1 includes the FPGA information management control unit 21A1, the migration destination server 20A2 includes the FPGA information management control unit 21A2, and migration is performed by transmitting application information from the migration source server 20A1 to the migration destination server 20A2. However, this is not limiting. For example, the FPGA information management control unit 21A1 of the migration source server 20A1 may be implemented as a single application, and the FPGA information management control unit 21A2 may not be provided in the migration destination server 20A2. Then, the FPGA information management control unit 21A1 implemented as a single application may be transmitted from the migration source server 20A1 to the migration destination server 20A2, and the processing of the first embodiment (see FIG. 2) may be executed. In this case, the FPGA information management control unit 21A1, which is realized as one application, may transmit the information to the migration destination server 20A2, excluding the FPGA information collection unit 211A1.

[0034] [Modification of First Embodiment] Next, a modification of the first embodiment of the present invention will be described.

[0035] 3 is a schematic configuration diagram of a migration system 100A2 according to a modification of the first embodiment of the present invention. Note that parts of the migration system 100A2 ( FIG. 3 ) according to a modification of the first embodiment that have the same configuration as the migration system 100A1 ( FIG. 1 ) according to the first embodiment are denoted by the same reference numerals, and their description will be omitted. Furthermore, the processing performed in the migration system 100A2 ( FIG. 3 ) according to the modification of the first embodiment is similar to the processing performed in the migration system 100A1 ( FIG. 1 ) according to the first embodiment (see FIG. 2 ), and therefore description thereof will be omitted.

[0036] A migration system 100A2 (FIG. 3) according to a modification of the first embodiment differs from the migration system 100A1 (FIG. 1) according to the first embodiment in that an FPGA information management control unit 21A1 of a migration source server 20A1 operates on a virtual machine 40A1. Also, a migration system 100A2 (FIG. 3) according to a modification of the first embodiment differs from the migration system 100A1 (FIG. 1) according to the first embodiment in that an FPGA information management control unit 21A2 of a migration destination server 20A2 operates on a virtual machine 40A2.

[0037] In the modified example of the first embodiment, the FPGA information management control unit 21A1 and the FPGA information management control unit 21A2 are implemented using virtual machines 40A1 and 40A2, respectively. However, this is not limiting. For example, the FPGA information management control unit 21A1 and the FPGA information management control unit 21A2 may be implemented using a container. In a virtual machine, the entire machine, including the hardware layer, is virtualized. In contrast, in a container, only the software layer at the operating system level or above is virtualized. According to the modified example of the first embodiment, there is no need to physically configure the FPGA information management control unit 21A1 of the migration source server 20A1 or the FPGA information management control unit 21A2 of the migration destination server 20A2. This reduces the manufacturing costs of the migration source server 20A1 and the migration destination server 20A2.

[0038] Second Embodiment Next, a second embodiment of the present invention will be described.

[0039] 4 is a schematic configuration diagram of a migration system 100B1 according to a second embodiment of the present invention. The migration system 100B1 includes a controller 10B, a migration source server 20B1, and a migration destination server 20B2. The controller 10B, the migration source server 20B1, and the migration destination server 20B2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100B1 according to the second embodiment of the present invention performs live migration, in which an application running on the migration source server 20B1 is moved to the migration destination server 20B2 and executed thereon.

[0040] The controller 10B includes an FPGA migration control unit 11B, an FPGA information collection control unit 12B, an FPGA information management control unit 13B, an FPGA application write control unit 14B, and an FPGA status write control unit 15B. The FPGA migration control unit 11B receives a migration instruction from an administrator of the migration system 100B1 or the like, and starts live migration processing by the migration system 100B1.

[0041] The FPGA information collection control unit 12B instructs the FPGA information collection unit 211B1 of the migration source server 20B1 to collect migration information of the FPGA 22B1 of the migration source server 20B1. In the second embodiment, the migration information includes application information (also referred to as circuit information) indicating an application executed by the FPGA 22A1 of the migration source server 20A1, and state information indicating the state of the application.

[0042] The FPGA information management control unit 13B instructs the FPGA information management control unit 21B1 of the migration source server 20B1 to perform live migration processing from the migration source server 20B1 to the migration destination server 20B2. The FPGA application writing control unit 14B instructs the FPGA application writing unit 213B1 of the migration source server 20B1 to write application information of the FPGA 22B1 of the migration source server 20A1 to the FPGA 22B2 of the migration destination server 20B2.

[0043] The FPGA status writing control unit 15B instructs the FPGA status writing unit 214B1 of the migration source server 20B1 to write status information indicating the status of the application being executed in the FPGA 22B1 of the migration source server 20A1 to the FPGA 22B2 of the migration destination server 20B2.

[0044] The migration source server 20B1 includes an FPGA information management control unit 21B1 and an FPGA 22B1. The FPGA information management control unit 21B1 includes an FPGA information collection unit 211B1, an FPGA information communication unit 212B1, an FPGA application writing unit 213B1, an FPGA status writing unit 214B1, and an FPGA information storage unit 215B1. The FPGA information collection unit 211B1 collects application information indicating an application 221B1 executed by the FPGA 22B1 of the migration source server 20B1, and stores the application information in the FPGA information storage unit 215A1 as an FPGA application information DB 2151A1.

[0045] In addition, the FPGA information collection unit 211B1 collects status information indicating the status of the application 221B1 executed by the FPGA 22B1 of the migration source server 20B1 and stores the status information in the FPGA information storage unit 215A1 as an FPGA status information DB 2152B1. The FPGA information communication unit 212B1 communicates between the migration source server 20B1, the controller 10B, and the migration destination server 20B2. For example, the FPGA information communication unit 212B1 receives instructions regarding migration from the controller 10B, and transmits application information and status information of the FPGA 22A1 of the migration source server 20B1 directly to the migration destination server 20B2 without going through the controller 10A or another device (e.g., a bitstream server).

[0046] The FPGA application writing unit 213B1 transmits application information of the FPGA 22B1 of the migration source server 20B1 to the migration destination server 20B2 via the FPGA information communication unit 212B1, thereby writing the application information to the FPGA 22B2 provided in the migration destination server 20B2. The FPGA status writing unit 214B1 transmits status information of the FPGA 22B1 of the migration source server 20B1 to the migration destination server 20B2 via the FPGA information communication unit 212B1, thereby writing the status information to the FPGA 22B2 provided in the migration destination server 20B2.

[0047] The FPGA information storage unit 215B1 is a storage device such as a memory, and stores an FPGA application information DB 2151B1, an FPGA status information DB 2152B1, etc. The FPGA application information DB 2151B1 is application information collected by the FPGA information collection unit 211B1, such as application information of the FPGA 22B1 of the migration source server 20B1. The FPGA status information DB 2152B1 is status information collected by the FPGA information collection unit 211B1, such as status information of the FPGA 22B1 of the migration source server 20B1. The FPGA 22B1 is an integrated circuit whose circuit configuration can be changed by the user after manufacturing. The FPGA 22B1 executes an application 221B1.

[0048] The configuration of the migration destination server 20B2 is the same as the configuration of the migration source server 20B1. That is, the migration destination server 20B2 is provided with an FPGA information management control unit 21B2 and an FPGA 22B2 as components corresponding to the FPGA information management control unit 21B1 and FPGA 22B1 provided in the migration source server 20B1. Therefore, in the second embodiment, only the configuration of the migration source server 20B1 will be described, and a description of the configuration of the migration destination server 20B2 will be omitted. The FPGA 22B2 executes an application 221B2.

[0049] 5 is a sequence diagram showing processing in the migration system 100B1 according to the second embodiment of the present invention. First, the FPGA migration control unit 11B receives a migration instruction from the migration source server 20B1 to the migration destination server 20B2, which is an instruction from an administrator of the migration system 100B1 or the like (step S201).

[0050] When FPGA migration control unit 11B receives the migration instruction, FPGA migration control unit 11B outputs an instruction to FPGA information collection control unit 12B to start collecting application information and state information of FPGA 22B1 of migration source server 20B1. FPGA information collection control unit 12B sends a collection request for application information and state information of FPGA 22B1 to migration source server 20B1 (step S202).

[0051] Upon receiving a request to collect application information and status information from the FPGA information collection control unit 12B, the FPGA information collection unit 211B1 of the migration source server 20B1 reads out application information indicating the application 221B1 being executed by the FPGA 22B1 of the migration source server 20B1 and status information indicating the status of the application 2121B1 (step S203).

[0052] Next, the FPGA information collection unit 211B1 stores the application information read in step S203 in the FPGA application information DB 2151B1 of the FPGA information storage unit 215B1, and stores the state information read in step S203 in the FPGA state information DB 2152B1 of the FPGA information storage unit 215B1 (step S204). Upon completion of the processing of step S204, the FPGA information collection unit 211B1 transmits a completion notification to the controller 10B notifying that the recording of the application information in the FPGA application information DB 2151B1 and the recording of the state information in the FPGA state information DB 2152B1 have been completed (step S205).

[0053] Next, when controller 10B receives the completion notification in step S205, FPGA application write control unit 14B of controller 10B transmits an instruction to write application information to migration source server 20B1 (step S206). When migration source server 20B1 receives the instruction to write application information in step S206, FPGA application writing unit 213B1 of migration source server 20B1 reads the application information stored in step S204 from FPGA application information DB 2151B1 (step S207).

[0054] Next, the FPGA application writing unit 213B1 of the migration source server 20B1 transmits the application information read in step S207 directly (i.e., without going through the controller 10B or another bitstream server) to the migration destination server 20B2 via the FPGA information communication unit 212B1 (step S208). The FPGA application writing unit 213B2 of the migration destination server 20B2 writes the application information received by the FPGA information communication unit 212B2 of the migration destination server 20B2 in step S208 to the FPGA 22B2 of the migration destination server 20B2 (step S209).

[0055] When the processing of step S209 is completed, the FPGA application writing unit 213B1 transmits a completion notification to the controller 10B via the FPGA information communication unit 212B1 notifying that writing of the application information to the FPGA 22B2 of the migration destination server 20B2 has been completed (step S210). When the controller 10B receives the completion notification in step S210, the FPGA status write control unit 15B of the controller 10B transmits an instruction to write the status information to the migration source server 20B1 (step S211).

[0056] When the migration source server 20B1 receives the instruction to write the state information in step S211, the FPGA state writer 214B1 of the migration source server 20B1 reads the state information stored in step S204 from the FPGA state information DB 2152B1 (step S212). Next, the FPGA state writer 214B1 of the migration source server 20B1 transmits the state information read in step S212 directly (i.e., without passing through the controller 10B or another bitstream server) to the migration destination server 20B2 via the FPGA information communication unit 212B1 (step S213).

[0057] FPGA status writing unit 214B2 of migration destination server 20B2 writes the status information received by FPGA information communication unit 212B2 of migration destination server 20B2 in step S213 to FPGA 22B2 of migration destination server 20B2 (step S214). This completes the transfer of application information and status information from FPGA 22B1 of migration source server 20B1 to FPGA 22B2 of migration destination server 20B2, and the migration process is completed.

[0058] 5, the case where the write process of the application information (i.e., steps S206 to S209 in FIG. 5) is performed first, followed by the write process of the state information (i.e., steps S211 to S214 in FIG. 5) has been described, but the present invention is not limited to this. For example, the write process of the state information may be performed first, followed by the write process of the application information, or the write process of the application information and the write process of the state information may be performed simultaneously.

[0059] 5 illustrates a case in which the application information and state information of FPGA 22B1 of migration source server 20B1 are stored in FPGA information storage unit 215B1 in step S204, and then the migration-related processing in steps S206 to S214 is performed, but this is not limiting. For example, in order to shorten the time required for migration, the migration-related processing in steps S206 to S214 may be started before recording of application information and state information in FPGA information storage unit 215B1 is completed in step S204.

[0060] As is clear from the above, the migration system 100B1 according to the first embodiment includes a migration source server 20B1 (also referred to as a first processing device) and a migration destination server 20B2 (also referred to as a second processing device). The migration source server 20B1 also includes an FPGA information collection unit 211B1 (also referred to as a migration information collection unit) that collects application information and status information (also referred to as migration information) of an FPGA 22B1 (also referred to as a first circuit) included in the migration source server 20B1. The migration source server 20B1 also includes an FPGA information storage unit 215B1 (also referred to as a first migration information storage unit) that stores the application information and status information collected by the FPGA information collection unit 211B1. The migration source server 20B1 also includes an FPGA information communication unit 212B1 (also referred to as a migration information transmission unit) that transmits application information and status information stored in the FPGA information storage unit 215B1 to the migration destination server 20B2. The migration destination server 20B2 also includes an FPGA information communication unit 212B2 (also referred to as a migration information reception unit) that receives the application information and status information transmitted by the FPGA information communication unit 212B1. The migration destination server 20B2 also includes an FPGA application writing unit 213B2 and an FPGA status writing unit 214B2 (also referred to as a migration information writing unit) that write the application information and status information received by the FPGA information communication unit 212B2 to an FPGA 22B2 (also referred to as a second circuit) provided in the migration destination server 20B2.

[0061] According to the second embodiment described above, when migration is performed to move application information and status information indicating application 221B1 running on FPGA 22B1 of migration source server 20B1 to migration destination server 20B2, the application information and status information are sent directly from migration source server 20B1 to migration destination server 20B2 without going through controller 10B or another bitstream server, thereby shortening the time until migration is completed. Therefore, the user can continue to use the application that was being used on migration source server 20B1 on migration destination server 20B2 from the state indicated by the status information.

[0062] In the second embodiment, the migration source server 20B1 includes the FPGA information management control unit 21B1, the migration destination server 20B2 includes the FPGA information management control unit 21B2, and migration is performed by transmitting application information and status information from the migration source server 20B1 to the migration destination server 20B2. However, this is not limiting. For example, the FPGA information management control unit 21B1 of the migration source server 20B1 may be implemented as a single application, and the FPGA information management control unit 21B2 may not be provided in the migration destination server 20B2. Then, the FPGA information management control unit 21B1 implemented as a single application may be transmitted from the migration source server 20B1 to the migration destination server 20B2, and the processing of the second embodiment (see FIG. 5) may be executed. In this case, the FPGA information management control unit 21B1, which is realized as one application, may transmit the information to the migration destination server 20B2, excluding the FPGA information collection unit 211B1.

[0063] [Modification of Second Embodiment] Next, a modification of the second embodiment of the present invention will be described.

[0064] 6 is a schematic configuration diagram of a migration system 100B2 according to a modification of the second embodiment of the present invention. Note that parts of the migration system 100B2 ( FIG. 6 ) according to a modification of the second embodiment that have the same configuration as the migration system 100B1 ( FIG. 4 ) according to the second embodiment are denoted by the same reference numerals, and their description will be omitted. Furthermore, the processing performed in the migration system 100B2 ( FIG. 6 ) according to the modification of the second embodiment is similar to the processing performed in the migration system 100B1 ( FIG. 4 ) according to the second embodiment (see FIG. 5 ), and therefore description thereof will be omitted.

[0065] A migration system 100B2 (FIG. 6) according to a modification of the second embodiment differs from the migration system 100B1 (FIG. 4) according to the second embodiment in that an FPGA information management control unit 21B1 of a migration source server 20B1 operates on a virtual machine 40B1. Also, a migration system 100B2 (FIG. 6) according to a modification of the second embodiment differs from the migration system 100B1 (FIG. 4) according to the second embodiment in that an FPGA information management control unit 21B2 of a migration destination server 20B2 operates on a virtual machine 40B2.

[0066] In the modified example of the second embodiment, the FPGA information management control unit 21B1 and the FPGA information management control unit 21B2 are implemented by the virtual machine 40B1 and the virtual machine 40B2, but this is not limiting. For example, the FPGA information management control unit 21B1 and the FPGA information management control unit 21B2 may be implemented by a container. In a virtual machine, the entire machine, including the hardware layer, is virtualized. On the other hand, in a container, only the software layer at the operating system level or above is virtualized.

[0067] According to the modified example of the second embodiment, there is no need to physically configure the FPGA information management control unit 21B1 of the migration source server 20B1 or the FPGA information management control unit 21B2 of the migration destination server 20B2, which reduces the manufacturing costs of the migration source server 20B1 and the migration destination server 20B2.

[0068] In the first and second embodiments and their modifications, a case has been described in which an application executed on a server equipped with an FPGA is migrated to continue execution on another server equipped with another FPGA, but the present invention is not limited to this. For example, the processing of the first and second embodiments and their modifications may be performed to continue execution of an application executed on a server equipped with a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) on another server equipped with another CPU or GPU.

[0069] The controllers 10A, 10B, migration source servers 20A1, 20B1, and migration destination servers 20A2, 20B2 according to the first and second embodiments and their modifications described above each include a processor and a memory. The processor executes programs stored in the memory to perform the functions of each unit of these devices. Some or all of the functions of each unit of these devices may be realized using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The programs may be recorded on a computer-readable recording medium. The computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, a semiconductor storage device (for example, an SSD (Solid State Drive)), or a storage device such as a hard disk or semiconductor storage device built into a computer system. The above program may be transmitted via a telecommunications line.

[0070] The present invention is applicable to a migration system, a processing device, a migration method, and the like that require shortening the time required to complete migration.

[0071] DESCRIPTION OF SYMBOLS 10A, 10B... Controller, 11A, 11B... FPGA migration control unit, 12A, 12B... FPGA information collection control unit, 13A, 13B... FPGA information management control unit, 14A, 14B... FPGA application write control unit, 15B... FPGA status write control unit, 20A1, 20B1... Migration source server, 20A2, 20B2... Migration destination server, 21A1, 21A2, 21B1, 21B2... FPGA information management control unit, 22A1, 22A2, 22B1, 22B2... FPGA, 100A1, 100A2, 100B1, 100B2... Migration system, 211A1, 211A2, 211B1, 211B2...FPGA information collecting unit 212A1, 212A2, 212B1, 212B2...FPGA information communicating unit 213A1, 213A2, 213B1, 213B2...FPGA application writing unit 214B1, 214B2...FPGA status writing unit 215A1, 215A2, 215B1, 215B2...FPGA information storage unit

Claims

1. A migration system comprising a first processing device and a second processing device, wherein the first processing device comprises: a migration information collection unit that collects migration information of a first circuit comprised in the first processing device; a first migration information storage unit that stores the migration information collected by the migration information collection unit; and a migration information transmission unit that transmits the migration information stored in the first migration information storage unit to the second processing device; and the second processing device comprises: a migration information reception unit that receives the migration information transmitted by the migration information transmission unit; and a migration information writing unit that writes the migration information received by the migration information reception unit to a second circuit comprised in the second processing device.

2. The migration system according to claim 1, wherein the migration information includes application information indicating an application executed on the first processing device.

3. The migration system according to claim 2, wherein the migration information further includes status information indicating the status of the application.

4. The migration system according to any one of claims 1 to 3, wherein the first circuit and the second circuit are FPGAs (Field-Programmable Gate Arrays).

5. A processing device comprising: a migration information collection unit that collects first migration information of a first circuit provided in the processing device; a first migration information storage unit that stores the first migration information collected by the migration information collection unit; a migration information transmission unit that transmits the first migration information stored in the first migration information storage unit to another processing device; a migration information reception unit that receives second migration information of a second circuit provided in the other processing device; and a migration information writing unit that writes the second migration information received by the migration information reception unit to the first circuit.

6. A migration method using a first processing device and a second processing device, wherein the first processing device collects migration information of a first circuit provided in the first processing device, the first processing device stores the collected migration information, the first processing device transmits the migration information stored in the first processing device to the second processing device, the second processing device receives the migration information transmitted by the first processing device, and the second processing device writes the migration information received by the second processing device to a second circuit provided in the second processing device.

Images