Migration system, processing device, and migration method

Abstract

A migration system according to one aspect of the present invention includes a first processing device and a second processing device. Said migration system comprises: a migration information extraction unit that extracts first migration information of a first circuit of the first processing device using a first driver, which is from among a plurality of drivers for use in processing in a plurality of circuits and which is used for the first circuit; and a migration information writing unit that uses a second driver, which is from among the plurality of drivers and which is used for a second circuit of the second processing device, to write, into the second processing device, second migration information based on the first migration information extracted by the migration information extraction unit.

Description

Migration system, processing device, and migration method

[0001] The present invention relates to a migration system, a processing device, and a migration method.

[0002] Field programmable gate arrays (FPGAs), which are suitable for low power consumption, low latency, and high-speed processing, are often used for processing such as AI (artificial intelligence), and are also being put to practical use on the cloud. During system maintenance and other such operations, it is necessary to migrate stateful applications running on FPGAs. Non-Patent Document 1 proposes live migration technology for FPGAs (i.e., technology that transfers functions and processing states to another FPGA without stopping the functions and processing running on the FPGA).

[0003] A. Fukuhara, et al. "FPGA context-based live migration maintaining network consistency." 2020 Eighth International Symposium on Computing and Networking Workshops (CANDARW). IEEE, 2020.

[0004] In the system described in Non-Patent Document 1, in order to collect information about FPGAs from a migration source server equipped with an FPGA, it was necessary to install a dedicated driver corresponding to the FPGA in the migration source server. Also, in the system described in Non-Patent Document 1, in order to write information in a migration destination server equipped with an FPGA, it was necessary to install a dedicated driver corresponding to the FPGA in the migration destination server. Therefore, in the system described in Non-Patent Document 1, it was only possible to migrate FPGAs that were compatible with the dedicated driver installed in the server, and it was not possible to migrate FPGAs that were not compatible with the dedicated driver.

[0005] In view of the above circumstances, an object of the present invention is to provide a migration system, a processing device, and a migration method that can perform migration regardless of the type of circuitry included in the processing device.

[0006] One aspect of the present invention is a migration system comprising a first processing device and a second processing device, the migration system comprising: a migration information extraction unit that extracts first migration information for the first circuit using a first driver used for a first circuit of the first processing device from among a plurality of drivers used to perform processing on a plurality of circuits; and a migration information writing unit that writes second migration information based on the first migration information extracted by the migration information extraction unit to the second processing device using a second driver used for a second circuit of the second processing device from among the plurality of drivers.

[0007] Another aspect of the present invention is a processing device comprising: a migration information extraction unit that extracts first migration information for a first circuit using a first driver used for a first circuit of the processing device from among a plurality of drivers used to perform processing in a plurality of circuits; and a migration information writing unit that writes second migration information for the second circuit to the processing device using a second driver used for a second circuit of another processing device from among the plurality of drivers.

[0008] Another aspect of the present invention is a migration method using a first processing device and a second processing device, which extracts first migration information for the first circuit using a first driver used for a first circuit of the first processing device from among a plurality of drivers used to perform processing on a plurality of circuits, and writes second migration information based on the extracted first migration information to the second processing device using a second driver used for a second circuit of the second processing device from among the plurality of drivers.

[0009] According to the present invention, it is possible to provide a migration system, a processing device, and a migration method that can perform migration regardless of the type of circuitry included in the processing device.

[0010] FIG. 1 is a schematic configuration diagram of a migration system according to a first embodiment of the present invention. FIG. 2 is a sequence diagram showing processing in the migration system according to the first embodiment of the present invention. FIG. 3 is a schematic configuration diagram of a migration system according to a second embodiment of the present invention. FIG. 4 is a sequence diagram showing processing in the migration system according to the second embodiment of the present invention. FIG. 5 is a schematic configuration diagram of a migration system according to a third embodiment of the present invention. FIG. 6 is a diagram showing an example of data stored in an FPGA information conversion DB according to the third embodiment of the present invention. FIG. 7 is a schematic configuration diagram of a migration system according to a fourth embodiment of the present invention. FIG. 8 is a sequence diagram showing processing in the migration system according to the fourth embodiment of the present invention.

[0011] Hereinafter, embodiments of the present invention will be described with reference to the drawings. The embodiments described below are merely examples, and the embodiments to which the present invention is applied are not limited to the following embodiments.

[0012] First Embodiment First, a first embodiment of the present invention will be described.

[0013] 1 is a schematic configuration diagram of a migration system 100A according to a first embodiment of the present invention. The migration system 100A includes a controller 10A, a migration source server 20A1, and a migration destination server 20A2. The controller 10A, the migration source server 20A1, and the migration destination server 20A2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100A according to the first embodiment of the present invention performs live migration, in which an application running on the migration source server 20A1 is moved to the migration destination server 20A2 and executed thereon.

[0014] The controller 10A includes an FPGA migration control unit 11A, an FPGA information collection unit 13A, an FPGA application write control unit 15A, and an FPGA information storage unit 17A. The FPGA migration control unit 11A receives a migration instruction from an administrator of the migration system 100A or the like, and starts live migration processing by the migration system 100A.

[0015] The FPGA information collection unit 13A collects application information (also referred to as circuit information) of the FPGA 22A1 included in the migration source server 20A1 and stores it as an FPGA application information DB (database) 171A in the FPGA information storage unit 17A. The FPGA application write control unit 15A uses the data stored in the FPGA application information DB 171A to write the application information of the FPGA 22A1 of the migration source server 20A1 to the FPGA 22A2 of the migration destination server 20A2. The FPGA information storage unit 17A is a storage device such as a memory. In the first embodiment, the FPGA information storage unit 17A stores the FPGA application information DB 171A.

[0016] The migration source server 20A1 includes an FPGA abstraction unit 21A1 and an FPGA 22A1. The FPGA abstraction unit 21A1 enables information collection and writing to various types of FPGAs from an application implemented in software. The FPGA abstraction unit 21A1 includes drivers compatible with various FPGAs and a driver selection function. When accessing the FPGA 22A1, the FPGA abstraction unit 21A1 selects a driver compatible with the FPGA to be accessed, thereby enabling information collection and writing to various FPGAs.

[0017] For example, the FPGA abstraction unit 21A1 stores a model number for identifying the type of FPGA and a driver used by the FPGA with that model number in association with each other. The FPGA abstraction unit 21A1 does not store only one pair of a model number for identifying the type of FPGA and a driver used by the FPGA with that model number, but stores multiple pairs. For example, the FPGA abstraction unit 21A1 stores a first model number indicating the type of FPGA in association with a first driver used by the FPGA with that first model number, and stores a second model number indicating the type of FPGA in association with a second driver used by the FPGA with that second model number. The FPGA 22A1 is an integrated circuit whose circuit configuration can be changed by a user after manufacturing. The FPGA 22A1 executes an application 221A1.

[0018] The configuration of the migration destination server 20A2 is the same as the configuration of the migration source server 20A1. That is, the migration destination server 20A2 is provided with an FPGA abstraction unit 21A2 and an FPGA 22A2 as components corresponding to the FPGA abstraction unit 21A1 and FPGA 22A1 provided in the migration source server 20A1. Therefore, in the first embodiment, only the configuration of the migration source server 20A1 will be described, and a description of the configuration of the migration destination server 20A2 will be omitted. The FPGA 22A2 executes an application 221A2.

[0019] 2 is a sequence diagram showing processing in the migration system 100A according to the first embodiment of the present invention. First, the FPGA migration control unit 11A receives a migration instruction from the administrator of the migration system 100A or the like, which is an instruction to migrate from the migration source server 20A1 to the migration destination server 20A2 (step S101).

[0020] When the FPGA migration control unit 11A receives the migration instruction, the FPGA migration control unit 11A outputs an instruction to the FPGA information collection unit 13A to start collecting application information of the FPGA 22A1 of the migration source server 20A1. The FPGA information collection unit 13A transmits a transmission request for the application information of the FPGA 22A1 to the migration source server 20A1 (step S102).

[0021] Next, the FPGA abstraction unit 21A1 selects a driver corresponding to the FPGA 22A1 from among the plurality of drivers stored in the FPGA abstraction unit 21A1, and extracts from the FPGA 22A1 application information indicating the application 221A1 being executed by the FPGA 22A1 and state information indicating the state of the application 221A1 (step S103). Next, the FPGA abstraction unit 21A1 transmits the application information of the FPGA 22A1 extracted in step S103 to the controller 10A (step S104).

[0022] Next, the FPGA information collection unit 13A stores the application information of the FPGA 22A1 received in step S104 in the FPGA application information DB 171A (step S105). When the processing of step S105 is finished, the FPGA information collection unit 13A notifies the FPGA application write control unit 15A that the processing of step S105 is complete. When the FPGA application write control unit 15A receives notification from the FPGA information collection unit 13A that the processing of step S105 is complete, the FPGA application write control unit 15A starts writing the application information to the FPGA 22A2 of the migration destination server 20A2. First, the FPGA application write control unit 15A transmits the application information of the FPGA 22A1 of the migration source server 20A1 stored in the FPGA application information DB 171A in step S105 to the migration destination server 20A2 (step S106).

[0023] Next, the FPGA abstraction unit 21A2 selects a driver corresponding to the FPGA 22A2 from among the multiple drivers stored in the FPGA abstraction unit 21A2, and writes the application information of the FPGA 22A1 of the migration source server 20A1 received in step S106 to the FPGA 22A2 (step S107).

[0024] When the processing of step S107 is completed, the FPGA abstraction unit 21A2 transmits a notification of the completion of the processing of step S107 to the controller 10A (step S108). This completes the transfer of the application information from the FPGA 22A1 of the migration source server 20A1 to the FPGA 22A2 of the migration destination server 20A2, and the migration processing is completed.

[0025] As is clear from the above description, the migration system 100A according to the first embodiment includes a migration source server 20A1 (also referred to as a first processing device) and a migration destination server 20A2 (also referred to as a second processing device). The migration system 100A also includes an FPGA abstraction unit 21A1 (also referred to as a migration information extraction unit) that extracts application information (also referred to as first migration information) of the FPGA 22A1 by using a first driver used for the FPGA 22A1 (also referred to as a first circuit) of the migration source server 20A1 from among a plurality of drivers used for performing processing in a plurality of FPGAs 22A1 and 22A2 (also referred to as circuits). The migration system 100A also includes an FPGA abstraction unit 21A2 (also referred to as a migration information writing unit) that uses a second driver from among multiple drivers to be used for the FPGA 22A2 (also referred to as a second circuit) of the migration destination server 20A2 (also referred to as a second processing device) to write application information (also referred to as second migration information) based on the application information of the FPGA 22A1 extracted by the FPGA abstraction unit 21A1 to the migration destination server 20A2.

[0026] In the first embodiment, the application information extracted from FPGA 22A1 of migration source server 20A1 (also referred to as first migration information) and the application information written to FPGA 22A2 of migration destination server 20A2 (also referred to as second migration information) are the same, and include application information indicating application 221A1 executed on migration source server 20A1.

[0027] According to the first embodiment described above, there is no need to implement a corresponding driver for each FPGA, and application information can be migrated regardless of the type of FPGA equipped in the migration source server 20A1 and the migration destination server 20A2.

[0028] Furthermore, in the first embodiment described above, multiple drivers used in multiple model numbers of FPGAs are stored in the migration source server 20A1 and the migration destination server 20A2, so there is no need to store multiple drivers in the controller 10A.

[0029] Second Embodiment Next, a second embodiment of the present invention will be described.

[0030] 3 is a schematic configuration diagram of a migration system 100B according to a second embodiment of the present invention. The migration system 100B includes a controller 10B, a migration source server 20B1, and a migration destination server 20B2. The controller 10B, the migration source server 20B1, and the migration destination server 20B2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100B according to the second embodiment of the present invention performs live migration, in which an application running on the migration source server 20B1 is moved to the migration destination server 20B2 and executed thereon.

[0031] The controller 10B includes an FPGA migration control unit 11B, an FPGA information collection unit 13B, an FPGA application write control unit 15B, an FPGA status write control unit 16B, and an FPGA information storage unit 17B. The FPGA migration control unit 11B receives a migration instruction from an administrator of the migration system 100B or the like, and starts live migration processing by the migration system 100B.

[0032] The FPGA information collection unit 13B collects application information (also referred to as circuit information) of the FPGA 22B1 included in the migration source server 20B1, and stores it as FPGA application information DB 171B in the FPGA information storage unit 17B. The FPGA information collection unit 13B also collects status information indicating the status of the application 221B1 of the FPGA 22B1 included in the migration source server 20B1, and stores it as FPGA status information DB 173B in the FPGA information storage unit 17B.

[0033] The FPGA application write control unit 15B uses data stored in the FPGA application information DB 171B to write application information of the FPGA 22B1 of the migration source server 20B1 to the FPGA 22B2 of the migration destination server 20B2. The FPGA status write control unit 16B uses data stored in the FPGA status information DB 173B to write status information of the FPGA 22B1 of the migration source server 20B1 to the FPGA 22B2 of the migration destination server 20B2. The FPGA information storage unit 17B is a storage device such as a memory. In the second embodiment, the FPGA information storage unit 17B stores the FPGA application information DB 171B and the FPGA status information DB 173B.

[0034] The migration source server 20B1 includes an FPGA abstraction unit 21B1 and an FPGA 22B1. The FPGA abstraction unit 21B1 enables information collection and writing to various types of FPGAs from applications implemented in software. The FPGA abstraction unit 21B1 includes drivers compatible with various FPGAs and a driver selection function. When accessing the FPGA 22B1, the FPGA abstraction unit 21B1 selects a driver compatible with the FPGA to be accessed, thereby enabling information collection and writing to various FPGAs.

[0035] For example, the FPGA abstraction unit 21B1 stores a model number for identifying the type of FPGA and a driver used by the FPGA with that model number in association with each other. The FPGA abstraction unit 21B1 does not store only one pair of a model number for identifying the type of FPGA and a driver used by the FPGA with that model number, but stores multiple pairs. For example, the FPGA abstraction unit 21B1 stores a first model number indicating the type of FPGA and a first driver used by the FPGA with that first model number in association with each other, and stores a second model number indicating the type of FPGA and a second driver used by the FPGA with that second model number in association with each other. The FPGA 22B1 is an integrated circuit whose circuit configuration can be changed by the user after manufacturing. The FPGA 22B1 executes the application 221B1.

[0036] The configuration of the migration destination server 20B2 is the same as the configuration of the migration source server 20B1. That is, the migration destination server 20B2 has an FPGA abstraction unit 21B2 and an FPGA 22B2 as components corresponding to the FPGA abstraction unit 21B1 and FPGA 22B1 provided in the migration source server 20B1. Therefore, in the second embodiment, only the configuration of the migration source server 20B1 will be described, and a description of the configuration of the migration destination server 20B2 will be omitted. The FPGA 22B2 executes an application 221B2. The FPGA 22B2 stores the state 222B1 in which the FPGA 22B2 is in.

[0037] 4 is a sequence diagram showing processing in the migration system 100B according to the second embodiment of the present invention. First, the FPGA migration control unit 11B receives a migration instruction from the administrator of the migration system 100B or the like, which is an instruction to migrate from the migration source server 20B1 to the migration destination server 20B2 (step S201).

[0038] When FPGA migration control unit 11B receives the migration instruction, FPGA migration control unit 11B outputs an instruction to FPGA information collection unit 13B to start collecting application information of FPGA 22B1 of migration source server 20B1. FPGA information collection unit 13B transmits a transmission request for application information of FPGA 22B1 to migration source server 20B1 (step S202).

[0039] Next, FPGA abstraction unit 21B1 selects a driver corresponding to FPGA 22B1 from among the multiple drivers stored in FPGA abstraction unit 21B1, and extracts from FPGA 22B1 application information indicating application 221B1 being executed by FPGA 22B1 and state information indicating the state of application 221B1 (step S203). Next, FPGA abstraction unit 21B1 transmits the application information and state information of FPGA 22B1 extracted in step S203 to controller 10B (step S204).

[0040] Next, the FPGA information collection unit 13B stores the application information of the FPGA 22B1 received in step S204 in the FPGA application information DB 171B, and stores the state information of the FPGA 22B1 received in step S204 in the FPGA state information DB 173B (step S205). When the processing of step S205 is completed, the FPGA information collection unit 13B notifies the FPGA application write control unit 15B that the processing of step S205 is completed.

[0041] When the FPGA application write control unit 15B receives a notification from the FPGA information collection unit 13B that the processing of step S205 has been completed, the FPGA application write control unit 15B starts writing the application information and status information to the FPGA 22B2 of the migration destination server 20B2. First, the FPGA application write control unit 15B transmits the application information of the FPGA 22B1 of the migration source server 20B1 stored in the FPGA application information DB 171B in step S205 to the migration destination server 20B2 (step S206).

[0042] Next, FPGA abstraction unit 21B2 selects a driver corresponding to FPGA 22B2 from the plurality of drivers stored in FPGA abstraction unit 21B2, and writes the application information of FPGA 22B1 of migration source server 20B1 received in step S206 to FPGA 22B2 (step S207). Upon completion of the processing of step S207, FPGA abstraction unit 21B2 transmits a notification that the processing of step S207 has been completed to controller 10B (step S208).

[0043] Next, FPGA status write control unit 16B transmits the status information of FPGA 22B1 of migration source server 20B1 stored in FPGA status information DB 173B in step S205 to migration destination server 20B2 (step S209). Next, FPGA status write control unit 16B writes the status information of FPGA 22B1 of migration source server 20B1 received in step S209 to FPGA 22B2 (step S210).

[0044] When the processing of step S210 is completed, FPGA abstraction unit 21B2 transmits a notification of the completion of the processing of step S210 to controller 10B (step S211). This completes the transfer of application information and state information from FPGA 22B1 of migration source server 20B1 to FPGA 22B2 of migration destination server 20B2, and the migration processing is completed.

[0045] 4, a case has been described in which the process of writing application information from the controller 10B to the migration destination server 20B2 (the process of steps S206 to S208 in FIG. 4) is completed, followed by the process of writing status information from the controller 10B to the migration destination server 20B2 (the process of steps S209 to S211 in FIG. 4). However, this is not limiting. For example, the process of writing status information from the controller 10B to the migration destination server 20B2 may be performed after the process of writing application information from the controller 10B to the migration destination server 20B2. Furthermore, the process of writing application information from the controller 10B to the migration destination server 20B2 and the process of writing status information from the controller 10B to the migration destination server 20B2 may be performed simultaneously.

[0046] As is clear from the above, the migration system 100B according to the second embodiment includes a migration source server 20B1 (also referred to as a first processing device) and a migration destination server 20B2 (also referred to as a second processing device). The migration system 100B includes an FPGA abstraction unit 21B1 (also referred to as a migration information extraction unit) that extracts application information (also referred to as first migration information) of the FPGA 22B1 by using a first driver used for the FPGA 22B1 (also referred to as a first circuit) of the migration source server 20B1 from among a plurality of drivers used to perform processing in a plurality of FPGAs 22B1 and 22B2 (also referred to as circuits). The migration system 100B also includes an FPGA abstraction unit 21B2 (also referred to as a migration information writing unit) that uses a second driver from among multiple drivers to be used for the FPGA 22B2 (also referred to as a second circuit) of the migration destination server 20B2 (also referred to as a second processing device) to write application information (also referred to as second migration information) based on the application information of the FPGA 22B1 extracted by the FPGA abstraction unit 21B1 to the migration destination server 20B2.

[0047] In the second embodiment, the application information and status information (also referred to as first migration information) extracted from FPGA 22B1 of migration source server 20B1 are the same as the application information and status information (also referred to as second migration information) written to FPGA 22B2 of migration destination server 20B2, and include application information indicating application 221B1 executed on migration source server 20B1 and status information indicating the state of application 221B1.

[0048] According to the second embodiment described above, there is no need to implement a corresponding driver for each FPGA, and migration of application information and status information can be performed regardless of the type of FPGA equipped in the migration source server 20B1 and the migration destination server 20B2.

[0049] Furthermore, in the second embodiment described above, multiple drivers used in multiple model numbers of FPGAs are stored in the migration source server 20B1 and the migration destination server 20B2, so there is no need to store multiple drivers in the controller 10B.

[0050] Third Embodiment Next, a third embodiment of the present invention will be described.

[0051] 5 is a schematic configuration diagram of a migration system 100C according to a third embodiment of the present invention. The migration system 100C includes a controller 10C, a migration source server 20C1, and a migration destination server 20C2. The controller 10C, the migration source server 20C1, and the migration destination server 20C2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100C according to the third embodiment of the present invention performs live migration, in which an application running on the migration source server 20C1 is moved to the migration destination server 20C2 and executed thereon.

[0052] The controller 10C includes an FPGA migration control unit 11C, an FPGA model number information collection unit 12C, an FPGA information collection unit 13C, an FPGA information conversion unit 14C, an FPGA application write control unit 15C, and an FPGA information storage unit 17C. The FPGA migration control unit 11C receives a migration instruction from an administrator of the migration system 100C or the like, and starts live migration processing by the migration system 100C.

[0053] The FPGA model number information collection unit 12C collects model number information indicating the model number of the FPGA 22C1 included in the migration source server 20C1 and stores it as FPGA model number information 1711C in a migration source FPGA information DB 171C of the FPGA information storage unit 17C. The FPGA model number information collection unit 12C also collects model number information indicating the model number of the FPGA 22C2 included in the migration destination server 20C2 and stores it as FPGA model number information 1731C in a migration destination FPGA information DB 173C of the FPGA information storage unit 17C.

[0054] The FPGA information collection unit 13C collects application information (also referred to as circuit information) of the FPGA 22C1 included in the migration source server 20C1 and stores it in a migration source FPGA information DB 171C of the FPGA information storage unit 17C as FPGA application information 1712C. The FPGA information collection unit 13C collects application information (also referred to as circuit information) of the FPGA 22C2 included in the migration source server 20C2 and stores it in a migration destination FPGA information DB 173C of the FPGA information storage unit 17C as FPGA application information 1732C.

[0055] The FPGA information conversion unit 14C refers to the FPGA information conversion DB172C, and uses the FPGA model number information 1711C stored in the migration source FPGA information DB171C and the FPGA model number information 1713C stored in the migration destination FPGA information DB173C to convert the FPGA application information 1712C in the migration source FPGA information DB171C into FPGA application information 1732C in the migration destination FPGA information DB173C, and stores it in the FPGA information conversion DB172C.

[0056] The FPGA application write control unit 15C writes FPGA application information 1732C stored in the migration destination FPGA application information DB 173C to the FPGA 22C2 of the migration destination server 20C2. The FPGA information storage unit 17C is a storage device such as a memory. In the third embodiment, the FPGA information storage unit 17C stores a migration source FPGA information DB 171C, an FPGA information conversion DB 172C, and a migration destination FPGA information DB 173C.

[0057] 6 is a diagram illustrating an example of data stored in the FPGA information conversion DB 172C according to the third embodiment of the present invention. The FPGA information conversion DB 172C stores the "model number of the FPGA included in the migration source server" (e.g., "FPGA1"), the "model number of the FPGA included in the migration destination server" (e.g., "FPGA2"), and the "conversion method" (e.g., "conversion method 1") in association with each other. The "conversion method" is information used to convert FPGA migration information ("application information" in the third embodiment) identified by the "FPGA model number included in the migration source server" into FPGA migration information ("application information" in the third embodiment) identified by the "FPGA model number included in the migration destination server". For example, when the FPGA information conversion DB 172C stores N model numbers (N is an integer of 2 or more) as "model numbers of FPGAs included in the migration source server", the FPGA information conversion DB 172C stores the following: ２ -N) transformation methods must be stored.

[0058] The FPGA information conversion DB 172C may store N conversion methods for converting migration information of FPGAs with N model numbers into information in a predetermined format, and may also store N conversion methods for converting information in the predetermined format into migration information of FPGAs with N model numbers. ２ Therefore, it is only necessary to store 2N transformation methods instead of 1-N, thereby reducing the amount of information to be stored.

[0059] Returning to the explanation of FIG. 5 , the migration source server 20C1 includes an FPGA abstraction unit 21C1 and an FPGA 22C1. The FPGA abstraction unit 21C1 enables information collection and writing to various types of FPGAs from an application implemented in software. The FPGA abstraction unit 21C1 includes drivers compatible with various FPGAs and a driver selection function. When accessing the FPGA 22C1, the FPGA abstraction unit 21C1 selects a driver compatible with the FPGA to be accessed, thereby enabling information collection and writing to various FPGAs.

[0060] For example, the FPGA abstraction unit 21C1 stores a model number for identifying the type of FPGA and a driver used by the FPGA with that model number in association with each other. The FPGA abstraction unit 21C1 does not store only one pair of a model number for identifying the type of FPGA and a driver used by the FPGA with that model number, but stores multiple pairs. For example, the FPGA abstraction unit 21C1 stores a first model number indicating the type of FPGA in association with a first driver used by the FPGA with that first model number, and stores a second model number indicating the type of FPGA in association with a second driver used by the FPGA with that second model number. The FPGA 22C1 is an integrated circuit whose circuit configuration can be changed by the user after manufacturing. The FPGA 22C1 executes an application 221C1.

[0061] The configuration of the migration destination server 20C2 is the same as the configuration of the migration source server 20C1. That is, the migration destination server 20C2 has an FPGA abstraction unit 21C2 and an FPGA 22C2 as components corresponding to the FPGA abstraction unit 21C1 and FPGA 22C1 provided in the migration source server 20C1. Therefore, in the third embodiment, only the configuration of the migration source server 20C1 will be described, and a description of the configuration of the migration destination server 20C2 will be omitted. The FPGA 22C2 executes an application 221C2.

[0062] 7 is a sequence diagram showing processing in the migration system 100C according to the third embodiment of the present invention. First, the FPGA migration control unit 11C receives a migration instruction from the administrator of the migration system 100C or the like, which is an instruction to migrate from the migration source server 20C1 to the migration destination server 20C2 (step S301).

[0063] When the FPGA migration control unit 11C receives the migration instruction, the FPGA model number information collection unit 12C sends a request to the migration source server 20C1 to send model number information of the FPGA 22C1 (step S302). Next, the FPGA abstraction unit 21C1 reads model number information indicating the model number of the FPGA 22C1 from the FPGA 22C1 (step S303). Next, the FPGA abstraction unit 21C1 sends the model number information of the FPGA 22C1 read in step S303 to the controller 10A (step S304).

[0064] Next, the FPGA model number information collection unit 12C stores the model number information of the FPGA 22C1 received in step S304 in the migration source FPGA information DB 171C as FPGA model number information 1711C (step S305). Next, the FPGA model number information collection unit 12C transmits a transmission request for the model number information of the FPGA 22C2 to the migration destination server 20C2 (step S306).

[0065] Next, the FPGA abstraction unit 21C2 reads model number information indicating the model number of the FPGA 22C2 from the FPGA 22C2 (step S307). Next, the FPGA abstraction unit 21C2 transmits the model number information of the FPGA 22C2 read in step S307 to the controller 10C (step S308). Next, the FPGA model number information collection unit 12C stores the model number information of the FPGA 22C2 received in step S308 as FPGA model number information 1731C in the migration destination FPGA information DB 173C (step S309).

[0066] Next, the FPGA information collection unit 13C transmits a request to transmit application information of the FPGA 22C1 to the migration source server 20C1 (step S310). Next, the FPGA abstraction unit 21C1 selects a driver corresponding to the FPGA 22C1 from the plurality of drivers stored in the FPGA abstraction unit 21C1, and extracts application information indicating the application 221C1 running on the FPGA 22C1 from the FPGA 22C1 (step S311).

[0067] Next, the FPGA abstraction unit 21C1 transmits the application information of the FPGA 22C1 extracted in step S311 to the controller 10C (step S312). Next, the FPGA information collection unit 13C stores the application information of the FPGA 22C1 received in step S312 in the migration source FPGA application information DB 171C (step S313). When the processing of step S313 is finished, the FPGA information collection unit 13C notifies the FPGA information conversion unit 14C that the processing of step S313 has been completed.

[0068] 7 illustrates a case in which the process of acquiring model number information of FPGA 22C1 of migration source server 20C1 (steps S302 to S305) is performed, followed by the process of acquiring model number information of FPGA 22C2 of migration destination server 20C2 (steps S306 to S309), and then the process of acquiring application information of FPGA 22C1 of migration source server 20C1 (steps S310 to S313). However, the present invention is not limited to this. These processes may be performed in any order, and may also be performed simultaneously.

[0069] When the FPGA information conversion unit 14C receives from the FPGA information collection unit 13C that the processing of step S313 has been completed, it refers to the FPGA information conversion DB 172C and uses the FPGA model number information 1711C stored in the migration source FPGA information DB 171C and the FPGA model number information 1731C stored in the migration destination FPGA information DB 173C to convert the FPGA application information 1712C stored in the migration source FPGA information DB 171C into application information that can be used by the FPGA 22C2 of the migration destination server 20C2, and stores this as FPGA application information 1732C in the migration destination FPGA information DB 173C (step S314). When the process of step S314 is finished, the FPGA information conversion unit 14C notifies the FPGA application write control unit 15C that the process of step S314 has been completed.

[0070] When the FPGA application write control unit 15C receives a notification from the FPGA information conversion unit 14C that the processing of step S314 has been completed, the FPGA application write control unit 15C starts writing application information to the FPGA 22C2 of the migration destination server 20C2. First, the FPGA application write control unit 15C transmits the FPGA application information 1732C stored in the migration destination FPGA information DB 173C in step S314 to the migration destination server 20C2 (step S315).

[0071] Next, the FPGA abstraction unit 21C2 selects a driver corresponding to the FPGA 22C2 from the multiple drivers stored in the FPGA abstraction unit 21C2, and writes the FPGA application information 1732C received in step S315 to the FPGA 22C2 (step S316). Upon completion of the processing of step S316, the FPGA abstraction unit 21C2 transmits a notification that the processing of step S316 is complete to the controller 10C (step S317). This completes the transfer of the application information from the FPGA 22C1 of the migration source server 20C1 to the FPGA 22C2 of the migration destination server 20C2, and the migration processing is completed.

[0072] As is clear from the above, the migration system 100C according to the third embodiment includes a migration source server 20C1 (also referred to as a first processing device) and a migration destination server 20C2 (also referred to as a second processing device). The migration system 100C includes an FPGA abstraction unit 21C1 (also referred to as a migration information extraction unit) that extracts application information (also referred to as first migration information) of the FPGA 22C1 by using a first driver used for the FPGA 22C1 (also referred to as a first circuit) of the migration source server 20C1 from among a plurality of drivers used for performing processing in a plurality of FPGAs 22C1, 22C2 (also referred to as circuits). The migration system 100A also includes an FPGA information conversion unit 14C (also referred to as a conversion unit) that converts the application information extracted by the FPGA abstraction unit 21C1 into application information (also referred to as second migration information) that can be processed by the FPGA 22C2 (also referred to as a second circuit). The migration system 100C also includes an FPGA abstraction unit 21C2 (also referred to as a migration information writing unit) that writes the application information (also referred to as second migration information) converted by the FPGA information conversion unit 14C to the migration destination server 20C2 based on the application information of the FPGA 22C1 extracted by the FPGA abstraction unit 21C1, using a second driver used for the FPGA 22C2 of the migration destination server 20C2 (also referred to as a second processing device) from among multiple drivers.

[0073] In the third embodiment, the application information extracted from FPGA 22C1 of migration source server 20C1 (also referred to as first migration information) and the application information written to FPGA 22C2 of migration destination server 20C2 (also referred to as second migration information) include application information indicating application 221C1 executed on migration source server 20C1.

[0074] According to the third embodiment described above, migration can be performed regardless of the model number (also called type) of the FPGA (also called circuit) included in the migration source server 20C1 or the migration destination server 20C2.

[0075] Furthermore, according to the third embodiment described above, there is no need to implement a corresponding driver for each FPGA, and even if the migration source server 20C1 and the migration destination server 20C2 use different FPGAs, application information can be collected and written, and application information can be migrated even between FPGAs of different model numbers.

[0076] Furthermore, in the third embodiment described above, a plurality of drivers used in a plurality of model numbers of FPGAs are stored in the migration source server 20C1 and the migration destination server 20C2, so there is no need to store a plurality of drivers in the controller 10C.

[0077] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described.

[0078] 8 is a schematic configuration diagram of a migration system 100D according to a fourth embodiment of the present invention. The migration system 100D includes a controller 10D, a migration source server 20D1, and a migration destination server 20D2. The controller 10D, the migration source server 20D1, and the migration destination server 20D2 are connected to a network 30 such as the Internet and are capable of communicating with each other. The migration system 100D according to the fourth embodiment of the present invention performs live migration, in which an application running on the migration source server 20D1 is moved to the migration destination server 20D2 and executed thereon.

[0079] The controller 10D includes an FPGA migration control unit 11D, an FPGA model number information collection unit 12D, an FPGA information collection unit 13D, an FPGA information conversion unit 14D, an FPGA application write control unit 15D, an FPGA status write control unit 16D, and an FPGA information storage unit 17D. The FPGA migration control unit 11D receives a migration instruction from an administrator of the migration system 100D or the like, and starts live migration processing by the migration system 100D.

[0080] The FPGA model number information collection unit 12D collects model number information indicating the model number of the FPGA 22D1 included in the migration source server 20D1 and stores it as FPGA model number information 1711D in a migration source FPGA information DB 171D of the FPGA information storage unit 17D. The FPGA model number information collection unit 12D also collects model number information indicating the model number of the FPGA 22D2 included in the migration destination server 20D2 and stores it as FPGA model number information 1731D in a migration destination FPGA information DB 173D of the FPGA information storage unit 17D.

[0081] The FPGA information collection unit 13D collects application information (also referred to as circuit information) of the FPGA 22D1 included in the migration source server 20D1 and stores it in a migration source FPGA information DB 171D of the FPGA information storage unit 17D as FPGA application information 1712D. The FPGA information collection unit 13D collects application information (also referred to as circuit information) of the FPGA 22D2 included in the migration source server 20D2 and stores it in a migration destination FPGA information DB 173D of the FPGA information storage unit 17D as FPGA application information 1732D.

[0082] The FPGA information conversion unit 14D refers to the FPGA information conversion DB172D and uses the FPGA model number information 1711D stored in the migration source FPGA information DB171D and the FPGA model number information 1713D stored in the migration destination FPGA information DB173D to convert the FPGA application information 1712C and FPGA status information 1713D of the migration source FPGA information DB171D into FPGA application information 1732D and FPGA status information 1733D of the migration destination FPGA information DB173D, and stores them in the FPGA information conversion DB172D.

[0083] The FPGA application write control unit 15D writes FPGA application information 1732D stored in the migration destination FPGA application information DB 173D to the FPGA 22D2 of the migration destination server 20D2. The FPGA status write control unit 16D writes FPGA status information 1733D stored in the migration destination FPGA application information DB 173D to the FPGA 22D2 of the migration destination server 20D2. The FPGA information storage unit 17D is a storage device such as a memory. In the fourth embodiment, the FPGA information storage unit 17D stores a migration source FPGA information DB 171D, an FPGA information conversion DB 172D, and a migration destination FPGA information DB 173D.

[0084] The contents stored in the FPGA information conversion DB 172D according to the fourth embodiment are the same as the contents stored in the FPGA information conversion DB 172C according to the third embodiment. That is, the FPGA information conversion DB 172D stores the "FPGA model number of the migration source server" (e.g., "FPGA1"), the "FPGA model number of the migration destination server" (e.g., "FPGA2"), and the "conversion method" (e.g., "conversion method 1") in association with each other, as shown in FIG. 6. However, in the fourth embodiment, the "conversion method" is information used to convert the FPGA migration information ("application information" and "status information" in the fourth embodiment) identified by the "FPGA model number of the migration source server" into the FPGA migration information ("application information" and "status information" in the fourth embodiment) identified by the "FPGA model number of the migration destination server."

[0085] Returning to the explanation of FIG. 8 , the migration source server 20D1 includes an FPGA abstraction unit 21D1 and an FPGA 22D1. The FPGA abstraction unit 21D1 enables information collection and writing to various types of FPGAs from an application implemented in software. The FPGA abstraction unit 21D1 includes drivers compatible with various FPGAs and a driver selection function. When accessing the FPGA 22D1, the FPGA abstraction unit 21D1 selects a driver compatible with the FPGA to be accessed, thereby enabling information collection and writing to various FPGAs.

[0086] For example, the FPGA abstraction unit 21D1 stores a model number for identifying the type of FPGA in association with a driver used by the FPGA of that model number. Note that the FPGA abstraction unit 21D1 does not store only one pair of a model number for identifying the type of FPGA and a driver used by the FPGA of that model number, but stores multiple pairs. For example, the FPGA abstraction unit 21D1 stores a first model number indicating the type of FPGA in association with a first driver used by the FPGA of that first model number, and stores a second model number indicating the type of FPGA in association with a second driver used by the FPGA of that second model number.

[0087] The FPGA 22D1 is an integrated circuit whose circuit configuration can be changed by a user after manufacturing. The FPGA 22D1 executes an application 221D1. The FPGA 22D2 stores the state 222D1 of the FPGA 22D2.

[0088] The configuration of the migration destination server 20D2 is the same as the configuration of the migration source server 20D1. That is, the migration destination server 20D2 has an FPGA abstraction unit 21D2 and an FPGA 22D2 as components corresponding to the FPGA abstraction unit 21D1 and FPGA 22D1 provided in the migration source server 20D1. Therefore, in the fourth embodiment, only the configuration of the migration source server 20D1 will be described, and a description of the configuration of the migration destination server 20D2 will be omitted. The FPGA 22D2 executes an application 221D2.

[0089] 9 is a sequence diagram showing processing in the migration system 100D according to the fourth embodiment of the present invention. First, the FPGA migration control unit 11D receives a migration instruction from the administrator of the migration system 100D or the like, which is an instruction to migrate from the migration source server 20D1 to the migration destination server 20D2 (step S401).

[0090] When the FPGA migration control unit 11D receives the migration instruction, the FPGA model number information collection unit 12D sends a request to the migration source server 20D1 to transmit the model number information of the FPGA 22D1 (step S402). Next, the FPGA abstraction unit 21D1 reads model number information indicating the model number of the FPGA 22D1 from the FPGA 22D1 (step S403). Next, the FPGA abstraction unit 21D1 transmits the model number information of the FPGA 22D1 read in step S403 to the controller 10D (step S404).

[0091] Next, the FPGA model number information collection unit 12D stores the model number information of the FPGA 22D1 received in step S404 in the migration source FPGA information DB 171D as FPGA model number information 1711D (step S405). Next, the FPGA model number information collection unit 12D transmits a transmission request for the model number information of the FPGA 22D2 to the migration destination server 20D2 (step S406).

[0092] Next, the FPGA abstraction unit 21D2 reads model number information indicating the model number of the FPGA 22C2 from the FPGA 22D2 (step S407). Next, the FPGA abstraction unit 21D2 transmits the model number information of the FPGA 22D2 read in step S407 to the controller 10D (step S408). Next, the FPGA model number information collection unit 12D stores the model number information of the FPGA 22D2 received in step S408 in the migration destination FPGA information DB 173D as FPGA model number information 1731D (step S409).

[0093] Next, the FPGA information collection unit 13D transmits a request to the migration source server 20D1 to transmit application information and state information of the FPGA 22D1 (step S410). Next, the FPGA abstraction unit 21D1 selects a driver corresponding to the FPGA 22D1 from the plurality of drivers stored in the FPGA abstraction unit 21D1, and extracts application information and state information indicating the application 221D1 running on the FPGA 22D1 from the FPGA 22D1 (step S411).

[0094] Next, the FPGA abstraction unit 21D1 transmits the application information and state information of the FPGA 22D1 extracted in step S411 to the controller 10D (step S412). Next, the FPGA information collection unit 13D stores the application information and state information of the FPGA 22D1 received in step S412 in the migration source FPGA application information DB 171D as FPGA application information 1712D and FPGA state information 1713D (step S413). When the processing of step S413 is finished, the FPGA information collection unit 13D notifies the FPGA information conversion unit 14D of the completion of the processing of step S413.

[0095] 9 illustrates a case in which the process of acquiring model number information of the FPGA 22D1 of the migration source server 20D1 (steps S402 to S405) is performed, followed by the process of acquiring model number information of the FPGA 22D2 of the migration destination server 20D2 (steps S406 to S409), and then the process of acquiring application information of the FPGA 22D1 of the migration source server 20D1 (steps S410 to S413), but the present invention is not limited to this. These processes may be performed in any order, and may also be performed simultaneously.

[0096] When the FPGA information conversion unit 14D receives from the FPGA information collection unit 13D information that the processing of step S413 has been completed, it refers to the FPGA information conversion DB 172D and uses the FPGA model number information 1711D stored in the migration source FPGA information DB 171D and the FPGA model number information 1731D stored in the migration destination FPGA information DB 173D to convert the FPGA application information 1712D and FPGA status information 1713D stored in the migration source FPGA information DB 171D into application information and status information usable by the FPGA 22D2 of the migration destination server 20D2, and stores them in the migration destination FPGA information DB 173D as FPGA application information 1732D and FPGA status information 1733D (step S414). When the process of step S414 is finished, the FPGA information conversion unit 14D notifies the FPGA application write control unit 15D of the completion of the process of step S414.

[0097] When the FPGA application write control unit 15D receives a notification from the FPGA information conversion unit 14D that the processing of step S414 has been completed, the FPGA application write control unit 15D starts writing application information to the FPGA 22D2 of the migration destination server 20D2. First, the FPGA application write control unit 15D transmits the FPGA application information 1732D stored in the migration destination FPGA information DB 173D in step S414 to the migration destination server 20D2 (step S415).

[0098] Next, the FPGA abstraction unit 21D2 selects a driver corresponding to the FPGA 22D2 from the plurality of drivers stored in the FPGA abstraction unit 21D2, and writes the FPGA application information 1732D received in step S415 to the FPGA 22D2 (step S416). Upon completion of the processing of step S416, the FPGA abstraction unit 21D2 transmits a notification that the processing of step S416 has been completed to the controller 10D (step S417).

[0099] Next, the FPGA status write control unit 16D transmits the FPGA status information 1733D stored in the migration destination FPGA information DB 173D in step S414 to the migration destination server 20D2 (step S418). Next, the FPGA abstraction unit 21D2 writes the FPGA status information 1733D received in step S418 to the FPGA 22D2 (step S419).

[0100] When the processing of step S419 is completed, the FPGA abstraction unit 21D2 transmits a notification of the completion of the processing of step S419 to the controller 10D (step S420). This completes the transfer of application information and state information from the FPGA 22D1 of the migration source server 20D1 to the FPGA 22D2 of the migration destination server 20D2, and the migration processing is completed.

[0101] 9 has been described as a case in which the process of writing application information from the controller 10D to the migration destination server 20D2 (the process of steps S415 to S417 in FIG. 9) is completed, followed by the process of writing status information from the controller 10D to the migration destination server 20D2 (the process of steps S418 to S420 in FIG. 9). However, this is not limiting. For example, the process of writing status information from the controller 10D to the migration destination server 20D2 may be performed after the process of writing application information from the controller 10D to the migration destination server 20D2. Furthermore, the process of writing application information from the controller 10D to the migration destination server 20D2 and the process of writing status information from the controller 10D to the migration destination server 20D2 may be performed simultaneously.

[0102] As is clear from the above, the migration system 100D according to the fourth embodiment includes a migration source server 20D1 (also referred to as a first processing device) and a migration destination server 20D2 (also referred to as a second processing device). The migration system 100D also includes an FPGA abstraction unit 21D1 (also referred to as a migration information extraction unit) that extracts application information and state information (also referred to as first migration information) of the FPGA 22D1 by using a first driver used for the FPGA 22D1 (also referred to as a first circuit) of the migration source server 20D1 from among a plurality of drivers used for performing processing in a plurality of FPGAs 22D1 and 22D2 (also referred to as circuits). The migration system 100D also includes an FPGA information conversion unit 14D (also referred to as a conversion unit) that converts the application information and state information extracted by the FPGA abstraction unit 21D1 into application information (also referred to as second migration information) that can be processed by the FPGA 22D2 (also referred to as a second circuit).The migration system 100D also includes an FPGA abstraction unit 21D2 (also referred to as a migration information writing unit) that writes the application information and state information (also referred to as second migration information) converted by the FPGA information conversion unit 14D to the migration destination server 20D2 (also referred to as a second processing device) based on the application information and state information of the FPGA 22D1 extracted by the FPGA abstraction unit 21D1, using a second driver used for the FPGA 22D2 of the migration destination server 20D2 (also referred to as a second processing device) from among multiple drivers.

[0103] In the fourth embodiment, the application information and status information (also referred to as first migration information) extracted from FPGA 22D1 of migration source server 20D1 and the application information and status information (also referred to as second migration information) written to FPGA 22D2 of migration destination server 20D2 include application information indicating application 221D1 executed on migration source server 20D1 and status information indicating the state of application 221D1.

[0104] According to the fourth embodiment described above, migration can be performed regardless of the model number (also called type) of the FPGA (also called circuit) included in the migration source server 20D1 or the migration destination server 20D2.

[0105] Furthermore, according to the fourth embodiment described above, there is no need to implement a corresponding driver for each FPGA, and even if the migration source server 20D1 and the migration destination server 20D2 use different FPGAs, application information and status information can be collected and written, and application information and status information can be migrated even between FPGAs of different model numbers.

[0106] Furthermore, in the fourth embodiment described above, multiple drivers used in multiple model numbers of FPGAs are stored in the migration source server 20D1 and the migration destination server 20D2. Therefore, there is no need to store multiple drivers in the controller 10D.

[0107] In the first to fourth embodiments described above, a case where an application executed on a server equipped with an FPGA is migrated to continue execution on another server equipped with another FPGA is described, but the present invention is not limited to this. For example, the processing of the first to fourth embodiments described above may be performed to continue execution of an application executed on a server equipped with a CPU (Central Processing Unit) or a GPU (Graphics Processing Unit) on another server equipped with another CPU or GPU.

[0108] The controllers 10A, 10B, 10C, and 10D, the migration source servers 20A1, 20B1, 20C1, and 20D1, and the migration destination servers 20A2, 20B2, 20C2, and 20D2 according to the first to fourth embodiments each include a processor and a memory. The processor executes programs stored in the memory to perform the functions of each unit of these devices. Some or all of the functions of each unit of these devices may be realized using hardware such as an ASIC (Application Specific Integrated Circuit), a PLD (Programmable Logic Device), or an FPGA (Field Programmable Gate Array). The programs may be recorded on a computer-readable recording medium. The computer-readable recording medium is, for example, a portable medium such as a flexible disk, a magneto-optical disk, a ROM, a CD-ROM, a semiconductor storage device (for example, an SSD (Solid State Drive)), or a storage device such as a hard disk or semiconductor storage device built into a computer system. The above program may be transmitted via a telecommunications line.

[0109] The present invention is applicable to a migration system, a processing device, a migration method, and the like that require migration, regardless of the type of circuitry included in the processing device.

[0110] DESCRIPTION OF THE REFERENCE NUMERALS 10A, 10B, 10C, 10D... Controllers 11A, 11B, 11C, 11D... FPGA migration control units 12C, 12D... FPGA model number information collection units 13A, 13B, 13C, 13D... FPGA information collection units 14C, 14D... FPGA information conversion units 15A, 15B, 15C, 15D... FPGA application write control units 16B, 16D... FPGA status write control units 17A, 17B, 17C, 17D... FPGA information storage units 20A1, 20B1, 20C1, 20D1... Migration source servers 20A2, 20B2, 20C2, 20D2... Migration destination servers 21A1, 21B1, 21C1, 21D1...FPGA abstraction unit, 21A2, 21B2, 21C2, 21D2...FPGA abstraction unit, 22A1, 22B1, 22C1, 22D1...FPGA, 22A2, 22B2, 22C2, 22D2...FPGA, 100A, 100B, 100C, 100D...migration system

Claims

1. A migration system comprising a first processing device and a second processing device, comprising: a migration information extraction unit that extracts first migration information for the first circuit by using a first driver used for a first circuit of the first processing device from among a plurality of drivers used for processing by a plurality of circuits; and a migration information writing unit that writes second migration information based on the first migration information extracted by the migration information extraction unit to the second processing device by using a second driver used for a second circuit of the second processing device from among the plurality of drivers.

2. The migration system according to claim 1, further comprising a conversion unit that converts the first migration information extracted by the migration information extraction unit into second migration information that can be processed by the second circuit.

3. The migration system according to claim 1 or 2, wherein the first migration information and the second migration information include application information indicating an application executed on the first processing device.

4. The migration system according to claim 3, wherein the first migration information and the second migration information further include status information indicating a status of the application.

5. The migration system according to claim 1 or 2, wherein the first circuit and the second circuit are FPGAs (Field-Programmable Gate Arrays).

6. A processing device comprising: a migration information extraction unit that extracts first migration information for a first circuit by using a first driver used for a first circuit of the processing device from among a plurality of drivers used for processing in a plurality of circuits; and a migration information writing unit that writes second migration information for the second circuit to the processing device by using a second driver used for a second circuit of another processing device from among the plurality of drivers.

7. A migration method using a first processing device and a second processing device, comprising: extracting first migration information for the first circuit using a first driver used for a first circuit of the first processing device from among a plurality of drivers used for processing in a plurality of circuits; and writing second migration information based on the extracted first migration information to the second processing device using a second driver used for a second circuit of the second processing device from among the plurality of drivers.

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