Control device and control method

Abstract

A control device (100) according to one aspect of the present disclosure comprises a first detection unit (110) that detects input of a first signal to a first terminal, a second detection unit (120) that detects input of a second signal to a second terminal that is different from the first terminal, and a control unit (130) that cold-starts a first processor (for example, a CPU (200)) when input of the first signal to the first terminal has been detected and input of the second signal to the second terminal is detected.

Description

Control device and control method

[0001] The present disclosure relates to a control device and a control method.

[0002] Conventionally, there are systems in which a debugger debugs a processor. Patent Document 1 discloses a system in which a debugger debugs multiple cores included in a multiprocessor.

[0003] JP 2018-88048 A

[0004] In recent years, some systems have been equipped with a mechanism that can restore a processor that has been powered off (restore power) using a path other than a computer, such as a debugger that debugs the processor. Such a mechanism turns on the power of a processor that has been powered off, for example, based on an input from an external terminal other than the terminal to which the debugger is connected.

[0005] If such a mechanism is adopted, the debugger cannot detect input to the external terminal. Therefore, when the processor is shut down and recovers, it cannot be cold started. In other words, when the processor is shut down and recovers, it cannot stop the processor's processing at the beginning of the program that the processor is executing when it is shut down and recovers. As a result, the debugger can only debug the processor after all the processing for the processor's shutdown and recovery has been completed, that is, after the processor has been started.

[0006] The present disclosure provides a control device and the like that can facilitate debugging of a processor.

[0007] A control device according to one aspect of the present disclosure includes a first detection unit that detects input of a first signal to a first terminal, a second detection unit that detects input of a second signal to a second terminal different from the first terminal, and a control unit that cold-starts a first processor if input of the second signal to the second terminal is detected when input of the first signal to the first terminal is detected.

[0008] A control method according to one aspect of the present disclosure detects input of a first signal to a first terminal, detects input of a second signal to a second terminal different from the first terminal, and cold-starts a first processor if input of the second signal to the second terminal is detected when input of the first signal to the first terminal is detected.

[0009] According to a control device according to one aspect of the present disclosure, it is possible to easily debug a processor.

[0010] FIG. 1 is a block diagram showing the configuration of a debugging system according to a first embodiment. FIG. 2 is a diagram showing a specific example of the configuration of an SoC according to the first embodiment. FIG. 3 is a flowchart showing the procedure for CPU recovery processing executed by the control device according to the first embodiment. FIG. 4 is a block diagram showing the configuration of a debugging system according to a second embodiment. FIG. 5 is a diagram showing a specific example of the configuration of an MCM according to the second embodiment. FIG. 6 is a diagram showing a specific example of a path through which a recovery signal according to the second embodiment flows. FIG. 7 is a diagram showing a specific example of a path through which an SWCLK according to the second embodiment flows. FIG. 8 is a flowchart showing the procedure for CPU recovery processing executed by the control device according to the second embodiment. FIG. 9 is a flowchart showing the procedure for CPU recovery processing executed by the control device according to the second embodiment. FIG. 10 is a flowchart showing a control method according to an embodiment.

[0011] (Background to the Disclosure) In recent years, the development of wearable devices has led to an increasing demand for smaller and thinner devices. In addition, systems tend to become more complex, and the number of LSIs (Large Scale Integrations) equipped with multiple processors such as CPUs (Central Processing Units) mounted on devices has been increasing in recent years.

[0012] Such processors have an interface (access port) for debugging. One example of such an interface (also called a debug interface) is JTAG (Joint Test Action Group). Another example of a debug interface is SWD (Serial Wire Debug).

[0013] SWD is an interface that uses a serial communication method and has fewer terminals than JTAG, while still providing the same debugging functionality as JTAG. Because SWD has fewer terminals than JTAG, it can be expected to require fewer pins (i.e., be more compact) than LSIs that use JTAG.

[0014] A multi-drop connection (multi-drop connection method) for connecting to multiple processors is defined as a connection method for SWD. This makes it possible to debug multiple processors in an LSI without increasing the number of terminals on the LSI. When multiple processors are implemented on a single piece of silicon, the debugger is connected to the multiple processors in the same way as with the multi-drop connection method. The input / output signal (SWDIO) used by the debugger for debugging is input and output in both directions between the debugger and the processors, so the connection to each processor can be switched by a selector.

[0015] The multi-drop connection in the SWD makes it easy to design and verify the processor, and also provides a high degree of freedom in terms of memory map configuration and debug connection control for each core.

[0016] However, when this connection method is adopted, for example, if the power supply to one of the multiple processors is cut off and then restored, the information necessary for debugging is deleted from the holding circuit (e.g., a circuit for storing information such as registers and / or memory) provided in the processor, making it difficult for the debugger to perform debugging from the beginning of the program executed by the processor.

[0017] Therefore, the inventors of the present invention have come up with the present invention.

[0018] Specifically, when a control device according to one aspect of the present disclosure receives an input from an external terminal to restore a processor from a power-off state, if the control device detects that the processor is connected to a debugger (i.e., the input from the debugger), it cold-starts the processor to stop processing. When multiple processors are integrated into a single silicon chip using a multi-drop connection method, it is not possible to stop processor processing upon power-off restoration. Therefore, by using information on whether an external debugger is connected or not, it is possible to switch between free-running and stopping processing at the beginning of the program by controlling the debugger connection to the processor that is powering down.

[0019] Each embodiment will be specifically described below with reference to the drawings.

[0020] It should be noted that each of the embodiments described below is a comprehensive or specific example. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims of the present disclosure are described as optional components.

[0021] Furthermore, unless otherwise specified, ordinal numbers such as "first" and "second" do not refer to the number or order of components, but are used to avoid confusion and distinguish between components of the same type.

[0022] Furthermore, in this specification, when a comparison is made, for example, with "above a threshold" or "below a threshold," it means that the distinction is made at the threshold, and may mean "greater than the threshold" or "below the threshold," respectively.

[0023] (First Embodiment) [Configuration] Fig. 1 is a block diagram showing the configuration of a debug system 1 according to the first embodiment. Fig. 2 is a diagram showing a specific example of the configuration of an SoC 400 according to the first embodiment. Note that Fig. 2 does not show the CPU 200 included in the semiconductor device 10. The determination circuit 420 is connected to the CPU 200 via a bus or the like, for example.

[0024] The debug system 1 is a system for debugging one or more processors (specifically, programs executed by a plurality of processor cores).

[0025] The debugging system 1 includes a semiconductor device 10 and a host 300 .

[0026] The semiconductor device 10 is a device that includes a target that is to be debugged by the host 300. The semiconductor device 10 is realized by an LSI. The target is, for example, a processor. In this embodiment, the semiconductor device 10 is realized by an SoC 400, and the target is realized by a CPU 200. That is, in this embodiment, the CPU 200 is debugged by the host 300.

[0027] The number of targets included in the semiconductor device 10 and the number of targets debugged by the host 300 may each be one or more.

[0028] The host 300 is a computer that executes debugging. The host 300 is realized by, for example, a personal computer that includes a non-volatile memory that stores a program, a volatile memory that is a temporary storage area for executing the program, a processor that executes the program, etc. The host 300 also includes a debug interface for executing debugging of the CPU 200 included in the semiconductor device 10.

[0029] The host 300 includes a debug interface having, for example, a port for communicating a clock signal (also simply referred to as CLK) for synchronization with the CPU 200 and a port for communicating data (also referred to as DIO) for executing debugging. The debug interface included in the host 300 is serially connected to, for example, a port included in the semiconductor device 10. This allows serial communication between the host 300 and the semiconductor device 10.

[0030] The host 300 is an example of a debugger.

[0031] The clock signal used during debugging by the host 300 is also referred to as SWCLK. That is, SWCLK is a clock signal used, for example, when the host 300 debugs the CPU 200. Data input / output during debugging by the host 300 is also referred to as SWDIO.

[0032] Furthermore, the clock generator may be realized by any component.

[0033] The semiconductor device 10 is a device including one or more processors to be debugged by the host 300. The semiconductor device 10 is realized on one chip (i.e., one semiconductor substrate) such as an SoC (System on Chip). The semiconductor device 10 includes a control device 100 and a CPU 200. The control device 100 and the CPU 200 are provided on one chip, for example.

[0034] The CPU 200 is a processor (specifically, a processor core of a CPU (Central Processing Unit)) that is the target of debugging executed by the host 300. The CPU 200 is an example of a first processor. The CPU 200 includes a debug interface that enables the host 300 to debug the CPU 200.

[0035] The CPU 200 is provided with a debug interface having, for example, a port for communicating a clock signal for synchronization with the host 300, a port for inputting data from the host 300, a port for outputting data to the host 300, and a debug access port including a port for outputting an enable signal. The data and enable signal output from the CPU 200 are output to the host 300.

[0036] The data output by the host 300 is input to the CPU 200. For example, the data output by the host 300 includes a target ID (Identifier) ​​that indicates the CPU 200. The CPU 200 stores in advance a target ID that indicates its own target, and based on the acquired target ID, if the target indicated by the target ID is its own target, it outputs data and an enable signal corresponding to the acquired data to the host 300, but if the target indicated by the target ID is not its own target, it does not output the data and enable signal to the host 300.

[0037] By performing such processing, when the host 300 debugs the CPU 200, for example, it establishes one-to-one communication with one target by outputting data including the target ID of the target to be debugged, and performs the debugging.

[0038] The semiconductor device 10 also includes, for example, a port unit that is serially connected to the host 300. The port unit includes, for example, two ports: a port for communicating a clock signal and a port for communicating data. The data and enable signal output from the CPU 200 are each output to the host 300 from, for example, the port of the port unit through which the data is communicated. Specifically, only when the host 300 is not using the data line, a switch that prevents input and output in the host 300 from colliding is switched using the enable signal, and the data is output to the host 300 from the port through which the data is communicated.

[0039] The control device 100 is an electronic circuit connected to the host 300 and the CPU 200. Specifically, the control device 100 is connected to the CPU 200 via a bus and communicates with the CPU 200 via the bus. The control device 100 includes a first detection unit 110, a second detection unit 120, and a control unit 130.

[0040] The first detection unit 110 is a circuit that detects an input of a signal (also referred to as an external signal) to the external terminal 500. The external terminal 500 is an example of a first terminal. The external signal is an example of a first signal. The first detection unit 110 performs a detection process to detect an input of an external signal to the external terminal 500, for example, by detecting an edge of the external terminal 500.

[0041] The second detection unit 120 is a circuit that detects a signal input to a terminal 510 that is connected to the host 300. The terminal 510 is an example of a second terminal. The signal is an example of a second signal. The second detection unit 120 performs a detection process that detects the input of SWCLK to the terminal 510, for example, by controlling the I / O cell 410. The second detection unit 120 detects the input of SWCLK to the terminal 510 by repeatedly switching the state of the terminal 510 between a pull-up state and a pull-down state, for example, by controlling the I / O cell 410.

[0042] The external terminal 500 and the terminal 510 are realized by different terminals. Specifically, the external terminal 500 and the terminal 510 are connected to different devices. For example, an electronic device such as a computer that can be operated by a user is connected to the external terminal 500, and the host 300 is connected to the terminal 510.

[0043] The control unit 130 is a circuit that controls the power supply of the CPU 200. For example, when the power supply of the CPU 200 is cut off, the control unit 130 restores the power supply of the CPU 200 upon receiving a signal via the external terminal 500. Here, when an external signal input to the external terminal 500 is detected, the control unit 130 determines whether an SWCLK input to the terminal 510 is detected. When an external signal input to the external terminal 500 is detected, the control unit 130 cold-starts the CPU 200 if an SWCLK input to the terminal 510 is detected.

[0044] A cold start is a process of stopping the processing of the CPU 200 at the beginning of a program of a recovery process executed when the CPU 200 recovers from a state in which power has been cut off. In other words, when the CPU 200 is cold started, the CPU 200 stops the processing at the beginning of the program of the recovery process.

[0045] On the other hand, when an input of an external signal to external terminal 500 is detected but an input of SWCLK to terminal 510 is not detected, control unit 130 does not cold start CPU 200. In this case, for example, control unit 130 allows CPU 200 to execute the entire program of a recovery process that CPU 200 executes when recovering from a power-off state, without stopping the processing of CPU 200 at the beginning of the program.

[0046] The first detection unit 110, the second detection unit 120, and the control unit 130 are realized, for example, by electronic circuits. The first detection unit 110, the second detection unit 120, and the control unit 130 may be realized by a single electronic circuit or by multiple electronic circuits. In this embodiment, the first detection unit 110, the second detection unit 120, and the control unit 130 are realized by an I / O cell 410 and a determination circuit 420.

[0047] The SoC 400 includes an I / O cell 410 , a determination circuit 420 , an external terminal 500 , and a terminal 510 .

[0048] The I / O cell 410 is a circuit for detecting the connection state with the host 300. Specifically, the I / O cell 410 is used to detect the input of SWCLK from the host 300. In other words, the I / O cell 410 is used by the determination circuit 420 to determine whether or not the terminal 510 is being driven.

[0049] Determination circuit 420 is a circuit that detects signal input to external terminal 500 and terminal 510 and restores (restores) power from shutdown to CPU 200. Specifically, determination circuit 420 is an SWCLK drive determination circuit that determines whether or not SWCLK is input to terminal 510. Specifically, determination circuit 420 starts up CPU 200 by supplying (specifically, resuming) power (specifically, electricity) to CPU 200 in a power-off state (specifically, power supply).

[0050] The determination circuit 420 detects an external signal input to the external terminal 500, for example, by detecting an edge of the external terminal 500. The determination circuit 420 also detects an SWCLK input to the terminal 510, for example, by controlling the I / O cell 410. For example, when the CPU 200 recovers from a power cutoff, the determination circuit 420 determines whether the terminal 510 is driven by toggling the pull-up state and pull-down state of the terminal 510 and monitoring the data input to the terminal 510. For example, if the terminal 510 is driven, the determination circuit 420 cold-starts the CPU 200.

[0051] The signal detected by the determination circuit 420 (second detection unit 120) to determine whether or not to cold start the CPU 200 does not have to be SWCLK, and may be determined arbitrarily.

[0052] The external terminal 500 is a terminal for receiving input of an external signal. For example, an electronic device such as a computer that can be operated at will by a user is connected to the external terminal 500. A power supply device such as a battery that can start or stop the supply of power to the CPU 200 (i.e., turn the power on and off) at will by a user may be connected to the external terminal 500.

[0053] The terminal 510 is a terminal for receiving the SWCLK, and is connected to the host 300, for example.

[0054] 3 is a flowchart showing the procedure of the recovery process of the CPU 200 executed by the control device 100 according to embodiment 1. The process shown in FIG. 3 is performed from a state in which the power supply to the CPU 200 is cut off.

[0055] First, the first detector 110 determines whether or not an input of an external signal to the external terminal 500 has been detected (S110).

[0056] When the first detection unit 110 determines that an external signal input to the external terminal 500 has not been detected (No in S110), the first detection unit 110 repeats the process of step S110.

[0057] On the other hand, if the first detection unit 110 determines that an external signal has been input to the external terminal 500 (Yes in S110), the second detection unit 120 determines whether or not an SWCLK input to the terminal 510 has been detected (S120).

[0058] If the second detection unit 120 determines that an input of SWCLK to the terminal 510 has been detected (Yes in S120), the control unit 130 cold-starts the CPU 200 (S130). That is, the control unit 130 starts up the CPU 200 and causes the CPU 200 to stop the recovery process at the beginning of the recovery process program. Thereafter, the host 300 starts debugging the CPU 200.

[0059] On the other hand, if the second detection unit 120 determines that it has not detected the input of SWCLK to terminal 510 (No in S120), the control unit 130 does not cold start the CPU 200, but instead causes the CPU 200 to execute all of the recovery processing programs (S140).

[0060] [Effects, etc.] As described above, the control device 100 according to the first embodiment includes a first detection unit 110 that detects an input of an external signal to the external terminal 500, a second detection unit 120 that detects an input of SWCLK to a terminal 510 different from the external terminal 500, and a control unit 130 that cold-starts the CPU 200 if an input of SWCLK to the terminal 510 is detected when an input of an external signal to the external terminal 500 is detected.

[0061] According to this, when an external signal for powering down the CPU 200 is detected via the external terminal 500, the control device 100 can determine whether to cold start the CPU 200 based on the SWCLK input from the terminal 510 to which the host 300 is connected. Therefore, the control device 100 can cold start the CPU 200 even when a signal other than a signal from the host 300 is used to perform the CPU recovery process. Therefore, the control device 100 can make it easier to debug the CPU 200.

[0062] Conventionally, there have been SoCs that allow the CPU to be powered off. Conventionally, when the CPU is powered on, the SWCLK can be toggled to cold start the CPU. Conventionally, there has also been a mechanism that allows the CPU to resume from a powered-off state by detecting an edge on an external terminal. Conventionally, when the external terminal is used to restore the CPU power, the timing of the toggle output is unknown in the debugger. Therefore, when the CPU resumes power from a powered-off state, the CPU cannot be cold started, and the only option is to attach the debugger after the CPU has started.

[0063] However, according to the control device 100, even if the SWD pin is used for the debug interface of the CPU 200 and the external terminal 500 is used when the CPU 200 is restored from a power-off state, the processing of the CPU 200 can be stopped when the CPU 200 is restored from a power-off state.

[0064] Furthermore, for example, the second detection unit 120 detects input of SWCLK to the terminal 510 by repeatedly switching the state of the terminal 510 between a pull-up state and a pull-down state.

[0065] This allows the input of SWCLK to the terminal 510 to be detected.

[0066] Furthermore, for example, the signal detected by the second detection unit 120 to determine whether or not to cold start the CPU 200 is a clock signal (i.e., SWCLK) used when the host 300 debugs the CPU 200 .

[0067] This allows the host 300 to cold start the CPU 200 using SWCLK even when a signal other than a signal from the host 300 is used to perform the recovery process for the CPU 200 .

[0068] (Embodiment 2) Next, a description will be given of a debug system according to embodiment 2. In the following description of embodiment 2, differences from embodiment 1 will be mainly described, and some or all of the description that overlaps with the description of embodiment 1 may be omitted or simplified.

[0069] [Configuration] Fig. 4 is a block diagram showing the configuration of a debug system 1A according to the second embodiment. Fig. 5 is a diagram showing a specific example of the configuration of an MCM 600 according to the second embodiment. Note that in Fig. 5, the CPUs 200, 210, and 220 included in the semiconductor device 11 are not shown. The determination circuit 420 included in the SoC 401 is connected to the CPU 200 via a bus or the like, for example. The determination circuit 421 included in the SoC 402 is connected to the CPU 210 via a bus or the like, for example. The determination circuit 421 included in the SoC 403 is connected to the CPU 220 via a bus or the like, for example.

[0070] The debug system 1A is a system for debugging a plurality of processors (specifically, programs executed by a plurality of processor cores).

[0071] The debugging system 1 A includes a semiconductor device 11 and a host 300 .

[0072] The semiconductor device 11 is a device including multiple targets to be debugged by the host 300. The semiconductor device 11 is realized by multiple LSIs. In this embodiment, the semiconductor device 11 is realized by an MCM 600. The MCM 600 is an MCM (Multi Chip Module) including CPUs 200, 210, and 220. In this embodiment, the multiple targets are realized by the CPUs 200, 210, and 220. That is, in this embodiment, the CPUs 200, 210, and 220 are debugged by the host 300. In addition, the control device 101 is realized by an SoC 401, the control device 102 is realized by an SoC 402, and the control device 103 is realized by an SoC 403. For example, the SoC 401 includes an external terminal 500, but the SoCs 402 and 403 do not include terminals for receiving external signals from external devices.

[0073] The semiconductor device 11 is a device including multiple processors that are the targets of debugging executed by the host 300. The semiconductor device 11 includes control devices 101, 102, and 103 and CPUs 200, 210, and 220. The control devices 101, 102, and 103 and the CPUs 200, 210, and 220 are provided, for example, on one chip (on one semiconductor substrate). The CPUs 210 and 220 are each an example of a second processor. The CPUs 210 and 220 have the same structure as the CPU 200, for example.

[0074] The control device 101 is an electronic circuit connected to the host 300 and the CPU 200. Specifically, the control device 101 is connected to the CPU 200 via a bus and communicates with the CPU 200 via the bus. The control device 101 includes a first detection unit 110, a second detection unit 120, a control unit 130, and an output unit 140.

[0075] The first detection unit 110 is a circuit that detects an external signal input to the external terminal 500 .

[0076] The second detection unit 120 is a circuit that detects a signal input to a terminal 510 that is connected to the host 300. The second detection unit 120 detects the input of SWCLK to the terminal 510 by, for example, controlling the I / O cell 410 to repeatedly switch the state of the terminal 510 between a pull-up state and a pull-down state.

[0077] The control unit 130 is a circuit that controls the power supply of the CPU 200. For example, when an input of an external signal to the external terminal 500 is detected and an input of SWCLK to the terminal 510 is detected, the control unit 130 cold-starts the CPU 200.

[0078] The output unit 140 is a circuit that outputs a signal (also referred to as a return signal) to the control device 102. The return signal is an example of a third signal. For example, when the CPUs 210 and 220 are to be cold started, the output unit 140 outputs a return signal that satisfies a predetermined condition, and when the CPUs 210 and 220 are not to be cold started, the output unit 140 outputs a return signal that does not satisfy the predetermined condition.

[0079] CPU 200, CPU 210, and CPU 220 are different CPUs. Specifically, the recovery process of CPU 200 is controlled by control device 101, the recovery process of CPU 210 is controlled by control device 102, and the recovery process of CPU 220 is controlled by control device 103.

[0080] For example, when cold starting CPU 210, output unit 140 outputs a return signal that satisfies the first condition. For example, when cold starting CPU 220, output unit 140 outputs a return signal that satisfies the second condition. For example, when cold starting both CPUs 210 and 220, output unit 140 outputs a return signal that satisfies both the first and second conditions. For example, when cold starting CPU 210 but not cold starting CPU 220, output unit 140 outputs a return signal that satisfies the first condition but not the second condition. For example, when not cold starting CPU 210 but cold starting CPU 220, output unit 140 outputs a return signal that does not satisfy the first condition but satisfies the second condition. Furthermore, for example, if neither the CPU 210 nor the CPU 220 is cold-started, the output section 140 outputs a recovery signal that does not satisfy either the first condition or the second condition.

[0081] The predetermined conditions (e.g., the first and second conditions described above) may be determined arbitrarily and are not particularly limited. The predetermined conditions are determined, for example, by the period during which the signal level (e.g., voltage) of the recovery signal is high and the period during which the signal level is low. That is, the predetermined conditions are determined, for example, by the duty ratio of the recovery signal. For example, a recovery signal having a first period during which the signal level is high and a second period during which the signal level is low is determined to satisfy the predetermined conditions. The first period and the second period may be determined arbitrarily and are not particularly limited. The first condition and the second condition may be different or the same.

[0082] Alternatively, if the duty ratio of the recovery signal is less than a first threshold, it may be determined that the first condition and the second condition are not satisfied, if the duty ratio is equal to or greater than the first threshold and less than a second threshold, it may be determined that the first condition is satisfied but the second condition is not satisfied, if the duty ratio is equal to or greater than the second threshold and less than a third threshold, it may be determined that the first condition is not satisfied but the second condition is satisfied, and if the duty ratio is equal to or greater than the third threshold, it may be determined that both the first condition and the second condition are satisfied. Each threshold may be set arbitrarily and is not particularly limited.

[0083] The output unit 140 generates the recovery signal by, for example, adjusting the signal level of SWCLK. For example, SWCLK and the recovery signal differ in at least one of the period during which the signal level is high and the period during which the signal level is low. The output unit 140 may include a clock generator for generating the recovery signal.

[0084] When the output unit 140 outputs the recovery signal, for example, the CPU 210 is cold started by the control unit 102, and the CPU 220 is cold started by the control unit 103. In other words, the output unit 140 outputs the recovery signal and then outputs SWCLK, and thereafter the output unit 140 outputs SWCLK to the control units 102 and 103. As a result, the CPU 210 and the CPU 220 are debugged by the host 300.

[0085] Information indicating whether to cold start the CPUs 210 and 220 is stored in advance in a holding circuit, such as a memory and / or register, included in the control device 101. The holding circuit is implemented, for example, by a latch circuit, but may be implemented with any other configuration, such as a flip-flop circuit. The holding circuit may also be communicatively connected to the host 300. Specifically, the holding circuit may be configured so that the host 300 can access the information. For example, the host 300 communicates with the holding circuit via a bus used by components such as the processor included in the SoC 401 to access the holding circuit. The information stored in the holding circuit may be located in an address space or memory space accessible by the host 300. Note that the information may be located in an address space or memory space accessible only by the host 300, or in an address space or memory space accessible by devices other than the host 300.

[0086] In this embodiment, the return signal is output from the control device 101 to the control device 102. Also, in this embodiment, the return signal is output from the control device 102 to the control device 103.

[0087] The first detection unit 110, the second detection unit 120, the control unit 130, and the output unit 140 are realized, for example, by electronic circuits. The first detection unit 110, the second detection unit 120, the control unit 130, and the output unit 140 may be realized by a single electronic circuit or by multiple electronic circuits. In this embodiment, the first detection unit 110, the second detection unit 120, the control unit 130, and the output unit 140 are realized by an I / O cell 410, a determination circuit 420, an adjustment circuit 430, and a selector 440.

[0088] The SoC 401 includes an I / O cell 410 , a determination circuit 420 , an adjustment circuit 430 , a selector 440 , an external terminal 500 , a terminal 510 , and a terminal 520 .

[0089] The I / O cell 410 is a circuit for detecting the connection state with the host 300 .

[0090] The determination circuit 420 is a circuit that detects the input of signals to the external terminals 500 and 510 and that turns off and returns the CPU 200 .

[0091] The adjustment circuit 430 is a circuit that generates a return signal.

[0092] The selector 440 is a selection circuit for outputting one of the SWCLK and the recovery signal from the terminal 520 to the SoC 402 (specifically, the terminal 530). For example, the selector 440 outputs the recovery signal input from the adjustment circuit 430 from the terminal 520, and then outputs the SWCLK input from the terminal 510 from the terminal 520.

[0093] The external terminal 500 is a terminal for receiving an input of an external signal.

[0094] A terminal 510 is a terminal for receiving SWCLK.

[0095] The terminal 520 is a terminal for outputting the SWCLK and the recovery signal to the SoC 402. The terminal 520 is connected to a terminal 530.

[0096] The control device 102 is an electronic circuit connected to the control device 101 and the CPU 210. Specifically, the control device 102 is connected to the CPU 210 via a bus and communicates with the CPU 210 via the bus. The control device 102 includes a third detection unit 150, a comparison unit 160, and a control unit 170.

[0097] The third detection unit 150 is a circuit that detects the input of a recovery signal to the terminal 520. The third detection unit 150 detects the input of a recovery signal to the terminal 510 by, for example, controlling an I / O cell connected to the terminal 520 to repeatedly switch the state of the terminal 520 between a pull-up state and a pull-down state.

[0098] The comparison unit 160 is a circuit for determining whether or not the recovery signal detected by the third detection unit 150 satisfies a predetermined condition. The comparison unit 160 determines, for example, whether or not the waveform of the recovery signal (specifically, the period when the signal level of the recovery signal is high and the period when the signal level is low) satisfies a first condition.

[0099] The information indicating the first condition is stored in advance in a holding circuit, such as a memory and / or register, included in the control device 102. The holding circuit is implemented, for example, by a latch circuit, but may be implemented with any other configuration, such as a flip-flop circuit. The holding circuit may also be communicatively connected to the host 300. Specifically, the holding circuit may be configured so that the host 300 can access the information. For example, the host 300 communicates with the holding circuit via a bus used by components such as the processor included in the SoC 402 to access the holding circuit. The information stored in the holding circuit may be located in an address space or memory space accessible by the host 300. Note that the information may be located in an address space or memory space accessible only by the host 300, or in an address space or memory space accessible by devices other than the host 300.

[0100] The control unit 170 is a circuit that controls the power supply of the CPU 210. For example, when the comparison unit 160 determines that the recovery signal satisfies a predetermined condition (specifically, a first condition), the control unit 170 cold-starts the CPU 210. On the other hand, for example, when the comparison unit 160 determines that the recovery signal does not satisfy the predetermined condition (specifically, the first condition), the control unit 170 does not cold-start the CPU 210 and instead causes the CPU 210 to execute all of the recovery processing program.

[0101] The third detection unit 150, the comparison unit 160, and the control unit 170 are realized, for example, by electronic circuits. The third detection unit 150, the comparison unit 160, and the control unit 170 may be realized by a single electronic circuit or by multiple electronic circuits. In this embodiment, the third detection unit 150, the comparison unit 160, and the control unit 170 are realized by a determination circuit 421 and a comparison circuit 450.

[0102] The SoC 402 includes a determination circuit 421 , a comparison circuit 450 , a terminal 530 , and a terminal 540 .

[0103] The determination circuit 421 is a circuit for turning off and returning the CPU 210 .

[0104] The comparison circuit 450 is a circuit for determining whether or not the recovery signal satisfies a predetermined condition (first condition).

[0105] The terminal 530 is a terminal for receiving the recovery signal and SWCLK.

[0106] The terminal 540 is a terminal for outputting the SWCLK and the recovery signal to the SoC 403. The terminal 540 is connected to the terminal 550.

[0107] The control device 103 is an electronic circuit connected to the control device 102 and the CPU 220. Specifically, the control device 103 is connected to the CPU 220 via a bus and communicates with the CPU 220 via the bus. The control device 103 has the same configuration as the control device 102. Specifically, the control device 103 includes a third detection unit 150, a comparison unit 160, and a control unit 170.

[0108] The third detection unit 150 included in the control device 103 is a circuit that detects the input of a recovery signal to the terminal 550. The comparison unit 160 included in the control device 103 is a circuit that determines whether the recovery signal satisfies a predetermined condition (a second condition). Information indicating the second condition is stored in advance in a holding circuit, such as a memory and / or a register, included in the control device 103. The control unit 170 included in the control device 103 is a circuit that controls the power supply of the CPU 220. If it determines that the recovery signal satisfies the predetermined condition (specifically, the second condition), it cold-starts the CPU 220. If it determines that the recovery signal does not satisfy the predetermined condition (specifically, the second condition), it does not cold-start the CPU 220 and instead causes the CPU 220 to execute all of the recovery processing program.

[0109] The SoC 403 has the same configuration as the SoC 402. Specifically, the SoC 403 includes a determination circuit 421, a comparison circuit 450, a terminal 550, and a terminal 560.

[0110] The determination circuit 421 included in the SoC 403 is a circuit for shutting down and restoring the CPU 220. The comparison circuit 450 included in the SoC 403 is a circuit for determining whether the restoration signal satisfies a predetermined condition (second condition).

[0111] The terminal 550 is a terminal for receiving the recovery signal and SWCLK.

[0112] Terminal 560 is a terminal for outputting SWCLK and a recovery signal to a device such as an SoC (not shown) located downstream of SoC 403 .

[0113] In addition, if the control device 101 is configured to be able to directly output a recovery signal to both the control device 102 and the control device 103, the output unit 140 may generate and output a recovery signal corresponding to each of the control device 102 and the control device 103 individually.

[0114] Furthermore, the number of control devices 101, 102, and 103 included in the semiconductor device 11 is three in this embodiment, but may be two, four or more, or may be arbitrarily determined, and is not particularly limited.

[0115] [Specific Example] Fig. 6 is a diagram showing a specific example of a path through which a return signal flows according to embodiment 2. Note that in Fig. 6, the path through which the return signal flows is indicated by a dashed line. Also, in Fig. 6, CPUs 200, 210, and 220 are not shown.

[0116] For example, when the determination circuit 420 receives an external signal via the external terminal 500, it determines whether or not SWCLK is being input to the terminal 510. If the determination circuit 420 determines that SWCLK is being input to the terminal 510, it cold starts the CPU 200. Furthermore, if the determination circuit 420 determines that SWCLK is being input to the terminal 510, the adjustment circuit 430 generates a recovery signal and outputs it to the selector 440. The selector 440 sets a signal flow path so that the recovery signal is output from the terminal 520. As a result, the recovery signal is output from the terminal 520 to the terminal 530.

[0117] The recovery signal output to the terminal 530 is output from the terminal 540 to the terminal 550. The recovery signal output to the terminal 550 is further output from the terminal 560, for example.

[0118] The comparator circuit 450 of the SoC 402 determines, for example, whether a signal (in this example, a recovery signal) is input to the terminal 530. If the comparator circuit 450 of the SoC 402 determines that a signal is input to the terminal 530, it determines whether the input signal satisfies a predetermined condition (specifically, a first condition). If the comparator circuit 450 of the SoC 402 determines that the predetermined condition (specifically, the first condition) is satisfied, the determination circuit 421 of the SoC 402 cold-starts the CPU 210.

[0119] The SoC 403 performs the same processing as the SoC 402. The comparator circuit 450 of the SoC 403 determines, for example, whether a signal (in this example, a recovery signal) is input to the terminal 550. If the comparator circuit 450 of the SoC 403 determines that a signal is input to the terminal 550, it determines whether the input signal satisfies a predetermined condition (specifically, a second condition). If the comparator circuit 450 of the SoC 403 determines that the predetermined condition (specifically, the second condition) is satisfied, the determination circuit 421 of the SoC 403 cold-starts the CPU 220.

[0120] 7 is a diagram showing a specific example of a path through which the SWCLK flows according to the second embodiment. Note that in FIG. 7, the path through which the recovery signal flows is indicated by a dashed line. Also, in FIG. 7, the CPUs 200, 210, and 220 are not shown.

[0121] 6 , after a predetermined time has elapsed, the selector 440 switches the signal flow path so that, of the SWCLK and the recovery signal, only SWCLK is output from the terminal 520. As a result, the SWCLK output from the host 300 to the terminal 510 is output from the terminal 520 to the terminal 530. The SWCLK output to the terminal 530 is output from the terminal 540 to the terminal 550. The SWCLK output to the terminal 550 is further output from the terminal 560, for example.

[0122] The predetermined time may be arbitrarily determined in advance and is not particularly limited.

[0123] 8 is a flowchart showing the procedure of the recovery process of the CPU 200 executed by the control device 101 according to embodiment 2. The process shown in FIG. 8 is performed from a state in which the power supply to the CPU 200 is cut off.

[0124] First, the first detector 110 determines whether or not an input of an external signal to the external terminal 500 has been detected (S110).

[0125] When the first detection unit 110 determines that an external signal input to the external terminal 500 has not been detected (No in S110), the first detection unit 110 repeats the process of step S110.

[0126] On the other hand, if the first detection unit 110 determines that an external signal has been input to the external terminal 500 (Yes in S110), the second detection unit 120 determines whether or not an SWCLK input to the terminal 510 has been detected (S120).

[0127] If the second detection unit 120 determines that an input of SWCLK to the terminal 510 has been detected (Yes in S120), the control unit 130 cold-starts the CPU 200 (S130).

[0128] Next, the output unit 140 generates a return signal indicating whether or not to cold start each of the CPUs 210 and 220 (S150).

[0129] Next, the output unit 140 outputs the generated return signal to the control device 102 (S160).

[0130] Next, after a predetermined time has elapsed since the output unit 140 output the generated recovery signal to the control device 102, the output unit 140 outputs the SWCLK input from the host 300 to the control device 102 (S170).

[0131] Furthermore, if the second detection unit 120 determines that it has not detected the input of SWCLK to terminal 510 (No in S120), the control unit 130 does not cold start the CPU 200, but instead causes the CPU 200 to execute all of the recovery processing programs (S140).

[0132] Fig. 9 is a flowchart showing the procedure of the recovery process of the CPUs 210 and 220 executed by the control devices 102 and 103 according to embodiment 2. Note that the recovery process of the CPU 210 executed by the control device 102 and the recovery process of the CPU 220 executed by the control device 103 are substantially the same, and therefore Fig. 9 will explain the process of the control device 102 as an example. The process shown in Fig. 9 is performed from a state in which the power supply to the CPU 210 has been cut off.

[0133] First, the third detection unit 150 determines whether or not a return signal has been input to the terminal 530 (S210).

[0134] When the third detection unit 150 determines that the input of the recovery signal to the terminal 530 has not been detected (No in S210), the third detection unit 150 repeats the process of step S210.

[0135] On the other hand, if the third detection unit 150 determines that an external signal has been input to the terminal 530 (Yes in S110), the comparison unit 160 determines whether the period of the return signal corresponds to the information stored in the holding circuit, that is, whether the period satisfies a predetermined condition (specifically, the first condition) (S220).

[0136] If the comparison unit 160 determines that the cycle of the recovery signal is the corresponding cycle (Yes in S220), the control unit 170 cold-starts the CPU 210 (S230).

[0137] On the other hand, if the comparison unit 160 determines that the period of the recovery signal is not a corresponding period (No in S220), the control unit 170 does not cold start the CPU 210, but instead causes the CPU 210 to execute all of the recovery processing program (S240).

[0138] [Effects, etc.] As described above, control device 101 according to the second embodiment includes first detection unit 110 that detects an external signal input to external terminal 500, second detection unit 120 that detects an SWCLK input to terminal 510 different from external terminal 500, and control unit 130 that cold-starts CPU 200 if an SWCLK input to terminal 510 is detected when an external signal input to external terminal 500 is detected. Control device 101 also includes output unit 140 that outputs a recovery signal, and output unit 140 outputs a signal that satisfies a predetermined condition as the recovery signal when CPUs 210 and 220 different from CPU 200 are to be cold-started, and outputs a signal that does not satisfy the predetermined condition as the recovery signal when CPUs 210 and 220 are not to be cold-started.

[0139] In the case of debugging a multi-CPU system, various SWD connection methods are possible, such as a multi-drop type, etc. However, the SWCLK is always a unidirectional drive.

[0140] In this embodiment, the MCM 600 includes control devices 101, 102, and 103 that are daisy-chained.

[0141] A mechanism for detecting a cause of recovery is provided as an operation for recovering from power interruption of the CPUs 200, 210, and 220. In this embodiment, the control device 101 detects a cause of recovery from power interruption (external signal) using the external terminal 500.

[0142] The information indicating which of CPUs 200, 210, and 220 will be cold-started may be stored in control device 101 before the power to CPUs 200, 210, and 220 is cut off, or may be set in control device 101 from host 300.

[0143] When the control device 101 detects a power-off / recovery factor, it restores power to the control devices 102 and 103. Thereafter, the control device 101 does not output SWCLK from the host 300 to the control devices 102 and 103, but instead varies the high period (high section) and low period (low section) of the SWCLK signal level according to a predetermined rule. This allows the control device 101 to switch which CPU in the downstream CPU group, such as the CPUs 210 and 220, is to be cold-started. In the SW debugger protocol, toggling SWCLK is meaningless if SWDIO is in a low state. Therefore, in this embodiment, the specification is such that the low period of SWDIO has meaning. Specifically, which CPU in the downstream CPU group is to be cold-started is switched depending on the length of the low period.

[0144] After the CPUs 200, 210, and 220 are started, the SWCLK is returned to the control of the host 300. The control device 101 includes, for example, a circuit for changing the period of the SWCLK in order to dynamically change the period of the SWCLK.

[0145] This allows cold starting only some of the CPUs 200, 210, and 220 included in the semiconductor device 11, while preventing cold starting of the remaining parts. Therefore, the control device 101 makes it easier for the host 300 to debug only those parts.

[0146] Furthermore, for example, SWCLK and the recovery signal differ in at least one of the period during which the signal level is high and the period during which the signal level is low.

[0147] This allows only some of the CPUs 200, 210, and 220 to be cold started.

[0148] Furthermore, for example, the output unit 140 outputs the SWCLK to the control device 102 after outputting the recovery signal to the control device 102 .

[0149] This allows only a portion of the CPUs 200, 210, and 220 to be cold started, and then processing based on SWCLK (i.e., debugging) can be performed on that portion.

[0150] (Representative Example) Fig. 10 is a flowchart showing a control method according to an embodiment. Specifically, Fig. 10 is a flowchart for explaining the basic processing steps of a control method executed by a control device such as the above-described control devices 100 and 101. For example, the control device includes a circuit, and the circuit performs the following processing. The circuit may include a processing circuit that performs the processing. The circuit may also include a holding circuit such as a register and / or memory.

[0151] The following processing is performed when the power supply to the processor is shut off.

[0152] First, the control device performs a detection process to detect input of a first signal to a first terminal. Specifically, the control device determines whether input of the first signal to the first terminal is detected (S10). The first terminal is, for example, the external terminal 500. The first signal is, for example, the external signal.

[0153] If the control device does not detect input of the first signal to the first terminal, specifically, if it determines that input of the first signal to the first terminal has not been detected (No in S10), it repeats the processing of step S10.

[0154] On the other hand, when the control device detects input of the first signal to the first terminal, specifically, when it determines that input of the first signal to the first terminal has been detected (Yes in S10), the control device performs a detection process to detect input of a second signal to the second terminal. Specifically, the control device determines whether input of the second signal to a second terminal different from the first terminal has been detected (S20). The second terminal is, for example, the above-mentioned terminal 510. The second signal is, for example, the above-mentioned SWCLK.

[0155] For example, the control device performs a detection process to detect an input of a second signal to the second terminal in parallel with a detection process to detect an input of a first signal to the first terminal. As a result, for example, when the input of the first signal to the first terminal is detected, the control device determines whether the input of the second signal to the second terminal is detected. Specifically, the control device determines whether the input of the second signal to the second terminal is also detected at the timing when the input of the first signal to the first terminal is detected.

[0156] When the control device detects the input of the second signal to the second terminal, specifically, when it determines that the input of the second signal to the second terminal has been detected (Yes in S20), it cold-starts the processor (S30). That is, the control device starts the processor and causes the processor to stop the recovery process at the beginning of the recovery process program. In this way, when the control device detects the input of the second signal to the second terminal when the input of the first signal to the first terminal is detected, it cold-starts the processor.

[0157] On the other hand, if the control device does not detect the input of the second signal to the second terminal, specifically, if it determines that the input of the first signal to the first terminal has not been detected (No in S20), the control device does not cold start the processor. In this case, for example, the control device starts up the processor and causes the processor to execute all of the recovery processing programs.

[0158] (Other Embodiments) As described above, the embodiments have been described as examples of the technology according to the present disclosure. However, the technology according to the present disclosure is not limited to these, and can be applied to the embodiments in which modifications, substitutions, additions, omissions, etc. are made as appropriate. For example, the following modifications are also included in one embodiment of the present disclosure.

[0159] For example, the number of control devices and CPUs (processors) included in the MCM 600 may be two, or four or more.

[0160] Also, for example, the control device and the processor are provided on one chip, but the control device and the processor may be provided on separate chips.

[0161] Furthermore, for example, some or all of the functions of the control device are typically realized by an LSI, which is an integrated circuit. These may be individually integrated into a single chip, or some or all of them may be integrated into a single chip. Furthermore, the integrated circuit is not limited to an LSI, and may be realized by a dedicated circuit or a general-purpose processor. It is also possible to use an FPGA (Field Programmable Gate Array), which can be programmed after LSI manufacturing, or a reconfigurable processor, which can reconfigure the connections and settings of circuit cells within the LSI.

[0162] Furthermore, if an integrated circuit technology that can replace LSI emerges due to advances in semiconductor technology or other derived technologies, it is natural that each component included in the control device 100 may be integrated into an integrated circuit using that technology.

[0163] Furthermore, for example, in each of the above embodiments, a process executed by a specific processing unit may be executed by another processing unit, the order of multiple processes may be changed, or multiple processes may be executed in parallel.

[0164] In addition, this disclosure also includes forms obtained by applying various modifications to each embodiment that a person skilled in the art would think of, and forms realized by arbitrarily combining the components and functions of each embodiment within the scope of this disclosure.

[0165] (Additional Note) Below, examples of techniques that can be obtained from the disclosure of this specification will be given, and the effects and the like that can be obtained from the exemplified techniques will be described.

[0166] (Technology 1) A control device comprising: a first detection unit that detects input of a first signal to a first terminal; a second detection unit that detects input of a second signal to a second terminal different from the first terminal; and a control unit that cold-starts a first processor if input of the second signal to the second terminal is detected when input of the first signal to the first terminal is detected.

[0167] The control devices 100 and 101 are an example of a control device. The first detection unit 110 is an example of a first detection unit. The second detection unit 120 is an example of a second detection unit. The control unit 130 is an example of a control unit. The external terminal 500 is an example of a first terminal. The terminal 510 is an example of a second terminal. The external signal is an example of a first signal. The SWCLK is an example of a second signal. The CPU 200 is an example of a first processor.

[0168] According to this, when a first signal for powering down a first processor is detected via a first terminal, the control device can determine whether to cold start the first processor based on the input of a second signal from a second terminal to which a computer such as a debugger is connected. For example, if the control device detects the input of the second signal to the second terminal at the timing when the input of the first signal to the first terminal is detected, the control device cold starts the first processor, and if the input of the second signal to the second terminal is not detected, the control device does not cold start the first processor. Therefore, the control device can cold start the first processor even when the recovery process of the first processor is performed using a signal other than a signal from a debugger. Therefore, the control device according to technique 1 facilitates debugging of the processor.

[0169] (Technology 2) The control device according to Technology 1, wherein the second detection unit detects the input of the second signal to the second terminal by repeatedly switching the state of the second terminal between a pull-up state and a pull-down state.

[0170] This makes it possible to detect the input of the second signal to the second terminal.

[0171] (Technology 3) The control device according to Technology 1 or 2 further includes an output unit that outputs a third signal, and the output unit outputs a signal that satisfies a predetermined condition as the third signal when a second processor different from the first processor is to be cold started, and outputs a signal that does not satisfy the predetermined condition as the third signal when the second processor is not to be cold started.

[0172] The return signal is an example of a third signal. The output unit 140 is an example of an output unit. The CPU 210 is an example of a second processor.

[0173] An LSI or MCM may have multiple processors mounted thereon. In such cases, it may be desired to debug only some of the processors. Therefore, the control device according to the third technique uses the third signal to switch whether or not to cold start the second processor. Therefore, the control device according to the third technique makes it easy to debug only some of the processors.

[0174] (Technology 4) The control device according to Technology 3, wherein the second signal and the third signal differ in at least one of a period during which the signal level is high and a period during which the signal level is low.

[0175] This allows only some of the processors to be cold started.

[0176] (Technology 5) The control device according to Technology 3 or 4, wherein the output unit outputs the second signal after outputting the third signal.

[0177] According to this, after cold starting only some of the processors, processing based on the second signal can be performed.

[0178] (Technology 6) A control device according to any one of technologies 1 to 5, wherein the second signal is a clock signal used by a debugger when debugging the first processor.

[0179] This allows the debugger to debug a cold-started processor even when a signal other than a signal from the debugger is used to perform the processor recovery process.

[0180] (Technology 7) A control method that detects input of a first signal to a first terminal, detects input of a second signal to a second terminal different from the first terminal, and cold-starts a first processor if input of the second signal to the second terminal is detected when input of the first signal to the first terminal is detected.

[0181] This provides the same effects as the control device described in the first technique.

[0182] These comprehensive or specific aspects may be realized as a system, a method, an integrated circuit, a computer program, or a non-transitory recording medium such as a computer-readable CD-ROM, or may be realized as any combination of a system, a method, an integrated circuit, a computer program, and a recording medium.

[0183] The present disclosure can be applied to an LSI equipped with a processor to be debugged.

[0184] 1, 1A Debug system 10, 11 Semiconductor device 100, 101, 102, 103 Control device 110 First detection unit 120 Second detection unit 130, 170 Control unit 140 Output unit 150 Third detection unit 160 Comparison unit 200, 210, 220 CPU 300 Host 400, 401, 402, 403 SoC 410 I / O cell 420, 421 Determination circuit 430 Adjustment circuit 440 Selector 450 Comparison circuit 500 External terminal 510, 520, 530, 540, 550, 560 Terminal 600 MCM

Claims

1. A control device comprising: a first detection unit that detects input of a first signal to a first terminal; a second detection unit that detects input of a second signal to a second terminal different from the first terminal; and a control unit that cold-starts a first processor if input of the second signal to the second terminal is detected when input of the first signal to the first terminal is detected.

2. The control device according to claim 1, wherein the second detection unit detects the input of the second signal to the second terminal by repeatedly switching the state of the second terminal between a pull-up state and a pull-down state.

3. The control device according to claim 1, further comprising an output unit that outputs a third signal, wherein the output unit outputs a signal that satisfies a predetermined condition as the third signal when a second processor different from the first processor is to be cold started, and outputs a signal that does not satisfy the predetermined condition as the third signal when the second processor is not to be cold started.

4. The control device according to claim 3, wherein the second signal and the third signal differ in at least one of the period during which the signal level is high and the period during which the signal level is low.

5. The control device according to claim 3, wherein the output unit outputs the second signal after outputting the third signal.

6. The control device according to any one of claims 1 to 5, wherein the second signal is a clock signal used when a debugger debugs the first processor.

7. A control method comprising: detecting an input of a first signal to a first terminal; detecting an input of a second signal to a second terminal different from the first terminal; and cold-starting a first processor if the input of the second signal to the second terminal is detected when the input of the first signal to the first terminal is detected.

Images