Gate drive circuit, display substrate, and display device

Abstract

A gate drive circuit, a display substrate, and a display device. The gate drive circuit comprises a plurality of cascaded shift registers (GOA) and M clock signal lines connected to the plurality of shift registers (GOA), wherein M is an even number greater than or equal to 4; a first signal input end (input) of an Nth-stage shift register (GOA) is connected to a signal output end of an (N-M2)th-stage shift register (GOA), wherein N is a positive integer; a second signal input end (PD_F) of the Nth-stage shift register (GOA) is connected to a signal output end of an (N-M / 2-P)th-stage shift register (GOA), wherein P is a positive integer greater than 0 and less than or equal to M / 2; or the second signal input end (PD_F) of the Nth-stage shift register (GOA) is connected to a pull-up output end (PU_out) of an (N-M / 2+J)-stage shift register (GOA), and the pull-up output end (PU_out) is connected to a pull-up node (PU), wherein J is a positive integer greater than 0 and less than M / 2. In the gate drive circuit, the contention relationship between the pull-up node (PU) and a pull-down node (PD) is reduced, and the output capability is improved.

Description

Gate driving circuit, display substrate and display device Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate drive circuit, a display substrate and a display device. Background Art

[0002] In the related technology, the output control subcircuit of the shift register transmits the clock signal to the signal output end under the control of the pull-up node voltage, and the output control subcircuit of the shift register transmits the second operating voltage provided by the second power supply end to the signal output end under the control of the pull-down node voltage. The voltage of the pull-down node affects the rise of the pull-up node, resulting in a competitive relationship between the pull-up node and the pull-down node, which in turn affects the product's low-temperature startup capability and service life.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a gate drive circuit, a display substrate and a display device.

[0005] To achieve the above objectives, according to one aspect of the present disclosure, a gate drive circuit is provided, comprising: a plurality of cascaded shift registers and M clock signal lines connected to the plurality of shift registers, each of the shift registers comprising an input subcircuit, an output control subcircuit, and a noise reduction control subcircuit, wherein the input subcircuit and the output control subcircuit are connected to a pull-up node, and the noise reduction control subcircuit and the output control subcircuit are connected to a first node; the input subcircuit is configured to charge the pull-up node under the control of a first input signal terminal; the output control subcircuit is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node, and to output a second operating voltage to the signal output terminal under the control of the potential of the first node; the noise reduction control subcircuit is configured to pull down the potential of the first node under the control of a second input signal terminal; wherein the first node comprises a pull-down node and / or a pull-down control node, and M is an even number greater than or equal to 4;

[0006] The first signal input terminals of the shift registers of the 1st to M / 2nd stages are connected to their respective corresponding first start signal terminals. Except for the shift registers of the 1st to M / 2nd stages, the first signal input terminal of the shift register of the Nth stage is connected to the signal output terminal of the shift register of the (NM / 2)th stage.

[0007] The second signal input terminals of the shift registers of levels 1 to M / 2+P are connected to their respective corresponding second starting signal terminals. Except for the shift registers of levels 1 to M / 2+P, the second signal input terminal of the shift register of level N is connected to the signal output terminal of the shift register of level (NM / 2-P), where P is a positive integer greater than 0 and less than or equal to M / 2, and N is a positive integer greater than M / 2+P; or, the second signal input terminals of the shift registers of levels 1 to M / 2-J are connected to their respective corresponding second starting signal terminals. Except for the shift registers of levels 1 to M / 2-J, the second signal input terminal of the shift register of level N is connected to the pull-up output terminal of the shift register of level (NM / 2+J), and the pull-up output terminal is connected to the pull-up node, where J is a positive integer greater than 0 and less than M / 2.

[0008] In some embodiments, the input subcircuit includes a first reset module, the first reset module is connected to the pull-up node, and the first reset module is configured to pull down the potential of the pull-up node under the control of a first reset signal input terminal.

[0009] Except for the shift register of the last M / 2+1 levels, the first reset signal input terminal of the shift register of the Nth level is connected to the signal output terminal of the shift register of the N+M / 2+1th level, and the first reset signal input terminal of the shift register of the last M / 2+1 levels is connected to the respective corresponding first reset signal terminals.

[0010] In some embodiments, the pull-down node includes a first pull-down node and a second pull-down node, and the noise reduction control subcircuit includes:

[0011] a first transistor, wherein a control electrode of the first transistor is connected to the second signal input terminal, a first electrode of the first transistor is connected to the first pull-down node, and a second electrode of the first transistor is connected to the second power supply terminal;

[0012] A second transistor, wherein a control electrode of the second transistor is connected to the second signal input terminal, a first electrode of the second transistor is connected to the second pull-down node, and a second electrode of the second transistor is connected to the second power supply terminal.

[0013] In some embodiments, the pull-down control node includes a first pull-down control node and a second pull-down control node, and the noise reduction control subcircuit includes:

[0014] a third transistor, wherein a control electrode of the third transistor is connected to the second signal input terminal, a first electrode of the third transistor is connected to the first pull-down control node, and a second electrode of the third transistor is connected to the second power supply terminal;

[0015] a fourth transistor, wherein a control electrode of the fourth transistor is connected to the second signal input terminal, a first electrode of the fourth transistor is connected to the second pull-down control node, and a second electrode of the fourth transistor is connected to the second power supply terminal.

[0016] In some embodiments, the output control subcircuit includes: a pull-up module, a first pull-down control module, and a first pull-down module, wherein the first pull-down control module and the first pull-down module are connected to a first pull-down node, and the signal output end includes a first signal output end and a second signal output end;

[0017] The pull-up module is connected to the pull-up node, the clock signal input terminal, the first signal output terminal, and the second signal output terminal, and is responsive to the control of the potential of the pull-up node and configured to input the clock signal provided by the clock signal input terminal to the first signal output terminal and the second signal output terminal when the potential of the pull-up node is in an effective level state;

[0018] The first pull-down control module is connected to the pull-up node, the first pull-down node, a second power supply terminal, and a third power supply terminal, and is responsive to control of the potential of the pull-up node to input a second operating voltage provided by the second power supply terminal to the first pull-down node when the potential of the pull-up node is in a valid level state, and to input a third operating voltage provided by the third power supply terminal to the first pull-down node when the potential of the pull-up node is in a non-valid level state;

[0019] The first pull-down module is connected to the first pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal and the fifth power supply terminal, and responds to the control of the potential of the first pull-down node. It is used to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and input the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the first pull-down node is in a valid level state.

[0020] In some embodiments, the pull-up module includes a fifth transistor, a sixth transistor, and a first capacitor.

[0021] The control electrodes of the fifth transistor and the sixth transistor are connected to the pull-up node, the first electrodes of the fifth transistor and the sixth transistor are connected to the clock signal input terminal, the second electrode of the fifth transistor is connected to the first signal output terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal;

[0022] A first end of the first capacitor is connected to the pull-up node, and a second end of the first capacitor is connected to the first signal output end.

[0023] In some embodiments, the clock signal input terminal includes a first clock signal input terminal and a second clock signal input terminal, and the pull-up module includes a fifth transistor, a sixth transistor, a first capacitor and a second capacitor.

[0024] The control electrode of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first clock signal input terminal, and the second electrode of the fifth transistor is connected to the first signal output terminal;

[0025] The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second clock signal input terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal;

[0026] A first end of the first capacitor is connected to the pull-up node, and a second end of the first capacitor is connected to the first signal output end;

[0027] A first end of the second capacitor is connected to the pull-up node, and a second end of the second capacitor is connected to the second signal output end.

[0028] In some embodiments, the first pull-down control module includes: a seventh transistor, an eighth transistor, a ninth transistor, and a tenth transistor;

[0029] The control electrode of the seventh transistor is connected to the third power supply terminal, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the first pull-down control node;

[0030] The control electrode of the eighth transistor is connected to the first pull-down control node, the first electrode of the eighth transistor is connected to the third power supply terminal, and the second electrode of the eighth transistor is connected to the first pull-down node;

[0031] The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the first pull-down control node, and the second electrode of the ninth transistor is connected to the second power supply terminal;

[0032] The control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the first pull-down node, and the second electrode of the tenth transistor is connected to the second power supply terminal;

[0033] The first pull-down module includes: an eleventh transistor and a twelfth transistor;

[0034] The control electrode of the eleventh transistor is connected to the first pull-down node, the first electrode of the eleventh transistor is connected to the first signal output terminal, and the second electrode of the eleventh transistor is connected to the fifth power supply terminal;

[0035] The control electrode of the twelfth transistor is connected to the first pull-down node, the first electrode of the twelfth transistor is connected to the second signal output end, and the second electrode of the twelfth transistor is connected to the second power supply end.

[0036] In some embodiments, the output control subcircuit further includes a second pull-down module and a second pull-down control module, wherein the second pull-down control module and the second pull-down module are connected to a second pull-down node;

[0037] The second pull-down control module is connected to the pull-up node, the second pull-down node, the second power supply terminal, and the fourth power supply terminal, and is responsive to the control of the potential of the pull-up node to input the second operating voltage provided by the second power supply terminal to the second pull-down node when the potential of the pull-up node is in a valid level state, and to input the fourth operating voltage provided by the fourth power supply terminal to the second pull-down node when the potential of the pull-up node is in a non-valid level state;

[0038] The second pull-down module is connected to the second pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal, and is responsive to the control of the potential of the second pull-down node and configured to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the second pull-down node is in an effective level state;

[0039] The third operating voltage switches between a valid level state and a non-valid level state, and the fourth operating voltage switches between a valid level state and a non-valid level state; at any time, one of the third operating voltage and the fourth operating voltage is in a valid level state, and the other is in a non-valid level state.

[0040] In some embodiments, the second pull-down control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, and a sixteenth transistor;

[0041] The control electrode of the thirteenth transistor is connected to the fourth power supply terminal, the first electrode of the thirteenth transistor is connected to the fourth power supply terminal, and the second electrode of the thirteenth transistor is connected to the second pull-down control node;

[0042] The control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode of the fourteenth transistor is connected to the fourth power supply terminal, and the second electrode of the fourteenth transistor is connected to the second pull-down node;

[0043] The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode of the fifteenth transistor is connected to the second pull-down control node, and the second electrode of the fifteenth transistor is connected to the second power supply terminal;

[0044] The control electrode of the sixteenth transistor is connected to the pull-up node, the first electrode of the sixteenth transistor is connected to the second pull-down node, and the second electrode of the sixteenth transistor is connected to the second power supply terminal;

[0045] The second pull-down module includes: a seventeenth transistor and an eighteenth transistor;

[0046] The control electrode of the seventeenth transistor is connected to the second pull-down node, the first electrode of the seventeenth transistor is connected to the first signal output terminal, and the second electrode of the seventeenth transistor is connected to the fifth power supply terminal;

[0047] The control electrode of the eighteenth transistor is connected to the second pull-down node, the first electrode of the eighteenth transistor is connected to the second signal output end, and the second electrode of the eighteenth transistor is connected to the second power supply end.

[0048] In some embodiments, the output control subcircuit further includes a first noise reduction module and a second noise reduction module.

[0049] The first noise reduction module is connected to the pull-up node, the first pull-down node, and the second power supply terminal, and is responsive to the control of the potential of the first pull-down node and configured to input the second operating voltage provided by the second power supply terminal to the pull-up node when the potential of the first pull-down node is in a valid level state;

[0050] The second noise reduction module is connected to the pull-up node, the second pull-down node and the second power supply terminal, and is responsive to control of the potential of the second pull-down node for inputting the second operating voltage provided by the second power supply terminal into the pull-up node when the potential of the second pull-down node is in a valid level state.

[0051] In some embodiments, the first noise reduction module includes a nineteenth transistor, wherein a control electrode of the nineteenth transistor is connected to the first pull-down node, a first electrode of the nineteenth transistor is connected to the pull-up node, and a second electrode of the nineteenth transistor is connected to the second power supply terminal;

[0052] The second noise reduction module includes a twentieth transistor, wherein the control electrode of the twentieth transistor is connected to the second pull-down node, the first electrode of the twentieth transistor is connected to the pull-up node, and the second electrode of the twentieth transistor is connected to the second power supply terminal.

[0053] In some embodiments, the input subcircuit includes: a signal input module, a first reset module, and a second reset module;

[0054] The signal input module is connected to the pull-up node, the first signal input terminal and the first power supply terminal, and is responsive to voltage control of the first signal input terminal, and is configured to input a first operating voltage provided by the first power supply terminal to the pull-up node when a first input signal provided by the first signal input terminal is in a valid level state;

[0055] The first reset module is connected to the pull-up node, the first reset signal input terminal, and the second power supply terminal, and is responsive to voltage control of the first reset signal input terminal and configured to input a second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the first reset signal input terminal is in a valid level state;

[0056] The second reset module is connected to the pull-up node, the second reset signal input terminal and the second power supply terminal, and is responsive to the voltage control of the second reset signal input terminal and is configured to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the second reset signal input terminal is in a valid level state.

[0057] In some embodiments, the signal input module includes a twenty-first transistor, a control electrode of the twenty-first transistor is connected to the first signal input terminal, a first electrode of the twenty-first transistor is connected to the first power supply terminal, and a second electrode of the twenty-first transistor is connected to the pull-up node;

[0058] The first reset module includes a twenty-second transistor, a control electrode of the twenty-second transistor is connected to the first reset signal input terminal, a first electrode of the twenty-second transistor is connected to the pull-up node, and a second electrode of the twenty-second transistor is connected to the second power supply terminal;

[0059] The second reset module includes a twenty-third transistor, a control electrode of the twenty-third transistor is connected to the second reset signal input terminal, a first electrode of the twenty-third transistor is connected to the pull-up node, and a second electrode of the twenty-third transistor is connected to the second power supply terminal.

[0060] According to another aspect of the present disclosure, a display substrate is provided, comprising a base substrate and the above-mentioned gate driving circuit, wherein the gate driving circuit is disposed on the base substrate.

[0061] In some embodiments, the shift register in the gate drive circuit includes:

[0062] a fifth transistor;

[0063] a sixth transistor, wherein the fifth transistor and the sixth transistor are arranged at intervals along the first direction;

[0064] a first capacitor, wherein the first capacitor and the sixth transistor are located on the same side of the fifth transistor and are arranged at intervals along a second direction, the first direction intersects the second direction, the first capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, the second electrode plate is located on a side of the first electrode plate away from the substrate, and the first electrode plate is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

[0065] In some embodiments, the display substrate includes a gate metal layer, a semiconductor layer, and a source / drain metal layer sequentially arranged in a direction away from the base substrate, wherein:

[0066] The control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are all located in the gate metal layer, and at least a portion of the control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are an integrated structure.

[0067] The first electrode of the fifth transistor, the second electrode of the fifth transistor, the first electrode of the sixth transistor, the second electrode of the sixth transistor, and the second electrode plate of the first capacitor are all located in the source-drain metal layer.

[0068] In some embodiments, the shift register also includes a first transfer electrode and a first connecting line, the first connecting line of the (NM / 2+J)th level shift register is electrically connected to the second signal input end of the Nth level shift register, the first transfer electrode is connected to the first connecting line through a first via, and the first transfer electrode is connected to the first electrode plate through a second via.

[0069] In some embodiments, the display substrate also includes a first signal transmission line extending along the second direction, the first signal transmission line of the (NM / 2)th level shift register is connected to the first signal input end of the Nth level shift register, and the orthographic projection of the first connecting line on the base substrate is arranged to intersect with the orthographic projection of the first signal transmission line on the base substrate.

[0070] In some embodiments, the shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially arranged in a direction away from the substrate, wherein:

[0071] The first electrode plate is located in the gate metal layer;

[0072] The first connecting line is located in the source-drain metal layer;

[0073] The first switching electrode is located in the transparent conductive layer.

[0074] In some embodiments, the display substrate also includes a first signal transmission line, and the shift register also includes a second transfer electrode and a second connecting line, one end of the second connecting line is connected to the second transfer electrode, and the other end of the second connecting line is connected to the second electrode of the sixth transistor, the second transfer electrode is connected to the second connecting line through a third via, and the second transfer electrode is connected to the first signal transmission line through a fourth via, and the first signal transmission line of the (NM / 2)th level shift register is connected to the first signal input end of the Nth level shift register.

[0075] In some embodiments, the first signal transmission line of the (NM / 2-P)th stage shift register is connected to the second signal input terminal of the Nth stage shift register.

[0076] In some embodiments, the shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially arranged in a direction away from the substrate, wherein:

[0077] The first signal transmission line is located in the gate metal layer;

[0078] The second connecting line is located in the source-drain metal layer;

[0079] The second switching electrode is located in the transparent conductive layer.

[0080] In some embodiments, the shift register further includes a second capacitor, and the second capacitor includes:

[0081] The first sub-capacitor includes a first sub-plate and a second sub-plate that are arranged opposite to each other;

[0082] The second sub-capacitor includes a third sub-plate and a fourth sub-plate that are arranged opposite to each other;

[0083] a third sub-capacitor, comprising a fifth sub-plate and a sixth sub-plate arranged opposite to each other;

[0084] The second sub-plate, the fourth sub-plate, and the fifth sub-plate are electrically connected, and the first sub-plate, the third sub-plate, and the sixth sub-plate are electrically connected.

[0085] In some embodiments, the first sub-plate, the third sub-plate, the fifth sub-plate and the first electrode plate are arranged in the same layer;

[0086] The second sub-plate, the fourth sub-plate and the sixth sub-plate are arranged in the same layer.

[0087] In some embodiments, the first sub-plate and the first electrode plate are an integrated structure.

[0088] In some embodiments, the shift register further includes a second transfer electrode, the second sub-plate and the fourth sub-plate are connected to the second transfer electrode through a third via, and the fifth sub-plate is connected to the second transfer electrode through a fourth via.

[0089] In some embodiments, the display substrate further includes a first signal transmission line, the first signal transmission line of the (NM / 2)th level shift register is connected to the first signal input end of the Nth level shift register, and a portion of the first signal transmission line serves as the fifth sub-plate.

[0090] In some embodiments, the sixth sub-plate includes a first extension portion and a second extension portion, the first extension portion is cross-connected with the second extension portion, the first extension portion is parallel to the first signal transmission line, and the two ends of the second extension portion are electrically connected to the first sub-plate and the third sub-plate respectively.

[0091] In some embodiments, the shift register further includes a first transfer electrode and a first connecting line, a portion of the first connecting line serves as the second extension portion, the first transfer electrode is connected to the second extension portion through a first via, and the first transfer electrode is connected to the first extension portion through a second via.

[0092] In some embodiments, the shift register also includes a second capacitor, the orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the first capacitor on the substrate and the orthographic projection of the sixth transistor on the substrate, the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate and the first electrode plate are an integral structure, and the second electrode plate and the fourth electrode plate are arranged on the same layer.

[0093] In some embodiments, the first capacitor further includes a fifth electrode plate, the fifth electrode plate being located on a side of the second electrode plate away from the first electrode plate, and the fifth electrode plate being electrically connected to the first electrode plate.

[0094] The second capacitor further includes a sixth electrode plate, which is located on a side of the fourth electrode plate away from the third electrode plate and is electrically connected to the third electrode plate. The fifth electrode plate and the sixth electrode plate are arranged on the same layer.

[0095] In some embodiments, the shift register further includes a first switching electrode, the first switching electrode is connected to the first electrode plate through a second via hole, and the first switching electrode, the fifth electrode plate, and the sixth electrode plate are an integrated structure.

[0096] In some embodiments, the active layer of the fifth transistor and the active layer of the sixth transistor, the active layer of the fifth transistor includes a first active area and a second active area, the first active area and the second active area are spaced apart and arranged along the second direction,

[0097] The first capacitor and the first active area are arranged at intervals along a first direction;

[0098] The active layer of the sixth transistor and the second active region are arranged at intervals along a first direction, the first capacitor and the active layer of the sixth transistor are arranged at intervals along a second direction, and the first direction intersects the second direction.

[0099] In some embodiments, the display substrate has a display area and a non-display area, the gate driving circuit is located in the non-display area, and the display substrate further includes a transparent electrode located in the display area, and the transparent electrode is arranged in the same layer as the first switching electrode.

[0100] According to yet another aspect of the present disclosure, a display device is provided, comprising the above-mentioned display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0101] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following detailed description, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0102] FIG1 shows an exemplary structural diagram of a gate driving circuit according to an optional embodiment of the present disclosure;

[0103] FIG2 is a schematic structural diagram of the shift register in FIG1 ;

[0104] FIG3 shows a schematic structural diagram of a shift register in FIG1 ;

[0105] FIG4 shows a schematic structural diagram of another shift register in FIG1 ;

[0106] FIG5 is a comparison diagram showing the signal output conditions of the two shift registers in FIG3 and FIG4;

[0107] FIG6 shows an exemplary structural diagram of a gate driving circuit according to another optional embodiment of the present disclosure;

[0108] FIG7 shows a schematic structural diagram of a shift register in FIG6 ;

[0109] FIG8 shows a schematic structural diagram of another shift register in FIG6 ;

[0110] FIG9 is a comparison diagram showing the signal output conditions of the two shift registers in FIG4 and FIG8;

[0111] FIG10 shows a comparison of the output capabilities of the two shift registers in FIG4 and FIG8 ;

[0112] FIG11 shows an exemplary structural diagram of a gate driving circuit according to another alternative embodiment of the present disclosure;

[0113] FIG12 shows a schematic structural diagram of a shift register in FIG11 ;

[0114] FIG13 shows a schematic structural diagram of another shift register in FIG11 ;

[0115] FIG14 shows a timing diagram of various signals in the shift register in FIG11 ;

[0116] FIG15 is a diagram comparing the signal outputs of the two shift registers in FIG8 and FIG13;

[0117] FIG16 shows a comparison of the output capabilities and charging rates of the two shift registers shown in FIG8 and FIG13 ;

[0118] FIG17 shows a capacitance design simulation diagram of the second capacitor 12 in FIG11 ;

[0119] FIG18 shows a timing diagram of clock signals in an optional embodiment of the present disclosure;

[0120] FIG19 is a schematic diagram showing the superposition of a gate metal layer, a semiconductor layer, a source / drain metal layer, an insulating layer, and a transparent conductive layer of a display substrate in an optional embodiment of the present disclosure;

[0121] FIG20 is a schematic plan view showing the gate metal layer in FIG19 ;

[0122] FIG21 is a schematic plan view showing the semiconductor layer in FIG19 ;

[0123] FIG22 is a schematic plan view showing the source / drain metal layer in FIG19 ;

[0124] FIG23 shows a schematic plan view of the insulating layer in FIG19 ;

[0125] FIG24 shows a schematic plan view of the transparent conductive layer in FIG19 ;

[0126] FIG25 is a schematic diagram showing the superposition of a gate metal layer, a semiconductor layer, a source / drain metal layer, an insulating layer, and a transparent conductive layer of a display substrate in another optional embodiment of the present disclosure;

[0127] FIG26 is a schematic plan view showing the gate metal layer in FIG25 ;

[0128] FIG27 is a schematic plan view showing the semiconductor layer in FIG25 ;

[0129] FIG28 is a schematic plan view showing the source / drain metal layer in FIG25 ;

[0130] FIG29 shows a schematic plan view of the insulating layer in FIG25 ;

[0131] FIG30 is a schematic plan view of the transparent conductive layer in FIG25 ;

[0132] FIG31 is a schematic diagram showing the superposition of a gate metal layer, a semiconductor layer, a source / drain metal layer, an insulating layer, and a transparent conductive layer of a display substrate in yet another optional embodiment of the present disclosure;

[0133] FIG32 is a schematic plan view of the gate metal layer in FIG31 ;

[0134] FIG33 is a schematic plan view of the semiconductor layer in FIG31 ;

[0135] FIG34 is a schematic plan view of the source / drain metal layer in FIG31 ;

[0136] FIG35 shows a schematic plan view of the insulating layer in FIG31 ;

[0137] FIG36 is a schematic plan view of the transparent conductive layer in FIG31 .

[0138] 10. Input subcircuit; 11. Signal input module; 12. First reset module; 13. Second reset module; 20. Output control subcircuit; 21. Pull-up module; 22. First pull-down control module; 23. First pull-down module; 24. Second pull-down module; 25. Second pull-down control module; 30. Noise reduction control subcircuit; 41. First electrode plate; 42. Second electrode plate; 43. Fifth electrode plate; 80. First transfer electrode; 90. First connecting line; 100. First via; 110. Second via; 120. First signal transmission line; 130. Second transfer electrode; 140. Second connecting line; 150. Third via; 160. Fourth via; 181 , first sub-plate; 182, second sub-plate; 183, third sub-plate; 184, fourth sub-plate; 185, fifth sub-plate; 186, sixth sub-plate; 187, first extension portion; 188, second extension portion; 191, third electrode plate; 192, fourth electrode plate; 193, sixth electrode plate; 230, second signal transmission line; 240, third transfer electrode; 250, fifth via hole; 260, sixth via hole; 270, third connecting line. DETAILED DESCRIPTION

[0139] The following describes the specific embodiments of the present disclosure in detail with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are only used to illustrate and explain the present disclosure and are not intended to limit the present disclosure.

[0140] Unless otherwise defined, the technical or scientific terms used in this application should have the ordinary meaning understood by a person of ordinary skill in the technical field to which this application belongs. The words "one", "a", "the" and the like used in this application do not indicate a limit on quantity and may indicate the singular or plural. The terms "include", "comprise", "have" and any variations thereof used in this application are intended to cover non-exclusive inclusions; for example, a process, method, system, product or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units that are not listed, or may also include other steps or units that are inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The word "multiple" used in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships can exist. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates an "or" relationship between the preceding and following objects. The terms "first," "second," and "third" used in this application merely distinguish similar objects and do not represent a specific ordering of the objects. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships. If the absolute position of the described objects changes, the relative positional relationship may also change accordingly.

[0141] As used herein, "parallel" and "perpendicular" include the conditions described and conditions similar to the conditions described, and the range of the similar conditions is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range for approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range for approximate perpendicularity can also be, for example, a deviation within 5°.

[0142] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0143] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0144] It should be noted that the transistors in the present invention may be thin-film transistors, field-effect transistors, or other switching devices with similar characteristics. A transistor generally comprises three electrodes: a gate, a source, and a drain. The source and drain electrodes in a transistor are structurally symmetrical and can be interchanged as needed. In the present invention, the control electrode refers to the gate of the transistor, and one of the first and second electrodes is the source electrode, while the other is the drain electrode.

[0145] In addition, according to transistor characteristics, transistors can be divided into N-type transistors and P-type transistors. When the transistor is an N-type transistor, its on-voltage is a high-level voltage and its off-voltage is a low-level voltage; when the transistor is a P-type transistor, its on-voltage is a low-level voltage and its off-voltage is a high-level voltage. In the present invention, "active level" refers to the voltage that can control the corresponding transistor to be on, and "inactive level" refers to the voltage that can control the corresponding transistor to be off. Therefore, when the transistor is an N-type transistor, the active level refers to the high level and the inactive level refers to the low level; when the transistor is a P-type transistor, the active level refers to the low level and the inactive level refers to the high level.

[0146] In the following descriptions of the various embodiments, an example is given in which all transistors are N-type transistors, wherein the active level refers to a high level and the inactive level refers to a low level.

[0147] The "same-layer arrangement" in the present disclosure means that multiple structures are formed by the same material layer through a composition process, thereby simplifying the preparation process, and the multiple structures arranged on the same layer are in the same layer in the stacking relationship; but this does not mean that the distances between the multiple structures and the substrate must be the same.

[0148] Figure 1 shows an example structural diagram of a gate drive circuit of an optional embodiment of the present disclosure; Figure 2 shows a structural schematic diagram of the shift register in Figure 1; Figure 3 shows a structural schematic diagram of a shift register in Figure 1; Figure 4 shows a structural schematic diagram of another shift register in Figure 1; Figure 5 shows a comparison diagram of the signal output conditions of the two shift registers in Figures 3 and 4.

[0149] In a first aspect, the present disclosure provides a gate drive circuit, as shown in Figures 1 and 2, the gate drive circuit includes a plurality of cascaded shift registers GOA and M clock signal lines connected to the plurality of shift registers GOA, each shift register GOA includes an input subcircuit 10, an output control subcircuit 20, and a noise reduction control subcircuit 30, wherein the input subcircuit 10 and the output control subcircuit 20 are connected to a pull-up node PU; the noise reduction control subcircuit 30 and the output control subcircuit 20 are connected to a first node, the input subcircuit 10 is configured to charge the pull-up node PU under the control of a first input signal terminal, the output control subcircuit 20 is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node PU, and output a second operating voltage to the signal output terminal under the control of the potential of the first node, the noise reduction control subcircuit 30 is configured to pull down the potential of the first node under the control of a second input signal terminal, wherein the first node includes a pull-down node and / or a pull-down control node; M is an even number greater than or equal to 4;

[0150] The first signal input terminals Input of the 1st to M / 2nd stage shift registers are connected to their respective corresponding first start signal terminals. Except for the 1st to M / 2nd stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the (NM / 2)th stage shift register, where N is a positive integer greater than M / 2+P.

[0151] The second signal input terminal PD_F of the 1st to M / 2-Jth level shift registers is connected to the corresponding second starting signal terminal. In addition to the 1st to M / 2-J level shift registers, the second signal input terminal PD_F of the Nth level shift register is connected to the pull-up output terminal PU_out of the (NM / 2+J)th level shift register, and the pull-up output terminal PU_out is connected to the pull-up node, where J is a positive integer greater than 0 and less than M / 2; wherein, the second signal input terminal PD_F is used to provide a second input signal for the noise reduction control sub-circuit 30.

[0152] In this way, when the potential of the pull-up node PU of the (M / 2-J)-level shift register GOA (NM / 2+J-level shift register) before the current-level shift register rises, the noise reduction control subcircuit 30 of the current-level shift register (N-level shift register) GOA is turned on at the same time to pre-pull down the pull-up node and / or pull-down control node of the current-level shift register GOA. That is to say, before the potential of the pull-up node PU of the current-level shift register GOA rises, the pull-down node of the current-level shift register GOA has been pulled down, thereby improving the competitive relationship between the pull-up node and the pull-down node to improve the product's low-temperature startup capability and service life.

[0153] It should be noted that when the pull-down node is in an active level state, the output control sub-circuit outputs the second operating voltage provided by the second power supply terminal. When the pull-down control node is in an active level state, the pull-down node is in an active level state, and the output control sub-circuit outputs the second operating voltage provided by the second power supply terminal. Furthermore, it can be said that the output control sub-circuit responds to control by the pull-down control node.

[0154] For example, the gate drive circuit includes 6 clock signal lines, then M=6, the first signal input terminals Input of the 1st to 3rd stage shift registers are connected to their respective corresponding first start signal terminals, and except for the 1st to 3rd stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-3th stage shift register.

[0155] J is a positive integer greater than 0 and less than 3. For example, if J=1, the second signal input terminal PD_F of the 1st to 2nd stage shift registers is connected to the corresponding second starting signal terminal, and except for the 1st to 2nd stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-2nd stage shift register. For another example, if J=2, the second signal input terminal PD_F of the first stage shift register is connected to the corresponding second starting signal terminal, and except for the first stage shift register, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-1th stage shift register.

[0156] For another example, the gate drive circuit includes 8 clock signal lines, refer to Figure 1, then M=8, the first signal input terminals Input of the 1st to 4th stage shift registers are connected to their respective corresponding first start signal terminals, and except for the 1st to 4th stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-4th stage shift register.

[0157] J is a positive integer greater than 0 and less than 4. For example, if J=1, the second signal input terminals PD_F of the 1st to 3rd stage shift registers are connected to their respective corresponding second starting signal terminals. In addition to the 1st to 3rd stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-3th stage shift register. For another example, if J=2, the second signal input terminals PD_F of the 1st to 2nd stage shift registers are connected to their respective corresponding second starting signal terminals. In addition to the 1st to 2nd stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-2nd stage shift register (see Figures 1, 3, and 4). For another example, if J=3, the second signal input terminal PD_F of the first stage shift register is connected to its respective corresponding second starting signal terminals. In addition to the first stage shift register, the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-1th stage shift register. And so on.

[0158] It should be noted that the first start signal terminal and the second start signal terminal can be connected to the frame start signal, and there is no specific limitation here. It only needs to ensure that the shift registers GOA of different levels are not started at the same time.

[0159] Each of the M adjacent shift register units is connected to the M clock signal lines in a one-to-one correspondence, and the first clock signal terminal CLKA of the i-th stage shift register and the i+Mn-th stage shift register are connected to the same clock signal line, where n is an integer not less than 0, and i is a positive integer greater than 0 and less than or equal to M.

[0160] For example, M in the gate drive circuit is 8, that is, the gate drive circuit includes eight clock signal lines, namely the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8.

[0161] Specifically, the clock signal input terminal of the shift register includes a first clock signal input terminal CLKA, wherein the first clock signal input terminal CLKA of the 8n+1 stage shift register GOA is connected to the first clock signal line CK1, the first clock signal input terminal CLKA of the 8n+2 stage shift register GOA is connected to the second clock signal line CK2, the first clock signal input terminal CLKA of the 8n+3 stage shift register GOA is connected to the third clock signal line CK3, the first clock signal input terminal CLKA of the 8n+4 stage shift register GOA is connected to the 8n+5 stage shift register GOA The four clock signal lines CK4 are connected, the first clock signal input terminal CLKA of the 8n+5th stage shift register GOA is connected to the fifth clock signal line CK5, the first clock signal input terminal CLKA of the 8n+6th stage shift register GOA is connected to the sixth clock signal line CK6, the first clock signal input terminal CLKA of the 8n+7th stage shift register GOA is connected to the seventh clock signal line CK7, and the first clock signal input terminal CLKA of the 8n+8th stage shift register GOA is connected to the eighth clock signal line CK8, where n is an integer not less than 0.

[0162] Figure 2 is a schematic diagram of the signals carried by the clock control signal lines in Figure 1. The duty cycles of the clock signals provided by the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, the fourth clock signal line CK4, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8 are all 1 / 2. Assuming a clock signal period of 8 hours, in this embodiment, the clock signals provided by the first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK4, the fourth clock signal line CK5, the fifth clock signal line CK5, the sixth clock signal line CK6, the seventh clock signal line CK7, and the eighth clock signal line CK8 are sequentially delayed by one hour.

[0163] In the specific embodiments shown in Figures 1, 3, and 4, M=8 and J=2 in the gate drive circuit, then the second signal input terminal PD_F of the Nth stage shift register is connected to the pull-up output terminal PU_out of the N-2th stage shift register, that is, when the pull-up node PU of the upper two stages shift register GOA (N-2th stage shift register) is raised, the pull-up node and / or pull-down control node of the current stage shift register GOA (Nth stage shift register) are simultaneously turned on to pre-pull down. In other words, before the pull-up node PU of the current stage shift register GOA is raised, the pull-down node of the current stage shift register GOA is pre-pulled down 2H in advance, thereby improving the competitive relationship between the pull-up node and the pull-down node to improve the low-temperature startup capability and service life of the product.

[0164] In some optional embodiments, the input sub-circuit 10 includes a first reset module 12 , which is connected to the pull-up node PU and configured to pull down the potential of the pull-up node PU under the control of the first reset signal input terminal Reset.

[0165] Except for the last M / 2+1 shift registers GOA, the first reset signal input terminal Reset of the Nth shift register GOA is connected to the signal output terminal of the N+M / 2+1th shift register GOA, and the first reset signal input terminal Reset of the last M / 2+1th shift register GOA is connected to the first reset signal terminal of each corresponding shift register. For example, if M=4, then except for the last three shift registers, the first reset signal input terminal Reset of the Nth shift register GOA is connected to the signal output terminal of the N+3th shift register, and the first reset signal input terminal Reset of the last three shift registers is connected to the first reset signal terminal. For example, if M=8, except for the last five shift registers GOA, the first reset signal input terminal Reset of the Nth shift register GOA is connected to the signal output terminal of the K+5th shift register GOA, and the first reset signal input terminal Reset of the last five shift registers GOA is connected to the first reset signal terminal.

[0166] Figure 3 is a schematic diagram of the structure of a shift register provided by the present invention, and Figure 4 is a schematic diagram of the structure of another shift register provided by the present invention. The shift register shown in Figure 3 is a specific solution based on the shift register shown in Figure 1, and the shift register shown in Figure 4 is another specific solution based on the shift register shown in Figure 1. The shift register includes an input subcircuit 10, an output control subcircuit 20, and a noise reduction control subcircuit 30.

[0167] In the specific embodiments shown in Figures 3 and 4, the input sub-circuit 10 is connected to the first signal input terminal Input and the first power supply terminal VDS, and is used to transmit the first operating voltage provided by the first power supply terminal VDS to the pull-up node PU under the control of the first input signal provided by the first signal input terminal Input.

[0168] As shown in FIG3 and FIG4 , the input sub-circuit 10 includes a signal input module 11 , a first reset module 12 and a second reset module 13 connected to the pull-up node PU.

[0169] The signal input module 11 is connected to the pull-up node PU, the first signal input terminal Input, and the first power supply terminal VDS. In response to voltage control of the first signal input terminal Input, the signal input module 11 is configured to input a first operating voltage provided by the first power supply terminal VDS to the pull-up node PU when a first input signal provided by the first signal input terminal Input is in an active level state. Specifically, the signal input module 11 includes a twenty-first transistor M21, a control electrode of the twenty-first transistor M21 being connected to the first signal input terminal Input, a first electrode of the twenty-first transistor M21 being connected to the first power supply terminal VDS, and a second electrode of the twenty-first transistor M21 being connected to the pull-up node PU.

[0170] In the specific embodiment shown in Figures 3 and 4, the first reset module 12 is connected to the pull-up node PU, the first reset signal input terminal Reset, and the second power supply terminal LVGL. In response to the voltage control of the first reset signal input terminal Reset, the first reset module 12 is configured to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the signal provided by the first reset signal input terminal Reset is at an active level. The first reset module 12 is configured to reset the pull-up node PU during the reset phase at the beginning of each scan cycle.

[0171] Specifically, the first reset module 12 includes a twenty-second transistor M22, a control electrode of the twenty-second transistor M22 is connected to the first reset signal input terminal Reset, a first electrode of the twenty-second transistor M22 is connected to the pull-up node PU, and a second electrode of the twenty-second transistor M22 is connected to the second power supply terminal LVGL.

[0172] In the specific embodiment shown in Figures 3 and 4, the second reset module 13 is connected to the pull-up node PU, the second reset signal input terminal STV0, and the second power supply terminal LVGL. In response to the voltage control of the second reset signal input terminal STV0, the second reset module 13 is configured to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the signal provided by the second reset signal input terminal STV0 is at an active level. The second reset module 13 is configured to reset the pull-up node PU at the beginning of each frame.

[0173] Specifically, the second reset module 13 includes a twenty-third transistor M23, a control electrode of the twenty-third transistor M23 is connected to the second reset signal input terminal STV0, a ​​first electrode of the twenty-third transistor M23 is connected to the pull-up node PU, and a second electrode of the twenty-third transistor M23 is connected to the second power supply terminal LVGL.

[0174] In the specific embodiments shown in Figures 3 and 4, the output control sub-circuit 20 is connected to the clock signal input terminal, the second power supply terminal LVGL, and the signal output terminal, and is responsive to the control of the voltage of the pull-up node PU. It is used to input the clock signal provided by the clock signal input terminal to the signal output terminal when the voltage of the pull-up node PU is in a valid level state, and to input the second operating voltage provided by the second power supply terminal LVGL to the signal output terminal when the voltage of the pull-up node PU is in an inactive level state.

[0175] In the specific embodiments shown in Figures 3 and 4, the output control subcircuit 20 includes a pull-up module 21, a first pull-down control module 22 and a first pull-down module 23. The first pull-down control module 22 and the first pull-down module 23 are connected to the first pull-down node PD_A, and the signal output end includes a first signal output end Gout and a second signal output end OC.

[0176] In the specific embodiments shown in Figures 3 and 4, the pull-up module 21 is connected to the pull-up node PU, the clock signal input terminal, the first signal output terminal Gout and the second signal output terminal OC, and is responsive to the control of the voltage of the pull-up node PU, and is used to input the clock signal provided by the clock signal input terminal to the first signal output terminal Gout and the second signal output terminal OC when the voltage of the pull-up node PU is in a valid level state.

[0177] In some optional embodiments, referring to Figures 3 and 4, the clock signal input terminal includes a first clock signal input terminal CLKA, the pull-up module 21 includes a fifth transistor M5, a sixth transistor M6 and a first capacitor C1, the control electrodes of the fifth transistor M5 and the sixth transistor M6 are connected to the pull-up node PU, the first electrode of the fifth transistor M5 and the first electrode of the sixth transistor M6 are connected to the first clock signal input terminal CLKA, the second electrode of the fifth transistor M5 is connected to the first signal output terminal Gout, and the second electrode of the sixth transistor M6 is connected to the second signal output terminal OC; the first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the first signal output terminal Gout.

[0178] It should be noted that the first signal output terminal Gout is used to connect to a gate line and provide signals to the sub-pixels in the same row connected to the gate line. The first signal output terminals Gout of different stages of the shift register are connected to different gate lines, thereby providing signals to sub-pixels in different rows. The second signal output terminal OC is used to connect to different stages of the shift register.

[0179] In the specific embodiments shown in Figures 3 and 4, the first pull-down control module 22 is connected to the pull-up node PU, the first pull-down node PD_A, the second power supply terminal LVGL, and the third power supply terminal VDD1, and is responsive to the control of the voltage of the pull-up node PU. It is used to input the second operating voltage provided by the second power supply terminal LVGL to the first pull-down node PD_A when the voltage of the pull-up node PU is in a valid level state, and to input the third operating voltage provided by the third power supply terminal VDD1 to the first pull-down node PD_A when the voltage of the pull-up node PU is in an inactive level state.

[0180] Specifically, the first pull-down control module 22 includes a seventh transistor M7, an eighth transistor M8, a ninth transistor M9 and a tenth transistor M10; the control electrode of the seventh transistor M7 is connected to the third power supply terminal VDD1, the first electrode of the seventh transistor M7 is connected to the third power supply terminal VDD1, and the second electrode of the seventh transistor M7 is connected to the first pull-down control node PD_CNA; the control electrode of the eighth transistor M8 is connected to the first pull-down control node PD_CNA, the first electrode of the eighth transistor M8 is connected to the third power supply terminal VDD1, and the second electrode of the eighth transistor M8 is connected to the first pull-down node PD_A; the control electrode of the ninth transistor M9 is connected to the pull-up node PU, the first electrode of the ninth transistor M9 is connected to the first pull-down control node PD_CNA, and the second electrode of the ninth transistor M9 is connected to the second power supply terminal LVGL; the control electrode of the tenth transistor M10 is connected to the pull-up node PU, the first electrode of the tenth transistor M10 is connected to the first pull-down node PD_A, and the second electrode of the tenth transistor M10 is connected to the second power supply terminal LVGL.

[0181] In the specific embodiments shown in Figures 3 and 4, the first pull-down module 23 is connected to the first pull-down node PD_A, the first signal output terminal Gout, the second signal output terminal OC, the second power supply terminal LVGL and the fifth power supply terminal VGL, and responds to the control of the voltage of the first pull-down node PD_A, and is used to input the second operating voltage provided by the second power supply terminal LVGL to the second signal output terminal OC and to input the fifth operating voltage provided by the fifth power supply terminal VGL to the first signal output terminal Gout when the voltage of the first pull-down node PD_A is in a valid level state.

[0182] It should be noted that the second power terminal LVGL and the fifth power terminal VGL may be the same port.

[0183] Specifically, the first pull-down module 23 includes an eleventh transistor M11 and a twelfth transistor M12; the control electrode of the eleventh transistor M11 is connected to the first pull-down node PD_A, the first electrode of the eleventh transistor M11 is connected to the first signal output terminal Gout, and the second electrode of the eleventh transistor M11 is connected to the fifth power supply terminal VGL; the control electrode of the twelfth transistor M12 is connected to the first pull-down node PD_A, the first electrode of the twelfth transistor M12 is connected to the second signal output terminal OC, and the second electrode of the twelfth transistor M12 is connected to the second power supply terminal LVGL.

[0184] In some optional embodiments, referring to FIG. 3 and FIG. 4 , the output control subcircuit 20 further includes a second pull-down module 24 and a second pull-down control module 25 . The second pull-down control module 25 and the second pull-down module 24 are connected to the second pull-down node PD_B.

[0185] In the specific embodiments shown in Figures 3 and 4, the second pull-down control module 25 is connected to the pull-up node PU, the second pull-down node PD_B, the second power supply terminal LVGL, and the fourth power supply terminal VDD2, and is responsive to the control of the voltage of the pull-up node PU. It is used to input the second operating voltage provided by the second power supply terminal LVGL to the second pull-down node PD_B when the voltage of the pull-up node PU is in a valid level state, and to input the fourth operating voltage provided by the fourth power supply terminal VDD2 to the second pull-down node PD_B when the voltage of the pull-up node PU is in an inactive level state.

[0186] The third operating voltage switches between an active level state and an inactive level state, and the fourth operating voltage switches between an active level state and an inactive level state. At any given moment, one of the third and fourth operating voltages is in an active level state and the other is in an inactive level state. In other words, the first pull-down control module 22 and the second pull-down control module 25 switch operations.

[0187] Specifically, the second pull-down control module 25 includes a thirteenth transistor M13, a fourteenth transistor M14, a fifteenth transistor M15 and a sixteenth transistor M16; the control electrode of the thirteenth transistor M13 is connected to the fourth power supply terminal VDD2, the first electrode of the thirteenth transistor M13 is connected to the fourth power supply terminal VDD2, and the second electrode of the thirteenth transistor M13 is connected to the second pull-down control node; the control electrode of the fourteenth transistor M14 is connected to the second pull-down control node PD_CNB, the first electrode of the fourteenth transistor M14 is connected to the fourth power supply terminal VDD2, and the second electrode of the fourteenth transistor M14 is connected to the second pull-down node PD_B; the control electrode of the fifteenth transistor M15 is connected to the pull-up node PU, the first electrode of the fifteenth transistor M15 is connected to the second pull-down control node PD_CNB, and the second electrode of the fifteenth transistor M15 is connected to the second power supply terminal LVGL; the control electrode of the sixteenth transistor M16 is connected to the pull-up node PU, the first electrode of the sixteenth transistor M16 is connected to the second pull-down node PD_B, and the second electrode of the sixteenth transistor M16 is connected to the second power supply terminal LVGL.

[0188] In the specific embodiments shown in Figures 3 and 4, the second pull-down module 24 is connected to the second pull-down node PD_B, the first signal output terminal Gout, the second signal output terminal OC, the second power supply terminal LVGL and the fifth power supply terminal VGL, and responds to the control of the voltage of the second pull-down node PD_B, and is used to input the second operating voltage provided by the second power supply terminal LVGL to the second signal output terminal OC and to input the fifth operating voltage provided by the fifth power supply terminal VGL to the first signal output terminal Gout when the voltage of the second pull-down node PD_B is in a valid level state.

[0189] Specifically, the second pull-down module 24 includes a seventeenth transistor M17 and an eighteenth transistor M18; the control electrode of the seventeenth transistor M17 is connected to the second pull-down node PD_B, the first electrode of the seventeenth transistor M17 is connected to the first signal output terminal Gout, and the second electrode of the seventeenth transistor M17 is connected to the fifth power supply terminal VGL; the control electrode of the eighteenth transistor M18 is connected to the second pull-down node PD_B, the first electrode of the eighteenth transistor M18 is connected to the second signal output terminal OC, and the second electrode of the eighteenth transistor M18 is connected to the second power supply terminal LVGL.

[0190] In some optional embodiments, the output control subcircuit 20 further includes a first noise reduction module 26 and a second noise reduction module 27 , as shown in FIG. 3 and FIG. 4 .

[0191] In the specific embodiments shown in Figures 3 and 4, the first noise reduction module 26 is connected to the pull-up node PU, the first pull-down node PD_A and the second power supply terminal LVGL, and is responsive to the control of the voltage of the first pull-down node PD_A, and is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the voltage of the first pull-down node PD_A is in a valid level state.

[0192] Specifically, the first noise reduction module 26 includes a nineteenth transistor M19, a control electrode of the nineteenth transistor M19 is connected to the first pull-down node PD_A, a first electrode of the nineteenth transistor M19 is connected to the pull-up node PU, and a second electrode of the nineteenth transistor M19 is connected to the second power supply terminal LVGL.

[0193] In the specific embodiments shown in Figures 3 and 4, the second noise reduction module 27 is connected to the pull-up node PU, the second pull-down node PD_B and the second power supply terminal LVGL, and is responsive to the control of the voltage of the second pull-down node PD_B, and is used to input the second operating voltage provided by the second power supply terminal LVGL to the pull-up node PU when the voltage of the second pull-down node PD_B is in a valid level state.

[0194] Specifically, the second noise reduction module 27 includes a twentieth transistor M20, a control electrode of the twentieth transistor M20 is connected to the second pull-down node PD_B, a first electrode of the twentieth transistor M20 is connected to the pull-up node PU, and a second electrode of the twentieth transistor M20 is connected to the second power supply terminal LVGL.

[0195] In some optional embodiments, the pull-down node includes a first pull-down node PD_A and a second pull-down node PD_B, and the noise reduction control sub-circuit 30 includes a first transistor M1 and a second transistor M2, please refer to Figures 3 and 4, the control electrode of the first transistor M1 is connected to the second signal input terminal PD_F, the first electrode of the first transistor M1 is connected to the first pull-down node PD_A, and the second electrode of the first transistor M1 is connected to the second power supply terminal LVGL; the control electrode of the second transistor M2 is connected to the second signal input terminal PD_F, the first electrode of the second transistor M2 is connected to the second pull-down node PD_B, and the second electrode of the second transistor M2 is connected to the second power supply terminal LVGL.

[0196] In some optional embodiments, please refer to Figure 3, the pull-down control node includes a first pull-down control node PD_CNA and a second pull-down control node PD_CNB, the noise reduction control sub-circuit 30 includes a third transistor M3 and a fourth transistor M4, the control electrode of the third transistor M3 is connected to the second signal input terminal PD_F, the first electrode of the third transistor M3 is connected to the first pull-down control node PD_CNA, and the second electrode of the third transistor M3 is connected to the second power supply terminal LVGL; the control electrode of the fourth transistor M4 is connected to the second signal input terminal PD_F, the first electrode of the fourth transistor M4 is connected to the second pull-down control node PD_CNB, and the second electrode of the fourth transistor M4 is connected to the second power supply terminal LVGL.

[0197] It should be noted that in the specific embodiment shown in FIG3 , the noise reduction control subcircuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. In the specific embodiment shown in FIG4 , the noise reduction control subcircuit 30 includes a first transistor M1 and a second transistor M2. That is, in the specific implementation shown in FIG3 , the shift register has 23 transistors, while in the specific embodiment shown in FIG4 , the shift register has 21 transistors, which facilitates achieving a narrow frame. As can be seen from FIG5 , the shift register shown in FIG3 is a 23T1C-P, while the shift register shown in FIG4 is a 21T1C-P. The output of each signal in the two shift registers is not much different.

[0198] Therefore, by removing the third transistor M3 and the fourth transistor M4 that pull down the pull-down control node from the 23T1C-P shift register shown in FIG3 , the result is the 21T1C-P shift register shown in FIG4 . While ensuring that the shift register function is not affected, the circuit complexity in the shift register is reduced and the product border is effectively reduced, thereby increasing the screen-to-body ratio and enhancing the aesthetics. After removing the third transistor M3 and the fourth transistor M4, the pull-down node can still be effectively pulled down to a low level, reducing the parasitic capacitance at the pull-up node PU. Compared to the 23T1C-P shift register, the 21T1C-P shift register voltage is increased by 0.04V, the Gout output voltage is increased by 0.13V, and the output capacity is enhanced.

[0199] Figure 6 shows an example structural diagram of a gate drive circuit of another optional embodiment of the present disclosure; Figure 7 shows a structural schematic diagram of a shift register in Figure 6; Figure 8 shows a structural schematic diagram of another shift register in Figure 6; Figure 9 shows a comparison diagram of the signal output conditions of the two shift registers in Figures 4 and 8; Figure 10 shows a comparison diagram of the output capabilities of the two shift registers in Figures 4 and 8.

[0200] In other optional embodiments, the shift register GOA is not connected to the pull-up output terminal PU_out, but is connected to the signal output terminal. Please refer to the specific embodiments shown in Figures 6 to 8. Compared with the embodiment shown in Figure 3, the shift register in the embodiment shown in Figure 7 does not have the pull-up output terminal PU_out, but the other structures are the same as the shift register structure shown in Figure 7.

[0201] Specifically, the first signal input terminals Input of the 1st to M / 2nd stage shift registers are connected to their respective corresponding first starting signal terminals, and except for the 1st to M / 2nd stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the (NM / 2)th stage shift register, where N is a positive integer; the second signal input terminals PD_F of the 1st to M / 2+Pth stage shift registers are connected to their respective corresponding second starting signal terminals, and except for the 1st to M / 2+Pth stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the signal output terminal of the (NM / 2-P)th stage shift register, where P is a positive integer greater than 0 and less than or equal to M / 2. When the potential of the pull-up node PU of the upper P-level shift register GOA is raised, the noise reduction control subcircuit 30 of the current-level shift register (N-th-level shift register) GOA is turned on at the same time, and the pull-up node and / or the pull-down control node of the current-level shift register GOA are pre-pulled down. That is to say, before the potential of the pull-up node PU of the current-level shift register GOA is raised, the pull-down node of the current-level shift register GOA has been pulled down, thereby improving the competitive relationship between the pull-up node and the pull-down node to improve the product's low-temperature startup capability and service life.

[0202] For example, the gate drive circuit includes 4 clock signal lines, then M=4, the first signal input terminals Input of the 1st to 2nd stage shift registers are connected to their respective corresponding first start signal terminals, and except for the 1st to 2nd stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-2th stage shift register.

[0203] P is a positive integer greater than 0 and less than or equal to 2. For example, if P=1, the second signal input terminals PD_F of the 1st to 3rd stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 3rd stage shift registers, the second signal input terminals PD_F of the 1st to 3rd stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 3rd stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the signal output terminal of the N-3rd stage shift register. For another example, if P=2, the second signal input terminals PD_F of the 1st to 4th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 4th stage shift registers, the second signal input terminals PD_F of the 1st to 4th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 4th stage shift registers, the second signal input terminals PD_F of the 1st to 4th stage shift registers are connected to the signal output terminal of the N-4th stage shift register.

[0204] For another example, the gate drive circuit includes 6 clock signal lines, then M=6, the first signal input terminals Input of the 1st to 3rd stage shift registers are connected to their respective corresponding first start signal terminals, and except for the 1st to 3rd stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-3th stage shift register.

[0205] P is a positive integer greater than 0 and less than or equal to 3. For example, if P=1, the second signal input terminals PD_F of the 1st to 4th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 4th stage shift registers, the second signal input terminals PD_F of the 1st to 4th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 4th stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the signal output terminal of the N-4th stage shift register. For another example, if P=2, the second signal input terminals PD_F of the 1st to 5th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 5th stage shift registers, the second signal input terminals PD_F of the 1st to 5th stage shift registers are connected to their respective corresponding second starting signal terminals. Except for the 1st to 5th stage shift registers, the second signal input terminals PD_F of the 1st to 5th stage shift registers are connected to the signal output terminal of the N-5th stage shift register, and so on.

[0206] In the specific embodiment shown in Figure 6, the gate drive circuit includes 8 clock signal lines, then M=8, the first signal input terminals Input of the 1st to 4th stage shift registers are connected to their respective corresponding first start signal terminals, and except for the 1st to 4th stage shift registers, the first signal input terminal Input of the Nth stage shift register is connected to the signal output terminal of the N-4th stage shift register.

[0207] In the specific embodiments shown in Figures 6 to 8, P=2, then the second signal input terminals PD_F of the 1st to 6th stage shift registers are connected to their respective corresponding second starting signal terminals, except for the 1st to 6th stage shift registers, the second signal input terminals PD_F of the 1st to 6th stage shift registers are connected to their respective corresponding second starting signal terminals, and except for the 1st to 6th stage shift registers, the second signal input terminal PD_F of the Nth stage shift register is connected to the signal output terminal of the N-6th stage shift register.

[0208] The cascade mode of the shift register GOA in the gate drive circuit shown in Figure 6 is different from the cascade mode of the shift register GOA in the gate drive circuit shown in Figure 1. By changing the cascade mode, when the second signal output terminal OC of the N-6th stage shift register starts to output, the pull-down node and the pull-down control node of the N-stage shift register GOA are respectively pulled down through the noise reduction control sub-circuit 30 of the N-stage shift register GOA. After 2H time, the pull-up node PU of the N-stage shift register GOA starts to rise. At this time, the pull-down node and the pull-down control node are at a low level, which can improve the competition relationship between the pull-up node PU and the pull-down node. The cascade mode shown in Figure 6 can avoid introducing parasitic capacitance into the pull-up node PU, thereby improving the output capacity of the circuit. At the same time, it avoids the rapid deterioration of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 caused by the second-stage rise of the pull-up node PU, thereby improving the stability of the circuit.

[0209] It should be noted that in the specific embodiment shown in Figure 7, the noise reduction control subcircuit 30 includes a first transistor M1, a second transistor M2, a third transistor M3, and a fourth transistor M4. In the specific embodiment shown in Figure 8, the noise reduction control subcircuit 30 includes a first transistor M1 and a second transistor M2. That is, in the specific implementation shown in Figure 7, the shift register has 23 transistors. Therefore, the shift register GOA shown in Figure 7 is 23T1C-O, and the shift register GOA shown in Figure 8 is 21T1C-O. While ensuring that the function of the shift register is not affected, the circuit complexity in the shift register is reduced and the product border is effectively reduced, the screen ratio is increased, and the aesthetics are improved.

[0210] Figure 9 compares the output of various signals in the 21T1C-O and 21T1C-P shift registers, while Figure 10 compares their output capabilities. It can be seen that the output shapes of the various signals in the 21T1C-O and 21T1C-P shift registers are similar, and the output capability of the 21T1C-O shift register is higher than that of the 21T1C-P shift register. The pull-down node in the 21T1C-O shift register decreases faster than that in the 21T1C-P shift register.

[0211] Compared with the 21T1C-P shift register, the voltage at the pull-up node PU of the 21T1C-O shift register is increased by 4.31V, the voltage of the Gout output is increased by 0.33V at room temperature, the voltage of the Gout output is increased by 1.04V at -10℃, and the voltage of the Gout output is increased by 3.99V at -20℃. The 21T1C-O shift register still has a high output capability under low temperature conditions.

[0212] Figure 11 shows an example structural diagram of a gate drive circuit of another optional embodiment of the present disclosure; Figure 12 shows a structural schematic diagram of a shift register in Figure 11; Figure 13 shows a structural schematic diagram of another shift register in Figure 11; Figure 14 shows a timing diagram of each signal in the shift register in Figure 11; 15 shows a comparison diagram of the output conditions of each signal of the two shift registers in Figures 8 and 13; Figure 16 shows a comparison diagram of the output capacity and charging rate of the two shift registers in Figures 8 and 13; Figure 17 shows a capacity design simulation diagram of the second capacitor in Figure 12 in Figure 11; Figure 18 shows a timing diagram of the clock signal in an optional embodiment of the present disclosure.

[0213] The cascade connection method of the gate drive circuit shown in FIG11 is the same as that of the gate drive circuit shown in FIG6 . However, the first signal output terminal Gout and the second signal output terminal OC of the gate drive circuit shown in FIG11 output different signals. The first signal output terminal Gout outputs the clock signal input by the first clock signal terminal CLKA, and the second signal output terminal OC outputs the clock signal input by the second clock signal terminal CLKB. The clock signal of the second clock signal terminal CLKB is delayed by H compared to the first clock signal terminal CLKA. In addition, the structure of the shift register shown in FIG12 adds a second clock signal input terminal CLKB and a second capacitor C2 compared to the structure of the shift register shown in FIG7 .

[0214] In the specific embodiment shown in Figure 12, the clock signal input end includes a first clock signal input end CLKA and a second clock signal input end CLKB, and the pull-up module 21 includes a fifth transistor M5, a sixth transistor M6, a first capacitor C1 and a second capacitor C2. The control electrode of the fifth transistor M5 is connected to the pull-up node PU, the first electrode of the fifth transistor M5 is connected to the first clock signal input end CLKA, and the second electrode of the fifth transistor M5 is connected to the first signal output end Gout; the control electrode of the sixth transistor M6 is connected to the pull-up node PU, the first electrode of the sixth transistor M6 is connected to the second clock signal input end CLKB, and the second electrode of the sixth transistor M6 is connected to the second signal output end OC; the first end of the first capacitor C1 is connected to the pull-up node PU, and the second end of the first capacitor C1 is connected to the first signal output end Gout; the first end of the second capacitor C2 is connected to the pull-up node PU, and the second end of the second capacitor C2 is connected to the second signal output end OC.

[0215] In some optional embodiments, the second capacitor C2 and the first capacitor C1 have the same capacitance, separating the first signal output terminal Gout from the second signal output terminal OC, which are controlled by the first clock signal input terminal CLKA (input CKi signal) and the second clock signal input terminal CLKB (input CKi+1 signal), respectively, to achieve asynchronous output. The second signal input terminal PD_F (row N-6 OC) of the N-stage shift register outputs a high level 1 hour before the first signal input terminal Input (row N-4 OC) to pull down the pull-down node and the pull-down control node. After 1 hour, the first signal input terminal Input begins to output a high level. At this time, the pull-down node and the pull-down control node are at a low level, which can improve the competition between the pull-up node and the pull-down node.

[0216] It should be noted that 1H is the time required to scan a row of sub-pixels, and the start and end times of the periods in which two adjacent rows of sub-pixels are in the on state differ by a unit scanning time H; accordingly, the start and end times of the pre-charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H, and the start and end times of the charging periods of two adjacent rows of sub-pixels differ by a unit scanning time H.

[0217] The first clock signal terminal CLKA of the i-th shift register and the first clock signal terminal CLKA of the i+Mn-th shift register are connected to the same clock signal line, and the second clock signal terminal CLKB of the i-th shift register and the second clock signal terminal CLKB of the i+Mn-th shift register are connected to the same clock signal line.

[0218] The first clock signal terminal CLKA of the i-th stage shift register and the second clock signal terminal CLKB of the i-th stage shift register are connected to different clock signal lines. For example, the first clock signal terminal CLKA of the i-th stage shift register is connected to the i-th clock signal line, and the second clock signal terminal CLKB of the i-th stage shift register is connected to the i+1-th clock signal line.

[0219] When the first signal input terminal Input of the N-th stage shift register starts to output a high level, the voltage of the pull-up node PU is charged to VGH1. At this time, the voltage of the first signal output terminal Gout is raised from VGL to VGH, and the voltage of the pull-up node PU is coupled to VGH2 (VGH2>VGH1) through the bootstrap effect of the first capacitor C1. After 1H, the voltage of the second signal output terminal OC starts to rise to VGH, and the voltage of the pull-up node PU is coupled to VGH3 (VGH3>VGH2>VGH1) through the bootstrap effect of the second capacitor C2. At this time, the gate voltage of the fifth transistor M5 is VGH3. After the output of the first signal output terminal Gout is completed, the voltage of the first clock signal input terminal CLKA changes from VGH to VGL. At this time, the voltage of the pull-up node PU is coupled to VGH4 through the bootstrap effect of the first capacitor C1 (VGH4>VGH5, and the voltage value can be controlled by adjusting the size relationship between C1 and C2). The voltage of the first signal output terminal Gout is discharged to VGL through M5, and then the voltage of the second signal output terminal OC is discharged from VGH to VGL. The voltage of the pull-up node PU is coupled to VGH5 by the second capacitor C2. Finally, the first reset signal input terminal Reset signal turns on the twenty-second transistor M22, and the voltage of the pull-up node PU returns to VGL.

[0220] The shift register in Figure 12 has 23 transistors, two capacitors, and is cascaded by the second signal output terminal OC and the second signal input terminal PD_F. Therefore, the shift register in Figure 12 is 23T2C-C. The shift register in Figure 13 has 21 transistors, which is two transistors less than the shift register shown in Figure 12, which is conducive to reducing the border and increasing the screen-to-body ratio.

[0221] Figure 15 shows a comparison of the signal output conditions of the two shift registers in Figures 8 and 13; compared with the shift register shown in Figure 8, the shift register shown in Figure 13 has a higher voltage, and the Tf of the first signal output terminal Gout is greatly reduced. By adjusting the GOE time (ensuring ≥Tf), the charging time is increased, the product charging rate is improved, related defects are avoided, and the image quality is improved.

[0222] As can be seen from FIG12 , as the capacitance of the second capacitor C2 increases, Tf of the first signal output terminal Gout decreases monotonically. However, considering the size of the frame, the second capacitor C2 and the first capacitor C1 remain consistent at 3Pf.

[0223] The working principle of the shift register unit of this embodiment is described below.

[0224] In the discharge stage, before the frame, that is, before display, a high-level signal is first input to the second reset signal input terminal STV0, and the low-level signal input through the low-level signal terminal (for example, the second power supply terminal LVGL, the fifth power supply terminal VGL) is used to discharge the pull-up node PU to prevent residual charge on the pull-up node PU from causing display abnormalities.

[0225] In the input stage, the first signal input terminal Input inputs a high-level signal, the twenty-first transistor M21 is turned on, and the pull-up node PU is pulled high by the high-level signal to charge the first capacitor C1.

[0226] In the output stage, since the pull-up node PU is pulled high in the input stage, the fifth transistor M5 and the sixth transistor M6 are both turned on, and the high level signal input from the clock signal terminal is output through the first signal output terminal Gout and the first signal output terminal OC.

[0227] During the reset phase, a high-level signal is input to the second reset signal input terminal STV0, the twenty-third transistor 23 is turned on, and the low-level signal input from the second power supply terminal LVGL pulls down the potential of the pull-up node PU to reset the pull-up node PU. Since the pull-up node PU is pulled low, the fifth transistor M5 and the sixth transistor M6 are turned off, and the first signal output terminal Gout and the first signal output terminal OC no longer output a high-level signal. At the same time, the first pull-down control node PD_CNA and the first pull-down node PD_A are both high-level signals, the eleventh transistor M11, the eleventh transistor M12, and the nineteenth transistor M19 are turned on, respectively, to reduce noise on the outputs of the pull-up node PU, the first signal output terminal Gout, and the first signal output terminal OC, until the next frame scan begins and the potential of the pull-up node PU is pulled high.

[0228] In a second aspect, the present disclosure provides a display substrate, which includes a base substrate and the above-mentioned gate driving circuit, and the gate driving circuit is arranged on the base substrate.

[0229] Figure 19 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source-drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in an optional embodiment of the present disclosure; Figure 20 shows a plan schematic diagram of the gate metal layer in Figure 19; Figure 21 shows a plan schematic diagram of the semiconductor layer in Figure 19; Figure 22 shows a plan schematic diagram of the source-drain metal layer in Figure 19; Figure 23 shows a plan schematic diagram of the insulating layer in Figure 19; and Figure 24 shows a plan schematic diagram of the transparent conductive layer TL in Figure 19.

[0230] As shown in Figure 19, the shift register GOA in the gate drive circuit includes a fifth transistor M5, a sixth transistor M6, and a first capacitor C1. The fifth transistor M5 and the sixth transistor M6 are arranged in a first direction. The first capacitor C1 and the sixth transistor M6 are located on the same side of the fifth transistor M5 and are arranged in a second direction Y. The first direction X intersects the second direction Y. The first capacitor C1 includes a first electrode plate 41 and a second electrode plate 42 arranged opposite each other. The second electrode plate 42 is located on the side of the first electrode plate 41 away from the substrate. The first electrode plate 41 is connected to the control electrode M5_g of the fifth transistor M5 and the control electrode M6_g of the sixth transistor M6. This arrangement fully utilizes the space on the substrate, which is conducive to achieving a narrow frame on the display substrate.

[0231] Specifically, the display substrate includes a gate metal layer (Gate), a semiconductor layer (ACT), and a source / drain metal layer (SD) arranged in sequence away from the base substrate. The semiconductor layer (ACT) is disposed on the base substrate and can be patterned using a semiconductor material, such as polycrystalline silicon. The semiconductor layer (ACT) can include the active layer and doped region patterns of each transistor in the pixel driver circuit. For a single transistor, doped region patterns are provided on both sides of the active layer, and the doped region patterns on both sides of the active layer can serve as the first and second electrodes of the transistor, respectively.

[0232] As shown in Figure 20, the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 are all located in the gate metal layer Gate. At least a portion of the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 are integrated into a single structure. The first electrode M5_1 of the fifth transistor M5, the second electrode M5_2 of the fifth transistor M5, the first electrode M6_1 of the sixth transistor M6, the second electrode M6_2 of the sixth transistor M6, and the second electrode plate 42 of the first capacitor C1 are all located in the source-drain metal layer SD. Integrating at least a portion of the control electrode M5_g of the fifth transistor M5, the control electrode M6_g of the sixth transistor M6, and the first electrode plate 41 effectively improves the tightness of the connection between the fifth transistor M5, the sixth transistor M6, and the first electrode plate 41, while also facilitating improved space utilization.

[0233] In the specific implementation shown in Figures 19 to 23, the shift register GOA also includes a first transfer electrode 80 and a first connecting line 90. The first connecting line 90 of the (NM / 2+J)-th level shift register GOA is electrically connected to the second signal input terminal PD_F of the N-th level shift register GOA. The first transfer electrode 80 is connected to the first connecting line 90 through the first via 100, and the first transfer electrode 80 is connected to the first electrode plate 41 through the second via 110.

[0234] As shown in Figures 19 to 23, the display substrate also includes a second signal transmission line 230 and a third transfer electrode 240. One end of the first connecting line 90 is connected to the first transfer electrode 80 through the first via 100, and the other end of the first connecting line 90 is connected to the third transfer electrode 240 through the fifth via 250. The third transfer electrode 240 is connected to the second signal transmission line 230 through the sixth via 260, wherein the second signal transmission line 230 of the (NM / 2+J)-th level shift register GOA is connected to the second signal input terminal PD_F of the N-th level shift register GOA.

[0235] The second signal transmission line 230 extends along the second direction Y, the first transfer electrode 80 is equivalent to the pull-up node PU in the circuit structure of the shift register GOA, and the third transfer electrode 240 is equivalent to the pull-up output terminal PU_out in the circuit structure of the shift register GOA.

[0236] As shown in Figures 19, 20 and 22, the display substrate also includes a first signal transmission line 120 extending along the second direction Y. The first signal transmission line 120 of the (NM / 2)-th level shift register GOA is connected to the first signal input terminal Input of the N-th level shift register GOA. The orthographic projection of the first connecting line 90 on the base substrate is arranged to intersect with the orthographic projection of the first signal transmission line 120 on the base substrate.

[0237] As shown in Figure 19, the display substrate also includes multiple signal transmission lines extending along the second direction Y, and the orthographic projection of the first connecting line 90 on the base substrate is arranged to intersect with the orthographic projections of the multiple signal transmission lines on the base substrate. That is, the first connecting line 90 spans across multiple transmission lines, which is conducive to improving space utilization and thus conducive to the development of the display substrate towards a narrow frame.

[0238] In the specific embodiments shown in Figures 19 to 24, the shift register GOA includes a gate metal layer Gate, a semiconductor layer ACT, a source-drain metal layer SD, and a transparent conductive layer TL, which are arranged in sequence along a direction away from the substrate, wherein the first electrode plate 41 is located in the gate metal layer Gate; the first connecting line 90 is located in the source-drain metal layer SD; and the first transfer electrode 80 is located in the transparent conductive layer TL.

[0239] In the specific embodiment shown in Figures 22 and 24, the shift register GOA further includes a second transfer electrode 130 and a second connecting line 140. One end of the second connecting line 140 is connected to the second transfer electrode 130, and the other end of the second connecting line 140 is connected to the second electrode M6_2 of the sixth transistor M6. The second transfer electrode 130 is connected to the second connecting line 140 via a third via 150. The second transfer electrode 130 is connected to the first signal transmission line 120 via a fourth via 160. The first signal transmission line 120 of the (NM / 2)-th stage shift register GOA is connected to the first signal input terminal Input of the N-th stage shift register GOA. The second connecting line 140 is located in the source-drain metal layer SD, and the second transfer electrode 130 is located in the transparent conductive layer TL.

[0240] In some optional embodiments, the first signal transmission line 120 of the (NM / 2+J)th stage shift register GOA is connected to the second signal input terminal PD_F of the Nth stage shift register GOA (not shown in the figure).

[0241] In some optional embodiments, the shift register GOA includes a gate metal layer Gate, a semiconductor layer ACT, a source-drain metal layer SD, and a transparent conductive layer TL arranged in sequence along a direction away from the substrate, wherein the first signal transmission line 120 is located in the gate metal layer Gate; the second connecting line 140 is located in the source-drain metal layer SD; and the second transfer electrode 130 is located in the transparent conductive layer TL.

[0242] Figure 25 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source-drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in another optional embodiment of the present disclosure; Figure 26 shows a plan schematic diagram of the gate metal layer in Figure 25; Figure 27 shows a plan schematic diagram of the semiconductor layer in Figure 25; Figure 28 shows a plan schematic diagram of the source-drain metal layer in Figure 25; Figure 29 shows a plan schematic diagram of the insulating layer in Figure 25; and Figure 30 shows a plan schematic diagram of the transparent conductive layer TL in Figure 25.

[0243] In some optional embodiments, referring to Figures 25 to 29, the shift register GOA further includes a second capacitor C2, and the second capacitor C2 includes a first sub-capacitor C2A, a second sub-capacitor C2B, and a third sub-capacitor C2C, wherein the first sub-capacitor C2A, the second sub-capacitor C2B, and the third sub-capacitor C2C are connected in series to form the second capacitor C2 to ensure the capacitance of the second capacitor C2.

[0244] As shown in Figures 26 and 28, the first sub-capacitor C2A includes a first sub-plate 181 and a second sub-plate 182 arranged opposite each other; the second sub-capacitor C2B includes a third sub-plate 183 and a fourth sub-plate 184 arranged opposite each other; and the third sub-capacitor C2C includes a fifth sub-plate 185 and a sixth sub-plate 186 arranged opposite each other. The second sub-plate 182, the fourth sub-plate 184, and the fifth sub-plate 185 are electrically connected, and the first sub-plate 181, the third sub-plate 183, and the sixth sub-plate 186 are electrically connected. This arrangement connects the first sub-capacitor C2A, the second sub-capacitor C2B, and the third sub-capacitor C2C in series, which avoids increasing the frame, improves the utilization of the substrate space, and achieves a narrow frame.

[0245] In the specific embodiment shown in Figure 26, the first sub-plate 181, the third sub-plate 183, the fifth sub-plate 185, and the first electrode plate 41 are arranged in the same layer. Compared to the embodiment shown in Figure 20, the first sub-plate 181 in Figure 26 is located between the control electrode M6_g of the sixth transistor M6 and the signal transmission line, while the second sub-plate 182 is located on the side of the first signal transmission line 120 away from the sixth transistor M6 to improve space utilization. The first sub-plate 181, the first electrode plate 41, and the control electrode M6_g of the sixth transistor M6 form an integrated structure, connecting the first capacitor C1 and the second capacitor C2 together.

[0246] In the specific embodiment shown in FIG. 28 , the second sub-plate 182 , the fourth sub-plate 184 and the sixth sub-plate 186 are arranged in the same layer.

[0247] In the specific embodiments shown in Figures 26 to 30, the shift register GOA further includes a second transfer electrode 130, a second sub-plate 182, and a fourth sub-plate 184 connected to the second transfer electrode 130 via a third via 150, and a fifth sub-plate 185 connected to the second transfer electrode 130 via a fourth via 160. The second sub-plate 182 and the fourth sub-plate 184 are integrally formed and connected to the fifth sub-plate 185 via the second transfer electrode 130. Furthermore, the second sub-plate 182 and the fourth sub-plate 184 span multiple signal transmission lines, thereby increasing the capacitance of the second capacitor C2 without increasing the frame width, thereby improving space utilization.

[0248] In the specific embodiment shown in Figure 26, the display substrate also includes a first signal transmission line 120. The first signal transmission line 120 of the (NM / 2)-th level shift register GOA is connected to the first signal input terminal Input of the N-th level shift register GOA. Part of the first signal transmission line 120 serves as the fifth sub-plate 185. The third sub-capacitor C2C uses a part of the first signal transmission line 120 as the electrode plate of the second sub-capacitor C2C, thereby increasing the capacitance of the second capacitor C2 without increasing the border width, thereby improving space utilization.

[0249] Specifically, referring to Figure 28 , the sixth sub-plate 186 includes a first extension 187 and a second extension 188. The first extension 187 and the second extension 188 are cross-connected. The first extension 187 is parallel to the first signal transmission line 120, and the ends of the second extension 188 are electrically connected to the first sub-plate 181 and the third sub-plate 183, respectively. The first extension 187 is parallel to the first signal transmission line 120. In other words, the orthographic projection of the first extension 187 on the gate metal layer Gate overlaps with a portion of the first signal transmission line 120, serving as the third sub-capacitor C2C. The provision of the first extension 187 increases the capacitance of the second capacitor C2.

[0250] As shown in FIG28 , the shift register GOA further includes a first transfer electrode 80 and a first connecting line 90. A portion of the first connecting line 90 serves as a second extension portion 188. The first transfer electrode 80 is connected to the second extension portion 188 via a first via 100, and the first transfer electrode 80 is connected to the second extension portion 188 via a second via 110. By using the first connecting line 90 as the second extension portion 188, a separate second extension portion 188 is no longer required, thereby improving space utilization on the display substrate.

[0251] Figure 31 shows a schematic diagram of the superposition of the gate metal layer, semiconductor layer, source-drain metal layer, insulating layer, and transparent conductive layer TL of a display substrate in another optional embodiment of the present disclosure; Figure 32 shows a plan schematic diagram of the gate metal layer in Figure 31; Figure 33 shows a plan schematic diagram of the semiconductor layer in Figure 31; Figure 34 shows a plan schematic diagram of the source-drain metal layer in Figure 31; Figure 35 shows a plan schematic diagram of the insulating layer in Figure 31; and Figure 36 shows a plan schematic diagram of the transparent conductive layer TL in Figure 31.

[0252] In the specific embodiments shown in Figures 31 to 36, the shift register GOA further includes a second capacitor C2. The orthographic projection of the second capacitor C2 on the substrate is located between the orthographic projection of the first capacitor C1 on the substrate and the orthographic projection of the sixth transistor M6 on the substrate. The second capacitor C2 includes a third electrode plate 191 and a fourth electrode plate 192. The third electrode plate 191 and the first electrode plate 41 are integrally structured, and the second electrode plate 42 and the fourth electrode plate 192 are provided on the same layer. This arrangement increases the second capacitor C2 without increasing the width of the frame, thereby improving the utilization of the frame.

[0253] In the specific embodiment shown in Figure 36, the first capacitor C1 also includes a fifth electrode plate 43, which is located on a side of the second electrode plate 42 away from the first electrode plate 41, and is electrically connected to the first electrode plate 41. The first capacitor C1 is a series capacitor, that is, a sub-capacitor is formed between the first electrode plate 41 and the second electrode plate 42, and a sub-capacitor is formed between the second electrode plate 42 and the fifth electrode plate 43. The two sub-capacitors are connected in series to form the first capacitor C1. While ensuring the capacitance of the first capacitor C1, the area of ​​the orthographic projection of the first capacitor C1 on the substrate is reduced, thereby improving space utilization.

[0254] In the specific embodiment shown in FIG36 , the second capacitor C2 further includes a sixth electrode plate 193, which is located on a side of the fourth electrode plate 192 away from the third electrode plate 191. The sixth electrode plate 193 is electrically connected to the third electrode plate 191, and the fifth electrode plate 43 and the sixth electrode plate 193 are disposed on the same layer. The second capacitor C2 is a series capacitor, that is, a sub-capacitor is formed between the third electrode plate 191 and the fourth electrode plate 192, and a sub-capacitor is formed between the fourth electrode plate 192 and the sixth electrode plate 193. The two sub-capacitors are connected in series to form the second capacitor C2, reducing the area of ​​the orthographic projection of the second capacitor C2 on the substrate, improving space utilization, and increasing the capacitance of the second capacitor C2.

[0255] In the specific embodiment shown in FIG31 , the shift register GOA further includes a first transfer electrode 80, which is connected to the first electrode plate 41 via a second via 110. The first transfer electrode 80 forms an integral structure with the fifth electrode plate 43 and the sixth electrode plate 193. The first electrode plate 41 and the third electrode plate 191 form an integral structure, and the first electrode plate 41 and the fifth electrode plate 43 are electrically connected via the first transfer electrode 80, thereby increasing the capacitance of the first capacitor C1. The third electrode plate 191 and the sixth electrode plate 193 are electrically connected via the first transfer electrode 80, thereby increasing the capacitance of the second capacitor C2.

[0256] As shown in Figure 33, the active layer M5_a of the fifth transistor M5 and the active layer M6_a of the sixth transistor M6, the active layer M5_a of the fifth transistor M5 includes a first active area M5_a1 and a second active area M5_a2, the first active area M5_a1 and the second active area M5_a2 are arranged at intervals along the second direction Y, and the first capacitor C1 and the first active area M5_a1 are arranged at intervals along the first direction X; the active layer M6_a and the second active area M5_a2 of the sixth transistor M6 are arranged at intervals along the first direction X, the first capacitor C1 and the active layer M6_a of the sixth transistor M6 are arranged at intervals along the second direction Y, and the first direction X intersects the second direction Y.

[0257] The display substrate also includes a third connecting line 270, which is used to connect other signal transmission lines and other transistors. The third connecting line 270 is parallel to the first connecting line 90 and is arranged at intervals. The first connecting line 90 and the third connecting line 270 are arranged along the second direction Y, and the first connecting line 90 is located between the second connecting line 140 and the third connecting line 270.

[0258] It should be noted that the first via hole 100 , the second via hole 110 , the third via hole 150 , the fourth via hole 160 , the fifth via hole 250 , and the sixth via hole 260 are located in the insulating layer PVX.

[0259] In some optional embodiments, the display substrate has a display area and a non-display area, the gate drive circuit is located in the non-display area, and the display substrate further includes a transparent electrode located in the display area, the transparent electrode being disposed in the same layer as the first transfer electrode 80. The transparent electrode can be a pixel electrode or a common electrode, which is not specifically limited herein.

[0260] The present disclosure also provides a display device, including the above-mentioned display substrate. The display device may include any device or product having a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, an electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0261] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A gate drive circuit, wherein: include: Multiple cascaded shift registers and M clock signal lines connected to the multiple shift registers, each shift register comprising an input subcircuit, an output control subcircuit, and a noise reduction control subcircuit, wherein the input subcircuit and the output control subcircuit are connected to a pull-up node, and the noise reduction control subcircuit and the output control subcircuit are connected to a first node; the input subcircuit is configured to charge the pull-up node under the control of a first input signal terminal; the output control subcircuit is configured to output a signal on the clock signal line to a signal output terminal under the control of the potential of the pull-up node, and to output a second operating voltage to the signal output terminal under the control of the potential of the first node; the noise reduction control subcircuit is configured to pull down the potential of the first node under the control of a second input signal terminal; wherein the first node includes a pull-down node and / or a pull-down control node, and M is an even number greater than or equal to 4; The first signal input terminals of the shift registers of the 1st to M / 2nd stages are connected to their respective corresponding first start signal terminals. Except for the shift registers of the 1st to M / 2nd stages, the first signal input terminal of the shift register of the Nth stage is connected to the signal output terminal of the shift register of the (NM / 2)th stage. The second signal input terminals of the shift registers of stages 1 to M / 2+P are connected to their respective corresponding second start signal terminals. Except for the shift registers of stages 1 to M / 2+P, the second signal input terminal of the shift register of stage N is connected to the signal output terminal of the shift register of stage (NM / 2-P), where P is a positive integer greater than 0 and less than or equal to M / 2, and N is a positive integer greater than M / 2+P. Alternatively, the second signal input terminals of the shift registers of the 1st to M / 2-Jth levels are connected to their respective corresponding second start signal terminals, and in addition to the shift registers of the 1st to M / 2-J levels, the second signal input terminal of the shift register of the Nth level is connected to the pull-up output terminal of the shift register of the (NM / 2+J)th level, and the pull-up output terminal is connected to the pull-up node, where J is a positive integer greater than 0 and less than M / 2.

2. The gate drive circuit according to claim 1, wherein: The input sub-circuit is further configured to pull down the potential of the pull-up node under the control of the first reset signal input terminal, Except for the shift register of the last M / 2+1 levels, the first reset signal input terminal of the shift register of the Nth level is connected to the signal output terminal of the shift register of the N+M / 2+1th level, and the first reset signal input terminal of the shift register of the last M / 2+1 levels is connected to the respective corresponding first reset signal terminals.

3. The gate drive circuit according to claim 1 or 2, wherein: The pull-down node includes a first pull-down node and a second pull-down node, and the noise reduction control subcircuit includes: a first transistor, wherein a control electrode of the first transistor is connected to the second signal input terminal, a first electrode of the first transistor is connected to the first pull-down node, and a second electrode of the first transistor is connected to the second power supply terminal; A second transistor, wherein a control electrode of the second transistor is connected to the second signal input terminal, a first electrode of the second transistor is connected to the second pull-down node, and a second electrode of the second transistor is connected to the second power supply terminal.

4. The gate drive circuit according to any one of claims 1 to 3, wherein: The pull-down control node includes a first pull-down control node and a second pull-down control node, and the noise reduction control subcircuit includes: a third transistor, wherein a control electrode of the third transistor is connected to the second signal input terminal, a first electrode of the third transistor is connected to the first pull-down control node, and a second electrode of the third transistor is connected to the second power supply terminal; a fourth transistor, wherein a control electrode of the fourth transistor is connected to the second signal input terminal, a first electrode of the fourth transistor is connected to the second pull-down control node, and a second electrode of the fourth transistor is connected to the second power supply terminal.

5. The gate drive circuit according to any one of claims 1 to 4, wherein: The output control subcircuit includes: a pull-up module, a first pull-down control module and a first pull-down module, the first pull-down control module and the first pull-down module are connected to a first pull-down node, and the signal output end includes a first signal output end and a second signal output end; The pull-up module, the pull-up node, the clock signal input terminal, the first signal output terminal, The clock signal input terminal is connected to the second signal output terminal, and is responsive to the control of the potential of the pull-up node, and is used to input the clock signal provided by the clock signal input terminal to the first signal output terminal and the second signal output terminal when the potential of the pull-up node is in an effective level state; The first pull-down control module is connected to the pull-up node, the first pull-down node, a second power supply terminal, and a third power supply terminal, and is responsive to control of the potential of the pull-up node to input a second operating voltage provided by the second power supply terminal to the first pull-down node when the potential of the pull-up node is in a valid level state, and to input a third operating voltage provided by the third power supply terminal to the first pull-down node when the potential of the pull-up node is in a non-valid level state; The first pull-down module is connected to the first pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal and the fifth power supply terminal, and responds to the control of the potential of the first pull-down node. It is used to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and input the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the first pull-down node is in a valid level state.

6. The gate driving circuit according to claim 5, wherein: The pull-up module includes a fifth transistor, a sixth transistor and a first capacitor. The control electrodes of the fifth transistor and the sixth transistor are connected to the pull-up node, the first electrodes of the fifth transistor and the sixth transistor are connected to the clock signal input terminal, the second electrode of the fifth transistor is connected to the first signal output terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal; A first end of the first capacitor is connected to the pull-up node, and a second end of the first capacitor is connected to the first signal output end.

7. The gate driving circuit according to claim 5, wherein: The clock signal input terminal includes a first clock signal input terminal and a second clock signal input terminal, and the pull-up module includes a fifth transistor, a sixth transistor, a first capacitor and a second capacitor. The control electrode of the fifth transistor is connected to the pull-up node, the first electrode of the fifth transistor is connected to the first clock signal input terminal, and the second electrode of the fifth transistor is connected to the first signal input terminal. Output terminal connection; The control electrode of the sixth transistor is connected to the pull-up node, the first electrode of the sixth transistor is connected to the second clock signal input terminal, and the second electrode of the sixth transistor is connected to the second signal output terminal; A first end of the first capacitor is connected to the pull-up node, and a second end of the first capacitor is connected to the first signal output end; A first end of the second capacitor is connected to the pull-up node, and a second end of the second capacitor is connected to the second signal output end.

8. The gate drive circuit according to any one of claims 5 to 7, wherein: The first pull-down control module includes: a seventh transistor, an eighth transistor, a ninth transistor and a tenth transistor; The control electrode of the seventh transistor is connected to the third power supply terminal, the first electrode of the seventh transistor is connected to the third power supply terminal, and the second electrode of the seventh transistor is connected to the first pull-down control node; The control electrode of the eighth transistor is connected to the first pull-down control node, the first electrode of the eighth transistor is connected to the third power supply terminal, and the second electrode of the eighth transistor is connected to the first pull-down node; The control electrode of the ninth transistor is connected to the pull-up node, the first electrode of the ninth transistor is connected to the first pull-down control node, and the second electrode of the ninth transistor is connected to the second power supply terminal; The control electrode of the tenth transistor is connected to the pull-up node, the first electrode of the tenth transistor is connected to the first pull-down node, and the second electrode of the tenth transistor is connected to the second power supply terminal; The first pull-down module includes: an eleventh transistor and a twelfth transistor; The control electrode of the eleventh transistor is connected to the first pull-down node, the first electrode of the eleventh transistor is connected to the first signal output terminal, and the second electrode of the eleventh transistor is connected to the A fifth power supply terminal is connected; The control electrode of the twelfth transistor is connected to the first pull-down node, the first electrode of the twelfth transistor is connected to the second signal output end, and the second electrode of the twelfth transistor is connected to the second power supply end.

9. The gate drive circuit according to any one of claims 5 to 8, wherein: The output control subcircuit further includes a second pull-down module and a second pull-down control module, wherein the second pull-down control module and the second pull-down module are connected to a second pull-down node; The second pull-down control module is connected to the pull-up node, the second pull-down node, the second power supply terminal, and the fourth power supply terminal, and is responsive to the control of the potential of the pull-up node to input the second operating voltage provided by the second power supply terminal to the second pull-down node when the potential of the pull-up node is in a valid level state, and to input the fourth operating voltage provided by the fourth power supply terminal to the second pull-down node when the potential of the pull-up node is in a non-valid level state; The second pull-down module is connected to the second pull-down node, the first signal output terminal, the second signal output terminal, the second power supply terminal, and the fifth power supply terminal, and is responsive to the control of the potential of the second pull-down node and configured to input the second operating voltage provided by the second power supply terminal to the second signal output terminal and the fifth operating voltage provided by the fifth power supply terminal to the first signal output terminal when the potential of the second pull-down node is in an effective level state; The third operating voltage switches between an effective level state and an ineffective level state, and the fourth operating voltage switches between an effective level state and an ineffective level state; At any time, one of the third operating voltage and the fourth operating voltage is in an effective level state, and the other is in an ineffective level state.

10. The gate driving circuit according to claim 9, wherein: The second pull-down control module includes: a thirteenth transistor, a fourteenth transistor, a fifteenth transistor and a sixteenth transistor; The control electrode of the thirteenth transistor is connected to the fourth power supply terminal, the first electrode of the thirteenth transistor is connected to the fourth power supply terminal, and the second electrode of the thirteenth transistor is connected to the second pull-down control electrode. Control node connection; The control electrode of the fourteenth transistor is connected to the second pull-down control node, the first electrode of the fourteenth transistor is connected to the fourth power supply terminal, and the second electrode of the fourteenth transistor is connected to the second pull-down node; The control electrode of the fifteenth transistor is connected to the pull-up node, the first electrode of the fifteenth transistor is connected to the second pull-down control node, and the second electrode of the fifteenth transistor is connected to the second power supply terminal; The control electrode of the sixteenth transistor is connected to the pull-up node, the first electrode of the sixteenth transistor is connected to the second pull-down node, and the second electrode of the sixteenth transistor is connected to the second power supply terminal; The second pull-down module includes: a seventeenth transistor and an eighteenth transistor; The control electrode of the seventeenth transistor is connected to the second pull-down node, the first electrode of the seventeenth transistor is connected to the first signal output terminal, and the second electrode of the seventeenth transistor is connected to the fifth power supply terminal; The control electrode of the eighteenth transistor is connected to the second pull-down node, the first electrode of the eighteenth transistor is connected to the second signal output end, and the second electrode of the eighteenth transistor is connected to the second power supply end.

11. The gate driving circuit according to claim 9, wherein: The output control subcircuit further includes a first noise reduction module and a second noise reduction module. The first noise reduction module is connected to the pull-up node, the first pull-down node, and the second power supply terminal, and is responsive to the control of the potential of the first pull-down node and configured to input the second operating voltage provided by the second power supply terminal to the pull-up node when the potential of the first pull-down node is in a valid level state; The second noise reduction module is connected to the pull-up node, the second pull-down node and the second power supply terminal, and is used to output the second working voltage provided by the second power supply terminal to the output terminal in response to the control of the potential of the second pull-down node when the potential of the second pull-down node is in an effective level state. into the pull-up node.

12. The gate driving circuit according to claim 11, wherein: The first noise reduction module includes a nineteenth transistor, wherein a control electrode of the nineteenth transistor is connected to the first pull-down node, a first electrode of the nineteenth transistor is connected to the pull-up node, and a second electrode of the nineteenth transistor is connected to the second power supply terminal; The second noise reduction module includes a twentieth transistor, wherein the control electrode of the twentieth transistor is connected to the second pull-down node, the first electrode of the twentieth transistor is connected to the pull-up node, and the second electrode of the twentieth transistor is connected to the second power supply terminal.

13. The gate drive circuit according to any one of claims 1 to 12, wherein: The input subcircuit includes: a signal input module, a first reset module and a second reset module; The signal input module is connected to the pull-up node, the first signal input terminal and the first power supply terminal, and is responsive to voltage control of the first signal input terminal, and is configured to input a first operating voltage provided by the first power supply terminal to the pull-up node when a first input signal provided by the first signal input terminal is in a valid level state; The first reset module is connected to the pull-up node, the first reset signal input terminal, and the second power supply terminal, and is responsive to voltage control of the first reset signal input terminal and configured to input a second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the first reset signal input terminal is in a valid level state; The second reset module is connected to the pull-up node, the second reset signal input terminal and the second power supply terminal, and is responsive to the voltage control of the second reset signal input terminal and is configured to input the second operating voltage provided by the second power supply terminal to the pull-up node when the signal provided by the second reset signal input terminal is in a valid level state.

14. The gate driving circuit according to claim 13, wherein: The signal input module includes a twenty-first transistor, wherein a control electrode of the twenty-first transistor is connected to the first signal input terminal, a first electrode of the twenty-first transistor is connected to the first power supply terminal, and a second electrode of the twenty-first transistor is connected to the pull-up node; The first reset module includes a twenty-second transistor, a control electrode of the twenty-second transistor is connected to the first reset signal input terminal, a first electrode of the twenty-second transistor is connected to the pull-up node, and a second electrode of the twenty-second transistor is connected to the second power supply terminal; The second reset module includes a twenty-third transistor, a control electrode of the twenty-third transistor is connected to the second reset signal input terminal, a first electrode of the twenty-third transistor is connected to the pull-up node, and a second electrode of the twenty-third transistor is connected to the second power supply terminal.

15. A display substrate, wherein: The gate driving circuit comprises a base substrate and the gate driving circuit according to any one of claims 1 to 14, wherein the gate driving circuit is arranged on the base substrate.

16. The display substrate according to claim 15, wherein: The shift register in the gate drive circuit includes: a fifth transistor; a sixth transistor, wherein the fifth transistor and the sixth transistor are arranged at intervals along the first direction; a first capacitor, wherein the first capacitor and the sixth transistor are located on the same side of the fifth transistor and are arranged at intervals along a second direction, the first direction intersects the second direction, the first capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other, the second electrode plate is located on a side of the first electrode plate away from the substrate, and the first electrode plate is connected to the control electrode of the fifth transistor and the control electrode of the sixth transistor.

17. The display substrate according to claim 16, wherein: The display substrate includes a gate metal layer, a semiconductor layer, and a source / drain metal layer sequentially arranged in a direction away from the base substrate, wherein: The control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are all located in the gate metal layer, and at least a portion of the control electrode of the fifth transistor, the control electrode of the sixth transistor, and the first electrode plate are an integrated structure. The first electrode of the fifth transistor, the second electrode of the fifth transistor, the first electrode of the sixth transistor, the second electrode of the sixth transistor, and the second electrode plate of the first capacitor are all located in the source-drain metal layer.

18. The display substrate according to claim 16, wherein: The shift register also includes a first transfer electrode and a first connecting line. The first connecting line of the (NM / 2+J)th level shift register is electrically connected to the second signal input end of the Nth level shift register. The first transfer electrode is connected to the first connecting line through a first via, and the first transfer electrode is connected to the first electrode plate through a second via.

19. The display substrate according to claim 18, wherein: The display substrate also includes a first signal transmission line extending along the second direction, the first signal transmission line of the (NM / 2)th level shift register is connected to the first signal input end of the Nth level shift register, and the orthographic projection of the first connecting line on the base substrate is arranged to intersect with the orthographic projection of the first signal transmission line on the base substrate.

20. The display substrate according to claim 18, wherein The shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially arranged in a direction away from the substrate, wherein: The first electrode plate is located in the gate metal layer; The first connecting line is located in the source-drain metal layer; The first switching electrode is located in the transparent conductive layer.

21. The display substrate according to any one of claims 16 to 20, wherein: The display substrate also includes a first signal transmission line, and the shift register also includes a second transfer electrode and a second connecting line, one end of the second connecting line is connected to the second transfer electrode, and the other end of the second connecting line is connected to the second electrode of the sixth transistor, the second transfer electrode is connected to the second connecting line through a third via, and the second transfer electrode is connected to the first signal transmission line through a fourth via, and the first signal transmission line of the (NM / 2)th level shift register is connected to the first signal input end of the Nth level shift register.

22. The display substrate according to claim 21, wherein The first signal transmission line of the (NM / 2-P)th stage shift register is connected to the second signal input terminal of the Nth stage shift register.

23. The display substrate according to claim 21, wherein The shift register includes a gate metal layer, a semiconductor layer, a source / drain metal layer, and a transparent conductive layer sequentially arranged in a direction away from the substrate, wherein: The first signal transmission line is located in the gate metal layer; The second connecting line is located in the source-drain metal layer; The second switching electrode is located in the transparent conductive layer.

24. The display substrate according to any one of claims 16 to 23, wherein: The shift register further includes a second capacitor, and the second capacitor includes: The first sub-capacitor includes a first sub-plate and a second sub-plate that are arranged opposite to each other; The second sub-capacitor includes a third sub-plate and a fourth sub-plate that are arranged opposite to each other; a third sub-capacitor, comprising a fifth sub-plate and a sixth sub-plate arranged opposite to each other; The second sub-plate, the fourth sub-plate and the fifth sub-plate are electrically connected, the first sub-plate, the third sub-plate and the sixth sub-plate are electrically connected, and the first sub-plate, the third sub-plate, the fifth sub-plate and the first electrode plate are arranged on the same layer; The second sub-plate, the fourth sub-plate and the sixth sub-plate are arranged in the same layer.

25. The display substrate according to claim 24, wherein: The first sub-plate and the first electrode plate are an integrated structure.

26. The display substrate according to claim 24, wherein: The shift register further includes a second switching electrode. The second sub-plate and the fourth sub-plate are connected to the second switching electrode through a third via hole. The fifth sub-plate is connected to the second switching electrode through a fourth via hole.

27. The display substrate according to claim 26, wherein: The display substrate further includes a first signal transmission line, the first signal transmission line of the (NM / 2)th stage shift register is connected to the first signal input terminal of the Nth stage shift register, and a portion of the first signal transmission line serves as the fifth sub-plate.

28. The display substrate according to claim 27, wherein: The sixth sub-plate includes a first extension portion and a second extension portion, the first extension portion is cross-connected with the second extension portion, the first extension portion is parallel to the first signal transmission line, and both ends of the second extension portion are electrically connected to the first sub-plate and the third sub-plate respectively.

29. The display substrate according to claim 28, wherein: The shift register further includes a first switching electrode and a first connecting line, a portion of the first connecting line serves as the second extension portion, the first switching electrode is connected to the second extension portion through a first via hole, and the first switching electrode is connected to the first extension portion through a second via hole.

30. The display substrate according to any one of claims 16 to 23, wherein: The shift register also includes a second capacitor, the orthographic projection of the second capacitor on the substrate is located between the orthographic projection of the first capacitor on the substrate and the orthographic projection of the sixth transistor on the substrate, the second capacitor includes a third electrode plate and a fourth electrode plate, the third electrode plate and the first electrode plate are an integral structure, and the second electrode plate and the fourth electrode plate are arranged on the same layer.

31. The display substrate according to claim 30, wherein: The first capacitor further includes a fifth electrode plate, the fifth electrode plate being located on a side of the second electrode plate away from the first electrode plate, and the fifth electrode plate being electrically connected to the first electrode plate. The second capacitor further includes a sixth electrode plate, which is located on a side of the fourth electrode plate away from the third electrode plate and is electrically connected to the third electrode plate. The fifth electrode plate and the sixth electrode plate are arranged on the same layer.

32. The display substrate according to claim 31, wherein The shift register further includes a first switching electrode, which is connected to the first electrode plate through a second via hole. The first switching electrode, the fifth electrode plate, and the sixth electrode plate form an integrated structure.

33. The display substrate according to any one of claims 16 to 32, wherein: The active layer of the fifth transistor and the active layer of the sixth transistor, the active layer of the fifth transistor includes a first active area and a second active area, the first active area and the second active area are arranged in a second direction with an interval, The first capacitor and the first active area are arranged at intervals along a first direction; The active layer of the sixth transistor and the second active region are arranged at intervals along the first direction, The first capacitor and the active layer of the sixth transistor are arranged at intervals along a second direction, and the first direction intersects the second direction.

34. The display substrate according to claim 18, wherein The display substrate has a display area and a non-display area. The gate driving circuit is located in the non-display area. The display substrate further includes a transparent electrode located in the display area. The transparent electrode and the first switching electrode are arranged in the same layer.

35. A display device, wherein: A display substrate comprising the display substrate according to any one of claims 15 to 34.

Images