Storage chip and preparation method therefor, and electronic device

Abstract

The present application relates to the technical field of storage. Provided are a storage chip and a preparation method therefor, and an electronic device, which make the effective area of a first storage unit to be 4F2, thereby increasing the storage density of a first storage chain and increasing the number of first storage units in the first storage chain. The storage chip comprises a first storage chain, first bit line gating tubes, first board line gating tubes and a routing layer, which are stacked in sequence, wherein the routing layer comprises a first bit line and first board lines; the first storage chain comprises a plurality of first storage sub-chains connected in series, each first storage sub-chain comprising a plurality of first storage units connected in series, and the first storage sub-chains being connected in series between the first bit line gating tubes and the first board line gating tubes; the first bit line gating tubes are connected in series between the first bit line and the first storage sub-chains, and the plurality of first storage sub-chains are electrically connected to the same first bit line by means of the plurality of first bit line gating tubes; and the first board line gating tubes are connected in series between the first board lines and the first storage sub-chains, and the plurality of first board line gating tubes are electrically connected to the plurality of first board lines on a one-to-one basis.

Description

Memory chip and preparation method thereof, and electronic device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 21, 2024, with application number 202410331837.8 and application name “Memory chip and its preparation method, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of storage technology, and in particular to a storage chip and a preparation method thereof, and an electronic device. Background Art

[0003] With the rapid development of the chip industry, memory performance and storage density have gradually become important factors limiting chip performance. In today's context of large-capacity and high-bandwidth storage requirements, memory cells need to be continuously miniaturized and stacked to achieve high-density storage.

[0004] Currently, chain ferroelectric random access memory (FeRAM) is a very popular new storage technology. One of the major advantages of chain ferroelectric memory is that its storage unit occupies an area of ​​4F. 2 , which is 33% smaller than the area occupied by a 1T1C (one transistor and one capacitor) memory cell, thus enabling higher density.

[0005] However, due to the presence of bit line gate tubes and / or plate line gate tubes, the area occupied by the memory cell of the traditional ferroelectric chain FeRam is not strictly 4F. 2 Therefore, the storage density of traditional ferroelectric chain FeRam still has room for improvement. Summary of the Invention

[0006] In order to solve the above technical problems, the present application provides a memory chip and its preparation method, and an electronic device, which can avoid the first line gate tube and the first plate line gate tube occupying the area of ​​the memory chip on the plane, so that the effective area of ​​the first storage unit on the first storage chain becomes a standard 4F 2 , so as to improve the storage density of the first storage chain and also increase the number of first storage units in the first storage chain.

[0007] In a first aspect, the present application provides a memory chip, comprising a substrate, a first memory chain disposed on the substrate, a first bit line selection tube and a first plate line selection tube stacked on a side of the first memory chain facing away from the substrate, and a routing layer disposed on a side of the first bit line selection tube and the first plate line selection tube facing away from the substrate. The routing layer comprises a first bit line and a plurality of first plate lines. The first memory chain comprises a plurality of first sub-memory chains connected in series, each of the first sub-memory chains comprising a plurality of first storage cells connected in series, the first sub-memory chain being connected in series between the first bit line selection tube and the first plate line selection tube. The first bit line selection tube is connected in series between the first bit line and the first sub-memory chain, and the plurality of first sub-memory chains are electrically connected to the same first bit line via a plurality of first bit line selection tubes; the first plate line selection tube is connected in series between the first plate line and the first sub-memory chain, and the plurality of first plate line selection tubes are electrically connected to the plurality of first plate lines in a one-to-one correspondence.

[0008] In the present application, the first bit line gate tube and the first plate line gate tube are stacked with the first storage chain. In this way, the first bit line gate tube and the first plate line gate tube can be overlapped with the first storage chain. That is, the orthographic projection of the first bit line gate tube and the first plate line gate tube on the XY plane falls within the orthographic projection range of the layer where the first storage chain is located on the XY plane, thereby avoiding the first bit line gate tube and the first plate line gate tube occupying the area of ​​the memory chip on the XY plane, so that the effective area of ​​the first storage unit on the first storage chain becomes a standard 4F. 2 , to improve the storage density of the first storage chain. Furthermore, even if the storage array contains more first storage chains due to the limitation of the on-state current of the transistor in the first storage cell, the multiple first bit line gating tubes and the multiple first plate line gating tubes electrically connected to the multiple first storage chains can be stacked with the first storage chain in the Z direction, thereby improving the storage density of the storage array. Moreover, because all the first bit line gating tubes and all the first plate line gating tubes electrically connected to the first storage chain can be stacked with the first storage chain in the Z direction, the number of first storage cells in the first storage chain can be increased infinitely if the size of the memory chip allows, that is, the length of the first storage chain can be infinitely long. The Z direction is the direction from the first storage chain to the first bit line gating tube and the first plate line gating tube, and the XY plane is perpendicular to the Z direction.

[0009] In some possible implementations, the first plate line gate transistor and the first bit line gate transistor may be disposed on the same layer or on different layers. The case where the first plate line gate transistor and the first bit line gate transistor are disposed on different layers includes: the first plate line gate transistor is disposed between the substrate and the first bit line gate transistor; or the first bit line gate transistor is disposed between the substrate and the first plate line gate transistor.

[0010] Compared to the solution where the first plate line gate transistor and the first bit line gate transistor are arranged on different layers, the solution where the first plate line gate transistor and the first bit line gate transistor are arranged on the same layer allows the first plate line gate transistor and the first bit line gate transistor to be manufactured using the same semiconductor process, thereby simplifying the manufacturing process of the memory chip. Furthermore, when the first plate line gate transistor and the first bit line gate transistor are arranged on the same layer, the first plate line gate transistor and the first bit line gate transistor can be electrically connected to the first storage chain and the wiring layer, respectively.

[0011] In some possible implementations, the first memory chain is fabricated using a front-end process, while the first bit line gate transistor, the first plate line gate transistor, and the routing layer are fabricated using a back-end process. This avoids high-temperature processing during the fabrication of the first bit line gate transistor, the first plate line gate transistor, and the routing layer, which could affect the performance of the transistors in the first memory chain.

[0012] In some possible implementations, the first bit line selection transistor includes a first sub-bit line selection transistor and a second sub-bit line selection transistor, the first plate line selection transistor includes a first sub-plate line selection transistor and a second sub-plate line selection transistor, and the first sub-storage chain is connected in series between the first sub-bit line selection transistor and the first sub-plate line selection transistor. The first sub-storage chain includes at least three segmented storage chains connected in series, one segmented storage chain connected in series between the first sub-bit line selection transistor and the second sub-plate line selection transistor, one segmented storage chain connected in series between the first sub-plate line selection transistor and the second sub-bit line selection transistor, and the remaining segmented storage chains connected in series between the second sub-bit line selection transistor and the second sub-plate line selection transistor.

[0013] In this way, the selection of the first sub-storage chain or the segmented storage chain can be dynamically adjusted according to the service life of the first storage chain to ensure the performance of the first storage chain within the service life.

[0014] Taking into account that at the beginning of the life of the first storage chain (for example, the usage time of the first storage chain is less than the preset time), the on-state current of the transistor is high and the performance is good, therefore, the selected first sub-storage chain can be relatively long. In the read and write stages, the first sub-bit line selection tube and the first sub-plate line selection tube connected in series with the selected storage cell work, and the second sub-bit line selection tube and the second sub-plate line selection tube do not work, so that the first sub-storage chain where the first selected storage cell is located is all selected, but the other storage cells in the selected first sub-storage chain except the first selected storage cell do not read or write signals.

[0015] For example, a first sub-storage chain includes five segmented storage chains connected in series, each of which includes two first storage cells. If the usage time of the first storage chain is less than a preset time, then during the read / write phase, a first sub-bit line selection transistor electrically connected to the first first storage cell of the first sub-storage chain and a first sub-plate line selection transistor electrically connected to the tenth first storage cell of the first sub-storage chain are turned on, while the remaining second sub-bit line selection transistors and second sub-plate line selection transistors electrically connected to the first sub-storage chain are turned off.

[0016] As the usage time increases, the performance of the transistor gradually decays and the on-state current decreases. For example, when the usage time of the first storage chain is greater than or equal to the preset time, during the read and write phase, a segmented storage chain in a first sub-storage chain may be selected, and other segmented storage chains in the first sub-storage chain may not be selected.

[0017] For example, in the read and write phase, if the first / second first storage cell on the first sub-storage chain is the first selected storage cell, the first sub-bit line selection tube and the second sub-plate line selection tube connected in series with the first selected storage cell will work, and the other second sub-bit line selection tubes and the first sub-plate line selection tubes will be turned off; if one of the third to eighth first storage cells on the first sub-storage chain is the first selected storage cell, the second sub-bit line selection tube and the second sub-plate line selection tube connected in series with the first selected storage cell will work, and the other first sub-bit line selection tubes and the first sub-plate line selection tubes will be turned off; if the ninth / tenth first storage cell on the first sub-storage chain is the first selected storage cell, the second sub-bit line selection tube and the first sub-plate line selection tube connected in series with the first selected storage cell will work, and the other first sub-bit line selection tubes and the second sub-plate line selection tubes will be turned off.

[0018] In some possible implementations, the memory chip further includes a comparison circuit, the routing layer further includes a second bit line, and the input end of the comparison circuit is electrically connected to the second bit line and the first bit line, respectively. During a read phase, the first bit line is used to input a stored signal to the comparison circuit, and the second bit line is used to input a reference voltage to the comparison circuit; the comparison circuit is used to determine whether the stored signal is a digital signal 0 or a digital signal 1 based on the reference voltage.

[0019] On this basis, the comparison circuit can be manufactured through a back-end process. This avoids high-temperature processing during the manufacture of the comparison circuit, which could affect the performance of the transistors in the first storage chain. Furthermore, when the comparison circuit is manufactured through a back-end process, the comparison circuit and the first storage chain can be stacked in the Z direction. That is, the orthographic projection of the comparison circuit on the XY plane falls within the orthographic projection of the first storage chain on the XY plane, thereby preventing the comparison circuit from occupying the area of ​​the storage chip on the XY plane.

[0020] In some possible implementations, the memory chip further includes a second memory chain, a second bitline selector, and a second plateline selector, and the routing layer further includes multiple second platelines. The second bitline selector and the second plateline selector are stacked on a side of the routing layer facing away from the first memory chain, and the second memory chain is stacked on a side of the second bitline selector and the second plateline selector facing away from the first memory chain. This can further improve storage density.

[0021] The second storage chain includes a plurality of second sub-storage chains connected in series, each of which includes a plurality of second storage cells connected in series. The second sub-storage chains are connected in series between a second bit line selection transistor and a second plate line selection transistor. The second bit line selection transistor is connected in series between a first bit line and the second sub-storage chain, and the plurality of second sub-storage chains are electrically connected to the same first bit line via the plurality of second bit line selection transistors. The second plate line selection transistor is connected in series between a second plate line and the second sub-storage chain, and the plurality of second plate line selection transistors are electrically connected to the plurality of second plate lines in a one-to-one correspondence.

[0022] In some possible implementations, the memory chip further includes a third storage chain, a third bitline selection transistor, a third plate line selection transistor, a fourth storage chain, a fourth bitline selection transistor, and a fourth plate line selection transistor, and the routing layer further includes a second bitline, multiple third plate lines, and multiple fourth plate lines. The third storage chain is disposed on the same layer as the first storage chain, and includes multiple third sub-storage chains connected in series, each of which includes multiple third storage cells connected in series. The third bitline selection transistor and the third plate line selection transistor are disposed on the same layer as the first line selection transistor and the first plate line selection transistor, and the third sub-storage chain is connected in series between the third bitline selection transistor and the third plate line selection transistor. The fourth storage chain is disposed on the same layer as the second storage chain, and includes multiple fourth sub-storage chains connected in series, each of which includes multiple fourth storage cells connected in series. The fourth bitline selection transistor and the fourth plate line selection transistor are disposed on the same layer as the second bitline selection transistor and the second plate line selection transistor, and the fourth sub-storage chain is connected in series between the fourth bitline selection transistor and the fourth plate line selection transistor.

[0023] A third bitline selection transistor is connected in series between the second bitline and the third sub-storage chain, and multiple third sub-storage chains are electrically connected to the same second bitline via multiple third bitline selection transistors. A third plateline selection transistor is connected in series between the third plateline and the third sub-storage chain, and multiple third plateline selection transistors are electrically connected to multiple third platelines in a one-to-one correspondence. A fourth bitline selection transistor is connected in series between the second bitline and the fourth sub-storage chain, and multiple fourth sub-storage chains are electrically connected to the same second bitline via multiple fourth bitline selection transistors. A fourth plateline selection transistor is connected in series between the fourth plateline and the fourth sub-storage chain, and multiple fourth plateline selection transistors are electrically connected to multiple fourth platelines in a one-to-one correspondence. The first and second storage chains are stacked in the Z direction, and the third and fourth storage chains are stacked in the Z direction, thereby increasing storage density. Furthermore, in the XY plane, the first and third storage chains are arranged in an array, and the second and fourth storage chains are arranged in an array.

[0024] The operations of the first storage chain, the second storage chain, the third storage chain, and the fourth storage chain in the memory chip can be divided into the following three situations:

[0025] In the first scenario, the first memory cell in the first memory chain and the third memory cell in the third memory chain are used for reading and writing signals. For example, during a read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, which is used to input a first read signal to a comparator circuit via a first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit. Alternatively, during a read phase, the plurality of third memory cells in the third memory chain include a third selected memory cell, which is used to input a second read signal to the comparator circuit via a second bit line, and the first bit line is used to input a second reference voltage to the comparator circuit.

[0026] When the first bit line transmits the first read signal, the second bit line provides the first reference signal. When the second bit line provides the second read signal, the first bit line provides the second reference signal. In other words, the functions of the first and second bit lines can be interchanged to enable time-sharing signal reading using the first and second bit lines.

[0027] In the second scenario, the first storage cell in the first storage chain and the second storage cell in the second storage chain are used for reading and writing signals. For example, during the read phase, the multiple first storage cells in the first storage chain include a first selected storage cell, which is used to input a first read signal to the comparator circuit via a first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit. Alternatively, during the read phase, the multiple second storage cells in the second storage chain include a second selected storage cell, which is used to input a second read signal to the comparator circuit via a first bit line BL1, and the second bit line is used to input a second reference voltage to the comparator circuit.

[0028] The first bit line is electrically connected to the first storage chain and the second storage chain, respectively. When the first storage chain includes a first selected storage cell, the first bit line can be used to transmit a first read signal output by the first selected storage cell, and the second bit line is used to transmit a first reference voltage. When the second storage chain includes a second selected storage cell, the first bit line can be used to transmit a second read signal output by the second selected storage cell, and the second bit line is still used to transmit the first reference voltage.

[0029] Similar to the second case, the read and write signals of the third storage unit in the third storage chain and the fourth storage unit in the fourth storage chain may also be used, which will not be described in detail here.

[0030] In a third scenario, the second storage cell in the second storage chain and the fourth storage cell in the fourth storage chain are used for reading and writing signals. For example, during a read phase, the plurality of second storage cells in the second storage chain include a second selected storage cell, which is used to input a first read signal to a comparator circuit via a first bit line, and the second bit line is used to input a first reference voltage to the comparator circuit. Alternatively, during a read phase, the plurality of fourth storage cells in the fourth storage chain include a fourth selected storage cell, which is used to input a second read signal to the comparator circuit via a second bit line, and the first bit line is used to input a second reference voltage to the comparator circuit.

[0031] When the first bit line transmits the first read signal, the second bit line provides the first reference signal. When the second bit line provides the second read signal, the first bit line provides the second reference signal. In other words, the functions of the first and second bit lines can be interchanged to enable time-sharing signal reading using the first and second bit lines.

[0032] In some possible implementations, the first storage unit includes a transistor and a capacitor connected in parallel, and the memory chip further includes a word line, a first gate line, and a second gate line. The word line is electrically connected to the gate of the transistor, the first electrode of the transistor is electrically connected to the first plate line gate transistor, and the second electrode of the transistor is electrically connected to the first bit line gate transistor; the first gate line is electrically connected to the gate of the first bit line gate transistor, and the second gate line is electrically connected to the gate of the first plate line gate transistor.

[0033] The word line is used to transmit a signal to the gate of the transistor to control the transistor to be turned on or off; the first gate line is used to transmit a signal to the gate of the first bit line gate tube to control the first bit line gate tube to be turned on or off; the second gate line is used to transmit a signal to the gate of the second bit line gate tube to control the first plate line gate tube to be turned on or off.

[0034] In a second aspect, the present application provides an electronic device comprising a processor and the memory chip described in the first aspect, wherein the processor is used to read and write data to the memory chip.

[0035] The second aspect and any implementation of the second aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the second aspect and any implementation of the second aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here.

[0036] In a third aspect, the present application provides a method for preparing a memory chip, comprising: forming a first memory chain on a substrate, the first memory chain comprising a plurality of first sub-memory chains connected in series, the first sub-memory chain comprising a plurality of first memory units connected in series; forming a first bit line selection tube and a first plate line selection tube on the first memory chain, the first sub-memory chain being connected in series between the first bit line selection tube and the first plate line selection tube; forming a routing layer on the side of the first bit line selection tube and the first plate line selection tube facing away from the substrate, the routing layer comprising a first bit line and a plurality of first plate lines, the first bit line selection tube being connected in series between the first bit line and the first sub-memory chain, and the plurality of first sub-memory chains being electrically connected to the same first bit line through a plurality of first bit line selection tubes; a first plate line selection tube being connected in series between the first plate line and the first sub-memory chain, and the plurality of first plate line selection tubes being electrically connected to the plurality of first plate lines in a one-to-one correspondence.

[0037] In some possible implementations, the routing layer further includes multiple second plate lines. After the routing layer is formed on the side of the first bit line selection tube and the first plate line selection tube facing away from the substrate, the chip fabrication method further includes: forming a second bit line selection tube and a second plate line selection tube on the side of the multiple second plate lines facing away from the substrate; forming a second storage chain on the side of the second bit line selection tube and the second plate line selection tube facing away from the substrate; the second storage chain includes multiple second sub-storage chains connected in series, each of the second sub-storage chains including multiple second storage cells connected in series; the second sub-storage chains are connected in series between the second bit line selection tube and the second plate line selection tube; the second bit line selection tube is connected in series between the first bit line and the second sub-storage chain, and the multiple second sub-storage chains are electrically connected to the same first bit line via the multiple second bit line selection tubes; the second plate line selection tube is connected in series between the second plate line and the second sub-storage chain, and the multiple second plate line selection tubes are electrically connected to the multiple second plate lines in a one-to-one correspondence.

[0038] The third aspect and any implementation of the third aspect correspond to the first aspect and any implementation of the first aspect, respectively. The technical effects corresponding to the third aspect and any implementation of the third aspect can be referred to the technical effects corresponding to the first aspect and any implementation of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] FIG1 is an interaction diagram of various modules in a memory provided by an embodiment of the present application;

[0040] FIG2 is an arrangement diagram of multiple storage units provided in an embodiment of the present application;

[0041] FIG3a is a structural diagram of a memory chip provided in an embodiment of the present application;

[0042] FIG3 b is a structural diagram of a memory chip provided in an embodiment of the present application;

[0043] FIG3 c is a structural diagram of a memory chip provided in an embodiment of the present application;

[0044] FIG4 is a circuit connection diagram of various electronic devices on a memory chip provided in an embodiment of the present application;

[0045] FIG5 is a timing diagram of the operation of the circuit shown in FIG4 ;

[0046] FIG6 is a circuit connection diagram of various electronic devices on a memory chip provided in an embodiment of the present application;

[0047] FIG7 a is a schematic diagram showing that some first line gating transistors and some first plate line gating transistors are not working, provided by an embodiment of the present application;

[0048] FIG7 b is a schematic diagram showing the operation of the first bit line gate transistor and the first plate line gate transistor according to an embodiment of the present application;

[0049] FIG8 is a circuit connection diagram of various electronic devices on a memory chip provided in an embodiment of the present application;

[0050] FIG9 is a structural diagram of a memory chip provided in an embodiment of the present application;

[0051] FIG10 is a circuit connection diagram of various electronic devices on a memory chip provided in an embodiment of the present application;

[0052] FIG11 a shows a working state of a first bit line and a second bit line provided by an embodiment of the present application;

[0053] FIG11 b shows another working state of the first bit line and the second bit line provided by an embodiment of the present application;

[0054] FIG12 a shows another working state of the first bit line and the second bit line provided in an embodiment of the present application;

[0055] FIG12 b shows another working state of the first bit line and the second bit line provided in an embodiment of the present application;

[0056] FIG13a shows another working state of the first bit line and the second bit line provided in an embodiment of the present application;

[0057] FIG13 b shows another working state of the first bit line and the second bit line provided in an embodiment of the present application;

[0058] FIG14 is a flow chart of the preparation of a memory chip according to an embodiment of the present application;

[0059] FIG15a is a diagram showing the preparation process of a memory chip according to an embodiment of the present application;

[0060] FIG15 b is a diagram illustrating a manufacturing process of a memory chip according to an embodiment of the present application;

[0061] FIG16 is a diagram showing the preparation process of the memory chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0063] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0064] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0065] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0066] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0067] An embodiment of the present application provides an electronic device, which may be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, or other device containing a memory.

[0068] Consumer electronic products include mobile phones, tablet computers, laptops, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bracelets, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Home electronic products include smart door locks, TVs, smart speakers, refrigerators, sweeping robots, etc. Car-mounted electronic products include car navigation systems and car displays, etc. Financial terminal products include automated teller machines (ATMs) and self-service terminals, etc. Communication electronic products include servers, memories, radars, base stations, and other communication equipment that contain memory chips.

[0069] For ease of explanation, the following uses a mobile phone as an example electronic device. A mobile phone may include a processor and memory, as shown in Figure 1. The memory includes a memory array, a controller, a row decoder, a column decoder, and the like. The processor can send the address of a selected memory cell to the row decoder and column decoder via the controller. The row decoder and column decoder decode the received address, identify the memory cell in the memory array, and then perform read and write operations on the selected memory cell.

[0070] As mentioned in the background technology, in order to achieve high-density storage, the memory cell in the chain ferroelectric memory can reach 4F 2 That is, as shown in Figure 2, assuming that the pitch between adjacent memory cells is the same, the sum of the single side size of any memory cell and the pitch between the memory cell and its adjacent memory cells is 2F, then the area occupied by the memory cell is 4F. 2 .

[0071] The chain ferroelectric memory includes a memory chip, the memory chip includes a memory array, the memory array includes multiple memory chains, each memory chain includes multiple memory cells, a bit line selector (BLS) is electrically connected between the multiple memory cells on a memory chain and the bit line, and a plate line selector (PLS) is electrically connected between the multiple memory cells on a memory chain and the plate line. In addition, the bit line selector and / or plate line selector also occupy a portion of the area in the memory chip. For example, the area occupied by the bit line selector and the plate line selector ranges from 20nm*20nm to 300nm*300nm. Therefore, although the area occupied by the memory cell is 4F 2However, the effective area of ​​a storage unit on a storage chain is not the standard 4F 2 .

[0072] Furthermore, the number of memory cells connected in series in a memory chain is limited by the on-state current of the transistors in the memory cells. Generally, the number of memory cells cannot exceed 32. Therefore, the number of memory chains in a traditional memory array is not small, and the number of bit line gate transistors and plate line gate transistors also increases accordingly. Therefore, the storage density of traditional memory chains still has room for improvement. In this application, the on-state current of the transistor can range from 100nA to 1000uA, and the off-state leakage current of the transistor can range from 0.1fA to 1000pA.

[0073] Based on this, the embodiment of the present application provides a memory chip, which can be applied to chain memories such as chain ferroelectric memory and chain dynamic random access memory (DRAM). The embodiment of the present application avoids the bit line gating tube and plate line gating tube occupying the area of ​​the memory chip by making the memory chain and the bit line gating tube and the plate line gating tube on different layers of the memory chip.

[0074] The structure of the memory chip is described in detail below with reference to the accompanying drawings.

[0075] As shown in Figures 3a and 4, the memory chip includes a substrate 10, a first memory chain, a first bit line select transistor BLS1, a first plate line select transistor PLS1, and a wiring layer. The first memory chain includes multiple first sub-memory chains connected in series, each of which includes multiple first memory cells connected in series. The first memory cells include transistors and capacitors, and the wiring layer includes a first bit line BL1 and multiple first plate lines PL1.

[0076] For example, the first storage chain includes 100 first sub-storage chains connected in series, each of which includes 10 first storage cells connected in series. That is, the first storage chain includes 1000 first storage cells connected in series. Of course, the number of first storage cells included in the multiple first sub-storage chains may also vary, which will not be further described here.

[0077] Along the Z direction, the first memory chain, first bit line select transistor BLS1, first plate line select transistor PLS1, and routing layers are stacked in sequence. The first memory chain can be fabricated using a front-end process, while the first bit line select transistor BLS1, first plate line select transistor PLS1, and routing layers can be fabricated using a back-end process. This avoids high-temperature processing during the fabrication of the first bit line select transistor BLS1, first plate line select transistor PLS1, and routing layers, which could affect the performance of the transistors in the first memory chain.

[0078] Optionally, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 can be set in the same layer (in other words, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 are formed by the same semiconductor process), and the first bit line BL1 and multiple first plate lines PL1 can be set in the same routing layer (in other words, the first bit line BL1 and multiple first plate lines PL1 can be formed by the same semiconductor process).

[0079] For example, as shown in Figure 3a, the first storage chain includes a transistor and a capacitor, which includes a first electrode and a second electrode. The transistor is located in the metal 0 (M0) layer, the first electrode is located in the M1 layer, and the second electrode is located in the M2 layer. The first bit line select transistor BLS1 and the first plate line select transistor PLS1 are located in layers M3 to Mn, where n>3. The first bit line BL1 and multiple first plate lines PL1 are located in the M(n+1) layer.

[0080] Furthermore, an insulating layer is provided between the first electrode and the second electrode; a first dielectric layer should also be provided between the M2 layer and the M3 layer, and the first bit line selection tube BLS1 and the first plate line selection tube PLS1 can be connected in series with the first sub-storage chain through the first through hole in the first dielectric layer; a second dielectric layer is also provided between the Mn layer and the M(n+1) layer, and the first bit line BL1 can be electrically connected to multiple first plate line selection tubes PLS1 on the first storage chain through the second through hole in the second dielectric layer, and multiple first plate lines PL1 can be electrically connected one-to-one with multiple first plate line selection tubes PLS1 through the second through hole in the second dielectric layer.

[0081] Of course, in addition to being stacked in the M0 layer to the M(n+1) layer in the above-mentioned manner, the transistors and capacitors of the first storage chain, the first bit line selection tube BLS1 and the first plate line selection tube PLS1, the first bit line BL1 and the multiple first plate lines PL1 can also be stacked in other ways, and the embodiments of the present application are not limited to this.

[0082] For example, the previous description describes the co-layered arrangement of the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1, both located in the M3 to Mn layers. However, in other possible implementations, the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 can also be arranged in different layers. For example, as shown in FIG3b , the first bit line gate transistor BLS1 is arranged between the substrate 10 and the first plate line gate transistor PLS1; or, as shown in FIG3c , the first bit line gate transistor BLS1 is arranged between the substrate 10 and the first plate line gate transistor PLS1.

[0083] Compared to the scheme where the first plate line gate transistor PLS1 and the first bit line gate transistor BLS1 are arranged on different layers, the scheme where the first plate line gate transistor PLS1 and the first bit line gate transistor BLS1 are arranged on the same layer allows the first plate line gate transistor PLS1 and the first bit line gate transistor BLS1 to be manufactured using the same semiconductor process, thereby simplifying the manufacturing process of the memory chip. Furthermore, when the first plate line gate transistor PLS1 and the first bit line gate transistor BLS1 are arranged on the same layer, it is convenient for the first plate line gate transistor PLS1 and the first bit line gate transistor BLS1 to be electrically connected to the wiring of the first storage chain and the wiring layer, respectively.

[0084] In the present application, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 are stacked with the first storage chain. In this way, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 can be overlapped with the first storage chain, that is, the orthographic projection of the first bit line gate tube BLS1 and the first plate line gate tube PLS1 on the XY plane falls within the orthographic projection range of the layer where the first storage chain is located on the XY plane, thereby avoiding the first bit line gate tube BLS1 and the first plate line gate tube PLS1 occupying the area of ​​the memory chip on the XY plane, so that the effective area of ​​the first storage unit on the first storage chain becomes a standard 4F 2 , to improve the storage density of the first storage chain. Furthermore, even if the memory array includes more first storage chains due to the limitation of the on-state current of the transistors in the first storage cells, the multiple first bit line selection transistors BLS1 and the multiple first plate line selection transistors PLS1 electrically connected to the multiple first storage chains can be stacked with the first storage chains in the Z direction, thereby improving the storage density of the memory array. Moreover, because all the first bit line selection transistors and all the first plate line selection transistors electrically connected to the first storage chain can be stacked with the first storage chain in the Z direction, the number of first storage cells in the first storage chain can be increased indefinitely if the size of the memory chip allows, that is, the length of the first storage chain can be infinitely long.

[0085] The XY plane is perpendicular to the Z direction. The orthographic projection of the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 on the XY plane refers to the projection of the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 perpendicularly projected onto the XY plane along the Z direction. The orthographic projection of the layer of the first storage chain on the XY plane refers to the projection of the layer of the first storage chain perpendicularly projected onto the XY plane along the Z direction.

[0086] As shown in Figure 4, the first sub-memory chain is connected in series between the first bit line select transistor BLS1 and the first plate line select transistor PLS1. Furthermore, the first bit line select transistor BLS1 is connected in series between the first bit line BL1 and the first sub-memory chain, and multiple first sub-memory chains are electrically connected to the same first bit line BL1 via multiple first bit line select transistors BLS1. A first plate line select transistor PLS1 is connected in series between the first plate line PL1 and the first sub-memory chain, and multiple first plate line select transistors PLS1 are electrically connected to multiple first plate lines PL1 in a one-to-one correspondence. In other words, different first plate line select transistors PLS1 are electrically connected to different first plate lines PL1.

[0087] The transistor in the first storage unit, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 all include a gate, a first electrode, and a second electrode. The first electrode is a source electrode and the second electrode is a drain electrode; or, the first electrode is a drain electrode and the second electrode is a source electrode. The materials of the gate electrode, the first electrode, and the second electrode include but are not limited to at least one of tungsten (W), titanium nitride (TiN), and molybdenum (Mo). In addition, the transistor in the first storage unit, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 also include a channel layer and a gate dielectric layer. The materials of the channel layer include but are not limited to single crystal silicon / germanium, polycrystalline silicon / germanium, oxide semiconductors (IGZO, IWO, etc.), organic semiconductors (pentacene, P3HT, etc.), two-dimensional material semiconductors (MoS2, WSe2, etc.), one-dimensional semiconductors (CNT, etc.), etc. The materials of the gate dielectric layer include but are not limited to SiO2, SiN x , high-k dielectric materials (HfO2, ZrO2, etc.). The first sub-storage chain is connected in series between the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1. This means that the first sub-storage chain is electrically connected to the second electrode of the first bit line gate transistor BLS1 and the first electrode of the first plate line gate transistor PLS1, respectively.

[0088] The first bit line selection transistor BLS1 is connected in series between the first bit line BL1 and the first sub-storage chain, which means that the first electrode of the first bit line selection transistor BLS1 is electrically connected to the first bit line BL1, and the second electrode of the first bit line selection transistor BLS1 is electrically connected to the first sub-storage chain.

[0089] The first plate line selection transistor PLS1 is connected in series between the first plate line PL1 and the first sub-storage chain, which means that: the first electrode of the first plate line selection transistor PLS1 is electrically connected to the first sub-storage chain, and the second electrode of the first plate line selection transistor PLS1 is electrically connected to the first plate line PL1.

[0090] In some possible implementations, the embodiments of the present application do not limit the connection method between the transistor and the capacitor in the first storage unit.

[0091] Optionally, as shown in FIG4 , in the first storage cell, a transistor may be connected in parallel with a capacitor, that is, a first electrode of the capacitor is electrically connected to a first electrode of the transistor, and a second electrode of the capacitor is electrically connected to a second electrode of the transistor. Furthermore, the first electrode of the transistor and the first electrode of the capacitor are electrically connected to a first electrode of the first plate line select transistor PLS1, and the second electrode of the transistor and the second electrode of the capacitor are electrically connected to a second electrode of the first bit line select transistor BLS1.

[0092] Therefore, the first plate line PL1, the second electrode of the first plate line gate tube PLS1, the first electrode of the first plate line gate tube PLS1, the first electrode of the transistor / the first electrode of the capacitor, the second electrode of the transistor / the second electrode of the capacitor, the second electrode of the first bit line gate tube BLS1, the first electrode of the first bit line gate tube BLS1, and the first bit line BL1 form a path.

[0093] Optionally, in the first storage unit, the transistor may be connected in series with the capacitor, that is, the first electrode of the capacitor is electrically connected to the first electrode of the transistor.

[0094] Optionally, in the first storage unit, the first electrode of the capacitor is electrically connected to the gate of the transistor.

[0095] The following describes the reading and writing principles of the storage cells on the first storage chain by taking the transistor and capacitor shown in FIG4 as examples, in which the transistor, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 in the first storage cell are all N-type transistors.

[0096] As shown in FIG4 , based on the above description, the memory chip may further include a plurality of word lines WL, a plurality of first gate lines (gate line 1, GL1), and a plurality of second gate lines GL2. The plurality of word lines WL, the plurality of first gate lines GL1, and the plurality of second gate lines GL2 may be arranged in the same layer as the first bit line BL1 and the first plate line PL1. The plurality of word lines WL are electrically connected in a one-to-one correspondence with the gates of the transistors in the plurality of first memory cells to control whether the transistors are turned on or off; the plurality of first gate lines GL1 are electrically connected in a one-to-one correspondence with the plurality of first bit line selection transistors BLS1 to control whether the first bit line selection transistors BLS1 are turned on or off; and the plurality of second gate lines GL2 are electrically connected in a one-to-one correspondence with the gates of the plurality of first plate line selection transistors PLS1 to control whether the first plate line selection transistors PLS1 are turned on or off.

[0097] As shown in Figure 5, in the standby stage, the first bit line BL1 and multiple first plate lines PL1 are all at a low level (for example, 0V); multiple first gate lines GL1 and multiple second gate lines GL2 are all at a low level (for example, 0V), the first bit line selection tube BLS1 and the first plate line selection tube PLS1 are both turned off, the first bit line BL1 cannot transmit signals to the first storage chain through the first bit line selection tube BLS1, and the first plate line PL1 cannot transmit signals to the first storage chain through the first plate line selection tube PLS1; multiple word lines WL are all at a high level, and the transistors in multiple first storage cells are turned on.

[0098] Next, as shown in FIG5 , in the pre-charge phase, multiple word lines WL are controlled to remain at a high level, and the transistors in multiple first memory cells are turned on. The first selected memory cell is connected in series to a first bit line gate transistor BLS1 and a first plate line gate transistor PLS1. The first gate line GL1 electrically connected to the first bit line gate transistor BLS1 and the second gate line GL2 electrically connected to the first plate line gate transistor PLS1 are controlled to become high levels, so that the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 are turned on. In this way, the first bit line BL1 and the first plate line PL1 electrically connected to the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 can be electrically connected to the first sub-memory chain where the first selected memory cell is located through the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1, so that the first sub-memory chain where the first selected memory cell is located is selected. However, the first bit line selection tube BLS1 and the first plate line selection tube PLS1 connected in series with other first sub-storage chains in the first storage chain are both turned off, and the other first sub-storage chains cannot be electrically connected to the first bit line BL1 and the first plate line PL1 through the first bit line selection tube BLS1 and the first plate line selection tube PLS1. Therefore, the other first sub-storage chains are not selected.

[0099] Those skilled in the art will appreciate that the first selected storage unit is one of the multiple first storage units. Unlike the other first storage units in the multiple first storage units, the first selected storage unit can be selected to read the storage signal during the read phase and can be selected to write the storage signal during the reverse write phase. The functions of the second selected storage unit in the multiple second storage units, the third selected storage unit in the multiple third storage units, and the fourth selected storage unit in the multiple fourth storage units described below are all the same as the functions of the first selected storage unit in the multiple first storage units and are not further described below.

[0100] Next, as shown in Figure 5, in the reading phase, the first selected memory cell among the multiple first memory cells is confirmed, the first bit line BL1 electrically connected to the first selected memory cell is precharged to 0V, and the first bit line BL1 is placed in a floating state so that the potential on the first bit line BL1 changes when the signal is read.

[0101] Furthermore, the selected first sub-memory chain includes a first selected memory cell and unselected memory cells. By controlling the word line WL electrically connected to the first selected memory cell to a low level, the transistors in the first selected memory cell are turned off; by controlling the word line WL electrically connected to the unselected memory cells to a high level, the transistors in the unselected memory cells are turned on. In this way, the first bit line BL1, the first bit line select transistor BLS1 electrically connected to the selected first sub-memory chain, the capacitor in the first selected memory cell, the transistors in the unselected memory cells, the first plate line select transistor PLS1 electrically connected to the selected first sub-memory chain, and the first plate line PL1 electrically connected to the selected first sub-memory chain form a path.

[0102] The first plate line PL1 electrically connected to the selected first sub-memory chain is controlled to be at a high level (eg, an operating voltage of 0.5V to 3V), and the storage signal in the capacitor of the first selected memory cell is read.

[0103] On this basis, as shown in FIG6 , the memory chip may further include a second bit line BL2 and a comparison circuit, which may be, for example, a sense amplifier (SA). The first bit line BL1 is electrically connected to a first input terminal of the sense amplifier SA for inputting a storage signal to the sense amplifier SA. The second bit line BL2 is electrically connected to a second input terminal of the sense amplifier SA for inputting a reference voltage Vref to the sense amplifier SA.

[0104] For example, if the first selected memory chain is a ferroelectric memory chain, the read phase consists of a destroy phase and a sense phase. During the destroy phase, the capacitor (ferroelectric capacitor) in the first selected memory cell undergoes a ferroelectric flip, transferring charge to the first bit line BL1. Subsequently, during the sense phase, the comparator circuit operates and differentially amplifies the received storage signal to determine whether the stored signal is a digital 0 or a digital 1 based on a reference voltage Vref.

[0105] Specifically, if the storage signal in the first selected memory cell is a digital signal 0, the potential of the first bit line BL1 will rise slightly (the denser dashed line in Figure 5), but the potential of the first bit line BL1 will still be below the reference voltage Vref. If the storage signal in the first selected memory cell is a digital signal 1, the potential of the first bit line BL1 will rise to a higher potential, exceeding the reference voltage Vref. The sense amplifier SA differentially amplifies the received storage signal based on the different potentials on the first bit line BL1, lowering the potential to 0V when the storage signal is a digital signal 0 and raising the potential to Vdd when the storage signal is a digital signal 1. At this point, the read operation is complete.

[0106] Furthermore, as shown in FIG6 , in addition to the second bit line BL2, the memory chip may further include a second memory chain, a second bit line selection transistor BLS2, a second plate line selection transistor PLS2, and a plurality of second plate lines PL2. The second memory chain may be fabricated using the same semiconductor process as the first memory chain, the second bit line selection transistor BLS2 and the second plate line selection transistor PLS2 may be fabricated using the same semiconductor process as the first bit line selection transistor BLS1 and the first plate line selection transistor PLS1, and the plurality of second plate lines PL2 and second bit lines BL2 may be fabricated using the same semiconductor process as the plurality of first plate lines PL1 and the first bit line BL1. The second memory chain includes a plurality of second sub-memory chains connected in series, each of which includes a plurality of second memory cells connected in series. The second bit line selection tube BLS2 is connected in series between the second bit line BL2 and the second sub-storage chain, and multiple second sub-storage chains are electrically connected to the same second bit line BL2 through multiple second bit line selection tubes BLS2; the second plate line selection tube PLS2 is connected in series between the second plate line PL2 and the second sub-storage chain, and multiple second plate line selection tubes PLS2 are electrically connected to multiple second plate lines PL2 one by one.

[0107] Referring to Figure 6, the word line WL, first bit line BL1, first plate line PL1, first gate line GL1, and second gate line GL2 electrically connected to the first storage chain, and the word line WL, second bit line BL2, second plate line PL2, first gate line GL1, and second gate line GL2 electrically connected to the second storage chain can be manufactured using the same semiconductor process. However, it should be understood that the word line WL, first bit line BL1, first plate line PL1, first gate line GL1, and second gate line GL2 electrically connected to the first storage chain are not shared with the word line WL, second bit line BL2, second plate line PL2, first gate line GL1, and second gate line GL2 electrically connected to the second storage chain.

[0108] As previously described, during the read phase, the first bit line BL1 inputs a stored signal to the sense amplifier SA, while the second bit line BL2 inputs a reference signal Vref to the sense amplifier SA. However, in some other embodiments, the first bit line BL1 and the second bit line BL2 may time-share the storage signal inputs to the sense amplifier SA. Specifically, when the first bit line BL1 inputs a stored signal to the sense amplifier SA, the second bit line BL2 inputs the reference signal Vref to the sense amplifier SA. Similarly, when the second bit line BL2 inputs a stored signal to the sense amplifier SA, the first bit line BL1 inputs the reference signal Vref to the sense amplifier SA.

[0109] In some possible implementations, the comparison circuit can be fabricated via a back-end process. This avoids high-temperature processing during the fabrication of the comparison circuit, which could affect the performance of transistors in the first storage chain. Furthermore, when the comparison circuit is fabricated via a back-end process, the comparison circuit and the first storage chain can be stacked in the Z direction. That is, the orthographic projection of the comparison circuit on the XY plane falls within the orthographic projection of the first storage chain on the XY plane, thereby preventing the comparison circuit from occupying the area of ​​the memory chip on the XY plane.

[0110] Next, as shown in Figure 5, during the write recovery phase, the first plate line PL1 electrically connected to the selected first sub-memory chain is maintained at a high voltage for a period of time, then drops to a low voltage (e.g., 0V), and then remains at a low voltage for a period of time. During this period, the word line WL electrically connected to the transistor of the first selected memory cell is maintained at a low voltage, thereby disconnecting the transistor of the first selected memory cell and maintaining the capacitor of the first selected memory cell. When the signal read during the read phase is a digital signal 0, the voltage on the first bit line BL1 is 0V. During the period when the first plate line PL1 electrically connected to the selected first sub-memory chain is at a high voltage, the digital signal 0 can be rewritten into the capacitor of the first selected memory cell. When the signal read during the read phase is a digital signal 1, the voltage on the first bit line BL1 is at a high voltage VDD. During the period when the first plate line PL1 electrically connected to the selected first sub-memory chain is at a low voltage, the digital signal 0 can be rewritten into the capacitor of the first selected memory cell.

[0111] Next, as shown in Figure 5, during the post-charge phase, the first bit line BL1 and the multiple first plate lines PL1 are at a low level. Afterward, the potentials of the multiple word lines WL remain low for a period of time before rising, turning on the transistors of the multiple first memory cells. Next, the first gate line GL1 electrically connected to the first bit line select transistor BLS1 and the second gate line GL2 electrically connected to the first plate line select transistor PLS1 go low, turning off the first bit line select transistor BLS1 and the first plate line select transistor PLS1. At this point, a read / write cycle is complete.

[0112] The above example briefly introduces the read and write process of the first storage unit, taking the example where the transistor of the first storage unit, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 are all N-type transistors, and the transistor in the first storage unit is connected in parallel with the capacitor. Of course, at least one of the transistor of the first storage unit, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 can be an N-type transistor, and the others can be P-type transistors; or, the transistor of the first storage unit, the first bit line selection tube BLS1, and the first plate line selection tube PLS1 can all be P-type transistors. Also, the transistor in the first storage unit and the capacitor can be connected in parallel in other ways, which is not limited in the embodiments of the present application.

[0113] In some possible implementations, taking the application of a memory chip in a chain ferroelectric memory as an example, the capacitor may be a ferroelectric capacitor, and the material of the ferroelectric layer located between the first electrode and the second electrode in the ferroelectric capacitor may include hafnium-based, zirconium-based oxides, hafnium-based, zirconium-based oxides containing doping elements (such as Hf, Zr, Si, Y, La, Ce, etc.), etc. The ferroelectric layer may be a single layer or multiple layers of ferroelectric / antiferroelectric materials of different components. The thickness of the ferroelectric layer may range from 2nm to 15nm, and the area of ​​the ferroelectric layer in the XY plane may be 0.04um. 2 ~0.25um 2 .

[0114] In some embodiments, as shown in Figure 7a, the first bit line selection tube BLS1 includes a first sub-bit line selection tube BLS1_1 and a second sub-bit line selection tube BLS1_2, the first plate line selection tube includes a first sub-plate line selection tube PLS1_1 and a second sub-plate line selection tube PLS1_2, and the first sub-storage chain is connected in series between the first sub-bit line selection tube BLS1_1 and the first sub-plate line selection tube PLS1_1.

[0115] The first sub-storage chain includes at least three segmented storage chains connected in series. One segmented storage chain is connected in series between the first sub-bitline gate transistor BLS1_1 and the second sub-plate line gate transistor PLS1_2, one segmented storage chain is connected in series between the first sub-plate line gate transistor PLS1_1 and the second sub-bitline gate transistor BLS1_2, and the remaining segmented storage chains are connected in series between the second sub-bitline gate transistor BLS1_2 and the second sub-plate line gate transistor PLS1_2. This allows the selection of the first sub-storage chain or segmented storage chain to be dynamically adjusted based on the service life of the first storage chain, thereby ensuring the performance of the first storage chain over its service life.

[0116] As shown in Figure 7a, considering that in the early stages of the life of the first storage chain (for example, the first storage chain's usage time is less than a preset time), the transistor's on-state current is high and its performance is good, so the selected first sub-storage chain can be relatively long. During the read and write phases, the first sub-bitline selection transistor and the first sub-plate line selection transistor connected in series with the selected storage cell are active, while the second sub-bitline selection transistor and the second sub-plate line selection transistor are inactive. This ensures that all of the first sub-storage chain containing the first selected storage cell is selected, but the other storage cells in the selected first sub-storage chain, except for the first selected storage cell, do not read or write signals. The usage time of the first storage chain refers to the actual usage time of the first storage chain after it is put into use, and the preset time refers to the usage time pre-designed by those skilled in the art for the first storage chain.

[0117] For example, as shown in Figure 7a, the first sub-storage chain includes five segmented storage chains connected in series, each of which includes two first storage cells. If the usage time of the first storage chain is less than a preset time, then during the read / write phase, the first sub-bitline selection transistor BLS1_1 electrically connected to the first first storage cell of the first sub-storage chain and the first sub-plate line selection transistor PLS1_1 electrically connected to the tenth first storage cell of the first sub-storage chain are turned on (black in the figure), and the other second sub-bitline selection transistors BLS1_2 and second sub-plate line selection transistors PLS1_2 electrically connected to the first sub-storage chain are turned off (gray in the figure).

[0118] As the usage time increases, the performance of the transistor gradually decays and the on-state current decreases. For example, when the usage time of the first storage chain is greater than or equal to the preset time, during the read and write phase, a segmented storage chain in a first sub-storage chain may be selected, and other segmented storage chains in the first sub-storage chain may not be selected.

[0119] For example, as shown in FIG7b, in the read / write phase, if the first / second first storage cell on the first sub-storage chain is the first selected storage cell, the first sub-bit line selection tube BLS1_1 and the second sub-plate line selection tube PLS1_2 connected in series with the first selected storage cell are on, and the other second sub-bit line selection tubes BLS1_2 and the first sub-plate line selection tube PLS1_1 are turned off; if one of the third to eighth first storage cells on the first sub-storage chain is the first selected storage cell, the third sub-bit line selection tube BLS1_1 connected in series with the first selected storage cell is on. The second sub-bit line selection tube BLS1_2 and the second sub-plate line selection tube PLS1_2 are working, and the other first sub-bit line selection tubes BLS1_1 and the first sub-plate line selection tube PLS1_1 are turned off; if the ninth / tenth first storage unit on the first sub-storage chain is the first selected storage unit, the second sub-bit line selection tube BLS1_2 and the first sub-plate line selection tube PLS1_1 connected in series with the first selected storage unit are working, and the other first sub-bit line selection tubes BLS1_1 and the second sub-plate line selection tube PLS1_2 are turned off.

[0120] In some possible implementations, the embodiments of the present application do not limit the specific time of the preset duration. The preset duration can be specifically designed according to the specific situation of the storage chip. For example, the preset duration can be 10 years.

[0121] The structure corresponding to Figure 6 above introduces a scheme in which the second storage chain is arranged on the same layer as the first storage chain, the second bit line selection tube BLS2 and the second plate line selection tube PLS2 are electrically connected to the second bit line BL2, and are arranged on the same layer as the first bit line selection tube BLS1 and the first plate line selection tube PLS1, and multiple second plate lines PL2 and second bit lines BL2 are arranged on the same layer as the first line BL1 and multiple first plate lines PL1. In other embodiments, as shown in Figure 8, the second storage chain, the second bit line selection tube BLS2, and the second plate line selection tube PLS2 can also be stacked with the first storage chain, the first bit line selection tube BLS1 and the first plate line selection tube PLS1, and the second storage chain and the second storage chain share the same first bit line BL1. The stacking setting scheme is described in detail below in combination with Figures 8 and 9.

[0122] As shown in Figure 9, the second plate line PL2 is arranged on the same layer as the first and second plate lines BL1 and PL1, all located on the routing layer. The second bit line select transistors BLS2 and PLS2 are stacked on the side of the first and second plate lines BL1 facing away from the first storage chain. The second storage chain is stacked on the side of the second bit line select transistors BLS2 and PLS2 facing away from the first storage chain. That is, while the first and second plate line select transistors BLS1 and PLS1 are stacked with the first storage chain in the Z direction, the second bit line select transistors BLS2 and PLS2, and the second storage chain, are also stacked with the first storage chain in the Z direction. This further improves storage density.

[0123] For example, as shown in Figure 9, multiple second plate lines PL2 are located in the M(n+1) layer; the second bit line selection tube BLS2 and the second plate line selection tube PLS2 are located in the M(n+2) layer to the Mm layer, where m>n+2; the second electrode of the capacitor in the second storage chain is located in the M(m+1) layer, the first electrode of the capacitor in the second storage chain is located in the M(m+2) layer, and the transistors in the second storage chain are located in the M(m+3) layer to the Mx layer, where x>m+3.

[0124] Furthermore, a third dielectric layer is provided between the M(n+1) layer and the M(n+2) layer, and a fourth dielectric layer is provided between the Mm layer and the second memory chain.

[0125] Of course, in addition to being stacked in the M(n+2) layer to the Mx layer in the above-mentioned manner, multiple second plate lines PL2, second bit line selection tubes BLS2 and second plate line selection tubes PLS2, transistors and capacitors of the second storage chain can also be stacked in other ways, and the embodiments of the present application are not limited to this.

[0126] For example, the previous description describes the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2 being disposed on the same layer, both located in layers M(n+2) to Mm. However, in other possible implementations, the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2 can also be disposed on different layers. For example, the second bit line gate transistor BLS2 can be disposed between the substrate 10 and the second plate line gate transistor PLS2; or the second bit line gate transistor BLS2 can be disposed between the substrate 10 and the second plate line gate transistor PLS2.

[0127] Compared to the solution where the second bitline gate transistor BLS2 and the second plate line gate transistor PLS2 are arranged on different layers, the solution where the second plate line gate transistor PLS2 and the second bitline gate transistor BLS2 are arranged on the same layer allows the second bitline gate transistor BLS2 and the second plate line gate transistor PLS2 to be manufactured using the same semiconductor process, thereby simplifying the manufacturing process of the memory chip. Furthermore, when the second bitline gate transistor BLS2 and the second plate line gate transistor PLS2 are arranged on the same layer, it is convenient to electrically connect the second bitline gate transistor BLS2 and the second plate line gate transistor PLS2 to the wiring of the first storage chain and the wiring layer, respectively.

[0128] On this basis, as shown in FIG8 , the second storage chain includes multiple second sub-storage chains connected in series, each of which includes multiple second storage cells connected in series. The second storage chain is connected in series between a second bit line select transistor BLS2 and a second plate line select transistor PLS2. The second bit line select transistor BLS2 is connected in series between the first bit line BL1 and the second sub-storage chain, and multiple second sub-storage chains are electrically connected to the same first bit line BL1 via multiple second bit line select transistors BLS2. That is, the same first bit line BL1 is electrically connected to both multiple first bit line select transistors BLS1 and multiple second bit line select transistors BLS2. The second plate line select transistor BLS2 is connected in series between the second plate line PL2 and the second sub-storage chain, and multiple second plate line select transistors PLS2 are electrically connected to multiple second plate lines PL2 in a one-to-one correspondence.

[0129] By having multiple first bit line selection transistors BLS1 and multiple second bit line selection transistors BLS2 share the same first bit line BL1, any first storage cell on the first storage chain can be selected as the first selected storage cell, or any second storage cell on the second storage chain can be selected as the second selected storage cell, thereby implementing time-sharing reading and writing of the first selected storage cell and the second selected storage cell. Furthermore, the number of wiring in the wiring layer is reduced.

[0130] Furthermore, as shown in Figure 10, the memory chip also includes a third storage chain, a third bit line selection tube BLS3, a third plate line selection tube PLS3, a fourth storage chain, a fourth bit line selection tube BLS4, a fourth plate line selection tube PLS4, a second bit line BL2, multiple third plate lines PL3, and multiple fourth plate lines PL4.

[0131] The third storage chain is arranged in the same layer as the first storage chain, and includes a plurality of third sub-storage chains connected in series, each of which includes a plurality of third storage units connected in series. The fourth storage chain is arranged in the same layer as the second storage chain, and includes a plurality of fourth sub-storage chains connected in series, each of which includes a plurality of fourth storage units connected in series.

[0132] The third bit line gate transistor BLS3 and the third plate line gate transistor PLS3 are arranged on the same layer as the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1. The third sub-storage chain is connected in series between the third bit line gate transistor BLS3 and the third plate line gate transistor PLS3. The fourth bit line gate transistor BLS4 and the fourth plate line gate transistor PLS4 are arranged on the same layer as the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2. The fourth sub-storage chain is connected in series between the fourth bit line gate transistor BLS4 and the fourth plate line gate transistor PLS4.

[0133] The second bit line BL2, multiple third plate lines PL3, and multiple fourth plate lines PL4 are arranged on the same layer as the first bit line BL1 and multiple second plate lines PL2, all located on the routing layer. A third bit line select transistor BLS3 is connected in series between the second bit line BL2 and the third sub-storage chain, and multiple third sub-storage chains are electrically connected to the same second bit line BL2 via multiple third bit line select transistors BLS3. A third plate line select transistor PLS3 is connected in series between the third plate line PL3 and the third sub-storage chain, and multiple third plate line select transistors PLS3 are electrically connected to multiple third plate lines PL3 in a one-to-one correspondence. A fourth bit line select transistor BLS4 is connected in series between the second bit line BL2 and the fourth sub-storage chain, and multiple fourth sub-storage chains are electrically connected to the same second bit line BL2 via multiple fourth bit line select transistors BLS4. A fourth plate line select transistor PLS4 is connected in series between the fourth plate line PL4 and the fourth sub-storage chain, and multiple fourth plate line select transistors PLS4 are electrically connected to multiple fourth plate lines PL4 in a one-to-one correspondence.

[0134] That is, the first and second memory chains sharing the same first bit line BL1 are stacked in the Z direction, and the third and fourth memory chains sharing the same second bit line BL2 are stacked in the Z direction. Furthermore, the first and third memory chains are fabricated using the same semiconductor process, and the second and fourth memory chains are fabricated using the same semiconductor process.

[0135] Since the first storage chain and the second storage chain share the same first bit line BL1, and the third storage chain and the fourth storage chain share the same second bit line BL2, and when the first bit line BL1 inputs a storage signal to the comparison circuit, the second bit line BL2 can be used to input a reference voltage Vref to the comparison circuit; when the second bit line BL2 inputs a storage signal to the comparison circuit, the first bit line BL1 can be used to input a reference voltage Vref to the comparison circuit.

[0136] Based on this, the operations of the first storage chain, the second storage chain, the third storage chain, and the fourth storage chain in the memory chip can be divided into the following three situations:

[0137] In the first case, the first memory cell in the first memory chain and the third memory cell in the third memory chain are used for reading and writing signals. For example, as shown in FIG11a , during the read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, which is used to input a first read signal data1 to a comparator circuit via a first bit line BL1, and a second bit line BL2 is used to input a first reference voltage Vref1 to the comparator circuit. Alternatively, as shown in FIG11b , during the read phase, the plurality of third memory cells in the third memory chain include a third selected memory cell, which is used to input a second read signal data2 to the comparator circuit via a second bit line BL2, and a first bit line BL1 is used to input a second reference voltage Vref2 to the comparator circuit.

[0138] In the second scenario, the first storage cells in the first storage chain and the second storage cells in the second storage chain are used for reading and writing signals. For example, as shown in FIG12a , during the read phase, the plurality of first storage cells in the first storage chain include a first selected storage cell, which is used to input a first read signal data1 to the comparison circuit via the first bit line BL1, and the second bit line BL2 is used to input a first reference voltage Vref1 to the comparison circuit. Alternatively, as shown in FIG12b , during the read phase, the plurality of second storage cells in the second storage chain include a second selected storage cell, which is used to input a second read signal data2 to the comparison circuit via the first bit line BL1, and the second bit line BL2 is used to input a second reference voltage Vref2 to the comparison circuit.

[0139] Similar to the second case, the read and write signals of the third storage unit in the third storage chain and the fourth storage unit in the fourth storage chain may also be used, which will not be described in detail here.

[0140] In the third scenario, the second storage cells in the second storage chain and the fourth storage cells in the fourth storage chain are used for reading and writing signals. For example, as shown in FIG13a , during the read phase, the plurality of second storage cells in the second storage chain include a second selected storage cell, which is used to input a first read signal data1 to the comparison circuit via the first bit line BL1, and the second bit line BL2 is used to input a first reference voltage Vref1 to the comparison circuit. Alternatively, as shown in FIG13b , during the read phase, the plurality of fourth storage cells in the fourth storage chain include a fourth selected storage cell, which is used to input a second read signal data2 to the comparison circuit via the second bit line BL2, and the first bit line BL1 is used to input a second reference voltage Vref2 to the comparison circuit.

[0141] The present application also provides a method for preparing a memory chip, as shown in FIG14 , which can be implemented by the following steps:

[0142] S110 , as shown in FIG. 15 a , a first storage chain is formed on a substrate 10 , the first storage chain including a plurality of first sub-storage chains connected in series, and the first sub-storage chain including a plurality of first memory cells connected in series.

[0143] For example, as shown in FIG15 a , the first storage chain includes a transistor and a capacitor, the capacitor including a first electrode and a second electrode. The transistor is located in the metal 0 (M0) layer, the first electrode is located in the M1 layer, and the second electrode is located in the M2 layer.

[0144] S120, as shown in FIG15b, a first bit line gate transistor BLS1 and a first plate line gate transistor PLS1 are formed on the first storage chain, and the first sub-storage chain is connected in series between the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1.

[0145] For example, as shown in FIG15 b , the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 are located in the M3 layer to the Mn layer, where n>3.

[0146] In some possible implementations, after step S110 and before step S120, a first dielectric layer may be formed on the first storage chain to electrically isolate the first storage chain from the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1. Furthermore, to connect the first sub-storage chain of the first storage chain in series between the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1, a first through-hole may be formed in the first dielectric layer. In this way, the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 formed after the first dielectric layer can be connected in series with the first sub-storage chain through the first through-hole.

[0147] S130, as shown in Figure 3a, a routing layer is formed on the side of the first bit line selection tube BLS1 and the first plate line selection tube PLS1 facing away from the substrate 10, the routing layer includes the first bit line BL1 and multiple first plate lines PL1, the first bit line selection tube BLS1 is connected in series between the first bit line BL1 and the first sub-storage chain, and the multiple first sub-storage chains are electrically connected to the same first bit line BL1 through multiple first bit line selection tubes BLS1; the first plate line selection tube PLS1 is connected in series between the first plate line PL1 and the first sub-storage chain, and the multiple first plate line selection tubes PLS1 are electrically connected to the multiple first plate lines PL1 in a one-to-one correspondence.

[0148] For example, as shown in FIG. 3 a , the first bit line BL1 and the plurality of first plate lines PL1 are located in the M(n+1) layer.

[0149] In some possible implementations, after step S120 and before step S130, a second dielectric layer may be formed on the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1. The second dielectric layer may be used to electrically isolate the first bit line gate transistor BLS1 and the first plate line gate transistor PLS1 from the first bit line BL1 and the plurality of first plate lines PL1. Furthermore, to achieve the serial connection of the first bit line gate transistor BLS1 between the first bit line BL1 and the first sub-memory chain, and the serial connection of the first plate line gate transistor PLS1 between the first plate line PL1 and the first sub-memory chain, a second through-hole may be formed in the second dielectric layer. In this way, the first bit line BL1 formed after the second dielectric layer can be electrically connected to the plurality of first plate line gate transistors PLS1 through the second through-hole, and the plurality of first plate lines PL1 can be electrically connected to the first plate line gate transistor PLS1 through the second through-hole.

[0150] In the present application, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 are stacked with the first storage chain. In this way, the first bit line gate tube BLS1 and the first plate line gate tube PLS1 can be overlapped with the first storage chain, that is, the orthographic projection of the first bit line gate tube BLS1 and the first plate line gate tube PLS1 on the XY plane falls within the orthographic projection range of the layer where the first storage chain is located on the XY plane, thereby avoiding the first bit line gate tube BLS1 and the first plate line gate tube PLS1 occupying the area of ​​the memory chip on the XY plane, so that the effective area of ​​the first storage unit on the first storage chain becomes a standard 4F 2 , thereby improving the storage density of the first storage chain. Furthermore, even if the memory array includes more first storage chains due to the limitation of the on-state current of the transistors in the first storage cells, the multiple first bit line selection transistors BLS1 and first plate line selection transistors PLS1 electrically connected to the multiple first storage chains can also be stacked with the first storage chains in the Z direction, thereby improving the storage density of the memory array.

[0151] In some embodiments, the routing layer further includes a plurality of second plate lines PL2. After step S130, the chip manufacturing method further includes:

[0152] S140 , as shown in FIG. 16 , a second bit line gate transistor BLS2 and a second plate line gate transistor PLS2 are formed on a side of the plurality of second plate lines PL2 facing away from the substrate 10 .

[0153] In some possible implementations, after step S130 and before step S140, a third dielectric layer may be formed on the plurality of second plate lines PL2. The third dielectric layer electrically isolates the plurality of first plate lines PL1, the first bit line BL1, and the plurality of second plate lines PL2 from the second bit line select transistors BLS2 and the second plate line select transistors PLS2. Furthermore, as mentioned in step S150, to achieve the connection of the second bit line select transistor BLS2 in series between the first bit line BL1 and the second sub-memory chain, and the connection of the second plate line select transistor PLS2 in series between the second plate line PL2 and the second sub-memory chain, a third through-hole may be formed in the third dielectric layer. In this way, the second bit line select transistor BLS2 formed after the third dielectric layer can be electrically connected to the plurality of second plate lines PL2 through the third through-hole, and the second plate line select transistor PLS2 can be electrically connected to the plurality of second plate lines PL2 through the third through-hole.

[0154] S150, as shown in FIG9, forms a second storage chain with the second bit line select transistor BLS2 and the second plate line select transistor PLS2 on a side facing away from the substrate 10; the second storage chain includes multiple second sub-storage chains connected in series, each of which includes multiple second storage cells connected in series, and the second sub-storage chains are connected in series between the second bit line select transistor BLS2 and the second plate line select transistor PLS2. The second bit line select transistor BLS2 is connected in series between the first bit line BL1 and the second sub-storage chain, and the multiple second sub-storage chains are electrically connected to the same first bit line BL1 through the multiple second bit line select transistors BLS2; the second plate line select transistor PLS2 is connected in series between the second plate line PL2 and the second sub-storage chain, and the multiple second plate line select transistors PLS2 are electrically connected to the multiple second plate lines PL2 in a one-to-one correspondence.

[0155] In some possible implementations, after step S140 and before step S150, a fourth dielectric layer may be formed on the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2. The fourth dielectric layer may be used to electrically isolate the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2 from the second storage chain. Furthermore, to connect the second sub-storage chain of the second storage chain in series between the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2, a fourth through hole may be formed in the fourth dielectric layer. In this way, the second bit line gate transistor BLS2 and the second plate line gate transistor PLS2 formed after the fourth dielectric layer can be connected in series with the second sub-storage chain through the fourth through hole.

[0156] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A memory chip, characterized in that: include: substrate; a first storage chain disposed on the substrate, the first storage chain comprising a plurality of first sub-storage chains connected in series, the first sub-storage chain comprising a plurality of first storage cells connected in series; a first bit line gate transistor and a first plate line gate transistor stacked on a side of the first storage chain facing away from the substrate, the first sub-storage chain being connected in series between the first bit line gate transistor and the first plate line gate transistor; A routing layer is provided on a side of the first bit line selection tube and the first plate line selection tube facing away from the substrate, the routing layer including a first bit line and a plurality of first plate lines, the first bit line selection tube is connected in series between the first bit line and the first sub-storage chain, and the plurality of first sub-storage chains are electrically connected to the same first bit line through the plurality of first bit line selection tubes; the first plate line selection tube is connected in series between the first plate line and the first sub-storage chain, and the plurality of first plate line selection tubes are electrically connected to the plurality of first plate lines in a one-to-one correspondence.

2. The memory chip according to claim 1, wherein: The first storage chain is manufactured through a front-end process, and the first bit line gate transistor, the first plate line gate transistor, and the routing layer are all manufactured through a back-end process.

3. The memory chip according to claim 1 or 2, wherein: The first bit line gate transistor includes a first sub-bit line gate transistor and a second sub-bit line gate transistor, the first plate line gate transistor includes a first sub-plate line gate transistor and a second sub-plate line gate transistor, and the first sub-storage chain is connected in series between the first sub-bit line gate transistor and the first sub-plate line gate transistor; The first sub-storage chain includes at least three segmented storage chains connected in series, one of the segmented storage chains is connected in series between the first sub-bit line gate transistor and the second sub-plate line gate transistor, one of the segmented storage chains is connected in series between the first sub-plate line gate transistor and the second sub-bit line gate transistor, and the other segmented storage chains are connected in series between the second sub-bit line gate transistor and the second sub-plate line gate transistor.

4. The memory chip according to claim 3, wherein: During a read / write phase, the plurality of first storage cells in the first storage chain include a selected storage cell; If the usage time of the first storage chain is less than the preset time, then in the read and write phase, the first sub-bit line gating transistor and the first sub-plate line gating transistor connected in series with the selected storage cell are in operation, and the second sub-bit line gating transistor and the second sub-plate line gating transistor are inoperative; If the usage time of the first storage chain is greater than or equal to the preset time time, then in the read and write phase, the first sub-bit line selection tube and the second sub-plate line selection tube connected in series with the selected storage unit work, or the second sub-bit line selection tube and the first sub-plate line selection tube connected in series with the selected storage unit work, or the second sub-bit line selection tube and the second sub-plate line selection tube connected in series with the selected storage unit work.

5. The memory chip according to any one of claims 1 to 4, characterized in that: The memory chip further includes a comparison circuit, the routing layer further includes a second bit line, and the comparison circuit is prepared by a back-end process; The input end of the comparison circuit is electrically connected to the second bit line and the first bit line respectively; wherein, in the reading stage, the first bit line is used to input the storage signal to the comparison circuit, and the second bit line is used to input the reference voltage to the comparison circuit; the comparison circuit is used to determine whether the storage signal is a digital signal 0 or a digital signal 1 based on the reference voltage.

6. The memory chip according to any one of claims 1 to 4, wherein: The memory chip further includes a second memory chain, a second bit line gating transistor, and a second plate line gating transistor, and the routing layer further includes a plurality of second plate lines; The second bit line gating transistor and the second plate line gating transistor are stacked on a side of the routing layer away from the first storage chain, and the second storage chain is stacked on a side of the second bit line gating transistor and the second plate line gating transistor away from the first storage chain; The second storage chain includes a plurality of second sub-storage chains connected in series, and the second sub-storage chain includes a plurality of second storage units connected in series; the second sub-storage chain is connected in series between the second bit line gating transistor and the second plate line gating transistor; The second bit line selection tube is connected in series between the first bit line and the second sub-storage chain, and the multiple second sub-storage chains are electrically connected to the same first bit line through multiple second bit line selection tubes; the second plate line selection tube is connected in series between the second plate line and the second sub-storage chain, and the multiple second plate line selection tubes are electrically connected to the multiple second plate lines in a one-to-one correspondence.

7. The memory chip according to claim 6, wherein: The memory chip further includes a third memory chain, a third bit line gating transistor, a third plate line gating transistor, a fourth memory chain, a fourth bit line gating transistor, and a fourth plate line gating transistor, and the routing layer further includes a second bit line, a plurality of third plate lines, and a plurality of fourth plate lines; The third storage chain is provided in the same layer as the first storage chain, the third storage chain includes a plurality of third sub-storage chains connected in series, and the third sub-storage chain includes a plurality of third storage units connected in series; The third bit line gate transistor and the third plate line gate transistor are arranged on the same layer as the first bit line gate transistor and the first plate line gate transistor, and the third sub-storage chain is connected in series between the third bit line gate transistor and the third plate line gate transistor; The fourth storage chain is provided in the same layer as the second storage chain, the fourth storage chain includes a plurality of fourth sub-storage chains connected in series, and the fourth sub-storage chain includes a plurality of fourth storage units connected in series; The fourth bit line gate transistor and the fourth plate line gate transistor are arranged on the same layer as the second bit line gate transistor and the second plate line gate transistor, and the fourth sub-storage chain is connected in series between the fourth bit line gate transistor and the fourth plate line gate transistor; The third bit line selection tube is connected in series between the second bit line and the third sub-storage chain, and the multiple third sub-storage chains are electrically connected to the same second bit line through the multiple third bit line selection tubes; the third plate line selection tube is connected in series between the third plate line and the third sub-storage chain, and the multiple third plate line selection tubes are electrically connected to the multiple third plate lines in a one-to-one correspondence; the fourth bit line selection tube is connected in series between the second bit line and the fourth sub-storage chain, and the multiple fourth sub-storage chains are electrically connected to the same second bit line through the multiple fourth bit line selection tubes; the fourth plate line selection tube is connected in series between the fourth plate line and the fourth sub-storage chain, and the multiple fourth plate line selection tubes are electrically connected to the multiple fourth plate lines in a one-to-one correspondence.

8. The memory chip according to claim 7, wherein: In a read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, the first selected memory cell is used to input a first read signal to the comparison circuit through the first bit line, and the second bit line is used to input a first reference voltage to the comparison circuit; or In the reading phase, the plurality of third storage cells in the third storage chain include a third selected storage cell, the third selected storage cell is used to input a second read signal to the comparison circuit through the second bit line, and the first bit line is used to input a second reference voltage to the comparison circuit.

9. The memory chip according to claim 7, wherein: In a read phase, the plurality of first memory cells in the first memory chain include a first selected memory cell, the first selected memory cell is used to input a first read signal to the comparison circuit through the first bit line, and the second bit line is used to input a first reference voltage to the comparison circuit; or In the reading phase, the plurality of second storage cells in the second storage chain include a second selected storage cell, the second selected storage cell is used to input a second read signal to the comparison circuit through the first bit line, and the second bit line is used to input a second reference voltage to the comparison circuit.

10. The memory chip according to claim 7, wherein: In a read phase, the plurality of second storage cells in the second storage chain include a second selected storage cell, the second selected storage cell is used to input a first read signal to the comparison circuit through the first bit line, and the second bit line is used to input a first reference voltage to the comparison circuit; or In the reading phase, the plurality of fourth storage cells in the fourth storage chain include a fourth selected storage cell, the fourth selected storage cell being used to input a second read signal to the comparison circuit through the second bit line, and the first bit line being used to input a second reference voltage to the comparison circuit.

11. The memory chip according to any one of claims 1 to 10, wherein: The first storage unit includes a transistor and a capacitor connected in parallel, and the routing layer further includes a word line, a first gate line, and a second gate line; The word line is electrically connected to the gate of the transistor, the first electrode of the transistor is electrically connected to the first plate line gate tube, and the second electrode of the transistor is electrically connected to the first bit line gate tube; The first gate line is electrically connected to the gate of the first bit line gate transistor, and the second gate line is electrically connected to the gate of the first plate line gate transistor.

12. A memory, characterized in that: It comprises a controller and the memory chip according to any one of claims 1 to 11, wherein the controller is used to control the memory chip to read and write data.

13. An electronic device, characterized in that: It comprises a processor and the memory according to claim 12, wherein the processor is used to read and write data to the memory chip through a controller in the memory.

14. A method for preparing a memory chip, characterized in that: include: forming a first storage chain on a substrate, wherein the first storage chain includes a plurality of first sub-storage chains connected in series, and the first sub-storage chain includes a plurality of first storage cells connected in series; A first bit line gating transistor and a first plate line gating transistor are formed on the first storage chain, and the first sub-storage chain is connected in series between the first bit line gating transistor and the first plate line gating transistor; A routing layer is formed on the side of the first bit line selection tube and the first plate line selection tube facing away from the substrate. The routing layer includes a first bit line and multiple first plate lines. The first bit line selection tube is connected in series between the first bit line and the first sub-storage chain, and the multiple first sub-storage chains are electrically connected to the same first bit line through multiple first bit line selection tubes; the first plate line selection tube is connected in series between the first plate line and the first sub-storage chain, and the multiple first plate line selection tubes are electrically connected to the multiple first plate lines in a one-to-one correspondence.

15. The method for preparing a memory chip according to claim 14, wherein: The routing layer further includes a plurality of second board lines; After forming a routing layer on the first bit line gate transistor and the first plate line gate transistor facing away from the substrate, the chip manufacturing method further includes: forming a second bit line gate transistor and a second plate line gate transistor on a side of the plurality of second plate lines away from the substrate; A second storage chain is formed on the side of the second bit line selection tube and the second plate line selection tube facing away from the substrate; the second storage chain includes multiple second sub-storage chains connected in series, and the second sub-storage chain includes multiple second storage units connected in series; the second sub-storage chain is connected in series between the second bit line selection tube and the second plate line selection tube; the second bit line selection tube is connected in series between the first bit line and the second sub-storage chain, and the multiple second sub-storage chains are electrically connected to the same first bit line through multiple second bit line selection tubes; the second plate line selection tube is connected in series between the second plate line and the second sub-storage chain, and the multiple second plate line selection tubes are electrically connected to the multiple second plate lines in a one-to-one correspondence.

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