Communication method and apparatus

Abstract

Provided in the present application are a communication method and apparatus. In the method, on the basis of performing convolution on some bit sequences among bit sequences to be sent, that is, on the basis of a coding framework of partial convolution of MPAC, CRC coding is introduced at a coding end, such that code weight distribution better than that of an MPAC code can be obtained, i.e. a greater coding gain can be obtained, and by means of a CRC code, the MPAC code can also be assisted in checking an output decoding path in a decoding stage, thus improving a path error detection capability, and thereby improving an error correction capability in the decoding stage, and improving the decoding performance.

Description

Communication method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on March 20, 2024, with application number 202410328509.2 and application name “Communication Method and Device,” the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of communication technology, and in particular to a communication method and device. Background Art

[0003] In recent years, a coding scheme that can approach the theoretical performance of finite code lengths has been proposed based on Polar codes: polarization-adjusted convolutional (PAC) codes. However, PAC codes require the assistance of the Fano decoding algorithm, which has the problem of high decoding complexity.

[0004] Currently, there are improved PAC code schemes based on the idea of ​​partial convolution and hybrid decoding strategies, namely modified PAC (MPAC) code and hybrid Fano-successive cancellation (HFSC) decoding. These can achieve a more ideal compromise between decoding performance and complexity within a limited decoding complexity. However, this decoding process cannot guarantee the correctness of the decoding output path, which will affect the error correction capability of the decoding algorithm. It is also impossible to determine whether the current decoding result is correct, and the decoding algorithm lacks error detection capabilities. Summary of the Invention

[0005] The embodiments of the present application provide a communication method and apparatus that can ensure the correctness of a decoding output path, determine whether a current decoding result is correct, and have error detection capabilities.

[0006] In a first aspect, a communication method is provided. The method can be performed by a first communication device, or by a module (such as a processor, chip, or chip system) applied to the first communication device. It can also be implemented by a logical node, a logical module, or software that can implement all or part of the functions of the first communication device. For the convenience of description, the following description takes the method performed by the first communication device as an example. The method includes: obtaining a bit sequence to be transmitted, the bit sequence to be transmitted includes a first bit sequence and a second bit sequence. Performing cyclic redundancy check (CRC) encoding on the first bit sequence to obtain a third bit sequence, and performing a convolution transform on the third bit sequence to obtain a fourth bit sequence. Performing polarization coding based on the second bit sequence and the fourth bit sequence to obtain a coded bit sequence. Outputting the coded bit sequence.

[0007] Based on the method of the first aspect, it can be seen that by introducing CRC coding at the coding end on the basis of convolution of part of the bit sequence to be transmitted, that is, based on the coding framework of MPAC partial convolution, it is possible to obtain a better code weight distribution than the MPAC code, that is, a greater coding gain, and the CRC code can be used to assist the MPAC code in the decoding stage to verify the output decoding path, increase the path error detection capability, thereby improving the error correction capability of the decoding stage and improving the decoding performance.

[0008] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the first bit sequence to obtain the third bit sequence may include: performing CRC encoding on the first bit sequence to obtain a CRC codeword, and performing code rate configuration on the CRC codeword to obtain the third bit sequence. It can be seen that performing CRC encoding on only a portion of the bit sequence to be transmitted can both increase the checksum of the decoding path through CRC and reduce the complexity of encoding and decoding.

[0009] Optionally, the bit sequence to be transmitted includes K information bits, the first bit sequence is K1 information bits of the K information bits, and the CRC codeword includes K1 information bits and r check bits, where K, K1, and r are integers greater than or equal to 1; configuring the code rate of the CRC codeword to obtain a third bit sequence may include: obtaining a bit sequence of length N1. Mapping the CRC codeword to K1+r first bits in a bit sequence of length N1 to obtain a third bit sequence, where K1+r is less than or equal to N1. The first bits are the first K1+r bits in the bit sequence of length N1, sorted from high to low according to row weight. In this way, based on the MPAC code coding framework, CRC coding is introduced to increase path error detection capability and improve decoding performance. The placement of the CRC codeword is designed to have a better code weight distribution than the MPAC code, that is, it can obtain a greater coding gain.

[0010] In one possible implementation, performing polar coding on the second bit sequence and the fourth bit sequence to obtain a coded bit sequence may include: performing code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence. Polar coding the fifth bit sequence can achieve a coded bit sequence that achieves improved decoding performance while also achieving lower average decoding complexity.

[0011] Optionally, the fourth bit sequence has a length of N1, the bit sequence to be transmitted includes K information bits, and the second bit sequence is K-K1 information bits of the K information bits; performing code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence may include: obtaining a bit sequence of length N. Based on the bit sequence of length N, determining K-K1+N1 second bits. Mapping the second bit sequence and the fourth bit sequence to the second bit in the bit sequence of length N to obtain a fifth bit sequence. The second bits are the first K-K1+N1 bits of the bit sequence of length N, sorted from high to low in terms of reliability. It can be understood that the second bit sequence and the fourth bit sequence are placed in bits with higher reliability and transmitted through a polarized channel with higher reliability. Bits with lower reliability can be set to 0. Constructing a long sequence can improve coding performance.

[0012] Optionally, mapping the second bit sequence and the fourth bit sequence to the second bit position in a bit sequence of length N to obtain a fifth bit sequence may include: mapping the second bit sequence to the third bit position in the bit sequence of length N, and mapping the fourth bit sequence to the fourth bit position in the bit sequence of length N to obtain a fifth bit sequence, wherein the third bit position is the first K-K1 bits of the second bit position sorted from high to low in terms of reliability, and the fourth bit position is the last N1 bits of the second bit position sorted from high to low in terms of reliability. It can be understood that by setting a different placement position for the bits that have undergone CRC encoding and convolution transformation than for the bits that are directly transmitted, the code weight distribution characteristic is guaranteed and the coding gain is improved.

[0013] On the second aspect, a communication method is provided, which can be executed by a second communication device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the second communication device, or by a logical node, a logical module, or software that can realize all or part of the functions of the second communication device. For the convenience of expression, the following is an introduction taking the method executed by the second communication device as an example. The method includes: obtaining a sequence to be decoded, the sequence to be decoded includes a first sequence and a second sequence. Fano decoding is performed on the first sequence to obtain a first bit sequence, and SC decoding is performed on the second sequence to obtain a second bit sequence. CRC check is performed on the first bit sequence. If the CRC check passes, the target bit sequence is determined based on the first bit sequence and the second bit sequence.

[0014] Optionally, the first sequence includes N1 bits, where the N1 bits are the last N1 bits of the M bits sorted from high to low according to reliability, and the M bits are the first M bits of the sequence to be decoded sorted from high to low according to reliability, and N1 and M are integers greater than or equal to 1.

[0015] The second sequence includes bits other than N1 bits in the sequence to be decoded.

[0016] Optionally, performing Fano decoding on the first sequence to obtain a first bit sequence may include: performing Fano decoding on the first K1+r bits in the first sequence sorted from high to low according to row weight according to a mapping relationship of the convolution transform to obtain the first bit sequence, where r is an integer greater than or equal to 1, and K1+r is less than or equal to N1.

[0017] Optionally, performing Fano decoding on the first sequence to obtain the first bit sequence includes: iterating a decoding path and performing Fano decoding on the first sequence according to the decoding path to obtain the first bit sequence. The decoding path is iterated if the CRC check fails.

[0018] Optionally, performing a CRC check on the first bit sequence may include: performing a CRC check on the first bit sequence when it is determined that decoding of the first bit sequence is completed.

[0019] It can be understood that the relevant technical effects of the method of the second aspect mentioned above can also refer to the relevant introduction of the first aspect mentioned above, and will not be repeated here.

[0020] In a third aspect, a communication method is provided. The method can be performed by a first communication device, or by a module (e.g., a processor, chip, or chip system) applied to the first communication device. The method can also be implemented by a logical node, logical module, or software that can implement all or part of the functions of the first communication device. For ease of description, the following description uses the method performed by the first communication device as an example. The method includes: obtaining a bit sequence to be transmitted. Performing cyclic redundancy check (CRC) encoding on the bit sequence to be transmitted to obtain a first bit sequence, where the first bit sequence includes a second bit sequence and a third bit sequence. Performing a convolution transform on the second bit sequence to obtain a fourth bit sequence. Performing polarization encoding on the third and fourth bit sequences to obtain a coded bit sequence. Outputting the coded bit sequence.

[0021] Based on the method of the third aspect, it can be seen that the difference between this method and the method of the first aspect is that the position of the CRC encoding module is different. By performing CRC encoding on the bit sequence to be transmitted, that is, performing CRC encoding before MPAC encoding, all information bits participate in CRC encoding, so that the CRC check has the ability to check all information bits of the bit sequence to be transmitted, and can use the CRC code to assist the MPAC code in the decoding stage to check the output decoding path, thereby increasing the path error detection capability.

[0022] Optionally, performing a convolution transform on the second bit sequence to obtain the fourth bit sequence includes: performing code rate configuration on the second bit sequence to obtain a fifth bit sequence; and performing a convolution transform on the fifth bit sequence to obtain the fourth bit sequence.

[0023] Optionally, the to-be-transmitted bit sequence includes K information bits, the first bit sequence includes K information bits and r check bits, and the second bit sequence includes K1 information bits and r check bits of the K information bits, where K, K1, and r are integers greater than or equal to 1; and performing code rate configuration on the second bit sequence to obtain a fifth bit sequence includes: obtaining a bit sequence of length N1. Mapping the second bit sequence to K1+r1 first bits in the bit sequence of length N1 to obtain the fifth bit sequence, where K1+r1 is less than or equal to N1.

[0024] The first bit is the first K1+r bits in the bit sequence of length N1 sorted from high to low according to row weight.

[0025] Optionally, performing polarization coding on the third bit sequence and the fourth bit sequence to obtain a coded bit sequence may include: performing code rate configuration on the third bit sequence and the fourth bit sequence to obtain a sixth bit sequence, and performing polarization coding on the sixth bit sequence to obtain the coded bit sequence.

[0026] Optionally, the fourth bit sequence has a length of N1, the to-be-transmitted bit sequence includes K information bits, and the second bit sequence includes K-K1 information bits of the K information bits and r-r1 parity bits of the r parity bits. Polar coding is performed on the third and fourth bit sequences to obtain a sixth bit sequence, including: obtaining a bit sequence of length N. Determining K-K1+r-r1+N1 second bits based on the bit sequence of length N. Mapping the third and fourth bit sequences to second bits of the bit sequence of length N to obtain the sixth bit sequence.

[0027] The second bit is the first K-K1+r-r1+N1 bits in the bit sequence of length N, sorted from high to low according to reliability.

[0028] Optionally, mapping the third bit sequence and the fourth bit sequence to the second bit position in a bit sequence of length N to obtain a sixth bit sequence includes: mapping the third bit sequence to the third bit position in the bit sequence of length N, and mapping the fourth bit sequence to the fourth bit position in the bit sequence of length N to obtain a fifth bit sequence, wherein the third bit position is the first K-K1+r-r1 bits of the second bit position sorted from high to low according to reliability, and the fourth bit position is the last N1 bits of the second bit position sorted from high to low according to reliability.

[0029] It can be understood that the relevant technical effects of the method of the third aspect mentioned above can also refer to the relevant introduction of the first aspect mentioned above, and will not be repeated here.

[0030] In a fourth aspect, a communication method is provided, which can be executed by a second communication device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the second communication device, or by a logical node, a logical module, or software that can realize all or part of the functions of the second communication device. For the convenience of expression, the following is an introduction to the method being executed by the second communication device. The method includes: obtaining a sequence to be decoded, the sequence to be decoded includes a first sequence and a second sequence. Fano decoding is performed on the first sequence to obtain a first bit sequence, and SC decoding is performed on the second sequence to obtain a second bit sequence. CRC check is performed on the first bit sequence and the second bit sequence. If the CRC check passes, the target bit sequence is determined based on the first bit sequence and the second bit sequence.

[0031] Optionally, the first sequence includes N1 bits, where the N1 bits are the last N1 bits of the M bits sorted from high to low according to reliability, and the M bits are the first M bits of the sequence to be decoded sorted from high to low according to reliability, and N1 and M are integers greater than or equal to 1.

[0032] The second sequence includes bits other than N1 bits in the sequence to be decoded.

[0033] Optionally, performing Fano decoding on the first sequence to obtain a first bit sequence may include: performing Fano decoding on the first K1+r1 bits in the first sequence sorted from high to low according to row weight according to a mapping relationship of the convolution transform to obtain the first bit sequence, where r1 is an integer greater than or equal to 1, and K1+r1 is less than or equal to N1.

[0034] Optionally, performing Fano decoding on the first sequence to obtain a first bit sequence, and performing SC decoding on the second sequence to obtain a second bit sequence, includes iterating a decoding path, performing Fano decoding on the first sequence according to the decoding path to obtain the first bit sequence, and performing SC decoding on the second sequence to obtain the second bit sequence. The decoding path is iterated if a CRC check fails.

[0035] Optionally, performing CRC check on the first bit sequence and the second bit sequence may include: when it is determined that decoding of the first bit sequence and the second decoding sequence is completed, performing CRC check on the first bit sequence and the second decoding sequence.

[0036] It can be understood that the relevant technical effects of the method of the fourth aspect mentioned above can also refer to the relevant introduction of the first aspect mentioned above, and will not be repeated here.

[0037] In a fifth aspect, a communication device is provided. The communication device includes: a module for executing the method of any one of aspects 1 to 4, such as a transceiver module and a processing module. For example, the transceiver module is configured to execute the transceiver function of the communication device, and the processing module is configured to execute functions of the communication device other than the transceiver function.

[0038] Optionally, the transceiver module may include a sending module and a receiving module, wherein the sending module is used to implement the sending function of the communication device of the fifth aspect, and the receiving module is used to implement the receiving function of the communication device of the fifth aspect.

[0039] Optionally, the communication device of the fifth aspect may further include a storage module, wherein the storage module stores a program or instruction. When the processing module executes the program or instruction, the communication device can execute the method of any one of the first to fourth aspects.

[0040] It can be understood that the communication device in the fifth aspect can be a terminal or a network device, or a chip (system) or other parts or components that can be set in a terminal or a network device, or a device that includes a terminal or a network device, or a component that completes part or all of the functions of a network device. This application does not limit this.

[0041] In addition, the technical effects of the communication device in the fifth aspect can refer to the technical effects of the first aspect mentioned above and will not be repeated here.

[0042] In a sixth aspect, a communication device is provided, comprising: a processor configured to execute the method of any one of the first to fourth aspects.

[0043] In one possible implementation, the communication device of the sixth aspect may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the communication device of the sixth aspect to communicate with other communication devices.

[0044] In one possible implementation, the communication device of the sixth aspect may further include a memory. The memory may be integrated with the processor or provided separately. The memory may be used to store the computer program and / or data involved in the method of any one of the first to fourth aspects.

[0045] In an embodiment of the present application, the communication device of the sixth aspect can be a terminal or network device of any one of the first to fourth aspects, or a chip (system) or other parts or components that can be set in the terminal or network device, or a device that includes the terminal or network device, or can be a component that completes part or all of the functions of the network device.

[0046] In addition, the technical effects of the communication device in the sixth aspect can refer to the technical effects of the method in any one of the first to fourth aspects, and will not be repeated here.

[0047] In a seventh aspect, a communication device is provided, comprising: a processor coupled to a memory, the processor configured to execute a computer program or instruction stored in the memory, so that the communication device performs the method of any one of the first to fourth aspects.

[0048] In one possible implementation, the communication device may further include a transceiver. The transceiver may be a transceiver circuit or an interface circuit. The transceiver may be used for the communication device to communicate with other communication devices.

[0049] In a possible implementation, the communication device further includes the memory for storing the above-mentioned computer program or instruction. Optionally, the memory and the processor are integrated together.

[0050] In an embodiment of the present application, the communication device of the seventh aspect can be a terminal or network device of any one of the first to fourth aspects, or a chip (system) or other parts or components that can be set in the terminal or network device, or a device that includes the terminal or network device.

[0051] In addition, the technical effects of the communication device in the seventh aspect can refer to the technical effects of the method in any one of the first to fourth aspects, and will not be repeated here.

[0052] In an eighth aspect, a communication system is provided, comprising: a first communication device for executing the methods of the first and third aspects, and a second communication device for executing the methods of the second and fourth aspects.

[0053] In a ninth aspect, a computer-readable storage medium is provided, comprising: a computer program or instructions; when the computer program or instructions are executed on a computer, the method of any one of the first to fourth aspects is implemented.

[0054] In a tenth aspect, a computer program product is provided, comprising a computer program or instructions, which, when executed on a computer, enables the method of any one of the first to fourth aspects to be implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] FIG1 is a schematic diagram of the encoding process of the MPAC code;

[0056] FIG2 is a schematic diagram showing the construction of a rate configuration subscript set for MPAC codes;

[0057] FIG3 is a flowchart of HFSC decoding; FIG.

[0058] FIG4 is a schematic diagram of the encoding and decoding process of the CRC-Polar code;

[0059] FIG5 is a first structural diagram of a communication system provided in an embodiment of the present application;

[0060] FIG6 is a second structural diagram of a communication system provided in an embodiment of the present application;

[0061] FIG7 is a schematic diagram of an application scenario of a communication system provided in an embodiment of the present application;

[0062] FIG8 is a schematic diagram 1 of the process of the communication method provided in an embodiment of the present application;

[0063] FIG9 is a schematic diagram of a code rate configuration subscript set provided in an embodiment of the present application;

[0064] FIG10 is a schematic diagram of a first encoding process of a CRC-MPAC code according to an embodiment of the present application;

[0065] FIG11 is a schematic diagram of a decoding process of a CRC-MPAC code provided in an embodiment of the present application;

[0066] FIG12 is a first schematic diagram of performance comparison provided by an embodiment of the present application;

[0067] FIG13 is a second schematic diagram of performance comparison provided by an embodiment of the present application;

[0068] FIG14 is a second schematic diagram of the process of the communication method provided in an embodiment of the present application;

[0069] FIG15 is a second schematic diagram of the encoding process of the CRC-MPAC code provided in an embodiment of the present application;

[0070] FIG16 is a schematic diagram of error correction performance provided by an embodiment of the present application;

[0071] FIG17 is a first structural diagram of a communication device provided in an embodiment of the present application;

[0072] FIG18 is a second structural diagram of the communication device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0073] 1. Channel Coding

[0074] Channel coding is a key technology for ensuring reliable information transmission in communication systems. By introducing mathematical structure and redundancy to the transmitted information bits at the transmitting end, the communication system gains the ability to correct errors. With the advent of the Internet of Everything (IoE), new applications in scenarios such as ultra-reliable low-latency communication (uRLLC) and massive machine-type communication (mMTC) pose new challenges to channel coding, especially for medium- and short-length channel coding. CRC-assisted Polar codes are a competitive medium- and short-length code that can achieve impressive decoding performance when assisted by the successive cancellation list (SCL) decoding algorithm.

[0075] 2. MPAC code

[0076] PAC code is a coding scheme based on Polar code that can approach the theoretical performance of finite code length. However, achieving excellent performance requires the assistance of the Fano decoding algorithm, which has the problems of high decoding complexity and uncontrollable decoding delay.

[0077] To address the above-mentioned problems with PAC codes and their Fano decoding, MPAC codes and HFSC decoding based on the idea of ​​partial convolution and a hybrid decoding strategy have been proposed. Compared with the original PAC codes and Fano decoding, the main difference of this scheme lies in the "partial convolution" coding structure and the "hybrid strategy" decoding algorithm. It has a better compromise advantage between decoding performance and complexity, and effectively makes up for the defect that the PAC code scheme with a length of 512 codes is difficult to achieve ideal decoding performance under the limited decoding complexity.

[0078] Figure 1 shows the relationship between (N,K)-(N c ,K c ) Schematic diagram of the MPAC code encoding process, where the parameter N c Determine the convolution transform The parameter Kc determines the number of information bits for convolution transformation.

[0079] As shown in Figure 1, the specific encoding process is described as follows: Information vector First divided into Two sub-bit vectors of the form . Among them, the sub-bit vector The vector is obtained through code rate configuration I Afterwards The codeword is obtained by preprocessing the convolution transform with a code rate of 1 The specific encoding process is Among them, the convolution transformation matrix G′ c The generating polynomial g(x)=g0+g1x+…+g m x m Determine that its constraint length is m+1. Sub-bit vector The codeword after convolution transformation They are transmitted together through the polarization channel under the effect of code rate configuration II. Let the vector after code rate configuration II be Then the codeword of MPAC code will be We get the polarization transformation matrix in, is the Polar kernel matrix, Expressed as a Kronecker product operation.

[0080] 3. Bitrate Configuration

[0081] The code rate configuration is used to specify which positions carry message bits. It is usually represented by a vector of a preset length. A 0 in the i-th position indicates that position i is a frozen bit, and a 1 in the i-th position indicates that position i carries a message. The above-mentioned code rate configurations I and II refer to the process of constructing a long vector from a short vector. The short vector is generally called an "information vector" and the long vector is generally called a "carrier vector." The construction process is that the information vector is placed in certain positions in the carrier vector according to a regular pattern, while the remaining positions are generally set to 0 bits. The position of the information vector in the carrier vector is usually determined by the information subscript set of the code rate configuration. Figure 2 is a schematic diagram of the code rate configuration subscript set construction for MPAC codes.

[0082] As shown in Figure 2, the MPAC coding rate configuration scheme consists of the Gaussian approximation (GA) criterion and the improved reed muller-Polar (iRMP) criterion. Rate configuration II uses the GA-based polarization channel reliability criterion to obtain three sets of position subscripts with different reliability levels, which are used to place the directly transmitted sub-information vectors. Codeword after convolution transformation And the frozen bit sequence 0. Assume that the reliability order obtained by GA is (j0,j1,…,j N-1 ) GA ,satisfy in, represents the mean of the log likelihood ratio (LLR) values ​​estimated by the GA method, The larger the value, the more polarization channels The more reliable. On this basis, we get the KK with the highest reliabilityc +N c The polarization channel subscripts form the set Furthermore, the less reliable N in set A can be determined c Positions constitute a set The position of the corresponding carrier vector will be placed with the codeword after convolution transformation Right now The sub-information vector will be transmitted in the polarization sub-channel corresponding to the set P. Similarly, the polarization sub-channel determined by the set A\P will be used to directly transmit the sub-information vector And the set A c The polarization subchannel of set A will transmit the frozen bit sequence 0 to ensure reliable information transmission, where set A\P includes the polarization subchannels in set A except the polarization subchannels in set P. Set A c The polarization subchannel of is the polarization subchannel in N polarization subchannels except the polarization subchannel of set A. And the code rate configuration I is to further determine the sub-information vector for convolution transformation In the carrier vector The purpose is to ensure that the code weight distribution of the constructed MPAC code is not too bad. Specifically, the polarization sub-channels corresponding to the set P are reordered according to the iRMP criterion, and K is obtained. c subchannel indexes, the sorting process is: define r(i) = 2 b(i) , where r(i) corresponds to the polarization transformation matrix G P The Hamming weight of the i-th row (i.e., row weight), b(i) represents the number of 1s in the binary representation of i. The subscript with the heavier row weight is preferred, i.e., r(i1)>r(i2). When the row weights are the same, the subscript with the higher reliability of the subchannel is further selected, i.e., r(i1)=r(i2), and The above i1 will always have a higher sorting priority than i2. Thus, the Kc positions that meet the iRMP criteria are prioritized to form the set Where (j [0] ,j [1] ,…,j [N-1] ) iRMP The sorted results.

[0083] 4. HFSC decoding

[0084] Figure 3 is a flowchart of the HFSC decoding process. HFSC decoding is a serial process that is performed node by node on the decoding binary tree, and finally a complete decoding path is obtained as output. During the decoding process, the SC decoding process will be applied to solve the polarization transformation, thereby obtaining the polarization transformation input bit. The decision LLR value On this basis, different types of decoding nodes will adopt different decoding strategies, that is, SC decoding and Fano decoding will be called respectively according to the node position i.

[0085] As shown in Figure 3, the bit sequence to be decoded is received Assume that the decoding node is currently Decoding is performed in the following cases: When i∈P, the bits at the convolution transform codeword position are decoded, and the Fano decoding strategy will be called. The node is allowed to fall back during the decoding process. It first needs to request the SC process to determine the LLR value. Calculate the path metric from this Then, the tree search process with path metric priority is performed, and Fano decoding is used to obtain the information vector Fano decoding is specifically divided into the following two cases: 1. When i∈B, it is the information bit position corresponding to the convolution transformation, and the node fallback search is allowed. Assume that the current search determines that the extended decoding node is i′≤i, the information bit for convolution transformation is determined by the mapping relationship of convolution transformation and returns Give SC process; 2. When i∈P\B, it is the frozen bit position corresponding to the convolution transformation, and the direct judgment and returns Give SC process.

[0086] when When the bit position of the direct transmission bit is decoded, the SC decoding strategy will be called, and the node is not allowed to fall back during this process. It first calculates the decision LLR value Obtained by direct SC judgment And update the path metric value SC decoding obtains information vector SC decoding is specifically divided into the following two cases: 1. When i∈A\P, in order to decode the directly transmitted information bits, directly according to the judgment LLR value get 2. When i∈A c When directly transmitting frozen bits, the direct decision Finally, you also need to Return to the SC process.

[0087] Finally, the complete information vector is obtained through information extraction

[0088] 5. CRC-Polar code

[0089] The CRC-Polar code is obtained by concatenating the CRC code with the Polar code. The 24-bit CRC in the CRC-aided-Polar (CA-Polar) code has both error correction and error detection capabilities. Among them, it can be considered that the 3-bit CRC is used for error correction and the remaining 21-bit CRC is used for error detection.

[0090] Figure 4 is a schematic diagram of the encoding and decoding process of the CRC-Polar code. As shown in Figure 4, the given CRC-Polar code parameters are as follows: K is the information bit size, r is the check bit length generated after CRC encoding, and N = 2 n is the code length of the Polar code. In the encoding module, CRC encoding is first performed on the K information bits to generate a CRC codeword K+r, and then polar encoding is performed through the polar code encoder to obtain a CRC-Polar code of length N. After passing through the transmission channel w, the receiver demodulates the received symbols and performs Polar decoding, and then decodes them through the polar code decoder and CRC check to obtain K information bits. For an (N,K)CRC-Polar concatenated code, its inner code is a (N,K+r)Polar code, and the outer code is a (K+r,K) CRC code. The specific process of CRC encoding is as follows: Given an information vector The corresponding polynomial expression is m(x)=m0+m1x+…+m K-1 x K-1 , the corresponding CRC codeword polynomial d(x) is: d(x)=x r ·m(x)+(x r m(x))mod p(x)

[0091] Where p(x) is the generating polynomial of the system CRC, p(x)=p0+p1x+…+p r x r The CRC code word can be obtained by the CRC code word polynomial d(x)

[0092] The specific process of polarization coding is as follows: and are the information carrying vector and codeword vector of CRC-Polar code respectively. The reliability of the corresponding N polarized channels is sorted, and the most reliable first K+r positions are selected to form the information subscript set: The remaining positions are formed into a frozen subscript set The encoded CRC codeword Fill to middle The corresponding position, the rest of the positions are fixed to 0, thus obtaining the complete information carrying vector It can be obtained that the codeword of CRC-Polar code is

[0093] Decoding scheme corresponding to CRC-Polar code:

[0094] After transmitting W through the channel, the receiver demodulates the received symbols and then performs Polar decoding. In particular, during decoding, the decoder does not distinguish between the K-bit information bits and the r-bit CRC check bits. The decoder will simultaneously obtain the K+r-bit CRC candidate codewords. The candidate codewords are then input into the CRC check module. The decoding module will determine the final output based on the CRC check result. If no candidate codeword passes the check, the decoding is declared to have failed. If a candidate codeword passes the check, the most reliable candidate codeword is selected and the K-bit information bits are extracted. This is the decoding output result.

[0095] It can be seen that the code spectrum of CA-Polar codes still has room for improvement, and their error correction capabilities need to be enhanced. The MPAC HFSC decoding algorithm can perform a fallback Fano search strategy at less reliable polarization subchannel locations during the decoding process, thereby obtaining a more reliable decoding path. However, this process still cannot guarantee the correctness of the decoding output path, and there is no list to improve fault tolerance, which affects the decoding performance of the entire scheme. Table 1 shows the distribution of first-bit decoding errors for the (512, 256)-(128, 64) MPAC code under a limited decoding complexity of η = 1024 (η is the normalized complexity value, corresponding to the number of LLR calculations Φ = ηN log2N). The number of simulated error frames is 10,000.

[0096] Table 1: Distribution of first bit decoding errors for MPAC codes (512,256)-(128,64)

[0097] It can be seen that due to the incomplete channel polarization phenomenon, the first error will be more likely to occur at the bit transmission position where the convolution transform is performed. In response to the above technical problems and the statistics of the first decoding error distribution in Table 1, the embodiment of the present application proposes the following technical solutions.

[0098] The technical solution in this application will be described below with reference to the accompanying drawings.

[0099] The technical solutions of the embodiments of the present application can be applied to various communication systems, such as wireless network (Wi-Fi) systems, vehicle-to-everything (V2X) communication systems, device-to-device (D2D) communication systems, Internet of Vehicles communication systems, fourth-generation (4G) mobile communication systems such as LTE systems, fifth-generation (5G) mobile communication systems such as NR systems, and communication systems evolved after 5G such as 6G.

[0100] In the embodiment of the present application, "indication" may include direct indication and indirect indication, and may also include explicit indication and implicit indication. The information indicated by a certain information (such as the first indication information, the second indication information, or the third indication information below) is called information to be indicated. In the specific implementation process, there are many ways to indicate the information to be indicated, such as but not limited to, the information to be indicated can be directly indicated, such as the information to be indicated itself or the index of the information to be indicated. The information to be indicated can also be indirectly indicated by indicating other information, where there is an association between the other information and the information to be indicated. It is also possible to indicate only a part of the information to be indicated, while the other parts of the information to be indicated are known or agreed in advance. For example, the indication of specific information can be achieved by means of the arrangement order of each piece of information agreed in advance (such as specified in the protocol), thereby reducing the indication overhead to a certain extent. At the same time, the common parts of each piece of information can be identified and indicated uniformly to reduce the indication overhead caused by indicating the same information separately.

[0101] In addition, the specific indication method can also be various existing indication methods, such as but not limited to the above-mentioned indication methods and various combinations thereof. As can be seen from the above, for example, when it is necessary to indicate multiple pieces of information of the same type, different indication methods may be used for different pieces of information. During the specific implementation process, the desired indication method can be selected according to specific needs. The embodiments of the present application do not limit the selected indication method. As such, the indication methods involved in the embodiments of the present application should be understood to cover various methods that can enable the party to be indicated to obtain the information to be indicated.

[0102] It should be understood that the information to be indicated can be sent as a whole or divided into multiple sub-information and sent separately, and the sending period and / or sending time of these sub-information can be the same or different. The specific sending method is not limited in the embodiments of this application. Among them, the sending period and / or sending time of these sub-information can be predefined, for example, predefined according to a protocol, or can be configured by the sending node device by sending configuration information to the receiving node device.

[0103] "Pre-definition" or "pre-configuration" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device, and the embodiments of the present application do not limit the specific implementation method. Among them, "saving" can mean saving in one or more memories. One or more memories can be set separately or integrated in an encoder or decoder, a processor, or a communication device. One or more memories can also be partially set separately and partially integrated in a decoder, a processor, or a communication device. The type of memory can be any form of storage medium, and the embodiments of the present application do not limit this.

[0104] The "protocol" involved in the embodiments of the present application may refer to a protocol family in the communication field, a standard protocol with a similar protocol family frame structure, or a related protocol used in future communication systems. The embodiments of the present application do not make specific limitations on this.

[0105] In the embodiments of the present application, descriptions such as "when...", "in the case of...", "if" and "if" all mean that the device will perform corresponding processing under certain objective circumstances. It does not limit the time, nor does it require the device to perform judgment actions when implemented, nor does it mean that there are other limitations.

[0106] In the description of the embodiments of the present application, unless otherwise specified, " / " indicates that the objects associated with each other are in an "or" relationship. For example, A / B can represent A or B. "And / or" in the embodiments of the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. A and B can be singular or plural. In addition, in the description of the embodiments of the present application, unless otherwise specified, "multiple" refers to two or more than two. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or multiple. In addition, in order to facilitate the clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with basically the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit differences. At the same time, in the embodiments of the present application, words such as "exemplary" or "for example" are used to indicate examples, illustrations or explanations. Any embodiment or implementation described as "exemplary" or "for example" in the embodiments of the present application should not be interpreted as being more preferred or more advantageous than other embodiments or implementations. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a concrete way for easy understanding.

[0107] The network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field will know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0108] To facilitate understanding of the embodiments of the present application, a communication system applicable to the embodiments of the present application is first described in detail using the communication system shown in Figure 5 as an example. For example, Figure 5 is a schematic diagram of the architecture of a communication system applicable to the method provided in the embodiments of the present application.

[0109] The communication system may include: a first communication device and a second communication device. The communication devices may be terminals or network devices, such as the first communication device being a terminal and the second communication device being a network device, or the first communication device being a network device and the second communication device being a terminal. Of course, communication between terminals or between network devices may also be possible.

[0110] In a specific example, as shown in FIG5 , the communication system mainly includes at least one of the following: a terminal, and a network device, such as an access network device.

[0111] In one possible scenario, the communication system can be applied to 5G or future 6G communication systems. For example, as shown in FIG6 , the communication system 10 includes a radio access network (RAN) 100, a core network (CN) 200, and the Internet 300. RAN 100 includes at least one RAN node (e.g., 110a and 110b in FIG6 , collectively referred to as 110) and at least one terminal (e.g., 120a-120j in FIG6 , collectively referred to as 120). RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in FIG6 ). Terminal 120 is wirelessly connected to RAN node 110. RAN node 110 is wirelessly or wiredly connected to core network 200. The core network devices in core network 200 and RAN node 110 in RAN 100 can be separate physical devices, or they can be a single physical device that integrates core network logical functions and radio access network logical functions.

[0112] The RAN 100 may be a 3GPP-related cellular system, such as a 4G or 5G mobile communication system, or a future-oriented evolutionary system (such as a 6G mobile communication system). The RAN 100 may also be an open access network (O-RAN or ORAN), a cloud radio access network (CRAN), or a Wi-Fi system. The RAN 100 may also be a communication system that integrates two or more of the above systems.

[0113] RAN node 110, sometimes also referred to as access network equipment, RAN entity, or access node, constitutes part of the communication system and facilitates wireless access for terminals. Multiple RAN nodes 110 in the communication system 10 can be of the same type or different types. In some scenarios, the roles of RAN node 110 and terminal 120 are relative. For example, network element 120i in Figure 6 can be a helicopter or drone, which can be configured as a mobile base station. For terminal 120j accessing the RAN 100 via network element 120i, network element 120i is a base station; however, for base station 110a, network element 120i is a terminal. RAN node 110 and terminal 120 are sometimes referred to as communication devices. For example, network elements 110a and 110b in Figure 6 can be understood as communication devices with base station functionality, and network elements 120a-120j can be understood as communication devices with terminal functionality.

[0114] In one possible scenario, a RAN node may be a base station, an evolved NodeB (eNodeB), a transmission reception point (TRP), a next generation NodeB (gNB), a next generation base station in a 6G mobile communication system, a base station in a future mobile communication system, or an access point (AP) in a Wi-Fi system. A RAN node may be a macro base station (such as 110a in FIG6 ), a micro base station or an indoor station (such as 110b in FIG6 ), a relay node or a donor node, or a wireless controller in a CRAN scenario. Optionally, a RAN node may also be a server, a wearable device, a vehicle or an onboard device. For example, an access network device in vehicle to everything (V2X) technology may be a road side unit (RSU). All or part of the functions of a RAN node in this application may also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). A RAN node in this application may also be a logical node, a logical module, or software that can implement all or part of the functions of a RAN node.

[0115] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, and different RAN nodes respectively implement part of the functions of the base station. For example, the RAN node can be a centralized unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU). The CU and DU can be set separately, or they can be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH).

[0116] In different systems, CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, CU may also be called O-CU (Open CU), DU may also be called O-DU, CU-CP may also be called O-CU-CP, CU-UP may also be called O-CU-UP, and RU may also be called O-RU. For the convenience of description, this application uses CU, CU-CP, CU-UP, DU and RU as examples for description. Any unit of CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0117] It is understood that the above-mentioned RAN node can be a newly defined name, and RAN node can also be expressed in different ways, such as access node, network device, wireless access node, etc., without limitation. Unless otherwise specified in this application, network device is used to express it.

[0118] Terminals can also be referred to as terminal devices, user equipment (UE), mobile stations, or mobile terminals. They can be widely used in various scenarios, such as device-to-device (D2D), vehicle-to-everything (V2X) communication, machine-type communication (MTC), the Internet of Things (IoT), smart point-of-sale (POS), customer-premises equipment (CPE), virtual reality (VR), augmented reality (AR), industrial control, autonomous driving, telemedicine, smart grids, smart furniture, smart offices, smart wearables (such as smart watches, smart bracelets, pedometers, and smart glasses), smart transportation, and smart cities. Terminals can be mobile phones, tablets, computers with wireless transceiver capabilities, wearable devices, vehicle devices (such as complete vehicle devices, vehicle-mounted modules, vehicle-mounted chips, on-board units (OBUs), or telematics boxes (T-BOXs)), drones, helicopters, airplanes, ships, robots, robotic arms, smart home devices, and satellite terminals. The embodiments of the present application do not limit the device form of the terminal.

[0119] The communication system of the embodiment of the present application is applicable to the coding scenario and can be implemented by a dedicated chip ASIC, a programmable chip FPGA, or by software (program code in a memory). As shown in Figure 7, the communication system mainly includes a source, source coding, channel coding, modulation, channel, demodulation, channel decoding, source decoding and a destination, wherein the coding part is located between source coding and modulation, and is responsible for channel coding the bits generated by the source, and then after modulation, the modulation symbols are sent through a noisy channel to the receiving end for demodulation, and then channel decoding is performed, and the channel part is located between demodulation and source decoding, and is responsible for recovering the source bit stream. The core innovation of the embodiment of the present application mainly relates to channel coding and channel decoding parts.

[0120] In this communication system, the first communication device introduces CRC coding at the coding end on the basis of convolution of part of the bit sequence to be transmitted, that is, based on the coding framework of MPAC partial convolution. This can not only obtain a better code weight distribution than the MPAC code, that is, it can obtain a larger coding gain, but also can assist the MPAC code in verifying the output decoding path in the decoding stage through the CRC code, increase the path error detection capability, thereby improving the error correction capability of the decoding stage and improving the decoding performance.

[0121] The embodiments of this application do not limit the device form factor of the network device. The device used to implement the function of the network device can be a network device; it can also be a device that supports the network device to implement the function, such as a chip system. The device can be installed in the network device or used in conjunction with the network device. In the embodiments of this application, the chip system can be composed of chips or can include chips and other discrete components.

[0122] The following will specifically describe the interaction process between each network element / device in the above communication system through a method embodiment in conjunction with Figure 8. The communication method provided in the embodiment of the present application can be applied to the above communication system and specifically applied to various scenarios / processes mentioned in the above communication system, which are described in detail below.

[0123] Figure 8 is a flow chart of a communication method according to an embodiment of the present application. The communication method is applicable to the above-mentioned communication system and mainly involves interaction between a first communication device and a second communication device.

[0124] As shown in Figure 8, the process of the communication method is as follows:

[0125] S801: A first communication device obtains a bit sequence to be sent.

[0126] The bit sequence to be sent may be a sequence containing multiple information bits. The bit sequence to be sent may include a first bit sequence and a second bit sequence. The number of information bits contained in each of the first bit sequence and the second bit sequence may be determined according to actual conditions and needs. For example, the bit sequence to be sent includes K information bits, the first bit sequence includes K1 information bits of the K information bits, and the second bit sequence includes K-K1 information bits of the K information bits, where K and K1 are integers greater than or equal to 1, and K1 is less than or equal to K. The bit sequence to be sent may also be represented by an information vector. For example, the bit sequence to be sent includes an information vector Representing K information bits from 0 to K-1, divided into Two sub-bit vectors of the form, that is, the first bit sequence is Representing K1 information bits from 0 to K1-1, the second bit sequence is Represents K-K1 information bits from K1 to K-1.

[0127] S802: The first communication device performs CRC encoding on the first bit sequence to obtain a third bit sequence, and performs convolution transformation on the third bit sequence to obtain a fourth bit sequence.

[0128] It can be understood that the third bit sequence may include the information bits and check bits in the first bit sequence, and the check bits may be generated by performing CRC encoding on the first bit sequence. For example, the first bit sequence includes K1 information bits, and r check bits are generated by performing CRC encoding on the K1 information bits. The convolution transformation of the third bit sequence may be a convolution transformation of the third bit sequence with a code rate of 1, for example, by using the convolution transformation matrix G′ c Perform convolution transformation, where the convolution transformation matrix G′ c The generating polynomial g(x)=g0+g1x+…+g m x m Determine that its constraint length is m+1.

[0129] In one possible implementation, performing cyclic redundancy check (CRC) encoding on the first bit sequence to obtain a third bit sequence may include: performing CRC encoding on the first bit sequence to obtain a CRC codeword, and performing code rate configuration on the CRC codeword to obtain the third bit sequence.

[0130] It can be understood that the CRC codeword may include information bits and check bits in the first bit sequence. The first bit sequence may be represented by an information vector. For example, the first bit sequence is That is, the first bit sequence includes bits from m0 to m K1-1The K1 information bits of the first bit sequence are CRC-encoded to obtain the CRC codeword vector Where r is the number of CRC check bits, specifically the polynomial d(x)=x corresponding to the CRC codeword r ·m(x)+(x r m(x)) mod p(x) for CRC encoding, where m(x) is the polynomial corresponding to the first bit sequence, expressed as m(x) = m0 + m1x + ... + m K1-1 x K1-1 , p(x) is the generating polynomial of CRC, defined as p(x)=p0+p1x+…+p r x r It can be seen that only performing CRC encoding on a part of the bit sequence to be transmitted can not only increase the verification of the decoding path through CRC, but also reduce the complexity of encoding and decoding.

[0131] Optionally, the bit sequence to be transmitted includes K information bits, the first bit sequence is K1 information bits of the K information bits, and the CRC codeword includes K1 information bits and r check bits, where K, K1, and r are integers greater than or equal to 1; and performing code rate configuration on the CRC codeword to obtain a third bit sequence may include: the first communication device obtains a bit sequence of length N1, and maps the CRC codeword to K1+r first bits in the bit sequence of length N1 to obtain the third bit sequence, where K1+r is less than or equal to N1. The first bits are the first K1+r bits in the bit sequence of length N1, sorted from high to low according to row weight.

[0132] It can be understood that the code rate configuration process can be a process of determining the position of the bits included in the CRC codeword in the third bit sequence, and the code rate configuration of the CRC codeword can be performed based on the iRMP criterion. The bit sequence of length N1 can be a sequence consisting of bits corresponding to the N1 polarized channels after sorting the N1 polarized channels using the iRMP criterion. The K1+r first bits can correspond to the first K1+r polarized channels of the N1 polarized channels. When sorting based on the iRMP criterion, the polarized channel with higher row weight is preferentially selected. If the row weights are the same, the polarized channel with higher reliability is selected, where the row weight is related to the number of 1s in the binary representation corresponding to the position of the polarized channel. The sorting process based on the iRMP criterion can also refer to the description of the MPAC code above and will not be repeated here. For example, N1 polarized channels are sorted according to the iRMP criterion as channel #0, channel #1, channel #2, ..., channel #N1-1. Channel #0 has the highest row weight. The first K1+r channels that meet the iRMP criterion are determined, namely, channel #0, channel #1, channel #2, ..., channel #K1+r-1. CRC codewords are then placed (padded) into the bit positions corresponding to the first K1+r polarized channels in the bit sequence of length N1, resulting in a third bit sequence of length N1. In this way, CRC coding is introduced based on the MPAC code framework, and the placement of the CRC codewords is designed, resulting in a better code weight distribution than MPAC codes, which can achieve greater coding gain.

[0133] In addition, a bit sequence of length N1 can be represented by a vector. For example, a bit sequence of length N1 is a carrier vector Contains N1 bits, and the CRC codeword vector Place (fill) to The first K1+r positions with the highest row weight are selected to obtain the complete bearing vector (the third bit sequence)

[0134] S803: The first communication device performs polarization coding according to the second bit sequence and the fourth bit sequence to obtain a coded bit sequence.

[0135] The fourth bit sequence is obtained by convolving the third bit sequence by the first communication device. For example, the third bit sequence is represented by the carrying vector: right After the convolution transform with code rate 1, the code word is obtained The second bit sequence and the fourth bit sequence can be polarization-encoded by using a polarization conversion matrix. The polarization conversion matrix can be referred to the description of the MPAC code and will not be described in detail here.

[0136] In a possible implementation, S803 may include: the first communication device performs code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence, and performs polarization coding on the fifth bit sequence to obtain a coded bit sequence.

[0137] It can be understood that the code rate configuration for the second bit sequence and the fourth bit sequence may be to determine the positions of the bits respectively included in the second bit sequence and the fourth bit sequence in the fifth bit sequence.

[0138] Optionally, the fourth bit sequence has a length of N1, the to-be-transmitted bit sequence includes K information bits, and the second bit sequence is K-K1 information bits of the K information bits; and the first communication device performs code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence, which may include: the first communication device obtains a bit sequence of length N, and determines K-K1+N1 second bits based on the bit sequence of length N. The first communication device maps the second bit sequence and the fourth bit sequence to the second bit in the bit sequence of length N to obtain a fifth bit sequence. The second bits are the first K-K1+N1 bits in the bit sequence of length N, sorted from high to low according to reliability.

[0139] It is understood that the code rate of the second and fourth bit sequences can be configured based on the GA criterion. The bit sequence of length N can be a sequence consisting of bits corresponding to the N polarized channels after the N polarized channels are sorted by reliability using the GA criterion. The second bit can correspond to the polarized channel with the highest reliability among the N polarized channels (K-K1+N1). The sorting process based on the GA criterion can also be referred to the description of the MPAC code above and will not be repeated here.

[0140] For example, N polarized channels are sorted according to the GA criterion as channel #0, channel #1, channel #2, ..., channel #N-1. Channel #0 has the highest reliability. The first K-K1+N1 polarized channels are determined, namely, channel #0, channel #1, channel #2, ..., channel #K-K1+N1-1. The second bit sequence and the fourth bit sequence are then placed (padded) into the bit positions corresponding to the first K-K1+N1 polarized channels in the bit sequence of length N, to obtain a fifth bit sequence of length N.

[0141] For another example, as shown in Figure 9, N polarized channels are sorted according to the general agreement (GA). The K-K1+N1 polarized channels before reliability constitute set A. The K-K1+N1 polarized channels in set A, corresponding to positions in a bit sequence of length N, are used to place the second bit sequence and the fourth bit sequence. That is, these K-K1+N1 polarized channels are used to transmit the second bit sequence and the fourth bit sequence. Optionally, polarized channels in set A other than the K-K1+N1 polarized channels are used to transmit frozen bits.

[0142] Optionally, the first communication device maps the second bit sequence and the fourth bit sequence to the second bit position in a bit sequence of length N to obtain a fifth bit sequence, which may include: the first communication device maps the second bit sequence to the third bit position in the bit sequence of length N, and maps the fourth bit sequence to the fourth bit position in the bit sequence of length N to obtain a fifth bit sequence, wherein the third bit position is the first K-K1 bits of the second bit position sorted from high to low according to reliability, and the fourth bit position is the last N1 bits of the second bit position sorted from high to low according to reliability.

[0143] It is understood that the second bit sequence can be a sequence that is directly transmitted without undergoing CRC encoding and convolutional transformation. The first communications device places the second bit sequence in the third bit position with the highest reliability (K-K1) among the second bit positions, and places the fourth bit sequence in the fourth bit position with the highest reliability (N1) among the second bit positions. For example, as shown in Figure 9, according to the GA sorting of N polarized channels, the polarized channels with the highest reliability (K-K1+N1) before the reliability constitute set A, and the polarized channels with the lowest reliability (N1) after the reliability in set A constitute set P. The N1 polarized channels in set A, corresponding to the positions in the bit sequence of length N, are used to place the fourth bit sequence. That is, these N1 polarized channels are used to transmit the fourth bit sequence. The K-K1 polarized channels in set A, excluding set P, corresponding to the positions in the bit sequence of length N, are used to place the second bit sequence. That is, these K-K1 polarized channels are used to transmit the second bit sequence.

[0144] Optionally, the fourth bit corresponds to a bit sequence of length N1. That is, the first bit is the K1+r highest bit before the fourth bit. For example, as shown in Figure 9, the polarized channels in set P with the K1+r highest number of bits before the row weight constitute set B. The K1+r polarized channels in set A corresponding to the positions in the bit sequence of length N are used to place the fourth bit sequence. That is, these K1+r polarized channels are used to transmit CRC codewords. Optionally, the polarized channels in set P, excluding those in set B, are used to transmit frozen bits.

[0145] In order to introduce the above CRC-MPAC concatenated code encoding process, a specific example is given. Figure 10 is a schematic diagram of the encoding process of the (N, K)-(N1, K1) CRC-MPAC code, where the parameter N1 determines the convolution transformation. The dimension of the parameter K1 determines the number of information bits to be convolved. As shown in Figure 10, the specific encoding process is described as follows: Information vector First divided into Two sub-bit vectors of the form . Among them, the sub-bit vector The CRC codeword vector will be obtained by CRC encoding Then through Perform code rate configuration I to obtain vector Afterwards The codeword is obtained by preprocessing the convolution transform with a code rate of 1 Subbit vector The codeword after convolution transformation They are transmitted together through the polarization channel under the action of code rate configuration II. The vector after code rate configuration II is After polarization transformation, the coded bit sequence is obtained For the specific encoding process, please refer to the description of MPAC encoding.

[0146] S804: The first communication device outputs a coded bit sequence, and correspondingly, the second communication device obtains a sequence to be decoded.

[0147] The sequence to be decoded may include a first sequence and a second sequence. It is understood that the sequence to be decoded may correspond to a coded bit sequence output by the first communication device. After receiving the sequence to be decoded, the second communication device determines the first sequence and the second sequence based on the polarization channel (transmission position) of the transmitted sequence. The first sequence may be a convolutionally transformed bit sequence, and the second sequence may be a directly transmitted bit sequence.

[0148] Optionally, the first sequence may include N1 bits, where the N1 bits are the last N1 bits of the M bits sorted from high to low in terms of reliability, and the M bits are the first M bits of the sequence to be decoded sorted from high to low in terms of reliability, where N1 and M are integers greater than or equal to 1. The second sequence may include bits other than the N1 bits of the sequence to be decoded.

[0149] It can be understood that the M bits may be bits in the sequence to be decoded that are transmitted via the polarized channel with the first M highest reliabilities. These M bits correspond to the K-K1+N1 second bits mentioned in S803. The N1 bit may be bits in the M bits that are transmitted via the polarized channel with the second N1 highest reliabilities. These N1 bits correspond to the N1 fourth bits mentioned in S803. The bits other than the N1 bits in the sequence to be decoded are transmitted via the remaining polarized channel.

[0150] S805: The second communication device performs Fano decoding on the first sequence to obtain a first bit sequence, and performs SC decoding on the second sequence to obtain a second bit sequence.

[0151] During the decoding process of the sequence to be decoded, different decoding strategies are applied to different types of decoding nodes. Decoding nodes correspond to different bits, distinguishing whether the bits corresponding to the decoding nodes belong to the first sequence or the second sequence. Fano decoding is performed on the first sequence, and SC decoding is performed on the second sequence, respectively. This means that SC decoding and Fano decoding are invoked depending on the position of the decoding node. If the bit corresponding to the decoding node position is one of the N1 bits, or in other words, the decoding node position corresponds to a polarized channel with the highest N1 reliability after the aforementioned reliability, such as set P in Figure 9, then the decoding node position corresponds to a bit position that is convolutionally transformed, and Fano decoding is invoked. If the bit corresponding to the node position belongs to a bit other than the N1 bits in the sequence to be decoded, or in other words, the decoding node position corresponds to the residual polarized channel, then the decoding node position corresponds to a bit position that is directly transmitted, and SC decoding is invoked.

[0152] For example, referring to the set P in FIG9 , it is assumed that the decoding node Decode, when When the bit of the convolution transform codeword position is decoded, the Fano decoding strategy will be called, and the node is allowed to fall back during the decoding process. It first needs to request the SC process to determine the LLR value. Calculate the path metric from this And then the tree search process with path metric priority is carried out accordingly. When , the bits at the directly transmitted bit positions are decoded, and the SC decoding strategy will be called. The Fano decoding and SC decoding processes can refer to the above description of the MPAC code, which will not be repeated here.

[0153] Optionally, S805 may include: the second communication device performs Fano decoding on the first K1+r bits in the first sequence sorted from high to low according to the mapping relationship of the convolution transformation to obtain a first bit sequence, where r is an integer greater than or equal to 1, and K1+r is less than or equal to N1.

[0154] It can be understood that when Fano decoding is performed on the first sequence, if the bit corresponding to the decoding node is located in the first K1+r highest bits in the first sequence, it means that the decoding node position corresponds to the information bit position of the convolution transformation. The information bit to be convolution transformed can be determined based on the mapping relationship of the convolution transformation to obtain the first bit sequence. The bits in the first sequence other than the first K1+r bits are frozen bits, and the frozen bits can be bits set to 0.

[0155] S806: The second communication device performs a CRC check on the first bit sequence.

[0156] During the CRC check, the second communication device inputs the obtained K1+r-bit first bit sequence into the CRC check module to obtain the CRC check result. If the CRC check passes, the K1-bit information bit is extracted and subsequent SC decoding is continued, referring to the HFSC decoding operation, until the last decoding node. If the CRC check fails, the decoding fails.

[0157] Optionally, S806 may include: when it is determined that the decoding of the first bit sequence is completed, performing a CRC check on the first bit sequence.

[0158] It can be understood that during the Fano decoding process, whether the decoding of the first bit sequence is complete is determined by determining whether the current decoding node is at the last position of the codeword after the convolution transformation, that is, whether all nodes allowed for fallback search have been explored. If it is the last position, Fano decoding of the first sequence is complete, and a CRC check is performed on the first bit sequence. If it is not the last position, decoding continues based on the above decoding process.

[0159] Optionally, S805 may include: iterating the decoding path, the second communication device performing Fano decoding on the first sequence according to the decoding path to obtain the first bit sequence, wherein the decoding path is iterated if the CRC check fails.

[0160] It can be understood that the second communication device performs Fano decoding on the first sequence according to each decoding node of the decoding path, and performs CRC check when the Fano decoding of the first sequence is completed. If the CRC check fails, it is considered that the current decoding path has not passed the CRC check, and the decoding path is rolled back, returning to the Fano search strategy to search for a more correct and reliable decoding path, that is, the decoding path is iterated at least once until the first sequence is Fano decoded with the iterated decoding path and the CRC check passes.

[0161] In this way, the introduction of CRC check can ensure that when the decoding of all allowed fallback search nodes is completed at the last position of the convolutional coding codeword, if there is an error in the decoding path, the decoding path of FANO decoding can be fallen back, which can avoid direct decoding failure when there is an error in the current decoding path, thereby improving the accuracy of decoding.

[0162] S807: If the CRC check passes, the second communication device determines a target bit sequence according to the first bit sequence and the second bit sequence.

[0163] The first bit sequence may be information bits that undergo convolution transformation, for example, including K1 information bits. The second bit sequence may be information bits that are directly transmitted, for example, including K-K1 information bits. The target bit sequence may include the first bit sequence and the second bit sequence, for example, including K1 information bits and K-K1 information bits, resulting in K information bits.

[0164] In order to introduce the decoding process of the CRC-MPAC concatenated code, a specific example is given. FIG11 is a schematic diagram of the decoding process of the CRC-MPAC code. As shown in FIG11, the specific decoding process is described as follows: The second communication device receives the sequence to be decoded. After that, suppose that the decoding node When i∈P, the bits at the convolution transform codeword position are decoded, and the Fano decoding strategy will be called. The node is allowed to fall back during the decoding process. It first needs to request the SC process to determine the LLR value. Calculate the path metric from this And then the tree search process with path metric priority is carried out. Assume that the decoding node to be expanded is determined by Fano search. First, determine whether it is at the last position of the convolutional codeword, that is, whether all nodes that allow fallback search have been explored. If it is not the last position, perform the same operation as the original HFSC decoding; if it is the last position, perform CRC check, and if the CRC check passes, return Give the SC process, and continue the subsequent decoding as HFSC decoding until the last decoding node, and finally get it through Fano decoding and SC decoding Extracted If the CRC check fails, the current decoding path is considered illegal and the system returns to the Fano search strategy to search for a more correct and reliable decoding path. When the bit position of the direct transmission bit is decoded, the SC decoding strategy will be called and the decoding result is The Fano decoding and SC decoding processes can also refer to the above description of MPAC code.

[0165] In summary, by convolving part of the bit sequence to be transmitted, that is, based on the MPAC partial convolution coding framework, CRC coding is introduced at the coding end. This can not only obtain a better code weight distribution than the MPAC code, that is, a larger coding gain, but also assist the MPAC code in verifying the output decoding path in the decoding stage through the CRC code, thereby increasing the path error detection capability, thereby improving the error correction capability of the decoding stage and improving the decoding performance.

[0166] In a specific example, an additive white Gaussian noise (AWGN) channel and binary phase shift keying (BPSK) modulation are used for simulation experiments. The CRC code length used by the CRC-MPAC concatenated code is 8, and the CRC code generator polynomial is p(x)=1+x 2 +x 4 +x 6 +x 7 +x 8 The convolution transform generating polynomials used by MPAC code and CRC-MPAC concatenated code are both g(x)=1+x 2 +x 3 +x 5 +x 6 , the GA in the construction process adopts the signal-to-noise ratio E s / N0=0.0dB. In the HFSC decoding process, b The path metric is calculated with / N0=1.5dB, and the decoding step size is set to Δ=2. For PAC codes, the RM construction and the same convolution transform generator polynomial g(x) are used, and its Fano decoding parameters are the same as the above HFSC configuration. For CRC-Polar codes, the 5G NR reliable sequence is used for construction, where the CRC generator polynomial is p(x)=1+x+x 2 +x 8 In the experiment, a decoding complexity upper limit η was set for HFSC decoding and Fano decoding to simulate the complexity constraints in real applications. To more accurately analyze the source of the performance improvement, the simulation also presents the partial code weight spectrum distribution of each scheme based on sending all-zero codewords and using the SCL decoding method with L = 150,000. "a+" indicates that the actual value will be greater than the value of a, "blank" indicates that there is no codeword of that code weight, and "..." indicates that the number of codewords of that code weight is unknown.

[0167] FIG12 is a performance comparison diagram provided by an embodiment of the present application, showing the frame error rate (FER) and normalized complexity performance comparison of different coding schemes with N=512 and K=256. c ,K c ) are compared with the performance of MPAC code under the upper limit of decoding complexity η = 1024. Through the comparison, it can be found that the CRC-MPAC concatenated code can improve the performance of the same (N) under the condition of approximately the same average decoding complexity. c ,K c ) Parameter MPAC code frame error rate FER performance. At FER = 10 -5 When compared with PAC and CRC-Polar codes, the CRC-MPAC concatenated code scheme achieves performance gains of approximately 0.27, 0.45, and 0.60 dB, respectively. This is consistent with the improved code weight distribution (reduced number of minimum weight codewords) of the CRC-MPAC concatenated code compared to the MPAC code. When compared with PAC and CRC-Polar codes, the CRC-MPAC concatenated code scheme achieves advantages in decoding performance and complexity at high signal-to-noise ratios.

[0168] Table 2 shows the partial code re-spectral distribution of each scheme with N=512, K=256.

[0169] Table 2: Partial code re-spectral distribution of various schemes with N=512, K=256

[0170] It can be seen that the CRC-MPAC concatenated code has a better decoding performance and complexity trade-off compared to the MPAC code due to the introduction of a CRC code of length 8, that is, its code weight distribution is significantly improved.

[0171] FIG13 is a second performance comparison diagram of an embodiment of the present application, which is a performance comparison of different encoding and decoding schemes with N=512 and K=130. It shows the performance of CRC-MPAC concatenated codes with convolution parameters (Nc, Kc) of (137, 65), (146, 98), and (162, 98) respectively compared with MPAC codes under η=1024. It is also not difficult to see the advantages of CRC-MPAC concatenated codes over existing encoding and decoding schemes. Unlike FIG12, the CRC-MPAC concatenated code only shows a more obvious performance advantage at high signal-to-noise ratios, which is consistent with the advantages of the CRC-MPAC concatenated code in code weight distribution, that is, the progressive performance is more ideal.

[0172] Table 3 shows the partial code re-spectral distribution of each scheme with N=512, K=130.

[0173] Table 3: Partial code re-spectral distribution of various schemes with N=512, K=130

[0174] It can be seen that the CRC-MPAC concatenated code has a better decoding performance and complexity trade-off compared to the MPAC code due to the introduction of a CRC code of length 8, that is, its code weight distribution is significantly improved.

[0175] Figure 14 is a second flow chart of the communication method provided in an embodiment of the present application. This communication method is applicable to the above-mentioned communication system, and mainly involves the interaction between the first communication device and the second communication device. Descriptions such as "first" and "second" are described based on the granularity of the embodiment. For example, the information referred to by the "first bit sequence" to "sixth bit sequence" in the embodiment of the present application is different from the "first bit sequence" to "fifth bit sequence" in the previous embodiment, and the "first bit position" to "fourth bit position" are also different from the information referred to by the "first bit position" to "fourth bit position" in the previous embodiment.

[0176] As shown in Figure 14, the process of the communication method is as follows:

[0177] S1401: A first communication device obtains a bit sequence to be sent.

[0178] The bit sequence to be sent can refer to the description of S801 to S807 and will not be described in detail here.

[0179] S1402: The first communication device performs cyclic redundancy check (CRC) encoding on a bit sequence to be sent to obtain a first bit sequence.

[0180] It can be seen that the difference between the embodiment of the present application and the previous embodiment lies in the different position of the CRC encoding module. The previous embodiment only performs CRC encoding on part of the information bits involved in the convolution. The embodiment of the present application performs CRC encoding on the bit sequence to be transmitted, that is, CRC encoding is performed before MPAC encoding. All information bits participate in CRC encoding, so that the CRC check has the ability to check all information bits of the bit sequence to be transmitted. In the embodiment of the present application, the first bit sequence is a CRC codeword after CRC encoding of the bit sequence to be transmitted. The first bit sequence may include a second bit sequence and a third bit sequence. The second bit sequence may be part of the information bits participating in the convolution transform, and the third bit sequence may be part of the information bits directly transmitted. The second bit sequence and the third bit sequence each contain a part of CRC check bits. For example, the bit sequence to be transmitted includes K information bits, the first bit sequence includes K information bits and r check bits, the second bit sequence includes K1 information bits and r1 check bits, and the third bit sequence includes K-K1 information bits and r-r1 check bits, wherein K1 information bits are among the K information bits, and r1 check bits are among the r check bits. K, K1, r, and r1 are integers greater than or equal to 1, r1 is less than or equal to r, and K1 is less than or equal to K.

[0181] S1403: The first communication device performs a convolution transform on the second bit sequence to obtain a fourth bit sequence.

[0182] The convolution transformation of the second bit sequence may refer to the description of the convolution transformation of the third bit sequence in S801 to S807, which will not be repeated here.

[0183] Optionally, performing a convolution transform on the second bit sequence to obtain the fourth bit sequence may include: performing code rate configuration on the second bit sequence to obtain a fifth bit sequence; and performing a convolution transform on the fifth bit sequence to obtain the fourth bit sequence.

[0184] It can be understood that, in the embodiment of the present application, configuring the code rate for the second bit sequence may be determining the position of the bits in the second bit sequence in the fifth bit sequence.

[0185] Optionally, the bit sequence to be transmitted may include K information bits, the first bit sequence includes K information bits and r check bits, and the second bit sequence includes K1 information bits of the K information bits and r1 check bits of the r check bits, where K, K1, r, and r1 are integers greater than or equal to 1; performing code rate configuration on the second bit sequence to obtain a fifth bit sequence includes: obtaining a bit sequence of length N1. Mapping the second bit sequence to K1+r1 first bits in a bit sequence of length N1 to obtain a fifth bit sequence, where K1+r1 is less than or equal to N1. The first bits are the first K1+r1 bits in the bit sequence of length N1, sorted from high to low according to row weight.

[0186] The code rate of the second bit sequence may be configured according to the iRMP criterion. For example, reference may be made to the description of the code rate configuration of the CRC codeword in S801 to S807 , which will not be described in detail here.

[0187] S1404: The first communication device performs polarization coding according to the third bit sequence and the fourth bit sequence to obtain a coded bit sequence.

[0188] Optionally, performing polarization coding on the third bit sequence and the fourth bit sequence to obtain a coded bit sequence may include: performing code rate configuration on the third bit sequence and the fourth bit sequence to obtain a sixth bit sequence, and performing polarization coding on the sixth bit sequence to obtain the coded bit sequence.

[0189] The code rate configuration for the third bit sequence and the fourth bit sequence may be performed according to the GA criterion. For example, reference may be made to the description of the code rate configuration for the second bit sequence and the fourth bit sequence in S801 to S807 , which will not be repeated here.

[0190] Optionally, the fourth bit sequence has a length of N1, the to-be-transmitted bit sequence includes K information bits, and the second bit sequence includes K-K1 information bits of the K information bits and r-r1 parity bits of the r parity bits. Polar coding is performed on the third and fourth bit sequences to obtain a sixth bit sequence, including: obtaining a bit sequence of length N. Determining K-K1+r-r1+N1 second bits based on the bit sequence of length N. Mapping the third and fourth bit sequences to the second bits of the bit sequence of length N to obtain a sixth bit sequence. The second bits are the first K-K1+r-r1+N1 bits of the bit sequence of length N, sorted in descending order of reliability.

[0191] Optionally, mapping the third bit sequence and the fourth bit sequence to the second bit position in a bit sequence of length N to obtain a sixth bit sequence includes: mapping the third bit sequence to the third bit position in the bit sequence of length N, and mapping the fourth bit sequence to the fourth bit position in the bit sequence of length N to obtain a fifth bit sequence, wherein the third bit position is the first K-K1+r-r1 bits of the second bit position sorted from high to low according to reliability, and the fourth bit position is the last N1 bits of the second bit position sorted from high to low according to reliability.

[0192] It can be understood that the third bit sequence can be a sequence that is directly transmitted through CRC encoding but not through convolution transformation. The first communication device places the third bit sequence at the third bit position with the highest reliability K-K1+r-r1 before the second bit position, and places the fourth bit sequence at the fourth bit position with the highest reliability N1 after the second bit position.

[0193] In order to introduce the above CRC-MPAC concatenated code encoding process, a specific example is given. FIG15 is a second schematic diagram of the encoding process of the CRC-MPAC code, where the parameter N1 determines the convolution transformation. The dimension of the information vector is , and the parameter K1 determines the number of information bits to be convolved. As shown in Figure 15, the specific encoding process is described as follows: Obtain CRC codeword vector through CRC encoding Then the CRC codeword vector is divided into Two sub-bit vectors of the form. Among them, the sub-bit vector Perform code rate configuration I to obtain vector Afterwards The codeword is obtained by preprocessing the convolution transform with a code rate of 1

[0194] Subbit vector The codeword after convolution transformation They are transmitted together through the polarization channel under the action of code rate configuration II. The vector after code rate configuration II is After polarization transformation, the coded bit sequence is obtained For the specific encoding process, please refer to the description of MPAC encoding.

[0195] S1405: The first communication device outputs a coded bit sequence. Correspondingly, the second communication device obtains a sequence to be decoded.

[0196] The sequence to be decoded includes a first sequence and a second sequence.

[0197] S1406: The second communication device performs Fano decoding on the first sequence to obtain a first bit sequence, and performs SC decoding on the second sequence to obtain a second bit sequence.

[0198] Optionally, the first sequence includes N1 bits, where the N1 bits are the last N1 bits of the M bits sorted from high to low according to reliability, and the M bits are the first M bits of the sequence to be decoded sorted from high to low according to reliability, and N1 and M are integers greater than or equal to 1.

[0199] The second sequence includes bits other than N1 bits in the sequence to be decoded.

[0200] Optionally, performing Fano decoding on the first sequence to obtain a first bit sequence may include: performing Fano decoding on the first K1+r1 bits in the first sequence sorted from high to low according to row weight according to a mapping relationship of the convolution transform to obtain the first bit sequence, where r1 is an integer greater than or equal to 1, and K1+r1 is less than or equal to N1.

[0201] Optionally, performing Fano decoding on the first sequence to obtain a first bit sequence, and performing SC decoding on the second sequence to obtain a second bit sequence, includes iterating a decoding path, performing Fano decoding on the first sequence according to the decoding path to obtain the first bit sequence, and performing SC decoding on the second sequence to obtain the second bit sequence. The decoding path is iterated if a CRC check fails.

[0202] S1407: The second communication device performs a CRC check on the first bit sequence and the second bit sequence.

[0203] Optionally, performing CRC check on the first bit sequence and the second bit sequence may include: when it is determined that decoding of the first bit sequence and the second decoding sequence is completed, performing CRC check on the first bit sequence and the second decoding sequence.

[0204] S1408: When the CRC check passes, the second communication device determines a target bit sequence according to the first bit sequence and the second bit sequence.

[0205] Figure 16 is a schematic diagram of error correction performance. As shown in Figure 16, the error correction performance of the two embodiments provided in this application is compared. The horizontal axis is the signal-to-noise ratio (SNR), and the vertical axis is the FER. S1 is the curve when CRC encoding is performed on a portion of the information bits participating in the convolution, and S2 is the curve when CRC encoding is performed on all information bits. The lower the curve, the better the error correction performance. It can be seen that CRC encoding of a portion of the information bits participating in the convolution has better error correction performance than CRC encoding of all information bits.

[0206] The method provided by the embodiment of the present application is described in detail above in conjunction with Figures 8 to 16. The communication device for executing the communication method provided by the embodiment of the present application is described in detail below in conjunction with Figures 17 and 18.

[0207] Figure 17 is a structural diagram of a communication device according to an embodiment of the present application. As shown in Figure 17 , the communication device 1700 includes a transceiver module 1701 and a processing module 1702. For ease of illustration, Figure 17 only shows the main components of the communication device.

[0208] The transceiver module 1701 is used to perform the transceiver function of the method shown in FIG8 , and the processing module 1702 is used to perform other functions of the method shown in FIG8 except the transceiver function.

[0209] Optionally, the transceiver module 1701 may include a sending module (not shown in FIG17 ) and a receiving module (not shown in FIG17 ). The sending module is used to implement the sending function of the communication device 1700 , and the receiving module is used to implement the receiving function of the communication device 1700 .

[0210] Optionally, the communication device 1700 may further include a storage module (not shown in FIG. 17 ) storing a program or instruction. When the processing module 1702 executes the program or instruction, the communication device 1700 may perform the functions of the terminal or network device in the method shown in FIG. 8 in the above method.

[0211] It can be understood that the communication device 1700 can be a terminal or a network device, or a chip (system) or other parts or components that can be set in a terminal or a network device, or a device that includes a terminal or a network device. This application does not limit this.

[0212] In addition, the technical effects of the communication device 1700 can refer to the technical effects of the communication method shown in Figure 8, and will not be repeated here.

[0213] Figure 18 is a second structural diagram of a communication device provided in an embodiment of the present application. Exemplarily, the communication device may be a terminal, or a chip (system) or other component or assembly that can be provided in a terminal. As shown in Figure 18, the communication device 1800 may include a processor 1801. Optionally, the communication device 1800 may further include a memory 1802 and / or a transceiver 1803. The processor 1801 is coupled to the memory 1802 and / or the transceiver 1803, such as by connecting via a communication bus, by connecting via an interface within the chip, or by connecting via other communication lines. Optionally, the memory 1802 may be integrated with the processor 1801.

[0214] The following is a detailed introduction to the various components of the communication device 1800 with reference to FIG18 :

[0215] The processor 1801 is the control center of the communication device 1800 and can be a single processor or a collective term for multiple processing elements. For example, the processor 1801 can be one or more central processing units (CPUs), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present application, such as one or more microprocessors (digital signal processors, DSPs) or one or more field programmable gate arrays (FPGAs).

[0216] Optionally, the processor 1801 can execute various functions of the communication device 1800 by running or executing software programs stored in the memory 1802 and calling data stored in the memory 1802, such as executing the communication method shown in Figure 8 above.

[0217] In a specific implementation, as an embodiment, the processor 1801 may include one or more CPUs, such as CPU0 and CPU1 shown in FIG. 18 .

[0218] In a specific implementation, as an embodiment, the communication device 1800 may also include multiple processors, such as the processor 1801 and the processor 1804 shown in FIG18 . Each of these processors may be a single-core processor (single-CPU) or a multi-core processor (multi-CPU). The processor herein may refer to one or more devices, circuits, and / or processing cores for processing data (e.g., computer program instructions).

[0219] Among them, the memory 1802 is used to store the software program for executing the solution of this application, and the execution is controlled by the processor 1801. The specific implementation method can refer to the above method embodiment and will not be repeated here.

[0220] Alternatively, the memory 1802 may be a read-only memory (ROM) or other type of static storage device that can store static information and instructions, a random access memory (RAM) or other type of dynamic storage device that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, an optical disc storage (including a compact disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 1802 may be integrated with the processor 1801 or exist independently and be coupled to the processor 1801 via an interface circuit (not shown in FIG. 18 ) of the communication device 1800, which is not specifically limited in this embodiment of the present application.

[0221] Transceiver 1803 is used for communication with other communication devices. For example, if communication device 1800 is a terminal, transceiver 1803 can be used to communicate with a network device or another terminal device. For another example, if communication device 1800 is a network device, transceiver 1803 can be used to communicate with a terminal or another network device.

[0222] Optionally, the transceiver 1803 may include a receiver and a transmitter (not shown separately in FIG18 ), wherein the receiver is used to implement a receiving function, and the transmitter is used to implement a transmitting function.

[0223] Optionally, the transceiver 1803 can be integrated with the processor 1801, or can exist independently and be coupled to the processor 1801 through the interface circuit of the communication device 1800 (not shown in Figure 18). This embodiment of the present application does not specifically limit this.

[0224] It is understandable that the structure of the communication device 1800 shown in FIG18 does not constitute a limitation on the communication device, and the actual communication device may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0225] In addition, the technical effects of the communication device 1800 can refer to the technical effects of the method in the above-mentioned method embodiment, and will not be repeated here.

[0226] It should be understood that the processor in the embodiments of the present application may be a central processing unit (CPU), and the processor may also be other general-purpose processors, DSPs, ASICs, FPGAs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor, etc.

[0227] It should also be understood that the memory in the embodiments of the present application can be a volatile memory or a non-volatile memory, or can include both volatile and non-volatile memories. Among them, the non-volatile memory can be a ROM, a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an EEPROM, or a flash memory. The volatile memory can be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0228] The above embodiments can be implemented in whole or in part by software, hardware (such as circuits), firmware or any other combination. When implemented using software, the above embodiments can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions or computer programs. When the computer instructions or computer program are loaded or executed on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center via a wired (such as infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server or data center that contains one or more available media sets. The available medium can be a magnetic medium (such as a floppy disk, hard disk, tape), an optical medium (such as a DVD), or a semiconductor medium. The semiconductor medium can be a solid-state drive.

[0229] It should be understood that the term "and / or" as used herein simply describes an association between related objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A alone, A and B together, or B alone. A and B can be singular or plural. Furthermore, the character " / " as used herein generally indicates an "or" relationship between the preceding and following related objects, but it may also indicate an "and / or" relationship. For specific understanding, please refer to the context.

[0230] In this application, "at least one" means one or more, and "plurality" means two or more. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, and c can be single or plural.

[0231] It should be understood that in the various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0232] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0233] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0234] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of units is only a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0235] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0236] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0237] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes the various possible memories mentioned above.

Claims

1. A communication method, characterized in that: include: Acquire a bit sequence to be sent, where the bit sequence to be sent includes a first bit sequence and a second bit sequence; performing cyclic redundancy check (CRC) encoding on the first bit sequence to obtain a third bit sequence, and performing a convolution transform on the third bit sequence to obtain a fourth bit sequence; performing polarization coding according to the second bit sequence and the fourth bit sequence to obtain a coded bit sequence; The coded bit sequence is output.

2. The method according to claim 1, characterized in that Performing cyclic redundancy check (CRC) encoding on the first bit sequence to obtain a third bit sequence includes: Performing CRC encoding on the first bit sequence to obtain a CRC codeword; Perform code rate configuration on the CRC codeword to obtain the third bit sequence.

3. The method according to claim 2, characterized in that The to-be-transmitted bit sequence includes K information bits, the first bit sequence is K1 information bits of the K information bits, the CRC codeword includes the K1 information bits and r check bits, where K, K1, and r are integers greater than or equal to 1; performing code rate configuration on the CRC codeword to obtain the third bit sequence includes: Obtain a bit sequence of length N1; The CRC codeword is mapped to K1+r first bits in the bit sequence of length N1 to obtain the third bit sequence, where K1+r is less than or equal to N1.

4. The method according to claim 3, characterized in that The first bits are the first K1+r bits in the bit sequence of length N1 sorted from high to low according to row weight.

5. The method according to any one of claims 1 to 4, characterized in that The performing polarization coding according to the second bit sequence and the fourth bit sequence to obtain a coded bit sequence includes: performing code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence; Polarization coding is performed on the fifth bit sequence to obtain the coded bit sequence.

6. The method according to claim 5, characterized in that The fourth bit sequence has a length of N1, the to-be-transmitted bit sequence includes K information bits, and the second bit sequence includes K-K1 information bits of the K information bits; and performing code rate configuration on the second bit sequence and the fourth bit sequence to obtain a fifth bit sequence includes: Get a bit sequence of length N; Determine K-K1+N1 second bits according to the bit sequence of length N; The second bit sequence and the fourth bit sequence are mapped to the second bit position in the bit sequence of length N to obtain the fifth bit sequence.

7. The method according to claim 6, characterized in that The second bits are the first K-K1+N1 bits in the bit sequence of length N, sorted from high to low according to reliability.

8. The method according to claim 6 or 7, characterized in that Mapping the second bit sequence and the fourth bit sequence to the second bit position in the bit sequence having a length of N to obtain the fifth bit sequence includes: The second bit sequence is mapped to the third bit position in the bit sequence of length N, and the fourth bit sequence is mapped to the fourth bit position in the bit sequence of length N, to obtain the fifth bit sequence, wherein the third bit position is the first K-K1 bits of the second bit positions sorted from high to low according to reliability, and the fourth bit position is the last N1 bits of the second bit positions sorted from high to low according to reliability.

9. A communication method, characterized in that: include: Obtaining a sequence to be decoded, where the sequence to be decoded includes a first sequence and a second sequence; Performing Fano decoding on the first sequence to obtain a first bit sequence, and performing SC decoding on the second sequence to obtain a second bit sequence; performing a CRC check on the first bit sequence; When the CRC check passes, a target bit sequence is determined according to the first bit sequence and the second bit sequence.

10. The method according to claim 9, characterized in that The first sequence includes N1 bits, where the N1 bits are the last N1 bits of the M bits sorted from high to low according to reliability, and the M bits are the first M bits of the sequence to be decoded sorted from high to low according to reliability, and N1 and M are integers greater than or equal to 1.

11. The method according to claim 9 or 10, characterized in that The second sequence includes bits other than the N1 bits in the sequence to be decoded.

12. The method according to any one of claims 9 to 11, characterized in that The performing Fano decoding on the first sequence to obtain a first bit sequence includes: According to the mapping relationship of the convolution transformation, the first K1+r bits in the first sequence, which are sorted from high to low according to row weight, are Fano decoded to obtain the first bit sequence, where r is an integer greater than or equal to 1, and K1+r is less than or equal to N1.

13. The method according to any one of claims 9 to 12, characterized in that The performing Fano decoding on the first sequence to obtain a first bit sequence includes: Iterating a decoding path, and performing Fano decoding on the first sequence according to the decoding path to obtain the first bit sequence; If the CRC check fails, the decoding path is iterated.

14. The method according to any one of claims 9 to 13, characterized in that The performing a CRC check on the first bit sequence includes: When it is determined that the decoding of the first bit sequence is completed, a CRC check is performed on the first bit sequence.

15. A communication device, characterized in that: The device includes: A module for executing the method according to any one of claims 1 to 8, or a module for executing the method according to any one of claims 9 to 14.

16. A communication device, characterized in that: The communication device comprises: a processor coupled to a memory; the memory is used to store computer instructions, and when the processor executes the instructions, the method according to any one of claims 1 to 8 or the method according to any one of claims 9 to 14 is executed.

17. The communication device according to claim 16, wherein: Also includes: The memory.

18. The communication device according to claim 16 or 17, characterized in that: Also includes: A transceiver is used for the communication device to communicate with other communication devices.

19. A computer-readable storage medium, characterized in that The computer-readable storage medium includes a computer program or instructions. When the computer program or instructions are executed on a computer, the computer executes the method according to any one of claims 1 to 8 or the method according to any one of claims 9 to 14.

20. A computer program product, characterized in that The computer program product comprises a computer program or instructions, which, when run on a computer, causes the method according to any one of claims 1 to 8 to be performed, or the method according to any one of claims 9 to 14 to be performed.

21. A communication system, characterized in that: The invention comprises a communication device for performing the method according to any one of claims 1 to 8, and a communication device for the method according to any one of claims 9 to 14.

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