Semiconductor device and solid-state imaging device

Abstract

[Problem] To provide a semiconductor device and a solid-state imaging device with which it is possible to suppress deterioration in the performance of a semiconductor substrate even when reducing the thickness of the semiconductor substrate. [Solution] In order to solve the aforementioned problem, the present disclosure provides a semiconductor device comprising: a semiconductor substrate provided with a well region; an insulator layer laminated on a second-surface side opposite from a first-surface side on which an electrode corresponding to the well region is formed; a conductor layer laminated on a second-surface side of the insulator layer opposite from the semiconductor substrate, the conductor layer having a conductor corresponding to the well region; and a metal body that is electrically connected to the conductor and applies a prescribed potential.

Description

Semiconductor device and solid-state imaging device

[0001] The present disclosure relates to a semiconductor device and a solid-state imaging device.

[0002] 2. Description of the Related Art Semiconductor devices are becoming increasingly multi-layered, such as with semiconductor substrates, and well regions are formed in these semiconductor substrates. While semiconductor substrates are becoming increasingly multi-layered, semiconductor substrates are also becoming thinner.

[0003] JP 2023-31150 A

[0004] However, as semiconductor substrates become thinner, electrons and holes that are distributed on the surface opposite to the side where the transistors are disposed may affect the well region.

[0005] Therefore, the present disclosure provides a semiconductor device and a solid-state imaging device that can suppress performance degradation of a semiconductor substrate even if the semiconductor substrate is made thinner.

[0006] In order to solve the above problems, the present disclosure provides a semiconductor device comprising: a semiconductor substrate having a well region; an insulator layer stacked on a second surface side opposite to a first surface side on which an electrode corresponding to the well region is formed; and a conductor layer stacked on the second surface side of the insulator layer opposite to the semiconductor substrate, the conductor layer having a conductor corresponding to the well region.

[0007] The semiconductor device may further include a metal body electrically connected to the conductor and applying a predetermined potential, the semiconductor substrate may be a silicon substrate, and the insulator layer may be a ferroelectric layer.

[0008] The device may further include a metal body electrically connected to the conductor and applying a predetermined potential, and the material of the ferroelectric layer may be at least one of lead zirconate titanate, barium titanate, and hafnium oxide.

[0009] The insulating layer may be a high-k insulator, which is an insulating material having a large dielectric constant.

[0010] The high dielectric constant (High-k) insulator material may be at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), and yttrium oxide (Y2O3).

[0011] The conductive material may be at least one of impurity-doped polysilicon, graphene, carbon nanotubes, and indium tin oxide (ITO).

[0012] The conductor may be configured as a conductor film having a pattern shape based on the position of the well region.

[0013] The well region may be at least one of a first well region of a first conductivity type and a second well region of a second conductivity type.

[0014] The well region may be a first well region of a first conductivity type and a second well region of a second conductivity type, and the conductor may be composed of a first conductor provided in correspondence with the first well region and a second conductor provided in correspondence with the second well region, and the first conductor and the second conductor may be insulated from each other.

[0015] The first conductor and the second conductor may be applied with different potentials.

[0016] The first conductor may be applied with a potential that generates polarization in the insulator layer that captures electrons or holes generated on the surface of the semiconductor substrate facing the insulator layer.

[0017] The second conductor may be applied with a potential that generates polarization in the insulator layer that captures electrons or holes generated on the surface of the semiconductor substrate facing the insulator layer.

[0018] The conductor may be composed of a second conductor provided corresponding to the gaps between the plurality of first well regions and a first conductor provided corresponding to the gaps between the plurality of second well regions, and the first conductor and the second conductor may be insulated from each other.

[0019] The semiconductor device may further include an insulating film laminated between the insulating layer and the conductive layer.

[0020] The semiconductor device may further include an insulating film laminated between the insulating layer and the semiconductor substrate.

[0021] The semiconductor device may further include a wiring layer formed of an insulating film having wiring and stacked on the surface of the semiconductor substrate opposite to the insulating layer.

[0022] The well region may include a transistor having a plurality of electrodes and a gate electrode in the wiring layer.

[0023] The well region may be a first well region of a first conductivity type and a second well region of a second conductivity type, and a first transistor may be configured in the first well region, and a second transistor having characteristics different from those of the first transistor may be configured in the second well region.

[0024] The metal body may be a through via that is connected to a wiring in the wiring layer and passes through the semiconductor substrate.

[0025] In order to solve the above-mentioned problems, according to the present disclosure, there is provided a solid-state imaging device comprising: a photoelectric conversion element layer including a photodiode; a first semiconductor substrate layer stacked on the photoelectric conversion element layer; and a second semiconductor substrate layer stacked on the first semiconductor substrate layer, wherein the first semiconductor substrate layer comprises: a semiconductor substrate provided with a well region; an insulator layer stacked on a second surface opposite to a first surface on which an electrode corresponding to the well region is formed; a conductor layer stacked on the insulator layer on the second surface opposite to the semiconductor substrate, and having a conductor corresponding to the well region; and a metal body electrically connected to the conductor and applying a predetermined potential.

[0026] 1 is a cross-sectional view schematically showing an example of a semiconductor device according to a first embodiment of the present disclosure; FIG. 2 is a diagram showing an example of a configuration in which a cross section of a first semiconductor substrate and a first multilayer wiring layer is extracted; FIG. 3 is a diagram schematically showing the functions of a conductor layer and an insulator layer; FIG. 4 is a diagram showing an example of the effect of an example in which only a first well region of a first conductivity type is formed; FIG. 5 is a diagram showing an example of the effect of an example in which only a first well region of a second conductivity type is formed; FIG. 6 is a plan view showing an example of patterning of a conductor in a conductor layer; FIG. 7 is a cross-sectional view of a conductor layer, a first semiconductor substrate, and a part of a wiring layer; FIG. 8 is a diagram showing a modified example of a semiconductor device; FIG. 9 is a cross-sectional view of a conductor layer, an insulator layer, a first semiconductor substrate, and a first multilayer wiring layer; FIG. 10 is a cross-sectional view according to a second embodiment; FIG. 11 is a plan view showing an example of patterning of a conductor in a conductor layer according to the second embodiment; FIG. 2 is an explanatory diagram showing an example of the installation positions of an outside-vehicle information detection unit and an imaging unit.

[0027] Hereinafter, embodiments of a semiconductor device and a solid-state imaging device will be described with reference to the drawings. The following description will focus on the main components of the semiconductor device and the solid-state imaging device, but the semiconductor device and the solid-state imaging device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0028] First Embodiment Fig. 1 is a cross-sectional view schematically illustrating an example of a semiconductor device 10 according to a first embodiment of the present disclosure. As shown in Fig. 1, the semiconductor device 10 is a semiconductor device used, for example, in a peripheral circuit of a solid-state imaging element. The semiconductor device 10 includes a first semiconductor substrate layer 20 and a second semiconductor substrate layer 30. The semiconductor device 10 is, for example, a semiconductor element, and the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30 are bonded at a bonding surface 20b.

[0029] For example, a logic circuit or a memory circuit (neither of which are shown) is formed on the first semiconductor substrate layer 20. The first semiconductor substrate layer 20 has a conductor layer 121, an insulator layer 122, a first semiconductor substrate 123, and a first wiring layer 124. In the following description, "upper" in "upper surface" and "lower" in "lower surface" refer to the top and bottom in the drawings. Furthermore, N and P mean that electrons and holes are the majority carriers, respectively.

[0030] The conductor layer 121 is made of, for example, a patterned conductor film. The conductor film can be made of, for example, impurity-doped polysilicon, graphene, carbon nanotubes, indium tin oxide (ITO), etc. That is, the conductor layer 121 is made of, for example, at least one material selected from these materials, and has, for example, a patterned conductor film.

[0031] A desired potential is applied to the conductor layer 121 from a power supply 300, for example, via a side contact 60s of the through-Si via 60. That is, the power supply 300 is connected to the through-Si via 60 via a wiring 50. The through-Si via 60 is formed of a conductor such as copper (Cu). Note that, as will be described later, it is also possible to supply an arbitrary potential from a potential line, instead of the power supply 300, via the through-Si via 60 and the wiring 50.

[0032] The insulator layer 122 is polarized in response to the potential applied to the conductor layer 121. The insulator layer 122 is, for example, a ferroelectric material. Examples of ferroelectric materials that can be used include lead zirconate titanate, barium titanate, and hafnium oxide. Alternatively, the insulator layer 122 may be formed of an insulator with a high dielectric constant κ, known as a high-k insulator.

[0033] When a ferroelectric material is used for the insulator layer 122, the polarization generated by the application of an electric field is maintained, which makes it possible to reduce the power consumption of the power supply 300 that supplies power to the through silicon via 60.

[0034] The lower surface of the first semiconductor substrate 123 is, for example, the polished surface 20p. A conductor layer 121 and an insulator layer 122 are stacked from the bonding surface 20b side between the lower side of the polished surface 20p and the upper side of the bonding surface 20b.

[0035] The first semiconductor substrate 123 is, for example, a silicon substrate. A well region 41 of the transistor 40 is formed in the first semiconductor substrate 123. A first wiring layer 124 having an interlayer insulating film formed thereon is disposed above the transistor 40, and wiring 50 is formed in each wiring layer of the first wiring layer 124. Similarly, a well region 41 of the capacitor 45 is formed in the first semiconductor substrate 123.

[0036] 2 is a diagram showing an example of a configuration in which a cross section of a first semiconductor substrate 123 and a first wiring layer 124 is extracted. As shown in FIG. 2, at least one of a first well region 41p of a first conductivity type and a second well region 41n of a second conductivity type is formed in the first semiconductor substrate 123. For example, the first conductivity type is n-type and the second conductivity type is p-type. Note that, although the following description will be given assuming that n-type is the first conductivity type and p-type is the second conductivity type, it is also possible to assume that p-type is the first conductivity type and n-type is the second conductivity type.

[0037] As described above, the first semiconductor substrate 123 has the first well region 41p and the second well region 41n. In this embodiment, there are no limitations on the type of well region formed in the first semiconductor substrate 123. Therefore, only the first well region 41p may be formed in the first semiconductor substrate 123, or only the second well region 41n may be formed.

[0038] The first semiconductor substrate 123 is, for example, a P-type silicon (Si) substrate. Note that the first semiconductor substrate 123 can also be configured as an n-type silicon (Si) substrate depending on the type of well region configured in the first semiconductor substrate 123. The impurity concentration in the first semiconductor substrate 123 can be set according to the purpose.

[0039] A depletion layer 48p is formed from the first well region 41p of the first conductivity type n toward the surrounding P-type substrate with a low impurity concentration. Similarly, a depletion layer 48n is formed from the second well region 41n toward the P-type substrate.

[0040] As shown in FIG. 2 , the first transistor 40p is a self-arc-suppressing element, such as a P-channel MOSFET in a CMOS circuit. An upper insulating film is disposed on the upper surface of a gate electrode 42p. The upper insulating film is, for example, a silicon oxide film or a silicon nitride film. Side insulating films are formed on the side surfaces of the gate structure including the gate electrode 42p and the upper insulating film. Furthermore, in the first transistor 40p, electrode diffusion layers 44p and 46p, which serve as a source electrode and a drain electrode, are formed in a first well region 41p of a first conductivity type n. In this manner, the first well region 41p is an n-type doped region.

[0041] The capacitor 45 (see FIG. 1) may have a configuration similar to that of the first transistor 40p, for example, in which the gate electrode 42p and the floating gate face each other via a block insulating film, thereby enabling the formation of a capacitor 45 in which the floating gate serves as a charge storage layer.

[0042] The second transistor 40n is a self-arc-suppressing element, e.g., an N-channel MOSFET of a CMOS circuit. An upper surface insulating film is disposed on the upper surface of the gate electrode 42n. The upper surface insulating film is, for example, a silicon oxide film or a silicon nitride film. Side insulating films are formed on the side surfaces of the gate structure including the gate electrode 42n and the upper surface insulating film. Furthermore, the second transistor 40n has electrode diffusion layers 44n, 46n, which serve as a source electrode and a drain electrode, formed in a second well region 41n of a second conductivity type p. Thus, the second well region 41n is a region doped p-type.

[0043] Note that the configuration examples of the transistor 40 and the capacitor 45 are not limited to these, and may be elements such as a transistor and a capacitor in which a first well region 41p of a first conductivity type n or a second well region 41n of a second conductivity type is configured. For example, an insulated gate field effect transistor, a diode, or the like may be used. Alternatively, a so-called double well region may be configured.

[0044] When the underside of the first semiconductor substrate 123 is polished, defects 70 (marked with an x ​​in the figure) due to polishing or contamination occur near the polished surface. In these defects 70, electrons or holes are generated along the underside of the first semiconductor substrate 123, depending on the type and concentration of impurities in the semiconductor substrate 123, for example.

[0045] As the first semiconductor substrate 123 is thinned, the distances between the first well region 41p and the second well region 41n and the defect 70 become closer. This raises the risk that the depletion layers 48p, 48n may reach the defect 70. When the depletion layers 48p, 48n reach the defect 70, electrons exist in the defect 70, so that the electrons enter the depletion layers 48p, 48n, causing leakage.

[0046] 1 , for example, a logic circuit or a memory circuit (neither of which are shown) is formed on the second semiconductor substrate layer 30. The second semiconductor substrate layer 30 is bonded to the lower bonding surface 20b of the first semiconductor substrate layer 20. The second semiconductor substrate layer 30 has a second semiconductor substrate 133 and a second wiring layer 134.

[0047] The second semiconductor substrate 133 is, for example, a silicon substrate. A well region of the transistor 40 is formed in the second semiconductor substrate 133. A second wiring layer 134 having an interlayer insulating film formed thereon is disposed above the transistor 40, and wiring 50 is formed in each wiring layer of the second wiring layer 134. Similarly, a well region of the capacitor 45 is formed.

[0048] Furthermore, the top and bottom of each wiring 50 are connected in the vertical direction (the vertical direction in this figure) by vias. The layer thickness of the second semiconductor substrate 133 is configured to be thicker than the layer thickness of the first semiconductor substrate 123. For example, the second semiconductor substrate 133 maintains a thickness that is sufficient to prevent the depletion layers 48p, 48n (see FIG. 2) of the transistor 40 from reaching the defects 70. It is also possible to thin the second semiconductor substrate layer 30. In this case, a conductor layer and an insulator layer are also configured in the second semiconductor substrate layer 30.

[0049] [Functions of the Conductor Layer 121 and the Insulator Layer 122]

[0050] 3 is a diagram schematically illustrating the functions of the conductor layer 121 and the insulator layer 122. FIG. 3 is a diagram illustrating an example of a cross section of the conductor layer 121, the insulator layer 122, the first semiconductor substrate 123, and the first wiring layer 124. In FIG. 3, the first well region 41p and the second well region 41n are described as a reference potential (ground potential). In the following description, the through-Si via 60 may be omitted for simplicity.

[0051] Polarizations 80d and 80u indicate the direction of polarization within the insulator layer 122. The direction of the electric field generated by polarization 80d is from the surface of the insulator layer 122 facing the first semiconductor substrate 123 to the surface facing the conductor layer 121 (opposite the arrow in the figure). The direction of the electric field generated by polarization 80u is from the surface of the insulator layer 122 facing the conductor layer 121 to the surface facing the first semiconductor substrate 123.

[0052] The conductors of the conductor layer 121 are arranged to correspond to the first transistor 40p and the second transistor 40n. For example, the conductors are arranged so as to overlap the depletion layers 48p and 48n in plan view.

[0053] A first conductor 121p is disposed on the lower surface side of the depletion layer 48p of the first transistor 40p, while a second conductor 121n is disposed on the lower surface side of the depletion layer 48n of the second transistor 40n.

[0054] The power supply 300a applies a positive potential to the second conductor 121p relative to the reference potential (ground potential). This causes the second conductor 121p to be positively charged. When the second conductor 121p is positively charged, the second conductor 121p side, which is the lower side of the insulator layer 122, becomes negatively charged, while the first semiconductor substrate 123 side, which is the upper side of the insulator layer 122, becomes positively charged, resulting in an upward orientation of the polarization 80u. When the upper side of the insulator layer 122 is positively charged, electrons 70e, which are negative carriers at the interface with the first semiconductor substrate 123, are pinned by electrostatic attraction. As a result, electrons 70e that would otherwise enter the depletion layer 48p are suppressed, thereby suppressing leakage. Since electrons 70e are not present in the depletion layer 48p, no leakage path is formed through the adjacent second well region 41p of the second conductivity type p.

[0055] The power supply 300b applies a negative potential to the first conductor 121n relative to the reference potential (ground potential). This causes the first conductor 121n to be negatively charged. When the first conductor 121n is negatively charged, the side of the first conductor 121n below the insulator layer 122 becomes positively charged, while the side of the first semiconductor substrate 123 above the insulator layer 122 becomes positively charged, resulting in a downward polarization 80d. When the upper side of the insulator layer 122 is negatively charged, holes 70h, which are positive carriers at the interface with the first semiconductor substrate 123, are pinned by electrostatic attraction and cannot move, preventing them from entering the depletion layer and suppressing leakage. As a result, no leakage path is formed through the adjacent first well region 41n of the first conductivity type n.

[0056] In this way, by changing the potential applied to the first conductors 121p, n, it is possible to freely change the direction of the polarizations 80u, 80d generated inside the insulator layer 122. As a result, by changing the potential according to the electrons 70e or holes 70h generated in the defects, the formation of a leak path is suppressed.

[0057] Furthermore, when a ferroelectric thin film is used for the insulator layer 122, the polarization 80u, d is maintained by applying a potential once, thereby reducing power consumption. When a high-k material is used for the insulator layer 122, for example, hafnium oxide (HfO ２ ), aluminum oxide (Al ２ O ３ ), zirconium oxide (ZrO ２ ), tantalum pentoxide (Ta ２ O ５ ), titanium oxide (TiO ２ ), lanthanum oxide (La ２ O ３ ) or yttrium oxide (Y ２ O ３ ) or the like. That is, the insulator layer 122 is a film formed of at least one material selected from these materials.

[0058] 4 is a diagram showing an example of the effect of forming only a first well region 41p of the first conductivity type n. In this example, the first well region 41p is assumed to be at a reference potential (ground potential). This is also an example in which the electrode 46p of multiple transistors 40p is shared.

[0059] The conductor of the conductor layer 121 is arranged to correspond to the first transistor 40p. The power supply 300a applies a positive potential to the first conductor 121 relative to the reference potential (ground potential). This generates polarization 80u in the insulator layer 122. Electrons 70e exist in defects that occur on the polished surface. The polarization 80u pins the electrons on the polished surface. This prevents electrons 70e from existing in defects on the polished surface. As a result, no leakage path is formed through the adjacent first well region 41p of the first conductivity type n.

[0060] 5 is a diagram showing an example of the effect of forming only the second well region 41n of the second conductivity type p. In this example, the second well region 41n is set to a reference potential (ground potential). This is also an example in which the electrode 46n of multiple transistors 40n is shared.

[0061] The conductor of the conductor layer 121 is arranged corresponding to the second transistor 40n. The power supply 300b applies a negative potential to the first conductor 121 relative to the reference potential (ground potential). This generates polarization 80d in the insulator layer 122. Holes 70h exist in defects that occur on the polished surface. The polarization 80d pins the holes 70h, preventing them from moving and preventing them from entering the depletion layer, thereby suppressing leakage. As a result, no leakage path is formed through the adjacent second well region 41n of the second conductivity type p.

[0062] 6 is a plan view showing an example of patterning of the conductor of the conductor layer 121. In FIG. 6, the conductor layer 121 and the first semiconductor substrate 123 are shown schematically in a plan view.

[0063] A plurality of second well regions 41n of the second conductivity type p of the first semiconductor substrate 123 are arranged in parallel on the upper surface of the conductor pattern of the first conductor 121n. A plurality of first well regions 41p of the first conductivity type n are arranged in parallel on the upper surface of the conductor pattern of the second conductor 121p. In this example, the plurality of second well regions 41n of the second conductivity type p and the plurality of first well regions 41p of the first conductivity type n are arranged alternately in a comb-teeth pattern.

[0064] A plurality of second transistors 40n are configured in the plurality of second well regions 41n of the second conductivity type p, and a plurality of first transistors 40p are configured in the plurality of first well regions 41p of the first conductivity type n.

[0065] 7 is a schematic cross-sectional view of the patterned conductor layer 121, first semiconductor substrate 123, and part of the wiring layer 124 shown in FIG. 6. For example, a power supply line VDD1 is connected to the conductor pattern of the first conductor 121n via a through-silicon via 60a and a wiring 50a. On the other hand, a power supply line VDD2 is connected to the conductor pattern of the second conductor 121p via a through-silicon via 60b and a wiring 50b. The potentials of the power supply lines VDD1 and VDD2 are configured to be set arbitrarily.

[0066] As a result, the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p are insulated from each other, and different potentials can be applied to the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p. This makes it possible to reverse the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the first conductor 121n and the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the second conductor 121p. It is also possible to apply the same potential, but with different magnitudes, to the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p.

[0067] 8 is a diagram showing a modified example of the semiconductor device 10. In this example, the bonding surface between the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30 is the surface of the wiring layer 124 of the first semiconductor substrate layer 20 opposite to the first semiconductor substrate 123. This makes it possible to form the conductive pattern of the conductor layer 121 after bonding the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30. Furthermore, it becomes possible to simplify the wiring connection between the wiring layers 124 and 134.

[0068] As described above, according to this embodiment, the conductor layer 121, the insulator layer 122, and the first semiconductor substrate 123 are stacked. By applying a potential to the conductor in the conductor layer 121, polarization in any direction can be generated in a predetermined region in the insulator layer 122, and electrons or holes generated on the surface of the first semiconductor substrate 123 facing the insulator layer 122 can be captured in the insulator layer 122. This prevents leakage through the well region of the first semiconductor substrate 123 even if the first semiconductor substrate 123 is thinned. This makes it possible to prevent performance degradation of the semiconductor device 10 even if the first semiconductor substrate 123 is thinned.

[0069] Second Embodiment The semiconductor device 10 according to the second embodiment differs from the semiconductor device 10 according to the first embodiment in that, when the distance between adjacent transistors 40 n and 40 p is made shorter, polarization can also be generated in the insulator layer 122 between the well regions of adjacent transistors 40 n and 40 p. The differences from the semiconductor device 10 according to the first embodiment will be described below.

[0070] 9 is a diagram showing an example of a cross section of the conductor layer 121, the insulator layer 122, the first semiconductor substrate 123, and the first wiring layer 124 according to the second embodiment. In this embodiment, the wells 41p and 41n are described as having a reference potential (ground potential). When adjacent transistors 40p are placed close to each other, if the first well regions 41p of the first conductivity type n are close to each other, leakage will occur through the interface between the first semiconductor substrate 123 and the insulator layer 122.

[0071] 9, in this embodiment, in the conductor layer 121, a second conductor 121n is formed below the region between the first well regions 41p of the first conductivity type n in the first semiconductor substrate 123. Although not shown in FIG. 9, a second conductor 121p is also formed below the first well regions 41p.

[0072] The power supply 300b applies a negative potential to the third conductor 121p relative to the reference potential (ground potential). This generates polarization 80d in the insulator layer 122. Holes 70h exist in defects that occur in the polished surface. The polarization 80d pins the holes 70h. By pinning holes at the interface of the first semiconductor substrate 123 between the first well regions 41p, it is possible to suppress well-to-well leakage through the surface of the first semiconductor substrate 123, even if the first well regions 41p are placed close to each other.

[0073] In this way, when the distance between adjacent transistors 40p is made shorter, polarization of the insulator layer 122 is also generated between the well regions of adjacent transistors 40p, making it possible to suppress well-to-well leakage through the surface of the first semiconductor substrate 123.

[0074] FIG. 10 is a diagram showing an example of a cross section of a conductor layer 121, an insulator layer 122, a first semiconductor substrate 123, and a first wiring layer 124 according to the second embodiment.

[0075] 10, in the conductor layer 121, first conductors 121p are formed below the regions between the second well regions 41n of the second conductivity type p in the first semiconductor substrate 123. Although not shown in FIG. 10, second conductors 121n are also formed below the second well regions 41n.

[0076] The power supply 300a applies a positive potential to the first conductor 121p relative to the reference potential (ground potential). This generates polarization 80u in the insulator layer 122. Electrons 70e exist in defects that occur on the polished surface. The polarization 80u pins the electrons 70e. By pinning the electrons 70e at the interface of the first semiconductor substrate 123 between the second well regions 41n, it is possible to suppress well-to-well leakage through the surface of the first semiconductor substrate 123, even when the wells are located close to each other.

[0077] In this way, when the distance between adjacent transistors 40p is made shorter, polarization of the insulator layer 122 is also generated between the well regions of adjacent transistors 40p, making it possible to suppress well-to-well leakage.

[0078] 11 is a plan view showing an example of patterning of the conductor of the conductor layer 121 according to the second embodiment. In FIG. 11, the conductor layer 121 and the first semiconductor substrate 123 are schematically shown in plan view.

[0079] A plurality of second well regions 41n of the second conductivity type p of the first semiconductor substrate 123 are arranged in parallel on both sides of the upper surface of the conductor pattern of the second conductor 121p. A plurality of first well regions 41p of the first conductivity type n are arranged in parallel on both sides of the upper surface of the conductor pattern of the first conductor 121n.

[0080] A plurality of second transistors 40n are configured in the plurality of second well regions 41n of the second conductivity type p, and a plurality of first transistors 40p are configured in the plurality of first well regions 41p of the first conductivity type n.

[0081] As a result, the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p are insulated from each other, so different potentials can be applied to the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p. This makes it possible to reverse the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the first conductor 121n and the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the second conductor 121p. It is also possible to apply the same potential, but with different magnitudes, to the conductor pattern of the first conductor 121n and the conductor pattern of the second conductor 121p. This makes it possible to reverse the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the first conductor 121n and the direction of polarization of the insulator layer 122 caused by the potential of the conductor pattern of the second conductor 121p, even when an adjacent region of multiple second well regions 41n of the second conductivity type p and an adjacent region of multiple first well regions 41p of the first conductivity type n are in the same layer.

[0082] Third Embodiment The semiconductor device 10 according to the third embodiment differs from the semiconductor device 10 according to the first embodiment in that an insulator is further formed on the upper surface or the lower surface of the insulator layer 122. The differences from the semiconductor device 10 according to the first embodiment will be described below.

[0083] 12 is a cross-sectional view schematically illustrating an example of a semiconductor device 10 according to the third embodiment. As shown in FIG. 12, an insulator 125 is further provided between the insulator layer 122 and the first semiconductor substrate 123. The insulator 125 can adjust the magnitude of the electric field used for polarization of the insulator layer 122. This makes it possible to adjust the magnitude of the electric field generated by polarization in the insulator layer 122.

[0084] 13 is a cross-sectional view schematically illustrating another example of the semiconductor device 10 according to the third embodiment. As shown in FIG. 13, an insulator 125 is further provided between the insulator layer 122 and the conductor layer 121. The insulator 125 can adjust the magnitude of the electric field used for polarization of the insulator layer 122. This makes it possible to adjust the magnitude of the electric field generated by polarization in the insulator layer 122.

[0085] Fourth Embodiment A semiconductor device 10 according to a fourth embodiment differs from the semiconductor device 10 according to the first embodiment in that it is configured using three semiconductor substrate layers. The differences from the semiconductor device 10 according to the first embodiment will be described below.

[0086] 14 is a cross-sectional view schematically illustrating an example of a semiconductor device 10 according to the fourth embodiment. As shown in FIG. 14, the semiconductor device 10 according to the fourth embodiment is an example configured as a solid-state imaging device. Note that a solid-state imaging device can be configured as a semiconductor element, and may also be referred to as a solid-state imaging element.

[0087] The third semiconductor substrate layer 200 is bonded to the upper surface 20f of the first semiconductor substrate layer 20. The third semiconductor substrate layer 200 is a photoelectric conversion element layer, and constitutes, for example, a CMOS image sensor (CIS). In this figure, the upper side is the light incident surface side. Therefore, the third semiconductor substrate layer 200 is stacked on the light incident surface side.

[0088] 14, the third semiconductor substrate layer 200 has a photodiode formation layer 213 in which a plurality of photodiodes 251 are formed, and a wiring layer 214 that wires these photodiodes 251. Furthermore, a color filter 252 is laminated on the upper surface of the photodiode 251 on the light incident surface side of the third semiconductor substrate layer 200, and an on-chip lens 253 is further laminated on the upper surface of the color filter 252.

[0089] As described above, two semiconductor chips, the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30, are stacked. Logic circuits, memory circuits (neither of which are shown), and the like are formed in the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30. It should be noted that pixel transistors may also be formed in the first semiconductor substrate layer 20. The logic circuits are, for example, vertical drive units, horizontal drive units, system control units, signal processing units, and the like, for sequentially reading out image data from each pixel formed by a photodiode 251. The memory circuit is, for example, a data storage unit that temporarily stores data required for processing by the signal processing unit. These logic circuits are housed separately in the first semiconductor substrate layer 20 and the second semiconductor substrate layer 30.

[0090] In this way, even when semiconductor devices 10 are stacked as a solid-state imaging device, the first semiconductor substrate 123 of the first semiconductor substrate layer 20 can be thinned, and the solid-state imaging device can be thinned.

[0091] <<Application Examples>> The technology according to the present disclosure can be applied to various products. For example, the technology according to the present disclosure may be realized as a unit mounted on any type of moving body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, a robot, construction machinery, agricultural machinery (tractors), a microscope system, or the like.

[0092] An example configuration of a biological sample analyzer according to the present disclosure is shown in Figure 15. The biological sample analyzer 6100 shown in Figure 15 includes a light irradiation unit 6101 that irradiates light onto a biological sample S flowing through a flow path C, a detection unit 6102 that detects light generated by irradiating the biological sample S with light, and an information processing unit 6103 that processes information related to the light detected by the detection unit. Examples of the biological sample analyzer 6100 include a flow cytometer and an imaging cytometer. The biological sample analyzer 6100 may also include a fractionation unit 6104 that separates specific biological particles P from within the biological sample. An example of a biological sample analyzer 6100 that includes the fractionation unit is a cell sorter.

[0093] (Biological Sample) The biological sample S may be a liquid sample containing biological particles. The biological particles may be, for example, cells or non-cellular biological particles. The cells may be living cells, and more specific examples include blood cells such as red blood cells and white blood cells, and reproductive cells such as sperm and fertilized eggs. The cells may be directly collected from a specimen such as whole blood, or may be cultured cells obtained after culturing. Examples of the non-cellular biological particles include extracellular vesicles, particularly exosomes and microvesicles. The biological particles may be labeled with one or more labeling substances (e.g., dyes (particularly fluorescent dyes) and fluorescent dye-labeled antibodies). Note that the biological sample analyzer of the present disclosure may also analyze particles other than biological particles, such as beads for calibration purposes.

[0094] (Flow Channel) The flow channel C is configured to allow the biological sample S to flow. In particular, the flow channel C can be configured to form a flow in which biological particles contained in the biological sample are aligned in a substantially straight line. The flow channel structure including the flow channel C may be designed to form a laminar flow. In particular, the flow channel structure is designed to form a laminar flow in which the flow of the biological sample (sample flow) is surrounded by the flow of sheath liquid. The design of the flow channel structure may be appropriately selected by those skilled in the art, and a known design may be adopted. The flow channel C may be formed in a flow channel structure such as a microchip (a chip having flow channels on the order of micrometers) or a flow cell. The width of the flow channel C may be 1 mm or less, particularly 10 μm or more and 1 mm or less. The flow channel C and the flow channel structure including it may be formed from a material such as plastic or glass.

[0095] The biological sample analyzer of the present disclosure is configured so that light from light irradiation unit 6101 is irradiated onto the biological sample flowing within flow path C, and particularly onto biological particles in the biological sample. The biological sample analyzer of the present disclosure may be configured so that the interrogation point of light on the biological sample is within the flow path structure in which flow path C is formed, or so that the interrogation point of light is outside the flow path structure. An example of the former is a configuration in which the light is irradiated onto flow path C within a microchip or flow cell. In the latter, the light may be irradiated onto biological particles after they have left the flow path structure (particularly its nozzle portion), and an example of this is a jet-in-air flow cytometer.

[0096] (Light Irradiation Unit) The light irradiation unit 6101 includes a light source unit that emits light and a light-guiding optical system that guides the light to an irradiation point. The light source unit includes one or more light sources. The type of light source is, for example, a laser light source or an LED. The wavelength of the light emitted from each light source may be any of ultraviolet light, visible light, and infrared light. The light-guiding optical system includes optical components such as a beam splitter group, a mirror group, or an optical fiber. The light-guiding optical system may also include a lens group for focusing light, such as an objective lens. There may be one or more irradiation points where the light intersects with the biological sample. The light irradiation unit 6101 may be configured to focus light irradiated from one or more different light sources onto one irradiation point.

[0097] (Detection Unit) The detection unit 6102 includes at least one photodetector that detects light generated by irradiating the bioparticles with light. The detected light is, for example, fluorescence or scattered light (e.g., one or more of forward scattered light, back scattered light, and side scattered light). Each photodetector includes one or more light-receiving elements, for example, a photodetector array. Each photodetector may include one or more PMTs (photomultiplier tubes) and / or photodiodes such as APDs and MPPCs as light-receiving elements. The photodetector includes, for example, a PMT array in which multiple PMTs are arranged in a one-dimensional direction. The detection unit 6102 may also include an imaging element such as a CCD or CMOS. The detection unit 6102 can acquire images of the bioparticles (e.g., bright-field images, dark-field images, and fluorescence images) using the imaging element.

[0098] The detection unit 6102 includes a detection optical system that allows light of a predetermined detection wavelength to reach a corresponding photodetector. The detection optical system includes a spectroscopic unit such as a prism or a diffraction grating, or a wavelength separation unit such as a dichroic mirror or an optical filter. The detection optical system is configured to, for example, disperse light generated by irradiating bioparticles with light, and detect the dispersed light using a plurality of photodetectors, the number of which is greater than the number of fluorescent dyes with which the bioparticles are labeled. A flow cytometer that includes such a detection optical system is called a spectral flow cytometer. The detection optical system is also configured to, for example, separate light corresponding to the fluorescent wavelength range of a specific fluorescent dye from the light generated by irradiating bioparticles with light, and detect the separated light using a corresponding photodetector.

[0099] The detection unit 6102 may also include a signal processing unit that converts the electrical signal obtained by the photodetector into a digital signal. The signal processing unit may include an A / D converter as a device that performs the conversion. The digital signal obtained by the conversion by the signal processing unit may be transmitted to the information processing unit 6103. The digital signal may be handled by the information processing unit 6103 as data related to light (hereinafter also referred to as "light data"). The light data may be light data including, for example, fluorescent light data. More specifically, the light data may be light intensity data, and the light intensity may be light intensity data of light including fluorescent light (which may include feature quantities such as area, height, and width).

[0100] (Information Processing Unit) The information processing unit 6103 includes, for example, a processing unit that processes various data (e.g., optical data) and a storage unit that stores various data. When the processing unit acquires optical data corresponding to a fluorescent dye from the detection unit 6102, the processing unit may perform fluorescence spillover correction (compensation processing) on ​​the light intensity data. Furthermore, in the case of a spectral flow cytometer, the processing unit performs fluorescence separation processing on the optical data to acquire light intensity data corresponding to the fluorescent dye. The fluorescence separation processing may be performed, for example, according to the unmixing method described in Japanese Patent Application Laid-Open No. 2011-232259. When the detection unit 6102 includes an image sensor, the processing unit may acquire morphological information of bioparticles based on images acquired by the image sensor. The storage unit may be configured to store the acquired optical data. The storage unit may further be configured to store spectral reference data used in the unmixing processing.

[0101] If the biological sample analyzer 6100 includes a fractionating unit 6104 (described below), the information processing unit 6103 can determine whether to fractionate bioparticles based on the optical data and / or morphological information. The information processing unit 6103 can then control the fractionating unit 6104 based on the result of this determination, allowing the fractionating unit 6104 to fractionate the bioparticles.

[0102] The information processing unit 6103 may be configured to output various data (e.g., optical data and images). For example, the information processing unit 6103 may output various data (e.g., two-dimensional plots, spectral plots, etc.) generated based on the optical data. The information processing unit 6103 may also be configured to accept input of various data, such as accepting gating processing on a plot by a user. The information processing unit 6103 may include an output unit (e.g., a display, etc.) or an input unit (e.g., a keyboard, etc.) for executing the output or input.

[0103] The information processing unit 6103 may be configured as a general-purpose computer, for example, as an information processing device including a CPU, RAM, and ROM. The information processing unit 6103 may be included in a housing that includes the light irradiation unit 6101 and the detection unit 6102, or may be located outside the housing. Furthermore, various processes or functions performed by the information processing unit 6103 may be realized by a server computer or a cloud connected via a network.

[0104] (Sorting unit) The sorting unit 6104 sorts the bioparticles according to the determination result by the information processing unit 6103. The sorting method may be a method of generating droplets containing bioparticles by vibration, applying an electric charge to the droplets to be sorted, and controlling the direction of travel of the droplets using electrodes. The sorting method may also be a method of controlling the direction of travel of the bioparticles within the flow channel structure to perform sorting. The flow channel structure is provided with, for example, a control mechanism using pressure (spray or suction) or electric charge. An example of such a flow channel structure is a chip (for example, the chip described in JP 2020-76736 A) having a flow channel structure in which a flow channel C branches downstream into a recovery flow channel and a waste flow channel, and specific bioparticles are recovered into the recovery flow channel.

[0105] 16 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied. The vehicle control system 7000 includes a plurality of electronic control units connected via a communication network 7010. In the example shown in FIG. 16, the vehicle control system 7000 includes a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an outside-vehicle information detection unit 7400, an inside-vehicle information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these multiple control units may be an in-vehicle communication network conforming to any standard, such as a Controller Area Network (CAN), a Local Interconnect Network (LIN), a Local Area Network (LAN), or FlexRay (registered trademark).

[0106] Each control unit includes a microcomputer that performs arithmetic processing according to various programs, a memory unit that stores the programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit includes a network I / F for communicating with other control units via a communication network 7010, and a communication I / F for communicating with devices or sensors inside and outside the vehicle via wired or wireless communication. Figure 16 illustrates the functional configuration of the integrated control unit 7600, including a microcomputer 7610, a general-purpose communication I / F 7620, a dedicated communication I / F 7630, a positioning unit 7640, a beacon receiving unit 7650, an in-vehicle device I / F 7660, an audio / video output unit 7670, an in-vehicle network I / F 7680, and a memory unit 7690. The other control units also include a microcomputer, a communication I / F, a memory unit, and the like.

[0107] The drivetrain control unit 7100 controls the operation of devices related to the drivetrain of the vehicle according to various programs. For example, the drivetrain control unit 7100 functions as a control device for a drive force generating device for generating drive force for the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device for an ABS (Antilock Brake System) or an ESC (Electronic Stability Control), etc.

[0108] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes at least one of a gyro sensor that detects the angular velocity of the axial rotational motion of the vehicle body, an acceleration sensor that detects the acceleration of the vehicle, or a sensor that detects the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine rotation speed, the rotation speed of the wheels, etc. The drivetrain control unit 7100 performs arithmetic processing using signals input from the vehicle state detection unit 7110, and controls the internal combustion engine, the drive motor, the electric power steering device, the brake device, etc.

[0109] The body system control unit 7200 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 7200. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0110] The battery control unit 7300 controls the secondary battery 7310, which is the power supply source for the drive motor, in accordance with various programs. For example, information such as battery temperature, battery output voltage, or remaining battery capacity is input to the battery control unit 7300 from a battery device equipped with the secondary battery 7310. The battery control unit 7300 performs arithmetic processing using these signals, and controls the temperature regulation of the secondary battery 7310 or a cooling device or the like equipped in the battery device.

[0111] The outside vehicle information detection unit 7400 detects information outside the vehicle equipped with the vehicle control system 7000. For example, at least one of an imaging unit 7410 and an outside vehicle information detection unit 7420 is connected to the outside vehicle information detection unit 7400. The imaging unit 7410 includes at least one of a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The outside vehicle information detection unit 7420 includes at least one of an environmental sensor for detecting the current weather or climate, or a surrounding information detection sensor for detecting other vehicles, obstacles, pedestrians, etc. around the vehicle equipped with the vehicle control system 7000.

[0112] The environmental sensor may be, for example, at least one of a raindrop sensor that detects rain, a fog sensor that detects fog, a sunshine sensor that detects the degree of sunshine, and a snow sensor that detects snowfall. The surrounding information detection sensor may be at least one of an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. The imaging unit 7410 and the outside vehicle information detection unit 7420 may be provided as independent sensors or devices, or may be provided as a device in which multiple sensors or devices are integrated.

[0113] 17 shows an example of the installation positions of the imaging unit 7410 and the vehicle exterior information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are provided, for example, at least one of the front nose, side mirrors, rear bumper, back door, and upper part of the windshield inside the vehicle cabin of the vehicle 7900. The imaging unit 7910 provided on the front nose and the imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 provided on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 provided on the upper part of the windshield inside the vehicle cabin is mainly used to detect leading vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0114] 17 shows an example of the imaging ranges of the imaging units 7910, 7912, 7914, and 7916. Imaging range a indicates the imaging range of the imaging unit 7910 provided on the front nose, imaging ranges b and c indicate the imaging ranges of the imaging units 7912 and 7914 provided on the side mirrors, respectively, and imaging range d indicates the imaging range of the imaging unit 7916 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 7910, 7912, 7914, and 7916, a bird's-eye view image of the vehicle 7900 viewed from above can be obtained.

[0115] The outside vehicle information detection units 7920, 7922, 7924, 7926, 7928, and 7930 provided on the front, rear, sides, corners, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, ultrasonic sensors or radar devices. The outside vehicle information detection units 7920, 7926, and 7930 provided on the front nose, rear bumper, back door, and above the windshield inside the vehicle cabin of the vehicle 7900 may be, for example, LIDAR devices. These outside vehicle information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, obstacles, etc.

[0116] Returning to FIG. 16 , the explanation will be continued. The outside-vehicle information detection unit 7400 causes the imaging unit 7410 to capture an image outside the vehicle and receives the captured image data. The outside-vehicle information detection unit 7400 also receives detection information from the connected outside-vehicle information detection unit 7420. If the outside-vehicle information detection unit 7420 is an ultrasonic sensor, a radar device, or a LIDAR device, the outside-vehicle information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the outside-vehicle information detection unit 7400 may perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, text on the road, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also perform environmental recognition processing for recognizing rainfall, fog, road conditions, etc. Based on the received information, the outside-vehicle information detection unit 7400 may also calculate the distance to an object outside the vehicle.

[0117] The outside vehicle information detection unit 7400 may also perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The outside vehicle information detection unit 7400 may perform processing such as distortion correction or alignment on the received image data, and may also generate an overhead image or a panoramic image by combining image data captured by different image capturing units 7410. The outside vehicle information detection unit 7400 may also perform viewpoint conversion processing using image data captured by different image capturing units 7410.

[0118] The interior information detection unit 7500 detects information inside the vehicle. A driver state detection unit 7510 that detects the driver's state is connected to the interior information detection unit 7500, for example. The driver state detection unit 7510 may include a camera that captures an image of the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sound from within the vehicle cabin. The biosensor is provided, for example, on the seat or steering wheel, and detects the biometric information of a passenger sitting in the seat or the driver gripping the steering wheel. The interior information detection unit 7500 may calculate the driver's level of fatigue or concentration based on the detection information input from the driver state detection unit 7510, or may determine whether the driver is dozing off. The interior information detection unit 7500 may perform processing such as noise canceling on the collected audio signal.

[0119] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 in accordance with various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is realized by a device that can be operated by a passenger, such as a touch panel, a button, a microphone, a switch, or a lever. Data obtained by voice recognition of voice input through a microphone may be input to the integrated control unit 7600. The input unit 7800 may be, for example, a remote control device using infrared or other radio waves, or an externally connected device such as a mobile phone or a personal digital assistant (PDA) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be, for example, a camera, in which case the passenger can input information using gestures. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on information input by a passenger or the like using the input unit 7800 and outputs the signal to the integrated control unit 7600. The passenger or the like operates the input unit 7800 to input various data to the vehicle control system 7000 and to instruct processing operations.

[0120] The storage unit 7690 may include a ROM (Read Only Memory) that stores various programs executed by the microcomputer, and a RAM (Random Access Memory) that stores various parameters, calculation results, sensor values, etc. The storage unit 7690 may also be realized by a magnetic storage device such as a HDD (Hard Disc Drive), a semiconductor storage device, an optical storage device, a magneto-optical storage device, or the like.

[0121] The general-purpose communication I / F 7620 is a general-purpose communication I / F that mediates communication with various devices present in the external environment 7750. The general-purpose communication I / F 7620 may implement a cellular communication protocol such as GSM (registered trademark) (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as a wireless LAN (also referred to as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication I / F 7620 may connect to a device (e.g., an application server or a control server) present on an external network (e.g., the Internet, a cloud network, or an operator-specific network) via, for example, a base station or an access point. In addition, the general-purpose communication I / F 7620 may connect to a terminal located near the vehicle (for example, a terminal of a driver, a pedestrian, or a store, or an MTC (Machine Type Communication) terminal) using, for example, P2P (Peer To Peer) technology.

[0122] The dedicated communication I / F 7630 is a communication I / F that supports a communication protocol designed for use in a vehicle. The dedicated communication I / F 7630 may implement a standard protocol such as WAVE (Wireless Access in Vehicle Environment), which is a combination of IEEE 802.11p at a lower layer and IEEE 1609 at an upper layer, DSRC (Dedicated Short Range Communications), or a cellular communication protocol. The dedicated communication I / F 7630 typically performs V2X communication, which is a concept including one or more of vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0123] The positioning unit 7640 performs positioning by receiving, for example, GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates position information including the latitude, longitude, and altitude of the vehicle. Note that the positioning unit 7640 may identify the current position by exchanging signals with a wireless access point, or may obtain position information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0124] The beacon receiving unit 7650 receives, for example, radio waves or electromagnetic waves transmitted from radio stations or the like installed on the road, and acquires information such as the current location, congestion, road closures, required travel time, etc. The function of the beacon receiving unit 7650 may be included in the dedicated communication I / F 7630 described above.

[0125] The in-vehicle device I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle devices 7760 present in the vehicle. The in-vehicle device I / F 7660 may establish wireless connections using wireless communication protocols such as wireless LAN, Bluetooth (registered trademark), NFC (Near Field Communication), or WUSB (Wireless USB). The in-vehicle device I / F 7660 may also establish a wired connection such as USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via a connection terminal (and a cable, if necessary) not shown. The in-vehicle device 7760 may include, for example, at least one of a mobile device or a wearable device owned by a passenger, or an information device carried into or attached to the vehicle. The in-vehicle device 7760 may also include a navigation device that searches for a route to an arbitrary destination. The in-vehicle device I / F 7660 exchanges control signals or data signals with these in-vehicle devices 7760.

[0126] The in-vehicle network I / F 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network I / F 7680 transmits and receives signals in accordance with a predetermined protocol supported by the communication network 7010.

[0127] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 in accordance with various programs based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the driving force generating device, the steering mechanism, or the braking device based on the acquired information inside and outside the vehicle, and output control commands to the drivetrain control unit 7100. For example, the microcomputer 7610 may perform cooperative control aimed at realizing functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the following distance, vehicle speed maintenance driving, vehicle collision warning, vehicle lane departure warning, etc. In addition, the microcomputer 7610 may perform cooperative control for the purpose of autonomous driving, in which the vehicle travels autonomously without relying on driver operation, by controlling a driving force generating device, a steering mechanism, a braking device, etc. based on information acquired about the vehicle's surroundings.

[0128] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and objects such as surrounding structures and people, and create local map information including information about the vicinity of the vehicle's current location, based on information acquired via at least one of the general-purpose communication I / F 7620, the dedicated communication I / F 7630, the positioning unit 7640, the beacon receiving unit 7650, the in-vehicle device I / F 7660, and the in-vehicle network I / F 7680. Furthermore, the microcomputer 7610 may predict dangers, such as a vehicle collision, the approach of a pedestrian, or entry into a closed road, based on the acquired information, and generate a warning signal. The warning signal may be, for example, a signal for generating a warning sound or turning on a warning lamp.

[0129] The audio / video output unit 7670 transmits at least one audio and / or visual output signal to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. In the example of FIG. 16 , an audio speaker 7710, a display unit 7720, and an instrument panel 7730 are illustrated as examples of the output devices. The display unit 7720 may include, for example, at least one of an on-board display and a head-up display. The display unit 7720 may have an AR (Augmented Reality) display function. The output device may be other devices besides these devices, such as headphones, a wearable device such as an eyeglass-type display worn by the occupant, a projector, or a lamp. When the output device is a display device, the display device visually displays results obtained by various processes performed by the microcomputer 7610 or information received from other control units in various formats, such as text, images, tables, and graphs. Furthermore, when the output device is an audio output device, the audio output device converts an audio signal consisting of reproduced voice data or acoustic data into an analog signal and outputs it audibly.

[0130] In the example shown in FIG. 16 , at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include another control unit not shown. In the above description, some or all of the functions performed by one of the control units may be assigned to another control unit. In other words, as long as information is transmitted and received via the communication network 7010, predetermined arithmetic processing may be performed by one of the control units. Similarly, a sensor or device connected to one of the control units may be connected to another control unit, and multiple control units may transmit and receive detection information to and from each other via the communication network 7010.

[0131] A computer program for realizing each function of the semiconductor device 10 according to the present embodiment described with reference to FIG. 1 can be implemented in any control unit or the like. A computer-readable recording medium storing such a computer program can also be provided. Examples of the recording medium include a magnetic disk, an optical disk, a magneto-optical disk, and a flash memory. The computer program may also be distributed, for example, via a network without using a recording medium.

[0132] In the vehicle control system 7000 described above, the semiconductor device 10 according to the present embodiment described with reference to Fig. 1 can be applied to the integrated control unit 7600 of the application example shown in Fig. 16. For example, it corresponds to 7410.

[0133] Furthermore, at least some of the components of the semiconductor device 10 described using Fig. 1 may be realized in a module (for example, an integrated circuit module configured on a single die) for the integrated control unit 7600 shown in Fig. 16. Alternatively, the semiconductor device 10 described using Fig. 1 may be realized by multiple control units of the vehicle control system 7000 shown in Fig. 16.

[0134] The present technology can be configured as follows:

[0135] (1) A semiconductor device comprising: a semiconductor substrate having a well region; an insulator layer stacked on a second surface opposite to a first surface on which an electrode corresponding to the well region is formed; and a conductor layer stacked on the second surface opposite to the semiconductor substrate of the insulator layer, the conductor having a conductor corresponding to the well region.

[0136] (2) The semiconductor device according to (1), further comprising a metal body electrically connected to the conductor and applying a predetermined potential, the semiconductor substrate being a silicon substrate, and the insulator layer being a ferroelectric layer.

[0137] (3) The semiconductor device according to (2), wherein the material of the ferroelectric layer is at least one of lead zirconate titanate, barium titanate, and hafnium oxide.

[0138] (4) The semiconductor device according to (1) or (2), wherein the insulator layer is a high-dielectric-constant (High-k) insulator, which is an insulator having a large dielectric constant.

[0139] (5) The semiconductor device according to (4), wherein the high dielectric constant (High-k) insulator material is at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), and yttrium oxide (Y2O3).

[0140] (6) The semiconductor device according to any one of (1) to (5), wherein the material of the conductor is at least one of impurity-doped polysilicon, graphene, carbon nanotubes, and indium tin oxide (ITO).

[0141] (7) The semiconductor device according to any one of (1) to (6), wherein the conductor is configured as a conductor film having a pattern shape based on the position of the well region.

[0142] (8) The semiconductor device according to (7), wherein the well region is at least one of a first well region of a first conductivity type and a second well region of a second conductivity type.

[0143] (9) The semiconductor device according to (7), wherein the well region is a first well region of a first conductivity type and a second well region of a second conductivity type, the conductor is composed of a first conductor provided in correspondence with the first well region and a second conductor provided in correspondence with the second well region, and the first conductor and the second conductor are insulated from each other.

[0144] (10) The semiconductor device according to (9), wherein different potentials are applied to the first conductor and the second conductor.

[0145] (11) The semiconductor device according to (10), wherein a potential is applied to the first conductor to generate polarization in the insulator layer that captures electrons or holes generated on a surface of the semiconductor substrate facing the insulator layer.

[0146] (12) The semiconductor device according to (10), wherein a potential is applied to the second conductor to generate polarization in the insulator layer that captures electrons or holes generated on the surface of the semiconductor substrate facing the insulator layer.

[0147] (13) The semiconductor device according to (8), wherein the conductor is composed of second conductors provided corresponding to spaces between the plurality of first well regions and first conductors provided corresponding to spaces between the plurality of second well regions, and the first conductors and the second conductors are insulated from each other.

[0148] (14) The semiconductor device according to any one of (1) to (13), further comprising an insulating film stacked between the insulating layer and the conductive layer.

[0149] (15) The semiconductor device according to any one of (1) to (13), further comprising an insulating film stacked between the insulating layer and the semiconductor substrate.

[0150] (16) The semiconductor device according to any one of (1) to (15), further comprising a wiring layer formed of an insulating film having wiring and stacked on a surface of the semiconductor substrate opposite to the insulating layer.

[0151] (17) The semiconductor device according to any one of (1) to (16), further comprising a transistor having a plurality of electrodes in the well region and a gate electrode in the wiring layer.

[0152] (18) The semiconductor device according to (17), wherein the well region is a first well region of a first conductivity type and a second well region of a second conductivity type, a first transistor is configured in the first well region, and a second transistor having characteristics different from those of the first transistor is configured in the second well region.

[0153] (19) The semiconductor device according to (16), wherein the metal body is a through via that is connected to a wiring in the wiring layer and penetrates the semiconductor substrate.

[0154] (20) A solid-state imaging device comprising: a photoelectric conversion element layer including a photodiode; a first semiconductor substrate layer stacked on the photoelectric conversion element layer; and a second semiconductor substrate layer stacked on the first semiconductor substrate layer, wherein the first semiconductor substrate layer comprises: a semiconductor substrate provided with a well region; an insulator layer stacked on a second surface opposite to a first surface on which an electrode corresponding to the well region is formed; a conductor layer stacked on the insulator layer on the second surface opposite to the semiconductor substrate, the conductor having a conductor corresponding to the well region; and a metal body electrically connected to the conductor and applying a predetermined potential.

[0155] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents.

[0156] 10: semiconductor device, 20: first semiconductor substrate layer, 30: second semiconductor substrate layer, 40, 40p, 40n: transistor, 41n: second well region, 41p: first well region, 45: capacitor, 48n, 48p: depletion layer, 50, 50a, 50b: wiring, 60, 60a, 60b: through silicon via, 121: conductor layer, 122: insulator layer, 123: first semiconductor substrate, 200: third semiconductor substrate layer.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a well region; an insulator layer laminated on a second surface opposite to a first surface on which an electrode corresponding to the well region is formed; and a conductor layer laminated on the second surface of the insulator layer opposite to the semiconductor substrate, the conductor having a conductor corresponding to the well region.

2. The semiconductor device according to claim 1, further comprising a metal body electrically connected to said conductor and applying a predetermined potential, said semiconductor substrate being a silicon substrate, and said insulator layer being a ferroelectric layer.

3. The semiconductor device according to claim 2, further comprising a metal body electrically connected to said conductor and applying a predetermined potential, wherein said ferroelectric layer is made of at least one of lead zirconate titanate, barium titanate, and hafnium oxide.

4. The semiconductor device according to claim 1, further comprising a metal body electrically connected to said conductor and applying a predetermined potential, wherein said insulator layer is a high dielectric constant (High-k) insulator, which is an insulator with a large dielectric constant.

5. The semiconductor device according to claim 4, wherein the high dielectric constant (High-k) insulator material is at least one of hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), titanium oxide (TiO2), lanthanum oxide (La2O3), and yttrium oxide (Y2O3).

6. The semiconductor device according to claim 1, further comprising a metal body electrically connected to said conductor and applying a predetermined potential, wherein said conductor is made of at least one of impurity-doped polysilicon, graphene, carbon nanotubes, and indium tin oxide (ITO).

7. The semiconductor device according to claim 1, further comprising a metal body electrically connected to said conductor and applying a predetermined potential, said conductor being configured as a conductor film having a pattern shape based on the position of said well region.

8. The semiconductor device according to claim 7, wherein the well region is at least one of a first well region of a first conductivity type and a second well region of a second conductivity type.

9. The semiconductor device according to claim 7, wherein the well region is a first well region of a first conductivity type and a second well region of a second conductivity type, the conductor is composed of a first conductor provided in correspondence with the first well region and a second conductor provided in correspondence with the second well region, and the first conductor and the second conductor are insulated from each other.

10. The semiconductor device according to claim 9, wherein different potentials are applied to the first conductor and the second conductor.

11. The semiconductor device according to claim 10, wherein the first conductor is applied with a potential that generates polarization in the insulator layer that captures electrons or holes generated on the surface of the semiconductor substrate facing the insulator layer.

12. The semiconductor device according to claim 10, wherein the second conductor is applied with a potential that generates polarization in the insulator layer that captures electrons or holes generated on the surface of the semiconductor substrate facing the insulator layer.

13. The semiconductor device described in claim 8, wherein the conductor is composed of second conductors provided corresponding to spaces between a plurality of the first well regions and first conductors provided corresponding to spaces between a plurality of the second well regions, and the first conductors and the second conductors are insulated from each other.

14. The semiconductor device according to claim 1, further comprising an insulating film laminated between said insulating layer and said conductive layer.

15. The semiconductor device according to claim 1, further comprising an insulating film laminated between said insulating layer and said semiconductor substrate.

16. The semiconductor device according to claim 1, further comprising a wiring layer formed of an insulating film having wiring and laminated on the surface of said semiconductor substrate opposite to said insulating layer.

17. The semiconductor device according to claim 1, further comprising a transistor having a plurality of electrodes in the well region and a gate electrode in the wiring layer.

18. The semiconductor device according to claim 17, wherein the well regions are a first well region of a first conductivity type and a second well region of a second conductivity type, a first transistor is configured in the first well region, and a second transistor having characteristics different from those of the first transistor is configured in the second well region.

19. The semiconductor device according to claim 16, wherein the metal body is a through via that is connected to a wiring in the wiring layer and penetrates the semiconductor substrate.

20. A solid-state imaging device comprising: a photoelectric conversion element layer including a photodiode; a first semiconductor substrate layer laminated on the photoelectric conversion element layer; and a second semiconductor substrate layer laminated on the first semiconductor substrate layer, wherein the first semiconductor substrate layer comprises: a semiconductor substrate provided with a well region; an insulator layer laminated on a second surface opposite to a first surface on which an electrode corresponding to the well region is formed; a conductor layer laminated on the second surface opposite to the semiconductor substrate of the insulator layer and having a conductor; and a metal body electrically connected to the conductor and applying a predetermined potential.

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