Imaging element and imaging device

Abstract

This imaging element comprises: a pixel unit in which a plurality of pixels each including a photoelectric conversion part that converts light into electric charge are disposed; an exposure processing unit that calculates an accumulation time during which the electric charge converted by the photoelectric conversion part is accumulated; and a replacement unit that replaces a part of first data related to the signal read from the pixel with second data related to the accumulation time calculated by the exposure processing unit.

Description

Image sensor and image pickup device Incorporation by Reference

[0001] This application claims priority from Japanese Patent Application No. 2024-43884, filed on March 19, 2024, the contents of which are incorporated herein by reference.

[0002] The present invention relates to an imaging element and an imaging device.

[0003] 2. Description of the Related Art A solid-state imaging device including a plurality of pixel cells is known (see, for example, Japanese Patent Application Laid-Open No. 2003-122294). Expanding the dynamic range has been desired for some time.

[0004] JP 2014-75767 A

[0005] The imaging element of the first disclosed technology includes a pixel section in which a plurality of pixels are arranged, each including a photoelectric conversion section that converts light into an electric charge, an exposure processing section that calculates an accumulation time for accumulating the electric charge converted by the photoelectric conversion section, and a replacement section that replaces a portion of first data relating to a signal read out from the pixel with second data relating to the accumulation time calculated by the exposure processing section.

[0006] The imaging device of the second disclosed technique includes the imaging element of the first disclosed technique.

[0007] FIG. 1 is an exploded perspective view showing an example of an image sensor. FIG. 2 is an explanatory diagram showing an example of a specific configuration of a pixel unit. FIG. 3 is a circuit diagram showing an example of a circuit configuration of a pixel. FIG. 4 is an explanatory diagram showing an example of a specific configuration of a control circuit unit. FIG. 5 is an explanatory diagram showing an example of the internal configuration of a control block. FIG. 6 is an explanatory diagram showing an example of signal transmission between a first semiconductor substrate and a second semiconductor substrate in an image sensor. FIG. 7 is an explanatory diagram showing an example of an X-Z cross section of an image sensor according to this embodiment. FIG. 8 is a timing chart showing an example of an image sensing operation of the image sensor. FIG. 9 is a timing chart showing an example of an image sensing operation of the image sensor. FIG. 10 is a timing chart showing an image sensing operation of an image sensor according to a comparative example. FIG. 11 is an explanatory diagram showing an example of a subject imaged by the image sensor. FIG. 12 is a timing chart showing exposure times for each of regions 1 to 5 shown in FIG. 11. FIG. 13 is a plan view showing an example layout of multiple control blocks. FIG. 14 is a circuit diagram showing another example of a pixel circuit configuration. FIG. 15 is a timing chart showing an example of an image sensing operation of the image sensor. FIG. 16 is an exploded perspective view showing another example of an image sensor. FIG. 17 is an explanatory diagram showing another example of the specific configuration of the control circuit unit. FIG. 18 is an explanatory diagram showing the connection relationship between a first semiconductor substrate and a second semiconductor substrate in an image sensor. FIG. 19 is an explanatory diagram showing an example of signal transmission between a first semiconductor substrate and a second semiconductor substrate in an image sensor. FIG. 20 is an explanatory diagram showing the connection relationship between an ADC unit and pixel blocks. FIG. 21 is a timing chart showing image capture operations within pixel blocks of an image sensor. FIG. 22 is an explanatory diagram showing an example of exposure timing for each pixel block. FIG. 23 is a block diagram showing an example of the configuration of autonomous exposure control method 1. FIG. 24 is a block diagram showing an example of the configuration of autonomous exposure control method 2. FIG. 25 is a block diagram showing an example of the configuration of autonomous exposure control method 3. FIG. 26 is an explanatory diagram (part 1) showing image data output from an image sensor. FIG. 27 is an explanatory diagram (part 2) showing image data output from an image sensor. FIG. 28 is a chart showing the correspondence relationship between exposure time and exposure value. FIG. 29 is an explanatory diagram showing Example 1 of embedding exposure values ​​into block image data. FIG. 30 is an explanatory diagram showing an example 2-1 of embedding exposure values ​​into block image data.Fig. 31 is an explanatory diagram showing Example 2-2 of embedding exposure values ​​into block image data. Fig. 32 is an explanatory diagram showing Example 3 of embedding exposure values ​​into block image data. Fig. 33 is an explanatory diagram showing Example 4 of embedding exposure values ​​into block image data. Fig. 34 is a block diagram showing an example of the configuration of an imaging device according to an embodiment.

[0008] The present invention will be described below through embodiments of the invention, but the following embodiments do not limit the scope of the invention as claimed. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0009] In this specification, the X-axis and Y-axis are orthogonal to each other, and the Z-axis is orthogonal to the XY plane. The XYZ-axes form a right-handed system. The direction parallel to the Z-axis may be referred to as the stacking direction of the imaging element. In this specification, the terms "up" and "down" are not limited to the up and down directions in the direction of gravity. These terms merely refer to relative directions in the Z-axis direction. Note that in this specification, the arrangement in the X-axis direction will be described as a "row" and the arrangement in the Y-axis direction as a "column," but the matrix direction is not limited to this.

[0010] <Configuration of Image Sensor> First, the configuration of the image sensor will be described with reference to Figures 1 to 22. The structure of the image sensor may be either a back-illuminated type or a front-illuminated type.

[0011] FIG. 1 is an exploded perspective view showing an example of an image sensor 100A. The image sensor 100A captures an image of a subject. The image sensor 100A generates image data of the captured subject. The image sensor 100A includes a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in FIG. 1, the first semiconductor substrate 110 is stacked on the second semiconductor substrate 120, and the second semiconductor substrate 120 is stacked on the third semiconductor substrate 130.

[0012] The first semiconductor substrate 110 has a pixel section 101. The pixel section 101 outputs a pixel signal based on incident light.

[0013] The second semiconductor substrate 120 has a control circuit section 102 and a peripheral circuit section 121. The peripheral circuit section 121 may have its circuits separated and arranged on the first semiconductor substrate and the second semiconductor substrate. In this case, the circuits can be arranged efficiently, and the chip area can be reduced.

[0014] The control circuit unit 102 receives pixel signals output from the first semiconductor substrate 110. The control circuit unit 102 processes the received pixel signals. The control circuit unit 102 is disposed on the second semiconductor substrate 120 at a position facing the pixel unit 101. For example, the control circuit unit 102 is disposed so as to overlap the pixel unit 101 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked. The control circuit unit 102 may output a control signal to the pixel unit 101 for controlling the driving of the pixel unit 101.

[0015] The peripheral circuit unit 121 controls the driving of the control circuit unit 102. The peripheral circuit unit 121 is arranged around the control circuit unit 102 on the second semiconductor substrate 120. Specifically, the peripheral circuit unit 121 is arranged in an area of ​​the second semiconductor substrate 120 that is arranged outside the area in which the control circuit unit 102 is arranged. The peripheral circuit unit 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel unit 101. The peripheral circuit unit 121 is arranged along two sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit unit 121 is not limited to this example.

[0016] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

[0017] 2 is an explanatory diagram showing an example of a specific configuration of the pixel unit 101. The pixel unit 101 has a plurality of pixel blocks 200. The plurality of pixel blocks 200 are arranged in the row and column directions in the pixel unit 101. Specifically, the plurality of pixel blocks 200 includes M×N (M and N are natural numbers) pixel blocks 200 arranged in the row and column directions in the pixel unit 101. Although the figure shows a case where M is equal to N, M and N may be different.

[0018] The pixel block 200 has a plurality of pixels 201. The plurality of pixels 201 are arranged in rows and columns in the pixel block 200. The pixel block 200 has m×n (m and n are natural numbers) pixels 201 arranged in the rows and columns. For example, the pixel block 200 has 16×16 pixels 201 arranged in the rows and columns. The number of pixels 201 corresponding to the pixel block 200 is not limited to this. Although the illustration shows a case where m is equal to n, m may be different from n.

[0019] The pixel block 200 has a plurality of pixels 201 connected to a common control line (for example, a transfer control line 311 and a discharge control line 312 described later) in the row direction. For example, each pixel 201 in the pixel block 200 is connected to the common control line so that the pixels 201 are set to the same exposure time. Specifically, for example, every n pixels 201 arranged in the row direction are connected by the common control line.

[0020] On the other hand, between different pixel blocks 200, one pixel block 200 may be set to an exposure time different from that of the other pixel block 200. For example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected by different control lines. The multiple pixels 201 in the mth row of one pixel block 200 are commonly connected by a control line different from the common control line to which the multiple pixels 201 in the mth row of the other pixel block 200 are connected. Furthermore, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the multiple pixels 201 included in one pixel block 200 and the multiple pixels 201 included in the other pixel block 200 are connected by different control lines. The pixels 201 in the mth row of one pixel block 200 are commonly connected to a control line that is different from the common control line to which the pixels 201 in the mth row of the other pixel block 200 are connected.

[0021] Furthermore, for example, when one pixel block 200 and the other pixel block 200 are arranged side by side in the row direction, the plurality of pixels 201 included in one pixel block 200 and the plurality of pixels 201 included in the other pixel block 200 are connected by different signal lines 202. The plurality of pixels 201 in the nth column of one pixel block 200 are connected in common by a signal line 202 that is different from the common signal line 202 to which the plurality of pixels 201 in the nth column of the other pixel block 200 are connected. Furthermore, when one pixel block 200 and the other pixel block 200 are arranged side by side in the column direction, the plurality of pixels 201 included in one pixel block 200 and the plurality of pixels 201 included in the other pixel block 200 are connected in common by different signal lines 202. The plurality of pixels 201 in the nth column of one pixel block 200 are connected in common by a signal line 202 that is different from the common signal line 202 to which the plurality of pixels 201 in the nth column of the other pixel block 200 are connected.

[0022] The pixel blocks 200 are arranged corresponding to the control blocks 400A and 400B (see FIGS. 4 and 17) described later. That is, one pixel block 200 is arranged for one control block 400A or 400B.

[0023] Furthermore, multiple pixel blocks 200 may be arranged for one control block 400A, 400B. Even when multiple pixel blocks 200 are arranged for one control block 400A, 400B, different exposure times may be set for each pixel block 200. When two pixel blocks 200 arranged in the column direction are arranged for one control block, the control blocks 400A, 400B control 2m×n pixels 201. Specifically, for example, the control blocks 400A, 400B control 32×16 pixels 201. The number of pixels 201 corresponding to the control blocks 400A, 400B is not limited to this.

[0024] 3 is a circuit diagram showing an example of the circuit configuration of a pixel 201. The pixel 201 includes a photoelectric conversion unit 300 and a readout unit 310. The readout unit 310 has a transfer unit 301, a discharge unit 302, an FD (floating diffusion) 303, a reset unit 304, and a pixel output unit 305, and reads out a pixel signal based on the charge converted by the photoelectric conversion unit 300 to a signal line 202. The pixel output unit 305 has an amplifier unit 351 and a selection unit 352. The transfer unit 301, the discharge unit 302, the FD 303, the reset unit 304, the amplifier unit 351, and the selection unit 352 are collectively referred to as the readout unit 310. The readout unit 310 will be described as an N-channel FET, but the type of transistor is not limited to this.

[0025] The photoelectric conversion unit 300 has a photoelectric conversion function of converting light into electric charges, and accumulates the electric charges generated by photoelectric conversion. The photoelectric conversion unit 300 is configured by, for example, a photodiode.

[0026] The transfer unit 301 transfers the charge of the photoelectric conversion unit 300 to the FD 303. The transfer unit 301 controls the electrical connection between the photoelectric conversion unit 300 and the FD 303. The transfer unit 301 is configured, for example, by a transistor. The transfer unit 301 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the photoelectric conversion unit 300 as the source terminal and a part of the FD 303 as the drain terminal. The gate terminal of the transfer unit 301 is connected to a transfer control line 311 for inputting a transfer control signal φTX. The transfer control line 311 will be described later.

[0027] The discharge unit 302 discharges the charge accumulated in the photoelectric conversion unit 300 to a power supply wiring to which a power supply voltage VDD is supplied. The discharge unit 302 controls the connection between the photoelectric conversion unit 300 and the power supply wiring. The discharge unit 302 is configured, for example, by a transistor. The discharge unit 302 may also be an element that has at least a gate terminal and constitutes part of a transistor in which a part of the photoelectric conversion unit 300 serves as a source terminal and a part of a diffusion region connected to the power supply wiring serves as a drain terminal. The gate terminal of the discharge unit 302 is connected to a discharge control line 312 for inputting a discharge control signal φPDRST. Note that although the discharge unit 302 has been described as discharging the charge of the photoelectric conversion unit 300 to a power supply wiring to which a power supply voltage VDD is supplied, the discharge unit 302 may also be discharged to a power supply wiring to which a power supply voltage different from the power supply voltage VDD is supplied.

[0028] The FD 303 accumulates the charges transferred from the photoelectric conversion unit 300 by the transfer unit 301 .

[0029] The reset unit 304 discharges the charge accumulated in the FD 303 to the power supply wiring to which the power supply voltage VDD is supplied. The reset unit 304 resets the potential of the FD 303 to the power supply voltage VDD, which is a reference potential. The reset unit 304 controls the electrical connection between the FD 303 and the power supply wiring. The reset unit 304 is configured, for example, by a transistor. The reset unit 304 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the FD 303 as a source terminal and a part of a diffusion region connected to the power supply wiring as a drain terminal. The gate terminal of the reset unit 304 is connected to a reset control line 313 for inputting a reset control signal φRST. The reset control line 313 will be described later.

[0030] The pixel output unit 305 outputs a pixel signal based on the potential of the FD 303 to the signal line 202. The pixel output unit 305 has an amplifier 351 and a selection unit 352. The amplifier 351 is configured with a transistor. The amplifier 351 has a gate terminal connected to the FD 303, a drain terminal connected to a power supply line to which a power supply voltage VDD is supplied, and a source terminal connected to the drain terminal of the selection unit 352.

[0031] The selection unit 352 controls the electrical connection between the pixel 201 and the signal line 202. When the selection unit 352 electrically connects the pixel 201 and the signal line 202, a pixel signal is output from the pixel 201 to the signal line 202. The selection unit 352 is configured by a transistor. The selection unit 352 may also be an element that has at least a gate terminal and configures part of a transistor with a part of the amplifier unit 351 as a source terminal and a part of a diffusion region connected to the signal line 202 as a drain terminal. The gate terminal of the selection unit 352 is connected to a selection control line 314 that spans multiple pixel blocks 200 and is used to input a selection control signal φSEL. The source terminal of the selection unit 352 is connected to the load current source 306.

[0032] The load current source 306 is connected to the signal line 202 and supplies a current for reading out pixel signals from the pixels 201. This stabilizes the operation of the amplifier unit 351. The load current source 306 is also connected to the signal line 202. The load current source 306 may be provided on the first semiconductor substrate 110 or on the second semiconductor substrate 120.

[0033] The FD 303 and the pixel output unit 305 may be shared with other pixels 201. For example, the FD 303 and the pixel output unit 305 may be shared by a plurality of pixels 201 arranged side by side in the row or column direction. The pixel 201 may also be configured with a plurality of photoelectric conversion units 300 and transfer units 301.

[0034] FIG. 4 is an explanatory diagram showing an example of a specific configuration of the control circuit unit 102. The control circuit unit 102 has multiple control blocks 400A. The multiple control blocks 400A are arranged in a row and column direction in the control circuit unit 102. Specifically, the control circuit unit 102 has M×N control blocks 400A. When one pixel block 200 is arranged for one control block 400A, the control circuit unit 102 has the control block 400A directly below the pixel block 200. One pixel block 200 and one control block 400A have substantially the same shape and size. Furthermore, when multiple pixel blocks 200 arranged in a column direction are arranged for one control block 400A, the control circuit unit 102 has one control block 400A directly below the multiple pixel blocks 200 arranged in a column direction.

[0035] The control block 400A is provided corresponding to the pixel block 200. As an example of the correspondence between the control block and the pixel block, for example, the control block 400A is located directly below the pixel block 200 in the direction in which the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked (stacking direction). The control block 400A is electrically connected to the pixel block 200 via a signal line 202, a transfer control line 311, and a discharge control line 312. Specifically, the control block 400A located directly below the pixel block 200 in the stacking direction is electrically connected to the pixel block 200 directly above it in the stacking direction (hereinafter referred to as the corresponding pixel block 200) via local control lines such as the transfer control line 311 and the discharge control line 312. The control block 400A also receives pixel signals output from the pixels 201 of the corresponding pixel block 200 via the signal line 202.

[0036] The control block 400A controls the driving of the corresponding pixel block 200. For example, the control block 400A controls the exposure time of the pixels 201 included in the corresponding pixel block 200. The control block 400A also has a signal processing unit 402 that processes input signals, and processes pixel signals output from the pixels 201 included in the corresponding pixel block 200. For example, the control block 400A converts analog pixel signals output from the pixels 201 included in the corresponding pixel block 200 into digital signals.

[0037] The control block 400A has a pixel control unit 401 and a signal processing unit 402. The pixel control unit 401 has an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413, and controls the pixels 201 of the pixel unit 101. The signal processing unit 402 has a signal input unit 421, a signal conversion unit 422, and a signal output unit 423, and converts analog pixel signals from the pixel unit 101 into digital signals and transfers them to the pixel control unit 401 and the data processing unit 103.

[0038] The autonomous exposure processing unit 411 is a circuit that calculates the exposure time of the pixels 201 included in the corresponding pixel block 200 based on the pixel signals converted into digital signals by the signal processing unit 402. Details of the autonomous exposure processing unit 411 will be described later.

[0039] The exposure control unit 412 is a circuit that controls the exposure of the pixels 201 included in the corresponding pixel block 200 based on the exposure time calculated by the autonomous exposure processing unit 411. Specifically, the exposure control unit 412 generates a control signal for controlling the exposure time (charge accumulation time of the photoelectric conversion unit 300) of the pixels 201 included in the corresponding pixel block 200. For example, the exposure control unit 412 adjusts the start timing or end timing of exposure of the pixels 201 included in the corresponding pixel block 200 to control the exposure time for each pixel block 200. The exposure control unit 412 is provided in the control block 400A and extends in the row direction.

[0040] The pixel driving unit 413 outputs the control signal generated by the exposure control unit 412 to the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 is a driving circuit that drives the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 drives the pixels 201 in a pixel row selected from the pixels 201 included in the corresponding pixel block 200. The pixel driving unit 413 is provided extending in the column direction. As a result, the pixel driving unit 413 is disposed at a position corresponding to the m pixels 201 arranged in the column direction. In the control block 400A, the autonomous exposure processing unit 411, exposure control unit 412, and pixel driving unit 413 are arranged in an L shape, with the pixel driving unit 413 extending in the column direction and the autonomous exposure processing unit 411 and exposure control unit 412 extending in the row direction.

[0041] The signal input unit 421 receives pixel signals output from pixels 201 included in the corresponding pixel block 200. The signal input unit 421 outputs the received pixel signals to the signal conversion unit 422. The signal input unit 421 may be provided for each of n pixels 201 arranged in the row direction in the corresponding pixel block 200. The signal input unit 421 may include a processing circuit that performs signal processing such as noise removal on the pixel signals output from the first semiconductor substrate 110. The signal input unit 421 may also include a voltage adjustment circuit that adjusts the voltage of the signal line 202 connected to the pixel 201 included in the corresponding pixel block 200 so that it does not fall below a predetermined value. The load current source 306 may be disposed in the signal input unit 421 included in the corresponding control block 400A.

[0042] The signal conversion unit 422 converts the pixel signals output from the signal input unit 421 into digital signals. The signal conversion unit 422 sequentially converts into digital signals the pixel signals output from m pixels 201 arranged in the column direction in the corresponding pixel block 200. The signal conversion unit 422 converts into parallel digital signals the pixel signals output from the pixels 201 arranged in n columns in the row direction in the corresponding pixel block 200.

[0043] The signal output unit 423 stores the pixel signals converted into digital signals by the signal conversion unit 422. The signal output unit 423 may have a latch circuit for storing the digital signals. The signal output unit 423 is arranged between the signal conversion unit 422 and the autonomous exposure processing unit 411 in the column direction. The signal output unit 423 outputs the pixel signals converted into digital signals to the outside of the control circuit unit 102. The signal output unit 423 is provided in the control block 400A and extends in the row direction. The signal output unit 423 is arranged between the signal conversion unit 422 and the autonomous exposure processing unit 411 in the column direction.

[0044] 5 is an explanatory diagram showing an example of the internal configuration of the control block 400A. The signal conversion unit 422 includes n comparators 501 and n storage units 502. The exposure control unit 412 includes a pixel block control unit 503 and a level shift unit 504. A combination of one comparator 501 and a storage unit 502 connected to that comparator 501 forms one ADC (Analog-to-Digital Converter) 500.

[0045] The comparators 501 are provided extending in the column direction in the control block 400A. The n comparators 501 are arranged side by side in the row direction. A comparator 501 is arranged for every m pixels 201 arranged in the column direction in the corresponding pixel block 200. The comparators 501 sequentially read out pixel signals from the m pixels 201 arranged in the column direction in the corresponding pixel block 200 and convert them into digital signals.

[0046] The storage unit 502 stores the pixel signals converted into digital signals using the comparator 501. The storage unit 502 is provided on the negative side of the comparator 501 in the Y-axis direction in the signal conversion unit 422. For example, the storage unit 502 has a latch circuit. The storage unit 502 may have a memory configured using an SRAM or the like.

[0047] The pixel block control unit 503 controls the operation of the transfer unit 301 and discharge unit 302 of the pixels 201 included in the corresponding pixel block 200. Specifically, the pixel block control unit 503 outputs a transfer control signal φTX for controlling the transfer unit 301 of the pixels 201 included in the corresponding pixel block 200, and a discharge control signal φPDRST for controlling the discharge unit 302 of the pixels 201 included in the corresponding pixel block 200. The pixel block control unit 503 is provided extending in the row direction in the control block 400A. The pixel block control unit 503 is arranged between the level shift unit 504 and the autonomous exposure processing unit 411 in the column direction.

[0048] The level shift unit 504 adjusts the voltage level of the control signal output from the pixel block control unit 503. Specifically, the level shift unit 504 boosts the voltage level of the transfer control signal φTX output from the pixel block control unit 503. The level shift unit 504 also boosts the voltage level of the discharge control signal φPDRST output from the pixel block control unit 503.

[0049] The transfer unit 301 receives the transfer control signal φTX boosted by the level shift unit 504 via a transfer control line 311. The discharge unit 302 receives the discharge control signal φPDRST boosted by the pixel block control unit 503 via a discharge control line 312.

[0050] In this way, the level shift unit 504 boosts the transfer control signal φTX and the discharge control signal φPDRST to voltage levels used in the transfer unit 301 and the discharge unit 302 of the readout unit 310 of the pixel 201. The level shift unit 504 is provided in the control block 400A, extending in the row direction.

[0051] The level shift unit 504 is provided closer to the outer periphery of the control block 400A than the pixel block control unit 503. The end of the level shift unit 504 on the positive side in the X-axis direction and the end on the negative side in the Y-axis direction are located at the outermost sides of the control block 400A. The end of the level shift unit 504 on the negative side in the X-axis direction is in contact with the pixel driving unit 413.

[0052] The level shift unit 504 and pixel drive unit 413 handle the level-shifted signal. On the other hand, the autonomous exposure processing unit 411, pixel block control unit 503, level shift unit 504, and pixel drive unit 413 handle the pixel signal output from the first semiconductor substrate 110.

[0053] Here, each component of the control block 400A is formed in a well region provided in the second semiconductor substrate 120. The well regions are provided separately according to the voltage level of the signals to be handled. The well regions are separated depending on whether the power supply used is a digital power supply or an analog power supply. Furthermore, even if the signal conversion unit 422 uses the same analog power supply, it may be separated from an area that uses another analog power supply from the standpoint of noise. Separating the well regions requires well isolation regions spaced apart according to the manufacturing process rules.

[0054] In the control block 400A, the well regions for forming the level shift unit 504 and the pixel driving unit 413 are separated from other well regions. For example, the level shift unit 504 and the pixel driving unit 413 can be provided in an L-shape, thereby sharing the well regions of the level shift unit 504 and the pixel driving unit 413. Sharing the well region makes it possible to omit a well isolation region, thereby improving layout efficiency.

[0055] Furthermore, by mirroring the circuit layout of adjacent blocks, adjacent blocks can share well regions and eliminate well isolation areas, thereby improving layout efficiency. Details will be described later with reference to FIG. 13.

[0056] The L-shaped pixel control unit 401 forms part of the outer periphery of the control block 400 A. This allows the well region to be shared with other control blocks 400 A adjacent in the row and column directions.

[0057] 6 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100A. The global driving unit 600 is provided in the peripheral circuit unit 121 arranged on either side of the control circuit unit 102.

[0058] The transfer control line 311a and the discharge control line 312a are each connected to the pixels 201 included in the pixel block 200a. The transfer control line 311a is connected to the gate terminal of the transfer unit 301 included in the pixel 201 included in the pixel block 200a, and the discharge control line 312a is connected to the gate terminal of the discharge unit 302 included in the pixel 201 included in the pixel block 200a. The transfer control line 311a supplies the transfer control signal φTX output from the control block 400Aa to the transfer unit 301 included in the pixel 201 included in the pixel block 200a. The discharge control line 312a supplies the discharge control signal φPDRST output from the control block 400Aa to the discharge unit 302 included in the pixel 201 included in the pixel block 200a.

[0059] Similarly, the transfer control line 311b and the discharge control line 312b are each connected to the pixel 201 included in the pixel block 200b. The transfer control line 311b is connected to the gate terminal of the transfer unit 301 included in the pixel 201 included in the pixel block 200b, and the discharge control line 312b is connected to the gate terminal of the discharge unit 302 included in the pixel 201 included in the pixel block 200b. The transfer control line 311b supplies the transfer control signal φTX output from the control block 400Ab to the transfer unit 301 included in the pixel 201 included in the pixel block 200b. The discharge control line 312b supplies the discharge control signal φPDRST output from the control block 400Ab to the discharge unit 302 included in the pixel 201 included in the pixel block 200b.

[0060] When there is no need to distinguish between the transfer control lines 311a and 311b, they are referred to as transfer control lines 311. When there is no need to distinguish between the discharge control lines 312a and 312b, they are referred to as discharge control lines 312.

[0061] The transfer control line 311 and the discharge control line 312 are examples of local control lines connected to the first pixel of the pixel block 200. Note that the transfer control line 311 and the discharge control line 312 are commonly connected to n pixels 201 arranged in the row direction in the pixel block 200.

[0062] The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 600 is connected to a reset control line 313, a selection control line 314, and a transfer selection control line 603 that output control signals to each pixel block 200.

[0063] The global driving unit 600 supplies a reset control signal φRST and a selection control signal φSEL to the plurality of pixel blocks 200 via a reset control line 313 and a selection control line 314. The global driving unit 600 supplies a transfer selection control signal φTXSEL to the plurality of control blocks 400A via a transfer selection control line 603.

[0064] The transfer selection control signal φTXSEL is supplied from the global drive unit 600 to the control block 400A to control the exposure time for each pixel block 200. The control block 400A, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The control block 400A determines whether or not to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

[0065] For example, when the transfer control signal φTX determines the end time of exposure, the control block 400A extends the exposure time by skipping the transfer control signal φTX. Also, when the transfer control signal φTX determines the start time of exposure, the control block 400A can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φPDRST determines the start or end time of exposure.

[0066] The reset control line 313, the selection control line 314, and the transfer selection control line 603 are provided in common to a plurality of pixel blocks 200. The reset control line 313, the selection control line 314, and the transfer selection control line 603 are wired so as to cross the first semiconductor substrate 110 in the row direction. The reset control line 313, the selection control line 314, and the transfer selection control line 603 may also be wired so as to cross the first semiconductor substrate 110 in the column direction.

[0067] For example, the reset control line 313 is connected to the gate terminal of the reset unit 304 of the pixel 201 in the pixel block 200 and supplies the reset control signal φRST. The selection control line 314 is connected to the gate terminal of the selection unit 352 of the pixel 201 in the pixel block 200 and supplies the selection control signal φSEL. The transfer selection control line 603 is connected to each of the multiple control blocks 400A and supplies the transfer selection control signal φTXSEL to the pixel control unit 401.

[0068] Although the global driving unit 600 outputs the transfer selection control signal φTXSEL to the control block 400A from the second semiconductor substrate 120 via the first semiconductor substrate 110, the transfer selection control signal φTXSEL may be output to the control block 400A without passing through the first semiconductor substrate 110. In this case, the transfer selection control line 603 is provided on the second semiconductor substrate 120.

[0069] The bonding portions 610 are provided on the bonding surfaces where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The bonding portions 610 align the transfer control lines 311, the discharge control lines 312, and the transfer selection control lines 603 between the first semiconductor substrate 110 and the second semiconductor substrate 120. Each of the bonding portions 610 is composed of a pair of conductive bonding pads, and is bonded and electrically connected by applying pressure to the first semiconductor substrate 110 and the second semiconductor substrate 120, for example.

[0070] The image sensor 100A controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer unit 301 and the discharge unit 302 using local control lines such as the transfer control line 311 and the discharge control line 312. The image sensor 100A can control the exposure time with fewer control lines by combining local control lines such as the transfer control line 311 and the discharge control line 312 with global control lines such as the reset control line 313, the selection control line 314, and the transfer selection control line 603.

[0071] FIG. 7 is an explanatory diagram showing an example of an X-Z cross section of an image sensor 100A according to this embodiment. While FIG. 7 shows a back-illuminated image sensor 100A, the image sensor 100A is not limited to a back-illuminated type. The image sensor 100A includes a microlens layer 700, a color filter layer 702, a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in the figure, light from a subject is incident in the direction indicated by the outline arrow (the negative Z-axis direction in the figure). The surface of the first semiconductor substrate 110 on which light is incident (the positive Z-axis side in the figure) may be referred to as the front surface, and the surface on the opposite side (the negative Z-axis side in the figure) may be referred to as the back surface.

[0072] The microlens layer 700 has a plurality of microlenses 701. The plurality of microlenses 701 are stacked on the positive side of the Z axis relative to the color filter layer 702. Light is incident on the microlenses 701. The microlenses 701 focus the incident light onto the photoelectric conversion unit 300. A microlens 701 may be provided for each photoelectric conversion unit 300. The optical axis L of the microlens 701 is the stacking direction (direction parallel to the Z axis) of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130.

[0073] Alternatively, in the peripheral portion of the pixel 201, so-called microlens shift may be performed, in which the position of the microlens 701 is shifted toward the center of the pixel portion 101. Generally, the photographic lens of a camera has a pupil position, and light is incident perpendicularly at the center of the optical axis, but light is incident obliquely at the periphery of the optical axis. Therefore, by performing microlens shift, it is possible to suppress peripheral shading.

[0074] The color filter layer 702 has a plurality of color filters 703 and a passivation film 704. The color filter layer 702 is stacked on the positive side of the Z axis relative to the first semiconductor layer 711. The color filter 703 is an optical filter that transmits light in a specific wavelength region. The color filter 703 is an optical filter having specific spectral characteristics. The multiple color filters 703 have multiple optical filters with different spectral characteristics, and transmit light in different wavelength regions. The multiple color filters 703 are arranged in a specific array (for example, a Bayer array).

[0075] An example of the first semiconductor substrate 110 is a back-illuminated CMOS image sensor. The first semiconductor substrate 110 has a first semiconductor layer 711 and a first wiring layer 712. The first semiconductor layer 711 is provided on the positive side of the Z axis relative to the first wiring layer 712. The first semiconductor layer 711 has a plurality of pixel blocks 200 arranged two-dimensionally in the row and column directions. The first semiconductor layer 711 has a plurality of pixels 201 arranged two-dimensionally in the row and column directions. Each of the plurality of pixels 201 has a plurality of photoelectric conversion units 300 that accumulate charge based on incident light, and a plurality of readout units 310.

[0076] The first wiring layer 712 is provided closer to the second semiconductor substrate 120 (toward the negative side of the Z axis in the drawing) than the first semiconductor layer 711. The first wiring layer 712 has a plurality of wires 713 made of a conductor film (metal film), a plurality of bonding pads 714, and an insulating film (insulating layer).

[0077] The first wiring layer 712 has a plurality of wirings 713 electrically connected to a power supply, a circuit, etc. In the first semiconductor substrate 110, the wirings 713 specifically include, for example, a power supply wiring to which a predetermined power supply voltage is supplied, a signal line 202 that transmits pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, a transfer control line 311 that transmits control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels), a discharge control line 312, a reset control line 313, a selection control line 314, and a transfer selection control line 603. The first wiring layer 712 may be multi-layered, and may include passive elements and active elements.

[0078] The bonding pads 714 are provided on the surface (the surface on the negative side of the Z axis) of the first wiring layer 712 and are connected to the wiring 713. As will be described later, the bonding pads 714 are also used to assist in connecting layers together. The bonding pads 714 are formed of a conductive material such as copper. The bonding pads 714 may also be formed of gold, silver, or aluminum. An insulating layer (insulating film) is formed between the multiple wirings 713 and between the multiple bonding pads 714.

[0079] The second semiconductor substrate 120 has a second semiconductor layer 721, a second wiring layer 722, and a wiring layer 723. The second wiring layer 722 is provided closer to the first semiconductor substrate 110 than the second semiconductor layer 721 (positive side of the Z axis in the figure). The wiring layer 723 is provided closer to the third semiconductor substrate 130 than the second semiconductor layer 721 (negative side of the Z axis in the figure), and is provided between the second semiconductor layer 721 and the third semiconductor substrate 130. The second semiconductor layer 721 has a control circuit unit 102 and a peripheral circuit unit 121. The control circuit unit 102 has a plurality of control blocks 400A arranged two-dimensionally in the row and column directions.

[0080] Similar to the first semiconductor substrate 110, the second semiconductor substrate 120 has a plurality of wirings 713 provided on the second wiring layer 722, a plurality of bonding pads 714 provided on the second wiring layer 722 and the wiring layer 723, and an insulating film (insulating layer) provided on the second wiring layer 722 and the wiring layer 723.

[0081] The second wiring layer 722 has a plurality of wirings 713 and bonding pads 714 for electrically connecting to a power supply or circuit, transmitting signals from the pixel unit 101 to the control circuit unit 102, and transmitting signals from the control circuit unit 102 to the pixel unit 101. In the second semiconductor substrate 120, the wirings 713 specifically include, for example, a power supply wiring for supplying a predetermined power supply voltage, a signal line 202 for transmitting pixel signals from the first semiconductor substrate 110 (pixels) to the second semiconductor substrate 120, and a transfer control line 311, a discharge control line 312, a reset control line 313, a selection control line 314, and a transfer selection control line 603 for transmitting control signals from the second semiconductor substrate 120 to the first semiconductor substrate 110 (pixels). The second wiring layer 722 may be multi-layered and may include passive and active elements. The wirings 713 and bonding pads 714 may also be provided in the wiring layer 723.

[0082] The second semiconductor substrate 120 further includes through-silicon vias (TSVs) 724 that connect the circuits provided on the front and back surfaces of the second semiconductor substrate 120 to each other. The TSVs 724 are preferably provided in the peripheral region. The TSVs 724 transmit image data and the like generated by the data processing unit 103 to the first semiconductor substrate 110. The TSVs 724 may also be provided in the first semiconductor substrate 110 and the third semiconductor substrate 130.

[0083] The third semiconductor substrate 130 has a third semiconductor layer 731 in which the data processing unit 103 is provided, and a third wiring layer 732. The third wiring layer 732 is provided between the third semiconductor layer 731 and the second semiconductor substrate 120.

[0084] Similar to the first semiconductor substrate 110, the third semiconductor substrate 130 has wiring 713 and a plurality of bonding pads 714 provided on a third wiring layer 732. The third wiring layer 732 has the plurality of wirings 713 and bonding pads 714 for electrical connection to a power supply, a circuit, etc., for transmitting signals from the control circuit unit 102 to the data processing unit 103, and for transmitting signals from the data processing unit 103 to the control circuit unit 102 of the second semiconductor substrate 120.

[0085] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 are stacked by electrical connection between the bonding pads 714 provided on each layer and bonding between the wiring layers (insulating layers) of each layer.

[0086] When the first semiconductor substrate 110 and the second semiconductor substrate 120 are stacked, an interface 720 is formed between the negative surface of the first wiring layer 712 along the Z axis and the positive surface of the second wiring layer 722. Similarly, when the second semiconductor substrate 120 and the third semiconductor substrate 130 are stacked, an interface 730 is formed between the negative surface of the wiring layer 723 along the Z axis and the positive surface of the third wiring layer 732. A plurality of bonding pads 714 are arranged on the interface 720 and the interface 730. Specifically, corresponding bonding pads 714 are aligned, and the two layers are stacked, thereby electrically connecting the aligned bonding portions.

[0087] The first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 may be stacked in the form of wafers before being made into chips, and then formed (individuated) by dicing the stacked wafers, or may be formed by dicing each of the first semiconductor substrate 110, the second semiconductor substrate 120, and the third semiconductor substrate 130 wafers and then stacking them.

[0088] 8 is a timing chart showing an example 1 of imaging operation of the image sensor 100A. Fig. 8 shows an example of imaging operation in which the drive of the image sensor 100A is controlled by the transfer control signal φTX, the discharge control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL. In Fig. 8, the discharge control signal φPDRST is locally controlled, while the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL are globally controlled. Note that the suffixes <1>, <2>, ..., <m> at the end of each signal on the left side indicate the row number of the pixel 201 within the pixel block.

[0089] The discharge control signal φPDRST controls the timing at which exposure starts. The exposure start timing corresponds to the falling edge of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the discharge control signal φPDRST. Because the discharge control signal φPDRST is locally controlled, the exposure time can be adjusted for each pixel block 200.

[0090] The transfer control signal φTX controls the timing to end exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303. The timing to end exposure corresponds to the falling edge of the transfer control signal φTX (for example, time T4). Because the transfer control signal φTX is a globally controlled signal, the timing to end exposure is the same for each pixel block 200.

[0091] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge in the FD 303. By discharging the charge in the FD 303 before the timing of the end of exposure, the influence of the charge remaining in the FD 303 when the charge is transferred from the photoelectric conversion unit 300 can be suppressed.

[0092] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. The selection control signal φSEL controls the on / off of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the transfer control signal φTX being turned on. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0093] The image sensor 100A locally controls the discharge control signal φPDRST, thereby changing the exposure start timing for each pixel block 200 and controlling the exposure time for each pixel block 200. The image sensor 100A may also locally control the transfer control signal φTX to control the exposure end timing for each pixel block 200. The image sensor 100A may also locally control both the transfer control signal φTX and the discharge control signal φPDRST to control both the exposure start timing and end timing for each pixel block 200.

[0094] 9 is a timing chart showing an example 2 of imaging operation of the image sensor 100A. Fig. 9 shows an example of imaging operation in which the drive of the image sensor 100A is controlled by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL. The image sensor 100A differs from the case of Fig. 8 in that the timing of the start of exposure is controlled by the transfer control signal φTX. The differences from Fig. 8 will be particularly described.

[0095] The transfer control signal φTX controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0096] At exposure start time T5, the transfer control signal φTX falls, thereby starting exposure. That is, before exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure starts in each pixel block 200 can be changed. However, the timing at which exposure starts in each pixel block 200 may also be synchronized.

[0097] Furthermore, at exposure end time T7, the transfer control signal φTX falls, thereby ending the exposure. That is, before exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303, and exposure ends at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure ends can be changed for each pixel block 200. However, the timing at which exposure ends can also be synchronized for each pixel block 200.

[0098] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. At time T6, the pixel 201 for which the selection control signal φSEL is set high outputs a pixel signal to the signal line 202.

[0099] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the FD 303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the timing of readout, charge is transferred from the photoelectric conversion unit 300 to the FD 303. The reset control signal φRST has the same switching timing during readout, so it can be made common to the pulse of the selection control signal φSEL.

[0100] By locally controlling the transfer control signal φTX, the image sensor 100A can change the timing of starting or ending exposure for each pixel block 200, thereby controlling the exposure time for each pixel block 200. Furthermore, the image sensor 100A uses a common pulse for the reset control signal φRST and the selection control signal φSEL, which allows for further simplification of the control circuit.

[0101] 10 is a timing chart showing an imaging operation of an image sensor according to a comparative example, in which the drive of the image sensor is controlled by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL, and the exposure time is not controlled for each pixel block 200.

[0102] In the comparative example, the start of exposure is controlled by the transfer control signal φTX and the reset control signal φRST. The exposure start timing is the timing (time t1) of the falling edges of the transfer control signal φTX and the reset control signal φRST. The exposure end timing is the timing (time t2) of the falling edge of the transfer control signal φTX. In the comparative example, the exposure start timing and end timing are controlled globally, and the exposure time is not controlled for each pixel block 200.

[0103] 11 is an explanatory diagram showing an example of a subject captured by the image sensor 100 A. In FIG. 11, the image sensor 100 A controls the exposure time for each pixel block 200 in a situation where the afternoon sun is shining outside a tunnel.

[0104] Areas 1 to 5 are five areas divided according to brightness. Areas 1 to 5 are numbered in order of brightness. Area 1 is the brightest area where the setting sun is directly visible. Area 2 is the area corresponding to the tunnel exit and is darker than Area 1. Area 3 is the area where the setting sun is reflected inside the tunnel and is darker than Area 2. Area 4 is the area inside the tunnel where the setting sun shines in from the exit and is darker than Area 3. Area 5 is the darkest area inside the tunnel where the setting sun does not shine in from the exit.

[0105] The image sensor 100A controls the exposure time for each pixel block 200 according to the brightness of each region. The image sensor 100A controls the exposure time so that the brighter the pixel block 200, the shorter the exposure time. The exposure time for region 1 is set to the shortest, and the exposure time for region 5 is set to the longest. For example, the exposure times for regions 1 to 5 are 1 / 15360 s, 1 / 1920 s, 1 / 960 s, 1 / 240 s, and 1 / 120 s.

[0106] Fig. 12 is a timing chart showing the exposure time for each of regions 1 to 5 shown in Fig. 11. In Fig. 12, the image sensor 100A controls the exposure time for each of the pixel blocks 200 in regions 1 to 5 shown in Fig. 11. The section from time T11 to time T19 corresponds to the video frame rate.

[0107] In region 1, the control block 400A controls driving so that the exposure time in the pixel block 200 is a predetermined exposure time ET1. The control block 400A controls the start of exposure with a discharge control signal φPDRST and the end of exposure with a transfer control signal φTX. In region 1, exposure ends at each of times T12 to T19.

[0108] In region 2, the control block 400A controls driving so that the exposure time in the pixel block 200 is exposure time ET2, which is longer than ET1. The control block 400A makes the exposure start time for region 2 earlier than region 1 and the exposure end time coincident with region 1. Therefore, in region 2, exposure ends at each of times T12 to T19. The exposure time ET2 for region 2 is shorter than the period of the sensor rate.

[0109] In region 3, the control block 400A controls driving so that the exposure time in the pixel block 200 is an exposure time ET3 that is longer than ET2. The control block 400A makes the exposure start time for region 3 earlier than for region 2, and makes the exposure end time coincident with that for region 2. Therefore, in region 3, exposure ends at each of times T12 to T19. The exposure time ET3 for region 3 is set to be the same as the period of the sensor rate.

[0110] In region 4, the control block 400A controls driving so that the exposure time in the pixel block 200 is an exposure time ET4 that is longer than ET3. The control block 400A sets the same exposure start time for region 4 as for region 3, but skips the end time of the exposure using the transfer selection control signal φTXSEL. The control block 400A achieves an exposure time four times longer than that of region 3 by skipping three times using the transfer selection control signal φTXSEL. In region 4, the transfer selection control signal φTXSEL is supplied at each of times T12 to T14.

[0111] In region 5, the control block 400A controls driving so that the exposure time in the pixel block 200 is an exposure time ET5 that is longer than ET4. The control block 400A sets the same exposure start time for region 5 as for region 4, but increases the number of times the exposure end time is skipped using the transfer selection control signal φTXSEL. The control block 400A skips seven times using the transfer selection control signal φTXSEL, thereby achieving an exposure time that is twice that of region 4. The exposure time ET5 for region 5 is set to be the same as the period of the video frame rate. In region 5, the transfer selection control signal φTXSEL is supplied at each of times T12 to T18.

[0112] The image sensor 100A achieves short-time exposure by shortening the interval between the transfer control signal φTX and the discharge control signal φPDRST. The image sensor 100A also achieves long-time exposure by skipping the control of the transfer control signal φTX using the transfer selection control signal φTXSEL. This allows for an expanded dynamic range.

[0113] 13 is a plan view showing an example layout of a plurality of control blocks 400A. The plurality of control blocks 400A are arranged in such a way that adjacent control blocks 400A are inverted. FIG. 13 shows an example of 12 control blocks 400A out of the plurality of control blocks 400A provided in the control circuit unit 102.

[0114] The inverted arrangement means that the areas in which the components of the control block 400A (for example, the exposure control unit 412, the pixel driving unit 413, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423) are formed are arranged in a mirror-inverted arrangement (arranged in line symmetry) around the boundary between the control blocks 400A. The circuits of the components of the control block 400A do not have to be arranged in an inverted arrangement. Furthermore, the readout order of the pixels in the control block 400A is not limited to being inverted.

[0115] For example, when adjacent control blocks 400A in the row direction are arranged in an inverted manner, the components of the control blocks 400A are arranged in an inverted manner in the row direction, and therefore the pixel driving units 413 are arranged adjacent to each other at the boundary between the control blocks 400A. This allows the adjacent pixel driving units 413 in the row direction to be laid out as a single pixel driving unit 413, thereby improving the layout efficiency of the control blocks 400A.

[0116] Similarly, when adjacent control blocks 400A in the column direction are arranged in an inverted manner, the components of the control blocks 400A are arranged in an inverted manner in the column direction, so that identical components are arranged adjacent to each other at the boundary between the two control blocks 400A. This allows the signal input units 421 adjacent to each other in the column direction to be laid out as a single signal input unit 421, thereby improving the layout efficiency of the control blocks 400A.

[0117] The control blocks 400A are arranged in a mirror image of the adjacent control blocks 400A. Although all the control blocks 400A are arranged in a mirror image in the row and column directions, they may be arranged in a mirror image in either the row or column direction. For example, the signal conversion unit 422 of a control block 400A is arranged in a mirror image of the signal conversion unit 422 of the control block 400A adjacent to it in the row direction. Furthermore, the signal conversion unit 422 of a control block 400A is also arranged in a mirror image of the signal conversion unit 422 of the control block 400A adjacent to it in the column direction.

[0118] The control block 400Aa and the control block 400Ab are arranged next to each other in the row direction. The control block 400Aa is arranged in an inverted manner relative to the control block 400Ab. The level shift unit 504 of the control block 400Aa is provided in the same well region as the level shift unit 504 of the control block 400Ab. Similarly, the pixel block control unit 503, the memory unit 502, and the signal output unit 423 are provided in the same well region in the control block 400Aa and the control block 400Ab.

[0119] The control block 400Ab and the control block 400Ac are arranged next to each other in the row direction. The control block 400Ab is arranged in an inverted manner relative to the control block 400Ac. The pixel driving unit 413 of the control block 400Ab is provided in the same well region as the pixel driving unit 413 of the control block 400Ac. The well region of the pixel driving unit 413 may also be shared with the well region of the level shift unit 504.

[0120] The control block 400Aa and the control block 400Ad are arranged next to each other in the column direction. The control block 400Aa is arranged in an inverted manner relative to the control block 400Ad. The pixel driving unit 413 of the control block 400Aa is provided in the same well region as the pixel driving unit 413 of the control block 400Ad. Furthermore, the signal conversion unit 422 of the control block 400Aa is provided in the same well region as the signal conversion unit 422 of the control block 400Ad.

[0121] The control block 400Ad and the control block 400Ae are arranged adjacent to each other in the column direction. The control block 400Ad is arranged in an inverted manner relative to the control block 400Ae. The pixel driving unit 413 and the level shifting unit 504 of the control block 400Ad are arranged in the same well region as the pixel driving unit 413 and the level shifting unit 504 of the control block 400Ae.

[0122] By inverting the arrangement of the control blocks 400A in the image sensor 100A, the layout can be made more efficient even when signal processing is performed in parallel for each control block 400A. By inverting the arrangement of the control blocks 400A in the XY plane, the image sensor 100A can share well regions with adjacent control blocks 400A. This reduces the number of times the well regions need to be switched, improving area efficiency.

[0123] 14 is a circuit diagram showing another example of the circuit configuration of the pixel 201. In the pixel 201, the same components as those in FIG. 3 are assigned the same reference numerals, and descriptions thereof will be omitted. The pixel 201 does not have the discharge unit 302 that was provided in the pixel 201. When discharging the charges accumulated in the photoelectric conversion unit 300 to the power supply wiring to which the power supply voltage VDD is supplied, a transfer control signal φTX is input to the gate terminal of the transfer unit 301, and a reset control signal φRST is input to the gate terminal of the reset unit 304.

[0124] Fig. 15 is a timing chart showing an imaging operation example 3 of the image sensor 100A. Fig. 15 shows an imaging operation example in which the pixel 201 shown in Fig. 14 is used to control the driving of the image sensor 100A by the transfer control signal φTX, the reset control signal φRST, and the selection control signal φSEL. The image sensor 100A differs from the case of Fig. 12 in that the timing of the start of exposure is controlled by the transfer control signal φTX. The differences from Fig. 12 will be particularly described.

[0125] The transfer control signal φTX controls the timing of the start and end of exposure. In frame (n), exposure starts at time T5 and ends at time T7.

[0126] At exposure start time T5, the transfer control signal φTX falls, thereby starting exposure. That is, before exposure start time T5, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is on, thereby discharging the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure starts in each pixel block 200 can also be changed.

[0127] Furthermore, at exposure end time T7, the transfer control signal φTX falls, thereby ending the exposure. That is, before exposure end time T7, the transfer control signal φTX turns on the transfer unit 301 while the reset control signal φRST is off, thereby transferring the charge accumulated in the photoelectric conversion unit 300 to the FD 303, and exposure ends at the falling edge of the transfer control signal φTX. Because the transfer control signal φTX is a locally controlled signal, the timing at which exposure ends can also be changed in each pixel block 200.

[0128] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. At time T6, the pixel 201 for which the selection control signal φSEL is set high outputs a pixel signal to the signal line 202.

[0129] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. The reset control signal φRST may be a globally controlled signal. Since the reset control signal φRST is always on except at the timing of readout, no charge is accumulated in the FD 303. On the other hand, by turning off the reset control signal φRST and turning on the transfer control signal φTX at the timing of readout, charge is transferred from the photoelectric conversion unit 300 to the FD 303. The reset control signal φRST has the same switching timing during readout, so it can be made common to the pulse of the selection control signal φSEL.

[0130] 1 to 15, exposure is performed in units of pixel blocks 200 each consisting of a plurality of pixels 201, and pixel signals from the pixel blocks 200 are read out in units of control blocks 400A corresponding to the pixel blocks 200, converting analog signals into digital signals. Furthermore, the image sensor 100A reads out pixel signals in parallel for each pixel block 200 using the control blocks 400A provided for each pixel block 200. Therefore, the image sensor 100A can set the exposure time for each pixel block 200 according to the intensity of incident light, thereby expanding the dynamic range.

[0131] Next, the configuration of an image sensor 100B that performs exposure in units of pixel blocks 200, sequentially reads out pixel signals for each pixel row, and performs AD conversion for each pixel column will be described with reference to FIGS.

[0132] Fig. 16 is an exploded perspective view showing another example of an image sensor. The image sensor 100B includes a first semiconductor substrate 110, a second semiconductor substrate 120, and a third semiconductor substrate 130. As shown in Fig. 16, the first semiconductor substrate 110 is stacked on the second semiconductor substrate 120, and the second semiconductor substrate 120 is stacked on the third semiconductor substrate 130.

[0133] The first semiconductor substrate 110 has a pixel unit 101 and a connection region 1601. The pixel unit 101 outputs a pixel signal based on incident light. The connection region 1601 is arranged around the pixel unit 101. In the example of FIG. 16 , a pair of connection regions 1601 are arranged along two opposing sides of the first semiconductor substrate 110, in front of and behind the pixel unit 101.

[0134] The second semiconductor substrate 120 has a control circuit section 102, a peripheral circuit section 121, and a signal processing section 1602. The signal processing section 1602 may be arranged with its circuits separated between the first semiconductor substrate 110 and the second semiconductor substrate 120. In that case, the connection region 1601 is also included in the signal processing section 1602 and becomes part of the area of ​​the signal processing section 1602. This allows the circuits to be arranged efficiently, reducing the chip area.

[0135] The control circuit section 102 outputs a control signal to the pixel section 101 for controlling the driving of the pixel section 101. The control circuit section 102 is disposed on the second semiconductor substrate 120 at a position facing the pixel section 101.

[0136] The peripheral circuit section 121 controls the driving of the control circuit section 102. The peripheral circuit section 121 is arranged around the control circuit section 102 on the second semiconductor substrate 120. The peripheral circuit section 121 may also be electrically connected to the first semiconductor substrate 110 and control the driving of the pixel section 101. The peripheral circuit section 121 is arranged along two opposing sides of the second semiconductor substrate 120, but the arrangement of the peripheral circuit section 121 is not limited to this example.

[0137] The signal processing unit 1602 receives analog pixel signals output from the first semiconductor substrate 110. The signal processing unit 1602 performs signal processing on the pixel signals. For example, the signal processing unit 1602 converts the analog pixel signals into digital signals. The signal processing unit 1602 may perform other signal processing. Examples of other signal processing include noise removal processing such as analog or digital CDS (Correlated Double Sampling). The signal processing unit 1602 is arranged on the periphery, i.e., outside, of the control circuit unit 102. In the example of FIG. 16 , a pair of signal processing units 1602 are arranged along two opposing sides of the second semiconductor substrate 120, in front and behind the control circuit unit 102. The signal processing units 1602 may be circuits included in the peripheral circuit unit 121.

[0138] The third semiconductor substrate 130 has a data processing unit 103. The data processing unit 103 uses the digital data output from the second semiconductor substrate 120 to perform addition processing, thinning processing, and other image processing.

[0139] Fig. 17 is an explanatory diagram showing another example of the specific configuration of the control circuit unit 102. In Fig. 17, a control block 400B has a pixel control unit 401 (autonomous exposure processing unit 411, exposure control unit 412, and pixel driving unit 413), but does not have a signal processing unit 402.

[0140] Instead of providing one control block 400B for one pixel block 200, one control block 400B may be provided for N pixel blocks 200 (N is a natural number greater than or equal to 2). The N pixel blocks 200 corresponding to one pixel block are sometimes referred to as a pixel block group. For example, two pixel blocks 200 arranged side by side in the column direction may be treated as one pixel block group, and one control block 400B may be provided for each pixel block 200. In this case, the control block 400B may control the exposure time for each pixel block 200.

[0141] In other words, the control block 400B is electrically connected to at least one pixel block 200 and can be said to be the smallest unit of a circuit that controls exposure of the pixels 201 in the at least one pixel block 200.

[0142] 18 is an explanatory diagram showing the connection relationship between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The first semiconductor substrate 110 includes connection regions 1801 and 1601 that are provided around the pixel unit 101 and are electrically connected to the pixel unit 101. The second semiconductor substrate 120 includes connection regions 1802 and 1803 that are provided around the control circuit unit 102 and are electrically connected to the control circuit unit 102. Note that the global drive unit 600 may be arranged with its circuits separated between the first semiconductor substrate 110 and the second semiconductor substrate 120. This allows for efficient circuit arrangement and reduces the chip area.

[0143] A pair of connection regions 1801 are connected to a pair of connection regions 1802 located opposite each other. The connection regions 1801 and 1802 connected to each other input a control signal from the global driving unit 600 to the pixel unit 101 using a global control line.

[0144] The pair of connection regions 1601 are connected to a pair of connection regions 1803 located opposite each other. The mutually connected connection regions 1601 and 1803 input pixel signals from the pixel unit 101 to the corresponding ADC units 1820 and 1830 using a common signal line.

[0145] 19 is an explanatory diagram showing an example of signal transmission between the first semiconductor substrate 110 and the second semiconductor substrate 120 in the image sensor 100B. The global driver 600 outputs a reset control signal φRST, a selection control signal φSEL, and a transfer selection control signal φTXSEL. The global driver 600 is connected to a reset control line 1903 and a selection control line 1904 that output signals to each pixel block 200. The global driver 600 supplies the reset control signal φRST to the multiple pixel blocks 200 via the reset control line 1903 and the selection control signal φSEL via the selection control line 1904. The global driver 600 supplies the transfer selection control signal φTXSEL to the multiple control blocks 400B via a transfer selection control line 1905.

[0146] The transfer selection control signal φTXSEL is supplied from the global drive unit 600 to the control block 400B to control the exposure time for each pixel block 200. The control block 400B, to which the transfer selection control signal φTXSEL is supplied, outputs the transfer selection control signal φTXSEL to the corresponding pixel block 200. The pixel block 200 determines whether or not to input the transfer selection control signal φTXSEL to the pixel 201 as the transfer control signal φTX or the discharge control signal φPDRST. As a result, input of the transfer control signal φTX or the discharge control signal φPDRST to the pixel 201 is skipped.

[0147] For example, when the transfer control signal φTX determines the end time of exposure, the control block 400B extends the exposure time by skipping the transfer control signal φTX. Also, when the transfer control signal φTX determines the start time of exposure, the control block 400B can shorten the exposure time by skipping the transfer control signal φTX. In this way, the exposure time of the pixel block 200 can be adjusted by the transfer selection control signal φTXSEL. The same applies when the discharge control signal φPDRST determines the start or end time of exposure.

[0148] The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are wired globally, i.e., are provided in common to a plurality of pixel blocks 200. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 are wired so as to cross the pixel unit 101 in the row direction. The reset control line 1903, the selection control line 1904, and the transfer selection control line 1905 may also be wired so as to cross the pixel unit 101 in the column direction.

[0149] For example, the reset control line 1903 is connected to the gate terminal of the reset unit 304 of the pixel block 200 and supplies a reset control signal φRST. The selection control line 1904 is connected to the gate terminal of the selection unit 352 of the pixel block 200 and supplies a selection control signal φSEL. In addition, the transfer selection control line 1905 is connected to each of the multiple control blocks 400B and supplies a transfer selection control signal φTXSEL to the pixel control unit 401.

[0150] Although the global driving unit 600 outputs the transfer selection control signal φTXSEL from the second semiconductor substrate 120 to the first semiconductor substrate 110, the global driving unit 600 may output the transfer selection control signal φTXSEL to the control block 400B without supplying it to the first semiconductor substrate 110. In this case, the transfer selection control line 1905 is provided on the second semiconductor substrate 120.

[0151] On the other hand, a transfer control line 1901a and a discharge control line 1902a are connected to the pixel block 200a. The transfer control line 1901a is connected to the gate terminal of the transfer unit 301 provided in the pixel block 200a. The transfer control line 1901a supplies the transfer control signal φTX output from the control block 400Ba to the pixel block 200a. The discharge control line 1902a is connected to the gate terminal of the discharge unit 302 provided in the pixel block 200a. The discharge control line 1902a supplies the discharge control signal φPDRST output from the control block 400Ba to the pixel block 200a.

[0152] The transfer control line 1901b and the discharge control line 1902b are connected to the pixel block 200b. The transfer control line 1901b is connected to the gate terminal of the discharge of the transfer unit 301 provided in the pixel block 200b. The transfer control line 1901b supplies the transfer control signal φTX output from the control block 400Bb to the pixel block 200b. The discharge control line 1902b is connected to the gate terminal of the discharge unit 302 provided in the pixel block 200b. The discharge control line 1902b supplies the discharge control signal φPDRST output from the control block 400Bb to the pixel block 200b.

[0153] A plurality of bonding portions 610 are provided on the bonding surfaces where the first semiconductor substrate 110 and the second semiconductor substrate 120 are bonded to each other. The bonding portions 610 of the first semiconductor substrate 110 are aligned with the bonding portions 610 of the second semiconductor substrate 120. The opposing bonding portions 610 are bonded and electrically connected by, for example, applying pressure to the first semiconductor substrate 110 and the second semiconductor substrate 120. In this case, the bonding portions 610 of the global control lines may be located under the corresponding pixel blocks 200, or may be located in the connection regions 1801 and 1802. On the other hand, the bonding portions 610 of the local control lines are located under the corresponding pixel blocks 200 (and also on the control block 400B).

[0154] The image sensor 100B controls the exposure time for each pixel block 200 by changing the timing of at least one of the transfer unit 301 and the discharge unit 302 using a local control line. The image sensor 100B can control the exposure time with fewer control lines by combining local control lines and global control lines.

[0155] 20 is an explanatory diagram showing the connection relationship between the ADC unit and pixel blocks. As shown in FIG. 20, a common signal line 202 extending in the column direction is arranged for each column within a pixel block 200c. Furthermore, this signal line 202 is also common to a plurality of pixel blocks 200c and 200d arranged in the column direction. Therefore, in this example, one signal line 202 is connected to m×M pixels 201 arranged in a single column, and pixel signals from these pixels 201 are output.

[0156] An ADC 2000 is connected to each of the signal lines 202 on the side of the second semiconductor substrate 120 via a joint 610. A plurality of ADCs 2000 corresponding to the plurality of signal lines 202 constitute the ADC unit 1820.

[0157] 20 , the ADCs 2000 corresponding to the pixel blocks 200c and 200d in the odd-numbered columns are provided in the ADC unit 1820, and the ADCs 2000 corresponding to the pixel blocks 200e and 200f in the even-numbered columns are provided in the ADC unit 1830. However, the arrangement of the pixel blocks 200c etc. and the corresponding ADC units 1820 etc. is not limited to this.

[0158] With the above configuration, each ADC 2000 converts pixel signals output sequentially from the m×M pixels 201 in one connected column into digital signals and outputs the digital signals. In this case, the ADC units 1820 and 1830 as a whole convert pixel signals from the pixels 201 arranged in n×N columns in the row direction into digital signals in parallel. From this perspective, this digital conversion can also be considered a type of so-called column ADC. Note that, while a single-slope ADC is an example of an ADC, other digital conversion methods may also be used. Furthermore, the connection positions of each pixel 201 and the signal lines 202 are not limited to the configuration shown in FIG. 20 , and may alternatively be within each pixel block 200c, for example.

[0159] 21 is a timing chart showing the imaging operation in the pixel block 200 of the image sensor 100B. Driving of the pixel block 200 is controlled by the transfer control signal φTX, the discharge control signal φPDRST, the reset control signal φRST, and the selection control signal φSEL.

[0160] The discharge control signal φPDRST controls the timing at which exposure starts. The exposure start timing corresponds to the falling edge of the discharge control signal φPDRST (for example, time T1). That is, before the exposure start time T1, the discharge control signal φPDRST turns on the discharge unit 302 to discharge the charge accumulated in the photoelectric conversion unit 300, and exposure starts at the falling edge of the discharge control signal φPDRST. Because the discharge control signal φPDRST is controlled locally, the exposure time can be adjusted for each pixel block 200.

[0161] The transfer control signal φTX controls the timing to end exposure. At time T3, the transfer control signal φTX turns on the transfer unit 301, thereby transferring the charges accumulated in the photoelectric conversion unit 300 to the FD 303. The timing to end exposure corresponds to the falling edge of the transfer control signal φTX (for example, time T4).

[0162] The reset control signal φRST controls the timing of discharging the charge accumulated in the FD 303. At time T2, the reset control signal φRST turns on the reset unit 304, thereby discharging the charge in the FD 303. By discharging the charge in the FD 303 before the timing of the end of exposure, the influence of the charge remaining in the FD 303 when the charge is transferred from the photoelectric conversion unit 300 can be suppressed.

[0163] The selection control signal φSEL is a signal for selecting an arbitrary pixel 201. The selection control signal φSEL controls the on / off of the selection unit 352. At time T2, the selection control signal φSEL is set to high. At time T3, the pixel 201 for which the selection control signal φSEL is set to high outputs a pixel signal to the signal line 202 in response to the transfer control signal φTX being turned on. On the other hand, the pixel 201 for which the selection control signal φSEL is not set to high does not output a pixel signal.

[0164] The image sensor 100B can locally control the discharge control signal φPDRST to change the exposure start timing for each pixel block 200 and control the exposure time for each pixel block 200. The image sensor 100B can also locally control the transfer control signal φTX to control the exposure end timing for each pixel block 200. The image sensor 100B can also locally control both the transfer control signal φTX and the discharge control signal φPDRST to control both the exposure start timing and end timing for each pixel block 200.

[0165] The pixel signal of each pixel 201 corresponds to the amount of charge accumulated in the photoelectric conversion unit 300. Therefore, controlling the timing of exposure of the pixel 201 can be said to be controlling the timing of charge accumulation in the photoelectric conversion unit 300. More specifically, controlling the timing of exposure of the pixel 201 can be said to be controlling the timing and length of the charge accumulation time from discharge to transfer of the charge.

[0166] 22 is an explanatory diagram showing an example of exposure timing for each pixel block 200. For three pixel blocks 200 arranged in a row, the exposure time is controlled for each pixel block 200. Here, the image sensor 100B changes the amount of exposure by shifting the pixel reset time for each pixel block 200.

[0167] On the other hand, the timing of reading out pixel signals is in order starting from the top pixel block 200. That is, pixel signals are read out from the pixels 201 in "pixel block 1," then from the pixels 201 in "pixel block 2," and then from the pixels 201 in "pixel block 3."

[0168] 21, pixel signals are sequentially read out from the pixels 201 in the upper rows within each pixel block 200. Therefore, when viewed from the entire pixel unit 101, pixel signals are sequentially read out from the upper rows of the m×M pixels 201 in the same column that are connected to a common signal line 202. In other words, the global drive unit 600 sets the selection control signal φSEL to high for each row, from the first row to the m×Mth row, across the plurality of pixel blocks 200 arranged in a single column.

[0169] 20, for multiple pixel blocks 200 arranged in one row, a common selection control line 1904 is connected to the n×N pixels arranged in the same row. Therefore, pixel signals are read out in parallel from the n×N pixels 201 connected to the row in which the selection control signal φSEL is set high. This makes it possible to output pixel signals for one frame.

[0170] 20, these pixel signals are converted into digital form by the ADC units 1820 and 252. The digitally converted pixel signals are output to the subsequent image processing stage to form an image for one frame.

[0171] As described above, from the viewpoint that pixel signals are read out sequentially from the top row of the same column among a plurality of pixel blocks 200, the readout method of this embodiment can also be said to be a so-called rolling shutter method for the entire pixel unit 101. However, it should be noted that even in this case, different exposure times can be set for each pixel block 200.

[0172] As described above, the image sensor 100B shown in FIGS. 16 to 22 performs exposure in pixel block 200 units, sequentially reading out pixel signals for each pixel row and performing AD conversion for each pixel column. Specifically, the image sensor 100B reads pixel signals from the pixels 201 of the upper pixel block 200 among the pixel blocks 200 arranged in a single column, and then reads out pixel signals from the pixels 201 of the pixel block 200 below it. This smooths out image distortion caused by the readout order when capturing an image of a moving subject, thereby reducing the sense of incongruity felt by viewers. More specifically, when a moving subject is captured in parallel from multiple pixel blocks 200 arranged in a single column, multiple sawtooth-shaped steps corresponding to the pixel blocks 200 appear in the vertical direction of the image (i.e., corresponding to the pixel column direction), creating an incongruity for the viewer. In contrast, the image sensor 100B shown in FIGS. 16 to 22 does not display these steps in the image.

[0173] Furthermore, the image sensor 100B shown in FIGS. 16 to 22 does not include an ADC unit that converts analog signals to digital signals within the control block 400B, but instead has a signal processing unit 1602 located outside the control circuit unit 102. This allows the area of ​​the control block 400B to be reduced, thereby reducing the size of the pixel blocks 200 located at positions corresponding to the control block 400B. In other words, exposure control by the control block 400B can be performed in units of a small number of pixels. This allows for precise exposure time control within an image, making the boundaries of the pixel blocks 200 less noticeable on the image. Furthermore, since digital conversion is not performed directly below the pixels 201, the impact of noise on the pixels 201 due to heat generation can be suppressed.

[0174] The signal processing unit 1602 does not have to be provided in a plurality of separate regions, and may be provided in one region for the entire pixel portion 101 .

[0175] As described above, from the viewpoint that pixel signals are read out sequentially from the top row of the same column among the multiple pixel blocks 200, similar to the image sensor 100A, the readout method of the image sensor 100B can also be said to be a so-called rolling shutter method for the entire pixel unit 101. However, even in this case, similar to the image sensor 100A, different exposure times can be set for each pixel block 200. As a result, similar to the image sensor 100A, the image sensor 100B also smooths out image distortion caused by the readout order when capturing an image of a moving subject, thereby reducing the sense of incongruity felt by the viewer.

[0176] [Autonomous exposure processing unit 411] Next, a detailed description will be given of the autonomous exposure processing unit 411. In the following description, when there is no need to distinguish between the image sensor elements 100A and 100B, they will be referred to as image sensor element 100, and when there is no need to distinguish between the control blocks 400A and 400B, they will be referred to as control block 400.

[0177] 4 and 17, the autonomous exposure processing unit 411 is implemented in the control block 400. The autonomous exposure processing unit 411 can also be implemented in the peripheral circuit unit 121 instead of in the control block 400, or it can be implemented in both the control block 400 and the peripheral circuit unit 121. These three patterns will be explained below with reference to FIGS. 23 to 25.

[0178] 23 is a block diagram showing an example configuration of autonomous exposure control method 1. Autonomous exposure control method 1 is an example configuration in which an autonomous exposure processing unit 411 is implemented within a control block 400. Adding the autonomous exposure processing unit 411 within the control block 400 increases the circuit size of the control block 400, but this may increase the size of each pixel 201 in the pixel block 200, making it possible to increase the light receiving area.

[0179] 23 will be described using the control block 400A as an example (similar to FIG. 25). The control block 400A has a signal conversion unit 422, a signal output unit 423, an autonomous exposure processing unit 411, an exposure control unit 412, and a pixel driving unit 413. For ease of explanation, the signal input unit 421 is omitted. In the case of the control block 400B, the signal input unit 421, the signal conversion unit 422, and the signal output unit 423 are not included in the control block 400B, but are arranged on the second semiconductor substrate 120 as a signal processing unit 1602 (similar to FIG. 25).

[0180] The signal conversion unit 422 has n ADCs 500. Each of the n ADCs 500 converts analog pixel signals from the m pixels 201 connected in the column direction into digital signals. The ADC 500 is configured with a comparator 501 and a storage unit 502.

[0181] The column selection circuit 2301 is included in the signal output unit 423. The column selection circuit 2301 sequentially selects columns of the pixel block 200 each time a readout column selection signal is input from the outside. Each time a horizontal transfer clock is input from the outside, the column selection circuit 2301 outputs digital pixel signals from m pixels 201 in the selected column to the peripheral circuit unit 121 via the substitution unit 2340 and the horizontal transfer line 2300, and also outputs the signals to the autonomous exposure processing unit 411.

[0182] The autonomous exposure processing unit 411 calculates an exposure value that indicates the exposure time of the pixel block 200. Specifically, the autonomous exposure processing unit 411 has, for example, a pre-processing unit 2311, a controller 2312, and an exposure value calculation unit 2313.

[0183] The preprocessing unit 2311 acquires digital pixel signals for each pixel column of the pixel block 200 from the column selection circuit 2301. The preprocessing unit 2311 then calculates statistical values ​​(e.g., average, median, maximum, or minimum) of the acquired pixel signals. The preprocessing unit 2311 outputs the calculation results to the exposure value calculation unit 2313.

[0184] The controller 2312 inputs a reset signal to the pre-processing unit 2311, causing the pre-processing unit 2311 to reset the pre-processing. As a result, the pre-processing unit 2311 calculates statistical values ​​of pixel signals from the pixel block 200 each time it is reset, that is, for each frame.

[0185] The exposure value calculation unit 2313 determines the next exposure value based on the calculation result (statistical value of pixel signals) from the preprocessing unit 2311. Specifically, for example, the exposure value calculation unit 2313 determines the next exposure value based on the calculation result so as to avoid underexposure or overexposure. For example, the exposure value calculation unit 2313 holds a first threshold value and a second threshold value. The first threshold value is a threshold value for determining whether the calculation result will be underexposed. The second threshold value is a threshold value greater than the first threshold value and is a threshold value for determining whether the calculation result will be overexposed.

[0186] The exposure value calculation unit 2313 holds the exposure value of the previous frame. The exposure value calculation unit 2313 determines whether the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value. If the calculation result is equal to or greater than the first threshold value and equal to or less than the second threshold value, the exposure value calculation unit outputs an exposure value with the same exposure time as the previous frame to the latch circuit 2321 of the exposure control unit 412. If the calculation result is less than the first threshold value, the exposure value calculation unit 2313 outputs an exposure value with an exposure time one step longer than the previous frame to the latch circuit 2321 of the exposure control unit 412. If the calculation result is greater than the second threshold value, the exposure value calculation unit outputs an exposure value with an exposure time one step shorter than the previous frame to the latch circuit 2321 of the exposure control unit 412.

[0187] The exposure value calculation unit 2313 may also hold multiple thresholds. In this case, if the calculation result is equal to or greater than the first threshold and equal to or less than the second threshold, the exposure value calculation unit 2313 outputs an exposure value having the same exposure time as the previous frame to the latch circuit 2321 of the exposure control unit 412.

[0188] Furthermore, if the calculation result is less than the first threshold value, the exposure value calculation unit 2313 adjusts the degree of change in exposure time depending on the degree of underexposure, to +1 step, +2 steps, or +3 steps compared to the previous frame, and outputs the exposure value to the latch circuit 2321 of the exposure control unit 412. Furthermore, if the calculation result exceeds the second threshold value, the exposure value calculation unit 2313 adjusts the degree of change in exposure time depending on the degree of overexposure, to -1 step, -2 steps, or -3 steps compared to the previous frame, and outputs the exposure value to the latch circuit 2321 of the exposure control unit 412.

[0189] The exposure control unit 412 includes, for example, a latch circuit 2321, a shift register 2322, a pixel block control unit 503, and a level shift unit 504. The latch circuit 2321 holds the exposure value from the autonomous exposure processing unit. The latch circuit 2321 outputs the held exposure value to the pixel block control unit 503 and the shift register 2322 every time a latch pulse is input from the outside.

[0190] The shift register 2322 converts the exposure value from the latch circuit 2321 from parallel to serial, and outputs the serial signal exposure value to the data processing unit 103 and also to the substitution unit 2340 .

[0191] If the exposure time is calculated by an external system outside the image sensor 100 and the calculation result is fed back to the image sensor 100, it takes time for the result to be reflected in the exposure time of the image sensor 100, resulting in increased power consumption. In contrast, by providing an autonomous exposure processing unit 411 within the control block 400, it is possible to improve the speed at which the exposure time is reflected in the pixel block 200 and reduce power consumption.

[0192] The setting unit 2330 is provided outside the control circuit unit 102, for example, in the peripheral circuit unit 121 or the data processing unit 103. The setting unit 2330 sets, for each control block 400A, the embedding position of the exposure value to be embedded in the digital pixel signal of m rows and n columns output from the column selection circuit 2301 to the peripheral circuit unit 121. The embedding position of the exposure value by the setting unit 2330 will be described later with reference to FIGS.

[0193] The control block 400A also includes a replacement unit 2340. The replacement unit 2340 replaces a portion of first data related to pixel signals read out from the pixels 201 with second data related to the accumulation time calculated by an exposure value calculation unit 2313 that calculates the accumulation time for accumulating the electric charges converted by the photoelectric conversion unit 300.

[0194] Specifically, for example, the substitution unit 2340 receives the digital pixel signals of m rows and n columns from the column selection circuit 2301, the exposure values ​​from the shift register 2322, and the embedding positions of the exposure values ​​from the setting unit 2330. The substitution unit 2340 selects the embedding target pixel signals from the digital pixel signals of m rows and n columns based on the embedding positions of the exposure values ​​from the setting unit 2330, and replaces the values ​​of the selected embedding target pixel signals with the bit values ​​included in the exposure values. The substitution unit 2340 then outputs the digital pixel signals in which the exposure values ​​have been embedded to the peripheral circuit unit 121 via the horizontal transfer line 2300.

[0195] 23 has been described as a case in which one control block 400 controls the exposure of one pixel block 200, but when one control block 400 controls the exposure of multiple pixel blocks 200, the autonomous exposure processing unit 411 may sequentially select one pixel block 200 from the multiple pixel blocks 200 in synchronization with a reset signal and calculate an exposure value. A selector is provided on the output side of the exposure value calculation unit 2313, and the controller 2312 outputs a selection signal to the selector to select one pixel block 200 from the multiple pixel blocks 200.

[0196] Furthermore, in this case, the exposure control unit 412 has a latch circuit 2321 and a shift register 2322 for each pixel block 200. Each latch circuit 2321 is connected to a selector (not shown) in the autonomous exposure processing unit 411, and when an exposure value is input from the selector, the latch circuit 2321 outputs the held exposure value to the pixel block control unit 503 and the shift register 2322 each time a latch pulse is input. This makes it possible to achieve autonomous exposure even when one control block 400 controls the exposure of multiple pixel blocks 200.

[0197] 24 is a block diagram showing an example configuration of autonomous exposure control method 2. Autonomous exposure control method 2 is an example configuration in which an autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121. The autonomous exposure processing unit 411 is implemented in the peripheral circuit unit 121 rather than in the control block. This allows the circuit scale of the control block 400 to be smaller than in the case of FIG. 23 .

[0198] The peripheral circuit unit 121 is connected to the pixel unit 101 via a horizontal transfer unit 2410. The horizontal transfer unit 2410 is connected to each pixel block 200 arranged in the row direction (hereinafter referred to as a pixel block row), and transfers pixel signals for each pixel block row to the peripheral circuit unit 121. Because the pixel unit 101 is a collection of pixel blocks 200 with M rows and N columns, the horizontal transfer unit 2410 transfers pixel signals to the peripheral circuit unit 121 for each M pixel block rows.

[0199] The peripheral circuit unit 121 has row-direction autonomous exposure processor groups 2400-1 to 2400-M, one for each pixel block row (when no distinction is needed, these will be simply referred to as row-direction autonomous exposure processor groups 2400). Each row-direction autonomous exposure processor group 2400 has a data sampling unit 2411 and autonomous exposure processors 411 (pre-processing units 2311, controllers 2312, and exposure value calculation units 2313) for N, the number of columns of pixel blocks. In FIG. 24 , since N=4, four sets of pre-processing units 2311, controllers 2312, and exposure value calculation units 2313 are implemented.

[0200] The data sampling unit 2411 divides the pixel signal sequence of the pixel block row from the horizontal transfer unit 2410 into N equal parts and samples them. The data sampling unit 2411 outputs each of the sampled pixel signal sequences to the corresponding pre-processing unit 2311.

[0201] As described above, the pre-processing unit 2311 calculates statistical values ​​of pixel signals from the corresponding pixel block 200. Furthermore, since the peripheral circuit unit 121 can have a larger circuit scale than the control block 400, the pre-processing unit 2311 can perform other processes in addition to calculating statistical values ​​of pixel signals.

[0202] For example, the pre-processing unit 2311 has a memory that stores the pixel numbers of defective pixels in the corresponding pixel block 200 that were defective during manufacturing, and when the data sampling unit 2411 samples a pixel signal of that pixel number, the pre-processing unit 2311 does not use the sampled pixel signal in calculating the statistical value of that pixel signal. This makes it possible to increase the accuracy of the calculation of the statistical value of the pixel signal.

[0203] Furthermore, the pre-processing unit 2311 may acquire calculation results from other pre-processing units 2311 that are responsible for pixel blocks 200 adjacent to the corresponding pixel block 200, and calculate statistical values ​​of pixel signals from the corresponding pixel block 200 based on the calculation results acquired from the other pre-processing units 2311. This makes it possible to smooth out exposure differences between adjacent pixel blocks 200.

[0204] Furthermore, the exposure value calculation unit 2313 is set with a first threshold value and a second threshold value, but at least one of the first threshold value and the second threshold value may be changeable depending on the shooting mode of the imaging device in which the image sensor 100 is implemented, thereby enabling optimal exposure calculation depending on the shooting mode.

[0205] The peripheral circuit unit 121 also has a latch circuit 2321 and a shift register 2322 for each exposure value calculation unit 2313. The shift register 2322 performs parallel-to-serial conversion on the exposure value from the latch circuit 2321 and outputs the serial exposure signal to the data processing unit 103, and also outputs the exposure value to the exposure control unit 412 in the control block 400 corresponding to the pixel block 200.

[0206] The setting unit 2330 is provided outside the control circuit unit 102, for example, in the peripheral circuit unit 121 or the data processing unit 103. The setting unit 2330 sets, for each control block 400, the embedding position of the exposure value to be embedded in the digital pixel signal of m rows and n columns output from the column selection circuit 2301 to the peripheral circuit unit 121. The embedding position of the exposure value by the setting unit 2330 will be described later with reference to FIGS.

[0207] The substitution unit 2340 is disposed on the second semiconductor substrate 120 or the third semiconductor substrate 130. Specifically, the substitution unit 2340 inputs, for each control block 400, the digital pixel signals of m rows and n columns from the horizontal transfer unit 2410, the exposure values ​​from the shift register 2322, and the embedding positions of the exposure values ​​from the setting unit 2330. The substitution unit 2340 selects embedding target pixel signals from the digital pixel signals of m rows and n columns based on the embedding positions of the exposure values ​​from the setting unit 2330, and replaces the values ​​of the selected embedding target pixel signals with the bit values ​​included in the exposure values. The substitution unit 2340 then outputs the digital pixel signals in which the exposure values ​​have been embedded for each control block 400.

[0208] The configuration shown in Figure 24 allows the circuit scale of the control block 400 to be smaller than that of Figure 23, and the size of the corresponding pixel block 200 to be reduced. This increases the number of pixel blocks, enabling more precise autonomous exposure control. Furthermore, the exposure control unit 412 and pixel driving unit 413 may be implemented in the peripheral circuit unit 121. This allows the circuit scale of the control block 400 to be further reduced, and the size of the corresponding pixel block 200 to be reduced.

[0209] 25 is a block diagram showing an example configuration of autonomous exposure control method 3. Autonomous exposure control method 3 is an example configuration in which the autonomous exposure processing unit 411 is implemented both in the control block 400A and in the peripheral circuit unit 121. When performing automatic exposure control in the control block 400A, data transmission such as sending pixel signals from the control block 400A to the peripheral circuit unit 121 and sending exposure values ​​from the peripheral circuit unit 121 to the pixel block 200 is not necessary. Therefore, feedback to the corresponding pixel block 200 is faster than when performing automatic exposure control in the peripheral circuit unit 121.

[0210] On the other hand, because the area of ​​the control block 400A is restricted by the area of ​​the corresponding pixel block 200, the circuit scale of the autonomous exposure processing unit 411 can be made larger by implementing it in the peripheral circuit unit 121 rather than implementing it within the control block 400A. For this reason, implementing it in the peripheral circuit unit 121 makes it possible to implement more advanced functions for autonomous exposure control (for example, removal of pixel signals from defective pixels, control of exposure gaps between adjacent pixel blocks 200, and calculation of optimal exposure according to the shooting mode, as described in FIG. 24 ).

[0211] Therefore, in autonomous exposure control method 3, image sensor 100 performs autonomous exposure control depending on the situation, using peripheral circuitry 121 when performing high-performance calculations related to autonomous exposure control, or using control block 400A when performing high-speed feedback of exposure values. In Figure 25, as an example, in autonomous exposure control method 3, autonomous exposure control is performed by row-direction autonomous exposure processing units 2400 in peripheral circuitry 121, but image sensor 100 performs autonomous exposure control for each control block 400A when some kind of trigger is given to control circuitry 102.

[0212] For example, when a user selects high-performance calculations related to autonomous exposure control, the image sensor 100 executes autonomous exposure control in the peripheral circuit unit 121, and when a user selects high-speed execution of exposure value feedback, the image sensor 100 executes autonomous exposure control in the control block 400A. Furthermore, when the remaining battery charge falls below a predetermined level, the image sensor 100 may select and execute low-power processing between high-performance calculations related to autonomous exposure control and high-speed execution of exposure value feedback.

[0213] The row-direction autonomous exposure processing unit group 2400 mounted in the peripheral circuit unit 121 has the same configuration as that shown in FIG. 24, and is therefore omitted in FIG.

[0214] The column selection circuit 2301 outputs an n-bit digital pixel signal to n OR circuits 2501. The autonomous exposure processing unit 2500 in the control block 400A has, in addition to the controller 2312, n OR circuits 2501, an output data latch circuit 2502, and an n-bit AND circuit 2503.

[0215] When the n-bit signal is output from the output data latch circuit 2502 , the controller 2312 inputs a reset signal to the output data latch circuit 2502 .

[0216] The OR circuit 2501 is a logic circuit with two inputs and one output. One input of the OR circuit 2501 is connected to the column selection circuit, and the other input is connected to the output of the n-bit AND circuit 2503.

[0217] The n OR circuits 2501 are connected to the input of an output data latch circuit 2502. The output data latch circuit 2502 holds the n-bit signals from the n OR circuits 2501. When a horizontal transfer clock is input, the output data latch circuit 2502 outputs an n-bit signal to an n-bit AND circuit 2503. When a reset signal is input from the controller 2312, the output data latch circuit 2502 resets the n-bit signal it is holding, and outputs an n-bit signal in which at least one bit of the n bits is 0 to the n-bit AND circuit 2503.

[0218] The n-bit AND circuit 2503 is an AND circuit with n inputs and 1 output, and the output of the output data latch circuit 2502 is connected to the input of the n-bit AND circuit 2503. The output of the n-bit AND circuit 2503 is connected to the selector 2512 of the exposure control unit 412 and the input of each OR circuit 2501. If the output from the n-bit AND circuit 2503 is "0", this indicates that the pixel row that output the n-bit digital pixel signal is not saturated. If the output from the n-bit AND circuit 2503 is "1", this indicates that the pixel row that output the n-bit digital pixel signal is saturated. Hereinafter, the 1-bit signal whose output from the n-bit AND circuit 2503 is "1" will be referred to as a saturation detection signal.

[0219] If the value of the digital pixel signal from a pixel 201 in a pixel column is "1", this indicates that the pixel 201 is saturated. If all values ​​of the n-bit signal from the column selection circuit 2301 are "1", this indicates that the entire pixel column is saturated. In this case, all "1"s are input to one input of each OR circuit 2501, and therefore each OR circuit 2501 outputs a 1-bit signal with a value of "1" to the output data latch circuit 2502.

[0220] The output data latch circuit 2502 holds the n-bit signal whose value is all “1”, and outputs the held n-bit signal to the n-bit AND circuit 2503 when a horizontal transfer clock is input.

[0221] When an n-bit signal whose value is all "1" is input, the n-bit AND circuit 2503 outputs a saturation detection signal whose value is "1" to the selector 2512 and each OR circuit 2501. As a result, the output data latch circuit 2502 outputs an n-bit signal whose value is all "1" to the n-bit AND circuit 2503 until a reset signal is input. Therefore, the n-bit AND circuit 2503 outputs a saturation detection signal until a reset signal is input to the output data latch circuit 2502 from the controller 2312.

[0222] 24, the exposure control unit 412 has a shift register 2511 and a selector 2512. The shift register 2511 converts the exposure value from the peripheral circuit unit 121 from serial to parallel, and outputs the converted value to the level shift unit 504 and the selector 2512.

[0223] The selector 2512 receives the exposure value and the set exposure value from the shift register 2511. The selector 2512 selects either the exposure value from the shift register 2511 or the set exposure value based on the output signal from the n-bit AND circuit 2503, and outputs the selected exposure value to the latch circuit 2321. The set exposure value is an exposure value that corresponds to an exposure time that does not saturate the pixels 201, and is, for example, an exposure value that is set so as to minimize the exposure time.

[0224] The set exposure value is calculated and set, for example, by an external system outside the control block 400A. The set exposure value may be a fixed value or may be selected by the external system. The external system may be, for example, the peripheral circuit unit 121 in the image sensor 100, the data processing unit 103 on the third semiconductor substrate 130, or an image processing unit 3411 connected to the image sensor 100 in an imaging device having the image sensor 100.

[0225] Specifically, for example, when the output signal from the n-bit AND circuit 2503 is not a saturation detection signal, the selector 2512 selects the exposure value from the shift register 2511 and outputs it to the latch circuit 2321. On the other hand, when the output signal from the n-bit AND circuit 2503 is a saturation detection signal, the selector 2512 selects the set exposure value and outputs it to the latch circuit 2321.

[0226] In FIG. 25 , the setting unit 2330 is provided in the peripheral circuit unit 121. The control block 400A includes a substitution unit 2340. Specifically, the substitution unit 2340 receives, for example, the digital pixel signals of m rows and n columns from the column selection circuit 2301, the exposure value from the shift register 2322, and the embedding position of the exposure value from the setting unit 2330. The substitution unit 2340 selects a pixel signal to be embedded from the digital pixel signals of m rows and n columns based on the embedding position of the exposure value from the setting unit 2330 in the peripheral circuit unit 121, and replaces the value of the selected pixel signal to be embedded with the bit value included in the exposure value. The substitution unit 2340 then outputs the digital pixel signal with the embedded exposure value to the peripheral circuit unit 121 via the horizontal transfer line 2300.

[0227] In the control block 400A, the autonomous exposure processing unit 2500 and the exposure control unit 412 execute autonomous exposure control using the exposure value from the peripheral circuit unit 121 until saturation is detected in the control block 400A. When saturation is detected in the control block 400A, autonomous exposure control is executed using the exposure value set in the exposure control unit 412.

[0228] This makes it possible to select between a process in which a highly accurate exposure value is set for a non-saturated pixel column using the exposure value from the peripheral circuit section 121, and a process that enables simple and high-speed feedback in which a set exposure value is changed to a non-saturated state for a saturated pixel column.

[0229] Furthermore, the autonomous exposure processing unit 2500 in the control block 400 may be the autonomous exposure processing unit 411 shown in Fig. 23. In this case, for example, the autonomous exposure processing unit 411 in the peripheral circuit unit 121 and the autonomous exposure processing unit 411 in the control block 400 may be selectable by user setting.

[0230] For example, an imaging device incorporating the imaging element 100 may be able to select between the autonomous exposure processing unit 411 in the peripheral circuit unit 121 and the autonomous exposure processing unit 411 in the control block 400 based on the remaining battery power. In this case, the imaging device may select autonomous exposure control by the autonomous exposure processing unit 411 in the peripheral circuit unit 121 if the remaining battery power is equal to or greater than a predetermined value, and may select autonomous exposure control by the autonomous exposure processing unit 411 in the control block 400 if the remaining battery power is less than the predetermined value. Furthermore, a user may select the autonomous exposure processing unit 411 in the peripheral circuit unit 121 if they want to capture high-quality images, or select the autonomous exposure processing unit 411 in the control block 400 if they want to reduce power consumption.

[0231] <Example of Embedding Exposure Values ​​in Image Data> Next, an example of embedding exposure values ​​in image data will be described.

[0232] 26 is an explanatory diagram (part 1) showing image data output from the image sensor 100. The image data IMG output from the image sensor 100 is composed of M×N pieces of block image data IMG(1,1) to IMG(M,N). The image data IMG is output from the image sensor 100 in the order of block image data IMG(1,1) to IMG(M,N). The block image data IMG(i,j) (i is an integer satisfying 1≦i≦M, and j is an integer satisfying 1≦j≦N) is image data output from the pixel block 200 in the ith row and jth column of the image sensor 100 (hereinafter referred to as pixel block 200(i,j)), i.e., the digital pixel signal in the mth row and nth column from the column selection circuit 2301.

[0233] As shown in FIGS. 2 and 4, the pixel block 200(i,j) is a set of pixels 201 arranged in m rows and n columns, but in FIG. 26, the explanation will be given assuming m=n=16. The output data from one pixel 201 is pixel data 2600. The pixel data 2600 is multi-bit, for example, 12-bit data. The pixel X coordinates indicate the pixel data 2600 in numerical order of m×n (=256). A set of pixel data 2600 with pixel X coordinate values ​​of 1 to 16 is the array of pixel data 2600 with m=1. When using the pixel X coordinate value in the pixel data 2600, a branch number is used. For example, pixel data 2600 with pixel X coordinate values ​​of 1 to 256 is represented as pixel data 2600-1 to 2600-256.

[0234] FIG. 27 is an explanatory diagram (part 2) showing image data output from the image sensor 100. The image data IMG in FIG. 27 shows the arrangement of pixel data 2600 corresponding to each pixel block 200(i,j) of the image sensor 100. In pixel block 200(i,j), the arrangement of pixel data 2600 in the first row is the column of pixel data 2600-1 to 2600-16 in FIG. 26, and the arrangement of pixel data 2600 in the second row is the column of pixel data 2600-17 to 2600-32 in FIG. 26. Continuing in the same manner, the arrangement of pixel data 2600 in the 16th row, which is the final row, is the column of pixel data 2600-241 to 2600-256 in FIG. 26.

[0235] 28 is a diagram showing the correspondence relationship between exposure time and exposure value. In diagram 2800, a TV value 2801, an exposure time 2802, and an exposure value 2803 are associated with each other. The TV value 2801 is identification information that uniquely identifies a combination of the exposure time 2802 and the exposure value 2803. The exposure time 2802 is the time during which the image sensor 100 can photoelectrically convert light and accumulate electric charge. The exposure value 2803 is data that expresses the exposure time 2802 in 4 bits, and is calculated by the exposure value calculation unit 2313.

[0236] Next, an example will be described with reference to FIGS. 29 to 33 in which the setting unit 2330 sets an embedding position, and the replacement unit 2340 selects a pixel signal at the embedding position set by the setting unit 2330, and embeds an exposure value.

[0237] (Embedding Example 1) Fig. 29 is an explanatory diagram showing Example 1 of embedding an exposure value 2803 into block image data IMG(i,j). The pixel data group 2900 to be embedded is a collection of pixel data 2600-1 to 2600-4 into which the exposure value 2803 is embedded. The replacement unit 2340 embeds the exposure value 2803 into a total of four least significant bits of each of the pixel data 2600-1 to 2600-4. The pixel data 2600-1 to 2600-4 are output in the block image data IMG(i,j) before the subsequent pixel data 2600-5 to 2600-256. Therefore, the output destination of the block image data IMG(i, j) (for example, the peripheral circuit unit 121, the data processing unit 103, or the image processing unit 3411 outside the image sensor 100 described later) can read out the exposure value 2803 more quickly than if the exposure value 2803 were embedded in the subsequent pixel data 2600-5 to 2600-256.

[0238] The pixel data 2600-1 to 2600-4, in which the lowest bit was used to embed the exposure value 2803, essentially amounts to 11 bits. However, since only the lowest bit of data is lost, the adverse effects are less likely to be noticeable as it is hidden by noise components. Furthermore, the number of pixel data in which the exposure value 2803 is embedded is only four pixel data in the block image data IMG(i,j), so the adverse effects are also less likely to be noticeable and are at a level that is difficult to see.

[0239] At the output destination of the block image data IMG(i, j), the exposure value 2803 is read from the least significant bit of each of the pixel data 2600-1, 2600-2, 2600-3, and 2600-4, and then the value of each least significant bit is set to 0. As a result, the pixel data 2600-1, 2600-2, 2600-3, and 2600-4 effectively become 11 bits.

[0240] 30 is an explanatory diagram showing example 2-1 of embedding the exposure value 2803 into block image data IMG(i,j). The pixel data group 3000 to be embedded is a collection of pixel data 2600-1, 2600-3, 2600-5, and 2600-7 into which the exposure value 2803 is embedded. The replacement unit 2340 embeds the exposure value 2803 in a total of four least significant bits of each of the pixel data 2600-1, 2600-3, 2600-5, and 2600-7.

[0241] 29, the exposure value 2803 is embedded in the four least significant bits of each of the consecutively arranged pixel data 2600-1 to 2600-4, but in Fig. 30, the exposure value 2803 is embedded in the discretely arranged pixel data 2600-1, 2600-3, 2600-5, and 2600-7. The image data 2600 into which the exposure value 2803 is embedded is not limited to the pixel data 2600-1, 2600-3, 2600-5, and 2600-7, as long as it is not consecutively arranged. Also, although the discrete arrangement interval of the image data 2600 into which the exposure value 2803 is embedded is set to one pixel data, it may be two or more pixel data.

[0242] At the output destination of the block image data IMG(i, j), the exposure value 2803 is read from the least significant bit of each of the pixel data 2600-1, 2600-3, 2600-5, and 2600-7, and then the value of each least significant bit is set to 0. As a result, the pixel data 2600-1, 2600-3, 2600-5, and 2600-7 effectively become 11 bits.

[0243] FIG. 31 is an explanatory diagram showing example 2-2 of embedding an exposure value 2803 into block image data IMG(i,j). FIG. 31 shows an example in which the image data 2600 into which the exposure value 2803 is embedded is discretely spaced at intervals of three pixels. Specifically, in FIG. 31, the embedding target pixel data group 3100 is a collection of pixel data 2600-1, 2600-5, 2600-9, and 2600-13 into which the exposure value 2803 is embedded. The replacement unit 2340 embeds the exposure value 2803 into a total of four least significant bits of each of the pixel data 2600-1, 2600-5, 2600-9, and 2600-13.

[0244] At the output destination of the block image data IMG(i,j), the exposure value 2803 is read from the least significant bit of each of the pixel data 2600-1, 2600-5, 2600-7, and 2600-13, and then the value of each least significant bit is set to 0. As a result, the pixel data 2600-1, 2600-5, 2600-7, and 2600-13 effectively become 11 bits.

[0245] (Embedding Example 3) FIG. 32 is an explanatory diagram showing Example 3 of embedding the exposure value 2803 into the block image data IMG(i,j). FIG. 32 shows an example in which the exposure value 2803 is embedded in the image data group 3200 located inside the edge of the block image data IMG(i,j), rather than in the pixel data groups 2900, 3000, and 3100 at the edges of the block image data IMG(i,j) as shown in FIGS. 29 to 31. That is, while the pixel data groups 2900, 3000, and 3100 in FIGS. 29 to 31 were one-dimensional arrays of pixel data 2600, in the image data group 3200 in FIG. 32, the image data 2600 into which the exposure value 2803 is embedded is dispersed two-dimensionally. Therefore, the adverse effects of embedding the data are even less than in Embedding Example 1, and the image is even less visible.

[0246] Specifically, for example, the embedding target pixel data group 3200 is a collection of pixel data 2600-68, 2600-76, 2600-192, and 2600-200 into which the exposure value 2803 is embedded. The replacement unit 2340 embeds the exposure value 2803 in a total of four least significant bits of each of the pixel data 2600-68, 2600-76, 2600-192, and 2600-200.

[0247] At the output destination of the block image data IMG(i,j), an exposure value 2803 is read from the least significant bit of each of the pixel data 2600-68, 2600-76, 2600-192, and 2600-200, and then the value of each of the least significant bits is set to 0. As a result, the pixel data 2600-68, 2600-76, 2600-192, and 2600-200 effectively become 11 bits.

[0248] Although the embedding examples 1 to 3 in FIGS. 29 to 32 are explained using a case where the data to be embedded is 4 bits, the present invention is not limited to this and it is also possible to embed more bits.

[0249] (Embedding Example 4) Fig. 33 is an explanatory diagram showing Example 4 of embedding the exposure value 2803 into block image data IMG(i, j). In Figs. 29 to 32, the 4-bit exposure value 2803 is distributed to the least significant bits of four pixel data 2600, but Fig. 33 shows an example in which the 4-bit exposure value 2803 is aggregated into the least significant four bits of one pixel data 2600. In Fig. 33, as an example, the replacement unit 2340 embeds the exposure value 2803 into the least significant four bits of pixel data 2600-35.

[0250] This pixel data 2600-35 is essentially 8 bits, which raises concerns about its impact on image quality. Therefore, the output destination of the pixel data 2600-35 may read out the exposure value 2803 and then treat the pixel data 2600-35 as a defective pixel. Therefore, the output destination of the pixel data 2600-35 may discard the pixel data 2600-35 and interpolate it from the surrounding pixel data. Note that when treating the pixel data 2600-35 as defective pixel data, the embedded exposure value 2803 is not limited to 4 bits, and all 12 bits may be used as the exposure value 2803.

[0251] To enable the output destination of the block image data IMG(i,j) to perform interpolation processing within the block image data IMG(i,j), the pixel data 2600 into which the exposure value 2803 is embedded is positioned inside the edges of the block image data IMG(i,j). For example, when the block image data IMG(i,j) is output from a pixel block 200(i,j) in a Bayer array, the pixel data 2600 into which the exposure value 2803 is embedded needs to be pixel data such that pixel data of the same color that is two pixel data away from the pixel data 2600 on the left, right, above, or below it exists in the block image data IMG(i,j).

[0252] In the case of pixel data 2600-35, four pieces of image data that are two pixels apart above, below, left, and right exist in the block image data IMG(i,j), so the above condition is met.

[0253] As shown in the above-described Embedding Examples 1 to 4, the exposure value 2803 is embedded at the same embedding position in each of the block image data IMG(i,j) output in the time direction. However, the setting unit 2330 may set different embedding positions in each of the block image data IMG(i,j) output in the time direction.

[0254] Specifically, for example, the setting unit 2330 includes a pseudo-random number generating circuit. The pseudo-random number generating circuit generates a pseudo-random number each time block image data IMG(i,j) is output, and adds the pseudo-random number to the embedding position (at least one of the X-coordinate value and the Y-coordinate value). The replacing unit 2340 embeds the exposure value 2803 in the block image data IMG(i,j) at the embedding position after the addition of the pseudo-random number.

[0255] In this way, the embedding position of the exposure value 2803 in the spatial direction within the block image data IMG(i,j) differs between block image data IMG(i,j) in the time direction, so that it is possible to distribute the influence of the exposure value 2803 at the same embedding position. Note that, although a pseudo-random number generating circuit is used in the above explanation, a counter that increments by a predetermined value may also be used.

[0256] 34 is a block diagram showing an example of the configuration of an image capturing apparatus 3400 according to an embodiment. The image capturing apparatus 3400 includes the image sensor 100, a system control unit 3401, a drive unit 3402, a photometry unit 3403, a work memory 3404, a recording unit 3405, a display unit 3406, an operation unit 3408, a drive unit 3414, and a photographing lens 3420.

[0257] The photographing lens 3420 guides the subject light beam incident along the optical axis OA to the image sensor 100. The photographing lens 3420 is composed of a group of multiple optical lenses, and forms an image of the subject light beam from the scene near its focal plane. The photographing lens 3420 may be an interchangeable lens that can be attached to and detached from the image capturing device 3400. Note that in FIG. 34 , the photographing lens 3420 is represented by a single virtual lens placed near the pupil.

[0258] The driving unit 3414 drives the photographing lens 3420. For example, the driving unit 3414 changes the focus position by moving the optical lens group of the photographing lens 3420. The driving unit 3414 may also drive an iris diaphragm in the photographing lens 3420 to control the amount of subject light entering the image sensor 100.

[0259] The drive unit 3402 has a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 3401. The operation unit 3408 also receives instructions from the photographer using a release button or the like.

[0260] The image sensor 100 passes pixel signals to an image processing unit 3411 in the system control unit 3401. The image processing unit 3411 generates image data by performing various image processes using the work memory 3404 as a workspace. For example, when generating image data in JPEG file format, a color video signal is generated from a signal obtained using the Bayer array, and then compression processing is performed. The generated image data is recorded in a recording unit 3405 and converted into a display signal, which is displayed on a display unit 3406 for a preset time.

[0261] The photometry unit 3403 detects the luminance distribution of a scene prior to a series of shooting sequences for generating image data. The photometry unit 3403 includes, for example, an AE sensor with approximately one million pixels. The calculation unit 3412 of the system control unit 3401 receives the output of the photometry unit 3403 and calculates the luminance of each region of the scene.

[0262] The calculation unit 3412 determines the shutter speed, aperture value, and ISO sensitivity in accordance with the calculated luminance distribution. The image sensor 100 may also serve as the photometry unit 3403. The calculation unit 3412 also executes various calculations for operating the image capture device 3400. Part or all of the drive unit 3402 may be mounted on the image sensor 100. Part of the system control unit 3401 may be mounted on the image sensor 100.

[0263] As described above, the image sensor 100 does not receive the exposure value 2803 for the pixel block 200 from outside the image sensor 100, but calculates it in the control block 400 corresponding to the pixel block 200 within the image sensor 100. In order to perform image processing outside the image sensor 100, the image sensor 100 needs to output the exposure value 2803 calculated by each control block 400 in addition to the block image data IMG(i, j) output for each pixel block 200.

[0264] For this reason, the image sensor 100 does not set the exposure value 2803 in the header or footer of the block image data IMG(i,j), but embeds the exposure value 2803 in the block image data IMG(i,j) itself.

[0265] This eliminates the need to set a header or footer in the block image data IMG(i,j) in order to set the exposure value 2803. In other words, it is sufficient for at least the output circuit unit (not shown) connected to each data output line to output the block image data IMG(i,j), and the circuit that rearranges the data, adds headers and footers, and transmits the data serially from the data output line can be used as is.

[0266] Furthermore, even if a header or footer is required, the exposure value 2803 is not set, so that an increase in the size of the header or footer can be suppressed.

[0267] Furthermore, the image processing unit 3411 outside the image sensor 100 can perform image processing using the block image data IMG(i,j) in which the exposure value 2803 is embedded, as is, and does not need to acquire the exposure value 2803 from the header or footer of the block image data IMG(i,j). In other words, by acquiring in advance the embedding position of the exposure value 2803 set by the setting unit 2330, the image processing unit 3411 can read the exposure value 2803 from the block image data IMG(i,j) and perform image processing.

[0268] Furthermore, the image processing unit 3411 executes, for example, the following process: In the block image data IMG(i, j), the exposure value 2803 is read from the pixel data 2600 into which the exposure value 2803 is embedded. Then, the image processing unit 3411 sets the value of the least significant bit of the pixel data 2600 from which the exposure value 2803 has been read to 0 (in the case of embedding examples 1 to 3). Alternatively, the image processing unit 3411 treats the pixel data 2600 as defective pixel data and fills it in by interpolating from surrounding pixel data.

[0269] At this point, because the exposure time differs for each pixel block 200, steps are visible at the boundaries of the pixel blocks 200. Therefore, the image processing unit 3411 applies a digital gain in accordance with the read exposure value 2803. With the reference exposure time being a digital gain of 1, a digital gain inversely proportional to the exposure time is applied, such that a large digital gain is applied to a pixel block 200 with a short exposure time and a small digital gain is applied to a pixel block 200 with a long exposure time.

[0270] Alternatively, there may be cases where no image is output, such as T12 to T18 in area 5 in Fig. 12. In such cases, the image processing unit 3411 discards the block image data IMG(i,j) from that pixel block 200 as invalid data, and outputs only the valid block image data IMG(i,j) of T11 and T19.

[0271] Furthermore, the system control unit 3401 may also have a pseudo-random number circuit similar to that in the image sensor 100. In this case, the pseudo-random number circuit in the image sensor 100 and the pseudo-random number circuit in the system control unit 3401 may be operated at the same time. As a result, each pseudo-random number circuit outputs the exact same pseudo-random number, and therefore there is no need for the image sensor 100 to output information such as the coordinate position in the block image data IMG(i,j) at which the exposure value 2803 should be embedded. In this way, the system control unit 3401 automatically reads out the exposure value 2803, corrects the block image data IMG(i,j), and corrects block gaps using digital gain. The corrected block image data IMG(i,j) can be used for recording or image display.

[0272] The present invention is not limited to the above-described contents, and may be implemented by any combination thereof. Furthermore, other embodiments conceivable within the scope of the technical concept of the present invention are also included in the scope of the present invention.

[0273] 100, 100A, 100B Image sensor, 101 Pixel unit, 102 Control circuit unit, 103 Data processing unit, 110 First semiconductor substrate, 120 Second semiconductor substrate, 121 Peripheral circuit unit, 130 Third semiconductor substrate, 200 Pixel block, 201 Pixel, 202 Signal line, 210 Pixel group, 300 Photoelectric conversion unit, 301 Transfer unit, 302 Discharge unit, 304 Reset unit, 305 Pixel output unit, 306 Load current source, 310 Readout unit, 351 Amplification unit, 352 Selection unit, 400, 400A, 400B Control block, 401 Pixel control unit, 402 Signal transfer unit, 411 Autonomous exposure processing unit, 412 Exposure control unit, 413 Pixel drive unit, 421 Signal input unit, 422 Signal processing unit, 423 Signal output unit, 2330 setting unit, 2340 replacement unit, IMG image data, IMG(i, j) block image data, 2803 exposure value

Claims

1. An imaging element comprising: a pixel section in which a plurality of pixels are arranged, each including a photoelectric conversion section that converts light into an electric charge; an exposure processing section that calculates an accumulation time for accumulating the electric charge converted by the photoelectric conversion section; and a replacement section that replaces a portion of first data relating to a signal read from the pixel with second data relating to the accumulation time calculated by the exposure processing section.

2. An imaging device according to claim 1, wherein the replacement section replaces a part of the first data of a first pixel among the plurality of pixels with the second data.

3. An imaging device according to claim 2, wherein a plurality of the first pixels are arranged in the pixel section.

4. An imaging element according to claim 3, wherein the pixel section is arranged such that pixel blocks each having at least one of the first pixels are aligned in a first direction and a second direction intersecting the first direction, and the replacement section replaces a portion of the first data of the first pixel in the pixel block with the second data.

5. An imaging device according to claim 4, wherein the pixel block includes a plurality of the first pixels.

6. An imaging device according to claim 5, wherein the first pixels are arranged side by side in the first direction or the second direction in the pixel block.

7. An imaging device according to claim 6, wherein the first pixels are arranged adjacent to each other in the first direction or the second direction in the pixel block.

8. An imaging device according to claim 4, wherein the pixel section is arranged on a first semiconductor substrate, and the exposure processing section is arranged on a second semiconductor substrate connected to the first semiconductor substrate.

9. An image pickup device according to claim 8, wherein the exposure processing section is disposed in a control circuit section at a position facing the pixel section on the second semiconductor substrate.

10. An imaging device according to claim 9, wherein the control circuit section has a plurality of the exposure processing sections.

11. An imaging element according to claim 10, wherein the control circuit section has control blocks each having the exposure processing section arranged side by side in the first direction and the second direction, and the exposure processing section calculates the accumulation time of the photoelectric conversion section included in the pixel of the corresponding pixel block.

12. An imaging device according to claim 11, wherein each of the control blocks has the replacement section, and the replacement section replaces a portion of the first data of the first pixel of the corresponding pixel block with the second data.

13. An imaging element according to claim 12, comprising an exposure control section, wherein the control block controls the accumulation time of the electric charges converted by the photoelectric conversion section of the pixel of the corresponding pixel block based on the calculation result of the exposure processing section.

14. An imaging device according to claim 13, wherein the control block has a pixel driving section for outputting a control signal generated by the exposure control section to the pixels.

15. An imaging device according to claim 14, wherein the control block has a level shift section that adjusts the voltage level of the control signal generated by the exposure control section, and the pixel driving section outputs the control signal, the voltage level of which has been adjusted by the level shift section, to the pixel.

16. An imaging device according to claim 15, wherein the pixel has a transfer section that transfers the electric charge of the photoelectric conversion section, and the pixel driving section outputs a transfer control signal for controlling the transfer section.

17. An imaging device according to claim 16, wherein the pixel has a discharge section that discharges electric charges from the photoelectric conversion section, and the pixel driving section outputs a discharge control signal for controlling the discharge section.

18. An imaging device according to claim 15, wherein the pixel has a discharge section that discharges electric charges from the photoelectric conversion section, and the pixel driving section outputs a discharge control signal for controlling the discharge section.

19. An imaging device according to claim 12, wherein the control block has a signal processing unit that performs signal processing on the signals read out from the pixels of the corresponding pixel block.

20. An imaging device according to claim 19, wherein the signal processing section has a conversion section that converts the signal into a digital signal.

21. An imaging device according to claim 20, wherein the replacement section replaces the lower bits of the first data with the second data.

22. An imaging element according to claim 8, wherein the second semiconductor substrate has a control circuit section disposed in a position facing the pixel section and a peripheral circuit section disposed outside the control circuit section, and the exposure processing section is disposed in the peripheral circuit section.

23. An image pickup device according to claim 22, wherein the peripheral circuit section has a plurality of the exposure processing sections.

24. An image pickup device according to claim 23, wherein the exposure processing unit calculates the accumulation time of the photoelectric conversion unit included in the pixel of the corresponding pixel block.

25. An imaging device according to claim 24, wherein the peripheral circuit section has the substitution section, and the substitution section replaces a portion of the first data of the first pixel in the corresponding pixel block with the second data.

26. An imaging element according to claim 25, wherein the control circuit section has a plurality of control blocks arranged in the first direction and the second direction, and each of the control blocks has an exposure control section that controls the accumulation time of the electric charges converted by the photoelectric conversion section of the pixel of the corresponding pixel block based on the calculation result of the exposure processing section.

27. An imaging device according to claim 26, wherein the control block has a pixel driving section for outputting a control signal generated by the exposure control section to the pixel of the corresponding pixel block.

28. An imaging element according to claim 27, wherein the control block has a level shift section that adjusts the voltage level of the control signal generated by the exposure control section, and the pixel driving section outputs the control signal, the voltage level of which has been adjusted by the level shift section, to the pixel.

29. An imaging device according to claim 28, wherein the pixel has a transfer section that transfers the electric charge of the photoelectric conversion section, and the pixel driving section outputs a transfer control signal for controlling the transfer section.

30. An imaging device according to claim 29, wherein the pixel has a discharge section that discharges electric charges from the photoelectric conversion section, and the pixel driving section outputs a discharge control signal for controlling the discharge section.

31. An imaging device according to claim 28, wherein the pixel has a discharge section that discharges electric charges from the photoelectric conversion section, and the pixel driving section outputs a discharge control signal for controlling the discharge section.

32. An imaging device according to claim 26, wherein the control block has a signal processing unit that performs signal processing on the signals read out from the pixels of the corresponding pixel block.

33. An imaging device according to claim 32, wherein the signal processing section has a conversion section that converts the signal into a digital signal.

34. An imaging device according to claim 33, wherein the replacement section replaces the lower bits of the first data with the second data.

35. An imaging device according to any one of claims 1 to 34.

Images