Shift register unit, gate driving circuit, display panel and driving method therefor

Abstract

The present disclosure relates to the technical field of display. Provided are a shift register unit, a gate driving circuit, a display panel and a driving method therefor. The shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit comprising a plurality of cascaded shift register units, and the display panel comprising a pixel driving circuit. The shift register unit comprises: a first output circuit and a second output circuit, the first output circuit being used for providing in a first driving state a gate driving signal to the pixel driving circuit and used for providing in a second driving state an invalid level signal to the pixel driving circuit, and the second output circuit being used for providing an input signal to a lower-level shift register unit. The display panel using the shift register unit can realize adjustment of the local refresh rate. (figure 2)

Description

Shift register unit, gate drive circuit, display panel and driving method thereof Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register unit, a gate driving circuit, a display panel and a driving method thereof. Background Art

[0002] In related technologies, in order to achieve better display effects, the refresh frequency of the display panel is high, and the display panel with a high refresh frequency consumes more energy.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0004] Summary of the Invention

[0005] According to one aspect of the present disclosure, a shift register unit is provided. The shift register unit is applied to a gate drive circuit in a display panel. The gate drive circuit includes a plurality of cascaded shift register units. The display panel includes a pixel drive circuit. The shift register unit includes:

[0006] a first output circuit, the first output circuit being configured to provide a gate driving signal to the pixel driving circuit in a first driving state, and being configured to provide an invalid level signal to the pixel driving circuit in a second driving state;

[0007] The second output circuit is electrically connected to the first output circuit, and the second output circuit is used to provide an input signal to the lower-stage shift register unit.

[0008] In an exemplary embodiment of the present disclosure, the first output circuit is connected to a first control node, a second control node, and a first output terminal. The first output circuit is configured to provide the gate driving signal to the first output terminal in response to at least signals of the first control node and the second control node. The first output terminal is configured to be connected to a pixel driving circuit.

[0009] The second output circuit is connected to the first control node, the second control node, and the second output end. The second output circuit is used to respond to at least the signals of the first control node and the second control node to provide the input signal to the second output end. The second output end is used to connect to the next stage shift register unit.

[0010] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0011] a first sub-output circuit connected to the second clock signal terminal, the first control node, and the first output terminal, the first sub-output circuit being configured to transmit the signal of the second clock signal terminal to the first output terminal in response to a signal of the first control node;

[0012] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0013] Wherein, the first clock signal terminal and the second clock signal terminal are used to output clock signals with the same timing in the first driving state of the first output circuit;

[0014] The second clock signal terminal is used to output an invalid level signal in the second driving state of the first output circuit.

[0015] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0016] a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a first node, the first sub-output circuit being configured to respond to a signal at the first enable signal terminal to transmit a signal at the first clock signal terminal to the first node, and to respond to a signal at the first control node to transmit a signal at the first node to the first output terminal;

[0017] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0018] The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

[0019] In an exemplary embodiment of the present disclosure, the first output circuit includes:

[0020] a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a second node, the first sub-output circuit being configured to transmit a signal from the first control node to the second node in response to a signal from the first enable signal terminal, and to transmit a signal from the first clock signal terminal to the first output terminal in response to a signal from the second node;

[0021] a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node;

[0022] The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

[0023] In an exemplary embodiment of the present disclosure, the first output circuit further includes:

[0024] a first control circuit connected to the first power supply terminal, the second enable signal terminal, and the second node, the first control circuit being configured to transmit the signal of the first power supply terminal to the second node in response to a signal of the second enable signal terminal;

[0025] The second enable signal terminal is used to output an invalid level in a first driving state of the first output circuit, and is used to output a valid level in a second driving state of the first output circuit.

[0026] In an exemplary embodiment of the present disclosure, the second sub-output circuit is further connected to a third clock signal terminal, and the second sub-output circuit is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power terminal to the first output terminal.

[0027] In an exemplary embodiment of the present disclosure, the second output circuit includes:

[0028] a third sub-output circuit connected to the first clock signal terminal, the first control node, and the second output terminal, the third sub-output circuit being configured to respond to a signal of the first control node to transmit a signal from the first clock signal terminal to the second output terminal;

[0029] The fourth sub-output circuit is connected to the first power supply terminal, the second output terminal, and the second control node. The fourth sub-output circuit is used to respond to the signal of the second control node to transmit the signal of the first power supply terminal to the second output terminal.

[0030] In an exemplary embodiment of the present disclosure, the fourth sub-output circuit is further connected to the third clock signal terminal, and the fourth sub-output circuit is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power supply terminal to the second output terminal.

[0031] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0032] an input circuit connected to an input signal terminal, a third control node, and a third clock signal terminal, the input circuit being configured to transmit an input signal from the input signal terminal to the third control node in response to a signal from the third clock signal terminal, wherein the third control node is connected to the first control node;

[0033] a second control circuit connected to the third control node, the first clock signal terminal, the second control node, and the first power terminal, the second control circuit being configured to respond to signals from the first clock signal terminal and the second control node to transmit the signal from the first power terminal to the third control node;

[0034] a third control circuit connected to the third control node, the first power supply terminal, and the second control node, the third control circuit being configured to respond to a signal from the third control node to transmit a signal from the first power supply terminal to the second control node;

[0035] A fourth control circuit is connected to the third control node, the first clock signal terminal, the second control node, the third node, and the first power supply terminal. The fourth control circuit is used to respond to the signal of the third control node to transmit the signal of the first power supply terminal to the third node, to respond to the signal of the first clock signal terminal to input a valid level signal to the third node, and to respond to the signal of the third node to input a valid level signal to the second control node.

[0036] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0037] The isolation circuit is connected to the second control node, the third control node, and the third clock signal terminal. The isolation circuit is used to respond to the signal of the third clock signal terminal to connect the second control node and the third control node.

[0038] In an exemplary embodiment of the present disclosure, the shift register unit further includes:

[0039] A total reset circuit is connected to the first control node, the third control node, the first output terminal, the second output terminal, the first power supply terminal, and the total reset signal terminal. The total reset circuit is used to respond to the signal of the total reset signal terminal to transmit the signal of the first power supply terminal to the first control node, the third control node, the first output terminal, and the second output terminal.

[0040] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0041] a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the first control node;

[0042] A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

[0043] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0044] a fifth transistor, having a first electrode connected to the first node, a second electrode connected to the first output terminal, and a gate connected to the first control node;

[0045] a fifteenth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first node, and a gate connected to the first enable signal terminal;

[0046] A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

[0047] In an exemplary embodiment of the present disclosure, the first sub-output circuit includes:

[0048] a fifth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the second node;

[0049] a sixteenth transistor, having a first electrode connected to the first control node, a second electrode connected to the second node, and a gate connected to the first enable signal terminal;

[0050] a first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the first output terminal;

[0051] The first control circuit includes:

[0052] The fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal.

[0053] In an exemplary embodiment of the present disclosure, the second sub-output circuit includes:

[0054] a fourth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the second control node;

[0055] a ninth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the third clock signal terminal;

[0056] A second capacitor has a first electrode connected to the second control node and a second electrode connected to the first power supply terminal.

[0057] In an exemplary embodiment of the present disclosure, the third sub-output circuit includes:

[0058] a twelfth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second output terminal, and a gate connected to the first control node;

[0059] a third capacitor, a first electrode of which is connected to the first control node, and a second electrode of which is connected to the second output terminal;

[0060] The fourth sub-output circuit includes:

[0061] a thirteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the second control node;

[0062] The fourteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the third clock signal terminal.

[0063] In an exemplary embodiment of the present disclosure, the input circuit includes:

[0064] a first transistor, having a first electrode connected to the input signal terminal, a second electrode connected to the third control node, and a gate connected to the third clock signal terminal;

[0065] The isolation circuit comprises:

[0066] an eighth transistor, having a first electrode connected to the third control node, a second electrode connected to the first control node, and a gate connected to the third clock signal terminal;

[0067] The second control circuit includes:

[0068] a sixth transistor, having a first electrode connected to the first power supply terminal and a gate connected to the second control node;

[0069] a seventh transistor, having a first electrode connected to the second electrode of the sixth transistor, a second electrode connected to the third control node, and a gate connected to the first clock signal terminal;

[0070] The third control circuit includes:

[0071] an eleventh transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second control node, and a gate connected to the third control node;

[0072] The fourth control circuit is configured to input a valid level signal to the third node using the first clock signal terminal in response to a signal from the first clock signal terminal, and to input a valid level signal to the second control node using the first clock signal terminal in response to a signal from the third node. The fourth control circuit includes:

[0073] a third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the third control node;

[0074] a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the third node, and a gate connected to the first clock signal terminal;

[0075] The tenth transistor has a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a gate connected to the third node.

[0076] In an exemplary embodiment of the present disclosure, the total reset circuit includes:

[0077] a seventeenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the general reset signal terminal;

[0078] an eighteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate connected to the general reset signal terminal;

[0079] A nineteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the general reset signal terminal;

[0080] The twentieth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the general reset signal terminal.

[0081] In an exemplary embodiment of the present disclosure, the timing of the input signal and the gate driving signal are the same or different.

[0082] In an exemplary embodiment of the present disclosure, the first output circuit is connected to a first output terminal, and the first output circuit is configured to provide the invalid level signal or the gate driving signal to the pixel driving circuit through the first output terminal.

[0083] In an exemplary embodiment of the present disclosure, the duty cycle of the effective level on the first clock signal terminal is greater than the duty cycle of the effective level on the second clock signal terminal.

[0084] According to one aspect of the present disclosure, a gate driving circuit is provided, wherein the gate driving circuit includes a plurality of the above-mentioned shift register units.

[0085] According to one aspect of the present disclosure, a display panel is provided, wherein the display panel includes the above-mentioned gate driving circuit.

[0086] According to one aspect of the present disclosure, a display panel driving method is provided, wherein the driving method is used to drive the above-mentioned display panel, wherein the display area of ​​the display panel includes a first display area and a second display area, and the driving method includes:

[0087] In the same time period, respectively controlling the number of frames in which the shift register units corresponding to the first display area and the second display area are in the second driving state;

[0088] The number of frames in which the shift register unit corresponding to the first display area is in the second driving state is greater than the number of frames in which the shift register unit corresponding to the second display area is in the second driving state, and the refresh frequency of the first display area is less than the refresh frequency of the second display area.

[0089] According to one aspect of the present disclosure, a display panel driving method is provided, wherein the driving method is used to drive the above-mentioned display panel, the display panel including a first display area, and the driving method includes:

[0090] In a first period, the number of frames for which the shift register unit corresponding to the first display area is controlled to be in a second driving state is n1;

[0091] In the second period, the number of frames during which the shift register unit connected to the first display area is controlled to be in the second driving state is n2, where n1 and n2 are positive integers greater than or equal to 1;

[0092] n1 is greater than n2, and the refresh frequency of the first display area in the first time period is less than the refresh frequency in the second time period.

[0093] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0094] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0095] FIG1 is a schematic structural diagram of an exemplary embodiment of a display panel disclosed herein;

[0096] FIG2 is a schematic structural diagram of an exemplary embodiment of a shift register unit disclosed herein;

[0097] FIG3 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0098] FIG4 is a timing diagram of each node in a driving method of a shift register unit disclosed in the present invention;

[0099] FIG5 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0100] FIG6 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0101] FIG7 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0102] FIG8 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0103] FIG9 is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure;

[0104] FIG10 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0105] FIG11 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0106] FIG12 is a schematic structural diagram of another exemplary embodiment of a shift register unit disclosed herein;

[0107] FIG13 is a schematic structural diagram of an exemplary embodiment of a gate driving circuit disclosed herein. DETAILED DESCRIPTION

[0108] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent like or similar structures, and thus their detailed description will be omitted.

[0109] The terms "a", "an", and "said" are used to indicate that there are one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that there may be additional elements / components / etc. in addition to the listed elements / components / etc.

[0110] As shown in Figure 1, it is a structural schematic diagram of an exemplary embodiment of the display panel of the present disclosure. The display panel may include a timing controller, a source driving circuit, a gate driving circuit and a pixel array. The timing controller is respectively connected to the source driving circuit and the gate driving circuit, and the source driving circuit is respectively connected to a plurality of data signal lines (Da1 to Dan). The gate driving circuit includes: a scanning driving circuit and a light-emitting driving circuit. The scanning driving circuit is respectively connected to a plurality of scanning signal lines (S1 to Sm), and the light-emitting driving circuit is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxi j, i and j may be natural numbers, at least one sub-pixel Pxi j may include a circuit unit and a light-emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit may be respectively connected to the scanning signal line, the light-emitting signal line and the data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the source driver circuit to the source driver circuit, may provide clock signals, scan start signals, etc. suitable for the specifications of the scan driver circuit to the scan driver circuit, and may provide clock signals, emission stop signals, etc. suitable for the specifications of the light-emitting driver circuit to the light-emitting driver circuit. The source driver circuit may use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines Da1, Da2, Da3, ..., and Dan. For example, the source driver circuit may use the clock signal to sample the grayscale values ​​and apply data voltages corresponding to the grayscale values ​​to data signal lines Da1 to Dan in units of pixel rows, where n may be a natural number. The scan driver circuit may generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver circuit may sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan drive circuit can be constructed in the form of a shift register and can generate a scan signal by sequentially transmitting a scan start signal provided in the form of an on-level pulse to the next stage circuit under the control of a clock signal, and m can be a natural number. The light-emitting drive circuit can generate an emission signal to be provided to the light-emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the light-emitting drive circuit can sequentially provide an emission signal with an off-level pulse to the light-emitting signal lines E1 to Eo. For example, the light-emitting drive circuit can be constructed in the form of a shift register and can generate an emission signal by sequentially transmitting an emission stop signal provided in the form of an off-level pulse to the next stage circuit under the control of a clock signal, and o can be a natural number.

[0111] FIG2 is a schematic diagram of the structure of an exemplary embodiment of a shift register unit according to the present disclosure. The shift register unit includes a first output circuit 11 and a second output circuit 12 electrically connected to each other. The first output circuit 11 is configured to provide a gate drive signal to a pixel drive circuit in a first drive state and to provide an inactive level signal to the pixel drive circuit in a second drive state. The second output circuit 12 is configured to provide an input signal to a subsequent shift register unit.

[0112] In this exemplary embodiment, the first output circuit and the second output circuit are designed independently. The second output circuit can normally provide input signals to the lower-level shift register unit, and the first output circuit can normally output gate drive signals when the pixel drive circuit needs to be refreshed, and output an invalid level signal when the pixel drive circuit does not need to be refreshed. This exemplary embodiment can adjust the refresh frequency of a local area of ​​the display panel, as well as adjust the refresh frequency of the same display area at different time periods. Specifically, when the refresh frequency required for a local area or part of the display screen is low, the display panel can reduce the power consumption of the display panel by reducing the refresh frequency of the local area or part of the display screen.

[0113] It should be noted that, in this exemplary embodiment, the gate drive signal includes an effective level period and an invalid level period, that is, the effective level and invalid level output by the shift register unit for a certain period of time (for example, in a frame) together constitute the gate drive signal. In this exemplary embodiment, the effective level signal is a signal that can drive the target circuit to turn on, and the invalid level signal is a signal that drives the target circuit to turn off. For example, when the target circuit is an N-type transistor, the effective level signal is a high level signal, and the invalid level signal is a low level signal. The second output circuit 12 is used to provide an input signal to the lower-level shift register unit, wherein the lower-level shift register unit can be an adjacent next-level shift register unit or an interval lower-level shift register unit. The first driving state is the driving state when the first output circuit normally provides the gate drive signal, and the second driving state is the driving state when the first output circuit provides an invalid level signal.

[0114] In this exemplary embodiment, the timing of the input signal and the gate drive signal can be the same or different. For example, when the pixel drive circuit does not need to be refreshed, the first output circuit outputs an invalid level signal (e.g., a low level), while the second output circuit 12 is used to provide an input signal (e.g., a high level) to the lower-level shift register unit.

[0115] As shown in Figure 3, a schematic diagram of the structure of another exemplary embodiment of the shift register unit of the present disclosure is shown. A first output circuit 11 is connected to a first control node PU1, a second control node PD, and a first output terminal OUT1. The first output circuit 11 is configured to respond at least to signals from the first control node PU1 and the second control node PD to provide a gate drive signal to the first output terminal OUT1. The first output terminal OUT1 is configured to connect to a pixel drive circuit. A second output circuit 12 is connected to the first control node PU1, the second control node PD, and a second output terminal OUT2. The second output circuit 12 is configured to respond at least to signals from the first control node PU1 and the second control node PD to provide an input signal to the second output terminal OUT2. The second output terminal OUT2 is configured to connect to the next-stage shift register unit.

[0116] As shown in FIG3 , the first output circuit 11 includes: a first sub-output circuit 111 and a second sub-output circuit 112. The first sub-output circuit 111 is connected to the second clock signal terminal CB2, the first control node PU1, and the first output terminal OUT1. The first sub-output circuit 111 is configured to respond to a signal at the first control node PU1 to transmit the signal at the second clock signal terminal CB2 to the first output terminal OUT1. The second sub-output circuit 112 is connected to the first power supply terminal VGL, the first output terminal OUT1, and the second control node PD. The second sub-output circuit 112 is configured to respond to a signal at the second control node PD to transmit the signal at the first power supply terminal VGL to the first output terminal OUT1. The first power supply terminal VGL is configured to provide an inactive level signal. In the first driving state of the first output circuit 11, the first clock signal terminal CB and the second clock signal terminal CB2 are configured to output clock signals of corresponding timings. In the first driving state, the timings of the first clock signal terminal CB and the second clock signal terminal CB2 may be the same or slightly different, and the timings of the valid levels at the first clock signal terminal CB and the second clock signal terminal CB2 at least partially overlap. The second clock signal terminal CB2 is used to output an inactive level signal in the second driving state of the first output circuit 11. When the first clock signal terminal CB and the second clock signal terminal CB2 output clock signals of corresponding timings, the first output circuit 11 is in the first driving state, and when the second clock signal terminal CB2 outputs an inactive level signal, the first output circuit 11 is in the second driving state.

[0117] As shown in FIG3 , the second sub-output circuit 112 is further connected to the third clock signal terminal CK. The second sub-output circuit 112 is further configured to respond to the signal of the third clock signal terminal CK to transmit the signal of the first power terminal VGL to the first output terminal OUT1 .

[0118] As shown in Figure 3, the second output circuit 12 includes: a third sub-output circuit 123 and a fourth sub-output circuit 124. The third sub-output circuit 123 is connected to the first clock signal terminal CB, the first control node PU1, and the second output terminal OUT2. The third sub-output circuit 123 is used to respond to the signal of the first control node PU1 to transmit the signal of the first clock signal terminal CB to the second output terminal OUT2; the fourth sub-output circuit 124 is connected to the first power supply terminal VGL, the second output terminal OUT2, and the second control node PD. The fourth sub-output circuit 124 is used to respond to the signal of the second control node PD to transmit the signal of the first power supply terminal VGL to the second output terminal OUT2.

[0119] As shown in FIG3 , the fourth sub-output circuit 124 is also connected to the third clock signal terminal CK. The fourth sub-output circuit 124 is further configured to respond to the signal of the third clock signal terminal CK to transmit the signal of the first power terminal VGL to the second output terminal OUT2 .

[0120] As shown in Figure 3, the shift register unit also includes: an input circuit 2, a second control circuit 3, a third control circuit 4, and a fourth control circuit 5. The input circuit 2 is connected to the input signal terminal IN, the third control node PU3, and the third clock signal terminal CK. The input circuit 2 is used to respond to the signal of the third clock signal terminal CK to transmit the input signal of the input signal terminal IN to the third control node PU3, wherein the third control node PU3 is connected to the first control node PU1; the second control circuit 3 is connected to the third control node PU3, the first clock signal terminal CB, the second control node PD, and the first power supply terminal VGL, and the second control circuit 3 is used to respond to the first clock signal terminal CB and the second control terminal The third control circuit 4 is connected to the third control node PU3, the first power terminal VGL, and the second control node PD, and is used to respond to the signal of the third control node PU3 to transmit the signal of the first power terminal VGL to the second control node PD. The fourth control circuit 5 is connected to the third control node PU3, the first clock signal terminal CB, the second control node PD, the third node N3, and the first power terminal VGL. The fourth control circuit 5 can be used to control the voltage of the third node N3 and the second control node PD in response to the signal of the first clock signal terminal CB and the third control node PU3. For example, the fourth control circuit 5 is used to respond to the signal of the third control node PU3 to transmit the signal of the first power terminal VGL to the third node N3, to respond to the signal of the first clock signal terminal CB to input a valid level signal to the third node N3, and to respond to the signal of the third node N3 to input a valid level signal to the second control node PD.

[0121] As shown in FIG3 , the shift register unit further includes an isolation circuit 6 connected to the second control node PD, the third control node PU3, and the third clock signal terminal CK. The isolation circuit 6 is configured to connect the second control node PD and the third control node PU3 in response to a signal from the third clock signal terminal CK. The isolation circuit 6 can reduce leakage current from the first control node PU1 to the input signal terminal IN.

[0122] As shown in Figure 3, the first sub-output circuit 111 includes: a fifth transistor T5 and a first capacitor C1. The first electrode of the fifth transistor T5 is connected to the second clock signal terminal CB2, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1; the first electrode of the first capacitor C1 is connected to the first control node PU1, and the second electrode is connected to the first output terminal OUT1.

[0123] As shown in Figure 3, the second sub-output circuit 112 includes: a fourth transistor T4, a ninth transistor T9, and a second capacitor C2. The first electrode of the fourth transistor T4 is connected to the first power supply terminal VGL, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the second control node PD; the first electrode of the ninth transistor T9 is connected to the first power supply terminal VGL, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the third clock signal terminal CK; the first electrode of the second capacitor C2 is connected to the second control node PD, and the second electrode is connected to the first power supply terminal VGL.

[0124] As shown in Figure 3, the third sub-output circuit 123 includes: a twelfth transistor T12 and a third capacitor C3, the first electrode of the twelfth transistor T12 is connected to the first clock signal terminal CB, the second electrode is connected to the second output terminal OUT2, and the gate is connected to the first control node PU1; the first electrode of the third capacitor C3 is connected to the first control node PU1, and the second electrode is connected to the second output terminal OUT2; the fourth sub-output circuit 124 includes: a thirteenth transistor T13 and a fourteenth transistor T14, the first electrode of the thirteenth transistor T13 is connected to the first power supply terminal VGL, the second electrode is connected to the second output terminal OUT2, and the gate is connected to the second control node PD; the first electrode of the fourteenth transistor T14 is connected to the first power supply terminal VGL, the second electrode is connected to the second output terminal OUT2, and the gate is connected to the third clock signal terminal CK.

[0125] As shown in FIG3 , the input circuit 2 includes: a first transistor T1, wherein the first electrode of the first transistor T1 is connected to the input signal terminal IN, the second electrode is connected to the third control node PU3, and the gate is connected to the third clock signal terminal CK; the isolation circuit includes: an eighth transistor T8, wherein the first electrode of the eighth transistor T8 is connected to the third control node PU3, the second electrode is connected to the first control node PU1, and the gate is connected to the third clock signal terminal CK; the second control circuit 3 includes: a sixth transistor T6 and a seventh transistor T7, wherein the first electrode of the sixth transistor T6 is connected to the first power supply terminal VGL, and the gate is connected to the second control node PD; the first electrode of the seventh transistor T7 is connected to the second electrode of the sixth transistor T6, the second electrode is connected to the third control node PU3, and the gate is connected to the first clock signal terminal CB; the third control circuit 4 includes: an eleventh transistor T11, wherein the first electrode of the eleventh transistor T11 is connected to the first power supply terminal VGL, the second electrode is connected to the third control node PU3, and the gate is connected to the first clock signal terminal CB The fourth control circuit 5 is configured to input a valid level signal to the third node N3 using the first clock signal terminal CB in response to the signal of the first clock signal terminal CB, and to input a valid level signal to the second control node PD using the first clock signal terminal CB in response to the signal of the third node N3. The fourth control circuit 5 includes: a third transistor T3, a second transistor T2, and a tenth transistor T10. The first electrode of the third transistor T3 is connected to the first power supply terminal VGL, the second electrode is connected to the third node N3, and the gate is connected to the third control node PU3; the first electrode of the second transistor T2 is connected to the first clock signal terminal CB, the second electrode is connected to the third node N3, and the gate is connected to the first clock signal terminal CB; the first electrode of the tenth transistor T10 is connected to the first clock signal terminal CB, the second electrode is connected to the second control node PD, and the gate is connected to the third node N3.

[0126] As shown in Figure 3, each transistor in the shift register unit is an N-type transistor, and accordingly, the first power supply terminal is a low-level power supply terminal. It should be understood that in other exemplary embodiments, the transistors in the shift register unit may also be P-type transistors.

[0127] As shown in Figure 4, it is a timing diagram of each node in a driving method of the shift register unit disclosed in the present invention. Among them, CB2 is the timing diagram of the second clock signal terminal, CK is the timing diagram of the third clock signal terminal, CB is the timing diagram of the first clock signal terminal, IN is the timing diagram of the input signal terminal, OUT1 is the timing diagram of the first output terminal, OUT2 is the timing diagram of the second output terminal, PD is the timing diagram of the second control node, PU3 is the timing diagram of the third control node, and PU1 is the timing diagram of the first control node.

[0128] The driving method of the shift register unit includes: a first stage t1, a second stage t2, a third stage t3, a fourth stage t4, and a fifth stage t5. Among them, in the first stage t1: the input signal terminal IN and the third clock signal terminal CK output high-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output low-level signals, the first transistor T1 is turned on, the high-level signal of the input signal terminal IN is transmitted to the third control node PU3, the eighth transistor T8 is turned on, the third control node PU3 inputs a high-level signal to the first control node PU1, the twelfth transistor T12 and the fifth transistor T5 are turned on, the first clock signal terminal CB inputs a low-level signal to the second output terminal OUT2, and the second clock signal terminal CB2 inputs a low-level signal to the first output terminal OUT1; at the same time, the third transistor T3 and the eleventh transistor T11 are turned on, the low-level signal of the first power supply terminal VGL is transmitted to the second control node PD and the third node N3, the tenth transistor T10, the thirteenth transistor T13, and the fourth transistor T4 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs a low-level signal to the first output terminal OUT1 and the second output terminal OUT2. That is, the first and second sub-output circuits 111 and 112 input a low level to the first output terminal OUT1, and the third and fourth sub-output circuits 123 and 124 input a low level to the second output terminal OUT2.

[0129] In the second phase t2, the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output high-level signals, the first control node PU1 and the third control node PU3 maintain a high level, the twelfth transistor T12 and the fifth transistor T5 are turned on, the first clock signal terminal CB inputs a high-level signal to the second output terminal OUT2, the second clock signal terminal CB2 inputs a high-level signal to the first output terminal OUT1, the third transistor T3 and the eleventh transistor T11 are turned on, the first power supply terminal VGL inputs a low-level signal to the second control node PD and the third node N3, the thirteenth transistor T13, the fourteenth transistor T14, the fourth transistor T4, and the ninth transistor T9 are all turned off. The first output terminal OUT1 and the second output terminal OUT2 output a high level.

[0130] In the third phase t3, the input signal terminal IN, the first clock signal terminal CB, and the second clock signal terminal CB2 output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2, respectively. The first output terminal OUT1 and the second output terminal OUT2 output low levels.

[0131] In the fourth stage t4: the input signal terminal IN and the third clock signal terminal CK output low-level signals, the first clock signal terminal CB and the second clock signal terminal CB2 output high-level signals, the first control node PU1 and the third control node PU3 maintain a low level, the third transistor T3 and the eleventh transistor T11 are turned off, the second transistor T2 is turned on, the first clock signal terminal CB inputs a high-level signal to the third node N3, the tenth transistor T10 is turned on, the first clock signal terminal CB inputs a high-level signal to the second control node PD, the thirteenth transistor T13 and the fourth transistor T4 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2 respectively.

[0132] In the fifth stage t5: the input signal terminal IN, the first clock signal terminal CB, and the second clock signal terminal CB2 output low-level signals, the third clock signal terminal CK outputs a high-level signal, the first transistor T1 and the eighth transistor T8 are turned on, the input signal terminal IN inputs a low-level signal to the third control node PU3 and the first control node PU1, the third transistor T3 and the eleventh transistor T11 are turned off, the fourteenth transistor T14 and the ninth transistor T9 are turned on, and the first power supply terminal VGL inputs low-level signals to the first output terminal OUT1 and the second output terminal OUT2, respectively. The first output terminal OUT1 and the second output terminal OUT2 output low levels.

[0133] Thereafter, the shift register unit may repeat the fourth stage and the fifth stage in sequence, and the first output terminal OUT1 and the second output terminal OUT2 maintain a low level.

[0134] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the second clock signal terminal CB2. As shown in Figure 5, it is a timing diagram of each node of the shift register unit in different display areas of the display panel disclosed in the present invention. Figure 5 shows the timing diagram of each signal end in a frame, wherein CB is the timing diagram of the first clock signal end, CB2 is the timing diagram of the second clock signal end, and CK is the timing diagram of the third clock signal end. This exemplary embodiment can use the second clock signal end CB2 to output a low-level signal in some frames, so that the shift register unit always outputs a low-level signal in the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in Figure 5, the refresh frequency of the first display area will be less than the refresh frequency of the second display area. The display area corresponding to the shift register unit refers to the display area where the pixel driving circuit connected to the shift register unit is located.

[0135] It should be understood that in other exemplary embodiments, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the second clock signal terminal CB2, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0136] In some embodiments, for example, as shown in FIG5 , the second clock signal terminal CB2 is continuously at a fixed potential (e.g., a low-level signal) during a first refresh time (e.g., corresponding to a first refresh frequency of the first display area), and the first clock signal terminal CB is continuously at a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during the first refresh time (e.g., corresponding to the first refresh frequency of the first display area). The second clock signal terminal CB2 is a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during a second refresh time (e.g., corresponding to a second refresh frequency of the second display area), and the first clock signal terminal CB is a periodic clock signal (e.g., a periodic clock signal with a duty cycle of approximately 50%) during the second refresh time.

[0137] FIG6 is a schematic diagram of the structure of another exemplary embodiment of a shift register unit according to the present disclosure. The difference between the shift register unit shown in FIG6 and the shift register unit shown in FIG3 lies in the different structure of the first sub-output circuit 111. As shown in FIG6, the first sub-output circuit 111 is connected to the first clock signal terminal CB, the first control node PU1, the first enable signal terminal EM1, the first output terminal OUT1, and the first node N1. The first sub-output circuit 111 is configured to respond to a signal from the first enable signal terminal EM1 to transmit the signal from the first clock signal terminal CB to the first node N1, and to respond to a signal from the first control node PU1 to transmit the signal from the first node N1 to the first output terminal OUT1. The first enable signal terminal EM1 is configured to output a valid level in the first driving state of the first output circuit 11, and to output an invalid level in the second driving state of the first output circuit 11. When the first enable signal terminal EM1 outputs a valid level, the first output circuit 11 is in the first driving state, and when the first enable signal terminal EM1 outputs an invalid level, the first output circuit 11 is in the second driving state.

[0138] As shown in Figure 6, the first sub-output circuit 111 includes: a fifth transistor T5, a fifteenth transistor T15, and a first capacitor C1. The first electrode of the fifth transistor T5 is connected to the first node N1, the second electrode is connected to the first output terminal OUT1, and the gate is connected to the first control node PU1; the first electrode of the fifteenth transistor T15 is connected to the first clock signal terminal CB, the second electrode is connected to the first node N1, and the gate is connected to the first enable signal terminal EM1; the first electrode of the first capacitor C1 is connected to the first control node PU1, and the second electrode is connected to the first output terminal OUT1.

[0139] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1. As shown in Figure 7, it is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure. Figure 7 shows the timing diagram of each signal terminal in a frame, wherein CB is the timing diagram of the first clock signal terminal, CK is the timing diagram of the third clock signal terminal, and EM1 is the timing diagram of the first enable signal terminal. This exemplary embodiment can use the first enable signal terminal EM1 to output a low-level signal in some frames, so that the shift register unit always outputs a low-level signal in the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in Figure 7, the refresh frequency of the first display area will be lower than the refresh frequency of the second display area.

[0140] It should be understood that in other exemplary embodiments, this exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0141] The driving method of the shift register unit shown in FIG6 may also include: a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 , and a fifth stage t5 .

[0142] As shown in Figure 8, a schematic diagram of the structure of another exemplary embodiment of the shift register unit of the present disclosure is shown. The difference between the shift register unit shown in Figure 8 and the shift register unit shown in Figure 3 lies in the different structure of the first output circuit 11. As shown in Figure 8, the first sub-output circuit 111 is connected to the first clock signal terminal CB, the first control node PU1, the first enable signal terminal EM1, the first output terminal OUT1, and the second node N2. The first sub-output circuit 111 is used to respond to the signal of the first enable signal terminal EM1 to transmit the signal of the first control node PU1 to the second node N2, and to respond to the signal of the second node N2 to transmit the signal of the first clock signal terminal CB to the first output terminal OUT1. The first enable signal terminal EM1 is used to output a valid level in the first driving state of the first output circuit 11, and to output an invalid level in the second driving state of the first output circuit 11. When the first enable signal terminal EM1 outputs a valid level, the first output circuit 11 is in the first driving state, and when the first enable signal terminal EM1 outputs an invalid level, the first output circuit 11 is in the second driving state.

[0143] As shown in FIG8 , the first sub-output circuit 111 includes a fifth transistor T5, a sixteenth transistor T16, and a first capacitor C1. The fifth transistor T5 has a first electrode connected to the first clock signal terminal CB, a second electrode connected to the first output terminal OUT1, and a gate connected to the second node N2. The sixteenth transistor T16 has a first electrode connected to the first control node PU1, a second electrode connected to the second node N2, and a gate connected to the first enable signal terminal EM1. The first capacitor C1 has a first electrode connected to the second node N2, and a second electrode connected to the first output terminal OUT1.

[0144] This exemplary embodiment can adjust the refresh frequency of the pixel driving circuit corresponding to the shift register unit by controlling the timing of the first enable signal terminal EM1. As shown in Figure 9, it is a timing diagram of each node of the shift register unit in different display areas of the display panel of the present disclosure. Figure 9 shows the timing diagram of each signal terminal in a frame, wherein CB is the timing diagram of the first clock signal terminal, CK is the timing diagram of the third clock signal terminal, and EM1 is the timing diagram of the first enable signal terminal. This exemplary embodiment can use the first enable signal terminal EM1 to output a low-level signal in some frames, so that the shift register unit always outputs a low-level signal in the frame, thereby reducing the refresh frequency of the display area corresponding to the shift register unit. As shown in Figure 9, the refresh frequency of the first display area will be lower than the refresh frequency of the second display area.

[0145] It should be understood that in other exemplary embodiments, this exemplary embodiment may also utilize the first enable signal terminal EM1 to output a low-level signal in some frames, so that the display panel includes more partitions with different refresh frequencies, and the refresh frequency of each partition is different.

[0146] As shown in FIG8 , the first output circuit 11 may further include a first control circuit 113 connected to the first power supply terminal VGL, the second enable signal terminal EM2, and the second node N2. The first control circuit 113 is configured to transmit the signal from the first power supply terminal VGL to the second node N2 in response to a signal from the second enable signal terminal EM2. The second enable signal terminal EM2 is configured to output an inactive level in the first driving state of the first output circuit 11 and to output an active level in the second driving state of the first output circuit 11. The first control circuit 113 may include a fifteenth transistor T15, wherein a first electrode of the fifteenth transistor T15 is connected to the first power supply terminal VGL, a second electrode is connected to the second node N2, and a gate is connected to the second enable signal terminal EM2.

[0147] As shown in FIG9 , when the first enable signal terminal EM1 outputs a high-level signal and the second enable signal terminal EM2 outputs a low-level signal, the first control circuit 113 does not affect the normal driving of the shift register unit. When the first enable signal terminal EM1 outputs a low-level signal and the second enable signal terminal EM2 outputs a high-level signal, the first control circuit 113 can continuously input a low-level signal to the first output terminal, thereby reducing noise at the first output terminal OUT1.

[0148] The driving method of the shift register unit shown in FIG8 may also include: a first stage t1 , a second stage t2 , a third stage t3 , a fourth stage t4 , and a fifth stage t5 .

[0149] FIG10 is a schematic diagram of another exemplary embodiment of a shift register unit according to the present disclosure. Based on the shift register unit shown in FIG3 , the shift register unit further includes a general reset circuit 7 connected to the first control node PU1, the third control node PU3, the first output terminal OUT1, the second output terminal OUT2, the first power supply terminal VGL, and the general reset signal terminal Tre. The general reset circuit 7 is configured to respond to a signal from the general reset signal terminal Tre to transmit a signal from the first power supply terminal VGL to the first control node PU1, the third control node PU3, the first output terminal OUT1, and the second output terminal OUT2.

[0150] As shown in FIG10 , the master reset circuit 7 includes: at least one of a seventeenth transistor T17, an eighteenth transistor T18, a nineteenth transistor T19, and a twentieth transistor T20. For example, a first electrode of the seventeenth transistor T17 is connected to the first power supply terminal VGL, a second electrode is connected to the third control node PU3, and a gate is connected to the master reset signal terminal Tre; a first electrode of the eighteenth transistor T18 is connected to the first power supply terminal VGL, a second electrode is connected to the first control node PU1, and a gate is connected to the master reset signal terminal Tre; a first electrode of the nineteenth transistor T19 is connected to the first power supply terminal VGL, a second electrode is connected to the first output terminal OUT1, and a gate is connected to the master reset signal terminal Tre; a first electrode of the twentieth transistor T20 is connected to the first power supply terminal VGL, a second electrode is connected to the second output terminal OUT2, and a gate is connected to the master reset signal terminal Tre.

[0151] The general reset circuit 7 can reset the first control node PU1 , the third control node PU3 , the first output terminal OUT1 , and the second output terminal OUT2 during the power-on and power-off of the display panel or during the blank period between frames.

[0152] FIG11 is a schematic diagram showing the structure of another exemplary embodiment of the shift register unit disclosed herein. Based on the shift register unit shown in FIG6 , the shift register unit may also include: a total reset circuit 7 .

[0153] FIG12 is a schematic diagram showing the structure of another exemplary embodiment of the shift register unit disclosed herein. Based on the shift register unit shown in FIG8 , the shift register unit may also include: a total reset circuit 7 .

[0154] This exemplary embodiment further provides a gate driving circuit, as shown in Figure 13, which is a schematic structural diagram of an exemplary embodiment of the gate driving circuit disclosed herein. The gate driving circuit includes a plurality of the above-mentioned shift register units GOA.

[0155] As shown in FIG13 , the gate drive circuit further includes a first clock signal line LCB, a second clock signal line LCK, a third clock signal line LCK2, and a fourth clock signal line LCB2. The first clock signal line LCB is used to provide a clock signal to the first clock signal terminal CB of the odd-numbered shift register unit and the third clock signal terminal of the even-numbered shift register unit; the second clock signal line LCK is used to provide a clock signal to the first clock signal terminal CB of the even-numbered shift register unit and the third clock signal terminal of the odd-numbered shift register unit; the third clock signal line LCK2 is used to provide a clock signal to the second clock signal terminal of the even-numbered shift register unit; and the fourth clock signal line LCB2 is used to provide a clock signal to the second clock signal terminal of the odd-numbered shift register unit.

[0156] This exemplary embodiment also provides a display panel, which may include the above-mentioned gate driving circuit. The display panel can be used in computers, mobile phones, tablet computers, televisions, etc.

[0157] This exemplary embodiment further provides a display panel driving method, wherein the driving method is used to drive the above-mentioned display panel, wherein the display area of ​​the display panel includes a first display area and a second display area, and the driving method includes:

[0158] In the same time period, respectively controlling the number of frames in which the shift register units corresponding to the first display area and the second display area are in the second driving state;

[0159] The number of frames in which the shift register unit corresponding to the first display area is in the second driving state is greater than the number of frames in which the shift register unit corresponding to the second display area is in the second driving state, and the refresh frequency of the first display area is less than the refresh frequency of the second display area.

[0160] It should be understood that in other exemplary embodiments, the display panel may further include more partitions with different refresh frequencies, and the refresh frequency of each partition is different. Accordingly, the number of frames in which the shift register units corresponding to different partitions are in the second driving state is different.

[0161] This exemplary embodiment further provides a display panel driving method, wherein the driving method is used to drive the above-mentioned display panel, the display panel includes a first display area, and the driving method includes:

[0162] In the first period, the number of frames for which the shift register unit connected to the first display area is controlled to be in the second driving state is n1;

[0163] In the second period, the number of frames during which the shift register unit connected to the first display area is controlled to be in the second driving state is n2, where n1 and n2 are positive integers greater than or equal to 1;

[0164] n1 is greater than n2, and the refresh frequency of the first display area in the first time period is less than the refresh frequency in the second time period.

[0165] When the first output circuit in the shift register unit is in the second driving state, the shift register unit is in the second driving state.

[0166] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0167] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing what is disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

[0168] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A shift register unit, wherein: The shift register unit is applied to a gate driving circuit in a display panel, the gate driving circuit includes a plurality of cascaded shift register units, the display panel includes a pixel driving circuit, and the shift register unit includes: a first output circuit, the first output circuit being configured to provide a gate driving signal to the pixel driving circuit in a first driving state, and being configured to provide an invalid level signal to the pixel driving circuit in a second driving state; The second output circuit is electrically connected to the first output circuit, and the second output circuit is used to provide an input signal to the lower-stage shift register unit.

2. The shift register unit according to claim 1, wherein: The first output circuit is connected to a first control node, a second control node, and a first output terminal, and is configured to provide the gate driving signal to the first output terminal in response to at least signals of the first control node and the second control node, and the first output terminal is configured to be connected to a pixel driving circuit; The second output circuit is connected to the first control node, the second control node, and the second output end. The second output circuit is used to respond to at least the signals of the first control node and the second control node to provide the input signal to the second output end. The second output end is used to connect to the next stage shift register unit.

3. The shift register unit according to claim 2, wherein: The first output circuit includes: a first sub-output circuit connected to the second clock signal terminal, the first control node, and the first output terminal, the first sub-output circuit being configured to transmit the signal of the second clock signal terminal to the first output terminal in response to a signal of the first control node; a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node; The first clock signal terminal and the second clock signal terminal are used to output clock signals with the same timing in the first driving state of the first output circuit; The second clock signal terminal is used to output an invalid level signal in the second driving state of the first output circuit.

4. The shift register unit according to claim 2, wherein: The first output circuit includes: a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a first node, the first sub-output circuit being configured to respond to a signal at the first enable signal terminal to transmit a signal at the first clock signal terminal to the first node, and to respond to a signal at the first control node to transmit a signal at the first node to the first output terminal; a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node; The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit.

5. The shift register unit according to claim 2, wherein: The first output circuit includes: a first sub-output circuit connected to a first clock signal terminal, a first control node, a first enable signal terminal, a first output terminal, and a second node, the first sub-output circuit being configured to transmit a signal from the first control node to the second node in response to a signal from the first enable signal terminal, and to transmit a signal from the first clock signal terminal to the first output terminal in response to a signal from the second node; a second sub-output circuit connected to the first power supply terminal, the first output terminal, and a second control node, the second sub-output circuit being configured to transmit a signal from the first power supply terminal to the first output terminal in response to a signal from the second control node; The first enable signal terminal is used to output a valid level in a first driving state of the first output circuit, and is used to output an invalid level in a second driving state of the first output circuit. The shift register unit according to claim 5 , wherein: The first output circuit further includes: a first control circuit connected to the first power supply terminal, the second enable signal terminal, and the second node, the first control circuit being configured to transmit the signal of the first power supply terminal to the second node in response to a signal of the second enable signal terminal; The second enable signal terminal is used to output an invalid level in a first driving state of the first output circuit, and is used to output a valid level in a second driving state of the first output circuit.

7. The shift register unit according to any one of claims 3 to 6, wherein: The second sub-output circuit is further connected to a third clock signal terminal, and is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power supply terminal to the first output terminal.

8. The shift register unit according to any one of claims 2 to 7, wherein: The second output circuit includes: a third sub-output circuit connected to the first clock signal terminal, the first control node, and the second output terminal, the third sub-output circuit being configured to respond to a signal of the first control node to transmit a signal from the first clock signal terminal to the second output terminal; The fourth sub-output circuit is connected to the first power supply terminal, the second output terminal, and the second control node. The fourth sub-output circuit is used to respond to the signal of the second control node to transmit the signal of the first power supply terminal to the second output terminal.

9. The shift register unit according to claim 8, wherein: The fourth sub-output circuit is also connected to the third clock signal terminal, and is further configured to respond to a signal from the third clock signal terminal to transmit a signal from the first power supply terminal to the second output terminal.

10. The shift register unit according to any one of claims 1 to 9, wherein: The shift register unit further includes: an input circuit connected to the input signal terminal, a third control node, and a third clock signal terminal, the input circuit being configured to transmit an input signal from the input signal terminal to the third control node in response to a signal from the third clock signal terminal, wherein the third control node is connected to the first control node; a second control circuit connected to the third control node, the first clock signal terminal, the second control node, and the first power terminal, the second control circuit being configured to respond to signals from the first clock signal terminal and the second control node to transmit the signal from the first power terminal to the third control node; A third control circuit is connected to the third control node, the first power supply terminal, and the second control node, and the third control circuit is used to respond to the signal of the third control node to turn on the first power supply terminal. The signal of the terminal is transmitted to the second control node; A fourth control circuit is connected to the third control node, the first clock signal terminal, the second control node, the third node, and the first power supply terminal. The fourth control circuit is used to respond to the signal of the third control node to transmit the signal of the first power supply terminal to the third node, to respond to the signal of the first clock signal terminal to input a valid level signal to the third node, and to respond to the signal of the third node to input a valid level signal to the second control node.

11. The shift register unit according to claim 10, wherein: The shift register unit further includes: The isolation circuit is connected to the second control node, the third control node, and the third clock signal terminal. The isolation circuit is used to respond to the signal of the third clock signal terminal to connect the second control node and the third control node.

12. The shift register unit according to claim 10 or 11, wherein: The shift register unit further includes: A total reset circuit is connected to the first control node, the third control node, the first output terminal, the second output terminal, the first power supply terminal, and the total reset signal terminal. The total reset circuit is used to respond to the signal of the total reset signal terminal to transmit the signal of the first power supply terminal to the first control node, the third control node, the first output terminal, and the second output terminal.

13. The shift register unit according to claim 3, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the second clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the first control node; A first capacitor has a first electrode connected to the first control node and a second electrode connected to the first output terminal.

14. The shift register unit according to claim 4, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the first node, a second electrode connected to the first output terminal, and a gate connected to the first control node; a fifteenth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first node, and a gate connected to the first enable signal terminal; A first capacitor, a first electrode connected to the first control node, and a second electrode connected to the first Output end.

15. The shift register unit according to claim 6, wherein: The first sub-output circuit includes: a fifth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the first output terminal, and a gate connected to the second node; a sixteenth transistor, having a first electrode connected to the first control node, a second electrode connected to the second node, and a gate connected to the first enable signal terminal; a first capacitor, a first electrode of which is connected to the second node, and a second electrode of which is connected to the first output terminal; The first control circuit includes: The fifteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second node, and a gate connected to the second enable signal terminal.

16. The shift register unit according to claim 7, wherein: The second sub-output circuit includes: a fourth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the second control node; a ninth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the third clock signal terminal; A second capacitor has a first electrode connected to the second control node and a second electrode connected to the first power supply terminal.

17. The shift register unit according to claim 9, wherein: The third sub-output circuit includes: a twelfth transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the second output terminal, and a gate connected to the first control node; a third capacitor, a first electrode of which is connected to the first control node, and a second electrode of which is connected to the second output terminal; The fourth sub-output circuit includes: a thirteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the second control node; The fourteenth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the third clock signal terminal.

18. The shift register unit according to claim 11, wherein: The input circuit comprises: a first transistor, having a first electrode connected to the input signal terminal, a second electrode connected to the third control node, and a gate connected to the third clock signal terminal; The isolation circuit comprises: an eighth transistor, having a first electrode connected to the third control node, a second electrode connected to the first control node, and a gate connected to the third clock signal terminal; The second control circuit includes: a sixth transistor, having a first electrode connected to the first power supply terminal and a gate connected to the second control node; a seventh transistor, having a first electrode connected to the second electrode of the sixth transistor, a second electrode connected to the third control node, and a gate connected to the first clock signal terminal; The third control circuit includes: an eleventh transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the second control node, and a gate connected to the third control node; The fourth control circuit is configured to input a valid level signal to the third node using the first clock signal terminal in response to a signal from the first clock signal terminal, and to input a valid level signal to the second control node using the first clock signal terminal in response to a signal from the third node. The fourth control circuit includes: a third transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third node, and a gate connected to the third control node; a second transistor, having a first electrode connected to the first clock signal terminal, a second electrode connected to the third node, and a gate connected to the first clock signal terminal; The tenth transistor has a first electrode connected to the first clock signal terminal, a second electrode connected to the second control node, and a gate connected to the third node.

19. The shift register unit according to claim 12, wherein: The total reset circuit comprises: a seventeenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the third control node, and a gate connected to the general reset signal terminal; an eighteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first control node, and a gate connected to the general reset signal terminal; A nineteenth transistor, having a first electrode connected to the first power supply terminal, a second electrode connected to the first output terminal, and a gate connected to the general reset signal terminal; The twentieth transistor has a first electrode connected to the first power supply terminal, a second electrode connected to the second output terminal, and a gate connected to the general reset signal terminal.

20. The shift register unit according to any one of claims 1 to 19, wherein: The timings of the input signal and the gate driving signal are the same or different.

21. The shift register unit according to any one of claims 1 to 19, wherein: The first output circuit is connected to a first output terminal, and is configured to provide the invalid level signal or the gate driving signal to the pixel driving circuit via the first output terminal.

22. The shift register unit according to claim 3, wherein: The duty cycle of the effective level on the first clock signal terminal is greater than the duty cycle of the effective level on the second clock signal terminal.

23. A gate drive circuit, wherein: The gate driving circuit includes a plurality of shift register units according to any one of claims 1 to 21.

24. A display panel, wherein: The display panel includes the gate driving circuit according to claim 23.

25. A display panel driving method, wherein: The driving method is used to drive the display panel according to claim 24, wherein the display area of ​​the display panel includes a first display area and a second display area, and the driving method includes: In the same time period, respectively controlling the number of frames in which the shift register units corresponding to the first display area and the second display area are in the second driving state; The number of frames in which the shift register unit corresponding to the first display area is in the second driving state is greater than the number of frames in which the shift register unit corresponding to the second display area is in the second driving state, and the refresh frequency of the first display area is less than the refresh frequency of the second display area.

26. A display panel driving method, wherein: The driving method is used to drive the display panel according to claim 24, wherein the display panel includes a first display area, and the driving method includes: In a first period, the number of frames for which the shift register unit corresponding to the first display area is controlled to be in a second driving state is n1; In the second period, the number of frames during which the shift register unit connected to the first display area is controlled to be in the second driving state is n2, where n1 and n2 are positive integers greater than or equal to 1; n1 is greater than n2, and the refresh frequency of the first display area in the first period is less than that in the second period. refresh frequency.

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