Pixel circuit, display substrate and display apparatus

Abstract

Provided are a pixel circuit, a display substrate and a display apparatus. The pixel circuit comprises a driving circuit and a switching circuit, which are used for controlling the turning on or off of different pixel units, wherein at least one pixel unit comprises a first sub-pixel and a second sub-pixel arranged adjacent to each other; the first sub-pixel comprises a first light-emitting element; the second sub-pixel comprises a second light-emitting element; both the first light-emitting element and the second light-emitting element emit light of a first wavelength; the first sub-pixel has a first viewing angle; the second sub-pixel has a second viewing angle; and the first viewing angle is smaller than the second viewing angle. The switching circuit comprises: a first sub-pixel switching circuit configured to control the turning on or off of the first sub-pixel; and a second sub-pixel switching circuit configured to control the turning on or off of the second sub-pixel, wherein the first sub-pixel switching circuit and the second sub-pixel switching circuit share the driving circuit.

Description

Pixel circuit, display substrate, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a pixel circuit, a display substrate, and a display device. Background Art

[0002] Privacy screens have two display modes: privacy-preventing and sharing. In privacy-preventing mode, the screen's field of view decreases, protecting privacy; in sharing mode, the screen's field of view increases, allowing for sharing of displayed content. Organic Light-Emitting Diode (OLED) displays offer advantages such as active illumination, wide viewing angles, high contrast, fast response times, low power consumption, and ultra-thinness. OLED privacy screens have garnered widespread attention.

[0003] How to optimize the driving circuit of OLED anti-peeping display screen is one of the important research topics for R&D personnel.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art.

[0005] Summary of the Invention

[0006] In one aspect, a pixel circuit is provided, which includes a driving circuit and a switching circuit for controlling different pixel units to turn on or off, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, the first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element, wherein the first light-emitting element and the second light-emitting element both emit light of a first wavelength, the first sub-pixel has a first field of view angle, and the second sub-pixel has a second field of view angle, and the first field of view angle is smaller than the second field of view angle, wherein the switching circuit includes: a first sub-pixel switching circuit for controlling the first sub-pixel to turn on or off; and a second sub-pixel switching circuit for controlling the second sub-pixel to turn on or off; the first sub-pixel switching circuit and the second sub-pixel switching circuit share one driving circuit.

[0007] According to some exemplary embodiments, the first sub-pixel switching circuit is respectively coupled to the second light-emitting control signal terminal, the driving circuit and the first electrode of the first light-emitting element, and the first sub-pixel switching circuit is configured to control the on-off of the driving circuit and the first light-emitting element in response to the second light-emitting control signal provided by the second light-emitting control signal terminal; the second sub-pixel switching circuit is respectively coupled to the third light-emitting control signal terminal, the driving circuit and the first electrode of the second light-emitting element, and the second sub-pixel switching circuit is configured to control the on-off of the driving circuit and the second light-emitting element in response to the third light-emitting control signal provided by the third light-emitting control signal terminal.

[0008] According to some exemplary embodiments, the first sub-pixel switching circuit and the first electrode of the first light-emitting element are coupled to a fourth node; the switching circuit also includes a third initialization sub-circuit, which is coupled to the reset signal terminal, the fourth node and the initialization signal terminal, and the third initialization sub-circuit is configured to respond to the reset signal received at the reset signal terminal, transmit the initialization signal received at the initialization signal terminal to the fourth node, so as to initialize the potential of the fourth node.

[0009] According to some exemplary embodiments, the first sub-pixel switch circuit and the first electrode of the first light-emitting element are coupled to a fourth node; the second sub-pixel switch circuit and the first electrode of the second light-emitting element are coupled to a fifth node; the switch circuit further includes a third initialization sub-circuit and a fourth initialization sub-circuit, wherein the third initialization sub-circuit is coupled to the reset signal terminal, the fourth node and the initialization signal terminal, and the third initialization sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the fourth node in response to the reset signal received at the reset signal terminal, so as to initialize the potential of the fourth node; the fourth initialization sub-circuit is coupled to the reset signal terminal, the fifth node and the initialization signal terminal, and the fourth initialization sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the fifth node in response to the reset signal received at the reset signal terminal, so as to initialize the potential of the fifth node.

[0010] According to some exemplary embodiments, the first sub-pixel switch circuit is respectively coupled to the second light-emitting control signal terminal, the first electrode of the first light-emitting element and the second electrode of the first light-emitting element, and the first sub-pixel switch circuit is configured to short-circuit the first light-emitting element in response to the second light-emitting control signal provided at the second light-emitting control signal terminal; the first electrode of the first light-emitting element, the first sub-pixel switch circuit and the driving circuit are coupled to a fourth node; the second sub-pixel switch circuit is respectively coupled to the third light-emitting control signal terminal, the first electrode of the second light-emitting element and the second electrode of the second light-emitting element, and the second sub-pixel switch circuit is configured to short-circuit the second light-emitting element in response to the third light-emitting control signal provided at the third light-emitting control signal terminal; the second electrode of the first light-emitting element, the first electrode of the second light-emitting element, the first sub-pixel switch circuit and the second sub-pixel switch circuit are coupled to a fifth node.

[0011] According to some exemplary embodiments, the switching circuit further includes a third initialization sub-circuit, which is coupled to the reset signal terminal, the fourth node and the initialization signal terminal, and the third initialization sub-circuit is configured to respond to the reset signal received at the reset signal terminal, transmit the initialization signal received at the initialization signal terminal to the fourth node, so as to initialize the potential of the fourth node.

[0012] According to some exemplary embodiments, the initialization signal terminal includes one of a first initialization signal terminal or a second initialization signal terminal.

[0013] According to some exemplary embodiments, the first sub-pixel switch circuit, the second sub-pixel switch circuit, and the driving circuit are coupled to a sixth node.

[0014] According to some exemplary embodiments, the driving circuit includes a second light-emitting control sub-circuit, which is coupled to the first light-emitting control signal terminal, the third node and the sixth node, and the second light-emitting control sub-circuit is configured to transmit the driving current from the third node to the sixth node in response to the first light-emitting control signal received at the first light-emitting control signal terminal.

[0015] According to some exemplary embodiments, the first sub-pixel switch circuit, the second sub-pixel switch circuit, and the driving circuit are coupled to a third node.

[0016] According to some exemplary embodiments, the driving circuit includes a second light-emitting control sub-circuit, which is coupled to the first light-emitting control signal terminal, the third node and the fourth node, and the second light-emitting control sub-circuit is configured to transmit the driving current from the third node to the fourth node in response to the first light-emitting control signal received at the first light-emitting control signal terminal.

[0017] According to some exemplary embodiments, the driving circuit further includes: a data writing sub-circuit, the data writing sub-circuit being coupled to a data signal terminal, a scan signal terminal and a second node, the data writing sub-circuit being configured to write a data signal received at the data signal terminal to the second node in response to a scan signal received at the scan signal terminal; a driving sub-circuit, the driving sub-circuit being coupled to a voltage signal terminal, a first node and a third node, the driving sub-circuit being configured to generate a driving current in response to a voltage at the first node; a compensation sub-circuit, the compensation sub-circuit being coupled to the scan signal terminal, the first node and the third node, the compensation sub-circuit being configured to transmit a voltage signal from the voltage signal terminal and a threshold voltage of the driving sub-circuit to the first node in response to a scan signal received at the scan signal terminal; and a storage sub-circuit, the storage sub-circuit being coupled between the first node and the second node, the storage sub-circuit being configured to store a voltage.

[0018] According to some exemplary embodiments, the driving circuit further includes: a first initialization sub-circuit, which is coupled to a first initialization signal terminal, the reset signal terminal and the first node, and the first initialization sub-circuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the first node in response to the reset signal received at the reset signal terminal to initialize the potential of the first node.

[0019] According to some exemplary embodiments, the driving circuit further includes: a second initialization sub-circuit, which is coupled to the reference voltage signal terminal, the reset signal terminal and the second node, and the second initialization sub-circuit is configured to transmit the reference voltage signal received at the reference voltage signal terminal to the second node in response to the reset signal received at the reset signal terminal.

[0020] According to some exemplary embodiments, the driving circuit further includes: a first light-emitting control sub-circuit, which is coupled to a reference voltage signal terminal, a first light-emitting control signal terminal and the second node, and the first light-emitting control sub-circuit is configured to transmit a reference voltage signal received at the reference voltage signal terminal to the second node in response to a first light-emitting control signal received at the first light-emitting control signal terminal.

[0021] According to some exemplary embodiments, the driving circuit further includes: an auxiliary sub-circuit coupled to the first node and a first light-emitting control signal terminal.

[0022] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a pixel circuit as described in any one of the above items arranged on the base substrate, wherein the pixel circuit includes a driving circuit and a switching circuit; a plurality of pixel units arranged on the base substrate, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, the first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element, wherein the first light-emitting element and the second light-emitting element both emit light of a first wavelength; and a light-shielding portion arranged on a side of the pixel unit away from the base substrate, wherein the light-shielding portion includes a plurality of openings, the orthographic projections of the openings on the base substrate at least partially overlap with the orthographic projections of the first sub-pixel on the base substrate; the orthographic projections of the light-shielding portion on the base substrate do not overlap with the orthographic projections of the second sub-pixel on the base substrate, wherein the switching circuit includes: a first sub-pixel switching circuit for controlling the first sub-pixel to be turned on or off; and a second sub-pixel switching circuit for controlling the second sub-pixel to be turned on or off; the first sub-pixel switching circuit and the second sub-pixel switching circuit share a driving circuit.

[0023] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a plurality of pixel units arranged on the base substrate, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction on the base substrate; a plurality of pixel circuits, wherein the plurality of pixel circuits are used to drive the plurality of pixel units, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, the first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element, wherein the first light-emitting element and the second light-emitting element both emit light of a first wavelength; and a light-shielding portion, which is provided on a side of the pixel unit away from the base substrate, wherein the light-shielding portion includes a plurality of openings. The orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the first sub-pixel on the substrate; the orthographic projection of the light shielding portion on the substrate does not overlap with the orthographic projection of the second sub-pixel on the substrate, wherein the pixel circuit includes a driving circuit and a switching circuit, the switching circuit including: a first sub-pixel switching circuit for controlling the opening or closing of the first sub-pixel; and a second sub-pixel switching circuit for controlling the opening or closing of the second sub-pixel; the first sub-pixel switching circuit and the second sub-pixel switching circuit share a driving circuit; the display substrate includes: a first conductive layer provided on the substrate; a conductive layer provided on the first conductive layer away from the substrate a first semiconductor layer on one side; a second conductive layer arranged on a side of the first semiconductor layer away from the base substrate; a third conductive layer arranged on a side of the second conductive layer away from the base substrate; a fourth conductive layer arranged on a side of the third conductive layer away from the base substrate; a fifth conductive layer arranged on a side of the fourth conductive layer away from the base substrate, wherein the first electrode of the first light-emitting element and the first electrode of the second light-emitting element are both located in the fifth conductive layer; the first sub-pixel switching circuit includes a third light-emitting control transistor, the third light-emitting control transistor includes a first electrode and a second electrode, the first electrode of the third light-emitting control transistor is electrically connected to the first electrode of the first light-emitting element through a first conductive transition portion The second sub-pixel switching circuit includes a fourth light-emitting control transistor, the fourth light-emitting control transistor includes a first electrode and a second electrode, the first electrode of the fourth light-emitting control transistor is electrically connected to the first electrode of the second light-emitting element through a second conductive transition portion, the driving circuit includes a second light-emitting control sub-circuit, the second light-emitting control sub-circuit includes a second light-emitting control transistor, the second light-emitting control transistor includes a first electrode, the second electrode of the third light-emitting control transistor, the second electrode of the fourth light-emitting control transistor and the first electrode of the second light-emitting control transistor are electrically connected through a third conductive transition portion, and the first conductive transition portion, the second conductive transition portion and the third conductive transition portion are all located in the third conductive layer.

[0024] According to some exemplary embodiments, the display substrate further includes a reset signal line, a second light-emitting control signal line, and a third light-emitting control signal line extending along a first direction, wherein the reset signal line includes a first reset signal sub-line, and the first reset signal sub-line, the second light-emitting control signal line, and the third light-emitting control signal line are all located in the second conductive layer; the third light-emitting control transistor further includes a third light-emitting control active layer and a control electrode, the third light-emitting control active layer is located in the first semiconductor layer, the orthographic projection of the third light-emitting control active layer on the base substrate at least partially overlaps with the orthographic projection of the second light-emitting control signal line on the base substrate, and the overlapping portion of the third light-emitting control active layer and the second light-emitting control signal line is the control electrode of the third light-emitting control transistor; the fourth light-emitting control transistor further includes a fourth light-emitting control active layer and a control electrode, the fourth light-emitting control active layer is located in the first semiconductor layer, the orthographic projection of the fourth light-emitting control active layer on the base substrate at least partially overlaps with the orthographic projection of the third light-emitting control signal line on the base substrate, and the overlapping portion of the fourth light-emitting control active layer and the third light-emitting control signal line is the control electrode of the third light-emitting control transistor.

[0025] According to some exemplary embodiments, the switching circuit further includes a third initialization sub-circuit, the third initialization sub-circuit includes a third initialization transistor, the third initialization transistor includes a third initialization active layer, a control electrode, a first electrode and a second electrode, the orthographic projection of the third initialization active layer on the substrate at least partially overlaps with the orthographic projection of the first sub-line of the reset signal on the substrate, the overlapping portion of the third initialization active layer and the first sub-line of the reset signal is the control electrode of the third initialization transistor, the second electrode of the third initialization transistor is electrically connected to the first electrode of the first light-emitting element through the first conductive transition portion; the display substrate further includes a second initialization signal line extending along the second direction, the second initialization signal line is located in the fourth conductive layer, and the first electrode of the third initialization transistor is electrically connected to the second initialization signal line through the fourth conductive transition portion.

[0026] According to some exemplary embodiments, the display substrate further includes a first initialization signal first sub-line, a reference voltage signal first sub-line, and a voltage signal first sub-line extending along a first direction, wherein the first initialization signal first sub-line and the reference voltage signal first sub-line are located in the second conductive layer, and the voltage signal first sub-line is located in the third conductive layer; the display substrate further includes a first initialization signal second sub-line, a reference voltage signal second sub-line, and a voltage signal second sub-line extending along a second direction, wherein the first initialization signal second sub-line, the reference voltage signal second sub-line, and the voltage signal second sub-line are all located in the fourth conductive layer, wherein the first initialization signal first sub-line and the first initialization signal second sub-line are electrically connected to form a mesh structure; the reference voltage signal first sub-line and the reference voltage signal second sub-line are electrically connected to form a mesh structure; the voltage signal first sub-line and the voltage signal second sub-line are electrically connected to form a mesh structure.

[0027] According to some exemplary embodiments, the display substrate further includes a scanning signal line extending along a first direction, wherein the scanning signal line includes a first scanning signal sub-line and a second scanning signal sub-line, the first scanning signal sub-line is located in the first conductive layer, and the second scanning signal sub-line is located in the third conductive layer; the driving circuit further includes a compensation sub-circuit, the compensation sub-circuit includes a compensation transistor, the compensation transistor includes a compensation active layer and a control electrode, the control electrode of the compensation transistor includes a first sub-control electrode and a second sub-control electrode, wherein the positive projections of any two of the compensation active layer, the first scanning signal sub-line and the second scanning signal sub-line on the substrate at least partially overlap, the overlapping portion of the compensation active layer and the first scanning signal sub-line is the first sub-control electrode of the compensation transistor, and the overlapping portion of the compensation active layer and the second scanning signal sub-line is the second sub-control electrode of the compensation transistor.

[0028] According to some exemplary embodiments, the reset signal line also includes a reset signal second sub-line, which is located in the third conductive layer; the display substrate also includes a reset signal switching portion, which is located in the first conductive layer, wherein the reset signal second sub-line is electrically connected to the reset signal switching portion through a first via; the driving circuit also includes a first initialization sub-circuit, the first initialization sub-circuit includes a first initialization transistor, the first initialization transistor includes a first initialization active layer and a control electrode, the control electrode of the first initialization transistor includes a third sub-control electrode and a fourth sub-control electrode, wherein the positive projections of any two of the first initialization active layer, the reset signal second sub-line and the reset signal switching portion on the base substrate at least partially overlap, the overlapping portion of the first initialization active layer and the reset signal switching portion is the third sub-control electrode of the first initialization transistor, and the overlapping portion of the first initialization active layer and the reset signal second sub-line is the fourth sub-control electrode of the first initialization transistor.

[0029] According to some exemplary embodiments, the display substrate further includes a first light-emitting control signal line extending along a first direction; the driving circuit further includes: a first light-emitting control subcircuit, a second light-emitting control subcircuit and an auxiliary subcircuit, wherein the first light-emitting control subcircuit includes a first light-emitting control transistor, and the first light-emitting control transistor includes a first light-emitting control active layer and a control electrode; the second light-emitting control subcircuit includes a second light-emitting control transistor, and the second light-emitting control transistor includes a second light-emitting control active layer and a control electrode; the auxiliary subcircuit includes an auxiliary transistor, and the auxiliary transistor includes a charge release active layer, a control electrode and a second electrode, wherein the orthographic projection of the first light-emitting control active layer on the substrate is aligned with the projection of the first light-emitting control signal line on the substrate. The orthographic projections on the substrate at least partially overlap, and the overlapping portion of the first light-emitting control active layer and the first light-emitting control signal line is the control electrode of the first light-emitting control transistor; the orthographic projection of the second light-emitting control active layer on the substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line on the substrate, and the overlapping portion of the second light-emitting control active layer and the first light-emitting control signal line is the control electrode of the second light-emitting control transistor; the orthographic projection of the charge release active layer on the substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line on the substrate, and the overlapping portion of the charge release active layer and the first light-emitting control signal line is the control electrode of the auxiliary transistor; and the second electrode of the auxiliary transistor is suspended.

[0030] According to some exemplary embodiments, the display substrate further includes a data signal line extending along a second direction, wherein the data signal line is located in the fourth conductive layer; the driving circuit further includes a data writing sub-circuit, wherein the data writing sub-circuit includes a data writing transistor, wherein the data writing transistor includes a data writing active layer and a second electrode, wherein the orthographic projection of the data writing active layer on the base substrate at least partially overlaps with the orthographic projection of the signal scanning first sub-line on the base substrate, and the overlapping portion of the data writing active layer and the signal scanning first sub-line is the control electrode of the data writing transistor; the second electrode of the data writing transistor is electrically connected to the data signal line through a sixth conductive transition portion, wherein the sixth conductive transition portion is located in the third conductive layer.

[0031] According to some exemplary embodiments, the driving circuit further includes a driving sub-circuit, the driving sub-circuit includes a driving transistor, the driving transistor includes a first electrode, the first electrode of the driving transistor is electrically connected to the second sub-line of the voltage signal through a fifth conductive transition portion, wherein the fifth conductive transition portion is located in the third conductive layer.

[0032] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above contents and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0034] 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure; FIG. 2 is a schematic partial cross-sectional view of a display substrate taken along line AA′ of FIG. 1 according to an embodiment of the present disclosure;

[0035] FIG3 is a schematic diagram showing connections between a pixel circuit and a pixel unit according to an embodiment of the present disclosure;

[0036] FIG4 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG5 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0037] FIG6 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG7 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0038] FIG8 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG9 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0039] FIG10 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG11 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0040] 12A is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG12B is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG12C is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG12D is a schematic diagram illustrating a planar structure of a combination of a first conductive layer and a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG12E is a schematic diagram illustrating a planar structure of a third conductive layer and a plurality of vias according to an exemplary embodiment of the present disclosure; FIG12F is a schematic diagram illustrating a planar structure of a fourth conductive layer and a plurality of vias of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG13 is a schematic diagram illustrating a planar structure of a combination of a first conductive layer, a second conductive layer, a first semiconductor layer, a third conductive layer, and a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure; FIG14 is a schematic partial cross-sectional view of a pixel circuit according to an exemplary embodiment of the present disclosure taken along line BB' in FIG13;

[0041] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0042] It should be noted that, for the sake of clarity, in the drawings used to describe the embodiments of the present invention, the sizes of layers, structures or regions may be enlarged or reduced, that is, these drawings are not drawn according to the actual scale. DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0045] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by those of ordinary skill in the art. The terms "first," "second," and similar terms used in this disclosure do not denote any order, quantity, or importance, but are simply used to distinguish different components. The terms "include," "comprising," and similar words mean that the element or object preceding the word encompasses the elements or objects listed after the word, and their equivalents, without excluding other elements or objects.

[0046] Unless otherwise specified, directional terms such as "upper," "lower," "left," "right," "inner," and "outer" are used herein to indicate positions or relationships based on the figures shown. These terms are intended solely to facilitate the description of the present disclosure and are not intended to indicate or imply that the devices, components, or parts referred to must have, be constructed, or operate in a specific orientation. It should be understood that when the absolute positions of the objects being described change, the relative positions they represent may also change accordingly. Therefore, these directional terms should not be construed as limiting the present disclosure.

[0047] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0048] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0049] In this document, the directional expressions "first direction" and "second direction" are used to describe different directions along a pixel unit, such as the longitudinal and transverse directions of a pixel unit, or the row and column directions of a sub-pixel arrangement. It should be understood that such expressions are merely exemplary descriptions and are not intended to limit the present disclosure.

[0050] The transistors used in all embodiments of the present disclosure may be thin film transistors (TFTs), field effect transistors (MOSs), or other devices with the same characteristics, and the embodiments of the present disclosure are not limited thereto.

[0051] For example, the transistor may be a TFT. The TFT may be manufactured using an a-Si process, an oxide semiconductor process, a low-temperature polysilicon (LTPS) process, or a high-temperature polysilicon (HTPS) process. The embodiments of the present disclosure are not limited thereto.

[0052] The embodiments of the present disclosure do not limit the type of transistor. The transistor can be an N-type transistor or a P-type transistor, an enhancement-type transistor or a depletion-type transistor. In the embodiments of the present disclosure, the present application is exemplarily described by taking all transistors as N-type transistors as an example. The N-type transistor is turned on (opened) under the action of a high-level voltage signal and is turned off (shut off) under the action of a low-level voltage signal; in the embodiments of the present disclosure, "operating voltage" refers to the voltage that can control the conduction of the N-type transistor, that is, the high-level voltage; "cut-off voltage" refers to the voltage that can control the cut-off of the N-type transistor, that is, the low-level voltage.

[0053] In the embodiments of the present disclosure, the gate of a transistor is a control electrode. To distinguish the two electrodes of the transistor other than the gate, one of the electrodes is directly described as a first electrode and the other as a second electrode. In this case, the first electrode of the transistor can be one of the source and drain of the transistor, and the second electrode can be the other of the source and drain of the transistor. Since the source and drain of a transistor can be symmetrical in structure, their structures can be identical.

[0054] The capacitor in the embodiments of the present disclosure can be a capacitive device independently manufactured through a process, for example, by manufacturing a dedicated capacitor electrode. The individual capacitor electrodes (first plate and second plate) of the capacitor can be implemented by a metal layer, a semiconductor layer (e.g., doped polysilicon), etc. The capacitor can also be a parasitic capacitance between transistors, or implemented by the transistor itself and other devices or circuits, or by utilizing the parasitic capacitance between the circuits within the circuit itself.

[0055] In an OLED privacy-prevention display, two identical OLED devices, such as OLED1 and OLED2, are designed within a pixel unit. In privacy-prevention mode, only OLED1 devices emit light. A special optical structure above the OLED1 devices reduces the viewing angle, achieving privacy protection. In shared mode, only OLED2 devices emit light. No special optical structure above the OLED2 devices allows for a wider viewing angle.

[0056] In the related art, separate pixel circuits are configured for the light-emitting elements in the two modes, thereby driving the OLED anti-peeping display device to display in different modes. The separate pixel circuits configured for the light-emitting devices in the two modes result in a complex pixel circuit design and a large number of wiring, which is not conducive to the thinness and narrow frame of the display substrate.

[0057] Some embodiments of the present disclosure provide a pixel circuit, which includes a driving circuit and a switching circuit for controlling different pixel units to turn on or off, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, the first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element, wherein the first light-emitting element and the second light-emitting element both emit light of a first wavelength, the first sub-pixel has a first field of view angle, and the second sub-pixel has a second field of view angle, and the first field of view angle is smaller than the second field of view angle, wherein the switching circuit includes: a first sub-pixel switching circuit for controlling the first sub-pixel to turn on or off; and a second sub-pixel switching circuit for controlling the second sub-pixel to turn on or off; the first sub-pixel switching circuit and the second sub-pixel switching circuit share one driving circuit.

[0058] In the embodiment of the present disclosure, the pixel circuits of two light-emitting elements of the same color can share a driving circuit, and combined with a switching circuit to control the two light-emitting elements of the same color to light up or not to light up to achieve different modes of display, which can reduce the complexity of the pixel circuit, reduce the number of transistors and the number of wirings, and help save wiring space, thereby helping to achieve a thinner and lighter display substrate with a narrower frame.

[0059] 1 is a schematic plan view of a display substrate according to an embodiment of the present disclosure; and FIG. 2 is a schematic partial cross-sectional view of the display substrate taken along line AA′ in FIG. 1 according to an embodiment of the present disclosure.

[0060] For example, in an embodiment of the present disclosure, with reference to FIG1 and FIG2 , a display substrate 100 is provided. The display substrate 100 includes: a base substrate 1; a plurality of pixel units 20 disposed on the base substrate 1; and a pixel circuit 30 for driving the pixel units 20. The plurality of pixel units 20 are arranged in an array in a display area AA along a first direction X or a second direction Y, where the first direction X and the second direction Y intersect. At least one pixel unit 20 includes a first sub-pixel SP1 and a second sub-pixel SP2 disposed adjacent to each other. The first sub-pixel SP1 may include a first light-emitting element L1, and the second sub-pixel SP2 may include a second light-emitting element L2. The first light-emitting element L1 and the second light-emitting element L2 may emit light of the same color, such as red, green, blue, or white light. The region where the first subpixel SP1 is located is provided with multiple light shielding portions 50. The light shielding portions 50 may include multiple openings 60, wherein the orthographic projections of the multiple openings on the substrate at least partially overlap with the orthographic projection of the first subpixel SP1 on the substrate. By adjusting the shape of the light shielding portion openings, the first subpixel SP1 can have a smaller field of view, such as a first field of view angle α1, thereby driving the first subpixel SP1 to display, thereby achieving anti-peeping display. No light shielding portion is provided above the region where the second subpixel SP2 is located, so the second subpixel SP2 has a larger field of view, such as a second field of view angle α2, where the first field of view angle α1 is smaller than the second field of view angle α2. The pixel circuit 30 can be electrically connected to both the first subpixel SP1 and the second subpixel SP2. The pixel circuit 30 can selectively drive the first subpixel SP1 or the second subpixel SP2 to illuminate, thereby achieving different display modes.

[0061] The pixel circuit 30 may include multiple transistors (such as thin film transistors TFT) and at least one capacitor Cst. For example, the pixel circuit 30 may be a "11T1C" circuit or a "12T1C" circuit, where "T" refers to a thin film transistor and the number before "T" refers to the number of thin film transistors; "C" refers to a capacitor and the number before "C" refers to the number of capacitors.

[0062] For example, in some embodiments of the present disclosure, the field of view angle of the sub-pixel can also be adjusted by the structural design of the light-emitting element. For example, the field of view angle of the first sub-pixel SP1 can be adjusted by adjusting the size of the first electrode of the first light-emitting element L1 in the first sub-pixel SP1 (for example, the size of the anode). For example, the field of view angle of the second sub-pixel SP2 can be adjusted by adjusting the size of the first electrode of the second light-emitting element L2 in the second sub-pixel SP2 (for example, the size of the anode). By adjusting the size of the first electrodes of different light-emitting elements, the field of view angles of different sub-pixels can be regulated, so that different modes of display can be further achieved through pixel circuit control.

[0063] It should be noted that the arrangement of the light-emitting elements in the embodiments of the present disclosure can be an RGB strip arrangement, a "pink" arrangement, or a pixel-sharing arrangement, such as an RGBG arrangement. According to the embodiments of the present disclosure, the light-emitting elements in pixels of the same color, such as red pixels (R), blue pixels (B), or green pixels (G) in the related art, can be split into a first light-emitting element L1 and a second light-emitting element L2, so that the overall pixel arrangement remains unchanged.

[0064] It should be noted that the implementation of sub-pixels with different viewing angles in the present disclosure may adopt various design methods known in the art, such as light shielding layer design, privacy film design, etc. The present disclosure does not impose any limitation on this.

[0065] It should also be noted that the figure exemplarily shows that the orthographic projection of the pixel unit on the substrate is a rectangle, but the embodiments of the present disclosure are not limited to this. For example, the orthographic projection of the pixel unit on the substrate can be a hexagon, a pentagon, a square, a circle, or other shapes. Although in the illustrated embodiment, the first direction X and the second direction Y are perpendicular to each other, the embodiments of the present disclosure are not limited to this.

[0066] FIG3 is a schematic diagram showing connections between a pixel circuit and a pixel unit according to an embodiment of the present disclosure.

[0067] For example, in an embodiment of the present disclosure, referring to FIG3 , a pixel circuit 30 includes a driving circuit 31 and a switching circuit 32 for controlling the on or off of different pixel units. The pixel unit 20 includes a first sub-pixel SP1 and a second sub-pixel SP2. The first sub-pixel SP1 may include a first light-emitting element L1, and the second sub-pixel SP2 may include a second light-emitting element L2. The first light-emitting element L1 and the second light-emitting element L2 may emit light of a first wavelength, wherein the first wavelength may be red, green, or blue. The switching circuit 32 may include a first sub-pixel switching circuit 321 and a second sub-pixel switching circuit 322. The first sub-pixel switching circuit 321 may be electrically connected to the first light-emitting element L1. By controlling the switching of the first sub-pixel switching circuit 321, the driving circuit 31 and the first light-emitting element L1 may be controlled to be on or off, thereby controlling the first sub-pixel SP1 to be turned on or off. The second sub-pixel switching circuit 322 may be electrically connected to the second light-emitting element L2. By controlling the switching of the second sub-pixel switching circuit 322, the driving circuit 31 and the second light-emitting element L2 may be controlled to be on or off, thereby controlling the second sub-pixel SP2 to be turned on or off. The first sub-pixel switching circuit 321 and the second sub-pixel switching circuit 322 may share a single driving circuit 31, thereby reducing the complexity of the pixel circuit, facilitating a reduction in the number of transistors and wiring in the pixel circuit, and saving wiring space, thereby achieving a thinner and lighter display substrate with a narrower bezel.

[0068] FIG4 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG5 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0069] For example, in some embodiments of the present disclosure, referring to FIG4 , the pixel circuit 30 includes a driving circuit 31 and a switching circuit 32. The driving circuit 31 can be used to generate a driving current I and transmit the driving current I to a node where the driving circuit 31 and the switching circuit 32 are coupled. For example, the driving circuit 31 and the switching circuit 32 are coupled to a sixth node N6.

[0070] Exemplarily, the driving circuit 31 may include: a data writing sub-circuit 311, which is coupled to the data signal terminal Data, the scan signal terminal GT and the second node N2, and the data writing sub-circuit 311 is configured to write the data signal received at the data signal terminal Data into the second node N2 in response to the scan signal received at the scan signal terminal GT.

[0071] The driving circuit 31 may further include a driving sub-circuit 313 coupled to the voltage signal terminal VDD, the first node N1 and the third node N3 , and configured to generate a driving current I in response to the voltage of the first node N1 .

[0072] The driving circuit 31 may further include: a compensation sub-circuit 312, which is coupled to the scan signal terminal GT, the first node N1 and the third node N3, and the compensation sub-circuit 312 is configured to transmit the voltage signal from the voltage signal terminal VDD and the threshold voltage of the driving sub-circuit 313 to the first node N1 in response to the scan signal received at the scan signal terminal GT.

[0073] The driving circuit 31 may further include a storage sub-circuit 310 , the storage sub-circuit 310 is coupled between the first node N1 and the second node N2 , and the storage sub-circuit is configured to store a voltage.

[0074] For example, in some embodiments of the present disclosure, continuing to refer to Figure 4, the driving circuit 31 may also include: a first initialization sub-circuit 314, the first initialization sub-circuit 314 is coupled to the first initialization signal terminal Vi1, the reset signal terminal Re and the first node N1, and the first initialization sub-circuit 314 is configured to respond to the reset signal received at the reset signal terminal Re, and transmit the first initialization signal received at the first initialization signal terminal Vi1 to the first node N1 to initialize the potential of the first node N1.

[0075] Exemplarily, the driving circuit 31 may further include: a second initialization sub-circuit 315, the second initialization sub-circuit 315 is coupled to the reference voltage signal terminal Vref, the reset signal terminal Re and the second node N2, and the second initialization sub-circuit 315 is configured to transmit the reference voltage signal received at the reference voltage signal terminal Vref to the second node N2 in response to the reset signal received at the reset signal terminal Re.

[0076] Exemplarily, the driving circuit 31 may further include: a first light-emitting control sub-circuit 316, the first light-emitting control sub-circuit 316 is coupled to the reference voltage signal terminal Vref, the first light-emitting control signal terminal EM1 and the second node N2, and the first light-emitting control sub-circuit 316 is configured to transmit the reference voltage signal received at the reference voltage signal terminal Vref to the second node N2 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0077] Exemplarily, the driving circuit 31 may further include: an auxiliary sub-circuit 319, which is coupled to the first node N1 and the first light-emitting control signal terminal EM1, and the auxiliary sub-circuit 319 is configured to release the charge from the first node N1 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0078] Exemplarily, the auxiliary sub-circuit 319 also has a voltage stabilizing effect on the voltage at the first node N1.

[0079] Exemplarily, the driving circuit 31 may further include: a second light-emitting control sub-circuit 318, the second light-emitting control sub-circuit 318 is coupled to the first light-emitting control signal terminal EM1, the third node N3 and the sixth node N6, and the second light-emitting control sub-circuit 318 is configured to transmit the driving current I from the third node N3 to the sixth node N6 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0080] 4 , the switch circuit 32 may include a first sub-pixel switch circuit 321 and a second sub-pixel switch circuit 322. The first sub-pixel switch circuit 321 is coupled to the second emission control signal terminal EM2, the driver circuit 31, and the first electrode L11 of the first light-emitting element L1, respectively. The first sub-pixel switch circuit 321 is configured to control the connection between the driver circuit 31 and the first light-emitting element L1 in response to a second emission control signal provided by the second emission control signal terminal EM2. The second sub-pixel switch circuit 322 is coupled to the third emission control signal terminal EM3, the driver circuit 31, and the first electrode L21 of the second light-emitting element L2, respectively. The second sub-pixel switch circuit 322 is configured to control the connection between the driver circuit 31 and the second light-emitting element L2 in response to a third emission control signal provided by the third emission control signal terminal EM3.

[0081] For example, the first light-emitting element L1 can be a light-emitting element in a pixel unit for display in anti-peeping mode, and the second light-emitting element L2 can be a light-emitting element in a pixel unit for display in shared mode. Under the premise that the driving circuit 31 generates a driving current, different display modes can be achieved by regulating the switching states of the first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322. For example, when the driving circuit 31 generates a driving current I and transmits the driving current I to the coupling node between the driving circuit 31 and the switch circuit 32, the first sub-pixel switch circuit 321 can be controlled to be turned on and the second sub-pixel switch circuit 322 can be controlled to be turned off, thereby illuminating the first light-emitting element L1 and achieving display in anti-peeping mode; the first sub-pixel switch circuit 321 can also be controlled to be turned off and the second sub-pixel switch circuit 322 can be controlled to be turned on, thereby achieving display in shared mode.

[0082] For example, in some embodiments of the present disclosure, the first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can be controlled to be closed at the same time, so that the corresponding display unit does not display content; the first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can be controlled to be opened at the same time, so that the corresponding display unit can be controlled to display in another shared mode, in which the first light-emitting element L1 and the second light-emitting element L2 are lit at the same time, the display light-emitting area accounts for a higher proportion, the display brightness is higher, and the display effect is better.

[0083] For example, continuing to refer to Figure 4, the first sub-pixel switch circuit 321 and the first electrode L11 of the first light-emitting element L1 are coupled to the fourth node N4; the switch circuit 32 may also include a third initialization sub-circuit 323, and the third initialization sub-circuit 323 is coupled to the reset signal terminal Re, the fourth node N4 and the initialization signal terminal Vi. The third initialization sub-circuit 323 is configured to respond to the reset signal received at the reset signal terminal Re, and transmit the initialization signal received at the initialization signal terminal Vi to the fourth node N4 to initialize the potential of the fourth node N4.

[0084] Exemplarily, the initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 or the second initialization signal terminal Vi2.

[0085] The initialization signals in the first initialization signal terminal Vi1 and the second initialization signal terminal Vi2 may be the same or different, and the present disclosure does not impose any specific limitation on this.

[0086] It should be understood that in the pixel circuit provided in the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, the fourth node N4, the fifth node N5 and the sixth node N6 do not necessarily represent actual existing components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. That is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0087] For example, in some embodiments of the present disclosure, in combination with Figures 4 and 5, in the driving circuit 31, the data writing sub-circuit 311 includes a data writing transistor T1, the driving sub-circuit 313 includes a driving transistor T3, the compensation sub-circuit 312 includes a compensation transistor T2, the storage sub-circuit 310 includes a storage capacitor C1, the first initialization sub-circuit 314 includes a first initialization transistor T4, the second initialization sub-circuit 315 includes a second initialization transistor T5, the first light-emitting control sub-circuit 316 includes a first light-emitting control transistor T6, the auxiliary sub-circuit 319 includes an auxiliary transistor T9, and the second light-emitting control sub-circuit 318 includes a second light-emitting control transistor T8.

[0088] It should be noted that each transistor includes a control electrode of the transistor, that is, a gate; a first electrode of the transistor, that is, one of a source or a drain; and a second electrode of the transistor, that is, the other of the source or the drain.

[0089] The control electrode of the data writing transistor T1 is electrically connected to the scan signal terminal GT, the first electrode of the data writing transistor T1 is electrically connected to the data signal terminal Data, and the second electrode of the data writing transistor T1 is electrically connected to the second node N2.

[0090] A control electrode of the driving transistor T3 is electrically connected to the first node N1 , a first electrode of the driving transistor T3 is electrically connected to the voltage signal terminal VDD, and a second electrode of the driving transistor T3 is electrically connected to the third node N3 .

[0091] A control electrode of the compensation transistor T2 is electrically connected to the scan signal terminal GT, a first electrode of the compensation transistor T2 is electrically connected to the first node N1, and a second electrode of the compensation transistor T2 is electrically connected to the third node N3.

[0092] The storage capacitor C1 includes a first plate C1a and a second plate C1b. The first plate C1a is electrically connected to the first node N1, and the second plate C1b is electrically connected to the second node N2.

[0093] A control electrode of the first initialization transistor T4 is electrically connected to the reset signal terminal Re, a first electrode of the first initialization transistor T4 is electrically connected to the first node N1, and a second electrode of the first initialization transistor T4 is electrically connected to the first initialization signal terminal Vi1.

[0094] A control electrode of the second initialization transistor T5 is electrically connected to the reset signal terminal Re, a first electrode of the second initialization transistor T5 is electrically connected to the second node N2, and a second electrode of the second initialization transistor T5 is electrically connected to the reference voltage signal terminal Vref.

[0095] The control electrode of the first light emitting control transistor T6 is electrically connected to the first light emitting control signal terminal EM1, the first electrode of the first light emitting control transistor T6 is electrically connected to the second node N2, and the second electrode of the first light emitting control transistor T6 is electrically connected to the reference voltage signal terminal Vref.

[0096] The control electrode of the auxiliary transistor T9 is electrically connected to the first light emitting control signal terminal EM1, the first electrode of the auxiliary transistor T9 is electrically connected to the first node N1, and the second electrode of the auxiliary transistor T9 is suspended. The second electrode of the auxiliary transistor T9 is suspended to release the charge from the first node N1.

[0097] Exemplarily, the auxiliary sub-circuit 319 also has a voltage stabilizing effect on the voltage at the first node N1.

[0098] The control electrode of the second light-emitting control transistor T8 is electrically connected to the first light-emitting control signal terminal EM1, the first electrode of the second light-emitting control transistor T8 is electrically connected to the third node N3, and the second electrode of the second light-emitting control transistor T8 is electrically connected to the sixth node N6. The driving current generated by the driving transistor flows through the third node N3. The second light-emitting control transistor T8 is disposed between the third node N3 and the switch circuit 32. The switch circuit 32 can be uniformly controlled by controlling the second light-emitting control transistor T8 to be on or off. For example, when both the first light-emitting element L1 and the second light-emitting element L2 are not displaying, the second light-emitting control transistor T8 can be controlled to be off, so that the driving current does not flow into the switch circuit 32, and thus both the first light-emitting element L1 and the second light-emitting element L2 do not emit light.

[0099] For example, in some embodiments of the present disclosure, continuing to refer to Figure 5, in the switching circuit, the first sub-pixel switching circuit 321 includes a first sub-pixel switching transistor T10, the second sub-pixel switching circuit 322 includes a second sub-pixel switching transistor T11, and the third initialization sub-circuit 323 includes a third initialization transistor T7.

[0100] The control electrode of the first sub-pixel switch transistor T10 is electrically connected to the second light-emitting control signal terminal EM2, the first electrode of the first sub-pixel switch transistor T10 is electrically connected to the sixth node N6, and the second electrode of the first sub-pixel switch transistor T10 and the first electrode L11 of the first light-emitting element L1 are coupled to the fourth node N4.

[0101] The control electrode of the second sub-pixel switch transistor T11 is electrically connected to the third light-emitting control signal terminal EM3, the first electrode of the second sub-pixel switch transistor T11 is electrically connected to the sixth node N6, and the second electrode of the second sub-pixel switch transistor T11 and the first electrode L21 of the second light-emitting element L2 are coupled to the fifth node N5.

[0102] A control electrode of the third initialization transistor T7 is electrically connected to the reset signal terminal Re, a first electrode of the third initialization transistor T7 is coupled to the first electrode L11 of the first light-emitting element L1 at the fourth node N4, and a second electrode of the third initialization transistor T7 is electrically connected to the initialization signal terminal Vi. The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 or the second initialization signal terminal Vi2.

[0103] Exemplarily, the operation of the pixel circuit 30 may include a reset phase, a write phase, and a light emitting phase.

[0104] In the reset stage, the reset signal terminal Re controls the first initialization transistor T4, the second initialization transistor T5 and the third initialization transistor T7 to be turned on, respectively resetting the control electrode of the driving transistor (the first node N1), the second plate C1b of the storage capacitor (the second node N2) and the first electrode L11 of the first light-emitting element (the fourth node N4).

[0105] During the writing phase, the scanning signal terminal GT controls the data writing transistor T1 and the compensation transistor T2 to be turned on, compensating the potential of the driving transistor T3 so that the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD+Vth, and the potential of the second plate C1b of the storage capacitor reaches Vdata.

[0106] During the light-emitting phase, the first light-emitting control signal terminal EM1 controls the first light-emitting control transistor T6, the second light-emitting control transistor T8, and the auxiliary transistor T9 to be turned on. Due to the coupling effect of the capacitor, the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD + Vth + Vdata - Vref, and the gate-source voltage Vgs of the driving transistor T3 is Vth + Vdata - Vref. The driving transistor T3 generates a driving current I, which satisfies the following formula: I = 1 / 2·K·(Vgs-Vth) 2 =1 / 2·K·(Vdata-Vref) 2

[0107] Wherein, K is a fixed constant related to the process parameters and geometric dimensions of the driver sub-circuit 313. Vgs is the gate-source voltage difference of the driver transistor in the driver sub-circuit 313.

[0108] The driving current I generated by the driving transistor T3 can flow through the sixth node coupled between the driving circuit 31 and the switching circuit 32. At this time, the second light-emitting control signal terminal EM2 can be used to control the first sub-pixel switching transistor T10 to turn on, thereby outputting the driving current to the first light-emitting element L1, thereby controlling the first light-emitting element L1 to illuminate, thereby achieving display in anti-peeping mode; alternatively, the third light-emitting control signal terminal EM3 can be used to control the second sub-pixel switching transistor T11 to turn on, thereby outputting the driving current to the second light-emitting element L2, thereby controlling the second light-emitting element L2 to illuminate, thereby achieving display in sharing mode.

[0109] The first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can share a driving circuit 31, thereby reducing the complexity of the pixel circuit, which is beneficial to reducing the number of transistors and the number of wirings in the pixel circuit, and is beneficial to saving wiring space, thereby achieving a thinner and narrower frame of the display substrate.

[0110] FIG6 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG7 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0111] For example, in some embodiments of the present disclosure, referring to Figure 6, the pixel circuit includes a driving circuit 31 and a switching circuit 32. The driving circuit 31 can be used to generate a driving current and transmit the driving current to a node where the driving circuit 31 and the switching circuit 32 are coupled. For example, the driving circuit 31 and the switching circuit 32 are coupled at a sixth node.

[0112] Exemplarily, the driving circuit 31 may include: a data writing sub-circuit 311 , wherein the data writing sub-circuit 311 is coupled to the data signal terminal Data, the scan signal terminal GT, and the second node N2 .

[0113] The driving circuit 31 may further include a driving sub-circuit 313 , which is coupled to the voltage signal terminal VDD, the first node N1 , and the third node N3 .

[0114] The driving circuit 31 may further include a compensation sub-circuit 312 , which is coupled to the scan signal terminal GT, the first node N1 , and the third node N3 .

[0115] The driving circuit 31 may further include a storage sub-circuit 310 , which is coupled between the first node N1 and the second node N2 .

[0116] The driving circuit 31 may further include a first initialization sub-circuit 314 , which is coupled to the first initialization signal terminal Vi1 , the reset signal terminal Re, and the first node N1 .

[0117] The driving circuit 31 may further include: a second initialization sub-circuit 315 , wherein the second initialization sub-circuit 315 is coupled to the reference voltage signal terminal Vref, the reset signal terminal Re, and the second node N2 .

[0118] The driving circuit 31 may further include a first light emitting control sub-circuit 316 , which is coupled to the reference voltage signal terminal Vref, the first light emitting control signal terminal EM1 , and the second node N2 .

[0119] The driving circuit 31 may further include: an auxiliary sub-circuit 319, which is coupled to the first node N1 and the first light-emitting control signal terminal EM1, and the auxiliary sub-circuit 319 is configured to release the charge from the first node N1 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0120] Exemplarily, the auxiliary sub-circuit 319 also has a voltage stabilizing effect on the voltage at the first node N1.

[0121] Exemplarily, the driving circuit 31 may further include: a second light-emitting control sub-circuit 318, the second light-emitting control sub-circuit 318 is coupled to the first light-emitting control signal terminal EM1, the third node N3 and the sixth node N6, and the second light-emitting control sub-circuit 318 is configured to transmit the driving current I from the third node N3 to the sixth node N6 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0122] In the driving circuit, the data writing sub-circuit 311 includes a data writing transistor T1, the driving sub-circuit 313 includes a driving transistor T3, the compensation sub-circuit 312 includes a compensation transistor T2, the storage sub-circuit 310 includes a storage capacitor C1, the first initialization sub-circuit 314 includes a first initialization transistor T4, the second initialization sub-circuit 315 includes a second initialization transistor T5, the first light-emission control sub-circuit 316 includes a first light-emission control transistor T6, the auxiliary sub-circuit 319 includes an auxiliary transistor T9, and the second light-emission control sub-circuit 318 includes a second light-emission control transistor T8. The connection method of each transistor in the driving circuit of the above embodiment can be the same as the connection method of the corresponding transistor in the embodiment of FIG. 5 , and will not be repeated here.

[0123] 6 , the switch circuit 32 may include a first sub-pixel switch circuit 321 and a second sub-pixel switch circuit 322. The first sub-pixel switch circuit 321 is coupled to the second emission control signal terminal EM2, the driver circuit 31, and the first electrode L11 of the first light-emitting element L1, respectively. The first sub-pixel switch circuit 321 is configured to control the connection between the driver circuit 31 and the first light-emitting element L1 in response to a second emission control signal provided by the second emission control signal terminal EM2. The second sub-pixel switch circuit 322 is coupled to the third emission control signal terminal EM3, the driver circuit 31, and the first electrode L21 of the second light-emitting element L2, respectively. The second sub-pixel switch circuit 322 is configured to control the connection between the driver circuit 31 and the second light-emitting element L2 in response to a third emission control signal provided by the third emission control signal terminal EM3.

[0124] 6 , the first sub-pixel switch circuit 321 and the first electrode L11 of the first light emitting element L1 are coupled to the fourth node N4 ; the second sub-pixel switch circuit 322 and the first electrode L21 of the second light emitting element L2 are coupled to the fifth node N5 .

[0125] The switch circuit 32 may further include a third initialization sub-circuit 323 and a fourth initialization sub-circuit 324. The third initialization sub-circuit 323 is coupled to the reset signal terminal Re, the fourth node N4, and the initialization signal terminal Vi. The third initialization sub-circuit 323 is configured to transmit the initialization signal received at the initialization signal terminal Vi to the fourth node N4 in response to the reset signal received at the reset signal terminal Re, thereby initializing the potential of the fourth node N4. The fourth initialization sub-circuit 324 is coupled to the reset signal terminal Re, the fifth node N5, and the initialization signal terminal Vi. The fourth initialization sub-circuit 324 is configured to transmit the initialization signal received at the initialization signal terminal Vi to the fifth node N5 in response to the reset signal received at the reset signal terminal Re, thereby initializing the potential of the fifth node N5. The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 or the second initialization signal terminal Vi2.

[0126] By configuring initialization circuits on the first electrode L11 of the first light-emitting element and the first electrode L21 of the second light-emitting element, the first electrode L11 of the first light-emitting element and the first electrode L21 of the second light-emitting element can be initialized, thereby eliminating residual charges in the previous light-emitting stage and achieving better light-emitting control effects.

[0127] For example, in an embodiment of the present disclosure, referring to FIG7 , in the switching circuit, the first sub-pixel switching circuit 321 includes a first sub-pixel switching transistor T10, the second sub-pixel switching circuit 322 includes a second sub-pixel switching transistor T11, the third initialization sub-circuit 323 includes a third initialization transistor T7, and the fourth initialization sub-circuit 324 includes a fourth initialization transistor T12.

[0128] The control electrode of the first sub-pixel switch transistor T10 is electrically connected to the second light-emitting control signal terminal EM2, the first electrode of the first sub-pixel switch transistor T10 is electrically connected to the sixth node N6, and the second electrode of the first sub-pixel switch transistor T10 and the first electrode L11 of the first light-emitting element L1 are coupled to the fourth node N4.

[0129] The control electrode of the second sub-pixel switch transistor T11 is electrically connected to the third light-emitting control signal terminal EM3, the first electrode of the second sub-pixel switch transistor T11 is electrically connected to the sixth node N6, and the second electrode of the second sub-pixel switch transistor T11 and the first electrode L21 of the second light-emitting element L2 are coupled to the fifth node N5.

[0130] A control electrode of the third initialization transistor T7 is electrically connected to the reset signal terminal Re, a first electrode of the third initialization transistor T7 and the first electrode L11 of the first light emitting element L1 are coupled to the fourth node N4, and a second electrode of the third initialization transistor T7 is electrically connected to the initialization signal terminal Vi.

[0131] A control electrode of the fourth initialization transistor T12 is electrically connected to the reset signal terminal Re, a first electrode of the fourth initialization transistor T12 and the first electrode L21 of the second light emitting element L2 are coupled to the fifth node N5, and a second electrode of the fourth initialization transistor T12 is electrically connected to the initialization signal terminal Vi.

[0132] The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 and the second initialization signal terminal Vi2.

[0133] Exemplarily, the operation of the pixel circuit 30 may include a reset phase, a write phase, and a light emitting phase.

[0134] In the reset stage, the reset signal terminal Re controls the first initialization transistor T4, the second initialization transistor T5, the third initialization transistor T7 and the fourth initialization transistor T12 to be turned on, and respectively resets the control electrode of the driving transistor (the first node N1) and the second plate C1b of the storage capacitor (the second node N2), the first electrode L11 of the first light-emitting element (the fourth node N4) and the first electrode L21 of the second light-emitting element (the fifth node N5).

[0135] During the writing phase, the scanning signal terminal GT controls the data writing transistor T1 and the compensation transistor T2 to be turned on, compensating the potential of the driving transistor T3 so that the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD+Vth, and the potential of the second plate C1b of the storage capacitor reaches Vdata.

[0136] In the light-emitting stage, the first light-emitting control signal terminal controls the first light-emitting control transistor T6, the second light-emitting control transistor T8 and the auxiliary transistor T9 to be turned on. Due to the coupling effect of the capacitor, the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD+Vth+Vdata-Vref, and the gate-source voltage Vgs of the driving transistor T3 is Vth+Vdata-Vref. The driving transistor T3 generates a driving current I, and the driving current flows through the sixth node N6.

[0137] At this time, by controlling the first sub-pixel switch transistor T10 to turn on through the second light-emitting control signal terminal EM2, the driving current can be output to the first light-emitting element L1, and the first light-emitting element can be controlled to light up, thereby realizing the display of the anti-peeping mode; or, by controlling the second sub-pixel switch transistor T11 to turn on through the third light-emitting control signal terminal EM3, the driving current can be output to the second light-emitting element L2, and the second light-emitting element can be controlled to light up, thereby realizing the display of the shared mode.

[0138] The first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can share a driving circuit 31, thereby reducing the complexity of the pixel circuit, which is beneficial to reducing the number of transistors and the number of wirings in the pixel circuit, and is beneficial to saving wiring space, thereby achieving a thinner and narrower frame of the display substrate.

[0139] FIG8 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG9 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0140] For example, in some embodiments of the present disclosure, referring to Figure 8, the pixel circuit includes a driving circuit 31 and a switching circuit 32. The driving circuit 31 can be used to generate a driving current and transmit the driving current to a node where the driving circuit 31 and the switching circuit 32 are coupled. For example, the driving circuit 31 and the switching circuit 32 are coupled to a third node N3.

[0141] Exemplarily, the driving circuit 31 may include: a data writing sub-circuit 311 , wherein the data writing sub-circuit 311 is coupled to the data signal terminal Data, the scan signal terminal GT, and the second node N2 .

[0142] The driving circuit 31 may further include a driving sub-circuit 313 , which is coupled to the voltage signal terminal VDD, the first node N1 , and the third node N3 .

[0143] The driving circuit 31 may further include a compensation sub-circuit 312 , which is coupled to the scan signal terminal GT, the first node N1 , and the third node N3 .

[0144] The driving circuit 31 may further include a storage sub-circuit 310 , which is coupled between the first node N1 and the second node N2 .

[0145] The driving circuit 31 may further include a first initialization sub-circuit 314 , which is coupled to the first initialization signal terminal Vi1 , the reset signal terminal Re, and the first node N1 .

[0146] The driving circuit 31 may further include: a second initialization sub-circuit 315 , wherein the second initialization sub-circuit 315 is coupled to the reference voltage signal terminal Vref, the reset signal terminal Re, and the second node N2 .

[0147] The driving circuit 31 may further include a first light emitting control sub-circuit 316 , which is coupled to the reference voltage signal terminal Vref, the first light emitting control signal terminal EM1 , and the second node N2 .

[0148] Exemplarily, the driving circuit 31 may further include: an auxiliary sub-circuit 319, which is coupled to the first node N1 and the first light-emitting control signal terminal EM1, and the auxiliary sub-circuit 319 is configured to release the charge from the first node N1 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0149] Exemplarily, the auxiliary sub-circuit 319 also has a voltage stabilizing effect on the voltage at the first node N1.

[0150] In the driving circuit, the data writing sub-circuit 311 includes a data writing transistor T1, the driving sub-circuit 313 includes a driving transistor T3, the compensation sub-circuit 312 includes a compensation transistor T2, the storage sub-circuit 310 includes a storage capacitor C1, the first initialization sub-circuit 314 includes a first initialization transistor T4, the second initialization sub-circuit 315 includes a second initialization transistor T5, the first light emission control sub-circuit 316 includes a first light emission control transistor T6, and the auxiliary sub-circuit 319 includes an auxiliary transistor T9. The connection method of the data writing transistor T1, the driving transistor T3, the compensation transistor T2, the storage capacitor C1, the first initialization transistor T4, the second initialization transistor T5, the first light emission control transistor T6, and the auxiliary transistor T9 in the driving circuit of the above embodiment can be the same as the connection method of the corresponding transistors in the embodiment of FIG. Such details will not be repeated here.

[0151] For example, in some embodiments of the present disclosure, the second light-emitting control subcircuit can be omitted from the driver circuit 31. The on-off switching between the driver circuit 31 and the first light-emitting element L1, and between the driver circuit 31 and the second light-emitting element L2, can be controlled solely by the first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 in the switch circuit 32, thereby achieving display in an anti-peeping mode or a shared mode. By omitting the second light-emitting control subcircuit, the number of transistors can be reduced. For example, the second light-emitting control transistor T8 can be eliminated, which helps reduce the number of wiring, saves space occupied by the driver circuit, and facilitates the realization of a narrow-frame display.

[0152] By way of example, with continued reference to FIG8 , the switch circuit 32 may include a first sub-pixel switch circuit 321 and a second sub-pixel switch circuit 322. The first sub-pixel switch circuit 321 is coupled to the second emission control signal terminal EM2, the driver circuit 31, and the first electrode L11 of the first light-emitting element L1, respectively. The first sub-pixel switch circuit 321 is configured to control the connection between the driver circuit 31 and the first light-emitting element L1 in response to a second emission control signal provided by the second emission control signal terminal EM2. The second sub-pixel switch circuit 322 is coupled to the third emission control signal terminal EM3, the driver circuit 31, and the first electrode L21 of the second light-emitting element L2, respectively. The second sub-pixel switch circuit 322 is configured to control the connection between the driver circuit 31 and the second light-emitting element L2 in response to a third emission control signal provided by the third emission control signal terminal EM3.

[0153] 8 , the first sub-pixel switch circuit 321 and the first electrode L11 of the first light emitting element L1 are coupled to the fourth node N4 ; the second sub-pixel switch circuit 322 and the first electrode L21 of the second light emitting element L2 are coupled to the fifth node N5 .

[0154] The switch circuit 32 may further include a third initialization sub-circuit 323 and a fourth initialization sub-circuit 324. The third initialization sub-circuit 323 is coupled to the reset signal terminal Re, the fourth node N4, and the initialization signal terminal Vi. The third initialization sub-circuit 323 is configured to transmit the initialization signal received at the initialization signal terminal Vi to the fourth node N4 in response to the reset signal received at the reset signal terminal Re, thereby initializing the potential of the fourth node N4. The fourth initialization sub-circuit 324 is coupled to the reset signal terminal Re, the fifth node N5, and the initialization signal terminal Vi. The fourth initialization sub-circuit 324 is configured to transmit the initialization signal received at the initialization signal terminal Vi to the fifth node N5 in response to the reset signal received at the reset signal terminal Re, thereby initializing the potential of the fifth node N5. The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 or the second initialization signal terminal Vi2.

[0155] By configuring initialization circuits on the first electrode L11 of the first light-emitting element and the first electrode L21 of the second light-emitting element, the first electrode L11 of the first light-emitting element and the first electrode L21 of the second light-emitting element can be initialized, thereby eliminating residual charges in the previous light-emitting stage and achieving better light-emitting control effects.

[0156] For example, the driving circuit 31 and the switching circuit 32 are coupled to a third node. The first sub-pixel switching circuit 321 and the second sub-pixel switching circuit 322 are both coupled to the switching circuit 32 at the third node. Therefore, the driving current transmitted to the third node can be controlled by turning on and off the first sub-pixel switching circuit 321 and the second sub-pixel switching circuit 322 to select a corresponding transmission path, thereby controlling the first light-emitting element L1 and the second light-emitting element L2 to light up or not.

[0157] For example, in an embodiment of the present disclosure, referring to FIG9 , in the switching circuit, the first sub-pixel switching circuit 321 includes a first sub-pixel switching transistor T10, the second sub-pixel switching circuit 322 includes a second sub-pixel switching transistor T11, the third initialization sub-circuit 323 includes a third initialization transistor T7, and the fourth initialization sub-circuit 324 includes a fourth initialization transistor T12.

[0158] The control electrode of the first sub-pixel switch transistor T10 is electrically connected to the second light-emitting control signal terminal EM2, the first electrode of the first sub-pixel switch transistor T10 is electrically connected to the third node N3, and the second electrode of the first sub-pixel switch transistor T10 and the first electrode L11 of the first light-emitting element L1 are coupled to the fourth node N4.

[0159] The control electrode of the second sub-pixel switch transistor T11 is electrically connected to the third light-emitting control signal terminal EM3, the first electrode of the second sub-pixel switch transistor T11 is electrically connected to the third node N3, and the second electrode of the second sub-pixel switch transistor T11 and the first electrode L21 of the second light-emitting element L2 are coupled to the fifth node N5.

[0160] A control electrode of the third initialization transistor T7 is electrically connected to the reset signal terminal Re, a first electrode of the third initialization transistor T7 and the first electrode L11 of the first light emitting element L1 are coupled to the fourth node N4, and a second electrode of the third initialization transistor T7 is electrically connected to the initialization signal terminal Vi.

[0161] A control electrode of the fourth initialization transistor T12 is electrically connected to the reset signal terminal Re, a first electrode of the fourth initialization transistor T12 and the first electrode L21 of the second light emitting element L2 are coupled to the fifth node N5, and a second electrode of the fourth initialization transistor T12 is electrically connected to the initialization signal terminal Vi.

[0162] The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 and the second initialization signal terminal Vi2.

[0163] Exemplarily, the operation of the pixel circuit 30 may include a reset phase, a write phase, and a light emitting phase.

[0164] In the reset stage, the reset signal terminal Re controls the first initialization transistor T4, the second initialization transistor T5, the third initialization transistor T7 and the fourth initialization transistor T12 to be turned on, and respectively resets the control electrode (first node N1) of the driving transistor and the second plate C1b (second node N2) of the storage capacitor, the first electrode L11 (fourth node N4) of the first light-emitting element and the first electrode L21 (fifth node N5) of the second light-emitting element.

[0165] During the writing phase, the scanning signal terminal GT controls the data writing transistor T1 and the compensation transistor T2 to be turned on, compensating the potential of the driving transistor T3 so that the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD+Vth, and the potential of the second plate C1b of the storage capacitor reaches Vdata.

[0166] In the light-emitting stage, the first light-emitting control signal terminal controls the first light-emitting control transistor T6 and the auxiliary transistor T9 to be turned on. Due to the coupling effect of the capacitor, the potential of the control electrode (first node N1) of the driving transistor T3 reaches VDD+Vth+Vdata-Vref, and the gate-source voltage Vgs of the driving transistor T3 is Vth+Vdata-Vref. The driving transistor T3 generates a driving current, and the driving current flows through the third node N3.

[0167] At this time, by controlling the first sub-pixel switch transistor T10 to turn on through the second light-emitting control signal terminal EM2, the driving current can be output to the first light-emitting element L1, and the first light-emitting element can be controlled to light up, thereby realizing the display of the anti-peeping mode; or, by controlling the second sub-pixel switch transistor T11 to turn on through the third light-emitting control signal terminal EM3, the driving current can be output to the second light-emitting element L2, and the second light-emitting element can be controlled to light up, thereby realizing the display of the shared mode.

[0168] The first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can share a driving circuit 31, thereby reducing the complexity of the pixel circuit, which is beneficial to reducing the number of transistors and the number of wirings in the pixel circuit, and is beneficial to saving wiring space, thereby achieving a thinner and narrower frame of the display substrate.

[0169] FIG10 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure; FIG11 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure.

[0170] For example, in some embodiments of the present disclosure, referring to Figure 10, the pixel circuit includes a driving circuit 31 and a switching circuit 32. The driving circuit 31 can be used to generate a driving current and transmit the driving current to a node where the driving circuit 31 and the switching circuit 32 are coupled. For example, the driving circuit 31 and the switching circuit 32 are coupled to a fourth node N4.

[0171] Exemplarily, the driving circuit 31 may include: a data writing sub-circuit 311 , wherein the data writing sub-circuit 311 is coupled to the data signal terminal Data, the scan signal terminal GT, and the second node N2 .

[0172] The driving circuit 31 may further include a driving sub-circuit 313 , which is coupled to the voltage signal terminal VDD, the first node N1 , and the third node N3 .

[0173] The driving circuit 31 may further include a compensation sub-circuit 312 , which is coupled to the scan signal terminal GT, the first node N1 , and the third node N3 .

[0174] The driving circuit 31 may further include a storage sub-circuit 310 , which is coupled between the first node N1 and the second node N2 .

[0175] The driving circuit 31 may further include a first initialization sub-circuit 314 , which is coupled to the first initialization signal terminal Vi1 , the reset signal terminal Re, and the first node N1 .

[0176] The driving circuit 31 may further include: a second initialization sub-circuit 315 , wherein the second initialization sub-circuit 315 is coupled to the reference voltage signal terminal Vref, the reset signal terminal Re, and the second node N2 .

[0177] The driving circuit 31 may further include a first light emitting control sub-circuit 316 , which is coupled to the reference voltage signal terminal Vref, the first light emitting control signal terminal EM1 , and the second node N2 .

[0178] Exemplarily, the driving circuit 31 may further include: an auxiliary sub-circuit 319, which is coupled to the first node N1 and the first light-emitting control signal terminal EM1, and the auxiliary sub-circuit 319 is configured to release the charge from the first node N1 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0179] Exemplarily, the auxiliary sub-circuit 319 also has a voltage stabilizing effect on the voltage at the first node N1.

[0180] Exemplarily, the driving circuit 31 may further include: a second light-emitting control sub-circuit 318, which is coupled to the first light-emitting control signal terminal EM1, the third node N3 and the fourth node N4, and the second light-emitting control sub-circuit 318 is configured to transmit the driving current from the third node N3 to the fourth node N4 in response to the first light-emitting control signal received at the first light-emitting control signal terminal EM1.

[0181] In the driving circuit, the data writing sub-circuit 311 includes a data writing transistor T1, the driving sub-circuit 313 includes a driving transistor T3, the compensation sub-circuit 312 includes a compensation transistor T2, the storage sub-circuit 310 includes a storage capacitor C1, the first initialization sub-circuit 314 includes a first initialization transistor T4, the second initialization sub-circuit 315 includes a second initialization transistor T5, the first light-emitting control sub-circuit 316 includes a first light-emitting control transistor T6, and the auxiliary sub-circuit 319 includes an auxiliary transistor T9. The connection method of the multiple transistors in the driving circuit of the above embodiment can be the same as the connection method of the corresponding transistors in the embodiment of Figure 5 above, and will not be repeated here.

[0182] For example, in the driving circuit, the second emission control subcircuit 318 includes a second emission control transistor T8, wherein a control electrode of the second emission control transistor T8 is electrically connected to the first emission control signal terminal EM1, a first electrode of the second emission control transistor T8 is electrically connected to the third node N3, and a second electrode of the second emission control transistor T8 is electrically connected to the fourth node N4. The second emission control transistor T8 can be controlled to be on to selectively transmit the drive current to the fourth node N4; alternatively, the second emission control transistor T8 can be controlled to be off to prevent the drive current from being transmitted to the fourth node N4.

[0183] For example, with continued reference to FIG. 10 , the switch circuit 32 may include a first sub-pixel switch circuit 321 and a second sub-pixel switch circuit 322. The first sub-pixel switch circuit 321 is coupled to the second emission control signal terminal EM2, the first electrode L11 of the first light-emitting element L1, and the second electrode L12 of the first light-emitting element L1, respectively. The first sub-pixel switch circuit 321 is configured to short-circuit the first light-emitting element L1 in response to the second emission control signal provided at the second emission control signal terminal EM2. The first electrode L11 of the first light-emitting element, the first sub-pixel switch circuit 321, and the driver circuit 31 are coupled to a fourth node N4. In other words, after the drive current generated by the driver circuit flows through the fourth node N4, the first sub-pixel switch circuit 321 can be controlled to turn on, causing the first light-emitting element L1 to be short-circuited and thus not emit light.

[0184] In this embodiment, the second sub-pixel switch circuit 322 is coupled to the third light-emitting control signal terminal EM3, the first electrode L21 of the second light-emitting element L2, and the second electrode L22 of the second light-emitting element L2, respectively. The second sub-pixel switch circuit 322 is configured to short-circuit the second light-emitting element L2 in response to the third light-emitting control signal provided at the third light-emitting control signal terminal EM3. The second electrode L12 of the first light-emitting element L1, the first electrode L21 of the second light-emitting element L2, the first sub-pixel switch circuit 321, and the second sub-pixel switch circuit 322 are coupled to a fifth node N5.

[0185] For example, in an embodiment of the present disclosure, referring to FIG. 10 and FIG. 11 , in the switch circuit, the first sub-pixel switch circuit 321 includes a first sub-pixel switch transistor T10 , and the second sub-pixel switch circuit 322 includes a second sub-pixel switch transistor T11 .

[0186] The control electrode of the first sub-pixel switch transistor T10 is electrically connected to the second light-emitting control signal terminal EM2. The first electrode of the first sub-pixel switch transistor T10 and the first electrode L11 of the first light-emitting element L1 are coupled to a fourth node N4. The second electrode of the first sub-pixel switch transistor T10, the second electrode L12 of the first light-emitting element L1, the first electrode L21 of the second light-emitting element L2, and the first electrode of the second sub-pixel switch transistor T11 are coupled to a fifth node N5. The control electrode of the second sub-pixel switch transistor T11 is electrically connected to the third light-emitting control signal terminal EM3. The second electrode of the second sub-pixel switch transistor T11 is electrically connected to the second electrode L22 of the second light-emitting element L2. For example, the second electrode L22 of the second light-emitting element L2 can be electrically connected to the low-potential voltage signal terminal VSS.

[0187] For example, in some embodiments of the present disclosure, the first sub-pixel switch transistor T10 and the first light-emitting element L1 are connected in parallel, and the second sub-pixel switch transistor T11 and the second light-emitting element L2 are connected in parallel. By regulating the first sub-pixel switch transistor T10 and the second sub-pixel switch transistor T11, the first light-emitting element L1 and the second light-emitting element L2 can be controlled to light up or not. For example, when the driving circuit 31 generates a driving current I flowing through the fourth node N4, by controlling the first sub-pixel switch transistor T10 to turn on and the second sub-pixel switch transistor T11 to turn off, the first light-emitting element L1 is short-circuited by the first sub-pixel switch transistor T10, and the driving current I flows into the second light-emitting element L2 through the first sub-pixel switch transistor T10, thereby achieving the goal that the first light-emitting element L1 is not lit and the second light-emitting element L2 is lit; or, when the driving circuit 31 generates a driving current I flowing through the fourth node N4, by controlling the first sub-pixel switch transistor T10 to turn off and the second sub-pixel switch transistor T11 to turn on, the second light-emitting element L2 is short-circuited by the second sub-pixel switch transistor T11, and the driving current I flows through the first light-emitting element L1 and then flows into the second sub-pixel switch transistor T11, thereby achieving the goal that the first light-emitting element L1 is lit and the second light-emitting element L2 is not lit.

[0188] Exemplarily, the switch circuit 32 may further include a third initialization sub-circuit 323, which may include a third initialization transistor T7. A control electrode of the third initialization transistor T7 is electrically connected to the reset signal terminal Re, a first electrode of the third initialization transistor T7 is coupled to the first electrode L11 of the first light-emitting element L1 at the fourth node N4, and a second electrode of the third initialization transistor T7 is electrically connected to the initialization signal terminal Vi.

[0189] The initialization signal terminal Vi may include one of the first initialization signal terminal Vi1 and the second initialization signal terminal Vi2.

[0190] The first sub-pixel switch circuit 321 and the second sub-pixel switch circuit 322 can share a driving circuit 31, thereby reducing the complexity of the pixel circuit, which is beneficial to reducing the number of transistors and the number of wirings in the pixel circuit, and is beneficial to saving wiring space, thereby achieving a thinner and narrower frame of the display substrate.

[0191] For example, in an embodiment of the present disclosure, a display substrate 100 is provided. Referring to FIG. 1 to FIG. 3 , the display substrate 100 includes a base substrate 1, a pixel circuit 30 as described in any of the aforementioned embodiments disposed on the base substrate 1, wherein the pixel circuit 30 includes a driving circuit 31 and a switching circuit 32; and a plurality of pixel units 20 disposed on the base substrate 1, wherein at least one pixel unit 20 includes a first sub-pixel SP1 and a second sub-pixel SP2 disposed adjacent to each other, the first sub-pixel SP1 including a first light-emitting element L1, and the second sub-pixel SP2 including a second light-emitting element L2, wherein both the first light-emitting element L1 and the second light-emitting element L2 can emit light of a first wavelength, for example, the first wavelength can be one of red light, green light, blue light, or white light. The display substrate 100 may further include a light-shielding portion 50, which is arranged on a side of the pixel unit 20 away from the base substrate 1, wherein the light-shielding portion 50 may include a plurality of openings 60, and the orthographic projection of the openings 60 on the base substrate 1 at least partially overlaps with the orthographic projection of the first sub-pixel SP1 on the base substrate 1; the orthographic projection of the light-shielding portion 50 on the base substrate 1 does not overlap with the orthographic projection of the second sub-pixel SP2 on the base substrate 1, thereby making the field of view angle of the first sub-pixel SP1 smaller than the field of view angle of the second sub-pixel SP2.

[0192] The switching circuit 32 may include a first sub-pixel switching circuit 321 for controlling the on / off state of the first sub-pixel SP1, and a second sub-pixel switching circuit 322 for controlling the on / off state of the second sub-pixel SP2. The first sub-pixel switching circuit 321 and the second sub-pixel switching circuit 322 may share a single driver circuit 31, thereby reducing the complexity of the pixel circuit, the number of transistors and wiring in the pixel circuit, and saving wiring space, thereby achieving a thinner and lighter display substrate with a narrower frame.

[0193] Figure 12A is a schematic diagram showing the planar structure of the first conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 12B is a schematic diagram showing the planar structure of the second conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 12C is a schematic diagram showing the planar structure of the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 12D is a schematic diagram showing the planar structure of the combination of the first conductive layer and the first semiconductor layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 12E is a schematic diagram showing the planar structure of the third conductive layer and multiple vias according to an exemplary embodiment of the present disclosure; Figure 12F is a schematic diagram showing the planar structure of the fourth conductive layer and multiple vias of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 13 is a schematic diagram showing the planar structure of the combination of the first conductive layer, the second conductive layer, the first semiconductor layer, the third conductive layer and the fourth conductive layer of the pixel circuit according to an exemplary embodiment of the present disclosure; Figure 14 is a partial cross-sectional schematic diagram showing the pixel circuit according to an exemplary embodiment of the present disclosure taken along the center line BB' of Figure 13.

[0194] For example, in some embodiments of the present disclosure, with reference to FIG1-3 , a display substrate 100 includes: a base substrate 1; a plurality of pixel units 20 disposed on the base substrate 1, the plurality of pixel units 20 being arranged in an array along a first direction X and a second direction Y on the base substrate 1; and a plurality of pixel circuits 30 for driving the plurality of pixel units 20. At least one pixel unit 20 includes a first sub-pixel SP1 and a second sub-pixel SP2 disposed adjacent to each other, the first sub-pixel SP1 including a first light-emitting element L1, and the second sub-pixel SP2 including a second light-emitting element L2, wherein the first light-emitting element L1 and the second light-emitting element L2 both emit light of a first wavelength. The display substrate 100 also includes a light shielding portion 50 disposed on a side of the pixel unit 20 away from the base substrate 1, wherein the light shielding portion 50 includes a plurality of openings 60, wherein the orthographic projections of the plurality of openings 60 on the base substrate 1 at least partially overlap with the orthographic projections of the first sub-pixel SP1 on the base substrate 1; and the orthographic projections of the light shielding portion 50 on the base substrate 1 do not overlap with the orthographic projections of the second sub-pixel SP2 on the base substrate 1. Since a light shielding portion is provided above the first sub-pixel and no light shielding portion is provided above the second sub-pixel, the field of view angle of the first sub-pixel is smaller than the field of view angle of the second sub-pixel. The first sub-pixel can be used for display in anti-peep mode, and the second sub-pixel can be used for display in sharing mode.

[0195] Continuing with reference to Figure 3, the pixel circuit 30 includes a driving circuit 31 and a switching circuit 32. The switching circuit 32 includes: a first sub-pixel switching circuit 321, used to control the opening or closing of the first sub-pixel SP1; and a second sub-pixel switching circuit 322, used to control the opening or closing of the second sub-pixel SP2; the first sub-pixel switching circuit SP1 and the second sub-pixel switching circuit SP2 can share a driving circuit 31.

[0196] In this embodiment, referring to Figure 14, the display substrate 100 includes: a first conductive layer 2 arranged on a base substrate 1; a first semiconductor layer 3 arranged on a side of the first conductive layer 2 away from the base substrate 1; a second conductive layer 4 arranged on a side of the first semiconductor layer 3 away from the base substrate 1; a third conductive layer 5 arranged on a side of the second conductive layer 4 away from the base substrate 1; and a fourth conductive layer 6 arranged on a side of the third conductive layer 5 away from the base substrate 1.

[0197] Exemplarily, the display substrate may further include a fifth conductive layer, which is disposed on a side of the fourth conductive layer away from the base substrate 1 , and the first electrode L11 of the first light-emitting element and the first electrode L21 of the second light-emitting element may both be located in the fifth conductive layer.

[0198] The first sub-pixel switch circuit 321 may include a third light emitting control transistor T10 including a first electrode D10 and a second electrode S10. The first electrode D10 of the third light emitting control transistor T10 is electrically connected to the first electrode L11 of the first light emitting element through the first conductive transition portion m1.

[0199] The second sub-pixel switch circuit 322 may include a fourth light emitting control transistor T11 including a first electrode D11 and a second electrode S11. The first electrode D11 of the fourth light emitting control transistor T11 is electrically connected to the first electrode L21 of the second light emitting element through the second conductive transition portion m2.

[0200] Exemplarily, the driving circuit 31 may include a second light-emitting control subcircuit, the second light-emitting control subcircuit includes a second light-emitting control transistor T8, the second light-emitting control transistor T8 includes a first electrode D8, the second electrode S10 of the third light-emitting control transistor T10, the second electrode S11 of the fourth light-emitting control transistor T11 and the first electrode D8 of the second light-emitting control transistor T8 are electrically connected through a third conductive transition portion m3, and the first conductive transition portion ml, the second conductive transition portion m2 and the third conductive transition portion m3 are all located in the third conductive layer 5.

[0201] Exemplarily, the display substrate 100 may further include a reset signal line Re, a second light-emitting control signal line EM2, and a third light-emitting control signal line EM3 extending along the first direction X, wherein the reset signal line Re includes a reset signal first sub-line Re1, and the reset signal first sub-line Re1, the second light-emitting control signal line EM2, and the third light-emitting control signal line EM3 are all located in the second conductive layer 4.

[0202] The third light-emitting control transistor T10 also includes a third light-emitting control active layer ACT10 and a control electrode G10. The third light-emitting control active layer ACT10 is located in the first semiconductor layer 3. The orthographic projection of the third light-emitting control active layer ACT10 on the substrate at least partially overlaps with the orthographic projection of the second light-emitting control signal line EM2 on the substrate. The overlapping portion of the third light-emitting control active layer ACT10 and the second light-emitting control signal line EM2 is the control electrode G10 of the third light-emitting control transistor T10.

[0203] The fourth light-emitting control transistor T11 also includes a fourth light-emitting control active layer ACT11 and a control electrode G11. The fourth light-emitting control active layer ACT11 is located in the first semiconductor layer 3. The orthographic projection of the fourth light-emitting control active layer ACT11 on the substrate at least partially overlaps with the orthographic projection of the third light-emitting control signal line EM3 on the substrate. The overlapping portion of the fourth light-emitting control active layer ACT11 and the third light-emitting control signal line EM3 is the control electrode G11 of the third light-emitting control transistor T11.

[0204] The switching circuit also includes a third initialization sub-circuit, which includes a third initialization transistor T7. The third initialization transistor T7 includes a third initialization active layer ACT7, a control electrode G7, a first electrode D7 and a second electrode S7. The positive projection of the third initialization active layer ACT7 on the substrate at least partially overlaps with the positive projection of the reset signal first sub-line Re1 on the substrate. The overlapping part of the third initialization active layer ACT7 and the reset signal first sub-line Rel is the control electrode G7 of the third initialization transistor T7. The second electrode S7 of the third initialization transistor T7 is coupled to the first electrode L11 of the first light-emitting element at the fourth node N4 through the first conductive transition portion m1.

[0205] The display substrate further includes a second initialization signal line Vi2 extending along the second direction Y. The second initialization signal line is located in the fourth conductive layer 6. The first electrode D7 of the third initialization transistor T7 is electrically connected to the second initialization signal line Vi2 through the fourth conductive transition portion m4.

[0206] Illustratively, in some embodiments of the present disclosure, the display substrate 100 may further include a first initialization signal first sub-line Vi1-1, a reference voltage signal first sub-line Vref1, and a voltage signal first sub-line VDD1 extending along the first direction X, wherein the first initialization signal first sub-line Vi1-1 and the reference voltage signal first sub-line Vrefl are located in the second conductive layer 4, and the voltage signal first sub-line VDD1 is located in the third conductive layer 5; the display substrate 100 may further include a first initialization signal second sub-line Vi1-2, a reference voltage signal second sub-line Vref2, and a voltage signal second sub-line VDD2 extending along the second direction, wherein the first initialization signal second sub-line Vi1-2, the reference voltage signal second sub-line Vref2, and the voltage signal second sub-line VDD2 are all located in the fourth conductive layer 6. The first initialization signal first sub-line Vi1-1 and the first initialization signal second sub-line Vi1-2 are electrically connected to form a mesh structure; the reference voltage signal first sub-line Vref1 and the reference voltage signal second sub-line Vref2 are electrically connected to form a mesh structure; the voltage signal first sub-line VDD1 and the voltage signal second sub-line VDD2 are electrically connected to form a mesh structure.

[0207] By designing multiple signal lines into a grid shape, the voltage drop in the signal lines can be reduced, thereby improving the display effect of the display substrate.

[0208] The display substrate also includes a scanning signal line GT extending along the first direction, wherein the scanning signal line GT includes a first scanning signal sub-line GT1 and a second scanning signal sub-line GT2, the first scanning signal sub-line GT1 is located in the first conductive layer 2, and the second scanning signal sub-line GT2 is located in the third conductive layer 5; the driving circuit also includes a compensation sub-circuit, the compensation sub-circuit includes a compensation transistor T2, the compensation transistor T2 includes a compensation active layer ACT2 and a control electrode G2, the control electrode G2 of the compensation transistor includes a first sub-control electrode G21 and a second sub-control electrode G22, wherein the positive projections of any two of the compensation active layer ACT2, the first scanning signal sub-line GT1 and the second scanning signal sub-line GT2 on the base substrate at least partially overlap, the overlapping portion of the compensation active layer ACT2 and the first scanning signal sub-line GT1 is the first sub-control electrode G21 of the compensation transistor, and the overlapping portion of the compensation active layer ACT2 and the second scanning signal sub-line GT2 is the second sub-control electrode G22 of the compensation transistor.

[0209] Illustratively, the reset signal line Re further includes a reset signal second sub-line Re2, which is located in the third conductive layer 5. The display substrate further includes a reset signal transfer portion Rem, which is located in the first conductive layer 2. The reset signal second sub-line Re2 is electrically connected to the reset signal transfer portion Rem through the first via VH1.

[0210] The driving circuit also includes a first initialization sub-circuit, the first initialization sub-circuit includes a first initialization transistor T4, the first initialization transistor T4 includes a first initialization active layer ACT4 and a control electrode G4, the control electrode G4 of the first initialization transistor includes a third sub-control electrode G41 and a fourth sub-control electrode G42, wherein the positive projections of any two of the first initialization active layer ACT4, the reset signal second sub-line Re2 and the reset signal transfer part Rem on the substrate at least partially overlap, the overlapping part of the first initialization active layer ACT4 and the reset signal transfer part Rem is the third sub-control electrode G41 of the first initialization transistor, and the overlapping part of the first initialization active layer ACT4 and the reset signal second sub-line Re2 is the fourth sub-control electrode G42 of the first initialization transistor.

[0211] The display substrate may further include a first light-emitting control signal line EM1 extending along the first direction. The driving circuit further includes: a first light-emitting control subcircuit, a second light-emitting control subcircuit and an auxiliary subcircuit, wherein the first light-emitting control subcircuit includes a first light-emitting control transistor T6, the first light-emitting control transistor T6 includes a first light-emitting control active layer ACT6 and a control electrode G6; the second light-emitting control subcircuit includes a second light-emitting control transistor T8, the second light-emitting control transistor T8 includes a second light-emitting control active layer ACT8 and a control electrode G8; the auxiliary subcircuit includes an auxiliary transistor T9, the auxiliary transistor T9 includes a charge release active layer ACT9, a control electrode G9 and a second electrode S9, wherein the orthographic projection of the first light-emitting control active layer ACT6 on the base substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line EM1 on the base substrate, and the first light-emitting control active layer ACT6 on the base substrate at least partially overlaps with the first light-emitting control signal line EM1 on the base substrate, and the first light-emitting control subcircuit includes a first light-emitting control transistor T6, the first light-emitting control transistor T6 includes a first light-emitting control active layer ACT6 and a control electrode G6; the second light-emitting control subcircuit includes a second light-emitting control transistor T8, the second light-emitting control transistor T8 includes a second light-emitting control active layer ACT8 and a control electrode G8; the auxiliary subcircuit includes an auxiliary transistor T9, the auxiliary transistor T9 includes a charge release active layer ACT9, a control electrode G9 and a second electrode S9, The overlapping portion of the light-emission control active layer ACT6 and the first light-emission control signal line EM1 forms the control electrode G6 of the first light-emission control transistor. The orthographic projection of the second light-emission control active layer ACT8 on the substrate at least partially overlaps with the orthographic projection of the first light-emission control signal line EM1 on the substrate, and the overlapping portion of the second light-emission control active layer ACT8 and the first light-emission control signal line EM1 forms the control electrode G8 of the second light-emission control transistor. The orthographic projection of the charge release active layer ACT9 on the substrate at least partially overlaps with the orthographic projection of the first light-emission control signal line EM1 on the substrate, and the overlapping portion of the charge release active layer ACT9 and the first light-emission control signal line EM1 forms the control electrode G9 of the auxiliary transistor. The second electrode S9 of the auxiliary transistor is suspended. By suspending the second electrode S9 of the auxiliary transistor, the charge accumulated in the control electrode of the driver sub-circuit can be released, which helps to improve the stability of the driver circuit.

[0212] The display substrate also includes a data signal line Data extending along the second direction, and the data signal line is located in the fourth conductive layer 6; the driving circuit also includes a data writing sub-circuit, the data writing sub-circuit includes a data writing transistor T1, the data writing transistor includes a data writing active layer ACT1 and a second electrode S1, the positive projection of the data writing active layer ACT1 on the base substrate and the positive projection of the signal scanning first sub-line GT1 on the base substrate at least partially overlap, and the overlapping part of the data writing active layer ACT1 and the signal scanning first sub-line GT1 is the control electrode G1 of the data writing transistor; the second electrode S1 of the data writing transistor is electrically connected to the data signal line Data through the sixth conductive transition portion m6, wherein the sixth conductive transition portion m6 is located in the third conductive layer 5.

[0213] The drive circuit also includes a drive subcircuit and a storage subcircuit. The drive subcircuit includes a drive transistor T3. The storage subcircuit includes a storage capacitor C1. The storage capacitor C1 includes a first plate C1a and a second plate C1b. The first plate C1a is located in the first conductive layer 2, and the second plate C1b is located in the second conductive layer 4. The drive transistor T3 includes an active layer ACT3, a control electrode G3, a first electrode D3, and a second electrode S3. The orthographic projection of the active layer ACT3 of the drive transistor T3 on the substrate at least partially overlaps with the first plate C1a of the storage capacitor. The overlapping portion of the active layer ACT3 of the drive transistor T3 and the first plate C1a of the storage capacitor constitutes the control electrode G3 of the drive transistor. The first electrode D3 of the drive transistor is electrically connected to the second sub-line VDD2 of the voltage signal via a fifth conductive transition portion m5, wherein the fifth conductive transition portion m5 is located in the third conductive layer 5.

[0214] The driving circuit also includes a second initialization sub-circuit, which includes a second initialization transistor T5. The second initialization transistor T5 includes an active layer ACT5, a control electrode G5, a first electrode D5, and a second electrode S5. The positive projection of the active layer ACT5 of the second initialization transistor T5 on the substrate at least partially overlaps with the positive projection of the reset signal second sub-line Re2 on the substrate. The overlapping portion of the active layer ACT5 of the second initialization transistor T5 and the reset signal second sub-line Re2 is the control electrode G5 of the second initialization transistor T5.

[0215] The data writing transistor T1 also includes a first electrode D1, the compensation transistor T2 also includes a first electrode D2 and S2, the first initialization transistor T4 also includes a first electrode D4 and a second electrode S4, the first light-emitting control transistor T6 also includes a first electrode D6 and a second electrode S6, the second light-emitting control transistor T8 also includes a second electrode S8, and the auxiliary transistor T9 also includes a first electrode D9 and a second electrode S9, wherein the second electrode S9 of the auxiliary transistor T9 is set to be suspended.

[0216] The first electrode D1 of the data write transistor T1, the first electrode D5 of the second initialization transistor T5, and the first electrode D6 of the first emission control transistor T6 are coupled to the second node N2 via an eleventh conductive transition portion m11. The eleventh conductive transition portion m11 can also be electrically connected to the second plate C1b of the storage capacitor via a second via VH2. The second electrode S6 of the second initialization transistor T5 and the second electrode of the first emission control transistor T6 are electrically connected to the first reference voltage signal sub-line Vref1 via a ninth conductive transition portion m9. The first reference voltage signal sub-line Vref1 and the second reference voltage signal sub-line Vref2 are electrically connected via an eighth conductive transition portion m8.

[0217] The first electrode D2 of the compensation transistor T2, the control electrode G3 of the driving transistor T3, the first electrode D4 of the first initialization transistor T4, and the first electrode D9 of the auxiliary transistor T9 are coupled to the first node N1 via the tenth conductive transition portion m10. The second electrode S4 of the first initialization transistor T4 is electrically connected to the first initialization signal line Vi1 via the seventh conductive transition portion m7.

[0218] The second electrode S3 of the driving transistor T3 , the second electrode S2 of the compensation transistor T2 , and the second electrode S8 of the second light emitting control transistor T8 are coupled to the third node N3 .

[0219] FIG15 is a schematic structural diagram of a display device according to some embodiments of the present disclosure.

[0220] Optionally, embodiments of the present disclosure further provide a display device. Referring to FIG. 15 , the display device 1000 may include the display substrate 100 described above. The display device may include, but is not limited to, electronic paper, mobile phones, tablet computers, monitors, laptop computers, digital photo frames, navigation systems, and any other product or component with a display function. It should be understood that this display device has the same beneficial effects as the display substrates provided in the aforementioned embodiments.

[0221] Although some embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made to these embodiments without departing from the principles and spirit of the present general inventive concept, the scope of which is defined in the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that: The pixel circuit includes a driving circuit and a switching circuit for controlling different pixel units to turn on or off, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel arranged adjacent to each other, the first sub-pixel includes a first light-emitting element, and the second sub-pixel includes a second light-emitting element, wherein the first light-emitting element and the second light-emitting element both emit light of a first wavelength, the first sub-pixel has a first field of view angle, and the second sub-pixel has a second field of view angle, and the first field of view angle is smaller than the second field of view angle. The switching circuit includes: a first sub-pixel switching circuit for controlling the first sub-pixel to be turned on or off; and a second sub-pixel switching circuit for controlling the second sub-pixel to be turned on or off; The first sub-pixel switching circuit and the second sub-pixel switching circuit share one driving circuit.

2. The pixel circuit according to claim 1, wherein: The first sub-pixel switch circuit is coupled to the second light-emitting control signal terminal, the drive circuit, and the first electrode of the first light-emitting element, respectively. The first sub-pixel switch circuit is configured to control the connection and disconnection of the drive circuit and the first light-emitting element in response to a second light-emitting control signal provided by the second light-emitting control signal terminal; The second sub-pixel switching circuit is coupled to the third light-emitting control signal terminal, the driving circuit and the first electrode of the second light-emitting element respectively, and the second sub-pixel switching circuit is configured to control the on and off of the driving circuit and the second light-emitting element in response to the third light-emitting control signal provided by the third light-emitting control signal terminal.

3. The pixel circuit according to claim 1 or 2, wherein: The first sub-pixel switch circuit and the first electrode of the first light-emitting element are coupled to a fourth node; The switching circuit also includes a third initialization sub-circuit, which is coupled to the reset signal terminal, the fourth node and the initialization signal terminal. The third initialization sub-circuit is configured to respond to the reset signal received at the reset signal terminal, transmit the initialization signal received at the initialization signal terminal to the fourth node, so as to initialize the potential of the fourth node.

4. The pixel circuit according to claim 1 or 2, wherein: The first sub-pixel switch circuit and the first electrode of the first light-emitting element are coupled to a fourth node; the second sub-pixel switch circuit and the first electrode of the second light-emitting element are coupled to a fifth node; The switch circuit further includes a third initialization sub-circuit and a fourth initialization sub-circuit, The third initialization sub-circuit is coupled to the reset signal terminal, the fourth node, and the initialization signal terminal. The third initialization sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the fourth node in response to the reset signal received at the reset signal terminal, so as to initialize the potential of the fourth node. The fourth initialization sub-circuit is coupled to the reset signal terminal, the fifth node and the initialization signal terminal. The fourth initialization sub-circuit is configured to transmit the initialization signal received at the initialization signal terminal to the fifth node in response to the reset signal received at the reset signal terminal to initialize the potential of the fifth node.

5. The pixel circuit according to claim 1, wherein: The first sub-pixel switch circuit is coupled to the second light emitting control signal terminal, the first electrode of the first light emitting element, and the second electrode of the first light emitting element, respectively, and the first sub-pixel switch circuit is configured to short-circuit the first light emitting element in response to a second light emitting control signal provided at the second light emitting control signal terminal; The first electrode of the first light-emitting element, the first sub-pixel switch circuit and the driving circuit are coupled to a fourth node; The second sub-pixel switch circuit is coupled to a third light emitting control signal terminal, a first electrode of the second light emitting element, and a second electrode of the second light emitting element, respectively, and the second sub-pixel switch circuit is configured to short-circuit the second light emitting element in response to a third light emitting control signal provided at the third light emitting control signal terminal; The second electrode of the first light-emitting element, the first electrode of the second light-emitting element, the first sub-pixel switch circuit, and the second sub-pixel switch circuit are coupled to a fifth node. The pixel circuit according to claim 5 , wherein: The switching circuit also includes a third initialization sub-circuit, which is coupled to the reset signal terminal, the fourth node and the initialization signal terminal. The third initialization sub-circuit is configured to respond to the reset signal received at the reset signal terminal, transmit the initialization signal received at the initialization signal terminal to the fourth node, so as to initialize the potential of the fourth node.

7. The pixel circuit according to any one of claims 1 to 6, wherein: The initialization signal terminal includes one of a first initialization signal terminal and a second initialization signal terminal.

8. The pixel circuit according to any one of claims 1 to 4, wherein: The first sub-pixel switch circuit, the second sub-pixel switch circuit, and the driving circuit are coupled to a sixth node.

9. The pixel circuit according to claim 8, wherein: The driving circuit includes a second light-emitting control sub-circuit, which is coupled to the first light-emitting control signal terminal, the third node and the sixth node. The second light-emitting control sub-circuit is configured to transmit the driving current from the third node to the sixth node in response to the first light-emitting control signal received at the first light-emitting control signal terminal.

10. The pixel circuit according to claim 4, wherein: The first sub-pixel switch circuit, the second sub-pixel switch circuit, and the driving circuit are coupled to a third node.

11. The pixel circuit according to claim 6, wherein: The driving circuit includes a second light-emitting control sub-circuit, which is coupled to the first light-emitting control signal terminal, the third node and the fourth node. The second light-emitting control sub-circuit is configured to transmit the driving current from the third node to the fourth node in response to the first light-emitting control signal received at the first light-emitting control signal terminal.

12. The pixel circuit according to any one of claims 1 to 11, wherein: The driving circuit further includes: a data writing sub-circuit, the data writing sub-circuit being coupled to the data signal terminal, the scan signal terminal, and the second node, the data writing sub-circuit being configured to write a data signal received at the data signal terminal into the second node in response to a scan signal received at the scan signal terminal; a driving sub-circuit coupled to the voltage signal terminal, the first node, and the third node, the driving sub-circuit being configured to generate a driving current in response to a voltage at the first node; a compensation subcircuit coupled to the scan signal terminal, the first node, and the third node, the compensation subcircuit configured to transmit the voltage signal from the voltage signal terminal and the threshold voltage of the driving subcircuit to the first node in response to a scan signal received at the scan signal terminal; and A storage sub-circuit is coupled between the first node and the second node, and is configured to store a voltage.

13. The pixel circuit according to any one of claims 1 to 12, wherein: The driving circuit also includes: a first initialization sub-circuit, which is coupled to the first initialization signal terminal, the reset signal terminal and the first node, and the first initialization sub-circuit is configured to respond to the reset signal received at the reset signal terminal, transmit the first initialization signal received at the first initialization signal terminal to the first node to initialize the potential of the first node.

14. The pixel circuit according to any one of claims 1 to 13, wherein: The driving circuit also includes: a second initialization sub-circuit, which is coupled to the reference voltage signal terminal, the reset signal terminal and the second node, and the second initialization sub-circuit is configured to transmit the reference voltage signal received at the reference voltage signal terminal to the second node in response to the reset signal received at the reset signal terminal.

15. The pixel circuit according to any one of claims 1 to 14, wherein: The driving circuit also includes: a first light-emitting control sub-circuit, which is coupled to the reference voltage signal terminal, the first light-emitting control signal terminal and the second node, and the first light-emitting control sub-circuit is configured to transmit the reference voltage signal received at the reference voltage signal terminal to the second node in response to the first light-emitting control signal received at the first light-emitting control signal terminal.

16. The pixel circuit according to any one of claims 1 to 15, wherein: The driving circuit further includes an auxiliary sub-circuit coupled to the first node and a first light-emitting control signal terminal.

17. A display substrate, wherein: The display substrate comprises: substrate; A pixel circuit is provided on the base substrate, wherein the pixel circuit includes a driving circuit and a switching circuit; a plurality of pixel units disposed on the substrate, wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel disposed adjacent to each other, the first sub-pixel includes a first light-emitting element, the second sub-pixel includes a second light-emitting element, wherein both the first light-emitting element and the second light-emitting element emit light of a first wavelength; and a light shielding portion disposed on a side of the pixel unit away from the base substrate, wherein the light shielding portion includes a plurality of openings, the orthographic projections of the openings on the base substrate at least partially overlap with the orthographic projections of the first sub-pixel on the base substrate; and the orthographic projections of the light shielding portion on the base substrate do not overlap with the orthographic projections of the second sub-pixel on the base substrate. Wherein, the switching circuit includes: a first sub-pixel switching circuit, for controlling the switching of the first sub-pixel; and a second sub-pixel switching circuit for controlling the on or off of the second sub-pixel; the first sub-pixel switching circuit and the second sub-pixel switching circuit share a driving circuit.

18. A display substrate, wherein: The display substrate comprises: substrate; A plurality of pixel units are provided on the base substrate, wherein the plurality of pixel units are arranged in an array along a first direction and a second direction on the base substrate; a plurality of pixel circuits, the plurality of pixel circuits being used to drive the plurality of pixel units; wherein at least one of the pixel units includes a first sub-pixel and a second sub-pixel disposed adjacent to each other, the first sub-pixel includes a first light-emitting element, the second sub-pixel includes a second light-emitting element, wherein both the first light-emitting element and the second light-emitting element emit light of a first wavelength; and a light shielding portion disposed on a side of the pixel unit away from the base substrate, wherein the light shielding portion includes a plurality of openings, the orthographic projections of the openings on the base substrate at least partially overlap with the orthographic projections of the first sub-pixel on the base substrate; and the orthographic projections of the light shielding portion on the base substrate do not overlap with the orthographic projections of the second sub-pixel on the base substrate. The pixel circuit includes a driving circuit and a switching circuit, wherein the switching circuit includes: a first sub-pixel switching circuit for controlling the first sub-pixel to be turned on or off; and a second sub-pixel switching circuit for controlling the second sub-pixel to be turned on or off; the first sub-pixel switching circuit and the second sub-pixel switching circuit share a driving circuit; The display substrate comprises: a first conductive layer disposed on the base substrate; a first semiconductor layer disposed on a side of the first conductive layer away from the base substrate; a second conductive layer disposed on a side of the first semiconductor layer away from the base substrate; a third conductive layer disposed on a side of the second conductive layer away from the base substrate; a fourth conductive layer disposed on a side of the third conductive layer away from the base substrate; and a fifth conductive layer disposed on a side of the fourth conductive layer away from the base substrate, wherein the first electrode of the first light-emitting element and the first electrode of the second light-emitting element are both located in the fifth conductive layer; The first sub-pixel switching circuit includes a third light-emitting control transistor, the third light-emitting control transistor includes a first electrode and a second electrode, and the first electrode of the third light-emitting control transistor is electrically connected to the first electrode of the first light-emitting element through a first conductive transition portion; The second sub-pixel switch circuit includes a fourth light emitting control transistor, The first electrode of the fourth light emitting control transistor is electrically connected to the first electrode of the second light emitting element through the second conductive transition portion. The driving circuit includes a second light-emitting control subcircuit, the second light-emitting control subcircuit includes a second light-emitting control transistor, the second light-emitting control transistor includes a first electrode, the second electrode of the third light-emitting control transistor, the second electrode of the fourth light-emitting control transistor and the first electrode of the second light-emitting control transistor are electrically connected through a third conductive transition portion, and the first conductive transition portion, the second conductive transition portion and the third conductive transition portion are all located in the third conductive layer.

19. The display substrate according to claim 18, wherein: The display substrate further includes a reset signal line, a second light emitting control signal line, and a third light emitting control signal line extending along the first direction. The reset signal line includes a first reset signal sub-line, and the first reset signal sub-line, the second light-emitting control signal line, and the third light-emitting control signal line are all located in the second conductive layer; The third light emission control transistor further includes a third light emission control active layer and a control electrode, the third light emission control active layer being located in the first semiconductor layer, an orthographic projection of the third light emission control active layer on the substrate at least partially overlapping with an orthographic projection of the second light emission control signal line on the substrate, and the overlapping portion of the third light emission control active layer and the second light emission control signal line serving as the control electrode of the third light emission control transistor; The fourth light-emitting control transistor also includes a fourth light-emitting control active layer and a control electrode. The fourth light-emitting control active layer is located in the first semiconductor layer. The orthographic projection of the fourth light-emitting control active layer on the base substrate at least partially overlaps with the orthographic projection of the third light-emitting control signal line on the base substrate. The overlapping portion of the fourth light-emitting control active layer and the third light-emitting control signal line is the control electrode of the third light-emitting control transistor.

20. The display substrate according to claim 19, wherein The switch circuit further includes a third initialization subcircuit, the third initialization subcircuit including a third initialization transistor, the third initialization transistor including a third initialization active layer, a control electrode, a first electrode, and a second electrode, the orthographic projection of the third initialization active layer on the substrate at least partially overlapping with the orthographic projection of the first sub-line of the reset signal on the substrate, the overlapping portion of the third initialization active layer and the first sub-line of the reset signal serving as the control electrode of the third initialization transistor, and the second electrode of the third initialization transistor being electrically connected to the first electrode of the first light-emitting element via the first conductive transition portion; The display substrate further includes a second initialization signal line extending along the second direction, the second initialization signal line is located in the fourth conductive layer, and the first electrode of the third initialization transistor is electrically connected to the second initialization signal line through a fourth conductive transition portion.

21. The display substrate according to any one of claims 18 to 20, wherein: The display substrate further comprises a first initialization signal first sub-line, a reference voltage signal first sub-line, and a voltage signal first sub-line extending along a first direction, wherein the first initialization signal first sub-line and the reference voltage signal first sub-line are located in the second conductive layer, and the voltage signal first sub-line is located in the third conductive layer; The display substrate further includes a first initialization signal second sub-line, a reference voltage signal second sub-line, and a voltage signal second sub-line extending along the second direction, wherein the first initialization signal second sub-line, the reference voltage signal second sub-line, and the voltage signal second sub-line are all located in the fourth conductive layer, wherein, The first initialization signal first sub-line and the first initialization signal second sub-line are electrically connected to form a mesh structure; The first reference voltage signal sub-line and the second reference voltage signal sub-line are electrically connected to form a mesh structure; The first voltage signal sub-line and the second voltage signal sub-line are electrically connected to form a mesh structure.

22. The display substrate according to any one of claims 18 to 21, wherein: The display substrate further includes a scan signal line extending along a first direction, wherein the scan signal line includes a first scan signal sub-line and a second scan signal sub-line, the first scan signal sub-line is located in the first conductive layer, and the second scan signal sub-line is located in the third conductive layer; The driving circuit also includes a compensation sub-circuit, which includes a compensation transistor. The compensation transistor includes a compensation active layer and a control electrode. The control electrode of the compensation transistor includes a first sub-control electrode and a second sub-control electrode. The positive projections of any two of the compensation active layer, the first sub-line of the scan signal, and the second sub-line of the scan signal on the substrate at least partially overlap. The overlapping portion of the compensation active layer and the first sub-line of the scan signal is the first sub-control electrode of the compensation transistor, and the overlapping portion of the compensation active layer and the second sub-line of the scan signal is the second sub-control electrode of the compensation transistor.

23. The display substrate according to claim 19, wherein The reset signal line further includes a reset signal second sub-line, and the reset signal second sub-line is located in the third conductive layer; The display substrate further includes a reset signal transfer portion, and the reset signal transfer portion is located in the first conductive layer, wherein: The second sub-line of the reset signal is electrically connected to the reset signal transfer portion through a first via hole; The driving circuit also includes a first initialization sub-circuit, the first initialization sub-circuit includes a first initialization transistor, the first initialization transistor includes a first initialization active layer and a control electrode, the control electrode of the first initialization transistor includes a third sub-control electrode and a fourth sub-control electrode, wherein the positive projections of any two of the first initialization active layer, the second sub-line of the reset signal and the reset signal transfer portion on the substrate at least partially overlap, the overlapping portion of the first initialization active layer and the reset signal transfer portion is the third sub-control electrode of the first initialization transistor, and the overlapping portion of the first initialization active layer and the second sub-line of the reset signal is the fourth sub-control electrode of the first initialization transistor.

24. The display substrate according to any one of claims 18 to 23, wherein: The display substrate further includes a first light emitting control signal line extending along a first direction; The driving circuit further includes: a first light-emitting control subcircuit, a second light-emitting control subcircuit and an auxiliary subcircuit. The first light-emitting control subcircuit includes a first light-emitting control transistor, which includes a first light-emitting control active layer and a control electrode; the second light-emitting control subcircuit includes a second light-emitting control transistor, which includes a second light-emitting control active layer and a control electrode; the auxiliary subcircuit includes an auxiliary transistor, which includes a charge release active layer, a control electrode and a second electrode, wherein: The orthographic projection of the first light-emitting control active layer on the base substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line on the base substrate, and the overlapping portion of the first light-emitting control active layer and the first light-emitting control signal line serves as the control electrode of the first light-emitting control transistor; The orthographic projection of the second light-emitting control active layer on the base substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line on the base substrate, and the overlapping portion of the second light-emitting control active layer and the first light-emitting control signal line serves as the control electrode of the second light-emitting control transistor; The orthographic projection of the charge-releasing active layer on the base substrate at least partially overlaps with the orthographic projection of the first light-emitting control signal line on the base substrate, and the overlapping portion of the charge-releasing active layer and the first light-emitting control signal line serves as the control electrode of the auxiliary transistor; and The second electrode of the auxiliary transistor is suspended.

25. The display substrate according to claim 22, wherein: The display substrate further includes a data signal line extending along the second direction, wherein the data signal line is located in the fourth conductive layer; The driving circuit further includes a data writing sub-circuit, the data writing sub-circuit including a data writing transistor, the data writing transistor including a data writing active layer and a second electrode, the orthographic projection of the data writing active layer on the substrate at least partially overlaps with the orthographic projection of the first signal scanning sub-line on the substrate, and the overlapping portion of the data writing active layer and the first signal scanning sub-line serves as a control electrode of the data writing transistor; The second electrode of the data writing transistor is electrically connected to the data signal line through a sixth conductive transition portion, wherein the sixth conductive transition portion is located in the third conductive layer.

26. The display substrate according to claim 21, wherein The driving circuit also includes a driving sub-circuit, which includes a driving transistor. The driving transistor includes a first electrode, and the first electrode of the driving transistor is electrically connected to the second sub-line of the voltage signal through a fifth conductive transition portion, wherein the fifth conductive transition portion is located in the third conductive layer.

27. A display device, wherein: The display device includes the display substrate according to any one of claims 17 to 26.

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