Display panel, display apparatus and driving method

Abstract

Disclosed are a display panel, a display apparatus and a driving method. The display panel comprises: a substrate, having a first display area (AA1) and a second display area (AA2); a plurality of first sub-pixels (P1) located in the first display area (AA1); and a plurality of second sub-pixels (P2) located in the second display area (AA2). At least one second sub-pixel (P2) of the plurality of second sub-pixels (P2) comprises a first pixel portion (P21) and a second pixel portion (P22), the light-emitting area of the first pixel portion (P21) being less than the light-emitting area of the second pixel portion (P22).

Description

Display panel, display device and driving method Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a display panel, display device, and driving method. Background Technology

[0002] With the continuous development of display technology, people's demands for display methods are becoming increasingly diversified. In some display applications, users like to share information with others. In other application scenarios, users need privacy protection, requiring display products to have anti-spy functions, such as when users are inputting personal information on their mobile phones or when users are handling confidential company information. Therefore, display sharing and privacy switching are gradually becoming functional trends in display products.

[0003] Summary of the Invention

[0004] This disclosure provides a display panel, a display device, and a driving method. The display panel includes:

[0005] The substrate has a first display area and a second display area;

[0006] Multiple first sub-pixels are located in the first display area;

[0007] A plurality of second sub-pixels are located in the second display area; at least one of the plurality of second sub-pixels includes: a first pixel portion and a second pixel portion; wherein the light-emitting area of ​​the first pixel portion is smaller than the light-emitting area of ​​the second pixel portion.

[0008] In one possible implementation, at least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the light-emitting area of ​​the third pixel portion is equal to the light-emitting area of ​​the fourth pixel portion.

[0009] In one possible implementation, at least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the light-emitting area of ​​the third pixel portion is smaller than the light-emitting area of ​​the fourth pixel portion.

[0010] In one possible implementation, the light-emitting area of ​​the fourth pixel is equal to the light-emitting area of ​​the second pixel.

[0011] In one possible implementation, at least one of the plurality of first sub-pixels is a monolithic connection structure.

[0012] In one possible implementation, the light-emitting area of ​​the first sub-pixel is greater than or equal to the sum of the light-emitting areas of the first sub-pixel portion and the second pixel portion.

[0013] In one possible implementation, the display panel includes: a first shielding layer; the first shielding layer includes: a first opening and a second opening; the orthographic projection of the first opening onto the substrate overlaps with the orthographic projection of the first pixel portion onto the substrate; the orthographic projection of the second opening onto the substrate overlaps with the orthographic projection of the second pixel portion onto the substrate.

[0014] The projected area of ​​the first opening on the substrate is smaller than the projected area of ​​the second opening on the substrate.

[0015] In one possible implementation, at least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the first masking layer further includes: a third opening and a fourth opening; the orthographic projection of the third opening on the substrate overlaps with the orthographic projection of the third pixel portion on the substrate; the orthographic projection of the fourth opening on the substrate overlaps with the orthographic projection of the fourth pixel portion on the substrate.

[0016] The projected area of ​​the fourth opening on the substrate is equal to the projected area of ​​the second opening on the substrate.

[0017] In one possible implementation, the projected area of ​​the third opening on the substrate is equal to the projected area of ​​the fourth opening on the substrate.

[0018] In one possible implementation, the projected area of ​​the third opening on the substrate is smaller than the projected area of ​​the fourth opening on the substrate.

[0019] In one possible implementation, at least one of the plurality of first sub-pixels is an integrally connected structure; the first shielding layer further includes: a fifth opening; the orthographic projection of the fifth opening onto the substrate overlaps with the orthographic projection of the first sub-pixel onto the substrate.

[0020] In one possible implementation, the projected area of ​​the fifth opening on the substrate is greater than or equal to the sum of the projected areas of the first opening and the second opening on the substrate.

[0021] In one possible implementation, the first opening includes: a plurality of first sub-openings; the plurality of first sub-openings of the first opening are arranged in an array.

[0022] In one possible implementation, the orthographic projection of the first sub-opening onto the substrate is rectangular, hexagonal, octagonal, circular, or elliptical.

[0023] In one possible implementation, the first pixel portion includes a first anode portion; the second pixel portion includes a second anode portion.

[0024] The orthographic projection area of ​​the first anode portion on the substrate is smaller than the orthographic projection area of ​​the second anode portion on the substrate.

[0025] In one possible implementation, at least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the third pixel portion has a third anode portion, and the fourth pixel portion has a fourth anode portion;

[0026] The projected area of ​​the third anode portion on the substrate is equal to the projected area of ​​the fourth anode portion on the substrate, and both are equal to the projected area of ​​the second anode portion on the substrate.

[0027] In one possible implementation, at least one of the plurality of first sub-pixels is an integrally connected structure; the first sub-pixel portion includes: a fifth anode portion;

[0028] The projected area of ​​the fifth anode portion on the substrate is greater than or equal to the sum of the projected areas of the first anode portion and the second anode portion on the substrate.

[0029] In one possible implementation, the display panel further includes a second light-shielding layer located on the side of the first light-shielding layer facing the substrate;

[0030] The second light-shielding layer includes: a first light-emitting port and a second light-emitting port; the orthographic projection of the first light-emitting port on the substrate overlaps with the orthographic projection of the first opening on the substrate; the orthographic projection of the second light-emitting port on the substrate overlaps with the orthographic projection of the second opening on the substrate.

[0031] In one possible implementation, the display panel further includes a lens layer located on the side of the first light-shielding layer opposite to the substrate;

[0032] The lens layer includes: a first lens and a second lens; the first lens covers the orthographic projection of the first opening onto the substrate; the orthographic projection of the second lens onto the substrate covers the orthographic projection of the second opening onto the substrate.

[0033] In one possible implementation, the display panel further includes: an encapsulation layer, and a touch layer located on the side of the encapsulation layer opposite to the substrate; the first light-shielding layer is located on the side of the encapsulation layer opposite to the substrate.

[0034] In one possible implementation, of the first sub-pixel and the second sub-pixel, at least the second sub-pixel includes: a plurality of light emitters stacked along a direction perpendicular to the substrate; the light emitters include one or a combination of the following film layers stacked together:

[0035] Hole transport layer;

[0036] Emissive layer;

[0037] Electron transport layer.

[0038] In one possible implementation, the second sub-pixel includes: a second pixel circuit;

[0039] Both the first anode portion and the second anode portion are electrically connected to the second pixel circuit.

[0040] In one possible implementation, the second pixel circuit includes at least: a first light-emitting control sub-circuit and a second light-emitting control sub-circuit; the display panel further includes: a first light-emitting control line and a second light-emitting control line;

[0041] The first light emission control sub-circuit is electrically connected to the first light emission control line and the first anode portion, and is configured to drive the first pixel portion to emit light under the control of the first light emission control line;

[0042] The second light emission control sub-circuit is electrically connected to the second light emission control line and the second anode portion, and is configured to drive the second pixel portion to emit light under the control of the second light emission control line.

[0043] In one possible implementation, the second sub-pixel includes: a first sub-pixel circuit and a second sub-pixel circuit;

[0044] The first anode portion is electrically connected to the first sub-pixel circuit; the second anode portion is electrically connected to the second sub-pixel circuit.

[0045] In one possible implementation, the plurality of second sub-pixels includes: a first pixel row and a second pixel row; the first pixel row and the second pixel row extend along a first direction and are alternately arranged along a second direction; the first pixel row includes: a plurality of first pixel portions; the second pixel row includes: a plurality of second pixel portions;

[0046] The display panel further includes: a first pixel row control line and a second pixel row control line; the first pixel row control line is electrically connected to the first pixel portion of the first pixel row, and the second pixel row control line is electrically connected to the second pixel portion of the second pixel row; the first pixel row control line is configured to provide a signal to the first pixel portion of the first pixel row, and the second pixel row control line is configured to provide a signal to the second pixel portion of the second pixel row.

[0047] This disclosure provides a display device, which includes the display panel as described in this disclosure.

[0048] This disclosure also provides a driving method for a display panel as described in this disclosure, comprising:

[0049] When it is determined that the normal display mode is to be performed, at least a portion of the first sub-pixel of the first display area and at least a portion of the second pixel of the second display area are controlled to emit light;

[0050] When a partial privacy display mode is selected, at least a portion of the first sub-pixel in the first display area and the first sub-pixel portion in the second display area are controlled to emit light.

[0051] In one possible implementation, when it is determined that a normal display mode is to be performed, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined that a normal display mode is to be performed, controlling the fourth pixel portion of the first display area and the second pixel portion of the second display area to emit light.

[0052] When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixel in the first display area and the first sub-pixel portion in the second display area to emit light includes: controlling the third pixel portion in the first display area and the first sub-pixel portion in the second display area to emit light.

[0053] In one possible implementation, when it is determined that a normal display mode is being performed, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined that a normal display mode is being performed, controlling all the first sub-pixels of the first display area and all the second sub-pixels of the second display area to emit light.

[0054] When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixels in the second display area to emit light includes: controlling all the first sub-pixels in the first display area and the first sub-pixels in the second display area to emit light.

[0055] In one possible implementation, when it is determined that a normal display mode is being performed, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined that a normal display mode is being performed, controlling all the first sub-pixels of the first display area and the second pixel portion of the second display area to emit light.

[0056] When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixels in the second display area to emit light includes: controlling all the first sub-pixels in the first display area and the first pixels in the second display area to emit light.

[0057] In one possible implementation, the driving method further includes: when a difference in brightness between the first display area and the second display area is determined during normal display mode, calling a stored relation table to adjust the brightness of the first display area and the second display area to be consistent. Attached Figure Description

[0058] Figure 1A is a schematic diagram of one of the display panels provided in an embodiment of this disclosure;

[0059] Figure 1B is a schematic diagram of Figure 1A in privacy display mode;

[0060] Figure 1C is a schematic diagram of Figure 1A in normal display mode;

[0061] Figure 1D is a schematic diagram of dividing the anode into a first anode portion and a second anode portion according to an embodiment of the present disclosure;

[0062] Figure 2A is a cross-sectional view of Figure 1A at the position of the dashed line A1A2;

[0063] Figure 2B is a cross-sectional view of Figure 1A at the position of dashed line A3A4;

[0064] Figure 2C is another cross-sectional view of Figure 1A at the position of the dashed line A1A2;

[0065] Figure 2D is a schematic diagram of the first opening at the first pixel part P21 in Figure 2C;

[0066] Figure 3 is a pixel circuit diagram of the second display area corresponding to Figure 1A;

[0067] Figure 4A is a schematic diagram of the wiring connection of the second display area corresponding to Figure 1A;

[0068] Figure 4B is a schematic diagram of the wiring connection of the first display area corresponding to Figure 1A;

[0069] Figure 5A is a second schematic diagram of a display panel provided in an embodiment of this disclosure;

[0070] Figure 5B is a schematic diagram of Figure 5A in privacy display mode;

[0071] Figure 5C is a schematic diagram of Figure 5A in normal display mode;

[0072] Figure 6A is a cross-sectional view of Figure 5A at the position of dashed line A1A2;

[0073] Figure 6B is a cross-sectional view of Figure 5A at the position of dashed line A3A4;

[0074] Figure 7 is the pixel circuit diagram of the second display area corresponding to Figure 5A;

[0075] Figure 8 is a schematic diagram of the wiring connection between the first display area and the second display area corresponding to Figure 5A;

[0076] Figure 9A is a third schematic diagram of the display panel provided in an embodiment of this disclosure;

[0077] Figure 9B is a schematic diagram of Figure 9A in privacy display mode;

[0078] Figure 9C is a schematic diagram of Figure 9A in normal display mode;

[0079] Figure 10A is a cross-sectional view of Figure 9A at the position of the dashed line A1A2;

[0080] Figure 10B is a cross-sectional view of Figure 9A at the position of dashed line A3A4;

[0081] Figure 11 is a pixel circuit diagram of the second display area corresponding to Figure 9A;

[0082] Figure 12A is a fourth schematic diagram of a display panel provided in an embodiment of this disclosure;

[0083] Figure 12B is a fifth schematic diagram of a display panel provided in an embodiment of this disclosure;

[0084] Figure 13A is a sixth schematic diagram of a display panel provided in an embodiment of this disclosure;

[0085] Figure 13B is a seventh schematic diagram of a display panel provided in an embodiment of this disclosure;

[0086] Figure 14 is a schematic diagram of the stacking of the first pixel portion provided in an embodiment of this disclosure;

[0087] Figure 15 is a schematic diagram of a plurality of first display areas and second display areas provided in an embodiment of the present disclosure;

[0088] Figure 16 is a schematic diagram of the application scenario of the display panel provided in the embodiments of this disclosure;

[0089] Figure 17 is a schematic diagram of the structure of a display panel provided in an embodiment of this disclosure;

[0090] Figure 18 is a schematic flowchart of the display panel driving method provided in an embodiment of this disclosure. Detailed Implementation

[0091] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0092] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0093] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0094] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0095] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0096] Privacy protection displays have new requirements in new scenarios, as shown in Figure 16. For example, the display screen only needs to have privacy protection in a certain area, while other areas need to display normally. An application scenario is in vehicle display, where the vehicle display can be a large horizontal screen. The driver and passenger can share the same screen. The area facing the driver can be a normal screen, while the passenger area needs to be an active privacy screen (when the vehicle is being driven, the passenger can choose to turn on active privacy protection while watching audio and video to avoid the passenger's display screen affecting the driver's driving, thereby improving safe driving).

[0097] In view of the above, this disclosure provides a display panel, as shown in Figures 1A, 5A, or 9A, wherein in Figures 1A, 5A, and 9A, the lower left figure is an enlarged view of the upper left dashed frame, and the lower right figure is an enlarged view of the upper right dashed frame. The display panel includes:

[0098] The substrate has a first display area AA1 and a second display area AA2; specifically, the first display area AA1 can be used as a normal display area, and the second display area AA2 can be used as a privacy display area.

[0099] Multiple first sub-pixels P1 are located in the first display area AA1; specifically, the first sub-pixel P1 may include a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B;

[0100] A plurality of second sub-pixels P2 are located in the second display area AA2; specifically, the second sub-pixel P2 may include a red sub-pixel R, a green sub-pixel G, or a blue sub-pixel B; at least one of the plurality of second sub-pixels P2 includes: a first pixel portion P21 and a second pixel portion P22; wherein, the light-emitting area of ​​the first pixel portion P21 is smaller than the light-emitting area of ​​the second pixel portion P22.

[0101] In one possible implementation, referring to FIG2A, where FIG2A is a cross-sectional schematic diagram along the dashed line A1A2 in FIG1A, the light-emitting area of ​​the first pixel P21 and the light-emitting area of ​​the second pixel P22 can be controlled by the size of the opening area of ​​the light-shielding layer (as shown in FIG2A, the first light-shielding layer 106). For example, in FIG2A, the display panel includes: a first light-shielding layer 106; the first light-shielding layer 106 includes: a first opening K1 and a second opening K2; the orthographic projection of the first opening on the substrate 101 overlaps with the orthographic projection of the first pixel P21 on the substrate 101; the orthographic projection of the second opening K2 on the substrate 101 overlaps with the orthographic projection of the second pixel P22 on the substrate 101; the orthographic projection area of ​​the first opening K1 on the substrate 101 is smaller than that of the second opening K2. The projected area of ​​the aperture K2 on the substrate 101 can be such that the light-emitting area of ​​the first pixel P21 is smaller than that of the second pixel P22. As shown in Figure 2A, when the first aperture K1 is smaller than the second aperture K2, in the area where the first pixel P21 is located, light from the frontal view can be emitted because the first aperture K1 is smaller, while light from the side view will be blocked (wherein, the dashed arrows represent light that is blocked by the light-shielding layer and cannot be emitted, and the solid arrows represent light that is emitted normally). In the area where the second pixel P22 is located, light emitted from both the frontal and side views can be emitted because the second aperture K2 is larger. That is, by controlling the size of the aperture at different positions of the light-shielding layer, the emission angle of the emitted light can be controlled, thereby achieving privacy protection or normal display control.

[0102] In this embodiment, the display panel has a first display area AA1 and a second display area AA2. The second sub-pixel P2 of the second display area AA2 includes a first pixel portion P21 and a second pixel portion P22. The light-emitting area of ​​the first pixel portion P21 is smaller than the light-emitting area of ​​the second pixel portion P22, allowing the frontal view light from the first pixel portion P21 to be emitted while the side view light is blocked. The second pixel portion P22 can emit both frontal and side view light. Therefore, when the second display area AA2 needs to be used for privacy viewing, by only displaying the first pixel portion P21, only the viewer directly facing the second display area AA2 can view the content displayed on the second display area AA2, while viewers in other positions cannot view the content displayed on the second display area AA2. The content enables privacy protection for the second display area AA2. When normal display of the second display area AA2 is required, at least the second pixel P22 is displayed, allowing the viewer directly in front of the second display area AA2 to view its content, while viewers in other positions can also view the content displayed in the second display area AA2, thus achieving normal display of the second display area AA2. This also enables partial privacy protection for the second display area AA2. In applications where partial privacy protection is required within a display panel, such as in vehicle displays where the driver and passenger share a screen, the passenger can choose to activate active privacy protection while watching audio-visual content to prevent the passenger's display from interfering with the driver's driving, thereby improving driving safety.

[0103] In one possible implementation, the light-emitting area of ​​the first sub-pixel P21 is smaller than the light-emitting area of ​​the second sub-pixel P22. This can be achieved by simultaneously reducing the light-emitting area of ​​the first sub-pixel P21 in both the sub-pixel row direction and the sub-pixel column direction. Specifically, this can be achieved by making the size of the first opening K1 smaller than that of the second opening K2 in both the sub-pixel row direction and the sub-pixel column direction.

[0104] In some exemplary embodiments, the second display area AA2 of the display panel may include an active privacy screen mode and a normal display mode. The active privacy screen mode can meet the display needs of the front passenger who requires independent viewing, while the normal display mode can meet the display needs of users in information-sharing scenarios. In some examples, the display panel may be equipped with a switching button, which the user can use to switch the display mode of the second display area AA2. However, this embodiment is not limited to this. In other examples, voice control, sensors, or other triggering methods can be used to initiate the switching of the display mode of the second display area AA2.

[0105] In one possible implementation, referring to Figures 1A and 2B, wherein Figure 2B is a cross-sectional view along the dashed line A3A4 in Figure 1A, at least one of the plurality of first sub-pixels P1 includes: a third pixel portion P11 and a fourth pixel portion P12; the light-emitting area of ​​the third pixel portion P11 is equal to the light-emitting area of ​​the fourth pixel portion P12.

[0106] In one possible implementation, the light-emitting area of ​​the third pixel P11 and the light-emitting area of ​​the fourth pixel P12 can be controlled by the size of the opening area of ​​the light-shielding layer (the first light-shielding layer 106 in FIG. 2B). For example, referring to FIG. 1A and FIG. 2B, the first light-shielding layer 106 further includes: a third opening K3 and a fourth opening K4; the orthographic projection of the third opening K3 on the substrate 101 overlaps with the orthographic projection of the third pixel P21 on the substrate 101; the orthographic projection of the fourth opening K4 on the substrate 101 overlaps with the orthographic projection of the fourth pixel P22 on the substrate 101; the orthographic projection area of ​​the third opening K3 on the substrate 101 is equal to the orthographic projection area of ​​the fourth opening K4 on the substrate 101, thereby making the light-emitting area of ​​the third pixel P11 equal to the light-emitting area of ​​the fourth pixel P12.

[0107] Specifically, referring to Figures 1B and 1C, where Figure 1B is a schematic diagram of the display panel shown in Figure 1A in privacy mode, and Figure 1C is a schematic diagram of the display panel shown in Figure 1A in normal mode, in privacy mode, as shown in Figure 1B, by displaying the third pixel P11 of the first display area AA1 and not displaying the fourth pixel P12, and by displaying the first pixel P21 of the second display area AA2 and not displaying the second pixel P22, the first display area AA1 can be displayed normally, while the second display area AA2 is in privacy mode. During normal display, as shown in Figure 1C, by disabling the third pixel portion P11 of the first display area AA1 and displaying the fourth pixel portion P12, and disabling the first pixel portion P21 of the second display area AA2 and displaying the second pixel portion P22, both the first display area AA1 and the second display area AA2 can be displayed normally. Moreover, during normal display, only the fourth pixel portion P12 of the first display area AA1 and the second pixel portion P22 of the second display area AA2 are displayed, which can minimize the visual difference between the first display area AA1 and the second display area AA2.

[0108] In one possible implementation, during normal display, the third pixel portion P11 of the first display area AA1 can be displayed while the fourth pixel portion P12 is not displayed, and the first pixel portion P21 of the second display area AA2 is not displayed while the second pixel portion P22 is displayed, thereby enabling both the first display area AA1 and the second display area AA2 to be displayed normally.

[0109] In one possible implementation, the light-emitting areas of the third pixel P11 and the fourth pixel P12 can be made equal to the light-emitting areas of the second pixel P22. Specifically, the projected area of ​​the fourth opening K4 on the substrate 101 can be equal to the projected area of ​​the second opening K2 on the substrate 101. Thus, during normal display, by displaying only the fourth pixel P12 of the first display area AA1 and the second pixel P22 of the second display area AA2, the visual difference between the first display area AA1 and the second display area AA2 can be minimized.

[0110] In one possible implementation, after dividing the second sub-pixel P2 of the second display area AA2 as shown in FIG1A, the first pixel portion P21 and the second pixel portion P22 of the sub-pixel P2 can be driven by different pixel circuits. For example, the circuit shown in FIG7 can be used for driving.

[0111] In another possible implementation, after dividing the second sub-pixel P2 of the second display area AA2 as shown in FIG1A, the first pixel portion P21 and the second pixel portion P22 of the same sub-pixel P2 can be driven to emit light by the same pixel circuit. That is, specifically, as shown in FIG3, the second sub-pixel P2 includes: a second pixel circuit; the first anode portion 205a and the second anode portion 205b are both electrically connected to the second pixel circuit. By driving the first pixel portion P21 and the second pixel portion P22 of the same sub-pixel P2 to emit light by the same pixel driving circuit, the circuit wiring space of the display panel can be saved and the cost of the display panel can be reduced.

[0112] In one possible implementation, referring to Figures 3, 4A, and 4B, where Figure 4A is a schematic diagram of the wiring connection corresponding to the second display area AA2, and Figure 4B is a schematic diagram of the wiring connection corresponding to the first display area AA1, the second pixel circuit includes at least: a first light-emitting control sub-circuit S1 and a second light-emitting control sub-circuit S2; the display panel also includes: a first light-emitting control line EM2 and a second light-emitting control line EM3; the first light-emitting control sub-circuit S1 is electrically connected to the first light-emitting control line EM2 and the first pixel part P21 (specifically, it can be the first anode part 205a in the first pixel part P21), and is configured to drive the first pixel part P21 to emit light under the control of the first light-emitting control line EM2; the second light-emitting control sub-circuit S2 is electrically connected to the second light-emitting control line and the second pixel part P22 (specifically, it can be the second anode part 205b in the second pixel part P22), and is configured to drive the second pixel part P22 to emit light under the control of the second light-emitting control line EM3.

[0113] Specifically, as shown in Figure 4A or Figure 4B, the display panel further includes a gate driving circuit, which may specifically include: a first sub-circuit (EM1-1…EM1-n), a second sub-circuit (EM2-1…EM2-n), a third sub-circuit (EM3-1…EM3-n), a fourth sub-circuit (Re1…Ren), and a fifth sub-circuit (GT1…GT n); wherein, the second sub-circuit (EM2-1…EM2-n) can provide a first light emission control signal for the sub-pixel row and transmit it to the sub-pixel row through the first light emission control line EM2; the third sub-circuit (EM3-1…EM3-n) can provide a second light emission control signal for the sub-pixel row and transmit it to the sub-pixel row through the second light emission control line EM3; the first sub-circuit (EM1-1…EM1-n) can provide a third light emission control signal for the sub-pixel row and transmit it to the sub-pixel row through the third light emission control line EM1; the fourth sub-circuit (Re1…Ren) can provide a reset signal for the sub-pixel row and transmit it to the sub-pixel row through the reset signal line Re; and the fifth sub-circuit (GT1…GT n)… (n) can provide a scan signal for the sub-pixel row and transmit it to the sub-pixel row through the scan signal line GT. Specifically, the first sub-circuit (EM1-1……EM1-n) may include transistors and / or capacitors, the second sub-circuit (EM2-1……EM2-n) may include transistors and / or capacitors, the third sub-circuit (EM3-1……EM3-n) may include transistors and / or capacitors, the fourth sub-circuit (Re1……Ren) may include transistors and / or capacitors, and the fifth sub-circuit (GT1……GT n) may include transistors and / or capacitors.

[0114] In some examples, the first pixel portion P21 may include a stacked first anode portion 205a, a first organic light-emitting layer, and a first cathode. The second pixel portion P22 may include a stacked second anode portion 205b, a second organic light-emitting layer, and a second cathode. The first cathode of the first pixel portion P21 may be electrically connected to a second power line VSS. The second cathode of the second pixel portion P22 may be electrically connected to the second power line VSS. In some examples, referring to FIG1D, the first anode portion 205a of the first pixel portion P21 and the second anode portion 205b of the second pixel portion P22 can be obtained by dividing the anode of the second sub-pixel P2 (e.g., dividing along the dashed line in FIG1D).

[0115] In some examples, the first power line VDD can be configured to continuously provide a high-level first voltage signal, and the second power line VSS can be configured to continuously provide a low-level second voltage signal. The first voltage signal is greater than the second voltage signal.

[0116] In some examples, the multiple transistors in the pixel circuit can be low-temperature polysilicon (LTPS) thin-film transistors (TFTs), oxide thin-film transistors (OTFTs), or a combination of both. The active layer of the LTPS TFT is made of low-temperature polysilicon (LTPS), while the active layer of the OTFT is made of oxide. LTPS TFTs offer advantages such as high mobility and fast charging, while OTFTs offer advantages such as low leakage current. In some examples, LTPS TFTs and OTFTs can be integrated onto a single display panel to form a low-temperature polysilicon-oxide (LTO) display panel. This leverages the advantages of both to achieve high resolution (PPI, pixels per inch), low-frequency driving, reduced power consumption, and improved display quality. However, this embodiment is not limited to this approach.

[0117] Figure 3 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, the pixel circuit can be a 9T1C structure. The pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a storage capacitor Cst. The first light-emitting control sub-circuit S1 may include: the eighth transistor T8; the second light-emitting control sub-circuit S2 may include: the ninth transistor T9. In the circuit structure shown in Figure 3, the first transistor T1 may be a reset transistor, the second transistor T2 may be a threshold compensation transistor, the third transistor T3 may be a driving transistor, the fourth transistor T4 may be a data writing transistor, the fifth transistor T5 may be a light-emitting control transistor, the sixth transistor T6 may be a light-emitting control transistor, the seventh transistor T7 may be a reset transistor, the eighth transistor T8 may be a light-emitting control transistor, and the ninth transistor T9 may be a light-emitting control transistor.

[0118] In some examples, as shown in Figure 3, the gate of the first transistor T1 is electrically connected to the first reset control line Re1, the first terminal of the first transistor T1 is electrically connected to the first initial signal line Vint1, and the second terminal of the first transistor T1 is electrically connected to the first node N1. The gate of the second transistor T2 is electrically connected to the scan line GT, the first terminal of the second transistor T2 is electrically connected to the first node N1, and the second terminal of the second transistor T2 is electrically connected to the third node N3. The gate of the third transistor T3 is electrically connected to the first node N1, the first terminal of the third transistor T3 is electrically connected to the second node N2, and the second terminal of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the scan line GT, the first terminal of the fourth transistor T4 is electrically connected to the data line Vdata, and the second terminal of the fourth transistor T4 is electrically connected to the second node N2. The gate of the fifth transistor T5 is electrically connected to the third light emission control line EM1, the first terminal of the fifth transistor T5 is electrically connected to the first power supply line VDD, and the second terminal of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the third light-emitting control line EM1, the first terminal of the sixth transistor T6 is electrically connected to the third node N3, and the second terminal of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the seventh transistor T7 is electrically connected to the second reset control line Re2, the first terminal of the seventh transistor T7 is electrically connected to the second initial signal line Vint2, and the second terminal of the seventh transistor T7 is electrically connected to the fifth node N5 (i.e., the first anode 205a of the first pixel P21). The gate of the eighth transistor T8 is electrically connected to the first light-emitting control line EM2, the first terminal of the eighth transistor T8 is electrically connected to the fourth node N4, and the second terminal of the eighth transistor T8 is electrically connected to the first anode 205a of the first pixel P21. The gate of the ninth transistor T9 is electrically connected to the second light-emitting control line EM3, the first terminal of the ninth transistor T9 is electrically connected to the fourth node N4, and the second terminal of the ninth transistor T9 is electrically connected to the second anode 205b of the second pixel P22. The first plate of the storage capacitor Cst is electrically connected to the first node N1, and the second plate of the storage capacitor Cst is electrically connected to the first power line VDD.

[0119] In some examples, the first node N1 is the connection point of the first transistor T1, the second transistor T2, the third transistor T3, and the storage capacitor Cst. The second node N2 is the connection point of the third transistor T3, the fourth transistor T4, and the fifth transistor T5. The third node N3 is the connection point of the third transistor T3, the second transistor T2, and the sixth transistor T6. The fourth node N4 is the connection point of the sixth transistor T6, the eighth transistor T8, and the ninth transistor T9. The fifth node N5 is the connection point of the seventh transistor T7, the eighth transistor T8, and the first anode portion 205a of the first pixel portion P21.

[0120] In some examples, the pixel circuit is illustrated using nine P-type transistors. The second reset control line Re2 can be connected to the scan line GT to receive a scan signal. In partial privacy mode, the first light-emitting control line EM2 continuously provides a low-level signal, turning on the third control transistor T8 and putting the first pixel P21 in an illuminated state; the second light-emitting control line EM3 continuously provides a high-level signal, turning off the fourth control transistor T9 and putting the second pixel P22 in a non-illuminated state. In shared (normal) display mode, the first light-emitting control line EM2 continuously provides a high-level signal, turning off the third control transistor T8 and putting the first pixel P21 in a non-illuminated state; the second light-emitting control line EM3 continuously provides a low-level signal, turning on the fourth control transistor T9 and putting the second pixel P22 in an illuminated state.

[0121] The pixel circuit described above is merely an example. This embodiment does not limit the structure of the pixel circuit.

[0122] As shown in Figure 1A, after dividing the first sub-pixel P1 of the first display area AA1, the third pixel portion P11 and the fourth pixel portion P12 of the same first sub-pixel P1 can be driven to emit light through the same pixel circuit. The first sub-pixel P1 includes: a first pixel circuit; the third anode portion 205c and the fourth anode portion 205d are both electrically connected to the first pixel circuit. The structure of the first pixel circuit can be the same as the circuit structure shown in Figure 3, and the driving process is similar, so it will not be described again here.

[0123] In one possible implementation, referring to Figures 5A, 6A and 6B, where Figure 6A can be a cross-sectional view along the dashed line A1A2 in Figure 5A, and Figure 6B can be a cross-sectional view along the dashed line A3A4 in Figure 5A, at least one of the plurality of first sub-pixels P1 includes: a third pixel portion P11 and a fourth pixel portion P12; the light-emitting area of ​​the third pixel portion P11 is smaller than the light-emitting area of ​​the fourth pixel portion P12.

[0124] In one possible implementation, referring to Figures 5A, 6A, and 6B, at least one of the plurality of first sub-pixels P1 includes: a third pixel portion P21 and a fourth pixel portion P22; the first masking layer 106 further includes: a third opening K3 and a fourth opening K4; the orthographic projection of the third opening K3 onto the substrate 101 overlaps with the orthographic projection of the third pixel portion P21 onto the substrate 101; the orthographic projection of the fourth opening K4 onto the substrate 101 overlaps with the orthographic projection of the fourth pixel portion P22 onto the substrate 101, and the orthographic projection area of ​​the third opening K3 onto the substrate 101 is smaller than the orthographic projection area of ​​the fourth opening K4 onto the substrate 101, thereby making the light-emitting area of ​​the third pixel portion P11 smaller than the light-emitting area of ​​the fourth pixel portion P12.

[0125] In this embodiment of the present disclosure, for the first display area AA1 that needs to be displayed normally, the first sub-pixel P1 can also be divided, for example, into a third pixel part P11 and a fourth pixel part P12, and the light-emitting area of ​​the third pixel part P11 is smaller than the light-emitting area of ​​the fourth pixel part P12, which can reduce the visual (e.g., brightness) difference between the first display area AA1 and the second display area AA2 when they are displayed normally.

[0126] Specifically, referring to Figures 5B and 5C, where Figure 5B is a schematic diagram of the display panel shown in Figure 5A in privacy mode, and Figure 5C is a schematic diagram of the display panel shown in Figure 5A in normal display mode, in privacy mode, as shown in Figure 5B, by displaying the third pixel P11 and the fourth pixel P12 of the first display area AA1, the first pixel P21 of the second display area AA2 is displayed, while the second pixel P22 is not displayed, thereby allowing the first display area AA1 to display normally, while the second display area AA2 is in privacy mode. In normal display mode, as shown in Figure 5C, by displaying the third pixel P11 and the fourth pixel P12 of the first display area AA1, the second display area AA2 is displayed, while the second display area AA2 is not displayed. The first pixel P21 of area AA2 is displayed, and the second pixel P22 is also displayed, so that both the first display area AA1 and the second display area AA2 can be displayed normally. Moreover, when the privacy screen is displayed, the third pixel P11 and the fourth pixel P12 of the first display area AA1 are also displayed, which avoids the problem that the light-emitting area of ​​each first sub-pixel P1 of the first display area AA1 is small and the brightness is limited when only the third pixel P11 is displayed. When the display is normal, by displaying the third pixel P11 and the fourth pixel P12 of the first display area AA1, and the first pixel P21 and the second pixel P22 of the second display area AA2, the visual difference between the first display area AA1 and the second display area AA2 can be minimized.

[0127] In one possible implementation, when performing a privacy display, by displaying the third pixel portion P11 of the first display area AA1 and not displaying the fourth pixel portion P12, and by displaying the first pixel portion P21 of the second display area AA2 and not displaying the second pixel portion P22, the first display area AA1 can be displayed normally, while the second display area AA2 performs a privacy display.

[0128] In one possible implementation, for the display panel shown in FIG5A, after the second sub-pixel P2 of the second display area AA2 is divided, the first pixel part P21 and the second pixel part P22 of the same sub-pixel P2 can be driven to emit light by the same pixel circuit. For example, the first pixel part P21 and the second pixel part P22 can be driven to emit light by the circuit shown in FIG3.

[0129] In one possible implementation, for the display panel shown in FIG5A, after the second sub-pixel P2 of the second display area AA2 is divided, the first pixel part P21 and the second pixel part P22 of the same sub-pixel P2 can be driven to emit light by different pixel circuits. The first pixel part P21 is driven by one pixel circuit, and the second pixel part P22 is driven by another pixel circuit. That is, specifically, the second sub-pixel includes: a first sub-pixel circuit and a second sub-pixel circuit; the first anode part 205a is electrically connected to the first sub-pixel circuit P21; and the second anode part 205b is electrically connected to the second sub-pixel circuit P22.

[0130] In one possible implementation, the structures of the first sub-pixel circuit and the second sub-pixel circuit can be as shown in Figure 7, including: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a first capacitor C1; wherein, the gate of the first transistor T1 is electrically connected to the scan line GT, the first electrode of the first transistor T1 is electrically connected to the data line Vdata, and the second electrode of the first transistor T1 is electrically connected to the second node N2; the gate of the second transistor T2 is electrically connected to the scan line GT, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the gate of the third transistor T3 is electrically connected to the first node, and the third transistor T3... The second terminal of transistor T3 is electrically connected to the first power supply line VDD; the second terminal of transistor T3 is electrically connected to the third stage N3; the gate of transistor T4 is electrically connected to the reset signal line Re; the first terminal of transistor T4 is electrically connected to the first initial signal line Vint; and the second terminal of transistor T4 is electrically connected to the first node N1; the gate of transistor T5 is electrically connected to the reset signal line Re; the first terminal of transistor T5 is electrically connected to the reference signal line Vref; and the second terminal of transistor T5 is electrically connected to the second node N2; the gate of transistor T6 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME; if the sub-pixel is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO; if the sub-pixel is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME). Electrical connections are established: the first terminal of the sixth transistor T6 is electrically connected to the reference signal line Vref, and the second terminal of the sixth transistor T6 is electrically connected to the second node N2; the gate of the seventh transistor T7 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME; if the sub-pixel is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO; if the sub-pixel is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME); the first terminal of the seventh transistor T7 is electrically connected to the third node N3, and the second terminal of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the reset signal line Re, the first terminal of the eighth transistor T8 is electrically connected to the second initial signal line Vint2, and the second terminal of the eighth transistor T8 is electrically connected to the fourth node N4; the gate of the ninth transistor T9 is electrically connected to the first pixel row control line EMO (or the second pixel row control line EME; if the sub-pixel is located in the first pixel row P100, it is electrically connected to the first pixel row control line EMO; if the sub-pixel is located in the second pixel row P200, it is electrically connected to the second pixel row control line EME); the first and second terminals of the ninth transistor T9 are electrically connected to the first node N1.The first terminal of the first capacitor C1 is electrically connected to the first node N1, and the second terminal of the first capacitor C1 is electrically connected to the second node N2. The first anode 205a of the first pixel P21 (or the second anode 205b of the second pixel P22, or the third anode 205c of the third pixel P11, or the fourth anode 205d of the fourth pixel P12) is electrically connected to the fourth node N4. The cathode of the first pixel P21 (or the cathode of the second pixel P22, or the cathode of the third pixel P11, or the cathode of the fourth pixel P12) is electrically connected to the second power signal line VSS.

[0131] In some examples, the first node N1 is the connection point of the first capacitor C1, the second transistor T2, the third transistor T3, the fourth transistor T4, and the ninth transistor T9. The second node N2 is the connection point of the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the first capacitor C1. The third node N3 is the connection point of the third transistor T3, the second transistor T2, and the seventh transistor T7. The fourth node N4 is the connection point of the seventh transistor T7, the eighth transistor T8, and the first anode portion 205a of the first pixel portion P21 (or the second anode portion 205b of the second pixel portion P22, or the third anode portion 205c of the third pixel portion P11, or the fourth anode portion 205d of the fourth pixel portion P12).

[0132] The driving and light-emitting process of the 9T1C pixel circuit shown in Figure 7 is similar to that of a conventional 9T1C pixel circuit, and will not be described again in the embodiments of this disclosure.

[0133] In one possible implementation, referring to FIG8, the plurality of second sub-pixels P2 includes: a first pixel row P100 (e.g., odd-numbered pixel rows can be used as the first pixel row), and a second pixel row P200 (e.g., even-numbered pixel rows can be used as the second pixel row); the first pixel row P100 and the second pixel row P200 extend along a first direction X and are alternately arranged along a second direction Y; the first pixel row P100 includes: a plurality of first pixel portions P21; the second pixel row P200 includes: a plurality of second pixel portions P22.

[0134] The display panel also includes: a first pixel row control line EMO and a second pixel row control line EME; the first pixel row control line EMO is electrically connected to the first pixel portion P21 of the first pixel row P100, and the second pixel row control line EME is electrically connected to the second pixel portion P22 of the second pixel row P200; the first pixel row control line EMO is configured to provide a signal to the first pixel portion P21 of the first pixel row P100, and the second pixel row control line EME is configured to provide a signal to the second pixel portion P22 of the second pixel row P200.

[0135] In one possible implementation, the first direction X can be the row direction of the sub-pixel, and the second direction Y can be the column direction of the sub-pixel; in another possible implementation, the first direction X can be the direction from the first display area AA1 to the second display area AA2, and the second direction Y can be the direction perpendicular to the first direction X.

[0136] In one possible implementation, the first pixel row P100 may further include a plurality of third pixel portions P11 of the first sub-pixel P1, and the second pixel row P200 may further include a plurality of fourth pixel portions P12 of the first sub-pixel P1. That is, the third pixel portion P11 of the first display area AA1 and the first pixel P21 of the second display area AA2 are located in odd-numbered rows and are signaled by the first pixel row control line EMO, and the fourth pixel portion P12 of the first display area AA1 and the second pixel P22 of the second display area AA2 are located in even-numbered rows and are signaled by the second pixel row control line EME.

[0137] In one possible implementation, referring to Figures 9A, 10A, and 10B, at least one of the plurality of first sub-pixels P1 is a single, integrally connected structure. That is, the first sub-pixel P1 of the first display area AA1 can be an undivided sub-pixel, the same as the sub-pixels of a conventional display panel. Specifically, referring to Figures 9A, 10A, and 10B, the first shielding layer 106 further includes a fifth opening K5; the orthographic projection of the fifth opening K5 onto the substrate 101 overlaps with the orthographic projection of the first sub-pixel P1 onto the substrate 101. That is, the fifth opening K5 can be the undivided first sub-pixel P1 corresponding to the first display area AA1.

[0138] In this embodiment of the disclosure, for the first display area AA1 that needs to be displayed normally, the first sub-pixel P1 may not be divided. That is, the first sub-pixel P1 is an integral connected structure, and only the second sub-pixel of the second display area AA2 needs to be divided, which reduces the manufacturing difficulty of the display panel.

[0139] In one possible implementation, for the display panel shown in FIG9A, after dividing the second sub-pixel P2 of the second display area AA2, in one possible implementation, the first pixel part P21 and the second pixel part P22 can be driven by the same pixel circuit, and the specific pixel circuit can be shown in FIG3; in another possible implementation, the first pixel part P21 and the second pixel part P22 can be driven by different pixel circuits, and each pixel circuit can be shown in FIG7; for not dividing the first sub-pixel P1 of the first display area AA1, in one possible implementation, the pixel circuit driving the first sub-pixel P1 can be specifically shown in FIG7.

[0140] In one possible implementation, for the display panel shown in FIG9A, the first sub-pixel P1 of the first display area AA1 is not divided, and the second sub-pixel P2 of the second display area AA2 is divided. For the second display AA2, the connection relationship of the signal traces in the display panel can be as shown in FIG4A; while for the first display area AA1, the connection relationship of the signal traces in the display panel can be as shown in FIG11. Unlike FIG4A, in a row of sub-pixels, there is only the first sub-pixel P1, instead of the divided first pixel part P21 and second pixel part P22.

[0141] In one possible implementation, referring to Figures 9A, 10A, and 10B, the light-emitting area of ​​the first sub-pixel P1 is greater than or equal to the sum of the light-emitting areas of the first sub-pixel portion P21 and the second pixel portion P22. Specifically, the projected area of ​​the fifth opening K5 onto the substrate 101 is greater than or equal to the sum of the projected areas of the first opening K1 and the second opening K2 onto the substrate 101. This allows the first display area AA1, which performs normal display, to have higher brightness and a better display effect.

[0142] Specifically, referring to Figures 9B and 9C, where Figure 9B is a schematic diagram of the display panel shown in Figure 9A in privacy mode, and Figure 9C is a schematic diagram of the display panel shown in Figure 9A in normal mode, in privacy mode, as shown in Figure 9B, by displaying the first sub-pixel P1 of the first display area AA1, displaying the first pixel P21 of the second display area AA2, and not displaying the second pixel P22, the first display area AA1 can be displayed normally, while the second display area AA2 is in privacy mode. In normal mode, as shown in Figure 9C, by displaying the first sub-pixel P1 of the first display area AA1, and not displaying the first pixel P21 of the second display area AA2, and displaying the second pixel P22, both the first display area AA1 and the second display area AA2 can be displayed normally.

[0143] In one possible implementation, referring to Figures 2C and 2D, Figure 2D is a schematic diagram of the distribution of multiple first sub-openings K10 at the first opening K1 in Figure 2C. The first opening K1 includes multiple first sub-openings K10; the multiple first sub-openings K10 of the first opening K1 are arranged in an array. In this way, the emission angle of the first opening K1 can be limited, which is beneficial to achieving the anti-peeping effect.

[0144] In one possible implementation, the orthographic projection of the first sub-opening K10 onto the substrate 101 is at least one of a rectangle, hexagon, octagon, circle, or ellipse.

[0145] In one possible implementation, the orthographic projection of the first opening K1 onto the substrate 101 can be at least one of a rectangle, hexagon, octagon, circle, or ellipse; in one possible implementation, the orthographic projection of the second opening K2 onto the substrate 101 can be at least one of a rectangle, hexagon, octagon, circle, or ellipse; in one possible implementation, the orthographic projection of the first light-emitting port Q1 onto the substrate 101 can be at least one of a rectangle, hexagon, octagon, circle, or ellipse; in one possible implementation, the orthographic projection of the second light-emitting port Q2 onto the substrate 101 can be at least one of a rectangle, hexagon, octagon, circle, or ellipse.

[0146] In one possible implementation, referring to FIG2A, the first pixel portion P21 includes a first anode portion 205a; the second pixel portion includes a second anode portion 205b; the projected area of ​​the first anode portion 205a on the substrate 101 is smaller than the projected area of ​​the second anode portion 205b on the substrate 101. Thus, the light-emitting area of ​​the first pixel portion P21 is adapted to be smaller than the light-emitting area of ​​the second pixel portion P22.

[0147] In one possible implementation, as shown in FIG2B, at least one of the plurality of first sub-pixels P1 includes: a third pixel portion P11 and a fourth pixel portion P12; the third pixel portion P11 has a third anode portion 205c, and the fourth pixel portion P12 has a fourth anode portion 205d; the orthogonal projection area of ​​the third anode portion 205c on the substrate 101 is equal to the orthogonal projection area of ​​the fourth anode portion 205d on the substrate 101, and both are equal to the orthogonal projection area of ​​the second anode portion 205b on the substrate 101.

[0148] In one possible implementation, as shown in FIG10B, at least one of the plurality of first sub-pixels P1 is an integrally connected structure; the first sub-pixel portion P1 includes: a fifth anode portion 205e; the orthogonal projection area of ​​the fifth anode portion 205e on the substrate 101 is greater than or equal to the sum of the orthogonal projection areas of the first anode portion 205a and the second anode portion 205b on the substrate 101.

[0149] In one possible implementation, as shown in FIG2A, the display panel further includes: a second light-shielding layer 107 located on the side of the first light-shielding layer 106 facing the substrate 101; the second light-shielding layer 107 includes: a first light-emitting port Q1 and a second light-emitting port Q2; the orthographic projection of the first light-emitting port Q1 on the substrate 101 overlaps with the orthographic projection of the first opening K1 on the substrate 101; the orthographic projection of the second light-emitting port Q2 on the substrate 101 overlaps with the orthographic projection of the second opening K2 on the substrate 101. In this embodiment of the disclosure, by providing two light-shielding layers (i.e., the first light-shielding layer 106 and the second light-shielding layer 107), the emission angle of the first sub-pixel portion P21 (or the second sub-pixel portion P22, or the third sub-pixel portion P11, or the fourth sub-pixel portion P22) can be limited (for example, the privacy viewing angle limited by the first light-shielding layer 106 alone may only be 60°, but by adding the second light-shielding layer 107, the privacy viewing angle can be reduced to 30°), thereby facilitating the achievement of a privacy protection effect.

[0150] In one possible implementation, the projected area of ​​the first light-emitting port Q1 on the substrate 101 can be smaller than the projected area of ​​the first opening K1 on the substrate 101; the projected area of ​​the second light-emitting port Q2 on the substrate 101 can be smaller than the projected area of ​​the second opening K2 on the substrate 101. In this way, the emission angle of the first sub-pixel P21 (or the second sub-pixel P22, or the third sub-pixel P11, or the fourth sub-pixel P22) can be limited, thereby facilitating the achievement of a privacy protection effect.

[0151] In one possible implementation, the projected area of ​​the first light-emitting port Q1 on the substrate 101 can be smaller than the projected area of ​​the second light-emitting port Q2 on the substrate 101, which can enable the second sub-pixel portion P22 of the second display area AA2 to achieve viewing angle limitation in other directions (for example, the second display area AA2 corresponding to the passenger seat can achieve angular emission in the windshield direction).

[0152] In one possible implementation, the projected area of ​​the first light-emitting port Q1 on the substrate 101 can be equal to the projected area of ​​the second light-emitting port Q2 on the substrate 101.

[0153] This embodiment does not limit the number of light-shielding layers. In other examples, the number of light-shielding layers may be greater than or equal to three, and a protective layer may be provided between adjacent light-shielding layers.

[0154] Figure 2A is a partial cross-sectional example of Figure 1A along the A1A2 direction. Figure 2A illustrates a partial cross-sectional structure of a second sub-pixel P2. In some examples, as shown in Figure 2A, in the direction perpendicular to the display panel, the display panel may include: a substrate 101, a display structure layer, an encapsulation structure layer 104, a second shielding layer 107, a first protective layer 105, and a first shielding layer 106 sequentially disposed on the substrate 101. The display structure layer may include: a circuit structure layer 102 and a light-emitting structure layer 103 sequentially disposed on the substrate 101. In some possible implementations, the display panel may include other film layers, such as spacers, etc., which are not limited herein. The circuit structure layer 102 may include: a buffer layer 210, a semiconductor layer 201, a first insulating layer 211, a first gate metal layer 204, a second insulating layer 212, a first source / drain metal layer 202, and a third insulating layer 213 sequentially disposed on the substrate 101.

[0155] In one possible implementation, referring to Figures 12A or 13A, the display panel further includes a lens layer located on the side of the first light-shielding layer 106 facing away from the substrate 101. The lens layer may include a first lens 108a and a second lens 108b. The first lens 108a covers the orthographic projection of the first opening K1 onto the substrate 101; the orthographic projection of the second lens 108b onto the substrate 101 covers the orthographic projection of the second opening K2 onto the substrate 101. In this embodiment, the display panel further includes a first lens 108a and a second lens 108b. The orthographic projection of the first lens 108a onto the substrate 101 covers the orthographic projection of the first opening K1 onto the substrate 101; the orthographic projection of the second lens 108b onto the substrate 101 covers the orthographic projection of the second opening K2 onto the substrate 101. The first lens 108a and the second lens 108b can be used to converge the light from the corresponding light-emitting ports, thereby improving the brightness of the display panel.

[0156] In one possible implementation, as shown in FIG12A or FIG13A, the display panel further includes: an encapsulation layer 104, and a touch layer 109 located on the side of the encapsulation layer 104 away from the substrate; a first light-shielding layer 106 is located on the side of the encapsulation layer 104 away from the substrate 101.

[0157] In one possible implementation, referring to Figures 12A or 13B, the touch layer 109 may be located on the side of the first light-shielding layer 106 facing the substrate 101; specifically, as shown in Figure 12A, the touch layer 109 may be located on the side of the second light-shielding layer 107 facing the substrate 101, and specifically, the touch layer 109 may be a film layer in contact with the second light-shielding layer 107; specifically, as shown in Figure 13B, the touch layer 109 may also be a film layer in contact with the first light-shielding layer 106.

[0158] In another possible implementation, referring to FIG13A, the touch layer 109 can be located on the side of the first light-shielding layer 106 facing away from the substrate 101. Specifically, a first protective layer 105 can be disposed between the touch layer 109 and the first light-shielding layer 106. Specifically, the touch layer 109 can be a film layer in contact with the lens layer. Specifically, when the touch layer 109 is located on the side of the lens layer facing the substrate 101, the touch layer 109 can replace a light-shielding layer. For example, as shown in FIG12A and FIG13A, it can replace the second light-shielding layer 107.

[0159] In one possible implementation, as shown in FIG12A, a second protective layer 110, an optical adhesive layer 111, a polarizer 112, and a cover plate 113 may be sequentially disposed on the side of the lens layer facing away from the substrate 101.

[0160] In one possible implementation, in this embodiment of the present disclosure, the display panel may have a color filter layer disposed on the encapsulation layer 104, that is, it may be a COE (CF On TFE). For example, as shown in FIG2A, FIG12B or FIG13B, the color filter layer may include a first color resist CR (e.g., a red color resist) located at the first opening K1 and the second opening K2. The color filter layer may also include a second color resist (e.g., a green color resist, not shown in FIG2A) and a third color resist (e.g., a blue color resist, not shown in FIG2A). In another possible implementation, in this embodiment of the present disclosure, the display panel may also be a non-COE structure. For example, as shown in FIG12A or FIG13A, the display panel may be provided with a polarizer 112.

[0161] In one possible implementation, the first light-shielding layer 106 and the second light-shielding layer 107 can be black matrix layers.

[0162] In one possible implementation, referring to FIG14, at least the second sub-pixel P2 includes a plurality of light emitters F stacked along a direction perpendicular to the substrate 101; the light emitters F include one or a combination of the following film layers stacked together:

[0163] Hole transport layer 207;

[0164] 206 light-emitting layer;

[0165] Electron transport layer 208.

[0166] In this embodiment of the disclosure, at least the second sub-pixel P2 includes a plurality of light emitters F stacked along a direction perpendicular to the substrate 101. That is, setting the second sub-pixel P2 as a stacked structure can improve the brightness of the second sub-pixel P2 and solve the problem of low brightness and / or low lifespan after the second sub-pixel P2 of the privacy display area is divided.

[0167] In one possible implementation, as shown in Figure 14, a charge transport layer CGL may also be provided between two adjacent light emitters F.

[0168] In some exemplary embodiments, the display panel may be an organic light-emitting diode (OLED) display panel, a quantum dot light-emitting diode (QLED) display panel, a plasma display panel (PDP) display panel, or an electrophoretic display (EPD) display panel. This embodiment is not limited to this.

[0169] In one possible implementation, the display panel may have only one first display area AA1 and one second display area AA2, with the first display area AA1 located on one side of the second display area AA2, as shown in FIG1A; in another possible implementation, the display panel may also have more first display areas AA1 and more second display areas AA2, for example, as shown in FIG15, the display panel may have two first display areas AA1 and one second display area AA2, wherein the second display area AA2 is located between the two first display areas AA1.

[0170] In one possible implementation, for the first display area AA1 and the first sub-pixel P1, the viewing angle perpendicular to the sub-pixel row direction can also be reduced. For example, the width of the first light-shielding layer 106 in the sub-pixel column direction can be reduced. Therefore, when this display panel is applied to the automotive field, when the sub-pixel row direction is from the first display area AA1 to the second display area AA2, the width of the first sub-pixel P1 in the sub-pixel column direction (i.e., perpendicular to the sub-pixel row direction) can be reduced. This reduces the viewing angle of the first sub-pixel P1 in the direction of projection onto the windshield, preventing the image displayed in the first display area AA1 from reflecting onto the windshield and affecting the driver's normal vision. For example, a privacy function can also be provided at the driver's position; for example, a vertical privacy function but no horizontal privacy function can also be provided.

[0171] Figure 17 is a schematic diagram of the structure of a display panel according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 17, the display panel may include: a timing controller 20, a data driver 40, a gate driving circuit, and a sub-pixel array 10. The gate driving circuit may include at least one driver, such as a scan driver 30. The timing controller 20, the data driver 40, and the gate driving circuit may be located in the peripheral area surrounding the display area of ​​the display panel. The sub-pixel array 10 located in the display area may include a plurality of regularly arranged sub-pixels PX. The scan driver 30 may be configured to provide scan signals to the sub-pixels PX along scan lines; the data driver 40 may be configured to provide data signals to the sub-pixels PX along data lines; and the timing controller 20 may be configured to control the scan driver 30 and the data driver 40.

[0172] In some examples, timing controller 20 can provide grayscale values ​​and control signals of specifications suitable for data driver 40 to data driver 40; timing controller 20 can provide clock signals, initial signals, etc., of specifications suitable for scan driver 30 to scan driver 30. Data driver 40 can use the grayscale values ​​and control signals received from timing controller 20 to generate data voltages to be provided to data lines D1 to Dn. For example, data driver 40 can sample grayscale values ​​using a clock signal and apply data signals corresponding to grayscale values ​​to data lines D1 to Dn on a sub-pixel line basis. Scan driver 30 can use clock signals, initial signals, etc., received from timing controller 20 to generate scan signals to be provided to scan lines G1 to Gm. For example, scan driver 30 can sequentially provide scan signals with on-level pulses to scan lines. In some examples, scan driver 30 may include a shift register that can generate scan signals by sequentially transmitting scan initial signals provided in the form of on-level pulses to the next stage circuit under the control of a clock signal. Here, n and m are both natural numbers.

[0173] In some examples, the gate driver circuitry can be directly disposed on the substrate. For example, the gate driver can be disposed in the peripheral areas on the left and right sides of the display area. In some examples, the gate driver can be formed together with the sub-pixel during the sub-pixel formation process. However, this embodiment does not limit the location or formation method of the gate driver. In some examples, the gate driver can be disposed on a separate chip or printed circuit board to connect to pads or solder pads formed on the substrate.

[0174] In some examples, the data driver 40 may be disposed on a separate chip or printed circuit board to connect to the sub-pixel PX via signal access pins disposed on the substrate. For example, the data driver 40 may be formed using a chip-on-glass, chip-on-plastic, or chip-on-film configuration to connect to signal access pins on the substrate. The timing controller 20 may be disposed separately from or integrated with the data driver 40. However, this embodiment is not limited to this.

[0175] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes a display panel as provided in embodiments of this disclosure.

[0176] Based on the same inventive concept, this disclosure also provides a driving method for a display panel provided in this disclosure, as shown in FIG18, which includes:

[0177] Step S100: When it is determined that the normal display mode is in operation, control at least a portion of the first sub-pixel of the first display area and at least a portion of the second pixel of the second display area to emit light.

[0178] Step S200: When determining to perform partial privacy display mode, control at least a portion of the first sub-pixel of the first display area and the first pixel portion of the second display area to emit light.

[0179] In one possible implementation, regarding the display panel corresponding to FIG1A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protected first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is divided into two normally displayed third pixel portions P11 and fourth pixel portions P12, in different display modes, regarding step S100, when determining to perform a normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to perform a normal display mode, controlling the fourth pixel portion P12 of the first display area AA1 and the second pixel portion P22 of the second display area AA2 to emit light, as shown in FIG1C;

[0180] Regarding step 2100, when determining to perform partial privacy display mode, controlling at least a portion of the first sub-pixel of the first display area and the first sub-pixel of the second display area to emit light includes: controlling the third pixel P11 of the first display area AA1 and the first pixel P21 of the second display area AA2 to emit light, as shown in FIG1B.

[0181] In one possible implementation, regarding the display panel corresponding to FIG5A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protected first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is divided into a privacy-protected third pixel portion P11 and a normally displayed fourth pixel portion P12, in different display modes, regarding step S100, when determining to enter the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when determining to enter the normal display mode, controlling all the first sub-pixels P1 of the first display area AA1 and all the second sub-pixels P2 of the second display area AA2 to emit light, as shown in FIG5C;

[0182] Regarding step S200, when determining to perform partial privacy display mode, controlling at least a portion of the first sub-pixels of the first display area and the first sub-pixel portion of the second display area to emit light includes: controlling all the first sub-pixels P1 of the first display area AA1 and the first pixel portion P21 of the second display area AA2 to emit light, as shown in Figure 5B.

[0183] In one possible implementation, regarding the display panel corresponding to FIG9A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protected first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is not divided, in different display modes, regarding step S100, when it is determined to enter the normal display mode, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined to enter the normal display mode, controlling all the first sub-pixels P1 of the first display area AA1 and the second pixel portion P22 of the second display area AA2 to emit light, as shown in FIG9C;

[0184] Regarding step S200, when determining to perform partial privacy display mode, controlling at least a portion of the first sub-pixels of the first display area and the first sub-pixel portion of the second display area to emit light includes: controlling all the first sub-pixels P1 of the first display area AA1 and the first pixel portion P21 of the second display area AA2 to emit light, as shown in FIG9B.

[0185] In one possible implementation, the driving method further includes step S300: when a difference in brightness between the first display area and the second display area is determined during normal display mode, a stored relation table is called to adjust the brightness of the first display area and the second display area to be consistent. The relation table includes a gamma correction relation table (Gama Look-Up Table, Gama LUT), and / or a moiré correction relation table (Demura LUT), and / or a brightness attenuation relation table (De Burn-in LUT).

[0186] Specifically, for the display panel structure corresponding to Figure 1A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protected first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is divided into two normally displayed third pixel portions P11 and fourth pixel portions P12, a first Gama LUT, a second Gama LUT, and a third Gama LUT can be stored in the display device. The first Gama LUT corresponds to the first display area AA1 and is used to correct the brightness of the first display area AA1 in privacy-protected display mode; the second Gama LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in privacy-protected mode; the third Gama LUT corresponds to both the first display area AA1 and the second display area AA2 and is used to correct the brightness of both the first display area AA1 and the second display area AA2 in normal display (i.e., shared display) mode. Furthermore, the display device can also store a first Demura LUT and a second Demura LUT, wherein the first Demura... The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the privacy display mode; the second DeBurn-in LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the shared display mode; in addition, the display device may also store a first DeBurn-in LUT, a second DeBurn-in LUT, and a third DeBurn-in LUT, wherein the first DeBurn-in LUT corresponds to the first display area AA1 and is used to correct the brightness of the first display area AA1 in the privacy display mode; the second DeBurn-in LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in the privacy display mode; the third DeBurn-in LUT corresponds to the first display area AA1 and the second display area AA2 and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the shared display mode.

[0187] Specifically, for the display panel structure corresponding to Figure 1A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protecting first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is divided into two normally displayed third pixel portions P11 and fourth pixel portions P12, the display device can store a first Gama LUT and a second Gama LUT; wherein, the first Gama LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 when displaying privacy; the second Gama LUT corresponds to the first display area AA1 and the second display area AA2 and is used to correct the brightness of the first display area AA1 when displaying privacy, and to correct the brightness of the first display area AA1 and the second display area AA2 when sharing the display; in addition, the display device can store a first Demura LUT and a second Demura LUT; wherein, the first Demura The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 when used for privacy display. The second Demura LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 when used for shared display. In addition, the display device may store a first De Burn-in LUT, a second De Burn-in LUT, and a third De Burn-in LUT. The first De Burn-in LUT corresponds to the first display area AA1 and is used to correct the brightness of the first display area AA1 when used for privacy display. The second De Burn-in LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 when used for privacy display and shared display. The third De Burn-in LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 when used for shared display.

[0188] Specifically, for the display panel structure corresponding to Figure 9A, that is, when the second sub-pixel P2 of the second display area AA2 is divided into a privacy-protected first pixel portion P21 and a normally displayed second pixel portion P22, and the first sub-pixel P1 of the first display area AA1 is not divided, a first Gama LUT, a second Gama LUT, and a third Gama LUT can be stored in the display device. The first Gama LUT corresponds to the first display area AA1 and is used to correct the brightness of the first display area AA1 in privacy-protected display mode and shared display mode. The second Gama LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in privacy-protected mode. The third Gama LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in shared display mode. Furthermore, the display device can also store a first Demura LUT and a second Demura LUT. The LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the privacy display mode; the second Demura LUT corresponds to the first display area AA1 and the second display area AA2, and is used to correct the brightness of the first display area AA1 and the second display area AA2 in the shared display mode; in addition, the display device may also store a first De Burn-in LUT, a second De Burn-in LUT, and a third De Burn-in LUT, wherein the first De Burn-in LUT corresponds to the first display area AA1 and is used to correct the brightness of the first display area AA1 in the privacy display mode and the shared display mode; the second De Burn-in LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in the privacy display mode; the third De Burn-in LUT corresponds to the second display area AA2 and is used to correct the brightness of the second display area AA2 in the shared display mode.

[0189] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0190] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations to the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention also intends to include these modifications and variations.

Claims

1. A display panel, wherein, include: The substrate has a first display area and a second display area; Multiple first sub-pixels are located in the first display area; Multiple second sub-pixels are located in the second display area; At least one of the plurality of second sub-pixels includes: a first pixel portion and a second pixel portion; wherein the light-emitting area of ​​the first pixel portion is smaller than the light-emitting area of ​​the second pixel portion.

2. The display panel as claimed in claim 1, wherein, At least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the light-emitting area of ​​the third pixel portion is equal to the light-emitting area of ​​the fourth pixel portion.

3. The display panel as claimed in claim 1, wherein, At least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the light-emitting area of ​​the third pixel portion is smaller than the light-emitting area of ​​the fourth pixel portion.

4. The display panel as described in claim 2 or 3, wherein, The light-emitting area of ​​the fourth pixel is equal to the light-emitting area of ​​the second pixel.

5. The display panel as claimed in claim 1, wherein, At least one of the plurality of first sub-pixels is a single connected structure.

6. The display panel as claimed in claim 5, wherein, The light-emitting area of ​​the first sub-pixel is greater than or equal to the sum of the light-emitting areas of the first pixel portion and the second pixel portion.

7. The display panel according to any one of claims 1-6, wherein, The display panel includes: a first shielding layer; the first shielding layer includes: a first opening and a second opening; the orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the first pixel portion on the substrate; the orthographic projection of the second opening on the substrate overlaps with the orthographic projection of the second pixel portion on the substrate. The projected area of ​​the first opening on the substrate is smaller than the projected area of ​​the second opening on the substrate.

8. The display panel as claimed in claim 7, wherein, At least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the first masking layer further includes: a third opening and a fourth opening; the orthographic projection of the third opening on the substrate overlaps with the orthographic projection of the third pixel portion on the substrate; the orthographic projection of the fourth opening on the substrate overlaps with the orthographic projection of the fourth pixel portion on the substrate. The projected area of ​​the fourth opening on the substrate is equal to the projected area of ​​the second opening on the substrate.

9. The display panel as claimed in claim 8, wherein, The projected area of ​​the third opening on the substrate is equal to the projected area of ​​the fourth opening on the substrate.

10. The display panel as claimed in claim 8, wherein, The projected area of ​​the third opening on the substrate is smaller than the projected area of ​​the fourth opening on the substrate.

11. The display panel as claimed in claim 7, wherein, At least one of the plurality of first sub-pixels is an integrally connected structure; the first shielding layer further includes: a fifth opening; the orthographic projection of the fifth opening on the substrate overlaps with the orthographic projection of the first sub-pixel on the substrate.

12. The display panel as claimed in claim 11, wherein, The projected area of ​​the fifth opening on the substrate is greater than or equal to the sum of the projected areas of the first opening and the second opening on the substrate.

13. The display panel according to any one of claims 7-12, wherein, The first opening includes: a plurality of first sub-openings; the plurality of first sub-openings of the first opening are arranged in an array.

14. The display panel as claimed in claim 13, wherein, The orthographic projection of the first sub-opening onto the substrate is rectangular, hexagonal, octagonal, circular, or elliptical.

15. The display panel according to any one of claims 1-14, wherein, The first pixel portion includes: a first anode portion; the second pixel portion includes: a second anode portion; The orthographic projection area of ​​the first anode portion on the substrate is smaller than the orthographic projection area of ​​the second anode portion on the substrate.

16. The display panel as claimed in claim 15, wherein, At least one of the plurality of first sub-pixels includes: a third pixel portion and a fourth pixel portion; the third pixel portion has a third anode portion and the fourth pixel portion has a fourth anode portion; The projected area of ​​the third anode portion on the substrate is equal to the projected area of ​​the fourth anode portion on the substrate.

17. The display panel as claimed in claim 16, wherein, At least one of the plurality of first sub-pixels is an integrally connected structure; the first sub-pixel portion includes: a fifth anode portion; The projected area of ​​the fifth anode portion on the substrate is greater than or equal to the sum of the projected areas of the first anode portion and the second anode portion on the substrate.

18. The display panel according to any one of claims 7-17, wherein, The display panel further includes: a second light-shielding layer located on the side of the first light-shielding layer facing the substrate; The second light-shielding layer includes: a first light-emitting port and a second light-emitting port; the orthographic projection of the first light-emitting port on the substrate overlaps with the orthographic projection of the first opening on the substrate; the orthographic projection of the second light-emitting port on the substrate overlaps with the orthographic projection of the second opening on the substrate.

19. The display panel according to any one of claims 7-18, wherein, The display panel further includes: a lens layer located on the side of the first light-shielding layer opposite to the substrate; The lens layer includes: a first lens and a second lens; the orthographic projection of the first lens onto the substrate covers the orthographic projection of the first opening onto the substrate; the orthographic projection of the second lens onto the substrate covers the orthographic projection of the second opening onto the substrate.

20. The display panel according to any one of claims 7-19, wherein, The display panel further includes: an encapsulation layer, and a touch layer located on the side of the encapsulation layer opposite to the substrate; the first light-shielding layer is located on the side of the encapsulation layer opposite to the substrate.

21. The display panel according to any one of claims 1-20, wherein, Of the first sub-pixel and the second sub-pixel, at least the second sub-pixel includes: a plurality of light emitters stacked along a direction perpendicular to the substrate; the light emitters include one or a combination of the following film layers stacked together: Hole transport layer; Emissive layer; Electron transport layer.

22. The display panel according to any one of claims 15-21, wherein, The second sub-pixel includes: a second pixel circuit; Both the first anode portion and the second anode portion are electrically connected to the second pixel circuit.

23. The display panel as claimed in claim 22, wherein, The second pixel circuit includes at least: a first light-emitting control sub-circuit and a second light-emitting control sub-circuit; the display panel further includes: a first light-emitting control line and a second light-emitting control line; The first light emission control sub-circuit is electrically connected to the first light emission control line and the first anode portion, and is configured to drive the first pixel portion to emit light under the control of the first light emission control line; The second light emission control sub-circuit is electrically connected to the second light emission control line and the second anode portion, and is configured to drive the second pixel portion to emit light under the control of the second light emission control line.

24. The display panel according to any one of claims 15-21, wherein, The second sub-pixel includes: a first sub-pixel circuit and a second sub-pixel circuit; The first anode portion is electrically connected to the first sub-pixel circuit; the second anode portion is electrically connected to the second sub-pixel circuit.

25. The display panel as claimed in claim 24, wherein, The plurality of second sub-pixels includes: a first pixel row and a second pixel row; the first pixel row and the second pixel row extend along a first direction and are alternately arranged along a second direction; the first pixel row includes: a plurality of first pixel portions; the second pixel row includes: a plurality of second pixel portions; The display panel further includes: a first pixel row control line and a second pixel row control line; the first pixel row control line is electrically connected to the first pixel portion of the first pixel row, and the second pixel row control line is electrically connected to the second pixel portion of the second pixel row; the first pixel row control line is configured to provide a signal to the first pixel portion of the first pixel row, and the second pixel row control line is configured to provide a signal to the second pixel portion of the second pixel row.

26. A display device, wherein, Includes the display panel as described in any one of claims 1-25.

27. A driving method for a display panel as described in any one of claims 1-25, wherein, include: When it is determined that the normal display mode is to be performed, at least a portion of the first sub-pixel of the first display area and at least a portion of the second pixel of the second display area are controlled to emit light; When a partial privacy display mode is selected, at least a portion of the first sub-pixel in the first display area and the first pixel portion in the second display area are controlled to emit light.

28. The driving method as described in claim 27, wherein, When it is determined that a normal display mode is to be entered, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined that a normal display mode is to be entered, controlling the fourth pixel portion of the first display area and the second pixel portion of the second display area to emit light. When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixel in the first display area and the first sub-pixel portion in the second display area to emit light includes: controlling the third pixel portion in the first display area and the first pixel portion in the second display area to emit light.

29. The driving method as described in claim 27, wherein, When it is determined that a normal display mode is to be entered, controlling the first sub-pixel of the first display area and at least the second pixel of the second display area to emit light includes: when it is determined that a normal display mode is to be entered, controlling all the first sub-pixels of the first display area and all the second sub-pixels of the second display area to emit light; When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixels in the first display area and the first sub-pixels in the second display area to emit light includes: controlling all the first sub-pixels in the first display area and the first pixels in the second display area to emit light.

30. The driving method as described in claim 29, wherein, When it is determined that a normal display mode is to be entered, controlling the first sub-pixel of the first display area and at least the second pixel portion of the second display area to emit light includes: when it is determined that a normal display mode is to be entered, controlling all the first sub-pixels of the first display area and the second pixel portion of the second display area to emit light; When determining to perform a partial privacy display mode, controlling at least a portion of the first sub-pixels in the first display area and the first pixel portion in the second display area to emit light includes: controlling all the first sub-pixels in the first display area and the first pixel portion in the second display area to emit light.

31. The driving method according to any one of claims 27-30, wherein, The driving method further includes: when a difference in brightness between the first display area and the second display area is determined during normal display mode, calling a stored relation table to adjust the brightness of the first display area and the second display area.

Images