Display substrate and display device

Abstract

A display substrate, comprising a first frame area (B1) and a second frame area (B2) which are communicated with each other, wherein the first frame area (B1) comprises a bending area (B02) located on one side of a display area (AA) in a first direction (D1). The display substrate comprises: a base (10); a plurality of sub-pixels (PX) arranged on the base (10) and located in the display area (AA); a plurality of gate driving circuits located in the second frame area (B2); and at least one first peripheral control line (L1) and a plurality of second peripheral control lines (L2, L3) located in the first frame area (B1). The potential of a signal transmitted by each first peripheral control line (L1) is lower than the potential of a signal transmitted by each second peripheral control line (L2, L3). In the bending area (B02), at least one second peripheral control line (L2) is located between at least one first peripheral control line (L1) and the boundary of the display substrate.

Description

Display substrate and display device Technical Field

[0001] This article relates to but is not limited to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diodes (OLEDs) and quantum-dot light-emitting diodes (QLEDs) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, light weight, flexibility and low cost.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] This embodiment provides a display substrate and a display device.

[0006] In one aspect, this embodiment provides a display substrate comprising: a display area and a frame area surrounding the display area. The frame area comprises a first frame area and a second frame area that are interconnected, the first frame area including at least a bend area located on one side of the display area along a first direction. The display substrate comprises: a substrate, a plurality of sub-pixels disposed on one side of the substrate and located in the display area, a plurality of gate drive circuits located in the second frame area, at least one first peripheral control line located in the first frame area, and a plurality of second peripheral control lines. The plurality of gate drive circuits are electrically connected to the plurality of sub-pixels and configured to provide a plurality of pixel control signals to the plurality of sub-pixels. At least one first peripheral control line is connected to the plurality of gate drive circuits. A portion of the plurality of second peripheral control lines are connected to the plurality of gate drive circuits; the potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line. In the bend area, at least one of the plurality of second peripheral control lines is located between the at least one first peripheral control line and a boundary of the display substrate.

[0007] In some exemplary embodiments, the display substrate further includes: a plurality of peripheral data lines located in the first border area, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; in a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and a boundary of the display substrate; the second direction intersects the first direction.

[0008] In some exemplary embodiments, in the bending region, a minimum distance between the at least one first peripheral control line and a boundary of the display substrate is greater than or equal to 1250 micrometers.

[0009] In some exemplary embodiments, the at least one first peripheral control line is configured to transmit a constant voltage signal, and a potential of the constant voltage signal is less than or equal to -6V.

[0010] In some exemplary embodiments, at least one of the plurality of sub-pixels includes a pixel circuit and a light-emitting element connected to the pixel circuit. The pixel circuit includes at least a driving transistor, a data writing transistor, and a compensation transistor; the gate of the data writing transistor is connected to a first scan line, the first electrode of the data writing transistor is connected to a data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; the gate of the driving transistor is connected to the second electrode of the compensation transistor, the second electrode of the driving transistor is connected to the first electrode of the compensation transistor, and the gate of the compensation transistor is connected to a second scan line. The plurality of gate driving circuits include at least one first scan driving circuit and at least one second scan driving circuit. The at least one first scan driving circuit is configured to provide a first scan signal to the first scan line, and the at least one second scan driving circuit is configured to provide a second scan signal to the second scan line. The plurality of second peripheral control lines include at least a second start signal line and a second scan driving output line connected to the at least one second scan driving circuit; the at least one first peripheral control line is located between the second start signal line and the second scan driving output line.

[0011] In some exemplary embodiments, the pixel circuit further includes a first reset transistor, wherein a gate of the first reset transistor is connected to a first reset control line, a first electrode of the first reset transistor is configured to receive a first initial signal, and a second electrode of the first reset transistor is connected to a second electrode of the drive transistor. In the bending region, a second peripheral control line of the plurality of second peripheral control lines that is closest to a boundary of the display substrate is configured to transmit the first initial signal.

[0012] In some exemplary embodiments, in the bending region, a minimum distance between a second peripheral signal line among the plurality of second peripheral control lines closest to the boundary of the display substrate and the boundary of the display substrate is greater than or equal to 400 micrometers.

[0013] In some exemplary embodiments, the first border region further includes: a first signal access region located on a side of the bending region away from the display region; the display substrate further includes: a plurality of first contact pads located in the first signal access region and arranged along a second direction; the second direction intersects the first direction; the plurality of first contact pads include: at least one first control contact pad connected to the at least one first peripheral control line, and a plurality of second control contact pads connected to the plurality of second peripheral control lines. In the second direction, at least one of the plurality of second control contact pads is located between the at least one first control contact pad and a boundary of the display substrate.

[0014] In some exemplary embodiments, the at least one first peripheral control line is located between a first second peripheral control line and a second second peripheral control line. In the second direction, the at least one first control contact pad is located between a second control contact pad connected to the first second peripheral control line and a second control contact pad connected to the second second peripheral control line.

[0015] In some exemplary embodiments, the at least one first peripheral control line is located between a first second peripheral control line and a second second peripheral control line; the first second peripheral control line is located on a side of the at least one first peripheral control line closer to a boundary of the display substrate; and in the second direction, the at least one first control contact pad is located on a side of the second control contact pad connected to the second second peripheral control line that is farther from the boundary of the display substrate.

[0016] In some exemplary embodiments, the first border region further includes: a first subregion located on a side of the bending region proximal to the display region, the first subregion being connected to the second border region. The display substrate further includes: a plurality of electrostatic discharge circuits located in the first subregion, the plurality of electrostatic discharge circuits being disposed adjacent to the plurality of gate drive circuits. The plurality of electrostatic discharge circuits are arranged in a plurality of rows along the first direction, each row of electrostatic discharge circuits including a plurality of electrostatic discharge circuits disposed along a second direction intersecting the first direction. The at least one first peripheral signal line is located between two adjacent rows of electrostatic discharge circuits.

[0017] In some exemplary embodiments, the plurality of electrostatic release circuits are arranged as a first row of electrostatic release circuits, a second row of electrostatic release circuits, and a third row of electrostatic release circuits in a direction away from the display area, and the at least one first peripheral signal line is located between the first row of electrostatic release circuits and the second row of electrostatic release circuits.

[0018] In some example embodiments, the display substrate includes a plurality of first peripheral control lines, and the plurality of electrostatic discharge circuits are connected to one of the first peripheral control lines.

[0019] In some exemplary embodiments, the plurality of gate driver circuits include a first group of gate driver circuits and a second group of gate driver circuits located on both sides of the display area along a second direction intersecting the first direction. The first group of gate driver circuits is connected to at least one first peripheral control line, and the second group of gate driver circuits is connected to at least one first peripheral control line. The first group of gate driver circuits includes the same number of gate driver circuits as the second group of gate driver circuits.

[0020] On the other hand, this embodiment provides a display device including the display substrate as described above.

[0021] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0022] Summary of the Figures

[0023] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0024] FIG1 is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0025] FIG2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0026] FIG3 is a schematic diagram illustrating the configuration of a gate drive circuit according to at least one embodiment of the present disclosure;

[0027] FIG4A is a partial cross-sectional schematic diagram of a display area according to at least one embodiment of the present disclosure;

[0028] FIG4B is another partial cross-sectional schematic diagram of the display area of ​​at least one embodiment of the present disclosure;

[0029] FIG5 is a schematic diagram of local wiring in a first border area according to at least one embodiment of the present disclosure;

[0030] FIG6 is a partial schematic diagram of a first border area according to at least one embodiment of the present disclosure;

[0031] FIG7 is a partial enlarged schematic diagram of area S1 in FIG6 ;

[0032] FIG8 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure;

[0033] FIG9 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure;

[0034] FIG10 is another partial wiring diagram of the first frame area according to at least one embodiment of the present disclosure;

[0035] FIG11 is another partial schematic diagram of the first border area according to at least one embodiment of the present disclosure;

[0036] FIG12 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure;

[0037] FIG13 is a partial enlarged schematic diagram of area S2 in FIG6 ;

[0038] FIG14 is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in FIG13 ;

[0039] FIG. 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure.

[0040] Details

[0041] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person skilled in the art can easily understand that the method and content can be transformed into other forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0042] In the drawings, the size of one or more components, layer thicknesses, or regions may be exaggerated for clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to these dimensions, and the shapes and sizes of one or more components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate idealized examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0043] In this specification, ordinal numbers such as "first," "second," and "third" are provided to avoid confusion among constituent elements, and are not intended to limit the number. "Multiple" in this disclosure means two or more.

[0044] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the orientation of the constituent elements being described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced depending on the circumstances.

[0045] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, or a detachable connection, or an integral connection; it can be a mechanical connection, or a connection; it can be a direct connection, or an indirect connection through an intermediate piece, or a connection between the two elements. For those of ordinary skill in the art, the meaning of the above terms in this disclosure can be understood according to the circumstances. Among them, "connection" can include "electrical connection", and "electrical connection" can include the situation where constituent elements are connected together through an element with some electrical function. There is no special restriction on "elements with some electrical function" as long as they can transmit electrical signals between connected constituent elements. Examples of "elements with some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with multiple functions.

[0046] In this specification, a transistor refers to a device that includes at least three terminals: a gate (gate electrode), a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, channel region, and source. In this specification, the channel region refers to the region through which current primarily flows.

[0047] In this specification, the first electrode can be a drain and the second electrode can be a source, or the first electrode can be a source and the second electrode can be a drain. Furthermore, the gate electrode can also be referred to as a control electrode. The functions of "source" and "drain" are sometimes interchangeable when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source" and "drain" can be interchangeable.

[0048] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0049] In this specification, circles, ellipses, triangles, rectangles, trapezoids, pentagons or hexagons are not in the strict sense, but may be approximate circles, approximate ellipses, approximate triangles, approximate rectangles, approximate trapezoids, approximate pentagons or approximate hexagons, etc. There may be some small deformations caused by tolerances, such as chamfers, arc edges and deformations.

[0050] In this specification, "about" and "approximately" are not strictly defined, and allow for process and measurement errors. In this disclosure, "same" includes situations where the values ​​differ by less than 10%, such as situations where the values ​​differ by less than 5%.

[0051] In this specification, "A extends along direction B" means that A may include a main portion and a secondary portion connected to the main portion, the main portion being a line, line segment, or strip, extending along direction B, and the length of the main portion extending along direction B being greater than the length of the secondary portion extending along other directions. Throughout this specification, "A extends along direction B" means "the main portion of A extends along direction B."

[0052] As used herein, "A and B are in the same layer" means that A and B are formed simultaneously through the same patterning process. "Same layer" does not always mean that the thickness or height of the layer is the same in a cross-sectional view. "The orthographic projection of A includes the orthographic projection of B" means that the orthographic projection of B falls within the orthographic projection of A, or that the orthographic projection of A covers the orthographic projection of B.

[0053] With the development of display technology, flexible display products are gaining increasing attention. The lower bezel of the display substrate of flexible display products bends and narrows in the bending area. This bending area can cause reliability corrosion along the edge of the lower bezel, which can easily cause display problems.

[0054] This embodiment provides a display substrate, comprising: a display area and a frame area surrounding the display area. The frame area comprises a first frame area and a second frame area that are interconnected. The first frame area includes at least a bend area located on one side of the display area along a first direction. The display substrate comprises: a substrate, a plurality of sub-pixels, a plurality of gate drive circuits, at least one first peripheral control line, and a plurality of second peripheral control lines. The plurality of sub-pixels are disposed on one side of the substrate and located in the display area. The plurality of gate drive circuits are located in the second frame area and electrically connected to the plurality of sub-pixels, configured to provide a plurality of pixel control signals to the plurality of sub-pixels. At least one first peripheral control line is located in the first frame area and connected to the plurality of gate drive circuits. A plurality of second peripheral control lines are located in the first frame area, with some of the plurality of second peripheral control lines connected to the plurality of gate drive circuits. The potential of the signal transmitted by each first peripheral control line is lower than the potential of the signal transmitted by each second peripheral control line. In the bend area, at least one of the plurality of second peripheral control lines is located between the at least one first peripheral control line and the boundary of the display substrate. In other words, the at least one second peripheral control line is located on a side of the at least one first peripheral control line close to the boundary of the display substrate. The at least one first peripheral control line is not the line closest to the boundary of the display substrate.

[0055] The display substrate provided in this embodiment increases the distance between the first peripheral control line and the boundary of the display substrate by arranging the first peripheral control line with a lower transmission potential on the side away from the boundary of the display substrate of at least one second peripheral control line with a higher transmission potential, which is beneficial to avoiding reliability corrosion of the first peripheral control line.

[0056] In some exemplary embodiments, the display substrate may further include: a plurality of peripheral data lines located in the first border region, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels. In the second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and a boundary of the display substrate. The second direction intersects the first direction; for example, the second direction may be perpendicular to the first direction. In some examples, the plurality of second peripheral control lines may be located on both sides of the plurality of peripheral data lines in the second direction, and the at least one first peripheral control line may be located on a side of the plurality of peripheral data lines close to the at least one second peripheral control line. This embodiment is not limited to this.

[0057] In some exemplary embodiments, at least one first peripheral control line may be configured to transmit a constant voltage signal, and the potential of the constant voltage signal may be less than or equal to -6V. In some examples, the potential of the signal transmitted by at least one first peripheral control line may be less than or equal to -6V and greater than or equal to -12V. For example, the potential range of the signal transmitted by the first peripheral control line may be -7V to -8V. The first peripheral control line of this example may be a trace that transmits the lowest potential in the first border area. This example prevents the first peripheral control line from being subjected to reliability corrosion by setting the first peripheral control line that transmits the lowest potential away from the boundary of the display substrate.

[0058] In some exemplary embodiments, the first border region may further include: a first signal access region located on a side of the bending region away from the display region. The display substrate may further include: a plurality of first contact pads located in the first signal access region and arranged along the second direction. The plurality of first contact pads may include: at least one first control contact pad connected to the at least one first peripheral control line, and a plurality of second control contact pads connected to the plurality of second peripheral control lines. In the second direction, at least one of the plurality of second control contact pads may be located between the at least one first control contact pad and a boundary of the display substrate. In other words, in the second direction, at least one second control contact pad may be located between the at least one first control contact pad and a boundary of the display substrate. In some examples, at least one first peripheral control line may be located between a first second peripheral control line and a second second peripheral control line; and in the second direction, the at least one first control contact pad may be located between a second control contact pad connected to the first second peripheral control line and a second control contact pad connected to the second second peripheral control line. In other examples, at least one first peripheral control line may be located between a first second peripheral control line and a second second peripheral control line; the first second peripheral control line may be located on a side of the at least one first peripheral control line that is closer to the boundary of the display substrate; and in the second direction, the at least one first control contact pad may be located on a side of the second control contact pad connected to the second second peripheral control line that is further away from the boundary of the display substrate. In this example, by arranging the first control contact pad connected to the first peripheral control line away from the boundary of the display substrate, signal transmission of the first peripheral control line and proper arrangement of the first peripheral control line within the first border area can be ensured.

[0059] In some exemplary embodiments, the first border area may further include: a first sub-area located on a side of the bending area close to the display area, and the first sub-area is connected to the second border area. The display substrate may further include: a plurality of electrostatic release circuits located in the first sub-area, and the plurality of electrostatic release circuits may be arranged adjacent to the plurality of gate drive circuits. The plurality of electrostatic release circuits may be arranged in a plurality of rows along the first direction, and each row of electrostatic release circuits includes a plurality of electrostatic release circuits arranged along the second direction. The at least one first peripheral signal line may be located between two adjacent rows of electrostatic release circuits. This example can reduce the length of the first peripheral signal line by arranging the first peripheral signal line between adjacent rows of electrostatic release circuits, which is beneficial to reducing the signal loading of the first peripheral signal line.

[0060] The solution of this embodiment is illustrated below through some examples.

[0061] Figure 1 is a schematic diagram of a display substrate of at least one embodiment of the present disclosure. In some examples, as shown in Figure 1, the display substrate may include: a display area AA and a border area BB located around the display area AA. The border area BB may include: a first border area B1 located on one side of the display area AA and a second border area B2 located on the other side of the display area AA. For example, the first border area B1 may be located on one side of the display area AA along the first direction D1. The first border area B1 and the second border area B2 may be connected. For example, the first border area B1 may be the lower border area of ​​the display substrate, and the second border area B2 may include: a left border area B21, a right border area B22 and an upper border area B23 of the display substrate.

[0062] In some examples, as shown in FIG1 , the display area AA may be a flat area including a plurality of sub-pixels PX that make up a pixel array. The plurality of sub-pixels PX may be configured to display dynamic images or still images. The display area AA may be referred to as an active area. In some examples, the display area AA may be a rectangle, such as a rounded rectangle. However, this embodiment is not limited thereto. For example, the display area may be a circular, elliptical, or other shape. In some examples, the display substrate may be a flexible substrate, and thus the display substrate may be deformable, such as being curled, bent, folded, or rolled up.

[0063] In some examples, the display area AA may include: a display structure layer arranged on a substrate, or may include a display structure layer and a touch structure layer arranged in sequence on the substrate. For example, the display substrate may integrate a touch structure to form a touch structure on a thin film package (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The Touch on TFE structure mainly includes a flexible multi-layer surface covering type (FMLOC, Flexible Multi-Layer On Cell) structure and a flexible single-layer surface covering type (FSLOC, Flexible Single-Layer On Cell) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The driving chip (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0064] In some examples, the display structure layer may include multiple sub-pixels PX, multiple gate lines GL, and multiple data lines DL. The multiple gate lines GL may extend along the second direction D2 and be arranged along the first direction D1, and the multiple data lines DL may extend along the first direction D1 and be arranged along the second direction D2. The first direction D1 and the second direction D2 may intersect; for example, the first direction D1 may be perpendicular to the second direction D2. The orthographic projections of the multiple gate lines GL and the multiple data lines DL on the substrate may intersect to form multiple sub-pixel regions. One sub-pixel PX may be disposed within one sub-pixel region. The multiple data lines DL may be electrically connected to the multiple sub-pixels PX and may be configured to provide data signals to the multiple sub-pixels PX. The multiple gate lines GL may be electrically connected to the multiple sub-pixels PX and may be configured to provide pixel control signals to the multiple sub-pixels PX. For example, the pixel control signals may include scan signals, or may include scan signals and light-emitting control signals, or may include scan signals, reset control signals, and light-emitting control signals.

[0065] In some examples, a pixel unit of the display area AA may include three sub-pixels, and the three sub-pixels may be a first sub-pixel emitting a first color light (e.g., red light), a second sub-pixel emitting a second color light (e.g., green light), and a third sub-pixel emitting a third color light (e.g., blue light). However, this embodiment is not limited to this. In some examples, a pixel unit may include four sub-pixels, and the four sub-pixels may be a sub-pixel emitting red light, a sub-pixel emitting green light, a sub-pixel emitting blue light, and a sub-pixel emitting white light. For another example, a pixel unit may include four sub-pixels, and the four sub-pixels may include a sub-pixel emitting red light, a sub-pixel emitting blue light, and two sub-pixels emitting green light.

[0066] In some examples, a sub-pixel PX may include: a pixel circuit and a light-emitting element electrically connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C or 8T1C structure. In the above circuit structure, T refers to a thin film transistor, C refers to a capacitor, the number before T represents the number of thin film transistors in the circuit, and the number before C represents the number of capacitors in the circuit. In some examples, the multiple transistors in the pixel circuit may include P-type transistors and N-type transistors. In other examples, the multiple transistors in the pixel circuit may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel circuit can simplify the process flow, reduce the process difficulty of the display substrate, and improve the product yield.

[0067] In some examples, the shape of the light-emitting elements of a sub-pixel can be rectangular, rhombus, pentagonal, or hexagonal. When a pixel unit includes three sub-pixels, the light-emitting elements of the three sub-pixels can be arranged horizontally, vertically, or in a triangular pattern; when a pixel unit includes four sub-pixels, the light-emitting elements of the four sub-pixels can be arranged horizontally, vertically, or in a square pattern. However, this embodiment is not limited to this.

[0068] In some examples, the light-emitting element may be any one of a light-emitting diode (LED), an organic light-emitting diode (OLED), a quantum dot light-emitting diode (QLED), a micro-LED (including mini-LED or micro-LED), etc. For example, the light-emitting element may be an OLED, which may emit red light, green light, blue light, or white light, etc. when driven by its corresponding pixel circuit. The color of the light emitted by the light-emitting element may be determined as needed. In some examples, the light-emitting element may include: an anode, a cathode, and an organic light-emitting layer located between the anode and the cathode. The anode of the light-emitting element may be electrically connected to the corresponding pixel circuit. However, this embodiment is not limited to this.

[0069] Figure 2 is an equivalent circuit diagram of a pixel circuit of at least one embodiment of the present disclosure. The pixel circuit of this example is illustrated using an 8T1C structure as an example. In some examples, as shown in Figure 2, the pixel circuit of this example may include eight pixel transistors (i.e., a first pixel transistor T1 to an eighth pixel transistor T8) and a storage capacitor Cst. The first pixel transistor T1 may also be referred to as a first reset transistor, the second pixel transistor T2 may also be referred to as a compensation transistor, the third pixel transistor T3 may also be referred to as a drive transistor, the fourth pixel transistor T4 may also be referred to as a data write transistor, the fifth pixel transistor T5 may also be referred to as a first light-emitting control transistor, the sixth pixel transistor T6 may also be referred to as a second light-emitting control transistor, the seventh pixel transistor T7 may also be referred to as a second reset transistor, and the eighth pixel transistor T8 may also be referred to as a third reset transistor. The light-emitting element EL may include an anode, a cathode, and an organic light-emitting layer disposed between the anode and the cathode.

[0070] In some examples, the first pixel transistor T1 and the third pixel transistor T3 to the eighth pixel transistor T8 may be first-type transistors, such as P-type transistors, and the second pixel transistor T2 may be a second-type transistor, such as N-type transistors. However, this embodiment is not limited to this. For example, the plurality of pixel transistors in the pixel circuit may all be P-type transistors, or may all be N-type transistors.

[0071] In some examples, the first type of transistor of the pixel circuit (for example, including the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8) can be a low-temperature polysilicon thin film transistor, and the second type of transistor of the pixel circuit (for example, including the second pixel transistor T2) can be an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin film transistors have the advantages of high mobility and fast charging, while oxide thin film transistors have the advantages of low leakage current. Integrating low-temperature polysilicon thin film transistors and oxide thin film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPS+Oxide) display substrate can take advantage of the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0072] In some examples, as shown in FIG2 , the pixel circuit can be electrically connected to a first scan line GL1, a second scan line GL2, a data line DL, a first power line PL1, a second power line PL2, an emission control line EML, a first initial signal line INIT1, a second initial signal line INIT2, a third initial signal line INIT3, a first reset control line RST1, and a second reset control line RST2. The first power line PL1 can be configured to provide a constant first voltage signal VDD to the pixel circuit, and the second power line PL2 can be configured to provide a constant second voltage signal VSS to the pixel circuit, with the first voltage signal VDD being greater than the second voltage signal VSS. The first scan line GL1 can be configured to provide a first scan signal SCAN1 to the pixel circuit. The second scan line GL2 can be configured to provide a second scan signal SCAN2 to the pixel circuit. The data line DL can be configured to provide a data signal to the pixel circuit. The emission control line EML can be configured to provide an emission control signal EM to the pixel circuit. The first reset control line RST1 can be configured to provide a first reset control signal RESET1 to the pixel circuit. The second reset control line may be configured to provide a second reset control signal RESET2 to the pixel circuit.

[0073] In some examples, as shown in FIG2 , the gate of the third pixel transistor T3 is electrically connected to the first node N1, the first electrode of the third pixel transistor T3 is electrically connected to the second node N2, and the second electrode of the third pixel transistor T3 is electrically connected to the third node N3. The gate of the fourth pixel transistor T4 is electrically connected to the first scan line GL1, the first electrode of the fourth pixel transistor T4 is electrically connected to the data line DL, and the second electrode of the fourth pixel transistor T4 is electrically connected to the second node N2. The gate of the second pixel transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second pixel transistor T2 is electrically connected to the third node N3, and the second electrode of the second pixel transistor T2 is electrically connected to the first node N1. The gate of the fifth pixel transistor T5 is electrically connected to the emission control line EML, the first electrode of the fifth pixel transistor T5 is electrically connected to the first power line PL1, and the second electrode of the fifth pixel transistor T5 is electrically connected to the second node N2. The gate of the sixth pixel transistor T6 is electrically connected to the emission control line EML, the first electrode of the sixth pixel transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth pixel transistor T6 is electrically connected to the fourth node N4. The gate of the first pixel transistor T1 is electrically connected to the first reset control line RST1, the first electrode of the first pixel transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first pixel transistor T1 is electrically connected to the third node N3. The first pixel transistor T1 can be configured to reset the third node N3. The gate of the seventh pixel transistor T7 is electrically connected to the second reset control line RST2, the first electrode of the seventh pixel transistor T7 is electrically connected to the second initial signal line INIT2, and the second electrode of the seventh pixel transistor T7 is electrically connected to the fourth node N4. The seventh pixel transistor T7 can be configured to reset the fourth node N4. The gate of the eighth pixel transistor T8 is electrically connected to the second reset control line RST2, the first electrode of the eighth pixel transistor T8 is electrically connected to the third initial signal line INIT3, and the second electrode of the eighth pixel transistor T8 is electrically connected to the second node N2. The eighth pixel transistor T8 can be configured to reset the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL1.

[0074] In this example, the first node N1 is the connection point of the storage capacitor Cst, the second pixel transistor T2 and the third pixel transistor T3, the second node N2 is the connection point of the fifth pixel transistor T5, the fourth pixel transistor T4, the eighth pixel transistor T8 and the third pixel transistor T3, the third node N3 is the connection point of the first pixel transistor T1, the third pixel transistor T3, the second pixel transistor T2 and the sixth pixel transistor T6, and the fourth node N4 is the connection point of the sixth pixel transistor T6, the seventh pixel transistor T7 and the light-emitting element EL.

[0075] The operation process of the pixel circuit shown in Figure 2 is described below. In the pixel circuit, the first pixel transistor T1, the third pixel transistor T3 to the eighth pixel transistor T8 are P-type transistors, and the second pixel transistor T2 is an N-type transistor.

[0076] In some examples, during a frame display period, the operation process of the pixel circuit may include at least: a first stage, a second stage, a third stage, and a fourth stage.

[0077] The first stage is called the first reset stage. The second reset control signal RESET2 provided by the second reset control line RST2 is a low-level signal, turning on the seventh pixel transistor T7 and the eighth pixel transistor T8. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The eighth pixel transistor T8 is turned on, allowing the third initial signal provided by the third initial signal line INIT3 to be provided to the second node N2. The seventh pixel transistor T7 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be provided to the fourth node N4, initializing the fourth node N4. The first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, the first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, and the emission control signal EM provided by the emission control line EML is a high-level signal, turning off the fourth pixel transistor T4, the first pixel transistor T1, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0078] The second stage is called the second reset stage. The first reset control signal RESET1 provided by the first reset control line RST1 is a low-level signal, turning on the first pixel transistor T1; the second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, turning on the second pixel transistor T2. The first pixel transistor T1 and the second pixel transistor T2 are turned on, so that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, initializing the first node N1. The second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, the first scan signal SCAN1 provided by the first scan line GL1 is a high-level signal, and the light control signal EM provided by the light control line EML is a high-level signal, turning off the seventh pixel transistor T7, the eighth pixel transistor T8, the fourth pixel transistor T4, the fifth pixel transistor T5, and the sixth pixel transistor T6. During this stage, the light-emitting element EL does not emit light.

[0079] The third stage is called the data writing stage or the threshold compensation stage. The first scan signal SCAN1 provided by the first scan line GL1 is a low-level signal, and the fourth pixel transistor T4 is turned on. The second scan signal SCAN2 provided by the second scan line GL2 is a high-level signal, and the second pixel transistor T2 is turned on. During this stage, the first electrode of the storage capacitor Cst is at a low level, and the third pixel transistor T3 is turned on. The second pixel transistor T2, the fourth pixel transistor T4, and the third pixel transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third pixel transistor T3, the third node N3, and the turned-on second pixel transistor T2. The difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third pixel transistor T3 is charged into the storage capacitor Cst. The voltage at the first electrode of the storage capacitor Cst (i.e., the first node N1) is Vdata-|Vth|, where Vdata is the data voltage output by the data line DL and Vth is the threshold voltage of the third pixel transistor T3. The first reset control signal RESET1 provided by the first reset control line RST1 is a high-level signal, the second reset control signal RESET2 provided by the second reset control line RST2 is a high-level signal, and the light-emitting control signal EM provided by the light-emitting control line EML is a high-level signal, so that the first pixel transistor T1, the seventh pixel transistor T7, the eighth pixel transistor T8, the fifth pixel transistor T5 and the sixth pixel transistor T6 are disconnected.

[0080] In the fourth stage, the emission control signal EM provided by the emission control line EML can be switched from a high-level signal to a low-level signal, turning on the fifth pixel transistor T5 and the sixth pixel transistor T6. The second scan signal SCAN2 provided by the second scan line GL2 is a low-level signal, turning off the second pixel transistor T2. The first scan signal SCAN1 provided by the first scan line GL1, the first reset control signal RESET1 provided by the first reset control line RST1, and the second reset control signal RESET2 provided by the second reset control line RST2 are high-level signals, turning off the fourth pixel transistor T4, the first pixel transistor T1, the seventh pixel transistor T7, and the eighth pixel transistor T8. The first voltage signal VDD output by the first power line PL1 can provide a driving voltage to the anode of the light-emitting element EL through the turned-on fifth pixel transistor T5, the third pixel transistor T3, and the sixth pixel transistor T6, driving the light-emitting element EL to emit light.

[0081] During the driving process of the pixel circuit, the driving current flowing through the third pixel transistor T3 is determined by the voltage difference between its gate and the first electrode. Since the voltage of the first node N1 is Vdata-|Vth|, the driving current of the third pixel transistor T3 is: I=K×(Vgs-Vth) 2=K×[(VDD-Vdata+|Vth|)-Vth] 2 =K×[VDD-Vdata] 2 ;

[0082] Among them, I is the driving current flowing through the third pixel transistor T3, that is, the driving current driving the light-emitting element, K is a constant, Vgs is the voltage difference between the gate and the first electrode of the third pixel transistor T3, Vth is the threshold voltage of the third pixel transistor T3, Vdata is the data voltage output by the data line DL, and VDD is the first voltage signal output by the first power line PL1.

[0083] From the above equation, it can be seen that the current flowing through the light-emitting element is independent of the threshold voltage of the third pixel transistor T3. Therefore, the pixel circuit of this embodiment can effectively compensate for the threshold voltage of the third pixel transistor T3. Moreover, the pixel circuit provided by this embodiment can improve the display quality caused by low frequency and enhance the display effect of the light-emitting element.

[0084] Figure 3 is a schematic diagram of the arrangement of the gate drive circuit of at least one embodiment of the present disclosure. In some examples, as shown in Figure 3, a plurality of gate drive circuits may be provided in the second border area B2. For example, the plurality of gate drive circuits may include a first group of gate drive circuits and a second group of gate drive circuits, the first group of gate drive circuits may be located in the left border area B21 of the second border area B2, and the second group of gate drive circuits may be located in the right border area B22 of the second border area B2. The number of gate drive circuits in the first group of gate drive circuits may be the same as the number of gate drive circuits in the second group of gate drive circuits. However, this embodiment is not limited to this.

[0085] In some examples, as shown in FIG3 , the plurality of gate driving circuits may include: two first scan driving circuits 21a and 21b, two second scan driving circuits 22a and 22b, two first reset driving circuits 23a and 23b, two second reset driving circuits 24a and 24b, and two light-emitting driving circuits 25a and 25b. The first group of gate driving circuits may include: the first scan driving circuit 21a, the second scan driving circuit 22a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light-emitting driving circuit 25a; and the second group of gate driving circuits may include: the first scan driving circuit 21b, the second scan driving circuit 22b, the first reset driving circuit 23b, the second reset driving circuit 24b, and the light-emitting driving circuit 25b. For example, in the left frame area B21 of the second frame area B2, the first scanning drive circuit 21a, the second scanning drive circuit 22a, the first reset drive circuit 23a, the second reset drive circuit 24a and the light-emitting drive circuit 25a can be arranged in sequence along the direction away from the display area AA; in the right frame area B22 of the second frame area B2, the first scanning drive circuit 21b, the second scanning drive circuit 22b, the first reset drive circuit 23b, the second reset drive circuit 24b and the light-emitting drive circuit 25b can be arranged in sequence along the direction away from the display area AA.

[0086] In some examples, the multiple pixel control signals provided by the multiple gate drive circuits to the multiple sub-pixels in the display area may include: a first scan signal, a second scan signal, a first reset control signal, a second reset control signal, and a light-emitting control signal. The first scan drive circuits 21a and 21b can be configured to provide the first scan signal to the multiple pixel circuits in the display area AA. The second scan drive circuits 22a and 22b can be configured to provide the second scan signal to the multiple pixel circuits in the display area AA. The light-emitting drive circuits 25a and 25b can be configured to provide the light-emitting control signal to the multiple pixel circuits in the display area AA. The first reset drive circuits 23a and 23b can be configured to provide the first reset control signal to the multiple pixel circuits in the display area AA. The second reset drive circuits 24a and 24b can be configured to provide the second reset control signal to the multiple pixel circuits in the display area AA. In this example, the first scan signal, the second scan signal, the light-emitting control signal, the first reset control signal, and the second reset control signal can all be driven using bilateral drive. However, this embodiment is not limited to this. In some other examples, at least one of the first scan signal, the second scan signal, the light emitting control signal, the first reset control signal, and the second reset control signal may be driven by a single side.

[0087] In some examples, the display area AA includes M rows of pixel circuits, where M is a positive integer. The multiple rows of pixel circuits in the display area AA can be labeled as row 1 to row M in sequence along the direction from the upper border area B23 to the first border area B1.

[0088] In some examples, the first scan driving circuits 21a and 21b can each include a plurality of cascaded first scan driving units (e.g., including GP(1) to GP(4)). Each level of the first scan driving unit can be configured to provide a first scan signal to a row of pixel circuits in the display area AA. For example, the first level of the first scan driving unit GP(1) can be configured to provide a first scan signal to the first row of pixel circuits in the display area AA.

[0089] In some examples, the second scan driving circuits 22a and 22b may each include a plurality of cascaded second scan driving units (e.g., including GN(1) to GN(4)). Each level of the second scan driving unit may be configured to provide a second scan signal to a row of pixel circuits in the display area AA. For example, the first level of the second scan driving unit GN(1) may be configured to provide a second scan signal to the first row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the second scan driving unit may be configured to provide a second scan signal to two adjacent rows of pixel circuits in the display area.

[0090] In some examples, the light-emitting driving circuits 25a and 25b may each include a plurality of cascaded light-emitting driving units (e.g., including EM(1) to EM(4)). Each level of light-emitting driving units may be configured to provide a light-emitting control signal to a row of pixel circuits in the display area AA. For example, the first level of light-emitting driving unit EM(1) may be configured to provide a light-emitting control signal to the first row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of light-emitting driving units may be configured to provide a light-emitting control signal to two adjacent rows of pixel circuits in the display area.

[0091] In some examples, the first reset driving circuits 23a and 23b can each include a plurality of cascaded first reset driving units (e.g., including RP(1) to RP(4)). Each level of the first reset driving unit can be configured to provide a first reset control signal to a row of pixel circuits in the display area AA. For example, the first level of the first reset driving unit RP(1) can be configured to provide a first reset control signal to the first row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the first reset driving unit can be configured to provide a first reset control signal to two adjacent rows of pixel circuits in the display area.

[0092] In some examples, the second reset driving circuits 24a and 24b can each include a plurality of cascaded second reset driving units (e.g., including RH(1) to RH(4)). Each level of the second reset driving unit can be configured to provide a second reset control signal to a row of pixel circuits in the display area AA. For example, the first level of the second reset driving unit RH(1) can be configured to provide a second reset control signal to the first row of pixel circuits in the display area AA. However, this embodiment is not limited to this. In other examples, each level of the second reset driving unit can be configured to provide a second reset control signal to two adjacent rows of pixel circuits in the display area.

[0093] FIG4A is a schematic partial cross-sectional view of a display region according to at least one embodiment of the present disclosure. FIG4A illustrates the structure of a sub-pixel in the display region as an example. In this example, the pixel circuit shown in FIG2 includes a low-temperature polysilicon thin-film transistor and an oxide thin-film transistor.

[0094] In some examples, as shown in FIG4A , in a direction perpendicular to the display substrate, the display area of ​​the display substrate may include at least: a substrate 10, and a circuit structure layer 12, a light-emitting structure layer 13, and an encapsulation structure layer 14 sequentially disposed on substrate 10. Circuit structure layer 12 may include at least: pixel circuits for multiple sub-pixels, each of which may include multiple transistors and at least one capacitor. Light-emitting structure layer 13 may include at least: light-emitting elements for multiple sub-pixels. In other examples, the display substrate may further include a touch structure layer located on the side of the encapsulation structure layer away from the substrate.

[0095] In some examples, FIG4A illustrates an example of each sub-pixel including a first-type transistor 21, a second-type transistor 22, and a capacitor 23. The first-type transistor 21 may be a low-temperature polysilicon thin-film transistor, and the second-type transistor 22 may be an oxide thin-film transistor.

[0096] In some examples, the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a second semiconductor layer, a third gate metal layer, a first source / drain metal layer, and a second source / drain metal layer, disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, and a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer; a third insulating layer 103 may be disposed between the second gate metal layer and the second semiconductor layer; a fourth insulating layer 104 may be disposed between the second semiconductor layer and the third gate metal layer; a fifth insulating layer 105 may be disposed between the third gate metal layer and the first source / drain metal layer; a sixth insulating layer 106 (also referred to as a passivation layer) and a seventh insulating layer 107 (also referred to as a first planarizing layer) may be disposed between the first source / drain metal layer and the second source / drain metal layer; the seventh insulating layer 107 may be located on a side of the sixth insulating layer 106 away from the substrate 10; and an eighth insulating layer 108 (also referred to as a second planarizing layer) may be disposed on a side of the second source / drain metal layer away from the substrate 10. Among them, the first insulating layer 101, the second insulating layer 102, the third insulating layer 103, the fourth insulating layer 104, the fifth insulating layer 105 and the sixth insulating layer 106 can be inorganic insulating layers, and the seventh insulating layer 107 and the eighth insulating layer 108 can be organic insulating layers. However, this embodiment is not limited to this. In other examples, a buffer layer can be further provided on the side of the first semiconductor layer close to the substrate. The buffer layer can prevent harmful substances in the substrate from invading the interior of the display panel and can also increase the adhesion of the film layer in the display panel to the substrate. In other examples, a bottom shielding metal layer (BSM) can be further provided on the side of the buffer layer close to the substrate. The bottom shielding metal layer can be configured to at least partially cover the active layer of the transistor of the pixel circuit to prevent external light from affecting the performance of the transistor. In other examples, the sixth insulating layer can be omitted between the first source and drain metal layer and the second source and drain metal layer, and only the seventh insulating layer can be provided between the first source and drain metal layer and the second source and drain metal layer.

[0097] In some examples, as shown in FIG4A , the first semiconductor layer in the display area may include at least a first active layer 210 of the first-type transistor 21. The first active layer 210 of the first-type transistor 21 may include a first region 2101, a second region 2102, and a channel region 2100 located between the first region 2101 and the second region 2102. The first gate metal layer may include at least a first gate 213 of the first-type transistor 21 and a first plate 231 of the capacitor 23. The orthographic projection of the first gate 213 of the first-type transistor 21 on the substrate 10 may overlap the orthographic projection of the channel region 2100 of the first active layer 210 on the substrate 10. The second gate metal layer may include at least a second plate 232 of the capacitor 23 and a third gate 224 of the second-type transistor 22. The orthographic projections of the second plate 232 and the first plate 231 of the capacitor 23 on the substrate 10 may at least partially overlap, for example, they may overlap. The second semiconductor layer may include at least a second active layer 220 of the second-type transistor 22. The third gate metal layer may include at least a second gate 223 of the second-type transistor 22. The orthographic projection of the second gate 223 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The orthographic projection of the third gate 224 of the second-type transistor 22 on the substrate 10 may partially overlap with the orthographic projection of the second active layer 220 on the substrate 10. The third gate 224 may be the bottom gate of the second-type transistor 22, and the second gate 223 may be the top gate of the second-type transistor 22.

[0098] In some examples, as shown in FIG4A , the first source-drain metal layer in the display area may include at least: a first source 211 and a first drain 212 of the first-type transistor 21, and a second source 221 and a second drain 222 of the second-type transistor 22. The fifth insulating layer 105 may have a plurality of pixel vias (e.g., including a first pixel via, a second pixel via, a third pixel via, and a fourth pixel via) in the display area. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the first pixel via may be removed to expose at least a portion of the surface of the first region 2101 of the first active layer 210. The fifth insulating layer 105, the fourth insulating layer 104, the third insulating layer 103, the second insulating layer 102, and the first insulating layer 101 within the second pixel via may be removed to expose at least a portion of the surface of the second region 2102 of the first active layer 210. The fifth insulating layer 105, fourth insulating layer 104, and third insulating layer 103 within the third and fourth pixel vias can be removed, exposing at least portions of the surfaces of both ends of the second active layer 220. The first source 211 of the first-type transistor 21 can be electrically connected to the first region 2101 of the first active layer 210 through the first pixel via, and the first drain 212 can be electrically connected to the second region 2102 of the first active layer 210 through the second pixel via. The second source 221 of the second-type transistor 22 can be electrically connected to one end of the second active layer 220 through the third pixel via, and the second drain 222 of the second-type transistor 22 can be electrically connected to the other end of the second active layer 220 through the fourth pixel via. The second source-drain metal layer can include at least a first connecting electrode 241. The first connecting electrode 241 can be electrically connected to the first drain 212 of the first-type transistor 21 of the pixel circuit through a fifth pixel via defined between the sixth and seventh insulating layers 106 and 107. In this example, the first switching electrode 241 can be used to achieve electrical connection between the pixel circuit and the light-emitting element.

[0099] In some examples, the gate lines of the display area may be located in the first gate metal layer and the third gate metal layer, the data lines of the display area may be located in the second source / drain metal layer, and the first power lines of the display area may be located in the second source / drain metal layer. This embodiment is not limited to this.

[0100] In some examples, as shown in FIG4A , the light-emitting structure layer 13 may include a pixel definition layer 134 and multiple light-emitting elements. For example, each light-emitting element may include a stacked first electrode 131, an organic light-emitting layer 132, and a second electrode 133. The first electrode 131 of the light-emitting element may be an anode. The first electrode 131 may be disposed on the eighth insulating layer 108 and electrically connected to the first transfer electrode 241 through a sixth pixel via provided in the eighth insulating layer 108. The pixel definition layer 134 is disposed on the first electrode 131 and the eighth insulating layer 108. The pixel definition layer 134 may have multiple pixel openings, each of which may expose at least a portion of the surface of a corresponding first electrode 131. At least a portion of the organic light-emitting layer 132 may be disposed within a pixel opening and connected to the corresponding first electrode 131. The second electrode 133 may be disposed on and connected to the organic light-emitting layer 132. Driven by the first electrode 131 and the second electrode 133, the organic light-emitting layer 132 may emit light of a corresponding color.

[0101] In some examples, the organic light-emitting layer 132 of the light-emitting element may include an emitting layer (EML), and at least one of the following film layers: a hole injection layer (HIL), a hole transport layer (HTL), a hole blocking layer (HBL), an electron blocking layer (EBL), an electron injection layer (EIL), and an electron transport layer (ETL). Driven by the voltage of the first electrode 131 and the second electrode 133, the light-emitting properties of the organic material can be utilized to emit light according to the required grayscale.

[0102] In some examples, the light-emitting layers of light-emitting elements of different colors may be different. For example, a red light-emitting element includes a red light-emitting layer, a green light-emitting element includes a green light-emitting layer, and a blue light-emitting element includes a blue light-emitting layer. In order to reduce the difficulty of the process and improve the yield, the hole injection layer and the hole transport layer on one side of the light-emitting layer may adopt a common layer, and the electron injection layer and the electron transport layer on the other side of the light-emitting layer may adopt a common layer. In some examples, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer can be made by a one-time process (a one-time evaporation process or a one-time inkjet printing process), and isolation is achieved by means of a surface step difference of the formed film layer or by surface treatment. For example, any one or more layers of the hole injection layer, the hole transport layer, the electron injection layer and the electron transport layer corresponding to adjacent sub-pixels can be isolated. In some examples, the organic light-emitting layer can be formed by evaporation using a fine metal mask (FMM) or an open mask (Open Mask), or by inkjet technology.

[0103] In some examples, as shown in FIG4A , the encapsulation structure layer 14 may include a stacked first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143. The first encapsulation layer 141 and the third encapsulation layer 143 may be made of inorganic materials, such as silicon nitride, silicon oxide, or silicon oxynitride. Inorganic materials have high density and can prevent the intrusion of water, oxygen, and the like. The second encapsulation layer 142 may be disposed between the first and third encapsulation layers 141, 143 to prevent external moisture from entering the light-emitting element. The second encapsulation layer 142 may be made of an organic material, such as a polymer material containing a desiccant or a polymer material that can block moisture, or a polymer resin to planarize the surface of the display panel and relieve stress in the first and third encapsulation layers 141, 143. It may also include a desiccant or other absorbent material to absorb intrusive water, oxygen, and other substances. However, this embodiment is not limited to this. For example, the encapsulation structure layer may have a five-layer stacked structure: inorganic / organic / inorganic / organic / inorganic.

[0104] Figure 4B is another partial cross-sectional schematic diagram of the display region of at least one embodiment of the present disclosure. In some examples, the multiple pixel transistors in the pixel circuit can be of the same transistor type, for example, all low-temperature polysilicon thin-film transistors. Figure 4B illustrates an example of a first-type transistor 21 and a capacitor 23 included in each sub-pixel.

[0105] In some examples, as shown in FIG4B , the circuit structure layer 12 of the display area may include: a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first source-drain metal layer, and a second source-drain metal layer, disposed on the substrate 10. A first insulating layer 101 may be disposed between the first semiconductor layer and the first gate metal layer, a second insulating layer 102 may be disposed between the first gate metal layer and the second gate metal layer, a third insulating layer 103 may be disposed between the second gate metal layer and the first source-drain metal layer, a sixth insulating layer 106 and a seventh insulating layer 107 may be disposed between the first source-drain metal layer and the second source-drain metal layer, and an eighth insulating layer 108 may be disposed on the side of the second source-drain metal layer away from the substrate 10. The seventh insulating layer 107 and the eighth insulating layer 108 may be organic insulating layers, and the first insulating layer 101, the second insulating layer 102, and the third insulating layer 103 may be inorganic insulating layers. The remaining structure of the display area of ​​the display substrate of this example can be referred to the description of the embodiment shown in FIG4A , and will not be repeated here.

[0106] Figure 5 is a schematic diagram of the local routing of the first border area of ​​at least one embodiment of the present disclosure. Figure 5 is illustrated by taking the area of ​​the first border area near the boundary XL on the left side of the display substrate as an example. In some examples, as shown in Figures 1 and 5, the first border area B1 may include: a first sub-area B01, a bending area B02, and a second sub-area B03 arranged in sequence along a side away from the display area AA in the first direction D1. The first sub-area B01 can also be called a first fan-out area. The first sub-area B01 can be connected to the left border area B21 and the right border area B22 of the second border area B2, and connected to the display area AA. The bending area B02 can be connected between the first sub-area B01 and the second sub-area B03. The second sub-area B03 may include at least: a first signal access area B034 and a second signal access area B035. The first signal access area B034 can be located on the side of the second signal access area B035 away from the bending area B02.

[0107] In some examples, the bending region B02 can be configured to bend the second sub-region B03 toward the back of the display area AA. Multiple bending connection lines extending along the first direction D1 can be provided within the bending region B02 to electrically connect the traces transmitting the same signal within the first sub-region B01 and the second sub-region B03. The multiple bending connection lines within the bending region B02 can be co-layered, for example, located in the second source / drain metal layer. However, this embodiment is not limited to this. In other examples, the multiple bending connections within the bending region can be located in the first source / drain metal layer.

[0108] In some examples, the first signal access area B034 may be provided with a plurality of first contact pads, and the plurality of first contact pads may be configured to be bound and connected to an external flexible printed circuit (FPC). The second signal access area B035 may be provided with a plurality of second contact pads, and the plurality of second contact pads may be configured to connect to a driver integrated circuit (IC). At least one first contact pad within the first signal access area B034 and at least one second contact pad within the second signal access area B035 may be connected by wiring.

[0109] In some examples, as shown in FIG5 , a plurality of peripheral control lines may be provided in the first border area B1. Each peripheral control line may include: a first routing segment located in the first sub-area B01, a control bending line located in the bending area B02, and a second routing segment located in the second sub-area B03; wherein the control bending line may connect the first routing segment and the second routing segment. The first routing segment may extend at least along the first direction D1 and extend toward the second border area B2 along the edge shape of the display area AA. The control bending line and the second routing segment may extend along the first direction D1. FIG5 is illustrated by taking three peripheral control lines as an example.

[0110] In some examples, the multiple peripheral control lines of the first border area B1 may include: a first peripheral control line L1, and multiple second peripheral control lines (for example, including a first second peripheral control line L2 and a second second peripheral control line L3). The first peripheral control line L1 can be configured to transmit a constant voltage signal. The potential of the signal transmitted by the first peripheral control line L1 can be lower than the potential of the signal transmitted by each second peripheral control line. For example, the potential of the signal transmitted by the first peripheral control line L1 can be the lowest potential of the signals transmitted by the multiple peripheral control lines. For example, the potential of the signal transmitted by the first peripheral control line L1 can be less than or equal to -6V. The first second peripheral control line L2 and the second second peripheral control line L3 can be peripheral control lines adjacent to the first peripheral control line L1.

[0111] In some examples, as shown in FIG5 , the first peripheral control line L1 may include a first routing segment 41-1 located in the first sub-region B01, a control bending line 42-1 located in the bending region B02, and a second routing segment 43-1 located in the second sub-region B03. The control bending line 42-1 may connect the first routing segment 41-1 and the second routing segment 43-1. The control bending line 42-1 and the second routing segment 43-1 may extend along a first direction D1. The second routing segment 43-1 may connect to a third routing segment 44-1 that extends approximately along the second direction D2, and the third routing segment 44-1 may connect to a fourth routing segment 45-1 that extends approximately along the first direction D1. For example, the second routing segment 43-1 and the third routing segment 44-1 can be interconnected and integrally formed, for example, located in the first gate metal layer or the second gate metal layer. The fourth routing segment 45-1 and the third routing segment 44-1 can be located in different conductive layers, for example, the fourth routing segment 45-1 can be located in the first source / drain metal layer. However, this embodiment is not limited to this. For example, the second routing segment 43-1 and the third routing segment 44-1 can be located in different conductive layers.

[0112] In some examples, as shown in FIG5 , the first second peripheral control line L2 may include a first routing segment 41-2 located in the first sub-region B01, a control bending line 42-2 located in the bending region B02, and a second routing segment 43-2 located in the second sub-region B03. The control bending line 42-2 may connect the first routing segment 41-2 and the second routing segment 43-2. ​​The control bending line 42-2 and the second routing segment 43-2 may extend along the first direction D1. The second routing segment 43-2 may connect to a third routing segment 44-2 that extends approximately along the second direction D2, and the third routing segment 44-2 may connect to a fourth routing segment 45-2 that extends approximately along the first direction D1. For example, the second routing segment 43-2 and the third routing segment 44-2 can be interconnected and integrally formed, for example, located in the first gate metal layer or the second gate metal layer. The fourth routing segment 45-2 and the third routing segment 44-2 can be located in different conductive layers, for example, the fourth routing segment 45-2 can be located in the first source / drain metal layer. However, this embodiment is not limited to this. For example, the second routing segment 43-2 and the third routing segment 44-2 can be located in different conductive layers.

[0113] In some examples, as shown in FIG5 , the second peripheral control line L3 may include a first routing segment 41-3 located in the first sub-region B01, a control bending line 42-3 located in the bending region B02, and a second routing segment 43-3 located in the second sub-region B03. The control bending line 42-3 may connect the first routing segment 41-3 and the second routing segment 43-3. The control bending line 42-3 and the second routing segment 43-3 may extend along the first direction D1. The second routing segment 43-3 may connect to a third routing segment 44-3 extending generally along the second direction D2, and the third routing segment 44-3 may connect to a fourth routing segment 45-3 extending generally along the first direction D1. For example, the second routing segment 43-3 and the third routing segment 44-3 can be interconnected and integrally formed, for example, located in the first gate metal layer or the second gate metal layer. The fourth routing segment 45-3 and the third routing segment 44-3 can be located in different conductive layers, for example, the fourth routing segment 45-3 can be located in the first source / drain metal layer. However, this embodiment is not limited to this. For example, the second routing segment 43-3 and the third routing segment 44-3 can be located in different conductive layers.

[0114] In some examples, the first routing segment 41-1 of the first peripheral control line L1, the first routing segment 41-2 of the first second peripheral control line L2, and the first routing segment 41-3 of the second second peripheral control line L3 can be a same-layer structure, for example, they can all be located in the first gate metal layer, or in the second gate metal layer, or can be a double-layer routing structure located in the first gate metal layer and the second gate metal layer.

[0115] In some examples, the control bending line 42-1 of the first peripheral control line L1, the control bending line 42-2 of the first second peripheral control line L2, and the control bending line 42-3 of the second second peripheral control line L3 can be a same-layer structure, for example, they can all be located in the first source-drain metal layer or the second source-drain metal layer.

[0116] In some examples, the second routing segment 43-1 of the first peripheral control line L1, the second routing segment 43-2 of the first second peripheral control line L2, and the second routing segment 43-3 of the second second peripheral control line L3 can be a same-layer structure, for example, they can all be located in the first gate metal layer or the second gate metal layer.

[0117] In some examples, third routing segments 44-1, 44-2, and 44-3 may be co-layered, for example, located in the first gate metal layer or the second gate metal layer. Fourth routing segments 45-1, 45-2, and 45-3 may be co-layered, for example, located in the first source / drain metal layer.

[0118] In some examples, the first peripheral control line L1 may be located between the first second peripheral control line L2 and the second second peripheral control line L3, the first second peripheral control line L2 may be located on a side of the first peripheral control line L1 that is closer to the boundary XL of the display substrate, and the second second peripheral control line L3 may be located on a side of the first peripheral control line L1 that is farther from the boundary XL of the display substrate.

[0119] In some examples, the plurality of first contact pads of the first signal access area B034 may include: a plurality of control contact pads (e.g., a first control contact pad 511, a second control contact pad 512, and a second control contact pad 513) arranged along the second direction D2. The first control contact pad 511, the second control contact pad 512, and the second control contact pad 513 may be arranged sequentially along the second direction D2. The first control contact pad 511 may be located on a side of the second control contact pad 512 that is close to the boundary XL of the display substrate. For example, the first control contact pad 511 may be the contact pad closest to the boundary XL of the display substrate among the plurality of first contact pads.

[0120] In some examples, the second routing segment 43-1 of the first peripheral control line L1 can be connected to the first control contact pad 511 via the third routing segment 44-1 and the fourth routing segment 45-1. The second routing segment 43-2 of the first second peripheral control line L2 can be connected to the second control contact pad 512 via the third routing segment 44-2 and the fourth routing segment 45-2. The third routing segment 44-2 can also extend to the second signal access area B035 and connect to the second contact pad within the second signal access area B035. The second routing segment 43-3 of the second second peripheral control line L3 can be connected to the second control contact pad 513 via the third routing segment 44-3 and the fourth routing segment 45-3. The third routing segment 44-3 can also extend to the second signal access area B035 and connect to the second contact pad within the second signal access area B035. However, this embodiment is not limited to this. In other examples, the second peripheral control line adjacent to the first peripheral control line can be connected only to the first contact pad within the first signal access area.

[0121] In some examples, taking the case where the material of the plurality of peripheral control lines includes metal aluminum (Al), when the potential of the signal output by the line close to the boundary of the display substrate is low, the H in the environment + High concentration, metallic Al and H + Reacts to generate Al 3+ , Al 3+ With F - / S 2- The reaction generates compounds, which easily leads to edge wiring corrosion. For the wiring with high potential for transmitting signals, the OH in the environment - High concentration, metal Al and OH- Reacts to form AlO 2- , preventing the formation of compounds, effectively preventing trace corrosion. This example places the first peripheral control line, which has the lowest transmission potential, on a side away from the display substrate boundary of at least one second peripheral control line, which has a higher transmission potential. This increases the distance between the first peripheral control line and the display substrate boundary, thereby preventing reliability corrosion on the first peripheral control line.

[0122] Figure 6 is a partial schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. In some examples, as shown in Figure 6, the second sub-area B03 may include: a second fan-out area B031, a circuit setting area B032, a third fan-out area B033, a second signal access area B035, and a first signal access area B034 arranged in sequence along the first direction D1 away from the bending area B02. However, this embodiment is not limited to this. In other examples, the second sub-area of ​​the first border area may include: a second fan-out area, a first signal access area, and a second signal access area arranged in sequence along the side away from the bending area in the first direction.

[0123] In some examples, the circuit arrangement area B032 may be provided with at least a plurality of test circuits arranged along the second direction D2. In other examples, a plurality of anti-static circuits may be provided on a side of the plurality of test circuits close to the bending area B02, and a plurality of data selection circuits may be provided on a side of the plurality of test circuits away from the bending area B02. However, this embodiment is not limited to this.

[0124] In some examples, the multiple bending connection lines in the bending area B02 may include: multiple data bending lines (for example, including a first group of data bending lines 312a, a second group of data bending lines 312b, a third group of data bending lines 312c and a fourth group of data bending lines 312d), multiple first power bending lines (for example, including a first group of first power bending lines 321a, a second group of first power bending lines 321b, a third group of first power bending lines 321c), multiple second power bending lines (for example, including a first group of second power bending lines 331a, a second group of second power bending lines 331b, a third group of second power bending lines 331c and a fourth group of second power bending lines 331d), multiple control bending lines (for example, including a first group of control bending lines 42a and a second group of control bending lines 42b), and multiple touch bending lines (for example, including a first group of touch bending lines 341a and a second group of touch bending lines 341b). The plurality of data meandering lines can be configured to transmit data signals. The plurality of first power meandering lines can be configured to transmit a first voltage signal VDD, and the plurality of second power meandering lines can be configured to transmit a second voltage signal VSS. FIG6 illustrates an overall diagram of each group of meandering connection lines within the bend region B02.

[0125] In some examples, the first group of control bending lines 42a, the first group of second power bending lines 331a, the first group of touch bending lines 341a, the second group of second power bending lines 331b, the first group of data bending lines 312a, the first group of first power bending lines 321a, the second group of data bending lines 312b, the second group of first power bending lines 321b, the third group of data bending lines 312c, the third group of first power bending lines 321c, the fourth group of data bending lines 312d, the third group of second power bending lines 331c, the second group of touch bending lines 341b, the fourth group of second power bending lines 331d, and the second group of control bending lines 42b can be arranged sequentially along the second direction D2. However, this embodiment is not limited to this. In other examples, the multiple touch bending lines can be omitted from the bending region; alternatively, the bending region can be provided with one or five groups of first power bending lines.

[0126] In some examples, the first border area B1 may be provided with a plurality of peripheral data lines. The plurality of peripheral data lines may include: a plurality of first data fan-out lines located in the first sub-area B01 (for example, including a first group of first data fan-out lines 311a and a second group of first data fan-out lines 311b), a plurality of second data fan-out lines located in the second fan-out area B031 (for example, including a first group of second data fan-out lines 313a and a second group of second data fan-out lines 313b), a plurality of data bending lines located in the bending area B02 (for example, including a first group of data bending lines 312a, a second group of data bending lines 312b, a third group of data bending lines 312c, and a fourth group of data bending lines 312d), and a plurality of third data fan-out lines located in the third fan-out area B03 (for example, including a first group of third data fan-out lines 314a and a second group of third data fan-out lines 314b). FIG6 shows an overall diagram of multiple data bending lines, multiple first data fan-out lines, multiple second data fan-out lines, and multiple third data fan-out lines. This example does not limit the number of data bending lines, first data fan-out lines, second data fan-out lines, and third data fan-out lines.

[0127] In some examples, multiple first data fan-out lines can be connected to multiple data lines in display area AA, for example, in a one-to-one correspondence. A first group of first data fan-out lines 311a can be connected to a first group of second data fan-out lines 313a via a first group of data bending lines 312a and a second group of data bending lines 312b, and a second group of first data fan-out lines 311b can be connected to a second group of second data fan-out lines 313b via a third group of data bending lines 312c and a fourth group of data bending lines 312d. For example, multiple first data fan-out lines can be connected to multiple data bending lines in a one-to-one correspondence, and multiple data bending lines can be connected to multiple second data fan-out lines in a one-to-one correspondence. A first group of second data fan-out lines 313a can be connected to a first group of third data fan-out lines 314a, and a second group of second data fan-out lines 313b can be connected to a second group of third data fan-out lines 314b. For example, a single third data fan-out line can be connected to multiple second data fan-out lines. This embodiment is not limited to this.

[0128] In some examples, the plurality of second contact pads of the second signal access region B035 may include a plurality of data contact pads 315. The plurality of third data fan-out lines may be electrically connected to the plurality of data contact pads 315 in the second signal access region B035.

[0129] In some examples, the first border area B1 may be provided with a plurality of peripheral control lines extending at least along the first direction D1. The plurality of peripheral control lines may include a first group of peripheral control lines and a second group of peripheral control lines, and the first group of peripheral control lines and the second group of peripheral control lines may be located on both sides of the plurality of peripheral data lines along the second direction D2. In other words, the plurality of peripheral data lines may be located in the middle of the plurality of peripheral control lines in the second direction D2. Each peripheral control line may include: a first routing segment located in the first sub-area B01, a control bending line located in the bending area B02, and a second routing segment located in the second sub-area B03.

[0130] In some examples, the multiple first routing segments of the first sub-area B01 may include: a first group of first routing segments 41a and a second group of first routing segments 41b. Figure 6 is illustrated by taking the multiple first routing segments of the first sub-area B01 as an example. This embodiment does not limit the number of first routing segments. The first group of first routing segments 41a and the second group of first routing segments 41b can be located on both sides of the multiple first data fan-out lines in the second direction D2. Among them, the first group of first routing segments 41a can be located on the side of the first group of first data fan-out lines 311a close to the boundary of the display substrate in the second direction D2, and the second group of first routing segments 41b can be located on the side of the second group of first data fan-out lines 311b close to the boundary of the display substrate in the second direction D2.

[0131] In some examples, the plurality of second routing segments of the second sub-area B03 may include: a first group of second routing segments 43a and a second group of second routing segments 43b. FIG6 is illustrated by taking the plurality of second routing segments of the second sub-area B03 as an example. This embodiment does not limit the number of second routing segments. The first group of second routing segments 43a and the second group of second routing segments 43b may be located on both sides of the plurality of second data fan-out lines and the plurality of third data fan-out lines in the second direction D2. The first group of second routing segments 43a may be located on a side of the first group of second data fan-out lines 313a and the first group of third data fan-out lines 314a close to the boundary of the display substrate in the second direction D2, and the second group of second routing segments 43b may be located on a side of the second group of second data fan-out lines 313b and the second group of third data fan-out lines 314b close to the boundary of the display substrate in the second direction D2.

[0132] In some examples, the first group of first routing segments 41a in the first sub-area B01 can be connected to the first group of second routing segments 43a in the second sub-area B03 through the first group of control bending lines 42a in the bending area B02; the second group of first routing segments 41b in the first sub-area B01 can be connected to the second group of second routing segments 43b in the second sub-area B03 through the second group of control bending lines 42b in the bending area B02.

[0133] In some examples, the second sub-area B03 may further be provided with a plurality of third routing segments (e.g., including a first group of third routing segments 44a and a second group of third routing segments 44b) and a plurality of fourth routing segments (e.g., including a first group of fourth routing segments 45a and a second group of fourth routing segments 45b). The second routing segments of a portion of the plurality of peripheral control lines may be connected to the first contact pad in the second signal access area B035 via the third routing segments extending along the second direction D2, and may also be connected to the first contact pad in the first signal access area B034 via the third routing segments extending along the second direction D2 and the fourth routing segments extending along the first direction D1. The second routing segments of another portion of the plurality of peripheral control lines may not be connected to the second contact pad in the second signal access area B035, but may be connected to the first contact pad in the first signal access area B034 via the third routing segments extending along the second direction D2 and the fourth routing segments extending along the first direction D1. For example, at least one peripheral control line in the other part of the peripheral control lines may also be connected to the test circuit located in the circuit arrangement area through a third routing segment extending along the second direction D2.

[0134] In some examples, the arrangement of the plurality of gate drive circuits located in the second border area B2 can be as shown in Figure 3, and the number and arrangement of the first group of gate drive circuits in the left border area B21 and the second group of gate drive circuits in the right border area B22 are the same. A portion of the peripheral control lines in the first group of peripheral control lines can be connected to the first group of gate drive circuits, and a portion of the peripheral control lines in the second group of peripheral control lines can be connected to the second group of gate drive circuits. The number and type of the first group of peripheral control lines and the second group of peripheral control lines located on both sides of the plurality of peripheral data lines can be the same. For example, the first group of peripheral control lines and the second group of peripheral control lines can be arranged roughly symmetrically about the center line of the first border area B1 parallel to the first direction D1. However, this embodiment is not limited to this. In other examples, when the number or type of gate drive circuits in the first group of gate drive circuits and the second group of gate drive circuits are different, the number or type of routing of the first group of peripheral control lines and the second group of peripheral control lines can be different.

[0135] Figure 7 is a partially enlarged schematic diagram of area S1 in Figure 6. Figure 7 uses the first set of peripheral control lines as an example for explanation. The description of the second set of peripheral control lines can refer to the description of the first set of peripheral control lines, so it is not repeated here.

[0136] In some examples, as shown in FIG7 , the first group of peripheral control lines may include: a first initial control line VI1, a second initial control line VI2, a third initial control line VI3, a fifth voltage control line VGH-N, a fourth voltage control line VGH, a light-emitting drive output line Eout, a fifth start signal line ESTV, a thirteenth clock signal line ECB, a twelfth clock signal line ECK, a fourteenth clock signal line ECX, a tenth clock signal line HCB, a ninth clock signal line HCK, a fourth start signal line HSTV, a second reset drive output line Hout, a first reset drive output line Pout, and a third start signal line PS TV, seventh clock signal line PCB, sixth clock signal line PCK, eighth clock signal line PCX, fourth clock signal line NCB, third clock signal line NCK, second start signal line NSTV, first voltage control line VGL1, second voltage control line VGL2, third voltage control line VGL3, second scan drive output line Nout, second clock signal line GCB, first clock signal line GCK, first start signal line GSTV, eleventh clock signal line HCX, fifth clock signal line NCX, first scan drive output line Gout, first panel detection line PCD1, and second panel detection line PCD2.

[0137] In some examples, in the first sub-area, the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the fifth voltage control line VGH-N, the fourth voltage control line VGH, the fifth start signal line ESTV, the thirteenth clock signal line ECB, the twelfth clock signal line ECK, the fourteenth clock signal line ECX, the tenth clock signal line HCB, the ninth clock signal line HCK, the fourth start signal line HSTV, the third start signal line PSTV, the seventh clock signal line PCB, the sixth clock signal line PCK, the eighth clock signal line PCX, the fourth clock signal line NCB, the third clock signal line NCK, the second start signal line NSTV, the first voltage control line VGL1, the second voltage control line VGL2, the third voltage control line VGL3, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV, the eleventh clock signal line HCX, and the fifth clock signal line NCX can all adopt a double-layer routing design located in the first gate metal layer and the second gate metal layer. The light-emitting drive output line Eout, the second reset drive output line Hout, the first reset drive output line Pout, the second scan drive output line Nout, the first scan drive output line Gout, the first panel detection line PCD1, and the second panel detection line PCD2 can be single-layer routing located in the first gate metal layer.

[0138] In some examples, the first start signal line GSTV, the first clock signal line GCK, the second clock signal line GCB, and the first scan driver output line Gout can be electrically connected to the first scan driver circuit 21a located in the left border area B21. The first start signal line GSTV can be configured to provide a start signal to the first scan driver circuit 21a, the first clock signal line GCK and the second clock signal line GCB can be configured to provide a clock signal to the first scan driver circuit 21a, and the first scan driver output line Gout can be configured to be connected to the output end of the last stage first scan driver unit of the first scan driver circuit 21a.

[0139] In some examples, the second start signal line NSTV, the third clock signal line NCK, the fourth clock signal line NCB, the fifth clock signal line NCX, and the second scan drive output line Nout can be electrically connected to the second scan drive circuit 22a in the left border area B21. The second start signal line NSTV can be configured to provide a start signal to the second scan drive circuit 22a, the third clock signal line NCK, the fourth clock signal line NCB, and the fifth clock signal line NCK can be configured to provide a clock signal to the second scan drive circuit 22a, and the second scan drive output line Nout can be configured to be connected to the output end of the second scan drive unit of the last stage of the second scan drive circuit 22a.

[0140] In some examples, the third start signal line PSTV, the sixth clock signal line PCK, the seventh clock signal line PCB, the eighth clock signal line PCX, and the first reset driver output line Pout can be electrically connected to the first reset driver circuit 23a within the left border area B21. The third start signal line PSTV can be configured to provide a start signal to the first reset driver circuit 23a, the sixth clock signal line PCK, the seventh clock signal line PCB, and the eighth clock signal line PCX can be configured to provide a clock signal to the first reset driver circuit 23a, and the first reset driver output line Pout can be configured to be connected to the output end of the last-stage first reset driver unit of the first reset driver circuit 23a.

[0141] In some examples, the fourth start signal line HSTV, the ninth clock signal HCK, the tenth clock signal HCB, the eleventh clock signal HCX, and the second reset driver output line Hout can be electrically connected to the second reset driver circuit 24a in the left border area B21. The fourth start signal line HSTV can be configured to provide a start signal to the second reset driver circuit 24a, the ninth clock signal HCK, the tenth clock signal HCB, and the eleventh clock signal HCX can be configured to provide a clock signal to the second reset driver circuit 24a, and the second reset driver output line Hout can be configured to be connected to the output end of the last-stage second reset driver unit of the second reset driver circuit 24a.

[0142] In some examples, the fifth start signal line ESTV, the twelfth clock signal ECK, the thirteenth clock signal ECB, the fourteenth clock signal ECX, and the light-emitting drive output line Eout can be electrically connected to the light-emitting drive circuit 25a in the left border area B21. The fifth start signal line ESTV can be configured to provide a start signal to the light-emitting drive circuit 25a, the twelfth clock signal ECK, the thirteenth clock signal ECB, and the fourteenth clock signal ECX can be configured to provide a clock signal to the light-emitting drive circuit 25a, and the light-emitting drive output line Eout can be configured to be connected to the output end of the last stage light-emitting drive unit of the light-emitting drive circuit 25a.

[0143] In some examples, the fifth voltage control line VGH-N can be electrically connected to the second scan driver circuit 22a in the left frame area B21 and configured to provide a seventh voltage signal to the second scan driver circuit 22a. The fourth voltage control line VGH can be electrically connected to the first scan driver circuit 21a, the first reset driver circuit 23a, the second reset driver circuit 24a, and the light-emitting driver circuit 25a in the left frame area B21 and configured to provide a sixth voltage signal. The fifth and sixth voltage signals can be constant voltage signals, and the sixth voltage signal can be different from the fifth voltage signal.

[0144] In some examples, the first voltage control line VGL1 can be electrically connected to the first scan driving circuit 21a, the first reset driving circuit 23a, the second reset driving circuit 24a, and the light-emitting driving circuit 25a in the left frame area B21, and configured to provide a third voltage signal. The second voltage control line VGL2 can be electrically connected to the second scan driving circuit 22a in the left frame area B21, and configured to provide a fourth voltage signal. The third voltage control line VGL3 can be electrically connected to the second scan driving circuit 22a in the left frame area B21, and configured to provide a fifth voltage signal.

[0145] In some examples, the third voltage signal, the fourth voltage signal, and the fifth voltage signal can be constant voltage signals, and the potentials of the third voltage signal, the fourth voltage signal, and the fifth voltage signal can all be less than or equal to -6V. The third voltage signal provided by the first voltage control line VGL1 and the fifth voltage signal provided by the third voltage control line VGL3 can be substantially the same, and the fourth voltage signal provided by the second voltage control line VGL2 can be different from the fifth voltage signal provided by the third voltage control line VGL3. For example, the potential of the fourth voltage signal can be less than or equal to the potential of the fifth voltage signal. In some examples, the potential range of the third voltage signal and the fifth voltage signal can both be -6V to -10V, and the potential range of the fourth voltage signal can be -6V to -12V. This example can help ensure the performance of the second scan drive circuit by providing two low-potential constant voltage signals to the second scan drive circuit.

[0146] In some examples, the first initial control line VI1 can be configured to provide a first initial signal, the second initial control line VI2 can be configured to provide a second initial signal, and the third initial control line VI3 can be configured to provide a third initial signal. The first initial control line VI1 can be connected to the first initial signal line of the display area and configured to provide the first initial signal to the first reset transistor of the pixel circuit. The second initial control line VI2 can be connected to the second initial signal line of the display area and configured to provide the second initial signal to the second reset transistor of the pixel circuit. The third initial control line VI3 can be connected to the third initial signal line of the display area and configured to provide the third initial signal to the third reset transistor of the pixel circuit.

[0147] In some examples, the first panel inspection line PCD1 and the second panel inspection line PCD2 may be configured to transmit a signal for detecting whether a crack exists on a periphery of the display substrate.

[0148] In some examples, the first initial control line VI1, the second initial control line VI2, the third initial control line VI3, the first panel detection line PCD1, and the second panel detection line PCD2 in the first group of peripheral control lines are not directly electrically connected to the multiple gate drive circuits, and the remaining lines are electrically connected to the multiple gate drive circuits.

[0149] In some examples, as shown in FIG7 , a first initial control line VI1, a second initial control line VI2, a third initial control line VI3, a fifth voltage control line VGH-N, a fourth voltage control line VGH, a light emitting driver output line Eout, a fifth start signal line ESTV, a thirteenth clock signal line ECB, a twelfth clock signal line ECK, a fourteenth clock signal line ECX, a tenth clock signal line HCB, a ninth clock signal line HCK, a fourth start signal line HSTV, a second reset driver output line Hout, a first reset driver output line Pout, a third start signal line PSTV, a seventh clock signal line PCB, a sixth clock signal line The clock signal line PCK, the eighth clock signal line PCX, the fourth clock signal line NCB, the third clock signal line NCK, the second start signal line NSTV, the first voltage control line VGL1, the second voltage control line VGL2, the third voltage control line VGL3, the second scan drive output line Nout, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV, the eleventh clock signal line HCK, the fifth clock signal line NCK, the first scan drive output line Gout, the first panel detection line PCD1, and the second panel detection line PCD2 can be arranged in sequence along the direction away from the boundary of the display substrate.

[0150] In this example, the plurality of first peripheral control lines may include a first voltage control line VGL1, a second voltage control line VGL2, and a third voltage control line VGL3. The remaining peripheral control lines are the second peripheral control lines described in the aforementioned embodiments. In this example, the first second peripheral control line may be the second start signal line NSTV, the second second peripheral control line may be the second scan drive output line Nout, and the three first peripheral control lines may be located between the second start signal line NSTV and the second scan drive output line Nout. The signals transmitted by the second start signal line NSTV and the second scan drive output line Nout are relatively stable and have little impact on the signals transmitted by the three first peripheral control lines. However, this embodiment is not limited to this. In other examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 may be located between the remaining second peripheral control lines, for example, between the first scan drive output line Gout and the first panel detection line PCD1, or between the first reset drive output line Pout and the second reset drive output line Hout. In other examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 may be located on a side of the plurality of second peripheral control lines close to the peripheral data lines, for example, on a side of the second panel detection line PCD2 away from the first panel detection line PCD1.

[0151] In some examples, the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 are arranged sequentially in a direction away from the boundary of the display substrate. In this example, the minimum distance between the plurality of first peripheral control lines and the boundary of the display substrate may be the minimum distance between the first voltage control line VGL1 and the boundary of the display substrate. The minimum distance W2 between the first voltage control line VGL1 and the boundary of the display substrate may be the distance between the edge of the first voltage control line VGL1 closest to the boundary of the display substrate and the boundary of the display substrate. W2 may be greater than or equal to 1250 microns, for example, approximately 2067 microns.

[0152] In some examples, the line closest to the boundary of the display substrate in the first group of peripheral control lines is the first initial control line VI1. The minimum distance W1 between the first initial control line VI1 and the boundary of the display substrate may be the distance between an edge of the first initial control line VI1 close to the boundary of the display substrate and the boundary of the display substrate. W1 may be greater than or equal to 400 microns, for example, approximately 535 microns.

[0153] In some examples, the potential of the signal transmitted by the first initial control line VI1 is higher than the potential of the signals transmitted by the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3. For example, the potential range of the signal transmitted by the first initial control line VI1 can be -3V to -4V.

[0154] In this example, by setting multiple first peripheral control lines (including the first voltage control line VGL1, the second voltage control line VGL2 and the third voltage control line VGL3) away from the boundary of the display substrate, the first peripheral control lines can be prevented from undergoing reliability corrosion, which is beneficial to avoiding display problems such as black screen and yellow screen on the display substrate.

[0155] In other examples, at least two of the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 can be interposed between different second peripheral traces. For example, the second voltage control line VGL2 and the third voltage control line VGL3 can be located between the second start signal line NSTV and the second scan drive output line Nout, and the first voltage control line VGL1 can be located between the first reset drive output line Pout and the second reset drive output line Hout. This embodiment is not limited to this. It is sufficient to ensure that the first voltage control line VGL1, the second voltage control line VGL2, and the third voltage control line VGL3 are not located closest to the edge of the display substrate.

[0156] FIG8 is another partial routing diagram of the first border region of at least one embodiment of the present disclosure. FIG8 is illustrated using the region of the first border region near the boundary XL on the left side of the display substrate as an example. In some examples, as shown in FIG8 , the first peripheral control line L1 is connected to the first control contact pad 511, the first second peripheral control line L2 is connected to the second control contact pad 512, and the second second peripheral control line L3 is connected to the second control contact pad 513. Within the first signal access area B034, the first control contact pad 511 can be located between the second control contact pads 512 and 513.

[0157] This example facilitates the arrangement of the first and second peripheral control lines by placing the first control contact pads connected to the first peripheral control lines between the second control contact pads connected to the adjacent second peripheral control lines. The remaining description of this example can be found in the description of the embodiment shown in FIG5 , and will not be repeated here.

[0158] FIG9 is another partial routing diagram of the first border region of at least one embodiment of the present disclosure. FIG9 is illustrated using the region of the first border region near the boundary XL on the left side of the display substrate as an example. In some examples, as shown in FIG9 , the first peripheral control line L1 is connected to the first control contact pad 511, the first second peripheral control line L2 is connected to the second control contact pad 512, and the second second peripheral control line L3 is connected to the second control contact pad 513. Within the first signal access area B034, the first control contact pad 511 can be located on the side of the second control contact pad 513 away from the boundary of the display substrate.

[0159] In this example, by disposing the first control contact pad connected to the first peripheral control line on a side away from the boundary of the display substrate where the second control contact pad connected to the adjacent second peripheral control line is located, this helps ensure signal transmission of the first peripheral control line and prevents interference between the signal transmitted by the adjacent second peripheral control line and the signal transmitted by the first peripheral control line. The remaining description of this example can be found in the description of the embodiment shown in FIG5 , and will not be repeated here.

[0160] In other examples, the first control contact pad connected to a first peripheral control line in the first group of peripheral control lines may be located on a side of the second control contact pads connected to all other second peripheral control lines that is away from the boundary of the display substrate. In other words, the first control contact pad may not be inserted within the plurality of second control contact pads, but may be located on a side of the plurality of second control contact pads connected to the first group of peripheral control lines that is away from the boundary of the display substrate.

[0161] Figure 10 is another partial routing diagram of the first border area of ​​at least one embodiment of the present disclosure. Figure 10 is illustrated by taking the area of ​​the first border area close to the boundary XL on the left side of the display substrate as an example. In some examples, as shown in Figure 10, the third routing segment 44-3 connected to the first peripheral control line L1 can be located on the side of the third routing segment 44-3 connected to the second second peripheral control line L3 close to the bending area B02. The third routing segments 44-1, 44-3, and 44-2 can be arranged in a direction away from the bending area B02. This example facilitates the connection between the first peripheral control line and the first control contact pad by adjusting the routing arrangement within the second sub-area, thereby avoiding interference between the signal transmitted by the second peripheral control line and the signal transmitted by the first peripheral control line. The rest of the description of this example can refer to the description of the embodiment shown in Figure 9, so it will not be repeated here.

[0162] Figure 11 is another partial schematic diagram of the first border area of ​​at least one embodiment of the present disclosure. In some examples, the first sub-area B01 may be provided with multiple electrostatic discharge circuits. Multiple electrostatic discharge circuits may be adjacent to multiple gate drive circuits in the second border area B2. For example, the first sub-area B01 may include a first corner area connected to the left border area B21, and a second corner area connected to the right border area B22. Multiple electrostatic discharge circuits may be located in the first corner area and the second corner area. Figure 11 is illustrated by taking the arrangement of multiple electrostatic discharge circuits in the first corner area as an example.

[0163] In some examples, as shown in FIG11 , the multiple electrostatic discharge circuits within the first sub-area B01 can be arranged in multiple rows along the first direction D1, and each row of electrostatic discharge circuits can include multiple electrostatic discharge circuits arranged along the second direction D2. For example, the multiple electrostatic discharge circuits can be arranged as a first row of electrostatic discharge circuits 61a, a second row of electrostatic discharge circuits 61b, and a third row of electrostatic discharge circuits 61c. The first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be arranged sequentially in a direction away from the display area.

[0164] In some examples, the first routing segment 41-1 of the first peripheral control line L1 located within the first sub-region B01 can be connected to multiple electrostatic discharge circuits. The first routing segment 41-1 of the first peripheral control line L1 can extend approximately along the curved edge of the display area toward the left border region B21 of the second border region. The first routing segment 41-1 of the first peripheral control line L1 can be located between the first row of electrostatic discharge circuits 61a and the second row of electrostatic discharge circuits 61b. Compared to the first peripheral control line bypassing the same side of multiple rows of electrostatic discharge circuits, the routing method of the first peripheral control line in this example can adapt to the position of the first peripheral control line away from the boundary of the display substrate, which can reduce the length of the first peripheral control line, thereby facilitating load reduction.

[0165] FIG12 is an equivalent circuit diagram of an electrostatic discharge circuit according to at least one embodiment of the present disclosure. In some examples, as shown in FIG12 , the electrostatic discharge circuit can be connected to a peripheral control line CL and configured to discharge static electricity from the peripheral control line CL to which it is connected. The electrostatic discharge circuit can include: first to fourth release transistors ST1 to ST4. The first electrode of the first release transistor ST1 can be electrically connected to the third voltage control line VGL1, the gate and second electrode of the first release transistor ST1 are electrically connected to the first electrode of the second release transistor ST2, the gate and second electrode of the second release transistor ST2 are electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the first electrode of the third release transistor ST3 is electrically connected to the peripheral control line CL corresponding to the first electrostatic discharge circuit, the gate and second electrode of the third release transistor ST3 are electrically connected to the first electrode of the fourth release transistor ST4, and the gate and second electrode of the fourth release transistor ST4 are electrically connected to the fourth voltage line VGH.

[0166] In one example, providing an electrostatic discharge circuit can prevent static electricity accumulation in the peripheral control lines from causing discharge breakdown and resulting in damage, thereby releasing the static electricity accumulated in the peripheral control lines and protecting the peripheral control lines.

[0167] In another example, the electrostatic discharge circuit may include two discharge transistors, each with one electrode connected to its own gate, thereby forming an equivalent diode connection. The signal line to be protected is connected between the two "diodes," and the other two ends of the two "diodes" are connected to the fourth voltage control line VGH and the first voltage control line VGL1, respectively. Thus, when a transient high voltage (e.g., 100V) appears in the signal line due to accumulated positive charge, one of the "diodes" conducts, releasing the positive charge in the signal line. When a transient low voltage (e.g., -100V) appears in the signal line due to accumulated negative charge, the other "diode" conducts, releasing the negative charge in the signal line.

[0168] Figure 13 is a partially enlarged schematic diagram of region S2 in Figure 6. Figure 14 is a schematic diagram of the first semiconductor layer, the first gate metal layer, and the second gate metal layer in Figure 13. Figures 13 and 14 illustrate the arrangement of multiple electrostatic discharge circuits in the first corner region of the first subregion as an example.

[0169] In some examples, as shown in Figures 13 and 14, the multiple electrostatic release circuits in the first sub-area include: a first row of electrostatic release circuits 61a, a second row of electrostatic release circuits 61b, and a third row of electrostatic release circuits 61c. The active layers of the release transistors of the multiple electrostatic release circuits located in the same row can be an integrated structure connected to each other. For example, the integrated structure can be a strip structure extending along the second direction D2. The active layers of the multiple release transistors can be located in the first semiconductor layer. The arrangement order of the four release transistors of adjacent electrostatic release circuits located in the same row can be opposite. For example, the first release transistor to the fourth release transistor of the first electrostatic release circuit in the first row of electrostatic release circuits in the second direction D2 are arranged along the second direction D2, and the fourth release transistor to the first release transistor of the second electrostatic release circuit can be arranged along the second direction D2.

[0170] In some examples, as shown in Figures 13 and 14, the third voltage control line VGL3, the second voltage control line VGL2, and the first voltage control line VGL1 can be located between the first row of electrostatic release circuits 61a and the second row of electrostatic release circuits 61b, and can be arranged in sequence in the first direction D1 along a direction away from the first row of electrostatic release circuits 61a.

[0171] In some examples, the first row of electrostatic discharge circuits 61a, the second row of electrostatic discharge circuits 61b, and the third row of electrostatic discharge circuits 61c can be connected to the first voltage control line VGL1 via a first connection line 621, a second connection line 622, a third connection line 623, and a fourth connection line 624. The first connection line 621, the second connection line 622, the third connection line 623, and the fourth connection line 624 can extend along the first direction D1 and be arranged along the second direction D2. The fourth voltage control line VGH can be located on a side of the third row of electrostatic discharge circuits 61c away from the second row of electrostatic discharge circuits 61b and can be electrically connected to the three rows of electrostatic discharge circuits via four connection lines extending along the first direction D1.

[0172] In some examples, the first row of electrostatic release circuits 61a can include six electrostatic release circuits. The six electrostatic release circuits arranged along the second direction D2 can be connected to the second start signal line NSTV, the third clock signal line NCK, the second clock signal line GCB, the first clock signal line GCK, the first start signal line GSTV and the eleventh clock signal line HCX in sequence to play an electrostatic protection role.

[0173] In some examples, the second row of electrostatic discharge circuits 61b may include six electrostatic discharge circuits. The six electrostatic discharge circuits in the second row of electrostatic discharge circuits 61b may be aligned with the six electrostatic discharge circuits in the first row of electrostatic discharge circuits 61a in the first direction D1. The six electrostatic discharge circuits in the second row of electrostatic discharge circuits 61b, arranged along the second direction D2, may be sequentially connected to the seventh clock signal line PCB, the sixth clock signal line PCK, the fourth clock signal line NCB, the eighth clock signal line PCX, the seventh clock signal line PCB, and the fourth start signal line HSTV to provide electrostatic protection.

[0174] In some examples, the third row of electrostatic discharge circuits 61c may include seven electrostatic discharge circuits, six of which may be aligned with the six electrostatic discharge circuits of the first row of electrostatic discharge circuits 61a in the first direction D1. The seven electrostatic discharge circuits of the third row of electrostatic discharge circuits 61c arranged along the second direction D2 may be sequentially connected to the ninth clock signal line HCK, the twelfth clock signal line ECK, the tenth clock signal line HCB, the fourteenth clock signal line ECX, the thirteenth clock signal line ECB, the fifth start signal line ESTV, and the fifth clock signal line NCX, thereby providing electrostatic protection.

[0175] In some examples, the first panel detection line PCD1 can be connected to the second detection connection line 631 located on the first gate metal layer via a first detection connection line 633 located on the first source / drain metal layer. The second panel detection line PCD2 can be connected to the fourth detection connection line 632 located on the first gate metal layer via a third detection connection line 634 located on the first source / drain metal layer.

[0176] In some examples, the first sub-region can also be provided with a second power border line 342 located in the first source-drain metal layer, and the second power border line 342 can be connected to the first group of second power bending lines 331a and the second group of second power bending lines 331b in the bending region to be configured to transmit a second voltage signal VSS.

[0177] The structure of the second corner region of the first sub-region is similar to that of the first corner region, and therefore will not be described in detail here.

[0178] Figure 15 is a schematic diagram of a display device according to at least one embodiment of the present disclosure. In some examples, as shown in Figure 15 , display substrate 910 may be an OLED display substrate. Display device 91 may be any product or component with a display function, such as an OLED display device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system. However, this embodiment is not limited to this.

[0179] In the description of this specification, the reference terms "one embodiment", "some embodiments", "example" or "some examples" and the like mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, unless they are mutually inconsistent.

[0180] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application.

Claims

1. A display substrate comprising a display area and a frame area surrounding the display area, wherein the frame area comprises: A first frame area and a second frame area are connected to each other, wherein the first frame area at least includes: a bending area located on one side of the display area along a first direction; The display substrate comprises: substrate; A plurality of sub-pixels are arranged on one side of the substrate and located in the display area; a plurality of gate driving circuits, located in the second frame area and electrically connected to the plurality of sub-pixels, and configured to provide a plurality of pixel control signals to the plurality of sub-pixels; at least one first peripheral control line, located in the first border region and connected to the plurality of gate drive circuits; a plurality of second peripheral control lines located in the first border region, a portion of the plurality of second peripheral control lines being connected to the plurality of gate drive circuits; a potential of a signal transmitted by each first peripheral control line being lower than a potential of a signal transmitted by each second peripheral control line; In the bending region, at least one second peripheral control line among the plurality of second peripheral control lines is located between the at least one first peripheral control line and a boundary of the display substrate.

2. The display substrate according to claim 1, further comprising: a plurality of peripheral data lines located in the first frame area, the plurality of peripheral data lines being electrically connected to the plurality of sub-pixels and configured to provide data signals to the plurality of sub-pixels; In a second direction, the plurality of second peripheral control lines and the at least one first peripheral control line are located between the plurality of peripheral data lines and a boundary of the display substrate; the second direction intersects the first direction.

3. The display substrate according to claim 1, wherein In the bending region, a minimum distance between the at least one first peripheral control line and a boundary of the display substrate is greater than or equal to 1250 micrometers.

4. The display substrate according to claim 1, wherein: The at least one first peripheral control line is configured to transmit a constant voltage signal, and a potential of the constant voltage signal is less than or equal to -6V.

5. The display substrate according to claim 1, wherein At least one sub-pixel among the plurality of sub-pixels comprises: a pixel circuit and a light-emitting element connected to the pixel circuit; The pixel circuit at least includes: a driving transistor, a data writing transistor and a compensation transistor; The gate of the data writing transistor is connected to the first scan line, the first electrode of the data writing transistor is connected to the data line, and the second electrode of the data writing transistor is connected to the first electrode of the driving transistor; The gate of the driving transistor is connected to the second electrode of the compensation transistor, the second electrode of the driving transistor is connected to the first electrode of the compensation transistor, and the gate of the compensation transistor is connected to the second scan line; The plurality of gate driving circuits include: at least one first scan driving circuit and at least one second scan driving circuit, wherein the at least one first scan driving circuit is configured to provide a first scan signal to the first scan line, and the at least one second scan driving circuit is configured to provide a second scan signal to the second scan line; The plurality of second peripheral control lines at least include: a second start signal line and a second scan drive output line connected to the at least one second scan drive circuit; The at least one first peripheral control line is located between the second start signal line and the second scan drive output line. The display substrate according to claim 5 , wherein: The pixel circuit further includes: a first reset transistor, a gate of the first reset transistor connected to a first reset control line, a first electrode of the first reset transistor configured to receive a first initial signal, and a second electrode of the first reset transistor connected to a second electrode of the driving transistor; In the bending region, a second peripheral control line closest to the boundary of the display substrate among the plurality of second peripheral control lines is configured to transmit the first initial signal.

7. The display substrate according to claim 1 or 6, wherein: In the bending region, a minimum distance between a second peripheral signal line closest to the boundary of the display substrate among the plurality of second peripheral control lines and the boundary of the display substrate is greater than or equal to 400 micrometers.

8. The display substrate according to claim 1, wherein: The first frame area further includes: a first signal access area located on a side of the bending area away from the display area; The display substrate further includes: a plurality of first contact pads located in the first signal access area and arranged along a second direction; the second direction intersects the first direction; The plurality of first contact pads include: at least one first control contact pad connected to the at least one first peripheral control line, and a plurality of second control contact pads connected to the plurality of second peripheral control lines; In the second direction, at least one second control contact pad among the plurality of second control contact pads is located between the at least one first control contact pad and a boundary of the display substrate.

9. The display substrate according to claim 8, wherein: The at least one first peripheral control line is located between the first second peripheral control line and the second second peripheral control line; In the second direction, the at least one first control contact pad is located between the second control contact pad connected to the first second peripheral control line and the second control contact pad connected to the second second peripheral control line.

10. The display substrate according to claim 8, wherein The at least one first peripheral control line is located between the first second peripheral control line and the second second peripheral control line; the first second peripheral control line is located on a side of the at least one first peripheral control line close to a boundary of the display substrate; In the second direction, the at least one first control contact pad is located on a side of the second control contact pad connected to the second second peripheral control line away from a boundary of the display substrate.

11. The display substrate according to claim 1, wherein: The first frame area further includes: a first sub-area located on a side of the bending area close to the display area, the first sub-area being connected to the second frame area; The display substrate further includes: a plurality of electrostatic discharge circuits located in the first sub-area, the plurality of electrostatic discharge circuits being disposed adjacent to the plurality of gate driving circuits; The multiple electrostatic discharge circuits are arranged in multiple rows along the first direction, and each row of electrostatic discharge circuits includes multiple electrostatic discharge circuits arranged along a second direction; the second direction intersects the first direction; The at least one first peripheral signal line is located between two adjacent rows of electrostatic discharge circuits.

12. The display substrate according to claim 11, wherein: The multiple electrostatic release circuits are arranged as a first row of electrostatic release circuits, a second row of electrostatic release circuits and a third row of electrostatic release circuits in a direction away from the display area, and the at least one first peripheral signal line is located between the first row of electrostatic release circuits and the second row of electrostatic release circuits. 13 . The display substrate according to claim 11 , comprising a plurality of first peripheral control lines, wherein the plurality of electrostatic discharge circuits are connected to one of the first peripheral control lines.

14. The display substrate according to claim 1, wherein The plurality of gate driving circuits include a first group of gate driving circuits and a second group of gate driving circuits located on both sides of the display area along a second direction, wherein the second direction intersects the first direction; The first group of gate drive circuits is connected to at least one first peripheral control line, and the second group of gate drive circuits is connected to at least one first peripheral control line; The number of gate driving circuits included in the first group of gate driving circuits is the same as the number of gate driving circuits included in the second group of gate driving circuits.

15. A display device comprising the display substrate according to any one of claims 1 to 14.

Images