Pixel circuit, driving method, display substrate, and display apparatus

Abstract

Provided are a pixel circuit (100), a driving method, a display substrate, and a display apparatus. The pixel circuit (100) comprises: a data writing circuit (110), separately electrically connected to a first scan line (Gate1), a data line (Data), and a control terminal of a driving circuit (120), and configured to, under the control of a first scan signal provided by the first scan line (Gate1), write a data voltage provided by the data line (Data) into the control terminal of the driving circuit (120); an energy storage circuit (130), electrically connected to the control terminal of the driving circuit (120), and configured to store electric energy; and the driving circuit (120), configured to drive a light-emitting element (140) under the control of a potential at the control terminal of the driving circuit (120). At least one of the data writing circuit (110) and the driving circuit (120) comprises a first sub-circuit (150) and a second sub-circuit (160) connected in parallel, the first sub-circuit (150) and the second sub-circuit (160) being configured to implement a same function.

Description

Pixel circuit, driving method, display substrate and display device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on March 25, 2024, with application number 202410346809.3 and invention name “Pixel circuit, driving method, display substrate and display device”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The embodiments of the present disclosure relate to, but are not limited to, the field of display technology, and in particular to a pixel circuit, a driving method, a display substrate, and a display device. Background Art

[0003] Display technology uses electronics to provide flexible visual information. Display panels, as the vehicle for implementing this technology, have become widely used. The images displayed on a display panel are generated by multiple pixels controlled by drive signals. Pixel circuits, the circuit structure that provides drive signals for pixels, are an integral part of a display panel.

[0004] Any transistor in the pixel circuit plays an irreplaceable role. Any abnormality in any transistor may cause the pixel corresponding to the pixel circuit to have an abnormality. Some transistor abnormalities will not only cause the pixel corresponding to the pixel circuit to have an abnormality, but also cause signal abnormalities on the signal line, thereby causing abnormalities in other pixels.

[0005] Summary of the Invention

[0006] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0007] Embodiments of the present disclosure provide a pixel circuit, a driving method, a display substrate, and a display device.

[0008] In a first aspect, an embodiment of the present disclosure provides a pixel circuit, comprising a data writing circuit, a driving circuit, an energy storage circuit, and a light-emitting element;

[0009] The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit respectively, and is configured to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line;

[0010] The energy storage circuit is electrically connected to the control terminal of the drive circuit and is configured to store electrical energy;

[0011] The driving circuit is electrically connected to the light emitting element and is configured to drive the light emitting element under the control of the potential of the control terminal of the driving circuit;

[0012] Wherein, at least one of the data writing circuit and the driving circuit includes: a first sub-circuit and a second sub-circuit arranged in parallel, and the first sub-circuit and the second sub-circuit are arranged to achieve the same function.

[0013] In some exemplary embodiments, the first sub-circuit includes a first transistor, and the second sub-circuit includes a second transistor;

[0014] The control electrode of the first transistor is electrically connected to the control electrode of the second transistor, the first electrode of the first transistor is electrically connected to the first electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the second electrode of the second transistor.

[0015] In some exemplary embodiments, the first transistor and the second transistor include a gate layer, a gate insulating layer, an active layer and a source-drain layer that are stacked together, and the orthographic projection of the source-drain layer on the substrate of the display panel where the pixel circuit is arranged is in the shape of a U-shaped Chinese character, and the orthographic projection of the U-shaped source-drain layer includes a first part and a second part that are parallel, and the orthographic projection of the gate layer on the substrate partially covers the first part and the second part, the first transistor corresponds to the first part, and the second transistor corresponds to the second part.

[0016] In some exemplary embodiments, the first sub-circuit includes a first driving sub-circuit, the second sub-circuit includes a second driving sub-circuit, and the driving circuit includes the first driving sub-circuit and the second driving sub-circuit connected in parallel.

[0017] In some exemplary embodiments, the first driving sub-circuit includes a first driving transistor, and the second driving sub-circuit includes a second driving transistor;

[0018] The control electrode of the first driving transistor is electrically connected to the control electrode of the second driving transistor, the first electrode of the first driving transistor is electrically connected to the first electrode of the second driving transistor, and the second electrode of the first driving transistor is electrically connected to the second electrode of the second driving transistor.

[0019] In some exemplary embodiments, the first sub-circuit includes a first data writing sub-circuit, the second sub-circuit includes a second data writing sub-circuit, and the data writing circuit includes the first data writing sub-circuit and the second data writing sub-circuit arranged in parallel.

[0020] In some exemplary embodiments, the first data writing sub-circuit includes a first data writing transistor, and the second data writing sub-circuit includes a second data writing transistor;

[0021] The control electrode of the first data write transistor is electrically connected to the control electrode of the second data write transistor, the first electrode of the first data write transistor is electrically connected to the first electrode of the second data write transistor, and the second electrode of the first data write transistor is electrically connected to the second electrode of the second data write transistor.

[0022] In some exemplary embodiments, the pixel circuit further includes: a detection circuit;

[0023] The detection circuit is electrically connected to the second scan line, the detection line, and a connection node between the drive circuit and the light-emitting element, respectively, and is configured to control the connection between the connection node and the detection line under the control of a second scan signal provided by the second scan line.

[0024] In some exemplary embodiments, the detection circuit includes a first detection sub-circuit and a second detection sub-circuit arranged in parallel;

[0025] The first detection sub-circuit includes a first detection transistor, and the second detection sub-circuit includes a second detection transistor;

[0026] The control electrode of the first detection transistor is electrically connected to the control electrode of the second detection transistor, the first electrode of the first detection transistor is electrically connected to the first electrode of the second detection transistor, and the second electrode of the first detection transistor is electrically connected to the second electrode of the second detection transistor.

[0027] In some exemplary embodiments, the pixel circuit further includes: a compensation circuit, a reset circuit, and a light emitting control circuit;

[0028] The compensation circuit is electrically connected to the first scan line and the driving circuit respectively, and is configured to perform voltage compensation on the driving circuit under the control of a first scan signal provided by the first scan line;

[0029] The reset circuit is electrically connected to the light emitting element and is configured to provide an initialization signal to the light emitting element under the control of a reset signal;

[0030] The light emitting control circuit is electrically connected to the first terminal and the second terminal of the driving circuit respectively, and is configured to connect the driving circuit and the light emitting element under the control of an enable signal;

[0031] Wherein, at least one of the compensation circuit, the reset circuit and the light emitting control circuit includes: a third subcircuit and a fourth subcircuit arranged in parallel, and the third subcircuit and the fourth subcircuit are arranged to achieve the same function.

[0032] In some exemplary embodiments, the third sub-circuit includes a first compensation sub-circuit, the fourth sub-circuit includes a second compensation sub-circuit, and the compensation circuit includes the first compensation sub-circuit and the second compensation sub-circuit connected in parallel.

[0033] In some exemplary embodiments, the first compensation subcircuit includes a first compensation transistor, and the second compensation subcircuit includes a second compensation transistor;

[0034] The control electrode of the first compensation transistor is electrically connected to the control electrode of the second compensation transistor, the first electrode of the first compensation transistor is electrically connected to the first electrode of the second compensation transistor, and the second electrode of the first compensation transistor is electrically connected to the second electrode of the second compensation transistor.

[0035] In some exemplary embodiments, the third sub-circuit includes a first reset sub-circuit, the fourth sub-circuit includes a second reset sub-circuit, and the reset circuit includes the first reset sub-circuit and the second reset sub-circuit connected in parallel.

[0036] In some exemplary embodiments, the first reset subcircuit includes a first reset transistor, and the second reset subcircuit includes a second reset transistor;

[0037] The control electrode of the first reset transistor is electrically connected to the control electrode of the second reset transistor, the first electrode of the first reset transistor is electrically connected to the first electrode of the second reset transistor, and the second electrode of the first reset transistor is electrically connected to the second electrode of the second reset transistor.

[0038] In some exemplary embodiments, the third subcircuit includes a first light-emitting control subcircuit, the fourth subcircuit includes a second light-emitting control subcircuit, and the light-emitting control circuit includes the first light-emitting control subcircuit and the second light-emitting control subcircuit arranged in parallel.

[0039] In some exemplary embodiments, the first light emission control subcircuit includes a first light emission control transistor, and the second light emission control subcircuit includes a second light emission control transistor;

[0040] Alternatively, the first light emission control subcircuit includes a third light emission control transistor, and the second light emission control subcircuit includes a fourth light emission control transistor;

[0041] Alternatively, the first light-emitting control subcircuit includes a first light-emitting control transistor, the second light-emitting control subcircuit includes a second light-emitting control transistor, the first light-emitting control subcircuit further includes a third light-emitting control transistor, and the second light-emitting control subcircuit further includes a fourth light-emitting control transistor.

[0042] In some exemplary embodiments, the control electrode of the first light emission control transistor is electrically connected to the control electrode of the second light emission control transistor, the first electrode of the first light emission control transistor is electrically connected to the first electrode of the second light emission control transistor, and the second electrode of the first light emission control transistor is electrically connected to the second electrode of the second light emission control transistor;

[0043] Alternatively, the control electrode of the third light emitting control transistor is electrically connected to the control electrode of the fourth light emitting control transistor, the first electrode of the third light emitting control transistor is electrically connected to the first electrode of the fourth light emitting control transistor, and the second electrode of the third light emitting control transistor is electrically connected to the second electrode of the fourth light emitting control transistor;

[0044] Alternatively, the control electrode of the first light-emitting control transistor is electrically connected to the control electrode of the second light-emitting control transistor, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the second light-emitting control transistor, the second electrode of the first light-emitting control transistor is electrically connected to the second electrode of the second light-emitting control transistor, the control electrode of the third light-emitting control transistor is electrically connected to the control electrode of the fourth light-emitting control transistor, the first electrode of the third light-emitting control transistor is electrically connected to the first electrode of the fourth light-emitting control transistor, and the second electrode of the third light-emitting control transistor is electrically connected to the second electrode of the fourth light-emitting control transistor.

[0045] In a second aspect, an embodiment of the present disclosure provides a driving method applicable to the pixel circuit described in the first aspect, the driving method comprising:

[0046] Using a data writing circuit, under the control of a first scanning signal provided by a first scanning line, the data voltage provided by the data line is written into the control terminal of the driving circuit;

[0047] The light emitting element is driven by the driving circuit under the control of the potential of the control terminal of the driving circuit.

[0048] In a third aspect, an embodiment of the present disclosure provides a display substrate comprising a plurality of pixel circuits as described in the first aspect arranged in an array.

[0049] In a fourth aspect, an embodiment of the present disclosure provides a display device, comprising: the display substrate according to the third aspect;

[0050] The control circuit is electrically coupled to the display substrate and is configured to provide a control signal to the display substrate.

[0051] Other features and advantages of the present disclosure will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present disclosure. Other advantages of the present disclosure can be realized and obtained through the solutions described in the description and the drawings.

[0052] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0053] Summary of the Figures

[0054] The following is a brief introduction to the drawings used in the embodiments of the present disclosure. The drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0055] FIG1A is a schematic diagram of a 3T1C pixel circuit with a detection transistor turned off in some technologies;

[0056] FIG1B is a schematic diagram of a 3T1C pixel circuit after the detection transistor is cut off in some technologies;

[0057] FIG1C is a timing diagram of a 3T1C pixel circuit in a normal display phase in some technologies;

[0058] FIG1D is a timing diagram of a 3T1C pixel circuit in a normal detection phase in some technologies;

[0059] FIG1E is a timing diagram of an abnormal display phase of a 3T1C pixel circuit in some technologies;

[0060] FIG1F is a timing diagram of a 3T1C pixel circuit abnormality detection phase in some technologies;

[0061] FIG1G is a schematic diagram of a transistor short circuit in a 3T1C pixel circuit in some technologies;

[0062] FIG2A is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure;

[0063] FIG2B is a schematic structural diagram of a pixel circuit in which a transistor is added based on FIG2A according to an embodiment of the present disclosure;

[0064] FIG2C is a schematic structural diagram of a transistor pin according to an embodiment of the present disclosure;

[0065] FIG2D is a schematic diagram of the structure of transistors arranged in parallel according to an embodiment of the present disclosure;

[0066] FIG2E is a schematic top view of a stacked structure of a transistor according to an embodiment of the present disclosure;

[0067] FIG2F is a schematic top view of a stacked structure of transistors arranged in parallel according to an embodiment of the present disclosure;

[0068] FIG2G is a schematic structural diagram of a pixel circuit in which a driving sub-circuit is added based on FIG2A according to an embodiment of the present disclosure;

[0069] FIG2H is a schematic structural diagram of a pixel circuit in which a driving transistor is added based on FIG2G according to an embodiment of the present disclosure;

[0070] FIG2I is a schematic structural diagram of a 3T1C pixel circuit in which driving transistors are arranged in parallel according to an embodiment of the present disclosure;

[0071] FIG2J is a schematic structural diagram of a 3T1C pixel circuit in which an abnormal second driving transistor is cut off according to an embodiment of the present disclosure;

[0072] FIG2K is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure, in which a data writing sub-circuit is added based on FIG2A ;

[0073] FIG2L is a schematic structural diagram of a pixel circuit in which a data writing transistor is added based on FIG2K according to an embodiment of the present disclosure;

[0074] FIG2M is a schematic structural diagram of a 3T1C pixel circuit in which data writing transistors are arranged in parallel according to an embodiment of the present disclosure;

[0075] FIG2N is a schematic structural diagram of a 3T1C pixel circuit in which an abnormal second data writing transistor is cut off according to an embodiment of the present disclosure;

[0076] FIG2O is a schematic structural diagram of a pixel circuit in which a detection circuit is added based on FIG2A according to an embodiment of the present disclosure;

[0077] FIG2P is a schematic structural diagram of a pixel circuit in which a detection sub-circuit is added based on FIG2O according to an embodiment of the present disclosure;

[0078] FIG2Q is a schematic structural diagram of a pixel circuit in which a detection transistor is added based on FIG2P according to an embodiment of the present disclosure;

[0079] FIG2R is a schematic structural diagram of a 3T1C pixel circuit in which detection transistors are arranged in parallel according to an embodiment of the present disclosure;

[0080] FIG2S is a schematic structural diagram of a 3T1C pixel circuit in which an abnormal first detection transistor is cut off according to an embodiment of the present disclosure;

[0081] FIG2T is a schematic structural diagram of a 3T1C pixel circuit in which a data writing transistor and a detection transistor are arranged in parallel according to an embodiment of the present disclosure;

[0082] FIG3A is a schematic structural diagram of another pixel circuit according to an embodiment of the present disclosure;

[0083] FIG3B is a schematic structural diagram of a pixel circuit in which a compensation sub-circuit is added based on FIG3A according to an embodiment of the present disclosure;

[0084] FIG3C is a schematic structural diagram of a pixel circuit in which a compensation transistor is added based on FIG3B according to an embodiment of the present disclosure;

[0085] FIG3D is a schematic structural diagram of a pixel circuit in which a reset subcircuit is added based on FIG3A according to an embodiment of the present disclosure;

[0086] FIG3E is a schematic structural diagram of a pixel circuit in which a reset transistor is added based on FIG3D according to an embodiment of the present disclosure;

[0087] FIG3F is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure, in which a light emitting control subcircuit is added based on FIG3A ;

[0088] FIG3G is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure, in which a light emitting control transistor is added based on FIG3F ;

[0089] FIG3H is a schematic structural diagram of a pixel circuit according to an embodiment of the present disclosure, in which a light emitting control transistor is added based on FIG3F ;

[0090] FIG3I is a schematic structural diagram of a 7T1C pixel circuit in which data writing transistors are arranged in parallel according to an embodiment of the present disclosure;

[0091] FIG4 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0092] Details

[0093] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other in any manner.

[0094] In the embodiments of the present disclosure, unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure have the common meanings understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, which can be direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. In the embodiments of the present disclosure, the use of "suitable for" and "configured to" means open and inclusive language, which does not exclude devices that are suitable for or configured to perform additional tasks or steps.

[0095] Every thin-film transistor (TFT) in a pixel circuit plays an irreplaceable role. Any TFT failure can cause anomalies in the pixel corresponding to the light-emitting element connected to that pixel circuit. Failures in some TFTs can cause not only anomalies in the pixel corresponding to the light-emitting element connected to that pixel circuit, but also anomalies in the signals transmitted by the signal lines connected to that pixel circuit, leading to anomalies in other pixels.

[0096] Figure 1A is a schematic diagram illustrating disconnecting a detection transistor in a 3T1C pixel circuit according to some techniques. As shown in Figure 1A , in a 3T1C pixel circuit (i.e., a pixel circuit comprising three transistors and one capacitor), when external compensation is performed and a fault in the detection transistor T2 occurs, the only way to ensure that signal lines (such as the Sense line) are not affected is to disconnect the detection transistor T2, thereby losing the corresponding pixel in the pixel circuit's light-emitting element.

[0097] Figure 1B illustrates the equivalent circuit of a 3T1C pixel circuit with the detection transistor disconnected, as seen in some technologies. As shown in Figure 1B , disconnecting the detection transistor T2 from the signal line (e.g., the Sense line) prevents abnormalities in the detection transistor T2 from affecting the signal line and, in turn, preventing abnormalities in other pixels.

[0098] In some exemplary embodiments, the operation process of the 3T1C pixel circuit may include two stages, one stage being configured to implement a normal display function (referred to as a normal display stage), and the other stage being configured to implement an external compensation function by detecting the electrical characteristics of a driver TFT (DT) to determine its threshold voltage (referred to as a detection stage).

[0099] FIG1C is a timing diagram of a 3T1C pixel circuit in a normal display phase in some technologies. As shown in FIG1C , the normal display phase can be divided into a data writing period and a light-emitting period. When the normal display function is implemented, during the data writing period of the normal display phase, the first scan line Gate1 and the second scan line Gate2 provide an on-state signal (e.g., a high-level signal) to turn on the switching transistor T1 and the detection transistor T2. The detection line Sense line is connected to the connection point S1, so that the data line Data writes the data voltage Vdata to the first node G, and the detection line Sense line writes the initial voltage V0 to the second node S. During the light-emitting period of the normal display phase, the driving current through the light-emitting element (e.g., the light-emitting diode in FIG1A ) is: I = k(Vdata - V0 - Vth). 2It can be seen that when the threshold voltage Vth of the driving transistor DT is not compensated, the driving current of the light-emitting element is related to the threshold voltage Vth of the driving transistor DT, which will cause the display effect to be affected by the uncontrollable factor of the threshold voltage Vth change.

[0100] FIG. 1D shows a timing diagram of a detection phase (Blank time) of a 3T1C pixel circuit in some technologies. As shown in FIG1D , the detection phase can be divided into a data writing period, a charging period, and a detection period. When the detection function is implemented, during the data writing period of the detection phase, the first scan line Gate1 and the second scan line Gate2 provide an on signal (e.g., a high-level signal) to turn on the switching transistor T1 and the detection transistor T2, and the detection line Sense line is connected to the connection point S1, so that the data voltage Vdata is written to the first node G and the initial voltage V0 is written to the second node S; during the charging period of the detection phase, the detection line Sense line is disconnected from the connection point S1, so that the detection line Sense line is in a floating state (Floating), and the driving transistor DT charges the detection line Sense line until the voltage on the detection line Sense line no longer rises. At this time, the driving transistor DT is turned off, that is, Vgs=0; during the detection period of the detection phase, the analog-to-digital converter ADC samples the voltage Vc on the detection line Sense line, that is, the voltage of the second node S, and can calculate the driving voltage Vth=Vd-Vc on both sides of the driving transistor DT. Afterwards, the data voltage Vdata′=Vdata+Vth is written again according to the detected information, and the driving current through the light-emitting element is: I=k(Vdata′-V0-Vth) 2 =k(Vdata-V0) 2 That is, the driving voltage Vth on both sides of the driving transistor DT in the pixel circuit corresponding to each pixel is different, and the written data voltage Vdata′ is different, thereby ensuring the consistency of the light-emitting current and realizing the external compensation function.

[0101] However, when an abnormality occurs in the detection transistor T2, for example, when the detection transistor T2 is open, the 3T1C pixel circuit will be converted into a 2T1C pixel circuit, and the data voltage will be written and light will be emitted. FIG1E is a timing diagram of the abnormal display stage of the 3T1C pixel circuit in some technologies. As shown in FIG1E , the abnormal display stage can be divided into a data writing time period and a light-emitting stage. During the data writing time period of the abnormal display stage, since the second node S is not charged, the voltage of the second node S is uncertain (indicated by "V?" in FIG1E ); during the light-emitting stage of the abnormal display stage, the Vgs of the driving transistor DT is uncertain, resulting in the inability to control the light-emitting brightness, which may lead to display abnormality.

[0102] Figure 1F is a timing diagram of the abnormality detection phase of a 3T1C pixel circuit in some technologies. As shown in Figure 1F, during detection compensation, the pixel fails to charge the Sense line. The analog-to-digital converter (ADC) samples the voltage V0 on the Sense line and incorrectly calculates the drive voltage Vth = Vd - V0 across the drive transistor DT. This results in the extracted Vth = Vd - V0 being incorrect (Vd - Vc), leading to compensation failure.

[0103] FIG1G is a schematic diagram of a transistor short circuit in a 3T1C pixel circuit in some technologies. As shown in FIG1G , what is more serious is that when a short circuit occurs between the active layer Active and the gate Gate of a TFT (such as the detection transistor T2), that is, when the active layer Active and the scan line Gate line (such as the second scan line Gate2) are short-circuited, the detection line Sense line and the second scan line Gate2 line will be short-circuited, resulting in a signal line abnormality. This will not only affect the pixel, but also affect other pixels (such as any one or more of the pixels in the same row and column as the pixel). At this time, it can be called a "point-to-line defect", that is, a line defect caused by a bad pixel. This situation can be repaired, that is, the detection transistor T2 is cut off, making it the above-mentioned 2T1C pixel circuit, avoiding line defects caused by an abnormality of a pixel point.

[0104] Therefore, how to prevent transistor anomalies from causing anomalies in the pixels corresponding to the pixel circuit and other pixels has become an important research issue.

[0105] The pixel circuit, driving method, display substrate and display device provided by the embodiments of the present disclosure. At least one of the data writing circuit and the driving circuit in the pixel circuit may include: a first sub-circuit and a second sub-circuit arranged in parallel. In this way, when an abnormality occurs in the data writing circuit or any sub-circuit in the driving circuit, the normal operation of the pixel circuit can be ensured by cutting off the sub-circuit where the abnormality occurs, thereby avoiding the abnormality of the pixel circuit, and further avoiding the adverse problems caused by the abnormality affecting other pixels (such as pixels in the same row and column). In addition, when an abnormality occurs in any sub-circuit in the data writing circuit and any sub-circuit in the driving circuit at the same time, the normal operation of the pixel circuit can be ensured by cutting off the sub-circuit where the abnormality occurs, thereby avoiding the adverse problems caused by the abnormality of the pixel circuit and the abnormality of the signal in the signal line to a greater extent.

[0106] The present disclosure provides a pixel circuit. FIG2A is a schematic structural diagram of a pixel circuit according to the present disclosure. As shown in FIG2A , the pixel circuit 100 provided in the present disclosure may include: a data writing circuit 110, a driving circuit 120, a storage circuit 130, and a light-emitting element 140.

[0107] The data writing circuit 110 is electrically connected to the first scan line Gate1, the data line Data, and the control terminal of the driving circuit 120, and is configured to write the data voltage provided by the data line Data into the control terminal of the driving circuit 120 under the control of the first scan signal provided by the first scan line Gate1;

[0108] The energy storage circuit 130 is electrically connected to the control terminal of the driving circuit 120 and is configured to store electrical energy;

[0109] The driving circuit 120 is electrically connected to the light emitting element 140 and is configured to drive the light emitting element 140 under the control of the potential of the control terminal of the driving circuit 120;

[0110] At least one of the data write circuit 110 and the drive circuit 120 may include a first sub-circuit 150 and a second sub-circuit 160 connected in parallel, wherein the first sub-circuit 150 and the second sub-circuit 160 are configured to implement the same function. FIG. 2A illustrates an example in which both the data write circuit 110 and the drive circuit 120 include the first sub-circuit 150 and the second sub-circuit 160 connected in parallel.

[0111] In some exemplary embodiments, the pixel circuit 100 may be a 3T1C pixel circuit. The pixel circuit 100 may include: a data writing circuit 110 , a driving circuit 120 , an energy storage circuit 130 , and a light emitting element 140 .

[0112] Thus, in the pixel circuit 100 provided in the embodiment of the present disclosure, since at least one of the data write circuit 110 and the drive circuit 120 includes: a first sub-circuit 150 and a second sub-circuit 160 arranged in parallel, when an abnormality occurs in any sub-circuit in the data write circuit 110 or any sub-circuit in the drive circuit 120, the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal sub-circuit, thereby avoiding the abnormality of the pixel circuit 100 and further avoiding the adverse problems caused by the abnormality affecting other pixels (such as pixels in the same row and column). In addition, when an abnormality occurs in any sub-circuit in the data write circuit 110 and any sub-circuit in the drive circuit 120 at the same time, the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal sub-circuit, thereby avoiding the adverse problems caused by the abnormality of the pixel circuit 100 and the abnormality of the signal in the signal line to a greater extent.

[0113] In some exemplary embodiments, as shown in FIG2B , the first sub-circuit 150 may include a first transistor 151, and the second sub-circuit 160 may include a second transistor 161; the control electrode of the first transistor 151 is electrically connected to the control electrode of the second transistor 161, the first electrode of the first transistor 151 is electrically connected to the first electrode of the second transistor 161, and the second electrode of the first transistor 151 is electrically connected to the second electrode of the second transistor 161. FIG2A illustrates an example in which the data write circuit 110 and the drive circuit 120 both include the first transistor 151 and the second transistor 161 connected in parallel.

[0114] FIG2C is a schematic diagram of the structure of the transistor pins of an embodiment of the present disclosure. As shown in FIG2C , the pins of the transistor may include: a control electrode, a first electrode, and a second electrode, wherein the control electrode may be a gate, the first electrode may be a source, and the second electrode may be a drain. In cases where transistors with opposite polarities are used or where the direction of current changes during circuit operation, the functions of the "source" and "drain" may sometimes be interchanged. Therefore, in this article, the "source" and "drain" may be interchanged.

[0115] Figure 2D is a schematic diagram of the structure of the parallel arrangement of transistors in an embodiment of the present disclosure. As shown in Figure 2D, the first transistor 151 and the second transistor 161 are arranged in parallel. Among them, the gate (Gate) of the first transistor 151 is electrically connected to the gate (Gate) of the second transistor 161, the source (Source) of the first transistor 151 is electrically connected to the source (Source) of the second transistor 161, and the drain (Drain) of the first transistor 151 is electrically connected to the drain (Drain) of the second transistor 161. In this way, by setting an electrical connection between the corresponding pins of the first transistor 151 and the second transistor 161, the parallel arrangement of the first transistor 151 and the second transistor 161 can be achieved.

[0116] In some exemplary embodiments, a transistor may include a gate layer, a gate insulating layer, an active layer, and a source / drain layer arranged in a stacked manner. FIG2E is a schematic top view of the stacked structure of a transistor according to an embodiment of the present disclosure. As shown in FIG2E , for a single transistor, the orthographic projection of its source / drain layer and gate layer on the substrate of the display panel on which the pixel circuit 100 is disposed may be a cross.

[0117] In some other exemplary embodiments, the structure of FIG. 2E may be improved to obtain two transistors connected in parallel.

[0118] FIG2F is a schematic top view of a stacked structure of transistors arranged in parallel according to an embodiment of the present disclosure. As shown in FIG2F , the first transistor 151 and the second transistor 161 include a gate layer, a gate insulating layer, an active layer, and a source-drain layer arranged in a stacked manner. The orthographic projection of the source-drain layer on the substrate of the display panel in which the pixel circuit 100 is arranged is a Chinese umbilical cord. The orthographic projection of the Chinese umbilical cord-shaped source-drain layer includes a first portion and a second portion that are parallel. The orthographic projection of the gate layer on the substrate partially covers the first portion and the second portion. The first transistor 151 corresponds to the first portion, and the second transistor 161 corresponds to the second portion. In this way, by setting the stacked structure of the first transistor 151 and the second transistor 161, the orthographic projection of the source-drain layer on the substrate of the display panel in which the pixel circuit 100 is arranged is a Chinese umbilical cord, which can realize the parallel arrangement of the first transistor 151 and the second transistor 161. As used herein, "parallel" may include both strictly parallel and "approximately parallel" conditions, including conditions that include a certain degree of error. Taking into account measurement errors and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus includes a state where the angle is greater than -5° and less than 5°.

[0119] In some exemplary embodiments, as shown in FIG2E , along the extension direction of the gate layer (or gate line) of a single TFT, the width of the rectangular source and drain layer's orthographic projection may be approximately 3.5 to 4.5 μm (micrometers). In this case, the width of the overlapping portion of the gate layer and the source and drain layer may be approximately 3.5 to 4.5 μm, and the channel width of the transistor may be approximately 3.5 to 4.5 μm. In this case, the width of the overlapping portion of the gate layer and the source and drain layer is approximately equal to the channel width of the transistor. When the width of the orthographic projection of the source and drain layer is approximately 4 μm, the channel size of the transistor is in, is the channel width-to-length ratio of the transistor, W is the channel width of the transistor, and L is the channel length of the transistor. In the embodiments of the present disclosure, the term "approximately" is used to refer to situations where the limits are not strictly defined and the process and measurement errors are allowed. For example, in the present disclosure, "approximately" can refer to situations where the values ​​differ by 10% or 5%, or can represent one or more standard deviations that are acceptable for a particular value as determined by a person of ordinary skill in the art.

[0120] In some exemplary embodiments, as shown in FIG. 2F, when two transistors are arranged in parallel, along the extending direction of the gate layer, the width of the positive projection of the source-drain layer in the shape of a Chinese character "hui" can be about 3.5 to 4.5 μm, the width of the first part can be about 1.5 to 2.5 μm, and the width of the second part can be about 1.5 to 2.5 μm.

[0121] Exemplarily, as shown in FIG. 2F, when the width of the positive projection of the source-drain layer in the shape of a Chinese character "hui" is 4 μm, the width of the first part is 2 μm, and the width of the second part is 2 μm, the channel sizes of the two transistors arranged in parallel are Where, is the channel width-to-length ratio of the transistor, W is the channel width of the transistor, and L is the channel length of the transistor. In this case, the channel sizes of the first transistor 151 and the second transistor 161 are the same.

[0122] Of course, in addition to the above exemplary manner, in some other exemplary embodiments, the channel sizes of the first transistor 151 and the second transistor 161 can be different. Whether the channel sizes of the first transistor 151 and the second transistor 161 are the same is determined according to whether there are requirements for the channel sizes of the transistors according to their functions.

[0123] Thus, by setting the widths of the first part and the second part of the positive projection to be the same, the channel sizes of the first transistor 151 and the second transistor 161 arranged in parallel can be made the same. Additionally, different channel sizes of the first transistor 151 and the second transistor 161 arranged in parallel can be obtained by setting the widths of the first part and the second part of the positive projection to be different.

[0124] In some exemplary embodiments, as shown in FIG. 2G, the first sub-circuit 150 may include a first driving sub-circuit 121, the second sub-circuit 160 may include a second driving sub-circuit 122, and the driving circuit 120 may include the first driving sub-circuit 121 and the second driving sub-circuit 122 arranged in parallel.

[0125] In some exemplary embodiments, as shown in FIG. 2H, the first driving sub-circuit 121 may include a first driving transistor 1211, and the second driving sub-circuit 122 may include a second driving transistor 1221; the control electrode of the first driving transistor 1211 is electrically connected to the control electrode of the second driving transistor 1221, the first electrode of the first driving transistor 1211 is electrically connected to the first electrode of the second driving transistor 1221, and the second electrode of the first driving transistor 1211 is electrically connected to the second electrode of the second driving transistor 1221.

[0126] In some exemplary embodiments, FIG2I is a schematic diagram illustrating the structure of a 3T1C pixel circuit in which drive transistors are arranged in parallel according to an embodiment of the present disclosure. As shown in FIG2I , the pixel circuit according to an embodiment of the present disclosure may be a 3T1C pixel circuit in which the drive transistors may include a first drive transistor DT and a second drive transistor DT' arranged in parallel.

[0127] For example, in the case of an abnormality in the second drive transistor DT', Figure 2J illustrates the structure of a 3T1C pixel circuit according to an embodiment of the present disclosure, wherein the abnormal second drive transistor is disconnected. As shown in Figure 2J , when the second drive transistor DT' is abnormal, the second drive transistor DT' can be disconnected, and the first drive transistor DT can be utilized to ensure normal operation of the 3T1C pixel circuit.

[0128] In addition, the size of the driving transistor is proportional to the light-emitting current at the location of the light-emitting element. When the abnormal driving transistor is cut off and the normal driving transistor is used to ensure the normal operation of the pixel circuit 100, the image gamma correction (gamma adjustment) is performed through the light compensation process of the optical compensation device. Among them, the optical compensation performs gamma adjustment for each sub-pixel.

[0129] In this way, by setting the driving circuit in the pixel circuit 100 of the embodiment of the present disclosure to include a first driving transistor DT and a second driving transistor DT' arranged in parallel, when an abnormality occurs in either the first driving transistor 1211 or the second driving transistor 1221, the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal driving transistor and utilizing the normal driving transistor.

[0130] In some exemplary embodiments, as shown in Figure 2K, the first sub-circuit 150 may include a first data writing sub-circuit 111, the second sub-circuit 160 may include a second data writing sub-circuit 112, and the data writing circuit 110 may include the first data writing sub-circuit 111 and the second data writing sub-circuit 112 arranged in parallel.

[0131] In some exemplary embodiments, as shown in Figure 2L, the first data write sub-circuit 111 may include a first data write transistor 1111, and the second data write sub-circuit 112 may include a second data write transistor 1121; the control electrode of the first data write transistor 1111 is electrically connected to the control electrode of the second data write transistor 1121, the first electrode of the first data write transistor 1111 is electrically connected to the first electrode of the second data write transistor 1121, and the second electrode of the first data write transistor 1111 is electrically connected to the second electrode of the second data write transistor 1121.

[0132] In some exemplary embodiments, FIG2M is a schematic diagram illustrating the structure of a 3T1C pixel circuit in which data write transistors are arranged in parallel according to an embodiment of the present disclosure. As shown in FIG2M , the pixel circuit in an embodiment of the present disclosure may be a 3T1C pixel circuit in which the data write transistors may include a first data write transistor T1 and a second data write transistor T1′ arranged in parallel.

[0133] For example, in the case of an abnormality in the second data write transistor T1', Figure 2N illustrates the structure of a 3T1C pixel circuit according to an embodiment of the present disclosure, wherein the abnormal second data write transistor is disconnected. As shown in Figure 2N, when an abnormality occurs in the second data write transistor T1', the second data write transistor T1' can be disconnected, and the first data write transistor T1 can be used to ensure normal operation of the 3T1C pixel circuit.

[0134] In this way, by setting the data writing circuit 110 in the pixel circuit 100 of the embodiment of the present disclosure to include a first data writing transistor T1 and a second data writing transistor T1' arranged in parallel, then, when an abnormality occurs in either the first data writing transistor 1111 or the second data writing transistor 1121, the normal operation of the pixel circuit 100 can be ensured by cutting off the data writing transistor with the abnormality and using the data writing transistor without the abnormality.

[0135] In some exemplary embodiments, as shown in FIG2O , the pixel circuit 100 may further include a detection circuit 170; the detection circuit 170 is electrically connected to the second scan line Gate2, the detection line Sense line, and the connection node between the driving circuit 120 and the light-emitting element 140, respectively, and is configured to control the connection between the connection node and the detection line Sense line under the control of the second scan signal provided by the second scan line Gate2.

[0136] In some exemplary embodiments, as shown in FIG. 2P , the detection circuit 170 may include a first detection sub-circuit 171 and a second detection sub-circuit 172 connected in parallel.

[0137] In some exemplary embodiments, as shown in FIG2Q , the first detection sub-circuit 171 may include a first detection transistor 1711, and the second detection sub-circuit 172 may include a second detection transistor 1721; the control electrode of the first detection transistor 1711 is electrically connected to the control electrode of the second detection transistor 1721, the first electrode of the first detection transistor 1711 is electrically connected to the first electrode of the second detection transistor 1721, and the second electrode of the first detection transistor 1711 is electrically connected to the second electrode of the second detection transistor 1721.

[0138] In some exemplary embodiments, Figure 2R illustrates a schematic diagram of a 3T1C pixel circuit with parallel detection transistors according to an embodiment of the present disclosure. As shown in Figure 2R , the pixel circuit according to an embodiment of the present disclosure may be a 3T1C pixel circuit, in which the detection transistors may include a first detection transistor T2 and a second detection transistor T2' arranged in parallel.

[0139] For example, Figure 2S illustrates the structure of a 3T1C pixel circuit, in which the abnormal first detection transistor T2 is disconnected, according to an embodiment of the present disclosure. As shown in Figure 2S , when the abnormal first detection transistor T2 is disconnected, the second detection transistor T2' is utilized to maintain normal operation of the 3T1C pixel circuit.

[0140] In other exemplary embodiments, Figure 2T is a schematic diagram of a 3T1C pixel circuit in which a data write transistor and a detection transistor are arranged in parallel according to an embodiment of the present disclosure. As shown in Figure 2T, the pixel circuit in an embodiment of the present disclosure may be a 3T1C pixel circuit, in which the data write transistor may include a first data write transistor T1 and a second data write transistor T1' arranged in parallel, and the detection transistor may include a first detection transistor T2 and a second detection transistor T2' arranged in parallel.

[0141] In this way, when any of the first data writing transistor T1 and the second data writing transistor T1', and any of the first detection transistor T2 and the second detection transistor T2', malfunction simultaneously, the data writing transistor and the detection transistor that are not malfunctioning can be utilized to ensure the normal operation of the 3T1C pixel circuit, thereby ensuring the normal operation of the 3T1C pixel circuit to a greater extent.

[0142] For example, when the first data writing transistor T1 and the first detecting transistor T2 are abnormal at the same time, the first data writing transistor T1 and the first detecting transistor T2 can be cut off, and the second data writing transistor T1' and the second detecting transistor T2' can be used to ensure the normal operation of the 3T1C pixel circuit.

[0143] For another example, when an abnormality occurs in either the first detection transistor 1711 or the second detection transistor 1721 , the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal detection transistor and using the normal detection transistor.

[0144] In addition to the external compensation method, in some exemplary embodiments, the pixel circuit may adopt an internal compensation method to compensate for the threshold voltage Vth of the driving transistor DT.

[0145] The present disclosure further provides a pixel circuit. FIG3A is a schematic diagram of the structure of another pixel circuit according to the present disclosure. As shown in FIG3A , the pixel circuit 100 provided in the present disclosure may include: a data writing circuit 110, a driving circuit 120, a storage circuit 130, and a light-emitting element 140; the pixel circuit 100 may also include: a compensation circuit 210, a reset circuit 220, and a light-emitting control circuit 230;

[0146] The compensation circuit 210 is electrically connected to the first scan line Gate1 and the driving circuit 120, and is configured to perform voltage compensation on the driving circuit 120 under the control of the first scan signal provided by the first scan line Gate1;

[0147] The reset circuit 220 is electrically connected to the light emitting element 140 and is configured to provide an initialization signal to the light emitting element 140 under the control of a reset signal;

[0148] The light emitting control circuit 230 is electrically connected to the first terminal and the second terminal of the driving circuit 120, respectively, and is configured to connect the driving circuit 120 and the light emitting element 140 under the control of an enable signal;

[0149] At least one of the compensation circuit 210 , the reset circuit 220 and the light emitting control circuit 230 includes: a third subcircuit 240 and a fourth subcircuit 250 arranged in parallel, and the third subcircuit 240 and the fourth subcircuit 250 are arranged to achieve the same function.

[0150] In some exemplary embodiments, the pixel circuit 100 proposed in the embodiments of the present disclosure may be a 7T1C pixel circuit (i.e., the pixel circuit includes 7 transistors and 1 capacitor). In this case, the pixel circuit 100 may include: a data writing circuit 110, a driving circuit 120, a tank circuit 130, a light-emitting element 140, a compensation circuit 210, a reset circuit 220, and a light-emitting control circuit 230. The compensation circuit 210 is configured to implement internal compensation. Because internal compensation can compensate for the threshold voltage Vth of the driving transistor DT, the pixel circuit 100 may no longer include the detection circuit 170.

[0151] Thus, in the pixel circuit 100 provided in the embodiment of the present disclosure, since at least one of the compensation circuit 210, the reset circuit 220, and the light-emission control circuit 230 may include a third sub-circuit 240 and a fourth sub-circuit 250 arranged in parallel, when an abnormality occurs in any of the sub-circuits of at least one of the compensation circuit 210, the reset circuit 220, and the light-emission control circuit 230, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal sub-circuit, thereby preventing the abnormality of the pixel circuit 100 and further preventing adverse problems caused by the abnormality affecting other pixels (such as pixels in the same row and column).

[0152] In some exemplary embodiments, as shown in FIG. 3B , the third sub-circuit 240 may include a first compensation sub-circuit 211 , the fourth sub-circuit 250 may include a second compensation sub-circuit 212 , and the compensation circuit 210 may include the first compensation sub-circuit 211 and the second compensation sub-circuit 212 arranged in parallel.

[0153] In some exemplary embodiments, as shown in FIG3C , the first compensation sub-circuit 211 may include a first compensation transistor 2111, and the second compensation sub-circuit 212 may include a second compensation transistor 2121. The control electrode of the first compensation transistor 2111 is electrically connected to the control electrode of the second compensation transistor 2121, the first electrode of the first compensation transistor 2111 is electrically connected to the first electrode of the second compensation transistor 2121, and the second electrode of the first compensation transistor 2111 is electrically connected to the second electrode of the second compensation transistor 2121. In this way, if either the first compensation transistor 2111 or the second compensation transistor 2121 experiences an abnormality, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal compensation transistor and utilizing the healthy compensation transistor.

[0154] In some exemplary embodiments, as shown in FIG. 3D , the third sub-circuit 240 may include a first reset sub-circuit 221 , the fourth sub-circuit 250 may include a second reset sub-circuit 222 , and the reset circuit 220 may include the first reset sub-circuit 221 and the second reset sub-circuit 222 arranged in parallel.

[0155] In some exemplary embodiments, as shown in FIG3E , the first reset sub-circuit 221 may include a first reset transistor 2211, and the second reset sub-circuit 222 may include a second reset transistor 2221; the control electrode of the first reset transistor 2211 is electrically connected to the control electrode of the second reset transistor 2221, the first electrode of the first reset transistor 2211 is electrically connected to the first electrode of the second reset transistor 2221, and the second electrode of the first reset transistor 2211 is electrically connected to the second electrode of the second reset transistor 2221. Thus, by configuring the reset circuit 220 in the pixel circuit 100 of the present embodiment to include the first reset transistor 2211 and the second reset transistor 2221 arranged in parallel, when either the first reset transistor 2211 or the second reset transistor 2221 experiences an abnormality, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal reset transistor and utilizing the normal reset transistor.

[0156] In some exemplary embodiments, as shown in FIG3F , the third sub-circuit 240 may include a first light-emitting control sub-circuit 231, the fourth sub-circuit 250 may include a second light-emitting control sub-circuit 232, and the light-emitting control circuit 230 may include the first light-emitting control sub-circuit 231 and the second light-emitting control sub-circuit 232 arranged in parallel.

[0157] In some exemplary embodiments, as shown in FIG3G , the first emission control subcircuit 231 may include a first emission control transistor 2311, and the second emission control subcircuit 232 may include a second emission control transistor 2321. Thus, by configuring the emission control circuit 230 in the pixel circuit 100 according to the present disclosure to include the first emission control transistor 2311 and the second emission control transistor 2321 connected in parallel, when an abnormality occurs in either the first emission control transistor 2311 or the second emission control transistor 2321, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal emission control transistor and utilizing the healthy emission control transistor.

[0158] In other exemplary embodiments, as shown in FIG3H , the first emission control subcircuit 231 may include a third emission control transistor 2312, and the second emission control subcircuit 232 may include a fourth emission control transistor 2322. Thus, by configuring the emission control circuit 230 in the pixel circuit 100 of the present disclosure to include the fourth emission control transistor 2322 and the fourth emission control transistor 2322 connected in parallel, when either the first emission control transistor 2311 or the fourth emission control transistor 2322 experiences an abnormality, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal emission control transistor and utilizing the healthy emission control transistor.

[0159] In some further exemplary embodiments, the first light-emitting control subcircuit 231 may include a first light-emitting control transistor 2311, the second light-emitting control subcircuit 232 may include a second light-emitting control transistor 2321, and the first light-emitting control subcircuit 231 may also include a third light-emitting control transistor 2312, and the second light-emitting control subcircuit 232 may also include a fourth light-emitting control transistor 2322.

[0160] In some exemplary embodiments, the control electrode of the first light-emitting control transistor 2311 is electrically connected to the control electrode of the second light-emitting control transistor 2321, the first electrode of the first light-emitting control transistor 2311 is electrically connected to the first electrode of the second light-emitting control transistor 2321, and the second electrode of the first light-emitting control transistor 2311 is electrically connected to the second electrode of the second light-emitting control transistor 2321.

[0161] In other exemplary embodiments, the control electrode of the third light-emitting control transistor 2312 is electrically connected to the control electrode of the fourth light-emitting control transistor 2322, the first electrode of the third light-emitting control transistor 2312 is electrically connected to the first electrode of the fourth light-emitting control transistor 2322, and the second electrode of the third light-emitting control transistor 2312 is electrically connected to the second electrode of the fourth light-emitting control transistor 2322.

[0162] In some further exemplary embodiments, the control electrode of the first light-emitting control transistor 2311 is electrically connected to the control electrode of the second light-emitting control transistor 2321, the first electrode of the first light-emitting control transistor 2311 is electrically connected to the first electrode of the second light-emitting control transistor 2321, the second electrode of the first light-emitting control transistor 2311 is electrically connected to the second electrode of the second light-emitting control transistor 2321, and the control electrode of the third light-emitting control transistor 2312 is electrically connected to the control electrode of the fourth light-emitting control transistor 2322, the first electrode of the third light-emitting control transistor 2312 is electrically connected to the first electrode of the fourth light-emitting control transistor 2322, and the second electrode of the third light-emitting control transistor 2312 is electrically connected to the second electrode of the fourth light-emitting control transistor 2322.

[0163] In some exemplary embodiments, FIG3I is a schematic diagram of a 7T1C pixel circuit in which data write transistors are arranged in parallel, according to an embodiment of the present disclosure. As shown in FIG3I , the pixel circuit in an embodiment of the present disclosure may be a 7T1C pixel circuit, in which the data write transistors include a first data write transistor T1 and a second data write transistor T1' arranged in parallel. In this way, if an abnormality occurs in the second data write transistor T1', the normal operation of the 7T1C pixel circuit is ensured by disconnecting the second data write transistor T1' and utilizing the first data write transistor T1.

[0164] In some exemplary embodiments, the driving transistor DT of the driving circuit 120 can be replaced by the first driving transistor 1211 and the second driving transistor 1221 arranged in parallel. In this way, when one of the driving transistors becomes abnormal, the abnormal driving transistor can be cut off and the other normal driving transistor can be used to ensure that the pixel circuit can still operate normally.

[0165] In some exemplary embodiments, the compensation transistor T3 of the compensation circuit 210 can be replaced by the first compensation transistor 2111 and the second compensation transistor 2121 connected in parallel. In this way, when one of the compensation transistors malfunctions, the abnormal compensation transistor can be disconnected and the other normal compensation transistor can be used to ensure that the pixel circuit can still operate normally.

[0166] In some exemplary embodiments, the reset transistor T4 of the reset circuit 220 can be replaced by the first reset transistor 2111 and the second reset transistor 2121 arranged in parallel. In this way, when one of the first reset transistor 2111 and the second reset transistor 2121 malfunctions, the malfunctioning reset transistor is disconnected, and the other normal reset transistor is used to ensure that the pixel circuit can still operate normally. Alternatively, the reset transistor T5 of the reset circuit 220 can be replaced by the first reset transistor 2111 and the second reset transistor 2121 arranged in parallel. In this way, when one of the reset transistors malfunctions, the malfunctioning reset transistor is disconnected, and the other normal reset transistor is used to ensure that the pixel circuit can still operate normally. Alternatively, the reset transistor T4 of the reset circuit 220 can be replaced by the first reset transistor 2111 and the second reset transistor 2121 arranged in parallel, and the reset transistor T5 of the reset circuit 220 can be replaced by the first reset transistor 2111 and the second reset transistor 2121 arranged in parallel. In this way, when an abnormality occurs in one of the reset transistors, the abnormal reset transistor can be cut off and the other normal reset transistor can be used to ensure that the pixel circuit can still work normally.

[0167] In some exemplary embodiments, the light-emission control transistor T6 of the light-emission control circuit 230 can be replaced by the first light-emission control transistor 2311 and the second light-emission control transistor 2321 arranged in parallel, and the light-emission control transistor T7 of the light-emission control circuit 230 can be replaced by the third light-emission control transistor 2312 and the fourth light-emission control transistor 2322 arranged in parallel. In this way, when one of the light-emission control transistors becomes abnormal, the abnormal light-emission control transistor can be cut off and the other normal light-emission control transistor can be used to ensure that the pixel circuit can still operate normally.

[0168] In the pixel circuit provided by the exemplary embodiment of the present disclosure, at least one of the data write circuit 110 and the drive circuit 120 in the pixel circuit 100 includes: a first sub-circuit 150 and a second sub-circuit 160 arranged in parallel. In this way, when an abnormality occurs in any sub-circuit in the data write circuit 110 or the drive circuit 120, the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal sub-circuit, thereby avoiding the abnormality of the pixel circuit 100 and further avoiding the adverse problems caused by the abnormality affecting other pixels (such as pixels in the same row and column). Alternatively, when an abnormality occurs in any sub-circuit in the data write circuit 110 and any sub-circuit in the drive circuit 120 at the same time, the normal operation of the pixel circuit 100 can be ensured by cutting off the abnormal sub-circuit, thereby avoiding the adverse problems caused by the abnormality of the pixel circuit 100 and the abnormality of the signal in the signal line to a greater extent.

[0169] The present disclosure further proposes a driving method, which is applicable to the pixel circuit 100 described in the above embodiment. As shown in FIG4 , the method includes:

[0170] In step 401 , the data voltage Vdata provided by the data line Data is written into the control terminal of the driving circuit 120 by using the data writing circuit 110 under the control of the first scanning signal provided by the first scanning line Gate1 .

[0171] In step 402 , the light emitting element 140 is driven by the driving circuit 120 under the control of the potential of the control terminal of the driving circuit 120 .

[0172] Through the above embodiment, the pixel circuit 100 described in the above embodiment is utilized, and the data write circuit 110 and the drive circuit 120 are utilized to control the light-emitting element 140, so that the pixel circuit 100 operates normally. Because at least one of the data write circuit 110 and the drive circuit 120 in the pixel circuit 100 includes a first sub-circuit 150 and a second sub-circuit 160 connected in parallel, when an abnormality occurs in either the data write circuit 110 or the drive circuit 120, the normal operation of the pixel circuit 100 can be ensured by disconnecting the abnormal sub-circuit, thereby preventing the abnormality in the pixel circuit 100 and, in turn, preventing adverse effects caused by the abnormality affecting other pixels (e.g., pixels in the same row and column).

[0173] The method of the embodiment of the present disclosure can be performed by a single device, such as a mobile phone, wearable device, computer, or server. The method of this embodiment can also be configured in a distributed scenario, where multiple devices cooperate with each other to complete the method. In this distributed scenario, one of the multiple devices may only perform one or more steps of the method of the embodiment of the present disclosure, and the multiple devices will interact with each other to complete the method.

[0174] The foregoing describes some embodiments of the present disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than described in the above embodiments and still achieve the desired results. Furthermore, the processes depicted in the accompanying drawings do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0175] The present disclosure also provides a display substrate comprising a plurality of pixel circuits according to any one of the above embodiments arranged in an array.

[0176] The display substrate of the above embodiment executes the driving method as described in any of the above embodiments and has the beneficial effects of the corresponding method embodiments, which will not be described in detail here.

[0177] The present disclosure also provides a display device, comprising: the display substrate described in the above embodiment; and a control circuit electrically coupled to the display substrate and configured to provide a control signal to the display substrate. The display device may be an LCD (Liquid Crystal Display), an AR (Augmented Reality) display, an electronic paper, an OLED (Organic Light-Emitting Diode), a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a smart wearable device, or other product or component with a display function.

[0178] Those skilled in the art will understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of the embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0179] In addition, to simplify the description and discussion, and so as not to obscure the embodiments of the present disclosure, known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided figures. In addition, devices may be shown in the form of block diagrams to avoid obscuring the embodiments of the present disclosure, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which the embodiments of the present disclosure are to be implemented (i.e., these details are well within the purview of those skilled in the art). Where exemplary details (e.g., circuits) are set forth to describe exemplary embodiments of the present disclosure, it will be apparent to those skilled in the art that the embodiments of the present disclosure may be implemented without these exemplary details or with variations in these exemplary details. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0180] Although the present disclosure has been described in conjunction with exemplary embodiments thereof, many alternatives, modifications, and variations of these embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the discussed embodiments.

[0181] The embodiments of the present disclosure are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present disclosure should be included in the scope of protection of the present disclosure.

Claims

1. A pixel circuit comprising: Data writing circuit, driving circuit, energy storage circuit and light emitting element; The data writing circuit is electrically connected to the first scan line, the data line and the control terminal of the driving circuit respectively, and is configured to write the data voltage provided by the data line into the control terminal of the driving circuit under the control of the first scan signal provided by the first scan line; The energy storage circuit is electrically connected to the control terminal of the drive circuit and is configured to store electrical energy; The driving circuit is electrically connected to the light emitting element and is configured to drive the light emitting element under the control of the potential of the control terminal of the driving circuit; Wherein, at least one of the data writing circuit and the driving circuit includes: a first sub-circuit and a second sub-circuit arranged in parallel, and the first sub-circuit and the second sub-circuit are arranged to achieve the same function.

2. The pixel circuit according to claim 1, wherein: The first sub-circuit includes a first transistor, and the second sub-circuit includes a second transistor; The control electrode of the first transistor is electrically connected to the control electrode of the second transistor, the first electrode of the first transistor is electrically connected to the first electrode of the second transistor, and the second electrode of the first transistor is electrically connected to the second electrode of the second transistor.

3. The pixel circuit according to claim 2, wherein: The first transistor and the second transistor include: a gate layer, a gate insulating layer, an active layer and a source-drain layer arranged in a stacked manner, the source-drain layer having an orthographic projection on a substrate of a display panel on which the pixel circuit is arranged is in the shape of a Chinese umbilical cord, the orthographic projection of the Chinese umbilical cord-shaped source-drain layer including a first part and a second part which are parallel, the orthographic projection of the gate layer on the substrate partially covering the first part and the second part, the first transistor corresponding to the first part, and the second transistor corresponding to the second part.

4. The pixel circuit according to claim 1, wherein: The first sub-circuit includes a first driving sub-circuit, the second sub-circuit includes a second driving sub-circuit, and the driving circuit includes the first driving sub-circuit and the second driving sub-circuit arranged in parallel.

5. The pixel circuit according to claim 4, wherein: The first driving sub-circuit includes a first driving transistor, and the second driving sub-circuit includes a second driving transistor; The control electrode of the first driving transistor is electrically connected to the control electrode of the second driving transistor, the first electrode of the first driving transistor is electrically connected to the first electrode of the second driving transistor, and the second electrode of the first driving transistor is electrically connected to the second electrode of the second driving transistor. The pixel circuit according to claim 1 , wherein: The first sub-circuit includes a first data writing sub-circuit, the second sub-circuit includes a second data writing sub-circuit, and the data writing circuit includes the first data writing sub-circuit and the second data writing sub-circuit arranged in parallel.

7. The pixel circuit according to claim 6, wherein: The first data writing sub-circuit includes a first data writing transistor, and the second data writing sub-circuit includes a second data writing transistor; The control electrode of the first data write transistor is electrically connected to the control electrode of the second data write transistor, the first electrode of the first data write transistor is electrically connected to the first electrode of the second data write transistor, and the second electrode of the first data write transistor is electrically connected to the second electrode of the second data write transistor.

8. The pixel circuit according to claim 1 , further comprising: Detection circuit; The detection circuit is electrically connected to the second scan line, the detection line, and the connection node between the drive circuit and the light emitting element, and is configured to control the connection node to be connected to the light emitting element under the control of the second scan signal provided by the second scan line. The detection lines are connected to each other.

9. The pixel circuit according to claim 8, wherein: The detection circuit includes: a first detection sub-circuit and a second detection sub-circuit arranged in parallel; The first detection sub-circuit includes a first detection transistor, and the second detection sub-circuit includes a second detection transistor; The control electrode of the first detection transistor is electrically connected to the control electrode of the second detection transistor, the first electrode of the first detection transistor is electrically connected to the first electrode of the second detection transistor, and the second electrode of the first detection transistor is electrically connected to the second electrode of the second detection transistor.

10. The pixel circuit according to claim 1, further comprising: Compensation circuit, reset circuit and light-emitting control circuit; The compensation circuit is electrically connected to the first scan line and the driving circuit respectively, and is configured to perform voltage compensation on the driving circuit under the control of a first scan signal provided by the first scan line; The reset circuit is electrically connected to the light emitting element and is configured to provide an initialization signal to the light emitting element under the control of a reset signal; The light emitting control circuit is electrically connected to the first terminal and the second terminal of the driving circuit respectively, and is configured to connect the driving circuit and the light emitting element under the control of an enable signal; Wherein, at least one of the compensation circuit, the reset circuit and the light emitting control circuit includes: a third subcircuit and a fourth subcircuit arranged in parallel, and the third subcircuit and the fourth subcircuit are arranged to achieve the same function.

11. The pixel circuit according to claim 10, wherein: The third sub-circuit includes a first compensation sub-circuit, the fourth sub-circuit includes a second compensation sub-circuit, and the compensation circuit includes the first compensation sub-circuit and the second compensation sub-circuit connected in parallel.

12. The pixel circuit according to claim 11, wherein: The first compensation subcircuit includes a first compensation transistor, and the second compensation subcircuit includes a second compensation transistor; The control electrode of the first compensation transistor is electrically connected to the control electrode of the second compensation transistor, the first electrode of the first compensation transistor is electrically connected to the first electrode of the second compensation transistor, and the second electrode of the first compensation transistor is electrically connected to the second electrode of the second compensation transistor.

13. The pixel circuit according to claim 10, wherein: The third sub-circuit includes a first reset sub-circuit, the fourth sub-circuit includes a second reset sub-circuit, and the reset circuit includes the first reset sub-circuit and the second reset sub-circuit connected in parallel.

14. The pixel circuit according to claim 13, wherein: The first reset sub-circuit includes a first reset transistor, and the second reset sub-circuit includes a second reset transistor; The control electrode of the first reset transistor is electrically connected to the control electrode of the second reset transistor, the first electrode of the first reset transistor is electrically connected to the first electrode of the second reset transistor, and the second electrode of the first reset transistor is electrically connected to the second electrode of the second reset transistor.

15. The pixel circuit according to claim 10, wherein: The third subcircuit includes a first light-emitting control subcircuit, the fourth subcircuit includes a second light-emitting control subcircuit, and the light-emitting control circuit includes the first light-emitting control subcircuit and the second light-emitting control subcircuit arranged in parallel.

16. The pixel circuit according to claim 15, wherein: The first light emission control subcircuit includes a first light emission control transistor, and the second light emission control subcircuit includes a second light emission control transistor; Alternatively, the first light emission control subcircuit includes a third light emission control transistor, and the second light emission control subcircuit includes a fourth light emission control transistor; Alternatively, the first light-emitting control subcircuit includes a first light-emitting control transistor, the second light-emitting control subcircuit includes a second light-emitting control transistor, the first light-emitting control subcircuit further includes a third light-emitting control transistor, and the second light-emitting control subcircuit further includes a fourth light-emitting control transistor.

17. The pixel circuit according to claim 16, wherein: The control electrode of the first light emitting control transistor is electrically connected to the control electrode of the second light emitting control transistor, the first electrode of the first light emitting control transistor is electrically connected to the first electrode of the second light emitting control transistor, and the second electrode of the first light emitting control transistor is electrically connected to the second electrode of the second light emitting control transistor; Alternatively, the control electrode of the third light emitting control transistor is electrically connected to the control electrode of the fourth light emitting control transistor, the first electrode of the third light emitting control transistor is electrically connected to the first electrode of the fourth light emitting control transistor, and the second electrode of the third light emitting control transistor is electrically connected to the second electrode of the fourth light emitting control transistor; Alternatively, the control electrode of the first light-emitting control transistor is electrically connected to the control electrode of the second light-emitting control transistor, the first electrode of the first light-emitting control transistor is electrically connected to the first electrode of the second light-emitting control transistor, the second electrode of the first light-emitting control transistor is electrically connected to the second electrode of the second light-emitting control transistor, the control electrode of the third light-emitting control transistor is electrically connected to the control electrode of the fourth light-emitting control transistor, the first electrode of the third light-emitting control transistor is electrically connected to the first electrode of the fourth light-emitting control transistor, and the second electrode of the third light-emitting control transistor is electrically connected to the second electrode of the fourth light-emitting control transistor.

18. A driving method, applicable to the pixel circuit according to any one of claims 1 to 17, wherein: The driving method includes: Using a data writing circuit, under the control of a first scanning signal provided by a first scanning line, the data voltage provided by the data line is written into the control terminal of the driving circuit; The light emitting element is driven by the driving circuit under the control of the potential of the control terminal of the driving circuit.

19. A display substrate comprising a plurality of pixel circuits according to any one of claims 1 to 17 arranged in an array.

20. A display device comprising: The display substrate according to claim 19; The control circuit is electrically coupled to the display substrate and is configured to provide a control signal to the display substrate.

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