Shift register, driving circuit, driving method, and display device

Abstract

The present disclosure relates to the technical field of display, and provides a shift register, a driving circuit, a driving method, and a display device. The shift register comprises a first control circuit, configured to control the potential of a first node under the control of a first clock signal from a first clock end; a gating circuit, configured to control the potential of the first node under the control of a plurality of gating signals from a plurality of gating ends; an input circuit, configured to control the potential of a second node under the control of the potential of the first node and a second clock signal from a second clock end; a second control circuit, configured to control the potential of a third node under the control of the potential of the second node; and an output circuit, configured to output a scanning signal under the control of the potentials of the second node and the third node.

Description

Shift register, driving circuit, driving method and display device

[0001] This application claims priority to Chinese patent application No. 202410374745.8 filed on March 29, 2024, the contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a shift register, a driving circuit, a driving method, and a display device. Background Art

[0003] To achieve a good balance between power consumption and high refresh rates, displays typically use regional high refresh rate technology, which requires the driver circuit to have flexible activation capabilities. Conventional shift register driver circuits have limited display drive capabilities and cannot adjust in real time to the image, thus failing to meet the more flexible high refresh rate requirements of displays. Summary of the Invention

[0004] The present disclosure provides a shift register, a driving circuit, a driving method and a display device.

[0005] According to a first aspect, the present disclosure provides a shift register, comprising: a first control circuit, configured to control the potential of a first node under the control of a first clock signal from a first clock terminal; a selection circuit, configured to control the potential of the first node under the control of multiple selection signals from multiple selection terminals; an input circuit, configured to control the potential of a second node under the control of the potential of the first node and a second clock signal from a second clock terminal; a second control circuit, configured to control the potential of a third node under the control of the potential of the second node; and an output circuit, configured to output a scan signal under the control of the potentials of the second node and the third node.

[0006] According to an embodiment of the present disclosure, the gating circuit controls the potential of the first node under the control of multiple gating signals from multiple gating terminals, and the gating circuit is configured to: control the potential of the first node to be maintained at a second level under the control of a first level of the multiple gating signals; and pull down the potential of the first node under the control of a second level of any one of the multiple gating signals.

[0007] According to an embodiment of the present disclosure, the gating circuit is further configured to: control the potential of the first node to be maintained at the second level under the control of the first level of the third node; and pull down the potential of the first node under the control of the second level of the third node.

[0008] According to an embodiment of the present disclosure, the first control circuit controls the potential of the first node under the control of a first clock signal from a first clock end. The first control circuit is configured to: charge the first node with a first voltage of a first power supply under the control of a second level of the first clock signal, and control the potential of the first node to be a second level; and maintain the potential of the first node to be the second level when the first clock signal is at the first level.

[0009] According to an embodiment of the present disclosure, the shift register further includes: a pull-down circuit configured to: pull down the potential of the third node under the control of the potential of the first node and the second clock signal; and pull down the potential of the second node under the control of the second level of the third node.

[0010] According to an embodiment of the present disclosure, the shift register also includes: a reset circuit, configured to reset the fourth node through the second voltage of the second power supply under the control of the first clock signal; and reset the potential of the second node under the control of the potential of the first node and the potential of the fourth node.

[0011] According to an embodiment of the present disclosure, the shift register further includes: a third control circuit electrically connected to the input circuit, the third control circuit being configured to control a voltage provided to the input circuit under control of a first voltage of the first power supply.

[0012] According to an embodiment of the present disclosure, the output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

[0013] According to an embodiment of the present disclosure, the gating circuit includes a tenth transistor, a twelfth transistor, and multiple gating transistors; wherein the control electrode of the tenth transistor and the control electrode of the twelfth transistor are electrically connected to the third node, the first electrode of the tenth transistor and the first electrode of the twelfth transistor are electrically connected to the first node, and the second electrode of the tenth transistor and the second electrode of the twelfth transistor are electrically connected to the first electrodes of the multiple gating transistors; the control electrodes of the multiple gating transistors are respectively electrically connected to the multiple gating terminals, and the second electrodes of the multiple gating transistors are electrically connected to the first clock terminal.

[0014] According to an embodiment of the present disclosure, the first control circuit includes a first transistor, an eleventh transistor, a thirteenth transistor, a first capacitor and a second capacitor; wherein, the control electrode of the first transistor is electrically connected to the first clock terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the eleventh transistor; the first electrode of the eleventh transistor is electrically connected to the first power supply, and the second electrode of the eleventh transistor is electrically connected to the first node; the control electrode of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first power supply, and the second electrode of the thirteenth transistor is electrically connected to the selection circuit; the first end of the first capacitor is electrically connected to the control electrode of the eleventh transistor, and the second end of the first capacitor is electrically connected to the first node; and the first end of the second capacitor is electrically connected to the first power supply, and the second end of the second capacitor is electrically connected to the first node.

[0015] According to an embodiment of the present disclosure, the second node includes a first subnode and a second subnode, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor; wherein the control electrode and the first electrode of the fifteenth transistor are electrically connected to the third power supply, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; the control electrode of the sixteenth transistor is electrically connected to the third power supply, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; the control electrode of the seventeenth transistor is electrically connected to the first subnode, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to the fourth power supply; the first electrode of the eighteenth transistor is electrically connected to the third power supply, and the second electrode of the eighteenth transistor is electrically connected to the third node; the control electrode of the nineteenth transistor is electrically connected to the second subnode, the first electrode of the nineteenth transistor is electrically connected to the third node, and the second electrode of the nineteenth transistor is electrically connected to the second power supply.

[0016] According to an embodiment of the present disclosure, the second node includes a first subnode and a second subnode, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor and a nineteenth transistor; wherein the control electrode and the first electrode of the fifteenth transistor are electrically connected to the first clock terminal, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; the control electrode of the sixteenth transistor is electrically connected to the first clock terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; the control electrode of the seventeenth transistor is electrically connected to the second subnode, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to the second electrode of the fifteenth transistor; the first electrode of the eighteenth transistor is electrically connected to the second electrode of the fifteenth transistor, and the second electrode of the eighteenth transistor is electrically connected to the first power supply; and the control electrode of the nineteenth transistor is electrically connected to the first subnode, the first electrode of the nineteenth transistor is electrically connected to the second electrode of the seventeenth transistor, and the second electrode of the nineteenth transistor is electrically connected to the second power supply.

[0017] According to an embodiment of the present disclosure, the second node includes a first sub-node and a second sub-node, and the input circuit includes a fourteenth transistor, a twenty-second transistor, and a twenty-fifth transistor; wherein the control electrode of the fourteenth transistor is electrically connected to the second clock terminal, the first electrode of the fourteenth transistor is electrically connected to the first power supply, and the second electrode of the fourteenth transistor is electrically connected to the fourth node; the control electrode of the twenty-second transistor is electrically connected to the first node, the first electrode of the twenty-second transistor is electrically connected to the fourth node, and the second electrode of the twenty-second transistor is electrically connected to the first sub-node; and the control electrode of the twenty-fifth transistor is electrically connected to the first node, the first electrode of the twenty-fifth transistor is electrically connected to the fourth node, and the second electrode of the twenty-fifth transistor is electrically connected to the second sub-node.

[0018] According to an embodiment of the present disclosure, the second node includes a first subnode and a second subnode, and the pull-down circuit includes a twentieth transistor, a twenty-first transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-sixth transistor, a twenty-seventh transistor and a twenty-eighth transistor; wherein the control electrode of the twentieth transistor is electrically connected to the first node, the first electrode of the twentieth transistor is electrically connected to the third node, and the second electrode of the twentieth transistor is electrically connected to the first electrode of the twenty-first transistor; the control electrode of the twenty-first transistor is electrically connected to the first clock terminal, and the second electrode of the twenty-first transistor is electrically connected to the second power supply; the control electrode of the twenty-third transistor, the control electrode of the twenty-fourth transistor, the control electrode of the twenty-sixth transistor and the control electrode of the twenty-seventh transistor are electrically connected to the third node; the twenty-third transistor is connected in series with the twenty-fourth transistor, the first electrode of the twenty-third transistor is electrically connected to the first subnode, and the second electrode of the twenty-fourth transistor is electrically connected to the second power supply; the twenty-sixth transistor is connected in series with the twenty-seventh transistor, the first electrode of the twenty-sixth transistor is electrically connected to the second subnode, and the second electrode of the twenty-seventh transistor is electrically connected to the second power supply; and the control electrode of the twenty-eighth transistor is electrically connected to the first subnode, the first electrode of the twenty-eighth transistor is electrically connected to the second electrode of the twenty-third transistor and the second electrode of the twenty-sixth transistor, and the second electrode of the twenty-eighth transistor is electrically connected to the first power supply.

[0019] According to an embodiment of the present disclosure, the reset circuit includes a twenty-ninth transistor and a thirtieth transistor; wherein the twenty-ninth transistor and the thirtieth transistor are connected in series, the control electrodes of the twenty-ninth transistor and the thirtieth transistor are electrically connected to the first clock terminal, the first electrode of the twenty-ninth transistor is electrically connected to the fourth node, and the second electrode of the thirtieth transistor is electrically connected to the second power supply.

[0020] According to a second aspect, the present disclosure provides a driving circuit, comprising M driving unit groups, each driving unit group comprising a plurality of shift registers as provided in any one embodiment of the present disclosure; wherein the mth driving unit group is electrically connected to the first selection end group, the m+1th driving unit group is electrically connected to the second selection end group, the selection signal output by the first selection end group is opposite to the selection signal output by the second selection end group, 1≤m<M, and M is a positive integer.

[0021] According to an embodiment of the present disclosure, the number of first gate terminals included in the first gate terminal group is the same as the number of second gate terminals included in the second gate terminal group, and the number of first gate terminals is the same as the number of gate transistors included in the shift register.

[0022] According to an embodiment of the present disclosure, the multiple shift registers included in the mth driving unit group are connected in the same manner as the multiple selection terminals included in the first selection terminal group, and the multiple shift registers included in the m+1th driving unit group are connected in the same manner as the multiple second selection terminals included in the second selection terminal group.

[0023] According to a third aspect, the present disclosure provides a display device comprising a display panel; and a driving circuit as provided in an embodiment of the present disclosure; wherein the display panel comprises a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0024] According to the fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided in the embodiment of the present disclosure, including: in the selection stage, controlling multiple selection signals to be the first level; in the non-selection stage, controlling at least one selection signal among the multiple selection signals to be the second level. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] FIG1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0026] FIG2 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0027] FIG3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0028] FIG4A is a schematic diagram of signal timing of a shift register according to an embodiment of the present disclosure;

[0029] FIG4B is a schematic diagram of a simulation of voltages in a shift register according to an embodiment of the present disclosure;

[0030] FIG4C is a schematic diagram of signal timing of a shift register according to another embodiment of the present disclosure;

[0031] FIG5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0032] FIG6 is a schematic diagram of signal timing of a shift register according to another embodiment of the present disclosure;

[0033] FIG7 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0034] FIG8A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0035] FIG8B is a signal timing diagram of a driving circuit according to an embodiment of the present disclosure;

[0036] FIG9A is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure;

[0037] 9B is a signal timing diagram of a driving circuit according to another embodiment of the present disclosure;

[0038] FIG9C is a timing diagram of a strobe signal according to an embodiment of the present disclosure;

[0039] FIG10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0040] FIG. 11 is a flowchart of a driving method according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of them. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are represented by the same or similar figure marks. In the following description, some specific embodiments are only for descriptive purposes and should not be understood as any limitation to the present disclosure, but are only examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual size and proportion, but only illustrate the contents of the embodiments of the present disclosure.

[0042] Unless otherwise defined, technical or scientific terms used in the embodiments of the present disclosure shall have the same general meaning as those skilled in the art. The terms "first," "second," and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are merely used to distinguish different components.

[0043] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may refer to a direct connection between two components or a connection between two components via one or more other components. In addition, the two components may be connected or coupled via a wired or wireless manner.

[0044] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetrical, so the source and drain are interchangeable. In the embodiments of the present disclosure, depending on their functions, the control electrode may be referred to as the control electrode, one of the source and drain may be referred to as the first electrode, and the other of the source and drain may be referred to as the second electrode.

[0045] It should be noted that in the description of the embodiments of the present disclosure, the symbol SCOUT can represent both a scan signal and an output terminal of the scan signal. Similarly, the symbol GVDD can represent both a power supply and a voltage provided by the power supply, the symbol VGL can represent both a power supply and a voltage provided by the power supply, and the symbol VGH can represent both a power supply and a voltage provided by the power supply. For example, the power supplies VGL and LVGL can provide a low voltage, while the power supplies VGH and GVDD can provide a high voltage. The following embodiments are similar to this, and similar parts are not repeated here.

[0046] FIG1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

[0047] As shown in FIG. 1 , the shift register 100 includes a first control circuit 110 , a gating circuit 120 , an input circuit 130 , a second control circuit 140 , and an output circuit 150 .

[0048] In the embodiment of the present disclosure, the first control circuit 110 is electrically connected to the first clock terminal CLK1, the selection circuit 120 is electrically connected to multiple selection terminals D0, D1, ..., Dn, the input circuit 130 is electrically connected to the second clock terminal CLK2, and the output circuit 150 is electrically connected to the output terminal SCOUT.

[0049] The first control circuit 110, the selection circuit 120 and the input circuit 130 are electrically connected to the first node P, the input circuit 130, the second control circuit 140 and the output circuit 150 are electrically connected to the second node QN, and the second control circuit 140 and the output circuit are electrically connected to the third node QB.

[0050] In the embodiment of the present disclosure, the first control circuit 110 is configured to control the potential of the first node P under the control of the first clock signal CLK1 from the first clock terminal CLK1. The selection circuit 120 is configured to control the potential of the first node P under the control of multiple selection signals D0, D1, ..., Dn from multiple selection terminals D0, D1, ..., Dn. The input circuit 130 is configured to control the potential of the second node QN under the control of the potential of the first node P and the second clock signal CLK2 from the second clock terminal CLK2. The second control circuit 140 is configured to control the potential of the third node QB under the control of the potential of the second node QN. The output circuit 150 is configured to output the scan signal SCOUT from the output terminal SCOUT under the control of the potentials of the second node QN and the third node QB.

[0051] In the disclosed embodiment, when the multiple selection signals D0-Dn are all at a low level and the first clock signal at the first clock terminal is also at a low level, the first node P is at a high potential, and the circuit is in the selection phase. When the second clock signal at the second clock terminal is at a high level, the input circuit controls the second node QN to a high potential, while the second control circuit 140 controls the third node QB to a low potential, ensuring normal output of the output circuit.

[0052] When at least one of the plurality of selection signals is at a high level, the potential of the first node P becomes low, and the shift register 100 is in a non-selection stage.

[0053] When the shift register is in the non-selected phase, the second control circuit 140 controls the second node QB to be at a low level and the third node QB to be at a high level, so that the shift register 100 can output a low voltage in the non-selected phase. When the shift register is in the selected phase, the second control circuit 140 controls the second node QN to be at a low level and the third node QB to be at a low level, so that the output circuit 150 of the shift register can output normally, and the potentials of the second node QN and the third node QB are reversed.

[0054] In the embodiment of the present disclosure, when the multiple selection signals are all at a low level, the first node P remains at a high potential, causing the second node QN to be at a high potential, thereby ensuring that the output terminal of the output circuit 150 outputs normally, and the shift register 100 remains in the selection stage. When one of the multiple selection signals is at a high level, the potential of the first node P is pulled down to a low level, causing the second node QN to be at a low potential, and the output terminal SCOUT of the output circuit 150 stops outputting, and the shift register 100 enters the non-selection stage.

[0055] According to the embodiments of the present disclosure, whether the shift register is in the gating phase can be directly determined by controlling the first node with a gating signal, resulting in a simple structure. In a driving circuit including multiple shift registers, any shift register can be selected for gating by the gating signal, providing flexible activation capability.

[0056] In the embodiment of the present disclosure, the first level can be a low level, and the second level can be a high level. Under the control of the low level of the multiple selection signals, the selection circuit 120 controls the potential of the first node P to remain at a high level, and the shift register 100 is in the selection stage. When any of the multiple selection signals is at a high level, the selection circuit 120 controls the potential of the first node P to be pulled down from the high level to the low level, and the shift register 100 is in the non-selection stage.

[0057] In an embodiment of the present disclosure, when the third node QB is at a low level, the gating circuit 120 controls the potential of the first node P to be maintained at a high level under the control of the low level of the third node QB. When the third node QB is at a high level, the potential of the first node P is pulled down to a low level under the control of the high level of the third node QB.

[0058] Under the control of the low level of the third node QB, the gating circuit 120 is in the cut-off state, which can control the potential of the first node P to be kept at a high level, thereby preventing the first node P from being electrically connected to the first clock terminal CLK1 and causing leakage.

[0059] In an embodiment of the present disclosure, under the control of the high level of the first clock signal CLK1, the first control circuit 110 charges the first node P with the first voltage VGH of the first power supply VGH, so that the potential of the first node P is at a high level. When the first clock signal CLK1 is at a low level, the first control circuit 110 maintains the potential of the first node P at a low level.

[0060] In an embodiment of the present disclosure, the output circuit 150 may include multiple output terminals SCOUT1, SCOUT2, ..., SCOUTn, which are configured to output multiple scan signals SCOUT1, SCOUT2, ..., SCOUTn for driving multiple rows of sub-pixel units.

[0061] FIG2 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0062] As shown in FIG. 2 , the shift register 200 includes a first control circuit 210 , a gating circuit 220 , an input circuit 230 , a second control circuit 240 , an output circuit 250 , a pull-down circuit 260 , and a reset circuit 270 .

[0063] In the embodiment of the present disclosure, the first control circuit 210, the gating circuit 220, the input circuit 230, the second control circuit 240 and the output circuit 250 are respectively similar in structure to the first control circuit 110, the gating circuit 120, the input circuit 130, the second control circuit 140 and the output circuit 150 described above, and are not further described for the sake of simplicity.

[0064] In the embodiment of the present disclosure, the pull-down circuit 260 is electrically connected to the second clock terminal CLK2 , and the reset circuit 270 is electrically connected to the first clock terminal CLK1 and the second power source LVGL.

[0065] In an embodiment of the present disclosure, the first control circuit 210, the selection circuit 220, the input circuit 230 and the pull-down circuit 260 are electrically connected to the first node P, the input circuit 230, the second control circuit 240, the output circuit 250 and the pull-down circuit 260 are electrically connected to the second node QN, the second control circuit 240, the output circuit 250 and the pull-down circuit 260 are electrically connected to the third node QB, and the reset circuit 270 and the input circuit 230 are electrically connected to the fourth node Q.

[0066] It should be noted that the present disclosure does not limit the number of output terminals.

[0067] In an embodiment of the present disclosure, when the first node P is at a high level and the second clock signal CLK2 is at a high level, the pull-down circuit 260 controls the potential of the third node QB to be pulled down to a low level under the control of the first node P and the second clock signal CLK2. Under the control of the low level of the third node QB, the potential of the second node QN is controlled to be pulled down to a low level.

[0068] When the output circuit 250 outputs normally, the pull-down circuit 260 controls the potential of the second node QB to be low, thereby preventing the second node QB from being coupled to a high potential, which would cause noise in the scan signal.

[0069] In the embodiment of the present disclosure, under the control of the high level of the first clock signal, the reset circuit 270 resets the fourth node Q via the second voltage LVGL of the second power supply LVGL, thereby controlling the fourth node Q to be at a low level. At this time, the first node P is at a high level. Under the control of the high level of the first node P and the low level of the fourth node, the reset circuit resets the potential of the second node QN, thereby controlling the second node QN to be at a low level.

[0070] Under the control of the first clock signal CLK1 , the reset circuit 270 resets the fourth node Q in the initial stage. Meanwhile, when the shift register is in the gating stage, the reset circuit 270 can continuously reset the fourth node Q.

[0071] FIG3 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0072] As shown in FIG. 3 , the shift register 300 includes a first control circuit 310 , a gating circuit 320 , an input circuit 330 , a second control circuit 340 , an output circuit 350 , a pull-down circuit 360 , and a reset circuit 370 .

[0073] In the embodiment of the present disclosure, the first control circuit 310 includes a first transistor T1, an eleventh transistor T11, a thirteenth transistor T13, a first capacitor C1, and a second capacitor C2. The gating circuit 320 includes a second transistor to a ninth transistor T2-T9, a tenth transistor T10, and a twelfth transistor T12 connected in parallel, wherein the second transistor to the ninth transistor T2-T9 can be a gating transistor. The input circuit 330 includes a fourteenth transistor T14, a twenty-second transistor T22, and a twenty-fifth transistor T25. The second control circuit 340 includes a fifteenth transistor T15, a sixteenth transistor T16, a seventeenth transistor T17, an eighteenth transistor T18, and a nineteenth transistor T19. The output circuit 350 includes a thirty-first transistor T31, a thirty-second transistor T32, a thirty-third transistor T33, and a thirty-fourth transistor T34. The pull-down circuit 360 includes a 20th transistor T20, a 21st transistor T21, a 23rd transistor T23, a 24th transistor T24, a 26th transistor T26, a 27th transistor T27, and a 28th transistor T28. The reset circuit 370 includes a 29th transistor T29 and a 30th transistor T30. The first transistor T1 to the 34th transistor T34 are all N-type transistors.

[0074] In the embodiment of the present disclosure, the second node QN may include a first sub-node Q1 and a second sub-node Q2.

[0075] In the embodiment of the present disclosure, the control electrode of the first transistor T1 is electrically connected to the first clock terminal CLK1, the first electrode of the first transistor T1 is electrically connected to the first power supply VGH, and the second electrode of the first transistor T1 is electrically connected to the control electrode of the eleventh transistor T11.

[0076] A control electrode of the eleventh transistor T11 is electrically connected to the first end of the first capacitor C1 , a first electrode of the eleventh transistor T11 is electrically connected to the first power supply VGH, and a second electrode of the eleventh transistor T11 is electrically connected to the first node P. A second end of the first capacitor C1 is electrically connected to the first node P.

[0077] A control electrode of the thirteenth transistor T13 is electrically connected to the first node P, a first electrode of the thirteenth transistor T13 is electrically connected to the first power supply VGH, and a second electrode of the thirteenth transistor T13 is electrically connected to the gating circuit 120 .

[0078] A first terminal of the second capacitor C2 is electrically connected to the first power source VGH, and a second terminal of the second capacitor C2 is electrically connected to the first node P.

[0079] The control electrodes of the second to ninth transistors T2-T9 are respectively electrically connected to the gate terminals D0-D7 of the first gate terminal group, the second electrodes of the second to ninth transistors T2-T9 are electrically connected to the first clock segment CLK1, and the first electrodes of the second to ninth transistors T2-T9 are electrically connected to the second electrode of the tenth transistor T10 and the second electrode of the twelfth transistor T12.

[0080] The control electrodes of the tenth transistor and the twelfth transistor are electrically connected to the third node QB, and the first electrodes of the tenth transistor T10 and the twelfth transistor T12 are electrically connected to the first node P.

[0081] A control electrode of the fourteenth transistor T14 is electrically connected to the second clock terminal CLK2 , a first electrode of the fourteenth transistor T14 is electrically connected to the first power supply VGH, and a second electrode of the fourteenth transistor T14 is electrically connected to the fourth node Q.

[0082] A control electrode of the twenty-second transistor T22 is electrically connected to the first node P, a first electrode of the twenty-second transistor T22 is electrically connected to the fourth node Q, and a second electrode of the twenty-second transistor T22 is electrically connected to the first sub-node Q1.

[0083] A control electrode of the twenty-fifth transistor T25 is electrically connected to the first node P, a first electrode of the twenty-fifth transistor T25 is electrically connected to the fourth node Q, and a second electrode of the twenty-fifth transistor is electrically connected to the second sub-node Q2.

[0084] The control electrode and the first electrode of the fifteenth transistor T15 are electrically connected to the third power supply GVDD, and the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16.

[0085] A control electrode of the sixteenth transistor T16 is electrically connected to the third power supply GVDD, and a second electrode of the sixteenth transistor T16 is electrically connected to a control electrode of the eighteenth transistor T18.

[0086] A control electrode of the seventeenth transistor T17 is electrically connected to the first subnode Q1 , a first electrode of the seventeenth transistor T17 is electrically connected to the control electrode of the eighteenth transistor T18 , and a second electrode of the seventeenth transistor T17 is electrically connected to the fourth power supply VGL.

[0087] A first electrode of the eighteenth transistor T18 is electrically connected to the third power supply GVDD, and a second electrode of the eighteenth transistor T18 is electrically connected to the third node QB.

[0088] A control electrode of the nineteenth transistor T19 is electrically connected to the second subnode Q2 , a first electrode of the nineteenth transistor T19 is electrically connected to the third node QB, and a second electrode of the nineteenth transistor T19 is electrically connected to the second power supply LVGL.

[0089] A control electrode of the twentieth transistor T20 is electrically connected to the first node P, a first electrode of the twentieth transistor T20 is electrically connected to the third node QB, and a second electrode of the twentieth transistor T20 is electrically connected to a first electrode of the twenty-first transistor T21.

[0090] A control electrode of the twenty-first transistor T21 is electrically connected to the first clock terminal CLK1 , and a second electrode of the twenty-first transistor T21 is electrically connected to the second power source LVGL.

[0091] The control electrodes of the twenty-third transistor T23 , the twenty-fourth transistor T24 , the twenty-sixth transistor T26 , and the twenty-seventh transistor T27 are electrically connected to the third node QB.

[0092] The twenty-third transistor T23 and the twenty-fourth transistor T24 are connected in series. A first electrode of the twenty-third transistor T23 is electrically connected to the first sub-node Q1 , and a second electrode of the twenty-fourth transistor T24 is electrically connected to the second power source LVGL.

[0093] The twenty-sixth transistor T26 and the twenty-seventh transistor T27 are connected in series. A first electrode of the twenty-sixth transistor T26 is electrically connected to the second subnode Q2 , and a second electrode of the twenty-seventh transistor T27 is electrically connected to the second power source LVGL.

[0094] The control electrode of the twenty-eighth transistor T28 is electrically connected to the first subnode Q1 , the first electrode of the twenty-eighth transistor T28 is electrically connected to the second electrode of the twenty-third transistor T23 and the second electrode of the twenty-sixth transistor T26 , and the second electrode of the twenty-eighth transistor T28 is electrically connected to the first power supply VGH.

[0095] The twenty-ninth transistor T29 and the thirtieth transistor T30 are connected in series, and the control electrodes of the twenty-ninth transistor T29 and the thirtieth transistor T30 are electrically connected to the first clock terminal CLK1, the first electrode of the twenty-ninth transistor T29 is electrically connected to the fourth node Q, and the second electrode of the thirtieth transistor T30 is electrically connected to the second power supply LVGL.

[0096] In the embodiment of the present disclosure, the control electrode of the thirty-first transistor T31 is electrically connected to the first sub-node Q1, the first electrode of the thirty-first transistor T31 is electrically connected to the clock terminal CLKE1, and the second electrode of the thirty-first transistor T31 is electrically connected to the first output terminal SCOUT(1).

[0097] A control electrode of the 32nd transistor T32 is electrically connected to the third node QB, a first electrode of the 32nd transistor T32 is electrically connected to the fourth power supply VGL, and a second electrode of the 32nd transistor T32 is electrically connected to the first output terminal SCOUT(1).

[0098] A first terminal of the third capacitor C3 is connected to the first sub-node Q1 , and a second terminal of the third capacitor C3 is connected to the first output terminal SCOUT( 1 ).

[0099] The control electrode of the thirty-third transistor T33 is electrically connected to the second sub-node Q2 , the first electrode of the thirty-third transistor T33 is electrically connected to the clock terminal CLKE2 , and the second electrode of the thirty-third transistor T33 is electrically connected to the second output terminal SCOUT( 2 ).

[0100] A control electrode of the 34th transistor T34 is electrically connected to the third node QB, a first electrode of the 34th transistor T34 is electrically connected to the fourth power supply VGL, and a second electrode of the 34th transistor T34 is electrically connected to the second output terminal SCOUT( 2 ).

[0101] A first terminal of the fourth capacitor C4 is electrically connected to the second sub-node Q2 , and a second terminal of the fourth capacitor C2 is electrically connected to the second output terminal SCOUT( 2 ).

[0102] It should be noted that the present disclosure does not limit the number of output terminals.

[0103] Figures 4A and 4C are signal timing diagrams of the shift register in Figure 3, and Figures 4A and 4C respectively show the timing waveforms of each signal in each stage during the forward and reverse sweep processes. Figure 4B is a simulation diagram of the voltage in the shift register according to an embodiment of the present disclosure.

[0104] The following takes the structure of the shift register shown in Figure 3 as an example, and describes the working process of the shift register provided by the embodiment of the present disclosure in combination with the signal timing diagrams shown in Figures 4A and 4C. The forward scanning and reverse scanning working processes of the shift register both include five stages.

[0105] For example, Figure 4A shows the signal timings in the five stages S1-S5 during the forward scanning process of the shift register 300. Figure 4A shows the signal timings provided to the first stage shift register in the cascaded plurality of shift registers.

[0106] Before the forward scan process begins, the first clock signal CLK1 outputs a high level, causing the potential of the first node P to reach a high level. The 29th transistor T29 and the 30th transistor T30 are turned on. The fourth node Q, the first subnode Q1, and the second subnode Q2 are reset via the 30th transistor T30, the 29th transistor T29, the 25th transistor T25, and the 22nd transistor T22, respectively. During the forward scan process, when the first clock signal CLK1 is at a high level, the above nodes are also reset.

[0107] In the first phase S1, the first clock signal CLK1 transitions from a high level to a low level, the select signals D0-D7 are low, the second clock signal is low, and the clock signals CLKE1 and CLKE2 are low. The first voltage VGH is high, the second voltage LVGL is low, the third voltage GVDD is high, and the fourth voltage VGL is low. The second voltage LVGL is lower than the fourth power supply voltage VGL. Because the threshold voltage Vth of a transistor is prone to negative drift, leading to leakage, when the second voltage LVGL is lower than the fourth voltage VGL, the Vgs (LVGL-VGL) value of the transistor in the off state can be negative.

[0108] When the first clock signal CLK1 is at a high level, the first transistor T1 is turned on under the control of the first clock signal CLK1. Since the first voltage VGH is at a high level, the high level is provided to the first terminal of the first capacitor C1 through the first transistor T1, thereby charging the first capacitor C1. The first capacitor C1 stores the high level, causing the potential of the first node P to be at a high level.

[0109] Under the control of the third voltage GVDD, the fifteenth transistor T15, the sixteenth transistor T16, and the eighteenth transistor T18 are turned on, so that the third node QB is at a high level.

[0110] Under the control of the high level of the third node QB, the twenty-third transistor T23, the twenty-fourth transistor T24, the twenty-sixth transistor T26, and the twenty-seventh transistor T27 are turned on. Under the control of the second voltage LVGL, a low level is provided to the first sub-node Q1 through the twenty-fourth transistor T24 and the twenty-third transistor T23, so that the first sub-node Q1 maintains a low level. The low level is provided to the second sub-node Q2 through the twenty-seventh transistor T27 and the twenty-sixth transistor T26, so that the second sub-node maintains a low level.

[0111] Under the control of the high level of the first node P, the 22nd transistor T22 is turned on, and the low level is provided to the fourth node Q through the 22nd transistor T22, so that the potential of the fourth node Q remains at a low level.

[0112] Under the control of the selection signals D0-D7, the second to ninth transistors T2 to T9 are turned off, the potential of the first node P is not affected by the second to ninth transistors T2 to T9 and is not reduced, and the potential of the first node P is maintained at a high level.

[0113] When the first clock signal CLK1 changes from a high level to a low level, under the control of the first clock signal CLK1, the first transistor T1 is turned off. Since the first capacitor C1 maintains a high potential, the eleventh transistor T11 remains on, so that the first voltage VGH is provided to the first node P, and the first node P remains at a high level.

[0114] In the second phase S2 , the first clock signal CLK1 is at a low level, and the second clock signal CLK2 changes from a low level to a high level.

[0115] Under the control of the second clock signal CLK2 , the fourteenth transistor T14 is turned on, and the first voltage VGH is provided to the fourth node Q through the fourteenth transistor T14 , so that the potential of the fourth node Q is at a high level.

[0116] Under the control of the high level of the first node P, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned on. The first voltage VGH is supplied to the first sub-node Q1 through the twenty-second transistor T22, and the first voltage VGH is supplied to the second sub-node Q2 through the twenty-fourth transistor T24, so that the potentials of the first sub-node Q1 and the second sub-node Q2 are high.

[0117] Under the control of the high level of the first subnode Q1 and the second subnode Q2, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on. The fourth voltage VGL is provided to the eighteenth transistor T18 through the seventeenth transistor T17. Under the control of the fourth voltage VGL, the eighteenth transistor T18 is turned off.

[0118] Under the control of the second clock signal CLK2, the 21st transistor T21 is turned on. Under the control of the high level of the first node P, the 20th transistor T20 is turned on. At this time, the low level of the second voltage LVGL is provided to the third node QB through the 20th transistor T20 and the 21st transistor T21, so that the potential of the third node QB is pulled down to a low level.

[0119] In the embodiment of the present disclosure, when the select terminals D0-D7 are all at a low level and the first clock signal CLK1 is at a low level, the first and second terminals of the transistors T2-T9 are also at a low level. However, since the threshold voltage Vth is generally negative, if the tenth transistor T10 and the twelfth transistor T12 are not present, the transistors T2-T9 may not be completely turned off, and Vgs may be less than 0, causing the potential of the first node P to become low under the influence of the first clock signal CLK1. The tenth transistor T10 and the twelfth transistor T12 provided in the shift register of the present disclosure are turned off under the control of the low potential of the third node QB, thereby avoiding leakage caused by the fourth node Q being connected to the low potential through the transistors T2-T9.

[0120] Furthermore, when the first and second subnodes Q1 and Q2 are at a high level, the seventeenth and nineteenth transistors T17 and T19 are turned on. Because the fifteenth, sixteenth, and eighteenth transistors T15, T16, and T18 are relatively small, when the seventeenth transistor T17 is turned on, the control electrode of the eighteenth transistor T18 drops to a negative voltage, operating in the saturation region. When the nineteenth transistor T19 is turned on, it operates in the linear region. Consequently, the third node QB is controlled to a low level, achieving potential inversion.

[0121] In the third phase S3 , the first clock signal CLK1 and the second clock signal CLK2 maintain a low level.

[0122] Under the control of the second clock signal CLK2, the potentials of the fourth node Q, the first subnode Q1, and the second subnode Q2 are maintained at a high level, and the third node QB is at a low level. Under the control of the high level of the first subnode Q1, the thirty-first transistor T31 is turned on, and the clock signal CLKE1 is provided to the first output terminal SCOUT(1) through the thirty-first transistor T31. Therefore, the first scan signal SCOUT(1) of the first output terminal SCOUT(1) is the same as the clock signal CLKE1. Under the control of the high level of the second subnode Q2, the thirty-third transistor T33 is turned on, and the clock signal CLKE2 is provided to the second output terminal SCOUT(2) through the thirty-third transistor T33. Therefore, the second scan signal SCOUT(2) of the second output terminal SCOUT(2) is the same as the clock signal CLKE2.

[0123] Due to the bootstrap effect of the third capacitor C3 and the fourth capacitor C4, after the thirty-first transistor T31 and the thirty-third transistor T33 are turned on, the third capacitor C3 continues to charge the first subnode Q1 and the fourth capacitor C4 continues to charge the second subnode, so that the potentials of the first subnode Q1 and the second subnode Q2 further increase.

[0124] At the end of the third phase S3, since the first capacitor C1 has finished discharging, the potential of the first node P becomes low under the control of the low level of the first clock signal CLK1. The gating phase of the shift register ends, and the first output terminal SCOUT(1) and the second output terminal SCOUT(2) stop outputting.

[0125] In the embodiment of the present disclosure, when the clock signal CLKE1 reaches a high level, the 30th transistor T31 is turned on. Due to the presence of the third capacitor C3, the 23rd and 24th transistors T23 and T24 of the present disclosure can prevent the first subnode Q1 from being coupled to a high potential and causing noise on the output. The 26th and 27th transistors T26 and T27 function similarly for the second subnode Q2 and will not be further described.

[0126] In the fourth stage S4 , the first clock signal is at a high level.

[0127] Under the control of the first clock signal, the 29th transistor T29 and the 30th transistor T30 are turned on, and the second voltage LVGL is provided to the fourth node Q through the 30th transistor T30 and the 29th transistor T29, so that the potential of the fourth node Q drops to a low level.

[0128] Under the control of the first clock signal, the first transistor T1 is turned on, and the first voltage VGH is provided to the first node P through the first transistor T1, causing the potential of the first node P to reach a high level. At the same time, the first capacitor C1, which was discharged during the third stage S3, is recharged. At this time, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned on, and the potentials of the first sub-node Q1 and the second sub-node Q2 drop to a low level.

[0129] Under the control of the low level of the first subnode Q1 and the second subnode Q2, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the eighteenth transistor T18 is turned on. The third voltage GVDD is provided to the third node QB through the eighteenth transistor T18, so that the potential of the third node QB is high.

[0130] In the fifth stage S5 , the strobe signal D0 of the strobe terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0131] Under the control of the selection signal D0, the second transistor T2 is turned on. Under the control of the high level of the third node QB, the tenth transistor T10 is turned on, and the first clock signal CLK1 is provided to the first node P through the second transistor T2 and the tenth transistor T10, so that the potential of the first node P becomes a low level.

[0132] Under the control of the low level of the first node P, the twenty-second transistor T22 and the twenty-fifth transistor T25 are turned off, so that the potentials of the first subnode Q1 and the second subnode Q2 drop to a low level, and the thirty-first transistor T31 and the thirty-third transistor T33 are turned off.

[0133] Under the control of the first clock signal and the selection signal D0, the shift register is in a non-selection stage.

[0134] In the disclosed embodiment, shift register gating is achieved through a total of 12 signals: D0-D7, CLK1 and CLK2, CLKE1, and CLKE2, resulting in a streamlined architecture. Each shift register can provide two scan signals. In a GOA unit composed of two shift registers provided by the disclosed embodiment, eight gating signals can support gating 1024 rows. If the number of rows needs to be increased, each additional gating signal can support gating twice as many rows.

[0135] FIG4B is a schematic diagram of a simulation of voltages in a shift register according to an embodiment of the present disclosure.

[0136] As shown in FIG4B , the simulated waveforms of the signal potentials in each stage of the shift register provided by the embodiment of the present disclosure are similar to the timing waveforms described in FIG4A , which will not be described in detail for the sake of brevity.

[0137] FIG4C is a schematic diagram of signal timing of a shift register according to another embodiment of the present disclosure.

[0138] 4C shows the signal timing provided to the last shift register in the cascaded plurality of shift registers. The third clock signal CLK3 and the fourth clock signal CLK4 are provided to the last shift register. The clock signals CLKE3 and CLKE4 are provided to the first shift register.

[0139] The timing of the fourth clock signal CLK4 is the same as the timing of the first clock signal CLK1 shown in FIG4A. The timing of the third clock signal CLK3 is the same as the timing of the second clock signal CLK2 shown in FIG4A. The timing of the clock signal CLKE4 is the same as the timing of the clock signal CLKE1 shown in FIG4A. The timing of the clock signal CLKE3 is the same as the timing of the clock signal CLKE2 shown in FIG4A.

[0140] The control of the fourth clock signal CLK4 on the last shift register can refer to the control of the first shift register by the first clock signal CLK1 described above. The control of the third clock signal CLK3 on the last shift register can refer to the control of the first shift register by the second clock signal CLK2 described above.

[0141] The control of the last shift register by the clock signal CLKE4 may refer to the control of the first shift register by the clock signal CLKE1 described above. The control of the last shift register by the clock signal CLKE3 may refer to the control of the first shift register by the clock signal CLKE2 described above.

[0142] When the last stage of the shift register is the 512th stage, the scan signals of the output terminal SCOUT (1023) and the output terminal SCOUT (1024) are respectively the first scan signal SCOUT (1) and the second scan signal SCOUT (2) output by the first stage shift register shown in FIG4A .

[0143] During the backscan process, the timing of each signal in the five stages S1-S5 of the last stage shift register is similar to that described in FIG4A , and will not be repeated for the sake of brevity.

[0144] FIG5 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0145] As shown in FIG. 5 , the shift register 500 includes a first control circuit 510 , a gate circuit 520 , an input circuit 530 , a second control circuit 540 , an output circuit 550 , a pull-down circuit 560 , and a reset circuit 570 .

[0146] In the embodiment of the present disclosure, the first control circuit 510, the gating circuit 520, the input circuit 530, the second control circuit 540, the pull-down circuit 560 and the reset circuit 570 are respectively similar in structure to the first control circuit 310, the gating circuit 320, the input circuit 330, the second control circuit 340, the pull-down circuit 360 and the reset circuit 370 described above, and are not further described for the sake of simplicity.

[0147] In the embodiment of the present disclosure, the second node QN may include a first sub-node Q1 , a second sub-node Q2 , a third sub-node Q3 and a fourth sub-node Q4 .

[0148] In the embodiment of the present disclosure, the output circuit 550, in addition to the control circuit 350 described above, further includes a 35th transistor T35, a 36th transistor T36, a 37th transistor T37, a 38th transistor T38, a 39th transistor T39, a 40th transistor T40, a 41st transistor T41, a 42nd transistor T42, a 43rd transistor T43, a 44th transistor T44, a fifth capacitor C5, and a sixth capacitor C6. The 35th to 44th transistors T35 to T44 are all N-type transistors.

[0149] A control terminal of the 35th transistor T35 is electrically connected to the first node P, a first terminal of the 35th transistor T35 is electrically connected to the fourth node Q, and a second terminal of the 35th transistor T35 is electrically connected to the third sub-node Q3.

[0150] The thirty-sixth transistor T36 and the thirty-seventh transistor T37 are connected in series, the control electrode of the thirty-sixth transistor T36 and the control electrode of the thirty-seventh transistor T37 are electrically connected to the third node QB, the second electrode of the thirty-sixth transistor T36 is electrically connected to the third sub-node Q3, and the second electrode of the thirty-seventh transistor T37 is electrically connected to the second power supply LVGL.

[0151] The control electrode of the 38th transistor T38 is electrically connected to the third sub-node Q3 , the first electrode of the 38th transistor T38 is electrically connected to the clock terminal CLKE3 , and the second electrode of the 38th transistor T38 is electrically connected to the third output terminal SCOUT( 3 ).

[0152] A control electrode of the thirty-ninth transistor T39 is electrically connected to the third node QB, a first electrode of the thirty-ninth transistor T39 is electrically connected to the fourth power supply VGL, and a second electrode of the thirty-ninth transistor T39 is electrically connected to the third output terminal SCOUT( 3 ).

[0153] A control terminal of the 40th transistor T40 is electrically connected to the first node P, a first electrode of the 40th transistor T40 is electrically connected to the fourth node Q, and a second electrode of the 35th transistor T35 is electrically connected to the third sub-node Q3.

[0154] The forty-first transistor T41 and the forty-second transistor T42 are connected in series, the control electrode of the forty-first transistor T41 and the control electrode of the forty-second transistor T42 are electrically connected to the fourth sub-node Q4, the second electrode of the forty-first transistor T41 is electrically connected to the fourth sub-node Q4, and the second electrode of the forty-second transistor T42 is electrically connected to the second power supply LVGL.

[0155] The control electrode of the forty-third transistor T43 is electrically connected to the fourth sub-node Q4, the first electrode of the forty-third transistor T43 is electrically connected to the clock terminal CLKE4, and the second electrode of the forty-third transistor T43 is electrically connected to the fourth output terminal SCOUT(4).

[0156] A control electrode of the forty-fourth transistor T44 is electrically connected to the third node QB, a first electrode of the forty-fourth transistor T44 is electrically connected to the fourth power supply VGL, and a second electrode of the forty-fourth transistor T44 is electrically connected to the fourth output terminal SCOUT(4).

[0157] FIG6 is a schematic diagram of signal timing of a shift register according to another embodiment of the present disclosure.

[0158] As shown in FIG6 , FIG6 shows the timing waveforms of various signals in each stage of the forward scanning process of the shift register 500 .

[0159] The following describes the process of the shift register provided by the embodiment of the present disclosure, taking the structure of the shift register 500 shown in FIG5 as an example, in conjunction with the signal timing diagram shown in FIG6. The timing changes of the first clock signal CLK1, the second clock signal CLK2, the clock signal CLKE1, the clock signal CLKE2, the first sub-node Q1, the second sub-node Q2, the first node P, the third node QB, and the fourth node Q are similar to the timing changes of the signals described above, and are not further described for the sake of simplicity.

[0160] In the first stage S1 , the timing changes of the signals in the shift register 500 are similar to those described above, and will not be repeated for the sake of brevity.

[0161] In the second phase S2 , the second clock signal CLK2 changes from a low level to a high level.

[0162] Under the control of the high level of the first node P, the 35th transistor T35 and the 40th transistor T40 are turned on. The first voltage VGH is supplied to the third sub-node Q3 through the 35th transistor T35, and the first voltage VGH is supplied to the fourth sub-node Q4 through the 40th transistor T40, so that the potentials of the third sub-node Q3 and the fourth sub-node Q4 are high.

[0163] Under the control of the high level of the first subnode Q1 and the fourth subnode Q4, the seventeenth transistor T17 and the nineteenth transistor T19 are turned on, and the fourth voltage VGL is provided to the eighteenth transistor T18 through the seventeenth transistor T17. Under the control of the fourth voltage VGL, the eighteenth transistor T18 is turned off.

[0164] In the third phase S3 , the first clock signal CLK1 and the second clock signal CLK2 maintain a low level.

[0165] Under the control of the second clock signal CLK2, the potentials of the fourth node Q, the third subnode Q3, and the fourth subnode Q4 are maintained at a high level, and the third node QB is at a low level. Under the control of the high level of the third subnode Q3, the thirty-eighth transistor T38 is turned on, and the clock signal CLKE3 is provided to the third output terminal SCOUT(3) through the thirty-eighth transistor T38. Therefore, the third scanning signal SCOUT(3) of the third output terminal SCOUT(3) is the same as the clock signal CLKE3. Under the control of the high level of the fourth subnode Q4, the forty-third transistor T43 is turned on, and the clock signal CLKE4 is provided to the output terminal SCOUT(4) through the forty-third transistor T43. Therefore, the fourth scanning signal SCOUT(4) of the fourth output terminal SCOUT(4) is the same as the clock signal CLKE4.

[0166] Due to the bootstrap effect of the fifth capacitor C5 and the sixth capacitor C6, after the thirty-eighth transistor T38 and the forty-third transistor T43 are turned on, the fifth capacitor C5 continues to charge the third subnode Q3 and the sixth capacitor C6 continues to charge the fourth subnode Q4, so that the potentials of the third subnode Q3 and the fourth subnode Q4 further increase.

[0167] In the fourth stage S4 , the first clock signal is at a high level.

[0168] Under the control of the first clock signal, the 29th transistor T29 and the 30th transistor T30 are turned on, and the second voltage LVGL is provided to the fourth node Q through the 30th transistor T30 and the 29th transistor T29, so that the potential of the fourth node Q drops to a low level.

[0169] Under the control of the first clock signal, the first transistor T1 is turned on, and the first voltage VGH is provided to the first node P through the first transistor T1, causing the potential of the first node P to reach a high level. At the same time, the first capacitor C1, which was discharged during the third stage S3, is recharged. At this time, the 35th transistor T35 and the 40th transistor T40 are turned on, and the potentials of the third sub-node Q3 and the fourth sub-node Q4 drop to a low level.

[0170] Under the control of the low level of the first subnode Q1 and the fourth subnode Q4, the seventeenth transistor T17 and the nineteenth transistor T19 are turned off, and the eighteenth transistor T18 is turned on. The third voltage GVDD is provided to the third node QB through the eighteenth transistor T18, so that the potential of the third node QB is high.

[0171] In the fifth stage S5 , the strobe signal D0 of the strobe terminal D0 is at a high level, and the first clock signal CLK1 is at a low level.

[0172] Under the control of the selection signal D0, the second transistor T2 is turned on. Under the control of the high level of the third node QB, the tenth transistor T10 is turned on, and the first clock signal is provided to the first node P through the second transistor T2 and the tenth transistor T10, so that the potential of the first node P becomes a low level.

[0173] Under the control of the low level of the first node P, the 35th transistor T35 and the 40th transistor T40 are turned off, so that the potentials of the third subnode Q2 and the fourth subnode Q4 are reduced to a low level, and the 38th transistor T38 and the 43rd transistor T43 are turned off.

[0174] Under the control of the first clock signal and the selection signal D0, the shift register is in a non-selection stage.

[0175] FIG7 is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0176] As shown in FIG. 7 , the shift register 700 includes a first control circuit 710 , a strobe circuit 720 , an input circuit 730 , a second control circuit 740 , an input circuit 750 , a pull-down circuit 760 , a reset circuit 770 , and a third control circuit 780 .

[0177] In the embodiment of the present disclosure, the first control circuit 710, the selection circuit 720, the input circuit 750 and the reset circuit 770 are respectively similar in structure to the first control circuit 510, the selection circuit 520, the input circuit 550 and the reset circuit 570 described above, and are not further described for the sake of simplicity.

[0178] In the embodiment of the present disclosure, the second control circuit 740 includes the fifteenth transistor T15, the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18 and the nineteenth transistor T19, similar to the second control circuit 540 described above, but the connection method of the fifteenth transistor T15 to the nineteenth transistor T19 is different from that of the second control circuit 540.

[0179] In the disclosed embodiment, the input circuit 730 further includes a 45th transistor T45, based on the previously described input circuit 530. The pull-down circuit 760 further includes a 46th transistor T46 and a 47th transistor T47, based on the previously described second pull-down circuit 560. The third control circuit 780 includes a 48th transistor T48 and a 49th transistor T49. The 45th through 49th transistors T45 through T49 are all N-type transistors.

[0180] The control electrode and the first electrode of the fifteenth transistor T15 are electrically connected to the first clock terminal CLK1 , and the second electrode of the fifteenth transistor T15 is electrically connected to the first electrode of the sixteenth transistor T16 .

[0181] A control electrode of the sixteenth transistor T16 is electrically connected to the first clock terminal CLK1 , and a second electrode of the sixteenth transistor T16 is electrically connected to a control electrode of the eighteenth transistor T18 .

[0182] The control electrode of the seventeenth transistor T17 is electrically connected to the second subnode Q2 , the first electrode of the seventeenth transistor T17 is electrically connected to the control electrode of the eighteenth transistor T18 , and the second electrode of the seventeenth transistor T17 is electrically connected to the second electrode of the fifteenth transistor T15 .

[0183] A first electrode of the eighteenth transistor T18 is electrically connected to the second electrode of the fifteenth transistor T15 , and a second electrode of the eighteenth transistor T18 is electrically connected to the first power source VGH.

[0184] A control electrode of the nineteenth transistor T19 is electrically connected to the first subnode Q1 , a first electrode of the nineteenth transistor T19 is electrically connected to the second electrode of the seventeenth transistor T17 , and a second electrode of the nineteenth transistor T19 is electrically connected to the second power supply LVGL.

[0185] The forty-fifth transistor T45 is connected in series with the fourteenth transistor T14 , a control electrode of the forty-fifth transistor T45 is electrically connected to the second clock terminal CLK2 , and a second electrode of the forty-fifth transistor T45 is electrically connected to the first power supply VGH.

[0186] The forty-sixth transistor T46 is connected in series with the twentieth transistor T20 and the twenty-first transistor T21 , and a control electrode of the forty-sixth transistor T46 is electrically connected to the first node P.

[0187] The forty-seventh transistor T47 is connected in series with the twenty-eighth transistor T28 . A control electrode of the forty-seventh transistor T47 is electrically connected to the first node P. A second electrode of the forty-seventh transistor T47 is electrically connected to the first power supply VGH.

[0188] The forty-eighth transistor T48 and the forty-ninth transistor T49 are connected in series, the control electrodes of the forty-eighth transistor T48 and the forty-ninth transistor T49 are electrically connected to the first power supply VGH, the second electrode of the forty-eighth transistor T48 is electrically connected to the first electrode of the fourteenth transistor T14, and the second electrode of the forty-ninth transistor T49 is electrically connected to the first power supply VGH.

[0189] The shift register 700 of the present disclosure utilizes a second control circuit 740 with a different structure from the shift registers 300 and 500. It employs an AC inverter and uses the eighteenth transistor T18 as a critical path for preventing leakage, thereby avoiding leakage caused by a negative Vth drift when the potential of the third node QB is high. The addition of the forty-eighth transistor T48 and the forty-ninth transistor T49 to the third control circuit 780 of the shift register 700 effectively prevents leakage current caused when the input circuit is closed.

[0190] When the shift register 700 is in the non-selected stage, the third node QB needs to be kept at a high level. When the first clock signal CLK1 is at a low level, if there is no eighteenth transistor T18, the Vgs of the sixteenth transistor T16, the seventeenth transistor T17, the nineteenth transistor T19 and the twentieth transistor T20 are all 0. If Vth drifts negatively, the above transistors will all have open channels, causing the potential of the third node QB to drop rapidly. When the eighteenth transistor T18 is added, it can ensure that the sixteenth transistor T16, the nineteenth transistor T19 and the twenty-first transistor T21 are completely turned off, eliminating the leakage channel and keeping the potential of the third node QB more stable.

[0191] FIG8A is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0192] As shown in Figure 8A, the driving circuit 800 includes M driving unit groups, each of which may include multiple shift registers as in the embodiments of the present disclosure. For example, the driving unit group 810 includes a shift register GOA1 and a shift register GOA2. It should be noted that Figure 8A only schematically illustrates a structure in which each driving unit group in the driving circuit 800 includes two shift registers. Each driving unit group includes two shift registers, and the driving circuit 800 includes a total of 2M shift registers. The 2M shift registers include shift register GOA1, shift register GOA2, shift register GOA3, ..., shift register GOA2M.

[0193] In an embodiment of the present disclosure, the plurality of gate terminals may include a plurality of first gate terminals D0-D7 of a first gate terminal group and a plurality of second gate terminals D0'-D7' of a second gate terminal group. The shift registers in the mth driving unit group are all electrically connected to the first gate terminal group, and the shift registers in the m+1th driving unit group are all electrically connected to the second gate terminal group. The gate signal output by the first gate terminal group is opposite to the gate signal output by the second gate terminal group, and 1≤m<M, where M is a positive integer greater than 1.

[0194] In the disclosed embodiment, the two shift registers in each driver unit group are electrically connected to different clock signals. For example, driver unit group 810 includes shift register GOA1 and shift register GOA2. Shift register GOA1 is electrically connected to a first clock terminal CLK1, a second clock terminal CLK2, and clock terminals CLKE1 and CLKE2. Shift register GOA2 is electrically connected to a third clock terminal CLK3, a fourth clock terminal CLK4, and clock terminals CLKE3 and CLKE4. Each shift register includes two output terminals.

[0195] In the embodiment of the present disclosure, the shift register may be any one of the shift register 100, the shift register 200, and the shift register 300 described above, which will not be described in detail here.

[0196] In the embodiment of the present disclosure, the 2M shift registers do not need to be cascaded, and the output signal is not controlled by other shift registers. Application to the driving circuit 800 can realize the output of a random frame displacement signal.

[0197] In an embodiment of the present disclosure, the number of first gate terminals included in the first gate terminal group is the same as the number of second gate terminals included in the second gate terminal group, and the number of first gate terminals is the same as the number of gate transistors included in the shift register. For example, the first gate terminal group includes eight gate terminals D0-D7, and the second gate terminal group includes eight gate terminals D0'-D7'.

[0198] Each gate terminal in the gate terminal group controls a gate transistor. The present disclosure does not limit the number of gate terminals and gate transistors, and the number of gate terminals and gate transistors can be set according to actual needs.

[0199] In an embodiment of the present disclosure, the multiple shift registers included in the mth driving unit group are connected in the same manner as the multiple first selection terminals included in the first selection terminal group, and the multiple shift registers included in the m+1th driving unit group are connected in the same manner as the multiple second selection terminals included in the second selection terminal group.

[0200] For example, a driving unit group may include two shift registers, and the shift registers in the group are connected to the strobe terminal in the same manner. For two adjacent driving unit groups, the shift registers in different driving unit groups are connected to the strobe terminal in different manners.

[0201] As shown in FIG8A , the shift registers of the first drive unit group 810 are all electrically connected to the first gate terminals D0-D7 of the first gate terminal group, and the shift registers of the second drive unit group are all electrically connected to the second gate terminals D0'-D7' of the second gate terminal group. The voltage levels of the first gate terminals D0-D7 and the second gate terminals D0'-D7' are opposite. When the gate signal output by the first gate terminal group is at a high level, the gate signal output by the second gate terminal group is at a low level. When the gate signal output by the first gate terminal group is at a low level, the gate signal output by the second gate terminal group is at a high level.

[0202] FIG8B is a signal timing diagram of a driving circuit according to an embodiment of the present disclosure.

[0203] As shown in FIG8B , FIG8B shows the timing waveforms of various signals in each stage of the driving circuit 800 during the forward scanning operation.

[0204] According to an embodiment of the present disclosure, Figure 8B shows signal changes of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the clock signal CLKE1, the clock signal CLKE2, the clock signal CLKE3 and the clock signal CLKE4, the first selection terminals D0-D7 of the first selection terminal group, the first node P, the first sub-node Q1, the second sub-node Q2, the third node QB, the fourth node Q, the first scan signal SCOUT(1) and the second scan signal SCOUT(2).

[0205] The timing changes of the first scan signal SCOUT(1), the second scan signal SCOUT(2), the first node P, the first sub-node Q1, the second sub-node Q2, the third node QB and the fourth node Q shown in Figure 8B are similar to the timing changes of the signals described above, and will not be repeated for the sake of simplicity.

[0206] In the embodiment of the present disclosure, the fourth clock terminal CLK4 connected to the shift register GOA2 described above has a similar function to the first clock terminal CLK1 connected to the shift register GOA1 described above, the third clock terminal CLK3 connected to the shift register GOA2 described above has a similar function to the second clock terminal CLK2 connected to the shift register GOA1 described above, and the clock terminal CLKE3 and clock terminal CLKE4 connected to the shift register GOA2 described above have similar functions to the clock terminal CLKE1 and clock terminal CLKE2 connected to the shift register GOA1 described above, which will not be repeated for the sake of simplicity.

[0207] FIG9A is a schematic structural diagram of a driving circuit according to another embodiment of the present disclosure.

[0208] As shown in Figure 9A, the driving circuit 900 includes M driving unit groups, each of which may include multiple shift registers as in the embodiments of the present disclosure. For example, the driving unit group 910 includes a shift register GOA1 and a shift register GOA2. It should be noted that Figure 9A only schematically illustrates a structure in which each driving unit group in the driving circuit 900 includes two shift registers. Each driving unit group includes two shift registers, and the driving circuit 900 includes 2M shift registers. The 2M shift registers include shift register GOA1, shift register GOA2, shift register GOA3, ..., shift register GOA2M.

[0209] In the embodiment of the present disclosure, the connection method between the shift register and the strobe terminal in each driving unit group is similar to the connection method in the driving circuit 800 described above, and is not repeated for the sake of simplicity.

[0210] In the embodiment of the present disclosure, the shift register in the first drive unit group 910 includes a shift register GOA1 and a shift register GOA2. Shift register GOA1 is electrically connected to a first clock terminal CLK1, a second clock terminal CLK2, and clock terminals CLKE1, CLKE2, CLKE3, and CLKE4. Shift register GOA2 is electrically connected to a third clock terminal CLK3, a fourth clock terminal CLK4, and clock terminals CLKE5, CLKE6, CLKE7, and CLKE8. Each shift register includes four output terminals.

[0211] In the embodiment of the present disclosure, the shift register may be any one of the shift register 500 and the shift register 700 described above, which will not be described in detail here.

[0212] FIG. 9B is a signal timing diagram of a driving circuit according to another embodiment of the present disclosure.

[0213] As shown in FIG. 9B , FIG. 9B shows the timing waveforms of various signals in each stage of the driving circuit 900 during the forward scanning operation.

[0214] According to an embodiment of the present disclosure, Figure 9B shows signal changes of the first clock signal CLK1, the second clock signal CLK2, the third clock signal CLK3, the fourth clock signal CLK4, the clock signals CLKE1-CLKE8, the first selection terminals D0-D7 of the first selection terminal group, the first node P, the first sub-node Q1, the second sub-node Q2, the third node QB, the fourth node Q, the first scan signal SCOUT(1), the second scan signal SCOUT(2), the third scan signal SCOUT(3), and the fourth scan signal SCOUT(4).

[0215] The first clock signal CLK1, the second clock signal CLK2, the clock signal CLKE1, the clock signal CLKE2, the clock signal CLKE3, the clock signal CLKE4, the first sub-node Q1, the second sub-node Q2, the third sub-node Q3, the fourth sub-node Q4, the first node P, the third node QB and the fourth node Q in Figure 9B are similar to the timing changes of the signals in Figure 6 described above, and are not repeated here for the sake of simplicity.

[0216] In the embodiment of the present disclosure, the relationships among the first clock signal CLK1 , the second clock signal CLK2 , the third clock signal CLK3 , and the fourth clock signal CLK4 are similar to those described in FIG. 8B , and are not further described for the sake of brevity.

[0217] The clock terminals CLKE1 and CLKE4 connected to the shift register GOA1 described above have similar functions to the clock terminals CLK5 and CLKE8 connected to the shift register GOA2 described above, and are not described again for simplicity.

[0218] Figure 9C is a timing diagram of the strobe signal according to an embodiment of the present disclosure. Figure 9C shows the timing of the strobe signals output by the plurality of first strobe terminals D0-D7 and the plurality of second strobe terminals D0'-D7' electrically connected to the driving circuits 800 and 900 described above.

[0219] In the embodiment of the present disclosure, when the first selection signal is at a first level, the corresponding second selection signal is at a second level. For example, when the first selection signal D0 is at a low level, the corresponding second selection signal D0' is at a high level. When the first selection signal D1 is at a low level, the corresponding second selection signal D1' is at a high level.

[0220] The pulse width of Dx is twice the pulse width of Dx-1, where x is an integer. The value range of x provided herein is 0-7. For example, the pulse width of the first selection signal D1 is twice the pulse width of the first selection signal D0. The pulse width of the second selection signal D1' is twice the pulse width of the second selection signal D0'.

[0221] In the disclosed embodiment, the number of gate transistors in the shift register can be set as needed, and the number of gate signals is set accordingly. The control electrode of the xth gate transistor among the multiple gate transistors in the shift register is selectively connected to one of the gate terminals Dx or Dx'. The shift registers within the same drive unit group are connected to the gate signal terminals in the same manner.

[0222] FIG10 is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0223] As shown in FIG. 10 , a display device 1000 includes a display panel 1010 and a driving circuit 1020 .

[0224] In the embodiment of the present disclosure, the display panel 1010 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit is used to drive the sub-pixel units Pixel.

[0225] In the embodiment of the present disclosure, the driving circuit 1020 may be the driving circuit 800 and the driving circuit 900 described above, which will not be described in detail here.

[0226] It should be noted that the number of sub-pixel units included in the display panel 1010 is only for illustrative purposes, and the present disclosure does not limit the number of sub-pixel units.

[0227] The driving circuit 1020 includes multiple shift registers that support gating, each of which is connected to a different row of sub-pixel units. When a row of sub-pixel units needs to be refreshed, the driving circuit can grate the corresponding shift register to achieve the refresh of the specified row of sub-pixel units.

[0228] FIG. 11 is a flowchart of a driving method according to an embodiment of the present disclosure.

[0229] As shown in FIG. 11 , the driving method may include operations S1110 - S1120 .

[0230] In the embodiment of the present disclosure, the driving method may be applied to the shift register 100 , the shift register 200 , the shift register 300 , the shift register 500 , and the shift register 700 described above.

[0231] In operation S1110 , in a gating phase, a plurality of gating signals are controlled to be at a first level.

[0232] In operation S1120, in a non-selection stage, at least one of the plurality of select signals is controlled to be at a second level.

[0233] In the embodiment of the present disclosure, operations S1110 - S1120 are similar to the operations performed by the shift register 300 , the shift register 500 , and the shift register 700 described above, and are not described again herein.

[0234] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0235] Those skilled in the art will appreciate that various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, even if such combinations or combinations are not explicitly described in this disclosure. In particular, various combinations and / or combinations of features described in the various embodiments and / or claims of this disclosure may be made, without departing from the spirit and teachings of this disclosure. All such combinations and / or combinations fall within the scope of this disclosure.

[0236] The embodiments of the present disclosure are described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be used in combination to advantage. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims

1. A shift register comprising: a first control circuit configured to control the potential of the first node under the control of a first clock signal from a first clock terminal; a gating circuit configured to control the potential of the first node under the control of a plurality of gating signals from a plurality of gating terminals; an input circuit configured to control the potential of the second node under the control of the potential of the first node and a second clock signal from a second clock terminal; a second control circuit configured to control the potential of the third node under the control of the potential of the second node; The output circuit is configured to output a scan signal under the control of the potentials of the second node and the third node.

2. The shift register according to claim 1, wherein: The gating circuit controls the potential of the first node under the control of a plurality of gating signals from a plurality of gating terminals, and the gating circuit is configured to: Under the control of the first levels of the plurality of selection signals, controlling the potential of the first node to be maintained at a second level; as well as Under the control of the second level of any one of the plurality of selection signals, the potential of the first node is pulled down.

3. The shift register according to claim 2, wherein: The gating circuit is configured to: Under the control of the first level of the third node, controlling the potential of the first node to be maintained at a second level; as well as Under the control of the second level of the third node, the potential of the first node is pulled down.

4. The shift register according to claim 1, wherein: The first control circuit controls the potential of the first node under the control of a first clock signal from a first clock terminal, and the first control circuit is configured to: Under the control of the second level of the first clock signal, the first node is charged by the first voltage of the first power supply to control the potential of the first node to be a second level; as well as When the first clock signal is at a first level, the potential of the first node is maintained at a second level.

5. The shift register according to claim 1 , further comprising: The pull-down circuit is configured as: pulling down the potential of the third node under the control of the potential of the first node and the second clock signal; as well as Under the control of the second level of the third node, the potential of the second node is pulled down.

6. The shift register according to claim 1 , further comprising: a reset circuit configured to reset the fourth node by a second voltage of a second power supply under the control of the first clock signal; as well as The potential of the second node is reset under the control of the potential of the first node and the potential of the fourth node.

7. The shift register according to claim 1 , further comprising: A third control circuit is electrically connected to the input circuit, and is configured to control a voltage provided to the input circuit under the control of a first voltage of a first power supply.

8. The shift register according to claim 1, wherein: The output circuit includes a plurality of output terminals, and the plurality of output terminals are configured to output a plurality of scanning signals, and the plurality of scanning signals are used to drive a plurality of rows of sub-pixel units.

9. The shift register according to claim 1, wherein: The gating circuit includes a tenth transistor, a twelfth transistor, and a plurality of gating transistors; wherein the control electrode of the tenth transistor and the control electrode of the twelfth transistor are electrically connected to the third node, the first electrode of the tenth transistor and the first electrode of the twelfth transistor are electrically connected to the first node, and the second electrode of the tenth transistor and the second electrode of the twelfth transistor are electrically connected to the first electrodes of the plurality of gating transistors; The control electrodes of the plurality of gating transistors are electrically connected to the plurality of gating terminals respectively, and the second electrodes of the plurality of gating transistors are electrically connected to the first clock terminal.

10. The shift register according to claim 1, wherein: The first control circuit includes a first transistor, an eleventh transistor, a thirteenth transistor, a first capacitor and a second capacitor; The control electrode of the first transistor is electrically connected to the first clock terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the eleventh transistor; A first electrode of the eleventh transistor is electrically connected to the first power source, and a second electrode of the eleventh transistor is electrically connected to the first node; The control electrode of the thirteenth transistor is electrically connected to the first node, the first electrode of the thirteenth transistor is electrically connected to the first power supply, and the second electrode of the thirteenth transistor is electrically connected to the gating circuit; A first terminal of the first capacitor is electrically connected to the control electrode of the eleventh transistor, and a second terminal of the first capacitor is electrically connected to the first node; and A first terminal of the second capacitor is electrically connected to the first power source, and a second terminal of the second capacitor is electrically connected to the first node.

11. The shift register according to claim 1, wherein: The second node includes a first subnode and a second subnode, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The control electrode and the first electrode of the fifteenth transistor are electrically connected to a third power supply, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; The control electrode of the sixteenth transistor is electrically connected to a third power supply, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; The control electrode of the seventeenth transistor is electrically connected to the first subnode, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to a fourth power supply; A first electrode of the eighteenth transistor is electrically connected to the third power supply, and a second electrode of the eighteenth transistor is electrically connected to the third node; A control electrode of the nineteenth transistor is electrically connected to the second subnode, a first electrode of the nineteenth transistor is electrically connected to the third node, and a second electrode of the nineteenth transistor is electrically connected to a second power supply.

12. The shift register according to claim 1, wherein: The second node includes a first subnode and a second subnode, and the second control circuit includes a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, and a nineteenth transistor; The control electrode and the first electrode of the fifteenth transistor are electrically connected to the first clock terminal, and the second electrode of the fifteenth transistor is electrically connected to the first electrode of the sixteenth transistor; The control electrode of the sixteenth transistor is electrically connected to the first clock terminal, and the second electrode of the sixteenth transistor is electrically connected to the control electrode of the eighteenth transistor; The control electrode of the seventeenth transistor is electrically connected to the second subnode, the first electrode of the seventeenth transistor is electrically connected to the control electrode of the eighteenth transistor, and the second electrode of the seventeenth transistor is electrically connected to the second electrode of the fifteenth transistor; A first electrode of the eighteenth transistor is electrically connected to a second electrode of the fifteenth transistor, and a second electrode of the eighteenth transistor is electrically connected to a first power source; and The control electrode of the nineteenth transistor is electrically connected to the first subnode, the first electrode of the nineteenth transistor is electrically connected to the second electrode of the seventeenth transistor, and the second electrode of the nineteenth transistor is electrically connected to a second power supply.

13. The shift register according to claim 1, wherein: The second node includes a first sub-node and a second sub-node, and the input circuit includes a fourteenth transistor, a twenty-second transistor, and a twenty-fifth transistor; wherein the control electrode of the fourteenth transistor is electrically connected to the second clock terminal, the first electrode of the fourteenth transistor is electrically connected to the first power supply, and the second electrode of the fourteenth transistor is electrically connected to the fourth node; a control electrode of the twenty-second transistor electrically connected to the first node, a first electrode of the twenty-second transistor electrically connected to the fourth node, and a second electrode of the twenty-second transistor electrically connected to the first sub-node; and A control electrode of the twenty-fifth transistor is electrically connected to the first node, a first electrode of the twenty-fifth transistor is electrically connected to the fourth node, and a second electrode of the twenty-fifth transistor is electrically connected to the second sub-node.

14. The shift register according to claim 5, wherein: The second node includes a first subnode and a second subnode, and the pull-down circuit includes a twentieth transistor, a twenty-first transistor, a twenty-third transistor, a twenty-fourth transistor, a twenty-sixth transistor, a twenty-seventh transistor, and a twenty-eighth transistor; wherein the control electrode of the 20th transistor is electrically connected to the first node, the first electrode of the 20th transistor is electrically connected to the third node, and the second electrode of the 20th transistor is electrically connected to the first electrode of the 21st transistor; A control electrode of the twenty-first transistor is electrically connected to the first clock terminal, and a second electrode of the twenty-first transistor is electrically connected to a second power supply; a control electrode of the twenty-third transistor, a control electrode of the twenty-fourth transistor, a control electrode of the twenty-sixth transistor, and a control electrode of the twenty-seventh transistor are electrically connected to the third node; The twenty-third transistor and the twenty-fourth transistor are connected in series, a first electrode of the twenty-third transistor is electrically connected to the first subnode, and a second electrode of the twenty-fourth transistor is electrically connected to a second power supply; The twenty-sixth transistor and the twenty-seventh transistor are connected in series, a first electrode of the twenty-sixth transistor is electrically connected to the second subnode, and a second electrode of the twenty-seventh transistor is electrically connected to a second power supply; and The control electrode of the twenty-eighth transistor is electrically connected to the first sub-node. The first electrode of the twenty-eighth transistor is electrically connected to the second electrode of the twenty-third transistor and the second electrode of the twenty-sixth transistor. The second electrode of the twenty-eighth transistor is electrically connected to a first power supply.

15. The shift register according to claim 6, wherein: The reset circuit includes a twenty-ninth transistor and a thirtieth transistor; wherein, the twenty-ninth transistor and the thirtieth transistor are connected in series. The control electrodes of the twenty-ninth transistor and the thirtieth transistor are electrically connected to the first clock terminal. The first electrode of the twenty-ninth transistor is electrically connected to the fourth node. The second electrode of the thirtieth transistor is electrically connected to a second power supply.

16. A driving circuit includes M driving unit groups, and each driving unit group includes a plurality of shift registers as described in any one of claims 1-15; in, The m-th driving unit group is electrically connected to a first gating terminal group, and the (m + 1)-th driving unit group is electrically connected to a second gating terminal group. The gating signals output by the first gating terminal group are opposite to the gating signals output by the second gating terminal group, where 1 ≤ m < M, and M is a positive integer greater than 1.

17. The driving circuit according to claim 16, wherein: The number of first gating terminals included in the first gating terminal group is the same as the number of second gating terminals included in the second gating terminal group, and the number of first gating terminals is the same as the number of gating transistors included in the shift register.

18. The driving circuit according to claim 16, wherein: The connection manners of the plurality of shift registers included in the m-th driving unit group and the plurality of first gating terminals included in the first gating terminal group are the same. The connection manners of the plurality of shift registers included in the (m + 1)-th driving unit group and the plurality of second gating terminals included in the second gating terminal group are the same.

19. A display device includes: a display panel; and a driving circuit as described in any one of claims 16-18; wherein, the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

20. A driving method is applied to the shift register as described in any one of claims 1-15, and includes: In the gating stage, controlling the plurality of gating signals to be all at a first level; In the non-gating stage, controlling at least one of the plurality of gating signals to be at a second level.

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