Display panel and manufacturing method therefor, and display device

Abstract

A display panel and a manufacturing method therefor, and a display device. The display panel comprises a substrate, a pixel definition layer, a light-emitting functional layer and a partition structure. The pixel definition layer is located on one side of the substrate. The pixel definition layer is provided with a plurality of pixel openings, and the plurality of pixel openings include a first pixel opening and a second pixel opening arranged adjacent to each other. The light-emitting functional layer is located on the side of the pixel definition layer away from the substrate. The light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked in a direction moving away from the substrate. The partition structure is located between the first pixel opening and the second pixel opening. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure. The surface of the partition structure away from the substrate is closer to the substrate than the surface of the pixel definition layer away from the substrate, or the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate. The display panel is used for displaying an image.

Description

Display panel, display panel manufacturing method and display device

[0001] The present application claims priority to the Chinese patent application No. 202410370695.6, filed on March 28, 2024, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates to the technical field of display, and in particular, to a display panel, a display panel manufacturing method and a display device. BACKGROUND

[0003] With the continuous development of display technology, display devices have gradually spread in people's lives. Among them, the organic light-emitting diode (OLED) display panel has been widely used in mobile phones, televisions, notebook computers and other display devices due to its self-luminous, low power consumption, wide viewing angle, fast response speed, high contrast and other advantages. SUMMARY

[0004] In one aspect, a display panel is provided, comprising a substrate, a pixel definition layer, a light-emitting functional layer and a partition structure.

[0005] The pixel definition layer is located on one side of the substrate. The pixel definition layer is provided with a plurality of pixel openings, and the plurality of pixel openings comprise a first pixel opening and a second pixel opening arranged adjacent to each other.

[0006] The light-emitting functional layer is located on the side of the pixel definition layer away from the substrate. The light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked in the direction away from the substrate.

[0007] The partition structure is located between the first pixel opening and the second pixel opening. In the light-emitting functional layer, at least the charge generation layer is disconnected at the partition structure.

[0008] The surface of the partition structure away from the substrate is closer to the substrate than the surface of the pixel definition layer away from the substrate; or the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate.

[0009] In some embodiments, the display panel further comprises a first dielectric layer, and the first dielectric layer is located between the partition structure and the substrate.

[0010] The surface of the first dielectric layer away from the substrate is provided with an opening, and at least part of the partition structure is located in the opening.

[0011] In some embodiments, the first dielectric layer is farther away from the surface of the substrate than the partition structure is farther away from the surface of the substrate.

[0012] In some embodiments, the partition structure is provided with an undercut structure near one side of the first pixel opening; and / or, the partition structure is provided with an undercut structure near one side of the second pixel opening.

[0013] The undercut structure is located in the opening, and there is a spacing between the undercut structure and the sidewall of the opening.

[0014] In the light-emitting functional layer, at least the charge generation layer is disconnected at the undercut structure.

[0015] In some embodiments, the partition structure is provided with an undercut structure near one side of one of the first pixel opening and the second pixel opening.

[0016] The partition structure is at least partially attached to the sidewall of the opening near one side of the other of the first pixel opening and the second pixel opening.

[0017] In some embodiments, the partition structure partially overlaps the surface of the first dielectric layer away from the surface of the substrate near one side of the other of the first pixel opening and the second pixel opening.

[0018] In some embodiments, the portion of the partition structure overlapping the surface of the first dielectric layer away from the surface of the substrate includes a first side surface near the other of the first pixel opening and the second pixel opening. The first side surface and the surface of the first dielectric layer away from the surface of the substrate have a first included angle, the first included angle is toward the opening, and the first included angle is an acute angle.

[0019] In some embodiments, the partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

[0020] In some embodiments, the display panel further comprises a common electrode layer located on a side of the second light-emitting layer away from the substrate. The common electrode layer is continuous at the partition structure.

[0021] In some embodiments, the partition structure is provided around the first pixel opening or the second pixel opening, and the partition structure has at least one gap.

[0022] In some embodiments, the display panel further comprises a common electrode layer located on a side of the second light-emitting layer away from the substrate. The common electrode layer is disconnected at the partition structure and continuous at the at least one gap.

[0023] In some embodiments, the partition structure comprises a plurality of block-shaped partition portions, and the plurality of partition portions are arranged at intervals around the first pixel opening or the second pixel opening.

[0024] In some embodiments, the partition structure comprises a negative photosensitive material.

[0025] In some embodiments, a slope of a side wall of the opening close to the undercut structure is greater than a slope of a side wall of the opening away from the undercut structure.

[0026] In some embodiments, a depth of the opening is less than a thickness of the first dielectric layer.

[0027] In another aspect, a method for manufacturing a display panel is provided, comprising the following steps:

[0028] forming a partition structure on a substrate.

[0029] forming a pixel definition layer on the substrate on which the partition structure is formed. The pixel definition layer is provided with a plurality of pixel openings, including a first pixel opening and a second pixel opening arranged adjacently, and the partition structure is located between the first pixel opening and the second pixel opening. A surface of the partition structure away from the substrate is closer to the substrate than a surface of the pixel definition layer away from the substrate; or the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate.

[0030] forming a light-emitting functional layer on a side of the pixel definition layer away from the substrate. The light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer arranged in sequence in a direction away from the substrate; and at least the charge generation layer in the light-emitting functional layer is disconnected at the partition structure.

[0031] In some embodiments, before forming the partition structure on the substrate, the method further comprises the following steps:

[0032] forming a first dielectric layer on a substrate.

[0033] forming an opening on a surface of the first dielectric layer away from the substrate.

[0034] wherein at least part of the partition structure is located in the opening.

[0035] In some embodiments, forming the partition structure on the substrate comprises the following steps:

[0036] forming a partition layer on a side of the first dielectric layer away from the substrate.

[0037] Exposure is performed on a target region of the partition layer to form a partition structure.

[0038] Part of the target region overlaps with the opening and has a spacing between the side wall of the opening; another part of the target region is located outside the opening and close to another of the first pixel opening and the second pixel opening.

[0039] In some embodiments, the material of the partition layer comprises a negative photosensitive material.

[0040] In another aspect, a display device is provided, comprising the display panel and the cover plate as described in any of the above embodiments. The cover plate is arranged on the light-out side of the display panel. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the drawings needed to be used in some embodiments of the present disclosure. Obviously, the drawings described in the following description are only some drawings of the embodiments of the present disclosure, and other drawings can also be obtained by those skilled in the art according to these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limited to the actual size, actual process, actual timing of signals, etc. of the products involved in the embodiments of the present disclosure.

[0042] FIG. 1 is a structural diagram of a display device according to some embodiments;

[0043] FIG. 2 is a sectional view of the display device in FIG. 1 along the section line B-B;

[0044] FIG. 3 is a structural diagram of a display panel according to some embodiments;

[0045] FIG. 4 is a partial planar structural diagram of a display panel according to some embodiments;

[0046] FIG. 5A is a film layer structural diagram of a pixel layer of a display panel according to some embodiments;

[0047] FIG. 5B is another film layer structural diagram of a pixel layer of a display panel according to some embodiments;

[0048] FIG. 6 is yet another film layer structural diagram of a pixel layer of a display panel according to some embodiments;

[0049] FIG. 7 is another structural diagram of a display panel according to some embodiments;

[0050] FIG. 8 is yet another structural diagram of a display panel according to some embodiments;

[0051] FIG. 9 is a structural diagram of a partition structure of a display panel according to some embodiments;

[0052] FIG. 10 is another structural diagram of the partition structure of the display panel according to some embodiments;

[0053] FIG. 11 is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0054] FIG. 12A is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0055] FIG. 12B is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0056] FIG. 12C is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0057] FIG. 13A is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0058] FIG. 13B is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0059] FIG. 13C is yet another structural diagram of the partition structure of the display panel according to some embodiments;

[0060] FIG. 14A is another partial plan view of the display panel according to some embodiments;

[0061] FIG. 14B is yet another partial plan view of the display panel according to some embodiments;

[0062] FIG. 15 is yet another partial plan view of the display panel according to some embodiments;

[0063] FIG. 16 is yet another partial plan view of the display panel according to some embodiments;

[0064] FIG. 17 is a sectional view of the display panel according to some embodiments;

[0065] FIG. 18 is a flowchart of a method for manufacturing the display panel according to some embodiments;

[0066] FIG. 19 is a structural diagram corresponding to step S1 in the method for manufacturing the display panel according to the embodiment shown in FIG. 18;

[0067] FIG. 20 is a structural diagram corresponding to step S2 in the method for manufacturing the display panel according to the embodiment shown in FIG. 18;

[0068] FIG. 21 is a structural diagram corresponding to step S3 in the method for manufacturing the display panel according to the embodiment shown in FIG. 18;

[0069] FIG. 22 is a structural diagram corresponding to step S0 in the preparation method of the display panel in the embodiment shown in FIG. 18;

[0070] FIG. 23 is another structural diagram corresponding to step S1 in the preparation method of the display panel in the embodiment shown in FIG. 18. DETAILED DESCRIPTION

[0071] The technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided in the present disclosure, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0072] Unless otherwise required by context, the term “comprise” and other forms of the term “comprise”, such as “comprises” and “comprising”, are to be construed as open, inclusive, meaning that “comprising” means “including, but not limited to”. In the description of the specification, the terms “one embodiment”, “some embodiments”, “exemplary embodiments”, “example”, “specific example” or “some examples” are intended to mean that the specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The illustrative representation of the above terms does not necessarily mean the same embodiment or example. In addition, the specific features, structures, materials or characteristics described can be included in any one or more embodiments or examples in any appropriate manner.

[0073] Hereinafter, the terms “first” and “second” are used only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined with “first” and “second” can explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise stated, the meaning of “a plurality of” is two or more.

[0074] In describing some embodiments, "coupled" and "connected," along with their derivatives, can be used. It should be understood that these terms are not intended as synonyms for each other. Rather, "connected" can be used to indicate that two or more elements are in direct physical or electrical contact with each other. "Coupled" can be used to indicate that two or more elements are in either physical or electrical contact with each other, even at a remote location from each other. The term "coupled" as used herein encompasses the case where one or more intervening elements can exist. The embodiments disclosed herein are not necessarily limited to the details of the embodiments described.

[0075] "A, B, and C at least one of" has the same meaning as "at least one of A, B, or C." Both of these phrases include the following combinations: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0076] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0077] As used herein, the term "if' can, depending on the context, optionally be interpreted as meaning "when," or "while," or "in response to determining," or "in response to detecting." Likewise, the phrase "if it is determined" or "if [a stated condition or event] is detected" can, depending on the context, optionally be interpreted as meaning "upon determining," or "in response to determining," or "upon detecting," or "in response to detecting [the stated condition or event]."

[0078] The use of "adapted to" or "configured to," as used herein, means open and inclusive language that does not exclude additional devices or steps not explicitly described.

[0079] Additionally, the use of "based on" means open and inclusive language that does not exclude additional conditions or values not explicitly stated.

[0080] As used herein, "about," "approximately," or "around" includes the recited value and the average value within an acceptable range of deviation from the particular value, as determined by one of ordinary skill in the art considering the measurement being discussed and the error in measurement associated with the particular quantity being measured (i.e., the limitations of the measurement system).

[0081] As used herein, "parallel," "perpendicular," "equal" include the recited condition and conditions that are approximately the recited condition, the range of approximation being within an acceptable deviation range as determined by one of ordinary skill in the art taking into account the measurement being discussed and the error associated with the measurement of the particular quantity (i.e., limitations of the measurement system). For example, "parallel" includes absolute parallel and near parallel, where the acceptable deviation range for near parallel can be, for example, within 5°; "perpendicular" includes absolute perpendicular and near perpendicular, where the acceptable deviation range for near perpendicular can also be, for example, within 5°. "Equal" includes absolute equality and near equality, where the acceptable deviation range for near equality can be, for example, a difference between the two that is less than or equal to 5% of either.

[0082] It should be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers can also be present.

[0083] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are idealized examples. In the interest of clarity, not all of the circular features can be shown in the drawings. It will be appreciated that in the development of any such actual implementation, numerous implementation-specific decisions can be made. These implementation-specific decisions can include, for example, manufacturing or processing tolerances, variations from the teaching, and / or the skill(s) of artisans within the relevant trade. As such, some aspects of the exemplary embodiments can be practiced without the these specific details. In other instances, well-known methods, procedures and components have not been described in detail so as not to unnecessarily obscure aspects of the exemplary embodiments. The exemplary embodiments are not limited to the illustrated ordering of acts or events unless specifically recited therein.

[0084] For convenience of the following description, an XYZ coordinate system is established. A third direction Z is a thickness direction of the display device, an XY plane is perpendicular to the Z direction, a first direction X and a second direction Y cross each other. For example, the first direction X and the second direction Y are perpendicular to each other.

[0085] It should be noted that, for example, 91 / 9 appearing in the drawings of the present disclosure indicates that the part is both 9 and 91, and other similar designations appearing in the drawings also follow the above description.

[0086] As shown in FIG. 1, some embodiments of the present disclosure provide a display device 100.

[0087] Exemplarily, the display device 100 can be any device that displays images whether in motion (e.g., video) or stationary (e.g., a still image), whether textual or pictorial. More particularly, it is contemplated that the embodiments can be implemented in or in association with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, personal data assistants (PDAs), hand-held or portable computers, GPS receivers / navigators, cameras, MP4 players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), cockpit controls and / or displays, camera view displays (e.g., display of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projections, architectural structures, packaging, and aesthetic structures (e.g., display of images on a piece of jewelry), and the like. By way of further example, the display device 100 is schematically depicted in FIG. 1 as a mobile phone.

[0088] Exemplarily, the display device 100 can be an electroluminescent display device or a photoluminescent display device. In the case that the display device 100 is an electroluminescent display device, the electroluminescent display device can be an organic electroluminescent display device (OLED) or a quantum dot electroluminescent display device (QLED). In the case that the display device 100 is a photoluminescent display device, the photoluminescent display device can be a quantum dot photoluminescent display device.

[0089] Hereinafter, some embodiments of the present disclosure are illustratively described with the display device 100 being an organic electroluminescent display device (OLED), but the embodiments of the present disclosure include but are not limited to this, and any other display device can also be considered as long as the same technical idea is applied.

[0090] In some embodiments, as shown in FIG. 2, which is a cross-sectional view of the display device 100 along the cross-sectional line B-B in FIG. 1, the display device 100 includes a display panel 10 and a cover plate 20. The cover plate 20 is disposed at the light exit side of the display panel 10.

[0091] The cover plate 20 can separate the display panel 10 from the external environment and provide protection for the display panel 10.

[0092] Exemplarily, the cover plate 20 can be a single-layer cover plate or a multi-layer cover plate 20 that are laminated together by adhesive material.

[0093] Exemplarily, the cover plate 20 can be a silicate glass cover plate, which can be a curved glass or an ultra-thin glass, for example.

[0094] The cover plate 20 can also be a flexible polymer film cover plate, which can be a transparent polyimide, PET, polyurethane, or the like.

[0095] The cover plate 20 can also be a combination of the above flexible polymer films, or a combination of the flexible polymer film and the silicate glass.

[0096] In some embodiments, the display device 100 can further include a circuit board (not shown in the figure). The circuit board is electrically connected to the display panel 10 and is configured to drive the display panel 10 to display images.

[0097] Exemplarily, the circuit board includes but is not limited to a PCB (Printed Circuit Board) and an FPC (Flexible Printed Circuit Board).

[0098] In some embodiments, the display device 100 can further include an under-screen camera, an under-screen fingerprint identification sensor, or the like, so that the display device 100 can implement multiple different functions such as photographing, video recording, fingerprint identification, and face recognition. The present disclosure does not make any limitation in this regard, and adaptive design can be made according to actual needs.

[0099] The display panel 10 is described in detail below.

[0100] In some embodiments, as shown in FIG. 3, which is a structural diagram of the display panel 10 according to some embodiments, the display panel 10 can have a rectangular structure.

[0101] It should be noted that the above-mentioned “rectangular structure” means that the shape of the boundary of the display panel 10 is generally rectangular, but is not limited to a standard rectangle. That is, the “rectangle” here not only includes the shape of a standard rectangle, but also includes shapes similar to a rectangle in consideration of process conditions. For example, as shown in FIG. 3, the long side and the short side of the rectangle are curved at each intersection (i.e., at the corners G), that is, the corners G are smooth, so that the shape of the boundary of the display panel 10 in the plan view is a rounded rectangle.

[0102] In other embodiments, the display panel 10 can have a circular structure, or other shapes with corners.

[0103] Some embodiments of the present disclosure are described below by way of example with the display panel 10 having a rectangular structure, but the embodiments of the present disclosure include but are not limited to this, and the shape of the display panel 10 can also consider any other shape.

[0104] In some embodiments, please refer to FIG. 3, the display panel 10 has a display area AA for displaying images, and a peripheral area AN located at least one side of the display area AA.

[0105] For example, the peripheral area AN is located at one side of the display area AA.

[0106] For another example, the peripheral area AN is located at opposite sides of the display area AA.

[0107] For yet another example, as shown in FIG. 3, the peripheral area AN surrounds the display area AA.

[0108] It should be noted that the specific arrangement of the peripheral area AN is related to the specific design of the display panel 10, and can be designed according to actual needs, which is only illustrative and not limiting.

[0109] In some embodiments, please refer to FIG. 3, the display panel 10 has a display area AA for displaying images, and a peripheral area AN located at least one side of the display area AA.

[0110] For example, the plurality of sub-pixels 9 in the display area AA of the display panel 10 can emit light of the same color, and the display panel 10 can further include a color film layer arranged on the light-emitting side of the plurality of sub-pixels 9. For example, the plurality of sub-pixels 9 emit white light, red light, green light or blue light, and in this case, the color light emitted by the sub-pixels 9 remains the same color after passing through the color film layer, or is converted into other color light, so that the display panel 10 can realize multi-color light emission when the plurality of sub-pixels 9 emit light of the same color.

[0111] Alternatively, the plurality of sub-pixels 9 in the display area AA of the display panel 10 emit light of different colors, for example, the plurality of sub-pixels 9 include red sub-pixels emitting red light, green sub-pixels emitting green light, and blue sub-pixels emitting blue light, so as to realize multi-color light emission of the display panel 10.

[0112] In some embodiments, please refer to FIG. 2, the display panel 10 includes a substrate 1, a driving layer 2, a pixel layer D and an encapsulation layer 8 arranged in sequence.

[0113] The pixel layer D is used to arrange the plurality of sub-pixels 9 in the display area AA of the display panel 10, and the plurality of sub-pixels 9 include first sub-pixels 91 and second sub-pixels 92 arranged adjacently.

[0114] It should be noted that the first sub-pixels 91 and the second sub-pixels 92 arranged adjacently means that there is no other sub-pixel 9 arranged between the first sub-pixel 91 and the second sub-pixel 92.

[0115] The driving layer 2 is used to drive the plurality of sub-pixels 9 in the pixel layer D to emit light.

[0116] The encapsulation layer 8 is used to encapsulate the pixel layer D, and plays a role of protecting the pixel layer D from corrosion caused by water and oxygen from the outside.

[0117] Exemplarily, the first sub-pixel 91 can be a red light sub-pixel for emitting red light, a green light sub-pixel for emitting green light, or a blue light sub-pixel for emitting blue light. The second sub-pixel 92 can also be a red light sub-pixel for emitting red light, a green light sub-pixel for emitting green light, or a blue light sub-pixel for emitting blue light.

[0118] It can be understood that the colors of the light emitted by the first sub-pixel 91 and the second sub-pixel 92 can be the same, for example, the first sub-pixel 91 and the second sub-pixel 92 can both be red light sub-pixels for emitting red light.

[0119] For another example, the first sub-pixel 91 and the second sub-pixel 92 can also both be green light sub-pixels for emitting green light.

[0120] For still another example, the first sub-pixel 91 and the second sub-pixel 92 can also both be blue light sub-pixels for emitting blue light.

[0121] The colors of the light emitted by the first sub-pixel 91 and the second sub-pixel 92 can also be different, for example, the first sub-pixel 91 can be a red light sub-pixel for emitting red light, and the second sub-pixel 92 can be a green light sub-pixel for emitting green light or a blue light sub-pixel for emitting blue light.

[0122] For another example, the first sub-pixel 91 can also be a green light sub-pixel for emitting green light, and the second sub-pixel 92 can be a red light sub-pixel for emitting red light or a blue light sub-pixel for emitting blue light.

[0123] For still another example, the first sub-pixel 91 can also be a blue light sub-pixel for emitting blue light, and the second sub-pixel 92 can be a red light sub-pixel for emitting red light or a green light sub-pixel for emitting green light.

[0124] Exemplarily, the material used to form the substrate 1 can include an inorganic material, for example, a glass material such as soda lime glass, quartz glass, sapphire glass, etc.

[0125] The material used to form the substrate 1 can also include an organic material, for example, one or more of polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyether sulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, and polyethylene naphthalate.

[0126] The material used to form the substrate 1 can also include both an organic material and an inorganic material.

[0127] Exemplarily, a plurality of pixel driving circuits can be arranged in the driving layer 2. The pixel driving circuit and the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are electrically connected, and the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) can emit light under the driving of the pixel driving circuit.

[0128] The pixel driving circuit can include a thin film transistor (TFT) and a storage capacitor.

[0129] Exemplarily, the encapsulation layer 8 can include an inorganic encapsulation layer and an organic encapsulation layer.

[0130] The pixel layer D is described in detail below.

[0131] In some embodiments, referring to FIG. 2, the pixel layer D of the display panel 10 includes a pixel electrode layer 4, a light-emitting functional layer 6, and a common electrode layer 7 arranged in sequence along the third direction Z. The pixel electrode layer 4 and the common electrode layer 7 can provide carriers such as electrons and holes to the light-emitting functional layer 6, so that the light-emitting functional layer 6 emits light.

[0132] The pixel electrode layer 4 is provided with a plurality of pixel electrodes 41, and the light-emitting functional layer 6 includes a plurality of light-emitting portions 6a, each of which overlaps with one pixel electrode 41 in the third direction Z.

[0133] The common electrode layer 7 can serve as a common electrode of a plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) in the pixel layer D. Each sub-pixel 9 (e.g., the first sub-pixel 91 or the second sub-pixel 92) in the pixel layer D can include a pixel electrode 41 and a common electrode arranged in sequence, and a light-emitting portion 6a located between the pixel electrode 41 and the common electrode.

[0134] Exemplarily, referring to FIG. 2, the pixel electrode layer 4 can be closer to the driving layer 2 than the common electrode layer 7.

[0135] Exemplarily, one of the pixel electrode 41 and the common electrode can serve as an anode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the other can serve as a cathode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92).

[0136] For example, the pixel electrode 41 can serve as an anode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92), and the common electrode can serve as a cathode of the sub-pixel 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92).

[0137] Exemplarily, the material for forming the pixel electrode 41 can include a metal material, such as any one or more of magnesium (Mg), silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo).

[0138] The material for forming the pixel electrode 41 can also include an alloy material of the above-mentioned metal material, such as an aluminum-neodymium alloy (AlNd) or a molybdenum-niobium alloy (MoNb).

[0139] Exemplarily, the pixel electrode 41 can be a single-layer structure.

[0140] Alternatively, the pixel electrode 41 can also be a multi-layer composite structure. For example, the pixel electrode 41 can be a Ti / Al / Ti structure or the like. For another example, the pixel electrode 41 can be a stack structure formed by a metal material and a transparent conductive material, such as ITO / Ag / ITO, Mo / AlNd / ITO or the like.

[0141] Exemplarily, the material for forming the common electrode layer 7 can include any one or several of magnesium (Mg), silver (Ag), aluminum (Al) or the like.

[0142] The material for forming the common electrode layer 7 can also include an alloy of any one or several of magnesium (Mg), silver (Ag), aluminum (Al) or the like.

[0143] The material for forming the common electrode layer 7 can also include a transparent conductive material, such as indium tin oxide (ITO).

[0144] In some embodiments, as shown in FIG. 4, and in combination with FIG. 2, FIG. 4 is a partial planar structure diagram of the display panel 10 according to some embodiments. The display panel 10 further includes a pixel definition layer (PDL) 5, which is located between the pixel electrode layer 4 and the light-emitting functional layer 6. A plurality of pixel openings K are formed in the pixel definition layer (PDL) 5, and the pixel openings K and the pixel electrodes 41 are correspondingly arranged, each pixel opening K exposes at least a partial area of one pixel electrode 41. The light-emitting portions 6a in the light-emitting functional layer 6 are arranged in the pixel openings K, and are respectively electrically connected with the pixel electrodes 41 and the common electrode layer 7.

[0145] By exposing at least a partial area of one pixel electrode 41 by each pixel opening K, the pixel definition layer (PDL) 5 can effectively define the actual effective area of the pixel electrode 41 (i.e. the area where the pixel electrode 41 is directly electrically connected with the light-emitting portion 6a in the light-emitting functional layer 6), and further define the light-emitting area and the light-emitting area of the sub-pixel 9.

[0146] Exemplarily, referring to FIG. 4, the pixel definition layer (PDL) 5 can cover the edges of the pixel electrode 41, and the pixel openings K expose partial internal areas of the pixel electrode 41.

[0147] Exemplarily, the material for forming the pixel definition layer (PDL) 5 can include an organic material, such as polyimide, acrylic or polyethylene terephthalate or the like.

[0148] For example, please continue to refer to FIG. 4, the plurality of pixel openings K in the pixel definition layer 5 includes a first pixel opening K1 and a second pixel opening K2 arranged adjacently. The first pixel opening K1 and the pixel electrode 41 in the first sub-pixel 91 are arranged correspondingly, and at least a partial region of the pixel electrode 41 in the first sub-pixel 91 is exposed. The second pixel opening K2 and the pixel electrode 41 in the second sub-pixel 92 are arranged correspondingly, and at least a partial region of the pixel electrode 41 in the second sub-pixel 92 is exposed.

[0149] It should be noted that the first pixel opening K1 and the second pixel opening K2 arranged adjacently means that no other pixel opening K is arranged between the first pixel opening K1 and the second pixel opening K2.

[0150] In some embodiments, as shown in FIG. 5A and FIG. 5B, both of FIG. 5A and FIG. 5B are a film layer structure diagram of the pixel layer D of the display panel 10 according to some embodiments. The light-emitting functional layer 6 in the pixel layer D includes a light-emitting layer 61.

[0151] For example, please continue to refer to FIG. 5A, the display panel 10 can be a QLED display panel. Based on that the display panel 10 is a QLED display panel, the light-emitting layer 61 can include a quantum dot layer (QDL). For example, the quantum dot layer (QDL) can have quantum dot particles, and the quantum dot particles can be connected to each other through surface modification groups.

[0152] Alternatively, please continue to refer to FIG. 5B, the display panel 10 can also be an OLED display panel. Based on that the display panel 10 is an OLED display panel, the light-emitting layer 61 can include an organic light-emitting layer (EML). For example, the organic light-emitting layer EML can include a light-emitting layer host material and a light-emitting layer guest material, and the light-emitting layer guest material can be a fluorescent dopant or a phosphorescent dopant.

[0153] In the following, some embodiments of the present disclosure are illustratively described by taking the display panel 10 as an OLED display panel, but the embodiments of the present disclosure include but are not limited to this, and any other type of display panel can also be considered as long as the same technical idea is applied.

[0154] In some embodiments, please continue to refer to FIG. 5B, the light-emitting functional layer 6 further includes one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0155] For example, the material used to form the hole injection layer (HIL) can include an oxide. The material used to form the hole injection layer (HIL) can also include an organic material.

[0156] Exemplarily, the material for forming the hole transport layer (HTL) can include arylamine, dimethylfluorene or carbazole material with hole transport property.

[0157] Exemplarily, the material for forming the electron transport layer (ETL) can include aromatic heterocyclic compound.

[0158] Exemplarily, the material for forming the electron injection layer (EIL) can include alkali metal or metal and its compound.

[0159] In some embodiments, please refer to FIG. 5B, the light-emitting functional layer 6 in the pixel layer D can include a single light-emitting layer 61.

[0160] In some other embodiments, as shown in FIG. 6, which is a film layer structure diagram of the pixel layer D of the display panel 10 according to some embodiments, the light-emitting functional layer 6 in the pixel layer D can include a multi-layer light-emitting layer 61.

[0161] Exemplarily, please refer to FIG. 6, the light-emitting functional layer 6 can include two light-emitting layers 61, i.e. a first light-emitting layer 61a and a second light-emitting layer 61b.

[0162] The second light-emitting layer 61b can be closer to the common electrode layer 7 than the first light-emitting layer 61a, and the common electrode layer 7 can be located on the side of the second light-emitting layer 61b away from the substrate 1.

[0163] The following will take the light-emitting functional layer 6 including two light-emitting layers 61 as an example to illustrate some embodiments of the present disclosure.

[0164] Please refer to FIG. 6, the light-emitting functional layer 6 further includes a charge generation layer (CGL) 62 between the first light-emitting layer 61a and the second light-emitting layer 61b. The charge generation layer (CGL) 62 can connect the first light-emitting layer 61a and the second light-emitting layer 61b in series to realize a kind of Tandem EL design.

[0165] On the one hand, due to the increase in the number of light-emitting layers 61, and the charge generation layer (CGL) 62 can reduce the driving voltage and generate new carriers, so the light-emitting efficiency of the light-emitting functional layer 6 can be doubled. On the other hand, under the same brightness, the current density of the display panel 10 with Tandem EL design is reduced compared with the display panel 10 with single-layer light-emitting design, which is beneficial to prolong the service life of the display panel 10.

[0166] Exemplarily, the charge generation layer (CGL) 62 can be configured to generate, transport and inject carriers.

[0167] Exemplarily, the charge generation layer (CGL) 62 can include an N-type charge generation layer (n-CGL) and a P-type charge generation layer (p-CGL).

[0168] The N-type charge generation layer (n-CGL) may, for example, include an organic electron transport layer (ETL) material doped with a metal material.

[0169] The P-type charge generation layer (p-CGL) may, for example, include an organic hole transport layer (HTL) material doped with a P-type light emitting dopant (p-dopant, PD).

[0170] In some embodiments, please refer to FIG. 6, part of the film layers in the light emitting functional layer 6 can be common layers.

[0171] The common layer in the light emitting functional layer 6 means that part of the film layers in the light emitting functional layer 6 are formed in the areas where the plurality of sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) are located, and are also formed in the gap areas between the plurality of sub-pixels 9 (for example, the gap area J between the first sub-pixel 91 and the second sub-pixel 92). That is, part of the film layers in the light emitting functional layer 6 are continuous film layers of the whole layer, in this case, it can be considered that the plurality of sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) share part of the film layers in the light emitting functional layer 6, and part of the film layers in the light emitting functional layer 6 can be considered as common layers in the light emitting functional layer 6.

[0172] Exemplarily, the partial film layer in the light-emitting functional layer 6 can be a common layer due to process reasons. For example, when a partial film layer in the light-emitting functional layer 6 is formed by using an open mask process, the material used to form the partial film layer in the light-emitting functional layer 6 is deposited in the area where the plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are located, specifically, the material used to form the partial film layer in the light-emitting functional layer 6 is deposited in the plurality of pixel openings K (e.g., the first pixel opening K1 and the second pixel opening K2), that is, the partial film layer in the light-emitting functional layer 6 is located in the plurality of pixel openings K (e.g., the first pixel opening K1 and the second pixel opening K2), and is used to form the light-emitting part 6a in the sub-pixel 9 (e.g., the light-emitting part 6a of the first sub-pixel 91 and the light-emitting part 6a of the second sub-pixel 92); at the same time, the material used to form the partial film layer (e.g., the charge generation layer (CGL) 62) in the light-emitting functional layer 6 is also deposited in the gap area between the plurality of sub-pixels 9 (e.g., the gap area J between the first sub-pixel 91 and the second sub-pixel 92), specifically, the material used to form the partial film layer (e.g., the charge generation layer (CGL) 62) in the light-emitting functional layer 6 is also deposited in the gap area between the plurality of pixel openings K (e.g., the gap area between the first pixel opening K1 and the second pixel opening K2), that is, the partial film layer (e.g., the charge generation layer (CGL) 62) in the light-emitting functional layer 6 is located in the gap area between the plurality of pixel openings K (e.g., the first pixel opening K1 and the second pixel opening K2), so that the two adjacent sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are connected through the light-emitting functional layer 6 formed in the gap area J. Specifically, the light-emitting part 6a of the two adjacent sub-pixels 9 (e.g., the light-emitting part 6a of the first sub-pixel 91 and the light-emitting part 6a of the second sub-pixel 92) are connected through the light-emitting functional layer 6 formed in the gap area J.

[0173] That is, the common layer in the light-emitting functional layer 6 can cover the area where the plurality of sub-pixels 9 (e.g., the first sub-pixel 91 and the second sub-pixel 92) are located, and the gap area between the plurality of sub-pixels 9 (e.g., the gap area J between the first sub-pixel 91 and the second sub-pixel 92), and the common layer is continuous at the gap area between the plurality of sub-pixels 9 (e.g., the gap area J between the first sub-pixel 91 and the second sub-pixel 92).

[0174] When the sub-pixel 9 is working, the carriers are prone to flow laterally through the common layer in the light-emitting functional layer 6 (that is, the carriers flow from one sub-pixel 9 to another sub-pixel 9), resulting in crosstalk between the adjacent sub-pixels 9, which is particularly serious at low gray levels.

[0175] Especially when the common layer in the light-emitting functional layer 6 has strong conductivity, it is easy to cause more serious crosstalk between the adjacent sub-pixels 9. For example, when the charge generation layer (CGL) 62 is the common layer, since the charge generation layer (CGL) 62 has strong conductivity, it will cause more serious crosstalk between the adjacent sub-pixels 9, which may cause color cast.

[0176] For example, as shown in FIG. 6, when the first sub-pixel 91 is working, the first sub-pixel 91 is input with a signal, and the second sub-pixel 92 will also be lit at the same time, causing the picture color purity of the first sub-pixel 91 to decrease, the low gray scale color gamut to decrease, and the display effect of the display panel 10 to be affected.

[0177] Based on this, in some embodiments, as shown in FIG. 7, which is a structural diagram of the display panel 10 according to some embodiments. The display panel 10 further includes a partition structure 32a. The partition structure 32a is located between the first pixel opening K1 and the second pixel opening K2. That is, the partition structure 32a is located between the first sub-pixel 91 and the second sub-pixel 92.

[0178] Based on the fact that the charge generation layer (CGL) 62 is the common layer in the light-emitting functional layer 6, in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32a.

[0179] It should be noted that the above-mentioned “in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32a” means that in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is discontinuous or non-integrated at the partition structure 32a.

[0180] By arranging the partition structure between the first sub-pixel 91 and the second sub-pixel 92 arranged adjacently, and making at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 disconnected at the partition structure 32a, the crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with strong conductivity is avoided, which is conducive to improving the display effect of the display panel 10.

[0181] Exemplarily, the partition structure 32a can include a negative photosensitive material.

[0182] Exemplarily, in the light-emitting functional layer 6, besides the charge generation layer (CGL) 62, other film layers in the light-emitting functional layer 6 can also be common layers in the light-emitting functional layer 6. For example, based on the light-emitting functional layer 6 including one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL), one or more of the hole injection layer (HIL), the hole transport layer (HTL), the electron blocking layer (EBL), the hole blocking layer (HBL), the electron transport layer (ETL), and the electron injection layer (EIL) can also be common layers in the light-emitting functional layer 6.

[0183] When part of the film layers in the light-emitting functional layer 6, besides the charge generation layer (CGL) 62, are common layers in the light-emitting functional layer 6, only the charge generation layer (CGL) 62 can be disconnected at the partition structure 32a, or the other film layers as common layers can also be disconnected at the partition structure 32a.

[0184] For example, as shown in FIG. 7, all the common layers in the light-emitting functional layer 6 are disconnected at the partition structure 32a. That is, part of the light-emitting functional layer 6 located away from the surface 32aa of the substrate 1 of the partition structure 32a and another part of the light-emitting functional layer 6 are discontinuous or not integrated.

[0185] By disconnecting all the common layers in the light-emitting functional layer 6 at the partition structure 32a, the carrier can be prevented from flowing laterally through the common layers in the light-emitting functional layer 6 (that is, the carrier flows from one sub-pixel 9 to another sub-pixel 9), thereby avoiding crosstalk between adjacent sub-pixels 9 (for example, the first sub-pixel 91 and the second sub-pixel 92) and further improving the display effect of the display panel 10.

[0186] For ease of illustration, some embodiments of the present disclosure are schematically described below by taking all the common layers in the light-emitting functional layer 6 as an example.

[0187] In some embodiments, please continue to refer to FIG. 7. Along the third direction Z, the spacing d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is greater than the spacing d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0188] That is, the surface 5aa of the pixel definition layer 5 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32a away from the substrate 1.

[0189] In one aspect, when forming the light-emitting functional layer 6 by the evaporation process, a mask plate needs to be arranged on the side of the pixel definition layer 5 and the partition structure 32a away from the substrate 1. Since the surface 5aa of the pixel definition layer 5 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32a away from the substrate 1, the surface 32aa of the partition structure 32a away from the substrate 1 is closer to the mask plate than the surface 5aa of the pixel definition layer 5 away from the substrate 1. Therefore, the partition structure 32a is prone to scratching with the mask plate. The debris of the partition structure 32a caused by the scratching may affect the packaging reliability, and the debris of the partition structure 32a caused by the scratching is easy to enter the pixel opening K, affecting the light emission of the light-emitting part 6a in the pixel opening K, which may cause the display panel 10 to have a black spot problem, resulting in a decrease in the yield of the display panel 10.

[0190] On the other hand, since the surface 5aa of the pixel definition layer 5 away from the substrate 1 is closer to the substrate 1 than the surface 32aa of the partition structure 32a away from the substrate 1, the partition structure 32 is prone to shielding the sub-pixel 9 in the side view state, and affecting the visual experience of the display panel 10.

[0191] Therefore, in some embodiments, as shown in FIG. 8, which is a structural diagram of a display panel 10 according to some embodiments. Along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is less than or equal to the distance d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0192] That is, the surface 32aa of the partition structure 32a away from the substrate 1 is closer to the substrate 1 than the surface 5aa of the pixel definition layer 5 away from the substrate 1, which is shown in FIG. 8; or, the surface 32aa of the partition structure 32a away from the substrate 1 is flush with the surface 5aa of the pixel definition layer 5 away from the substrate 1.

[0193] By making the surface 32aa of the partition structure 32a away from the substrate 1 not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, on the one hand, when forming the light-emitting functional layer 6 by the evaporation process, the partition structure 32a and the mask plate can be prevented from scratching, so that the debris of the partition structure 32a caused by the scratching can be avoided, the light-emitting part 6a in the pixel opening K can emit light normally, and the packaging reliability can be improved, which is conducive to improving the yield of the display panel 10.

[0194] On the other hand, since the surface 32aa of the partition structure 32a away from the substrate 1 is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, in the side view state, the partition structure 32 can be prevented from shielding the sub-pixel 9, and the visual experience of the display panel 10 can be improved.

[0195] In some embodiments, please continue to refer to FIG. 8, and in combination with FIG. 9, FIG. 9 is a structural diagram of the partition structure 32a of the display panel 10 according to some embodiments. The display panel 10 further comprises a first dielectric layer 31 located between the partition structure 32a and the substrate 1. The first dielectric layer 31 is provided with an opening T away from a surface 31a of the substrate 1, and at least part of the partition structure 32a is located in the opening T.

[0196] Please continue to refer to FIG. 9. By arranging at least part of the partition structure 32a in the opening T, the size g1 of the partition structure 32a along the third direction Z (hereinafter referred to as the height g1 of the partition structure 32a for ease of description) can be increased, that is, the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a close to the substrate 1 is increased, so that the edge of the partition structure 32a has a large difference, which is beneficial to improve the partition effect of the partition structure 32a on the light-emitting functional layer 6 and avoid the continuous light-emitting functional layer 6 at the partition structure 32a.

[0197] Exemplarily, the first dielectric layer 3 can comprise a planar layer. The planar layer is mainly used to block water and oxygen and block alkali ions.

[0198] Exemplarily, the first dielectric layer 3 can be coated by a spin coating process to obtain PI (Polyimide, polyimide), or can be deposited by a PECVD process to obtain silicon nitride, silicon oxide or silicon oxynitride.

[0199] Exemplarily, the opening T can penetrate the first dielectric layer 3.

[0200] Alternatively, as shown in FIG. 9, the opening T can also not penetrate the first dielectric layer 3. That is, the depth g2 of the opening T is less than the thickness g3 of the first dielectric layer 31.

[0201] It should be noted that the "depth g2 of the opening T" refers to the size g2 of the opening T along the third direction Z. The "thickness g3 of the first dielectric layer 31" refers to the size g3 of the first dielectric layer 31 along the third direction Z.

[0202] In some embodiments, please continue to refer to FIG. 9. The side 32ac of the partition structure 32a close to the second pixel opening K2 can be provided with an undercut structure.

[0203] Alternatively, as shown in FIG. 10, FIG. 10 is a structural diagram of the partition structure 32a of the display panel 10 according to some embodiments. The side 32ab of the partition structure 32a close to the first pixel opening K1 can be provided with an undercut structure.

[0204] Alternatively, as shown in FIG. 11, which is a structural diagram of the partition structure 32a of the display panel 10 according to some embodiments. The side 32ac of the partition structure 32a close to the second pixel opening K2 and the side 32ab of the partition structure 32a close to the first pixel opening K1 can each be provided with an undercut structure.

[0205] It should be noted that the aforementioned “undercut structure” is formed by the side 32ac of the partition structure 32a close to the second pixel opening K1 and / or the side 32ab of the partition structure 32a close to the first pixel opening K1 being recessed inwardly of the partition structure 32a by a certain distance.

[0206] The aforementioned “in the light-emitting functional layer 6, at least the charge generation layer (CGL) 62 is disconnected at the partition structure 32a” can specifically be that, in the light-emitting functional layer 6, at least the charge generation layer 62 is disconnected at the undercut structure of the partition structure 32a.

[0207] By providing the undercut structure and disconnecting at least the charge generation layer 62 in the light-emitting functional layer 6 at the undercut structure, it is at least possible to avoid the crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with strong conductivity, which is conducive to improving the display effect of the display panel 10.

[0208] Exemplarily, please continue to refer to FIGS. 9, 10 and 11. The undercut structure is located in the opening T, and the undercut structure and the sidewall of the opening T have a spacing d4. That is, the undercut structure and the sidewall of the opening T are not in contact.

[0209] In some embodiments, as shown in FIGS. 9, 12A, 12B and 12C, which are structural diagrams of the partition structure 32a of the display panel 10 according to some embodiments. Based on the side 32ac of the partition structure 32a close to the second pixel opening K2, the undercut structure is provided, and the side 32ab of the partition structure 32a close to the first pixel opening K1 is at least partially attached to the sidewall of the opening T.

[0210] Exemplarily, please continue to refer to FIG. 9, FIG. 12A, FIG. 12B and FIG. 12C, the slope of the side wall of the opening T close to the undercut of the one side of the partition structure 32a is greater than the slope of the side wall of the opening T away from the undercut of the one side of the partition structure 32a. Since the one side 32ac of the partition structure 32a close to the second pixel opening K2 is provided with the undercut in the embodiment shown in FIG. 9, FIG. 12A, FIG. 12B and FIG. 12C, therefore the slope of the side wall of the opening T close to the one side 32ac of the partition structure 32a is greater than the slope of the side wall of the opening T close to the one side 32ab of the partition structure 32a.

[0211] That is to say, the slope of the side wall of the opening T close to the one side 32ab of the partition structure 32a is smaller, and the side wall is relatively flat, which is beneficial to the attachment of the one side 32ab close to the first pixel opening K1 to the side wall when the partition structure 32a is formed in the opening T, and is beneficial to the adhesion of the side wall to the one side 32ab of the first pixel opening K1.

[0212] Exemplarily, as shown in FIG. 12A, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 along the third direction Z can be smaller than the distance d3 between the surface 31a of the first dielectric layer 31 away from the substrate 1 and the substrate 1. That is to say, the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32a away from the substrate 1.

[0213] Based on that the surface 31a of the first dielectric layer 31 away from the substrate 1 is farther away from the substrate 1 than the surface 32aa of the partition structure 32a away from the substrate 1, the one side 32ab of the partition structure 32a close to the first pixel opening K1 can be completely adhered to the side wall of the opening T.

[0214] Alternatively, as shown in FIG. 12B, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 along the third direction Z can be equal to the distance d3 between the surface 31a of the first dielectric layer 31 away from the substrate 1 and the substrate 1. That is to say, the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32a away from the substrate 1.

[0215] Based on that the surface 31a of the first dielectric layer 31 away from the substrate 1 is flush with the surface 32aa of the partition structure 32a away from the substrate 1, the one side 32ab of the partition structure 32a close to the first pixel opening K1 can be completely adhered to the side wall of the opening T.

[0216] Alternatively, as shown in FIG. 12C, along the third direction Z, the distance d2 between the partition structure 32a and the surface 32aa of the substrate 1, can be greater than the distance d3 between the first dielectric layer 31 and the surface 31a of the substrate 1. That is, the surface 31a of the first dielectric layer 31 is closer to the substrate 1 than the surface 32aa of the partition structure 32a.

[0217] Based on the surface 31a of the first dielectric layer 31 being closer to the substrate 1 than the surface 32aa of the partition structure 32a, the side 32ab of the partition structure 32a close to the first pixel opening K1 can have a portion abutting the sidewall of the opening T and another portion extending outside the opening T, and the portion of the side 32ab of the partition structure 32a close to the first pixel opening K1 extending outside the opening T is free of contact with the surface 31a of the first dielectric layer 31.

[0218] Alternatively, as shown in FIG. 9, along the third direction Z, the distance d2 between the partition structure 32a and the surface 32aa of the substrate 1, can be greater than the distance d3 between the first dielectric layer 31 and the surface 31a of the substrate 1. That is, the surface 31a of the first dielectric layer 31 is closer to the substrate 1 than the surface 32aa of the partition structure 32a.

[0219] Based on the surface 31a of the first dielectric layer 31 being closer to the substrate 1 than the surface 32aa of the partition structure 32a, the side 32ab of the partition structure 32a close to the first pixel opening K1 can have a portion abutting the sidewall of the opening T and another portion extending outside the opening T, and the portion of the side 32ab of the partition structure 32a close to the first pixel opening K1 extending outside the opening T is free of contact with the surface 31a of the first dielectric layer 31.

[0220] For example, as shown in FIG. 9, the portion of the partition structure 32a lapping on the surface 31a of the first dielectric layer 31 includes a first side surface 32ae based on the portion of the side 32ab of the partition structure 32a close to the first pixel opening K1 extending outside the opening T, lapping on the surface 31a of the first dielectric layer 31, the first side surface 32ae being close to the first pixel opening K1 and belonging to the side 32ab of the partition structure 32a close to the first pixel opening K1.

[0221] The first side surface 32ae and the first dielectric layer 31 away from the surface 31a of the substrate 1 have a first included angle R1. The first included angle R1 is toward the opening T, and the first included angle R1 is an acute angle. That is, the first side surface 32ae is a bevel, which makes the first dielectric layer 31 away from the surface 31a of the substrate 1 be able to be smoothly transitioned to the surface 32aa of the partition structure 32a away from the substrate 1 by the first side surface 32ae.

[0222] When the pixel definition layer (PDL) 5 is formed, the pixel definition layer (PDL) 5 is formed on the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1. Since the first dielectric layer 31 away from the surface 31a of the substrate 1 is able to be smoothly transitioned to the surface 32aa of the partition structure 32a away from the substrate 1 by the first side surface 32ae, the pixel definition layer (PDL) 5 is able to be continuously formed between the surface 31a of the first dielectric layer 31 away from the substrate 1, the first side surface 32ae, and the surface 32aa of the partition structure 32a away from the substrate 1, which can avoid the pixel definition layer (PDL) 5 being broken at the partition structure 32a, and can reduce the stress on the transition area (i.e., the first side surface 32ae) between the surface 31a of the first dielectric layer 31 away from the substrate 1 and the surface 32aa of the partition structure 32a away from the substrate 1, which is beneficial to improve the stability of the display panel 10.

[0223] In some other embodiments, as shown in FIGS. 10, 13A, 13B, and 13C, which are all a structure diagram of the partition structure 32a of the display panel 10 according to some embodiments, based on the side 32ab of the partition structure 32a close to the first pixel opening K1, an undercut structure is arranged, and the side 32ac of the partition structure 32a close to the second pixel opening K2 is at least partially attached to the sidewall of the opening T.

[0224] For example, as shown in FIGS. 10, 13A, 13B, and 13C, the slope of the sidewall of the opening T close to the undercut structure is greater than the slope of the sidewall of the opening T away from the undercut structure. Since the side 32ab of the partition structure 32a close to the first pixel opening K1 is arranged with the undercut structure in the embodiments shown in FIGS. 10, 13A, 13B, and 13C, the slope of the sidewall of the opening T close to the side 32ab of the partition structure 32a is greater than the slope of the sidewall of the opening T close to the side 32ac of the partition structure 32a.

[0225] That is, the side 32ac of the partition structure 32a close to the first pixel opening K1 has a smaller slope of the side wall, and the side wall is relatively flat, so that the side 32ac of the partition structure 32a close to the first pixel opening K1 is easily attached to the side wall when the partition structure 32a is formed in the opening T, and the side wall is easily attached to the side 32ac of the partition structure 32a close to the first pixel opening K1.

[0226] Exemplarily, as shown in FIG. 13A, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a and the substrate 1 can be smaller than the distance d3 between the surface 31a of the first dielectric layer 3 and the substrate 1. That is, the surface 31a of the first dielectric layer 3 is farther away from the substrate 1 than the surface 32aa of the partition structure 32a.

[0227] Based on that the surface 31a of the first dielectric layer 3 is farther away from the substrate 1 than the surface 32aa of the partition structure 32a, the side 32ac of the partition structure 32a close to the second pixel opening K2 can be attached to the side wall of the opening T.

[0228] Alternatively, as shown in FIG. 13B, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a and the substrate 1 can be equal to the distance d3 between the surface 31a of the first dielectric layer 3 and the substrate 1. That is, the surface 31a of the first dielectric layer 3 is flush with the surface 32aa of the partition structure 32a.

[0229] Based on that the surface 31a of the first dielectric layer 3 is flush with the surface 32aa of the partition structure 32a, the side 32ac of the partition structure 32a close to the second pixel opening K2 can be attached to the side wall of the opening T.

[0230] Alternatively, as shown in FIG. 13C, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a and the substrate 1 can be greater than the distance d3 between the surface 31a of the first dielectric layer 3 and the substrate 1. That is, the surface 31a of the first dielectric layer 3 is closer to the substrate 1 than the surface 32aa of the partition structure 32a.

[0231] Based on the first dielectric layer 31 being farther away from the surface 31a of the substrate 1 than the surface 32aa of the partition structure 32a, the side 32ac of the partition structure 32a close to the second pixel opening K2 can be partially attached to the sidewall of the opening T and partially extended out of the opening T, and the portion of the side 32ac of the partition structure 32a close to the second pixel opening K2 extended out of the opening T can not contact the surface 31a of the first dielectric layer 31.

[0232] Alternatively, as shown in FIG. 10, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a and the substrate 1 can be greater than the distance d3 between the surface 31a of the first dielectric layer 31 and the substrate 1. That is, the surface 31a of the first dielectric layer 31 is closer to the substrate 1 than the surface 32aa of the partition structure 32a.

[0233] Based on the first dielectric layer 31 being farther away from the surface 31a of the substrate 1 than the surface 32aa of the partition structure 32a, the side 32ac of the partition structure 32a close to the second pixel opening K2 can be partially attached to the sidewall of the opening T and partially extended out of the opening T, and the portion of the side 32ac of the partition structure 32a close to the second pixel opening K2 extended out of the opening T can not contact the surface 31a of the first dielectric layer 31.

[0234] For example, as shown in FIG. 10, the portion of the partition structure 32a attached to the surface 31a of the first dielectric layer 31 includes a first side surface 32ae based on the portion of the side 32ac of the partition structure 32a close to the second pixel opening K2 extended out of the opening T, the first side surface 32ae being close to the second pixel opening K2 and belonging to the side 32ac of the partition structure 32a close to the second pixel opening K2.

[0235] The first side surface 32ae and the surface 31a of the first dielectric layer 31 form a first included angle R1. The first included angle R1 is directed toward the opening T, and the first included angle R1 is an acute angle. That is, the first side surface 32ae is a bevel surface, so that the surface 31a of the first dielectric layer 31 can be smoothly transitioned from the first side surface 32ae to the surface 32aa of the partition structure 32a.

[0236] When the pixel definition layer (PDL) 5 is formed, the pixel definition layer (PDL) 5 is formed on the surface 31a away from the substrate 1 of the first dielectric layer 31, the first side surface 32ae, and the surface 32aa away from the substrate 1 of the partition structure 32a. Since the surface 31a away from the substrate 1 of the first dielectric layer 31 can be smoothly transitioned to the surface 32aa away from the substrate 1 of the partition structure 32a by the first side surface 32ae, the pixel definition layer (PDL) 5 can be continuously formed between the surface 31a away from the substrate 1 of the first dielectric layer 31, the first side surface 32ae, and the surface 32aa away from the substrate 1 of the partition structure 32a, the pixel definition layer (PDL) 5 can be prevented from being disconnected at the partition structure 32a, and the stress on the transition area (i.e., the first side surface 32ae) between the surface 31a away from the substrate 1 of the first dielectric layer 31 and the surface 32aa away from the substrate 1 of the partition structure 32a of the pixel definition layer (PDL) 5 can be reduced, which is beneficial to improving the stability of the display panel 10.

[0237] In some embodiments, as shown in FIGS. 14A and 14B, both of FIGS. 14A and 14B are a partial plan view of a display panel 10 according to some embodiments. The partition structure 32a is arranged around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has at least one gap Q.

[0238] Based on the partition structure 32a being arranged around the first pixel opening K1 and the partition structure 32a having at least one gap Q, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a around the first pixel opening K1 and be continuous at the gap Q, i.e., at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6, the part located in the first pixel opening K1 and the other part (e.g., at least the charge generation layer (CGL) 62 of the light-emitting functional layer 6, the part located in the second pixel opening K2) are only connected at the gap Q, which can reduce the crosstalk between the first sub-pixel 91 and the other sub-pixel 9 (e.g., the second sub-pixel 92) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, which is beneficial to improving the display effect of the display panel 10.

[0239] Based on the partition structure 32a being arranged around the second pixel opening K2 and the partition structure 32a having at least one gap Q, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a around the second pixel opening K2 and continuous at the gap Q, that is, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, the part located in the second pixel opening K2 and the other part (for example, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, the part located in the first pixel opening K1) are connected only at the gap Q, which can reduce the crosstalk between the second sub-pixel 92 and the other sub-pixels 9 (for example, the first sub-pixel 91) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, and is conducive to improving the display effect of the display panel 10.

[0240] For example, please continue to refer to FIG. 14A, the partition structure 32a is arranged around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has a gap Q.

[0241] Alternatively, please continue to refer to FIG. 14B, the partition structure 32a is arranged around the first pixel opening K1 or the second pixel opening K2, and the partition structure 32a has a plurality of gaps Q.

[0242] It can be understood that when the partition structure 32a has a plurality of gaps Q, the partition structure 32a is divided into a plurality of block-shaped partition portions 32a', that is, the partition structure 32a includes a plurality of block-shaped partition portions 32a'. The plurality of partition portions 32a' are arranged at intervals around the first pixel opening K1 or the second pixel opening K2.

[0243] In other embodiments, as shown in FIG. 15, which is a partial planar structure diagram of a display panel 10 according to some embodiments. The partition structure 32a has a closed loop shape around the first pixel opening K1 or the second pixel opening K2.

[0244] Based on the partition structure 32a having a closed loop shape around the first pixel opening K1, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the partition structure 32a around the first pixel opening K1, that is, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, the part located in the first pixel opening K1 and the other part (for example, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, the part located in the second pixel opening K2) are not connected, which can avoid the crosstalk between the first sub-pixel 91 and the other sub-pixels 9 (for example, the second sub-pixel 92) caused by at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6, and is conducive to further improving the display effect of the display panel 10.

[0245] Based on the closed loop shape of the partition structure 32a surrounding the second pixel opening K2, at least the charge generation layer (CGL) 62 in the light emitting functional layer 6 can be disconnected at the partition structure 32a surrounding the second pixel opening K2, i.e., at least the charge generation layer (CGL) 62 in the light emitting functional layer 6, the part located within the second pixel opening K2 and the other part (e.g., the part of at least the charge generation layer (CGL) 62 in the light emitting functional layer 6 located within the first pixel opening K1) are not connected, so that the crosstalk between the second sub-pixel 92 and the other sub-pixels 9 (e.g., the first sub-pixel 91) caused by at least the charge generation layer (CGL) 62 in the light emitting functional layer 6 can be avoided, and the display effect of the display panel 10 can be further improved.

[0246] In some embodiments, please refer to FIGS. 14A, 14B and 15, the partition structure 32a includes a third sub-partition structure 323 located between the first sub-pixel 91 and the second sub-pixel 92, the third sub-partition structure 323 can be a part of the partition structure 32a surrounding the first pixel opening K1 and a part of the partition structure 32a surrounding the second pixel opening K2, i.e., only one partition structure 32a (i.e., the third sub-partition structure 323) is arranged between the first sub-pixel 91 and the second sub-pixel 92, and the third sub-partition structure 323 can be a common partition structure of the partition structure 32a surrounding the first pixel opening K1 and the partition structure 32a surrounding the second pixel opening K2. The distance between the first sub-pixel 91 and the second sub-pixel 92 can be reduced, so that the layout of the plurality of sub-pixels 9 in the display panel 10 is more compact, and the pixel density of the display panel 10 can be improved.

[0247] In some other embodiments, as shown in FIG. 16, which is a partial planar structure diagram of the display panel 10 according to some embodiments, the partition structure 32a surrounding the first pixel opening K1 includes a first sub-partition structure 321, and the partition structure 32a surrounding the second pixel opening K2 includes a second sub-partition structure 322. The first sub-partition structure 321 and the second sub-partition structure 322 are located between the first sub-pixel 91 and the second sub-pixel 92, and are sequentially arranged along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92.

[0248] That is, two partition structures 32a (i.e., a first sub-partition structure 321 and a second sub-partition structure 322) are arranged between the first sub-pixel 91 and the second sub-pixel 92. When at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 is not disconnected or not completely disconnected at one of the first sub-partition structure 321 and the second sub-partition structure 322, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the other of the first sub-partition structure 321 and the second sub-partition structure 322. For example, when at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 is not disconnected or not completely disconnected at the first sub-partition structure 321, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be disconnected at the second sub-partition structure 322.

[0249] Therefore, by sequentially arranging the first sub-partition structure 321 and the second sub-partition structure 322 between the first sub-pixel 91 and the second sub-pixel 92 along the arrangement direction of the first sub-pixel 91 and the second sub-pixel 92, at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 can be completely disconnected at the partition structure 32a, thereby further avoiding crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with strong conductivity, and facilitating improvement of the display effect of the display panel 10.

[0250] It should be noted that in FIG. 16, only the case where the partition structure 32a has a closed loop shape surrounding the first pixel opening K1 or the second pixel opening K2 is taken as an example to schematically illustrate the arrangement manner of the partition structure 32a between the first sub-pixel 91 and the second sub-pixel 92. Based on the partition structure 32a being arranged around the first pixel opening K1 or the second pixel opening K2 and the partition structure 32a having at least one notch Q, corresponding arrangement can also be made, which will not be described herein again.

[0251] In some embodiments, the common electrode layer 7 can be continuous at the partition structure 32a.

[0252] Alternatively, as shown in FIG. 17, which is a cross-sectional view of a display panel 10 according to some embodiments. The common electrode layer 7 can also be disconnected at the partition structure 32a.

[0253] For example, referring to FIG. 17, and combining FIG. 14A and FIG. 14B, based on the partition structure 32a being arranged around the first pixel opening K1 or the second pixel opening K2 and the partition structure 32a having at least one notch Q, the common electrode layer 7 can be continuous at the at least one notch Q, facilitating transmission of common electrode (e.g., cathode) signals between the first sub-pixel 91 and the second sub-pixel 92.

[0254] Alternatively, please continue to refer to FIG. 17, and in combination with FIG. 15, based on the closed-loop shape of the partition structure 32a surrounding the first pixel opening K1 or the second pixel opening K2, in order to ensure the continuity of the common electrode layer 7 between the first sub-pixel 91 and the second sub-pixel 92, a connection structure can be added to make the common electrode layer 7 continuous between the first sub-pixel 91 and the second sub-pixel 92, facilitating the transmission of the common electrode (for example, the cathode) signal between the first sub-pixel 91 and the second sub-pixel 92.

[0255] The preparation method of the display panel 10 is described in detail below.

[0256] In some embodiments, as shown in FIG. 18, FIG. 18 is a flowchart of the preparation method of the display panel 10 according to some embodiments. The preparation method of the display panel 10 includes steps S1-S3.

[0257] S1: As shown in FIG. 19, FIG. 19 is a structure diagram corresponding to step S1 in the preparation method of the display panel 10 in the embodiment shown in FIG. 18. The partition structure 32a is formed on the substrate 1.

[0258] S2: As shown in FIG. 20, FIG. 20 is a structure diagram corresponding to step S2 in the preparation method of the display panel 10 in the embodiment shown in FIG. 18. The pixel definition layer 5 is formed on the substrate 1 with the partition structure 32a.

[0259] The pixel definition layer 5 is provided with a plurality of pixel openings K. The plurality of pixel openings K includes the first pixel opening K1 and the second pixel opening K2 arranged adjacent to each other, and the partition structure 32a is located between the first pixel opening K1 and the second pixel opening K2.

[0260] The surface 32aa of the partition structure 32a away from the substrate 1 is closer to the substrate 1 than the surface 5aa of the pixel definition layer 5 away from the substrate 1; or the surface 32aa of the partition structure 32a away from the substrate 1 is flush with the surface 5aa of the pixel definition layer 5 away from the substrate 1. That is, along the third direction Z, the distance d2 between the surface 32aa of the partition structure 32a away from the substrate 1 and the substrate 1 is less than or equal to the distance d1 between the surface 5aa of the pixel definition layer 5 away from the substrate 1 and the substrate 1.

[0261] S3: As shown in FIG. 21, FIG. 21 is a structure diagram corresponding to step S3 in the preparation method of the display panel 10 in the embodiment shown in FIG. 18. The light-emitting functional layer 6 is formed on the side of the pixel definition layer 5 away from the substrate 1.

[0262] Please continue to refer to FIG. 6. The light-emitting functional layer 6 includes a first light-emitting layer 61a, a charge generation layer (CGL) 62, and a second light-emitting layer 61b, which are sequentially stacked in a direction away from the substrate 1. The light-emitting functional layer 6, at least the charge generation layer (CGL) 62, is interrupted at the interruption structure 32a.

[0263] By arranging the interruption structure 32a between the first pixel opening K1 and the second pixel opening K2 (i.e., between the first sub-pixel 91 and the second sub-pixel 92), and causing at least the charge generation layer (CGL) 62 in the light-emitting functional layer 6 to be interrupted at the interruption structure 32a, the crosstalk between the first sub-pixel 91 and the second sub-pixel 92 caused by the charge generation layer (CGL) 62 with strong conductivity is avoided, which is conducive to improving the display effect of the display panel 10.

[0264] Further, the surface 32aa of the interruption structure 32a away from the substrate 1 is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1. On the one hand, when the light-emitting functional layer 6 is formed by an evaporation process, the interruption structure 32a and the mask plate can be prevented from being scratched, so that the debris of the interruption structure 32a caused by the scratching can be avoided, the normal light emission of the light-emitting part 6a in the pixel opening K is ensured, and the packaging reliability is improved, which is conducive to improving the yield of the display panel 10.

[0265] On the other hand, since the surface 32aa of the interruption structure 32a away from the substrate 1 is not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, the interruption structure 32 can be prevented from blocking the sub-pixel 9 in a side view state, and the visual experience of the display panel 10 is improved.

[0266] In some embodiments, please continue to refer to FIG. 18. Before the step S1, the preparation method of the display panel 10 further includes a step S0.

[0267] S0: As shown in FIG. 22, FIG. 22 is a structural diagram corresponding to the step S0 in the preparation method of the display panel 10 in the embodiment shown in FIG. 18. The first dielectric layer 31 is formed on the substrate 1. The opening T is formed on the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0268] For example, please continue to refer to FIG. 22. The opening T formed on the surface 31a of the first dielectric layer 31 away from the substrate 1 can include the following steps:

[0269] The photoresist (PR) is coated on the surface 31a of the first dielectric layer 31 away from the substrate 1.

[0270] The first dielectric layer 31 is exposed using a mask (Mask) and then developed to form the opening T.

[0271] In some embodiments, please refer to FIG. 18, and also refer to FIG. 23, which is a structural diagram corresponding to step S1 in the preparation method of the display panel 10 according to the embodiment shown in FIG. 18. Based on the above step S0, step S1 in the preparation method of the display panel 10 includes step S11 and step S12.

[0272] S11: forming the partition layer 32 on the side of the first dielectric layer 31 away from the substrate 1.

[0273] S12: performing exposure treatment on the target region M of the partition layer 32 to form the partition structure 32a. At least part of the partition structure 32a is located in the opening T.

[0274] By arranging at least part of the partition structure 32a in the opening T, the surface 32aa of the partition structure 32a away from the substrate 1 is ensured to be not higher than the surface 5aa of the pixel definition layer 5 away from the substrate 1, and at the same time, the height g1 of the partition structure 32a can be increased, i.e., the distance between the surface 32aa of the partition structure 32a away from the substrate 1 and the surface 32ad of the partition structure 32a close to the substrate 1 can be increased, so that the edge of the partition structure 32a has a large difference in height, which is beneficial to improve the partition effect of the partition structure 32a on the light-emitting functional layer 6 and avoid the continuousness of the light-emitting functional layer 6 at the partition structure 32a.

[0275] Exemplarily, the material of the partition layer 32 includes a negative photosensitive material. For example, the material of the partition layer 32 can include a negative photoresist.

[0276] It should be noted that the part of the negative photoresist exposed to light (i.e., the exposed part) will not be dissolved in the photoresist developer, and the part not exposed to light (i.e., the part other than the exposed part) will be dissolved in the photoresist developer or will be dissolved very slowly.

[0277] Please refer to FIG. 23, based on the material of the partition layer 32 including a negative photoresist, after forming the partition layer 32 on the side of the first dielectric layer 31 away from the substrate 1, a mask can be used to perform exposure treatment on the target region M of the partition layer 32, and then a developing reaction is performed to form the partition structure 32a.

[0278] Exemplarily, please refer to FIG. 23, part of the target region M overlaps with the opening T, there is an overlapping region J1, and there is a distance d5 between the side wall of the opening T. After the exposure treatment on the target region M, at least part of the obtained partition structure 32a is located in the opening T.

[0279] Another part m1 of the target region M is located outside the opening T and close to one of the first pixel opening K1 and the second pixel opening K2. The part of the partition structure 32a obtained after the exposure process of the target region M can be overlapped on the surface 31a of the first dielectric layer 32 away from the substrate 1.

[0280] Exemplarily, please continue to refer to FIG. 23, the dimension h1 (for the convenience of description, hereinafter referred to as the thickness h1 of the part of the partition layer 32 located in the opening T) of the part of the partition layer 32 located in the opening T in the third direction Z is greater than the dimension h2 (for the convenience of description, hereinafter referred to as the thickness h2 of the part of the partition layer 32 not located in the opening T) of the part of the partition layer 32 not located in the opening T in the third direction Z.

[0281] When the target region M of the partition layer 32 is subjected to the exposure process, due to the greater thickness h1 of the part of the target region M located in the opening T, the side of the part of the target region M located in the opening T away from the mask (Mask) can be insufficiently exposed and easily dissolved in the photoresist developer to form an undercut structure (undercut).

[0282] When the target region M of the partition layer 32 is subjected to the exposure process, due to the smaller thickness h2 of the part of the target region M not located in the opening T, the part of the target region M not located in the opening T can be sufficiently exposed, and the part of the partition structure 32a obtained after the development process overlapped on the surface 31a of the first dielectric layer 32 away from the substrate 1 can be inclined away from the undercut structure (undercut).

[0283] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A display panel, comprising: a substrate, a pixel definition layer located on one side of the substrate; the pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings comprises a first pixel opening and a second pixel opening arranged adjacently; a light-emitting functional layer located on a side of the pixel definition layer away from the substrate, part of the light-emitting functional layer is located in the first pixel opening and the second pixel opening; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer arranged in sequence in a direction away from the substrate, at least part of the charge generation layer in the light-emitting functional layer is located between the first pixel opening and the second pixel opening; a partition structure located between the first pixel opening and the second pixel opening, at least the charge generation layer in the light-emitting functional layer is disconnected at the partition structure; a surface of the partition structure away from the substrate is closer to the substrate than a surface of the pixel definition layer away from the substrate; or, the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate.

2. The display panel of claim 1, wherein, The display panel further comprises a first dielectric layer, the first dielectric layer is located between the partition structure and the substrate; a surface of the first dielectric layer away from the substrate is provided with an opening, at least part of the partition structure is located in the opening.

3. The display panel of claim 2, wherein, The surface of the first dielectric layer away from the substrate is closer to the substrate than the surface of the partition structure away from the substrate.

4. The display panel of claim 2, wherein, The partition structure is provided with an undercut structure on a side close to the first pixel opening; and / or, the partition structure is provided with an undercut structure on a side close to the second pixel opening; The undercut structure is located in the opening, and a spacing is formed between the undercut structure and a sidewall of the opening; At least the charge generation layer in the light-emitting functional layer is disconnected at the undercut structure.

5. The display panel of claim 4, wherein, The partition structure is provided with an undercut structure on a side close to one of the first pixel opening and the second pixel opening; At least part of the partition structure on a side close to the other of the first pixel opening and the second pixel opening is attached to the sidewall of the opening.

6. The display panel of claim 5, wherein, Part of the partition structure on a side close to the other of the first pixel opening and the second pixel opening is partially overlapped on the surface of the first dielectric layer away from the substrate.

7. The display panel of claim 6, wherein, The part of the partition structure overlapped on the surface of the first dielectric layer away from the substrate comprises a first side surface close to the other of the first pixel opening and the second pixel opening, the first side surface and the surface of the first dielectric layer away from the substrate form a first included angle; the first included angle is directed towards the opening, and the first included angle is an acute angle.

8. The display panel of claim 1, wherein, The partition structure has a closed loop shape surrounding the first pixel opening or the second pixel opening.

9. The display panel of claim 8, wherein, The display panel further comprises a common electrode layer, the common electrode layer is located on a side of the second light-emitting layer away from the substrate; the common electrode layer is continuous at the partition structure.

10. The display panel of claim 1, wherein, The partition structure is arranged around the first pixel opening or the second pixel opening, and the partition structure has at least one notch.

11. The display panel of claim 10, wherein, The display panel further comprises a common electrode layer, which is located on a side of the second light-emitting layer away from the substrate; the common electrode layer is discontinuous at the partition structure and continuous at the at least one gap.

12. The display panel of claim 10, wherein, The partition structure comprises a plurality of block-shaped partition portions, and the plurality of partition portions are arranged at intervals around the first pixel opening or the second pixel opening.

13. The display panel according to any one of claims 1 to 12, wherein The partition structure comprises a negative photosensitive material.

14. The display panel according to any one of claims 5 to 7, wherein, The slope of a side wall of the opening close to the undercut structure is greater than the slope of a side wall of the opening away from the undercut structure.

15. The display panel according to any one of claims 2 to 7, wherein, The depth of the opening is less than the thickness of the first dielectric layer.

16. A manufacturing method of a display panel, comprising: forming a partition structure on a substrate; forming a pixel definition layer on the substrate on which the partition structure is formed; the pixel definition layer is provided with a plurality of pixel openings, the plurality of pixel openings comprise a first pixel opening and a second pixel opening arranged adjacently, and the partition structure is located between the first pixel opening and the second pixel opening; a surface of the partition structure away from the substrate is close to the substrate compared with a surface of the pixel definition layer away from the substrate; or the surface of the partition structure away from the substrate is flush with the surface of the pixel definition layer away from the substrate; forming a light-emitting functional layer on a side of the pixel definition layer away from the substrate; the light-emitting functional layer comprises a first light-emitting layer, a charge generation layer and a second light-emitting layer which are sequentially stacked in a direction away from the substrate; at least the charge generation layer in the light-emitting functional layer is discontinuous at the partition structure.

17. The manufacturing method of the display panel according to claim 16, wherein, before the step of forming the partition structure on the substrate, the method further comprises: forming a first dielectric layer on the substrate; forming an opening on a surface of the first dielectric layer away from the substrate; wherein at least part of the partition structure is located in the opening.

18. The method of producing a display panel according to claim 17, wherein, the step of forming the partition structure on the substrate comprises: forming a partition layer on a side of the first dielectric layer away from the substrate; performing exposure processing on a target region of the partition layer to form the partition structure; wherein a part of the target region overlaps with the opening and has a spacing with a side wall of the opening; another part of the target region is located outside the opening and close to another one of the first pixel opening and the second pixel opening.

19. The method of producing a display panel according to claim 18, wherein The material of the partition layer comprises a negative photosensitive material.

20. A display device, comprising: the display panel according to any one of claims 1-15; a cover plate arranged on a light-outgoing side of the display panel.

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