Shift register, gate drive circuit, and display panel

Abstract

A shift register (SR), a gate drive circuit (GOA), and a display panel (PNL). The shift register (SR) comprises an input circuit (CRIM), a cascade output circuit (CROM), a control circuit (CTR), and a scanning output circuit (GOM); the input circuit (CRIM) is used for controlling the level of a first node (Q1) and the level of a control node (QB) under the control of a first clock signal (CKA) and a cascade output signal of a previous-stage cascade output circuit (CROM); the cascade output circuit (CROM) is used for outputting the cascade output signal under the control of the first node (Q1), the control node (QB), and a second clock signal (CKB); the control circuit (CTR) is used for controlling the level of a fourth node (Q4) under the control of the first node (Q1), the control node (QB), and the first clock signal (CKA); the scanning output circuit (GOM) is used for outputting a scanning signal under the control of the control node (QB), the fourth node (Q4), and an output clock signal (GCK); and the effective level duration of the cascade output signal outputted by the cascade output circuit (CROM) is less than the effective level duration of the scanning signal outputted by the scanning output circuit (GOM).

Description

Shift register, gate drive circuit and display panel

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202410371094.7, filed on March 28, 2024, entitled “Shift register, gate drive circuit and display panel”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit, and a display panel. Background Art

[0004] In the display field, such as OLED (organic light emitting diode) display, the application of LTPO (low temperature polycrystalline oxide) is becoming more and more widespread.

[0005] To achieve narrow bezels, the gate drive circuit (GOA) generally requires P-type LTPS (low-temperature polycrystalline silicon). The gates of certain TFTs (thin-film transistors) in the pixel drive circuit (PDC) require high-level pulse waveforms for effective output. Therefore, using P-type TFTs to output high-level pulse waveforms is crucial. Furthermore, due to the demands for high pixel density (ppi) and high refresh rates, the output waveform needs to be as wide as possible.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0007] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a shift register, a gate driving circuit and a display panel to improve the display quality of the display panel.

[0008] According to one aspect of the present disclosure, there is provided a shift register, the shift register comprising an input circuit, a cascade output circuit, a control circuit, and a scan output circuit;

[0009] The input circuit is used to control the levels of the first node and the control node under the control of the first clock signal and the cascade output signal of the previous stage cascade output circuit;

[0010] The cascade output circuit is used to output a cascade output signal under the control of the first node, the control node and the second clock signal;

[0011] The control circuit is used to control the level of the fourth node under the control of the first node, the control node, and the first clock signal;

[0012] The scan output circuit is used to output a scan signal under the control of the control node, the fourth node, and the output clock signal;

[0013] The effective level duration of the cascade output signal output by the cascade output circuit is shorter than the effective level duration of the scan signal output by the scan output circuit.

[0014] In one embodiment of the present disclosure, the cascade output circuit includes a first cascade output sub-circuit and a second cascade output sub-circuit;

[0015] The first electrode of the first cascade output sub-circuit is electrically connected to the first power supply voltage terminal, the second electrode is electrically connected to the cascade output signal terminal, and the control terminal is electrically connected to the control node. The first cascade output sub-circuit is configured to apply the first power supply voltage to the cascade output signal terminal in response to a strobe level of the control node;

[0016] The first pole of the second cascade output sub-circuit is electrically connected to the second clock signal terminal, the second pole of the second cascade output sub-circuit is electrically connected to the cascade output signal terminal, the control terminal of the second cascade output sub-circuit is electrically connected to the first node, and the second cascade output sub-circuit is configured to load the voltage of the second clock signal to the cascade output signal terminal in response to the selection level of the first node.

[0017] In one embodiment of the present disclosure, the scan output circuit includes a first scan output sub-circuit and a second scan output sub-circuit;

[0018] The first scan output sub-circuit has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the scan output signal terminal, and a control terminal electrically connected to a control node, and the first scan output sub-circuit is configured to output the second power supply voltage to the scan output signal terminal in response to a strobe level of the control node;

[0019] The first electrode of the second scan output sub-circuit is electrically connected to the output clock signal terminal, the second electrode is electrically connected to the scan output signal terminal, and the control terminal is electrically connected to the fourth node. The second scan output sub-circuit is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

[0020] In one embodiment of the present disclosure, the input circuit includes a cascade input subcircuit, a first subcircuit, and a second subcircuit;

[0021] The first terminal of the cascade input subcircuit is electrically connected to the cascade input signal terminal, the second terminal of the cascade input subcircuit is electrically connected to the first node, and the control terminal of the cascade input subcircuit is electrically connected to the first clock signal terminal. The cascade input subcircuit is configured to, in response to a gating level of the first clock signal, cause a voltage of the cascade input signal to be applied to the first node.

[0022] The first sub-circuit is electrically connected to the second power supply voltage terminal, the second sub-circuit is electrically connected to the control node, and the control terminal is electrically connected to the first clock signal terminal. The first sub-circuit is configured to apply the second power supply voltage to the control node in response to a gating level of the first clock signal.

[0023] The first pole of the second sub-circuit is electrically connected to the first clock signal terminal, the second pole is electrically connected to the control node, and the control terminal is electrically connected to the first node. The second sub-circuit is configured to load the voltage of the first clock signal to the control node in response to the selection level of the first node.

[0024] In one embodiment of the present disclosure, the control circuit includes a third sub-circuit, a fourth sub-circuit, and a fifth sub-circuit;

[0025] The third sub-circuit has a first terminal electrically connected to the first clock signal terminal, a second terminal electrically connected to a third node, and a control terminal electrically connected to the control node. The third sub-circuit is configured to, in response to a gating level of the control node, load a voltage of the first clock signal to the third node.

[0026] The fourth sub-circuit has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the first node, and is configured to, in response to a gating level of the first node, cause the second power supply voltage to be applied to the third node;

[0027] The first electrode of the fifth sub-circuit is electrically connected to the third node, the second electrode is electrically connected to the fourth node, and the control end is electrically connected to any one of the second clock signal end and the second power supply voltage end. The fifth sub-circuit is configured to load the voltage of the third node to the fourth node in response to the selection level of the second clock signal or the second power supply voltage.

[0028] In one embodiment of the present disclosure, the first cascade output sub-circuit includes a third transistor and a first capacitor;

[0029] A first electrode of the third transistor, a first electrode plate of the first capacitor, and the first power supply voltage terminal are electrically connected, a second electrode of the third transistor is electrically connected to the cascade output signal terminal, a control terminal of the third transistor, a second electrode plate of the first capacitor, and the control node are electrically connected, and the third transistor is configured to cause the first power supply voltage to be applied to the cascade output signal terminal in response to a gating level of the control node;

[0030] The second cascade output sub-circuit includes an eighth transistor and a second capacitor;

[0031] The first electrode of the eighth transistor is electrically connected to the second clock signal terminal, the second electrode of the eighth transistor, the second electrode plate of the second capacitor and the cascade output signal terminal are electrically connected to each other, the control terminal of the eighth transistor, the first electrode plate of the second capacitor and the second node are electrically connected to each other, and the eighth transistor is configured to respond to the selection level of the second node so that the voltage of the second clock signal is loaded to the cascade output signal terminal.

[0032] In one embodiment of the present disclosure, the first scan output sub-circuit includes a fifteenth transistor and a fourth capacitor;

[0033] The first electrode of the fifteenth transistor is electrically connected to the second power supply voltage terminal, and the second electrode is electrically connected to the scan output signal terminal. The control terminal of the fifteenth transistor, the first electrode plate of the fourth capacitor, and the control node are electrically connected to each other. The fifteenth transistor is configured to output the second power supply voltage to the scan output signal terminal in response to a gating level of the control node. The second electrode plate of the fourth capacitor is electrically connected to the first clock signal terminal.

[0034] The second scan output sub-circuit includes a fourteenth transistor and a third capacitor;

[0035] The first electrode of the fourteenth transistor is electrically connected to the output clock signal terminal, and the second electrode is electrically connected to the scan output signal terminal. The control terminal of the fourteenth transistor, the first electrode plate of the third capacitor, and the fourth node are electrically connected to each other. The fourteenth transistor is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

[0036] In one embodiment of the present disclosure, the cascade input subcircuit includes a second transistor;

[0037] The second transistor has a first electrode electrically connected to the cascade input signal terminal, a second electrode electrically connected to the first node, and a control terminal electrically connected to the first clock signal terminal, and the second transistor is configured to, in response to a gating level of the first clock signal, load a voltage of the cascade input signal to the first node;

[0038] The first sub-circuit includes a first transistor;

[0039] The first transistor has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the control node, and a control terminal electrically connected to the first clock signal terminal, and the first transistor is configured to load the second power supply voltage to the control node in response to a gating level of the first clock signal;

[0040] The second sub-circuit includes a fourth transistor;

[0041] The first electrode of the fourth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the control node, and the control terminal is electrically connected to the first node. The fourth transistor is configured to respond to the selection level of the first node so that the voltage of the first clock signal is loaded to the control node.

[0042] In one embodiment of the present disclosure, the third sub-circuit includes a tenth transistor;

[0043] The tenth transistor has a first electrode electrically connected to the first clock signal terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the control node, and the tenth transistor is configured to, in response to a gating level of the control node, load the voltage of the first clock signal to the third node;

[0044] The fourth sub-circuit includes a ninth transistor;

[0045] The ninth transistor has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the first node, and the ninth transistor is configured to, in response to a gating level of the first node, load the second power supply voltage to the third node;

[0046] The fifth sub-circuit includes a twelfth transistor;

[0047] The first electrode of the twelfth transistor is electrically connected to the third node, the second electrode of the twelfth transistor is electrically connected to the fourth node, the control terminal of the twelfth transistor is electrically connected to any one of the second clock signal terminal and the second power supply voltage terminal, and the twelfth transistor is configured to respond to the selection level of the second clock signal or the second power supply voltage so that the voltage of the third node is loaded to the fourth node.

[0048] In one embodiment of the present disclosure, the shift register further includes a sixteenth transistor;

[0049] The first electrode of the sixteenth transistor, the control end of the sixteenth transistor and the first clock signal end are electrically connected to each other, the second electrode of the sixteenth transistor is electrically connected to the first electrode plate of the fourth capacitor, and the sixteenth transistor is configured to respond to the selection level of the first clock signal so that the voltage of the first clock signal is loaded onto the first electrode plate of the fourth capacitor.

[0050] In one embodiment of the present disclosure, the control circuit further includes a thirteenth transistor;

[0051] The first electrode of the thirteenth transistor is electrically connected to the third node, the second electrode of the thirteenth transistor is electrically connected to the fourth node, the control end of the thirteenth transistor is electrically connected to any one of the first node, the second node, and the cascade input signal end, and the thirteenth transistor is configured to respond to the selection level of the first node or the second node or the cascade input signal so that the voltage of the third node is loaded to the fourth node.

[0052] In one embodiment of the present disclosure, the shift register further includes a seventeenth transistor;

[0053] The first electrode of the seventeenth transistor is electrically connected to the second electrode of the tenth transistor, the second electrode of the seventeenth transistor is electrically connected to the third node, the control terminal of the seventeenth transistor is electrically connected to the second clock signal terminal, and the seventeenth transistor is configured to respond to the selection level of the second clock signal so that the voltage of the second electrode of the tenth transistor is loaded to the third node.

[0054] In one embodiment of the present disclosure, the shift register further includes a fifth transistor, a sixth transistor, and a seventh transistor;

[0055] A first electrode of the fifth transistor is electrically connected to a first power supply voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the sixth transistor, a control terminal of the fifth transistor is electrically connected to the control node, and the fifth transistor is configured to, in response to a gating level of the control node, cause the first power supply voltage to be applied to the first electrode of the sixth transistor;

[0056] The second electrode of the sixth transistor, the second electrode of the second transistor, the first electrode of the seventh transistor, and the first node are electrically connected to each other, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal, and the sixth transistor is configured to, in response to a gating level of the second clock signal, load a voltage of the first electrode of the sixth transistor to the first node;

[0057] The second electrode of the seventh transistor is electrically connected to the second node, the control terminal of the seventh transistor is electrically connected to the second power supply voltage terminal, and the seventh transistor is configured to load the voltage of the first node to the second node in response to the second power supply voltage;

[0058] The clock period of the first clock signal, the clock period of the second clock signal and the clock period of the output clock signal are all the same;

[0059] The duration of the gating level of the first clock signal does not exceed 1 / 4 of a clock cycle;

[0060] The duration of the gating level of the second clock signal does not exceed 1 / 4 of a clock cycle;

[0061] The effective level of the output clock signal lasts for a period greater than 1 / 2 of a clock cycle;

[0062] The gating level of the first clock signal is earlier than the gating level of the second clock signal by 1 / 2 clock cycle;

[0063] The effective level of the output clock signal is earlier than the selection level of the second clock signal by 1 / 4 clock cycle.

[0064] According to another aspect of the present disclosure, a gate drive circuit is provided, comprising a plurality of the above-mentioned shift registers cascaded in sequence; wherein the cascade output signal terminal of the shift register of the previous stage is electrically connected to the cascade input signal terminal of the shift register of the next stage.

[0065] According to a first aspect of the present disclosure, there is provided a display panel, comprising a gate drive circuit and a first control trace, a second control trace, and a third control trace for driving the gate drive circuit;

[0066] The gate drive circuit comprises a plurality of shift registers according to any one of claims 1 to 13 that are cascaded in sequence; the cascade output signal terminal of the shift register of the previous stage is electrically connected to the cascade input signal terminal of the shift register of the next stage;

[0067] The first control line is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register;

[0068] The second control line is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register;

[0069] The third control trace is electrically connected to the output clock signal terminal of the shift register.

[0070] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0072] FIG1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0073] FIG2 is a schematic diagram of a film layer of a display panel in one embodiment of the present disclosure.

[0074] FIG3 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0075] FIG4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0076] FIG5 is a driving timing diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0077] FIG6 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0078] FIG. 7 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0079] FIG8 is a circuit diagram of a shift register in one embodiment of the present disclosure.

[0080] FIG9 is a circuit diagram of a shift register in one embodiment of the present disclosure.

[0081] FIG10 is a driving timing diagram corresponding to the shift register in one embodiment of the present disclosure.

[0082] FIG11 is a circuit diagram of a shift register in one embodiment of the present disclosure.

[0083] FIG12 is a circuit diagram of a shift register in one embodiment of the present disclosure.

[0084] FIG13 is a driving timing diagram corresponding to the shift register in one embodiment of the present disclosure.

[0085] FIG14 is a circuit diagram of a shift register in one embodiment of the present disclosure.

[0086] FIG15 is a circuit diagram of a shift register in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0087] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0088] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0089] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0090] In the embodiment of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor. In an embodiment of the present disclosure, at least part of the signal has a high level and a low level; one of the high level and the low level can be used as the gating level of the signal, and the gating level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the cutoff level of the signal, and the cutoff level of the signal can turn off the controlled transistor. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its gating level is a low level, and its cutoff level is a high level. For another example, for a signal that controls an N-type transistor (the signal can be loaded to the control terminal of the N-type transistor), its gating level is a high level, and its cutoff level is a low level.

[0091] Structural layer A is located on the side of structural layer B facing away from the base substrate. This means that structural layer A is formed on the side of structural layer B facing away from the base substrate. When structural layer B is a patterned structure, part of structural layer A may also be located at the same physical height as structural layer B or lower than the physical height of structural layer B, with the base substrate serving as a height reference.

[0092] An embodiment of the present disclosure provides a display panel PNL. Referring to FIG. 1 , the display panel PNL includes a display area AA and a peripheral area BB located on at least one side of the display area AA. In the display area AA, the display panel PNL is provided with an array of display units UU, each of which includes a sub-pixel PIX and a pixel driving circuit PDC for driving the sub-pixel PIX. The display panel PNL does not have a display unit in the peripheral area BB, or the display unit provided is not used to display an image. Referring to FIG. 1 , the display panel PNL is provided with a plurality of scan lines GL extending along a row direction DH in the display area AA, each scan line GL being provided in a one-to-one correspondence with each display unit row. The pixel driving circuit PDC of each display unit in the display unit row is electrically connected to the corresponding scan line GL. The display panel PNL is also provided with a plurality of data lines DL extending along a column direction DV in the display area AA, each data line DL being provided in a one-to-one correspondence with each display unit column. The pixel driving circuit PDC of each display unit in the display unit column is electrically connected to the corresponding data line DL. In this way, the pixel driving circuit PDC of each display unit is connected to the scan line GL and the data line DL. The scan line GL is loaded with a scan signal to control the state of the pixel driving circuit PDC. It will be understood that in the example of Figure 1, only one scan line GL corresponding to the display unit row is illustrated; as needed, the display panel PNL can be provided with a plurality of different scan lines GL corresponding to the display unit row. The data line DL can be loaded with a data voltage Vdata for driving the pixel driving circuit PDC. The pixel driving circuit PDC can drive the sub-pixel PIX according to the written data voltage Vdata, thereby controlling the brightness of the sub-pixel PIX. It will be understood that the pixel driving circuit PDC can also control the brightness of the sub-pixel PIX according to other signals.

[0093] Optionally, the pixel drive circuit PDC includes at least a data write transistor, a drive transistor and a storage capacitor, and the gate of the drive transistor can be electrically connected to an electrode plate of the storage capacitor. The source of the data write transistor can be electrically connected to the data line DL, and the gate of the data write transistor can be electrically connected to a write control line for loading a data write signal (a scan signal). The pixel drive circuit PDC is configured so that when the gating level of the data write signal is loaded on the write control line, the data write transistor is turned on, thereby causing the drive voltage on the data line DL to be written to the gate of the drive transistor and the storage capacitor. When the data write transistor is turned off, the drive voltage can be maintained by the storage capacitor. The drive transistor can output a drive current to drive the sub-pixel PIX to emit light under the control of the voltage on its gate. It is understandable that the pixel drive circuit PDC of the embodiment of the present disclosure may also include other transistors or capacitors so that the pixel drive circuit PDC has better driving performance. For example, the pixel drive circuit PDC can be a pixel drive circuit of 7T1C (7 thin film transistors and a storage capacitor), 8T1C (8 thin film transistors and a storage capacitor) or other architectures.

[0094] Optionally, the sub-pixel PIX can be a current-driven self-luminous element, for example, it can be any one of the light-emitting elements such as OLED, PLED, QLED, Micro LED, MiNi LED, etc. In this embodiment, the sub-pixel PIX can include sub-pixels PIX of multiple different colors, for example, a red sub-pixel for emitting red light, a blue sub-pixel for emitting green light, and a green sub-pixel for emitting green light. It is understood that in other embodiments of the present disclosure, the sub-pixels PIX in the display area AA may also have sub-pixels PIX of other colors (for example, a yellow sub-pixel for emitting yellow light, a cyan sub-pixel for emitting cyan light, a white sub-pixel for emitting white light, etc.).

[0095] In one embodiment of the present disclosure, referring to FIG2 , the display panel PNL may include a base substrate SBT, a drive layer DRL, and a pixel layer PIXL, which are stacked in sequence. The pixel layer PIXL includes subpixels PIX, and the drive layer DRL includes a pixel drive circuit PDC for driving the subpixels PIX. Each subpixel PIX can emit light to display an image under the drive of the pixel drive circuit PDC. Furthermore, the display panel PNL also includes a thin film encapsulation layer TFE located on the side of the pixel layer PIXL away from the drive backplane DBP. The thin film encapsulation layer TFE can encapsulate and protect the pixel layer PIXL.

[0096] Optionally, the substrate SBT can be a substrate of an inorganic material, or a substrate of an organic material; of course, it can also be a composite substrate formed by stacking a substrate of an inorganic material and a substrate of an organic material. For example, in some embodiments of the present disclosure, the material of the substrate SBT can be a glass material such as soda-lime glass, quartz glass, sapphire glass, etc. In some other embodiments of the present disclosure, the material of the substrate SBT can be polymethyl methacrylate, polyvinyl alcohol, polyvinyl phenol, polyethersulfone, polyimide, polyamide, polyacetal, polycarbonate, polyethylene terephthalate, polyethylene naphthalate or a combination thereof. In some other embodiments of the present disclosure, the substrate SBT can also be a flexible substrate, for example, the material of the substrate SBT can include polyimide.

[0097] Optionally, in the drive layer DRL, any pixel drive circuit PDC may include a thin film transistor TFT and a storage capacitor. Furthermore, the thin film transistor TFT may be selected from a top-gate thin film transistor, a bottom-gate thin film transistor, or a dual-gate thin film transistor; the material of the active layer of the thin film transistor may be an amorphous silicon semiconductor material, a low-temperature polycrystalline silicon semiconductor material, a metal oxide semiconductor material, an organic semiconductor material, a carbon nanotube semiconductor material, or other types of semiconductor materials; and the thin film transistor may be an N-type thin film transistor or a P-type thin film transistor.

[0098] It is understandable that, among the transistors in the pixel driving circuit, the types of any two transistors may be the same or different. For example, in some embodiments, in a pixel driving circuit, some transistors may be N-type transistors and some transistors may be P-type transistors. Again for example, in other embodiments, in a pixel driving circuit, the material of the active layer of some transistors may be a low-temperature polysilicon semiconductor material, and the material of the active layer of some transistors may be a metal oxide semiconductor material. In some embodiments of the present disclosure, the thin film transistors are low-temperature polysilicon transistors. In some other embodiments of the present disclosure, some thin film transistors are low-temperature polysilicon transistors, and some thin film transistors are metal oxide transistors.

[0099] Optionally, the drive layer DRL may include a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, a planarization layer PLN, etc. stacked between the substrate SBT and the pixel layer PIXL. Each thin film transistor and storage capacitor may be formed by film layers such as the semiconductor layer SCL, the gate insulating layer GI, the gate layer GT, the interlayer dielectric layer ILD, and the source / drain metal layer SD. The positional relationship of each film layer may be determined according to the film layer structure of the thin film transistor. Furthermore, the semiconductor layer SCL may be used to form the channel region of the transistor, and may also be used to form partial wiring or conductive structures by conductorization when necessary. The gate layer may be used to form one or more scan wirings, such as one or more gate layer wirings such as a write control wiring, a reset control wiring, and a light emitting control wiring, and may also be used to form the gate of a transistor, and may also be used to form part or all of the electrode plates of a storage capacitor. The source / drain metal layer may be used to form source / drain metal layer wirings such as a data line DL and a drive power supply voltage wiring, and may also be used to form part of the electrode plates of a storage capacitor. Of course, in other embodiments of the present disclosure, the driving layer DRL may further include other film layers as needed, for example, it may further include a light shielding layer located between the semiconductor layer SCL and the substrate SBT. As needed, any of the above-mentioned film layers such as the semiconductor layer SCL, the gate layer GT, the source / drain metal layer SD, etc. may also be multi-layered. For example, the driving layer DRL may include two different semiconductor layers SCL, or two or three source / drain metal layers SD, or two or three gate layers GT. Accordingly, the insulating film layers in the driving layer DRL (such as the gate insulating layer GI, the interlayer dielectric layer ILD, the planarization layer PLN, etc.) may be adaptively increased or decreased, or new insulating film layers may be added as needed.

[0100] Optionally, the driving layer DRL may further include a passivation layer. The passivation layer may be provided on a surface of the source / drain metal layer SD away from the substrate SBT, so as to protect the source / drain metal layer SD.

[0101] As an example, referring to FIG2 , the driving layer DRL may include an inorganic buffer layer BUF, a semiconductor layer SCL, a gate insulating layer GI, a gate layer GT, an interlayer dielectric layer ILD, a source / drain metal layer SD, and a planarization layer PLN stacked in sequence, and the thin film transistor formed in this way is a top-gate thin film transistor.

[0102] In one embodiment of the present disclosure, referring to FIG2 , the sub-pixel PIX in the pixel layer PIXL is a thin-film light-emitting element, which may include two stacked electrodes and a light-emitting functional layer sandwiched between the two electrodes. For example, referring to FIG2 , the pixel layer PIXL may include a pixel electrode layer PEL, a light-emitting functional layer EFL, and a common electrode layer COML stacked in sequence. The pixel electrode layer PEL includes a plurality of pixel electrodes PE in the display area of ​​the display panel; the portion of the light-emitting functional layer EFL connected to the pixel electrode PE serves as the light-emitting functional unit of the sub-pixel PIX, and the common electrode layer COML serves as a common electrode electrically connected to the light-emitting functional units of each sub-pixel PIX.

[0103] Furthermore, the pixel layer PIXL may also include a pixel definition layer PDL located between the pixel electrode layer PEL and the light-emitting function layer EFL. The pixel definition layer PDL has a plurality of through pixel openings arranged in a one-to-one correspondence with the plurality of pixel electrodes PE, and any pixel opening exposes at least a portion of the corresponding pixel electrode. For example, the pixel definition layer PDL covers the edge of the pixel electrode PE and exposes at least a portion of the internal area of ​​the pixel electrode PE, so that the pixel definition layer PDL can effectively define the actual effective area of ​​the pixel electrode PE (the area directly connected to the light-emitting function layer EFL), thereby defining the light-emitting area and light-emitting area of ​​the sub-pixel PIX. The light-emitting function layer EFL at least covers the pixel electrode PE exposed by the pixel definition layer PDL. The common electrode layer COML can cover the light-emitting function layer EFL in the display area. The pixel electrode PE and the common electrode layer COML provide carriers such as electrons and holes to the light-emitting function layer EFL, so that the light-emitting function layer EFL emits light. The portion of the light-emitting function layer EFL located between the pixel electrode PE and the common electrode layer COML can serve as a light-emitting function unit. The pixel electrode PE, the common electrode layer COML, and the light emitting functional unit form a light emitting element LD as a sub-pixel, wherein one of the pixel electrode PE and the common electrode layer COML serves as an anode of the sub-pixel PIX, and the other serves as a cathode of the sub-pixel PIX.

[0104] In one example, the pixel electrode PE serves as an anode of the sub-pixel PIX, and the common electrode layer COML serves as a cathode of the sub-pixel PIX.

[0105] It is understandable that the types of light-emitting elements are different, and the materials and film layers of the light-emitting functional layer EFL are different.

[0106] For example, when the light-emitting element is an OLED, the light-emitting functional layer (EFL) may include an organic light-emitting layer (EML), and may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the organic light-emitting layer (EML) may include a light-emitting layer host material and a light-emitting layer guest material. The light-emitting layer guest material may be a fluorescent dopant or a phosphorescent dopant, and in particular, may be a thermally activated delayed fluorescent material. It is understood that when the OLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the light-emitting functional layer (EFL).

[0107] For another example, when the light-emitting element is a QLED, the light-emitting functional layer (EFL) may include a quantum dot layer (QDL), and may include one or more of a hole injection layer (HIL), an electron transport layer (ETL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Furthermore, the quantum dot layer (QDL) may include quantum dot particles, which may be interconnected via surface modification groups. It is understood that when the QLED adopts a stacked structure, a charge generation layer (CGL) may also be provided in the light-emitting functional layer (EFL).

[0108] 3 , in the display panel PNL, a gate drive circuit GOA is provided in the peripheral area BB to provide scan signals to the pixel drive circuit PDC. Depending on the needs of the pixel drive circuit PDC, multiple gate drive circuits GOA may be provided in the peripheral area BB to provide different scan signals. Alternatively, some scan signals may share a single gate drive circuit GOA.

[0109] Optionally, according to the needs of the pixel driving circuit PDC, the scanning signal may include but is not limited to one or more of the following signals: a write control signal for controlling the writing of the data voltage into the pixel driving circuit PDC, a light emitting control signal for controlling the output driving current of the pixel driving circuit PDC, a reset control signal for controlling the resetting of the pixel driving circuit PDC, etc.

[0110] Taking the 3T1C pixel driving circuit PDC shown in FIG4 as an example, the pixel driving circuit PDC includes a first transistor T1X to a third transistor T3X and a storage capacitor Cst. In which, a first electrode of the first transistor T1X is electrically connected to the data voltage terminal, a second electrode of the first transistor T1X, a first electrode plate of the storage capacitor Cst, a control terminal of the third transistor T3X, and a first node N1 are electrically connected to each other, and the control terminal of the first transistor T1X is electrically connected to the write control signal terminal. The first transistor T1X is configured to load the data voltage DATA to the first node N1 in response to the gate level of the write control signal G1; a first electrode of the second transistor T2X is electrically connected to the compensation signal terminal, a second electrode of the second transistor T2X, a second electrode of the third transistor T3X, the second electrode plate of the storage capacitor Cst, and a second node N2 are electrically connected to each other, and the control terminal of the second transistor T2X is electrically connected to the compensation control signal terminal. The second transistor T2X is configured to load the voltage of the compensation signal SENSE to the second node N2 in response to the gate level of the compensation control signal G2; a first electrode of the third transistor T3X is electrically connected to the driving power supply voltage terminal, and the third transistor T3X is configured to generate a driving current in response to the gate level of the first node N1 to drive the sub-pixel to emit light.

[0111] Figure 5 is a driving timing diagram corresponding to the 3T1C pixel driving circuit PDC shown in Figure 4. The various stages of this example are described below using the driving timing diagram shown in Figure 5. The first to third transistors T1X to T3X are N-type transistors, the gating level of the write control signal G1, the gating level of the compensation control signal G2, and the gating level of the first node N1 are all high, and the driving power supply voltage is the high-level power supply voltage ELVDD.

[0112] During the Write phase, as shown in Figures 4 and 5 , the write control signal G1 and the compensation control signal G2 are high, turning on the first transistor T1X and the second transistor T2X. However, during the first half of this phase, the data voltage DATA is low, so the first node N1 is low. The compensation signal SENSE is applied to the second node N2, causing N2 to be low. During the second half of this phase, the data voltage DATA changes from low to high, so the first node N1 is gradually pulled up to a high level to write the data voltage DATA into the storage capacitor Cst. The compensation signal SENSE is applied to the second node N2, causing N2 to remain low.

[0113] In the Emssion phase, as shown in Figures 4 and 5, the write control signal G1 and the compensation control signal G2 are at a low level, turning off the first transistor T1X and the second transistor T2X. The third transistor T3X is turned on by coupling with the storage capacitor Cst, thereby generating a drive current to drive the sub-pixel to emit light.

[0114] Thus, during the first half of the Write phase, the write control signal G1 controls the first transistor T1X to turn on early, and the data voltage DATA is not written to the first node N1. This precharges the first node N1, thereby improving charging efficiency. Furthermore, the early turn-on of the first transistor T1X prevents insufficient charging of the first node N1 due to the first transistor T1X turning on too slowly during data writing in the second half of the Write phase, thereby achieving fast charging and quick response. Therefore, in this example, the waveforms of the write control signal G1 and the compensation control signal G2 need to be sufficiently wide.

[0115] Taking the 6T2C pixel driving circuit PDC shown in FIG. 6 as an example, the pixel driving circuit PDC includes a first transistor T1X to a sixth transistor T6X, a storage capacitor Cst1 and a stabilizing capacitor Cst2 . Wherein, the first electrode of the first transistor T1X is electrically connected to the data voltage terminal, the second electrode of the first transistor T1X, the first electrode plate of the storage capacitor Cst1, the second electrode of the third transistor T3X, the control terminal of the sixth transistor T6X and the first node N1 are electrically connected to each other, the control terminal of the first transistor T1X is electrically connected to the write control signal terminal, and the first transistor T1X is configured to load the data voltage DATA to the first node N1 in response to the strobe level of the write control signal G1; the first electrode of the second transistor T2X, the first electrode plate of the voltage-stabilizing capacitor Cst2, and the driving power supply voltage terminal are electrically connected to each other, the second electrode of the second transistor T2X is electrically connected to the first electrode of the sixth transistor T6X, the control terminal of the second transistor T2X is electrically connected to the first light-emitting control signal terminal, and the second transistor T2X is configured to load the driving power supply voltage to the first electrode of the sixth transistor T6X in response to the strobe level of the first light-emitting control signal EM1; the first electrode of the third transistor T3X is electrically connected to the reference voltage terminal, the control terminal of the third transistor T3X is electrically connected to the first reset control signal terminal, and the third transistor T3X is electrically connected to the reference voltage terminal. X is configured to load the reference voltage Vref to the first node N1 in response to the strobe level of the first reset control signal RST1; the first electrode of the fourth transistor T4X, the second electrode plate of the storage capacitor Cst1, the second electrode plate of the stabilizing capacitor Cst2, the second electrode of the sixth transistor T6X, and the second node N2 are electrically connected to each other, the second electrode of the fourth transistor T4X, the second electrode of the fifth transistor T5X, the third node N3, and the pixel electrode are electrically connected to each other, the control terminal of the fourth transistor T4X is electrically connected to the second light-emitting control signal terminal, and the fourth transistor T4X is configured to load the voltage of the second node N2 to the third node N3 in response to the strobe level of the second light-emitting control signal EM2; the first electrode of the fifth transistor T5X is electrically connected to the initialization signal terminal, the control terminal of the fifth transistor T5X is electrically connected to the second reset control signal terminal, and the fifth transistor T5X is configured to load the initialization signal Vini to the third node in response to the strobe level of the second reset control signal RST2; and the sixth transistor T6X is configured to generate a driving current in response to the strobe level of the first node N1.

[0116] In this example, the pixel driver circuit PDC can first be supplied with the gate level of the first reset control signal RST1 and the gate level of the second reset control signal RST2. This causes the third transistor T3X to turn on, resetting the first node N1, and the fifth transistor T5X to turn on, resetting the pixel electrode of the subpixel. Then, the pixel driver circuit PDC can be supplied with the gate level of the write control signal G1; this causes the first transistor T1X to turn on, loading the data voltage DATA to the first node N1. This allows the data voltage DATA and the threshold voltage of the sixth transistor T6X to be written to the first node N1. Then, the pixel driver circuit PDC can be supplied with the gate level of the first emission control signal EM1 and the gate level of the second emission control signal EM2, thereby turning on the second transistor T2X and the fourth transistor T4X. Under the control of the first node N1, the sixth transistor T6X outputs a drive current to the subpixel, thereby controlling the subpixel's luminance. In this example, the waveform of the write control signal G1 needs to be sufficiently wide.

[0117] In an embodiment of the present disclosure, referring to FIG7 , a gate drive circuit GOA and first, second, and third control lines CL1, CL2, and CL3 for driving the gate drive circuit GOA are provided in the peripheral area BB of the display panel PNL to provide scan signals to the display area AA of the display panel PNL. The gate drive circuit GOA includes a plurality of shift registers SR connected in cascade. In two adjacent stages of shift registers SR, the cascade output signal terminal of the previous stage shift register SR is electrically connected to the cascade input signal terminal of the next stage shift register SR. Referring to FIG8 , the shift register SR includes an input circuit CRIM, a cascade output circuit CROM, a control circuit CTR, and a scan output circuit GOM. Among them, the input circuit CRIM is used to control the levels of the first node Q1 and the control node QB under the control of the first clock signal CKA and the cascade output signal CROUT of the previous stage cascade output circuit CROM; the cascade output circuit CROM is used to output the cascade output signal CROUT under the control of the first node Q1, the control node QB, and the second clock signal CKB; the control circuit CTR is used to control the level of the fourth node Q4 under the control of the first node Q1, the control node QB, and the first clock signal CKA; the scan output circuit GOM is used to output the scan signal under the control of the control node QB, the fourth node Q4, and the output clock signal GCK.

[0118] Referring to FIG. 10 , the duration of the active level of the cascade output signal CROUT output by the cascade output circuit CROM is shorter than the duration of the active level of the scan signal output by the scan output circuit GOM. Thus, the scan signal for the subpixel row is output through the scan output circuit GOM, while the cascade input signal CRIN for the next stage is output through the cascade output circuit CROM, separating the cascade and output. When the scan output circuit GOM of the previous shift register SR has not yet completed its output, the next shift register SR also outputs. This, on the one hand, causes the scan signal output by the previous shift register SR to overlap with the scan signal output by the next shift register SR, thereby offsetting the impact of the rising edges of the scan signals output by two adjacent subpixel rows and improving the display quality of the display panel PNL. On the other hand, it can also increase the refresh rate and charging efficiency of the pixel drive circuit.

[0119] It is understood that in two adjacent shift registers SR, the active level of the cascade output signal CROUT refers to the level output by the cascade output circuit CROM of the previous shift register SR, and is used to activate the level of the input circuit CRIM of the next shift register SR. The cascade output signal CROUT of the previous stage and the cascade input signal CRIN of the next stage are the same signal. In the embodiment of the present disclosure, the active level of the cascade output signal CROUT is a low level. The active level of the scan signal output by the scan output circuit GOM is a high level.

[0120] In one embodiment of the present disclosure, referring to FIG. 8 , the cascade output circuit CROM includes a first cascade output sub-circuit CROC1 and a second cascade output sub-circuit CROC2 .

[0121] The first electrode of the first cascade output sub-circuit CROC1 is electrically connected to the first power supply voltage terminal, the second electrode is electrically connected to the cascade output signal terminal, and the control terminal is electrically connected to the control node QB. The first cascade output sub-circuit CROC1 is configured to load the first power supply voltage V1 to the cascade output signal terminal in response to the selection level of the control node QB.

[0122] In one embodiment of the present disclosure, referring to FIG8 , a first electrode of the second cascade output sub-circuit CROC2 is electrically connected to the second clock signal terminal, a second electrode of the second cascade output sub-circuit CROC2 is electrically connected to the cascade output signal terminal, a control terminal of the second cascade output sub-circuit CROC2 is electrically connected to the first node Q1, and the second cascade output sub-circuit CROC2 is configured to load the voltage of the second clock signal CKB to the cascade output signal terminal in response to the selection level of the first node Q1.

[0123] In one embodiment of the present disclosure, referring to FIG. 8 , the scan output circuit GOM includes a first scan output sub-circuit GOC1 and a second scan output sub-circuit GOC2 .

[0124] Among them, the first electrode of the first scan output sub-circuit GOC1 is electrically connected to the second power supply voltage terminal, the second electrode is electrically connected to the scan output signal terminal GOUT, and the control terminal is electrically connected to the control node QB. The first scan output sub-circuit GOC1 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the selection level of the control node QB.

[0125] In one embodiment of the present disclosure, referring to FIG8 , a first electrode of the second scan output sub-circuit GOC2 is electrically connected to the output clock signal terminal, a second electrode is electrically connected to the scan output signal terminal GOUT, and a control terminal is electrically connected to the fourth node Q4. The second scan output sub-circuit GOC2 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the selection level of the fourth node Q4.

[0126] In one embodiment of the present disclosure, referring to FIG. 8 , the input circuit CRIM includes a cascade input sub-circuit CRIC, a first sub-circuit VSC1 , and a second sub-circuit VSC2 .

[0127] The cascade input sub-circuit CRIC has a first terminal electrically connected to the cascade input signal terminal, a second terminal electrically connected to the first node Q1, and a control terminal electrically connected to the first clock signal terminal. The cascade input sub-circuit CRIC is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. It should be noted that in the first-stage shift register SR, the signal at the cascade input signal terminal is the start signal STV.

[0128] In one embodiment of the present disclosure, referring to FIG8 , a first electrode of the first sub-circuit VSC1 is electrically connected to the second power supply voltage terminal, a second electrode is electrically connected to the control node QB, and a control terminal is electrically connected to the first clock signal terminal. The first sub-circuit VSC1 is configured to load the second power supply voltage V2 to the control node QB in response to the selection level of the first clock signal CKA.

[0129] In one embodiment of the present disclosure, referring to FIG8 , a first pole of the second sub-circuit VSC2 is electrically connected to the first clock signal terminal, a second pole is electrically connected to the control node QB, and a control terminal is electrically connected to the first node Q1. The second sub-circuit VSC2 is configured to load the voltage of the first clock signal CKA to the control node QB in response to the selection level of the first node Q1.

[0130] In one embodiment of the present disclosure, referring to FIG. 8 , the control circuit CTR includes a third sub-circuit VSC3 , a fourth sub-circuit VSC4 , and a fifth sub-circuit VSC5 .

[0131] Among them, the first electrode of the third sub-circuit VSC3 is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the third node Q3, and the control terminal is electrically connected to the control node QB. The third sub-circuit VSC3 is configured to respond to the selection level of the control node QB so that the voltage of the first clock signal CKA is loaded to the third node Q3.

[0132] In one embodiment of the present disclosure, referring to FIG8 , a first electrode of the fourth sub-circuit VSC4 is electrically connected to the second power supply voltage terminal, a second electrode is electrically connected to the third node Q3, and a control terminal is electrically connected to the first node Q1. The fourth sub-circuit VSC4 is configured to load the second power supply voltage V2 to the third node Q3 in response to a selection level of the first node Q1.

[0133] In one embodiment of the present disclosure, referring to FIG8 , a first terminal of the fifth sub-circuit VSC5 is electrically connected to the third node Q3, a second terminal is electrically connected to the fourth node Q4, and a control terminal is electrically connected to either the second clock signal terminal or the second power supply voltage terminal. The fifth sub-circuit VSC5 is configured to load the voltage of the third node Q3 onto the fourth node Q4 in response to the gate level of the second clock signal CKB or the second power supply voltage V2. In one example, the control terminal of the fifth sub-circuit VSC5 is electrically connected to the second clock signal terminal. In another example, the control terminal of the fifth sub-circuit VSC5 is electrically connected to the second power supply voltage terminal.

[0134] In one embodiment of the present disclosure, referring to FIG8 , the first cascade output sub-circuit CROC1 includes a third transistor T3 and a first capacitor C1. A first electrode of the third transistor T3 is electrically connected to a first electrode plate of the first capacitor C1, and a first power supply voltage terminal. A second electrode of the third transistor T3 is electrically connected to a cascade output signal terminal. A control terminal of the third transistor T3 is electrically connected to a second electrode plate of the first capacitor C1, and a control node QB. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to a gating level at the control node QB. In other embodiments of the present disclosure, the first cascade output sub-circuit CROC1 may include multiple third transistors T3 connected in series or in parallel.

[0135] In one embodiment of the present disclosure, referring to FIG8 , the second cascade output sub-circuit CROC2 includes an eighth transistor T8 and a second capacitor C2. A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal, a second electrode of the eighth transistor T8, a second electrode plate of the second capacitor C2, and the cascade output signal terminal are electrically connected to each other, and a control terminal of the eighth transistor T8, a first electrode plate of the second capacitor C2, and a second node Q2 are electrically connected to each other. The eighth transistor T8 is configured to, in response to a gating level at the second node Q2, apply the voltage of the second clock signal CKB to the cascade output signal terminal. In other embodiments of the present disclosure, the second cascade output sub-circuit CROC2 may include multiple eighth transistors T8 connected in series or in parallel.

[0136] In one embodiment of the present disclosure, referring to FIG8 , the first scan output sub-circuit GOC1 includes a fifteenth transistor T15 and a fourth capacitor C4. A first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal, and a second electrode is electrically connected to the scan output signal terminal GOUT. A control terminal of the fifteenth transistor T15, a first electrode plate of the fourth capacitor C4, and a control node QB are electrically connected to each other. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to a gate level at the control node QB. A second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal. In other embodiments of the present disclosure, the first scan output sub-circuit GOC1 may include multiple fifteenth transistors T15 connected in series or in parallel.

[0137] In one embodiment of the present disclosure, referring to FIG8 , the second scan output sub-circuit GOC2 includes a fourteenth transistor T14 and a third capacitor C3. A first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal, and a second electrode is electrically connected to the scan output signal terminal GOUT. A control terminal of the fourteenth transistor T14, a first electrode plate of the third capacitor C3, and a fourth node Q4 are electrically connected to one another. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to a gating level at the fourth node Q4. In other embodiments of the present disclosure, the second scan output sub-circuit GOC2 may include multiple fourteenth transistors T14 connected in series or in parallel.

[0138] In one embodiment of the present disclosure, referring to FIG8 , the cascade input sub-circuit CRIC includes a second transistor T2. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal, a second electrode is electrically connected to the first node Q1, and a control terminal is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. In other embodiments of the present disclosure, the cascade input sub-circuit CRIC may include multiple second transistors T2 connected in series or in parallel.

[0139] In one embodiment of the present disclosure, referring to FIG8 , the first sub-circuit VSC1 includes a first transistor T1. A first electrode of the first transistor T1 is electrically connected to a second power supply voltage terminal, a second electrode is electrically connected to a control node QB, and a control terminal is electrically connected to a first clock signal terminal. The first transistor T1 is configured to apply the second power supply voltage V2 to the control node QB in response to a gate level of the first clock signal CKA. In other embodiments of the present disclosure, the first sub-circuit VSC1 may further include multiple first transistors T1 connected in series or in parallel.

[0140] In one embodiment of the present disclosure, referring to FIG8 , the second sub-circuit VSC2 includes a fourth transistor T4. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the control node QB, and a control terminal is electrically connected to the first node Q1. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to a gating level of the first node Q1. In other embodiments of the present disclosure, the second sub-circuit VSC2 may further include multiple fourth transistors T4 connected in series or in parallel.

[0141] In one embodiment of the present disclosure, referring to FIG8 , the third sub-circuit VSC3 includes a tenth transistor T10. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal, a second electrode is electrically connected to the third node Q3, and a control terminal is electrically connected to the control node QB. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the third node Q3 in response to a gating level at the control node QB. In other embodiments of the present disclosure, the third sub-circuit VSC3 may further include multiple tenth transistors T10 connected in series or in parallel.

[0142] In one embodiment of the present disclosure, referring to FIG8 , the fourth sub-circuit VSC4 includes a ninth transistor T9. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal, a second electrode is electrically connected to the third node Q3, and a control terminal is electrically connected to the first node Q1. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to a gate level at the first node Q1. In other embodiments of the present disclosure, the fourth sub-circuit VSC4 may include multiple ninth transistors T9 connected in series or in parallel.

[0143] In one embodiment of the present disclosure, referring to FIG8 , the fifth sub-circuit VSC5 includes a twelfth transistor T12. A first electrode of the twelfth transistor T12 is electrically connected to the third node Q3. A second electrode of the twelfth transistor T12, a control terminal of the fourteenth transistor T14, a first electrode plate of the third capacitor C3, and a fourth node Q4 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to either a second clock signal terminal or a second power supply voltage terminal. The twelfth transistor T12 is configured to load the voltage of the third node Q3 onto the fourth node Q4 in response to a gate level of the second clock signal CKB or the second power supply voltage V2. In one example, the control terminal of the twelfth transistor T12 is electrically connected to the second power supply voltage terminal. In another example, the control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. Because the second clock signal CKB is intermittently on, the fourth node Q4 can be prevented from being abnormally set, thereby improving the display quality of the display panel PNL.

[0144] In one embodiment of the present disclosure, referring to FIG15 , the shift register SR further includes a sixteenth transistor T16. The first electrode of the sixteenth transistor T16, the control terminal of the sixteenth transistor T16, and the first clock signal terminal are electrically connected to each other, and the second electrode of the sixteenth transistor T16 is electrically connected to the first electrode plate of the fourth capacitor C4. The sixteenth transistor T16 is configured to, in response to the gating level of the first clock signal CKA, load the voltage of the first clock signal CKA onto the first electrode plate of the fourth capacitor C4. Thus, by arranging the sixteenth transistor T16 between the fourth capacitor C4 and the first clock signal terminal, since the sixteenth transistor T16 is only turned on under the control of the gating level of the first clock signal CKA and turned off under the control of the cut-off level of the first clock signal CKA, it is possible to avoid continuous charging or discharging of the fourth capacitor C4, thereby reducing the power consumption of the system.

[0145] In one embodiment of the present disclosure, referring to FIG8 , the control circuit CTR further includes a thirteenth transistor T13. A first electrode of the thirteenth transistor T13, a first electrode of the twelfth transistor T12, and a third node Q3 are electrically connected to each other. A second electrode of the thirteenth transistor T13, a second electrode of the twelfth transistor T12, a control terminal of the fourteenth transistor T14, a first electrode plate of the third capacitor C3, and a fourth node Q4 are electrically connected to each other. The control terminal of the thirteenth transistor T13 is electrically connected to either the first node Q1 or the second node Q2. The thirteenth transistor T13 is configured to, in response to a gating level of the first node Q1 or the second node Q2, cause the voltage of the third node Q3 to be applied to the fourth node Q4. In other embodiments of the present disclosure, the control circuit CTR may further include a plurality of thirteenth transistors T13 connected in series or in parallel.

[0146] In one embodiment of the present disclosure, referring to FIG. 11 , the shift register SR further includes a seventeenth transistor T17. A first electrode of the seventeenth transistor T17 is electrically connected to the second electrode of the tenth transistor T10, a second electrode of the seventeenth transistor T17 is electrically connected to the third node Q3, and a control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal. The seventeenth transistor T17 is configured to, in response to a gate level of the second clock signal CKB, load the voltage of the second electrode of the tenth transistor T10 to the third node Q3. Thus, the seventeenth transistor T17 separates the ninth transistor T9 from the tenth transistor T10. Since the control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal, the seventeenth transistor T17 is intermittently turned on, thereby preventing the third node Q3 from being abnormally set, thereby improving the display quality of the display panel PNL.

[0147] In one embodiment of the present disclosure, referring to FIG8 , the shift register SR further includes a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6, and a control terminal of the fifth transistor T5 is electrically connected to the control node QB. The fifth transistor T5 is configured to, in response to a gating level of the control node QB, apply the first power supply voltage V1 to the first electrode of the sixth transistor T6.

[0148] The second electrode of the sixth transistor T6, the second electrode of the second transistor T2, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other, the control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal, and the sixth transistor T6 is configured to respond to the gating level of the second clock signal CKB so that the voltage of the first electrode of the sixth transistor T6 is loaded to the first node Q1.

[0149] The second electrode of the seventh transistor T7 is electrically connected to the second node Q2, and the control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to load the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.

[0150] In this way, the voltage of the entire circuit system can be stabilized by the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 , thereby improving the stability of the circuit system.

[0151] In one embodiment of the present disclosure, referring to FIG14 , the shift register SR further includes a thirteenth transistor T13. The first electrode of the thirteenth transistor T13, the first electrode of the twelfth transistor T12, and the third node Q3 are electrically connected to each other. The second electrode of the thirteenth transistor T13, the second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the thirteenth transistor T13 is electrically connected to the cascade input signal terminal. The thirteenth transistor T13 is configured to, in response to the gating level of the cascade input signal CRIN, load the voltage of the third node Q3 to the fourth node Q4. In other embodiments of the present disclosure, the shift register SR may further include a plurality of thirteenth transistors T13 connected in series or in parallel.

[0152] In one embodiment of the present disclosure, referring to FIG8 , the shift register SR further includes an eleventh transistor T11. A first electrode of the eleventh transistor T11 is electrically connected to the control node QB, a second electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a second electrode plate of the fourth capacitor C4 are electrically connected to each other, and the control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, load the voltage of the control node QB to the control terminal of the fifteenth transistor T15. In this way, the voltage of the entire circuit system can be stabilized by the eleventh transistor T11, thereby improving the reliability of the circuit system.

[0153] In one embodiment of the present disclosure, referring to Figures 10 and 13 , the clock period of the first clock signal CKA, the clock period of the second clock signal CKB, and the clock period of the output clock signal GCK are all the same. The duration of the gating level of the first clock signal CKA does not exceed 1 / 4 of the clock period. For example, the duration of the gating level of the first clock signal CKA is 1 / 4, 1 / 5, 1 / 6, etc., of the clock period.

[0154] The duration of the gate level of the second clock signal CKB does not exceed 1 / 4 of the clock cycle. For example, the duration of the gate level of the second clock signal CKB is 1 / 4, 1 / 5, 1 / 6 of the clock cycle.

[0155] The duration of the effective level of the output clock signal GCK is greater than 1 / 2 of the clock cycle. For example, the duration of the effective level of the output clock signal GCK is 2 / 3, 3 / 4, 4 / 5, etc. of the clock cycle.

[0156] The selection level of the first clock signal CKA is earlier than the selection level of the second clock signal CKB by 1 / 2 clock cycle, and the selection level of the first clock signal CKA and the selection level of the second clock signal CKB have the same duration.

[0157] The active level of the output clock signal GCK is 1 / 4 clock cycle earlier than the gate level of the second clock signal CKB. It should be noted that in the embodiments of the present disclosure, either the active level of the output clock signal GCK or the second power supply voltage V2 is a high level, while the other is a low level. The gate levels of the first clock signal CKA and the second clock signal CKB are the same, for example, both are low.

[0158] The duration of the effective level of the output clock signal GCK is greater than 1 / 2 clock cycle. Since the output of the scan output signal terminal GOUT depends on the waveform of the output clock signal GCK, in the two adjacent shift registers SR, when the output of the scan output signal terminal GOUT of the previous shift register SR is not completed, the next shift register SR also outputs, so that the scan signal output by the previous shift register SR overlaps with the scan signal output by the next shift register SR, so as to offset the influence of the rising edge of the scan signal of the two adjacent sub-pixel rows output, thereby improving the display quality of the display panel PNL.

[0159] It will be understood that in the embodiments of the present disclosure, a clock cycle refers to the period of a clock signal. As shown in FIG10 , taking the first clock signal CKA as an example, a clock cycle refers to the duration from the first time the first clock signal CKA changes to a low level to the second time it changes to a low level. In other words, a clock cycle refers to the duration from time P1 to time P4.

[0160] In one embodiment of the present disclosure, referring to FIG7 , in two adjacent shift registers SR, the cascade output signal terminal of the upper shift register SR is electrically connected to the cascade input signal terminal of the lower shift register SR. A first control trace CL1 is electrically connected to the first clock signal terminal of the odd-numbered shift register SR and to the second clock signal terminal of the even-numbered shift register SR. A second control trace CL2 is electrically connected to the second clock signal terminal of the odd-numbered shift register SR and to the first clock signal terminal of the even-numbered shift register SR. For example, as shown in FIG1 , a first control trace CL1 is electrically connected to the first clock signal terminal of shift register SR1, the first clock signal terminal of shift register SR3, and the first clock signal terminal of shift register SR5, and is also electrically connected to the second clock signal terminals of shift register SR2, the second clock signal terminals of shift register SR4, and the second clock signal terminals of shift register SR6. A second control trace CL2 is electrically connected to the second clock signal terminals of shift register SR1, the second clock signal terminals of shift register SR3, and the second clock signal terminals of shift register SR5, and is also electrically connected to the first clock signal terminals of shift register SR2, the first clock signal terminals of shift register SR4, and the first clock signal terminals of shift register SR6. A third control trace CL3 is electrically connected to the output clock signal terminals of the shift registers SR. This facilitates achieving a narrow bezel on the display panel PNL.

[0161] Based on this, in an embodiment of the present disclosure, as shown in FIG7 , a gate drive circuit GOA and first, second, and third control lines CL1, CL2, and CL3 for driving the gate drive circuit GOA are provided in the peripheral area BB of the display panel PNL to provide scan signals to the display area AA of the display panel PNL. The gate drive circuit GOA includes a plurality of shift registers SR connected in cascade. In two adjacent shift register stages SR, the cascade output signal terminal of the previous shift register SR is electrically connected to the cascade input signal terminal of the next shift register SR. The first control line CL1 is electrically connected to the first clock signal terminal of the odd-numbered shift register SR and to the second clock signal terminal of the even-numbered shift register SR. The second control line CL2 is electrically connected to the second clock signal terminal of the odd-numbered shift register SR and to the first clock signal terminal of the even-numbered shift register SR. The third control line CL3 is electrically connected to the output clock signal terminal of the shift register SR.

[0162] In a first example, as shown in FIG9 , the shift register SR includes first to fifteenth transistors T1 to T15. A first electrode of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second electrode of the first transistor T1, a first electrode of the fourth transistor T4, a control terminal of the fifth transistor T5, a first electrode plate of the first capacitor C1, a control terminal of the third transistor T3, a control terminal of the tenth transistor T10, a first electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a control node QB are electrically connected to one another, and the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to cause the second power supply voltage V2 to be applied to the control node QB in response to a gating level of the first clock signal CKA. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal. A second electrode of the second transistor T2, the control terminal of the fourth transistor T4, the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. A first electrode of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. A second electrode of the third transistor T3, the second electrode plate of the second capacitor C2, the second electrode of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to the gate level of the control node QB. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to the gate level of the first node Q1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6. The fifth transistor T5 is configured to apply the first power supply voltage V1 to the first electrode of the sixth transistor T6 in response to the gate level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to apply the voltage of the first electrode of the sixth transistor T6 to the first node Q1 in response to the gate level of the second clock signal CKB. The second electrode of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to apply the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to apply the voltage of the second clock signal CKB to the cascade output signal terminal in response to the gate level of the second node Q2. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. A second electrode of the ninth transistor T9, a second electrode of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to the gate level of the first node Q1. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the third node Q3 in response to the gate level of the control node QB. The second electrode of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, apply the voltage of the control node QB to the control terminal of the fifteenth transistor T15. The first electrode of the twelfth transistor T12, the first electrode of the thirteenth transistor T13, and the third node Q3 are electrically connected to each other. The second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, the fourth node Q4, and the second electrode of the thirteenth transistor T13 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to, in response to the gate level of the second clock signal CKB, apply the voltage of the third node Q3 to the fourth node Q4. The control terminal of the thirteenth transistor T13 is electrically connected to either the first node Q1 or the second node Q2. The thirteenth transistor T13 is configured to, in response to a gate level at the first node Q1 or the second node Q2, load the voltage of the third node Q3 to the fourth node Q4. The first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second electrode of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to, in response to a gate level at the fourth node Q4, output the voltage of the output clock signal GCK to the scan output signal terminal GOUT. The first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to, in response to a gate level at the control node QB, output the second power supply voltage V2 to the scan output signal terminal GOUT. The second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0163] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The active level of the output clock signal GCK is high.

[0164] Figure 10 is a driving timing diagram for the shift register SR shown in Figure 9 . The clock cycles of the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all the same. The duration of the select level of the first clock signal CKA is 1 / 4 of a clock cycle. The duration of the select level of the second clock signal CKB is 1 / 4 of a clock cycle. The duration of the active level of the output clock signal GCK is 3 / 4 of a clock cycle. The select level of the first clock signal CKA precedes the select level of the second clock signal CKB by 1 / 2 of a clock cycle, and the select levels of the first clock signal CKA and the second clock signal CKB have the same duration. The active level of the output clock signal GCK precedes the select level of the second clock signal CKB by 1 / 4 of a clock cycle.

[0165] The working principle of the shift register SR shown in FIG. 9 will be described below with reference to FIG. 10 .

[0166] 9 and 10 , at time P1, the cascade input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at a low level, and the second clock signal CKB is at a high level, then the first transistor T1, the second transistor T2, the seventh transistor T7, and the eleventh transistor T11 are turned on, the low-level power supply voltage VGL causes the control node QB to be at a low level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned on, and at the same time, the cascade input signal CRIN causes the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 to be turned on, so that the cascade output signal terminal outputs a high level of the second clock signal CKB; since the first node Q1 and the second node Q2 are at a low level, the thirteenth transistor T13 is turned on; since the third node Q3 is at a low level, the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT outputs a low level of the output clock signal GCK.

[0167] At time P2, the cascade input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all high. The first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. Through the coupling effect of the second capacitor C2, the first node Q1 and the second node Q2 remain low, turning on the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13. The first clock signal CKA causes the control node QB to be high, turning off the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15. The cascade output signal terminal then outputs the high-level second clock signal CKB. The low-level power supply voltage VGL causes the third node Q3 and the fourth node Q4 to remain low, turning on the fourteenth transistor T14 and causing the scan output signal terminal GOUT to output the high-level output clock signal GCK.

[0168] At time P3, the cascade input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all high, and the second clock signal CKB is low. The first and second transistors T1 and T2 are turned off, while the sixth and twelfth transistors T6 and T12 are turned on. The first and second nodes Q1 and Q2 remain low, and the fourth, eighth, ninth, and thirteenth transistors T4 and T8, respectively, are turned on, causing the cascade output signal terminal to output the low-level second clock signal CKB. The control node QB remains high, and the third, fifth, tenth, and fifteenth transistors T3, T5, and T10 are turned off. The low-level power supply voltage VGL causes the third and fourth nodes Q3 and Q4 to remain low, turning on the fourteenth transistor T14 and causing the scan output signal terminal GOUT to continue outputting the high-level output clock signal GCK.

[0169] At time P4, the cascade input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all high, turning off the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12. The first node Q1 and the second node Q2 remain low, turning on the fourth transistor T4, the eighth transistor T8, the ninth transistor T9, and the thirteenth transistor T13, causing the cascade output signal terminal to output the high-level second clock signal CKB. The first clock signal CKA causes the control node QB to remain high, turning off the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15. The low-level power supply voltage VGL causes the third node Q3 and the fourth node Q4 to remain low, turning on the fourteenth transistor T14, and causing the scan output signal terminal GOUT to continue outputting the high-level output clock signal GCK.

[0170] At time P5, the cascade input signal CRIN and the second clock signal CKB are both at a high level, and the first clock signal CKA and the output clock signal GCK are both at a low level, then the first transistor T1, the second transistor T2, the seventh transistor T7 and the eleventh transistor T11 are turned on, the low-level power supply voltage VGL causes the control node QB to be at a low level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10 and the fifteenth transistor T15 are turned on, and at the same time, the cascade input signal CRIN causes the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned off, so that the cascade output signal terminal outputs a high level of the high-level power supply voltage VGH; since the first node Q1 and the second node Q2 are at a high level, the thirteenth transistor T13 is turned off; the fourth node Q4 is at a low level, then the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT outputs the low level of the output clock signal GCK.

[0171] Thus, in the adjacent two-stage shift register SR, since the output clock signal GCK is turned on in advance at the P1 time of the upper stage shift register SR, the cascade input signal CRIN of the lower stage shift register SR is inputted with a low level at the P3 time, so that the lower stage shift register SR is also started, and the scan output signal terminal GOUT (GOUT shown in FIG10 ) of the upper stage shift register SR is turned on in advance. <n>) and the scan output signal terminal GOUT (G shown in FIG. 10 ) of the next stage shift register SR<N+1> ) The waveforms outputted have obvious overlap, so as to offset the influence of the rising edges of the scanning signals of the two adjacent sub-pixel rows outputted, thereby improving the display quality of the display panel PNL.

[0172] In a second example, as shown in FIG11 , the shift register SR includes first to twelfth transistors T1 to T12, a fourteenth transistor T14, a fifteenth transistor T15, and a seventeenth transistor T17. A first electrode of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second electrode of the first transistor T1, a first electrode of the fourth transistor T4, a control terminal of the fifth transistor T5, a first electrode plate of the first capacitor C1, a control terminal of the third transistor T3, a control terminal of the tenth transistor T10, a first electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a control node QB are electrically connected to one another, and the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to cause the second power supply voltage V2 to be applied to the control node QB in response to a gate level of the first clock signal CKA. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal. A second electrode of the second transistor T2, the control terminal of the fourth transistor T4, the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. A first electrode of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. A second electrode of the third transistor T3, the second electrode plate of the second capacitor C2, the second electrode of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to the gate level of the control node QB. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to the gate level of the first node Q1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6. The fifth transistor T5 is configured to apply the first power supply voltage V1 to the first electrode of the sixth transistor T6 in response to the gate level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to apply the voltage of the first electrode of the sixth transistor T6 to the first node Q1 in response to the gate level of the second clock signal CKB. The second electrode of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to apply the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to apply the voltage of the second clock signal CKB to the cascade output signal terminal in response to the gate level of the second node Q2. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. A second electrode of the ninth transistor T9 is electrically connected to the third node Q3. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to the gate level of the first node Q1. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal. A second electrode of the tenth transistor T10 is electrically connected to the first electrode of the seventeenth transistor T17. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the first electrode of the seventeenth transistor T17 in response to the gate level of the control node QB. The second electrode of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, apply the voltage of the control node QB to the control terminal of the fifteenth transistor T15. The first electrode of the twelfth transistor T12, the second electrode of the seventeenth transistor T17, and the third node Q3 are electrically connected to each other. The second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second power supply voltage terminal. The twelfth transistor T12 is configured to, in response to the second power supply voltage V2, apply the voltage of the third node Q3 to the fourth node Q4. A first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. A second electrode of the fourteenth transistor T14, a second electrode plate of the third capacitor C3, a second electrode of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the gate level of the fourth node Q4. A first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the gate level of the control node QB. The second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal. A control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal. The seventeenth transistor T17 is configured to load the voltage of the second electrode of the tenth transistor T10 to the third node Q3 in response to the gate level of the second clock signal CKB.

[0173] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The active level of the output clock signal GCK is high.

[0174] In this way, the ninth transistor T9 and the tenth transistor T10 are separated by the seventeenth transistor T17. Since the control terminal of the seventeenth transistor T17 is electrically connected to the second clock signal terminal, the seventeenth transistor T17 is intermittently turned on, thereby avoiding the situation where the third node Q3 and the fourth node Q4 are abnormally set when the first clock signal CKA is at a low level.

[0175] In a third example, as shown in FIG12 , the shift register SR includes first to twelfth transistors T1 to T12, a fourteenth transistor T14, and a fifteenth transistor T15. A first electrode of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second electrode of the first transistor T1, a first electrode of the fourth transistor T4, a control terminal of the fifth transistor T5, a first electrode plate of the first capacitor C1, a control terminal of the third transistor T3, a control terminal of the tenth transistor T10, a first electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a control node QB are electrically connected to one another, and the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to cause the second power supply voltage V2 to be applied to the control node QB in response to a gating level of the first clock signal CKA. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal. A second electrode of the second transistor T2, the control terminal of the fourth transistor T4, the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. A first electrode of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. A second electrode of the third transistor T3, the second electrode plate of the second capacitor C2, the second electrode of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to the gate level of the control node QB. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to the gate level of the first node Q1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6. The fifth transistor T5 is configured to apply the first power supply voltage V1 to the first electrode of the sixth transistor T6 in response to the gate level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to apply the voltage of the first electrode of the sixth transistor T6 to the first node Q1 in response to the gate level of the second clock signal CKB. The second electrode of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to apply the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to apply the voltage of the second clock signal CKB to the cascade output signal terminal in response to the gate level of the second node Q2. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. A second electrode of the ninth transistor T9, a second electrode of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to the gate level of the first node Q1. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the third node Q3 in response to the gate level of the control node QB. The second electrode of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, apply the voltage of the control node QB to the control terminal of the fifteenth transistor T15. The first electrode of the twelfth transistor T12 is electrically connected to the third node Q3. The second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, and the fourth node Q4 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to, in response to the gate level of the second clock signal CKB, apply the voltage of the third node Q3 to the fourth node Q4. A first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. A second electrode of the fourteenth transistor T14, a second electrode plate of the third capacitor C3, a second electrode of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to output the voltage of the output clock signal GCK to the scan output signal terminal GOUT in response to the gate level of the fourth node Q4. A first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to output the second power supply voltage V2 to the scan output signal terminal GOUT in response to the gate level of the control node QB. The second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0176] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The active level of the output clock signal GCK is high.

[0177] Figure 13 is a driving timing diagram for the shift register SR shown in Figure 12 . The clock cycles of the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all the same. The duration of the select level of the first clock signal CKA is 1 / 4 of a clock cycle. The duration of the select level of the second clock signal CKB is 1 / 4 of a clock cycle. The duration of the active level of the output clock signal GCK is 3 / 4 of a clock cycle. The select level of the first clock signal CKA precedes the select level of the second clock signal CKB by 1 / 2 of a clock cycle, and the select levels of the first clock signal CKA and the second clock signal CKB have the same duration. The active level of the output clock signal GCK precedes the select level of the second clock signal CKB by 1 / 4 of a clock cycle.

[0178] The working principle of the shift register SR shown in FIG12 will be described below with reference to FIG13 .

[0179] 12 and 13 , at time P1, the cascade input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all at a low level, and the second clock signal CKB is at a high level, then the first transistor T1, the second transistor T2, the seventh transistor T7, and the eleventh transistor T11 are turned on, and the twelfth transistor T12 is turned off; the fourth node Q4 is at a high level, so that the fourteenth transistor T14 is turned off; the low-level power supply voltage VGL causes the control node QB to be at a low level, then the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15 are turned on, and at the same time, the cascade input signal CRIN causes the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 to be turned on, so that the cascade output signal terminal outputs a high level of the second clock signal CKB; since the fifteenth transistor T15 is turned on, the scan output signal terminal GOUT outputs a low level of the low-level power supply voltage VGL.

[0180] At time P2, the cascade input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all high. The first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12 are turned off. Through the coupling effect of the second capacitor C2, the first node Q1 and the second node Q2 remain low, turning on the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9. The first clock signal CKA causes the control node QB to be high, turning off the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15. The cascade output signal terminal then outputs the high level of the second clock signal CKB. Through the coupling effect of the third capacitor C3, the fourth node Q4 is low, turning on the fourteenth transistor T14, and the scan output signal terminal GOUT outputs the high level of the output clock signal GCK.

[0181] At time P3, the cascade input signal CRIN, the first clock signal CKA, and the output clock signal GCK are all high, and the second clock signal CKB is low. The first and second transistors T1 and T2 are turned off, while the sixth and twelfth transistors T6 and T12 are turned on. The first and second nodes Q1 and Q2 remain low, and the fourth, eighth, and ninth transistors T4 and T8 are turned on, causing the cascade output signal terminal to output the low-level second clock signal CKB. The control node QB remains high, and the third, fifth, tenth, and fifteenth transistors T3 and T5 are turned off. The low-level power supply voltage VGL causes the third and fourth nodes Q3 and Q4 to remain low, turning on the fourteenth transistor T14 and causing the scan output signal terminal GOUT to continue outputting the high-level output clock signal GCK.

[0182] At time P4, the cascade input signal CRIN, the first clock signal CKA, the second clock signal CKB, and the output clock signal GCK are all high, turning off the first transistor T1, the second transistor T2, the sixth transistor T6, and the twelfth transistor T12. The first node Q1 and the second node Q2 remain low, and the fourth transistor T4, the eighth transistor T8, and the ninth transistor T9 are turned on, causing the cascade output signal terminal to output the high-level second clock signal CKB. The first clock signal CKA causes the control node QB to remain high, turning off the third transistor T3, the fifth transistor T5, the tenth transistor T10, and the fifteenth transistor T15. The low-level power supply voltage VGL causes the third node Q3 to remain low, and due to the coupling effect of the third capacitor C3, the fourteenth transistor T14 is turned on, causing the scan output signal terminal GOUT to output the high-level output clock signal GCK.

[0183] At time P5, the cascade input signal CRIN and the second clock signal CKB are both high, and the first clock signal CKA and the output clock signal GCK are both low, then the first transistor T1, the second transistor T2, the seventh transistor T7 and the eleventh transistor T11 are turned on, and the twelfth transistor T12 is turned off; the low-level power supply voltage VGL causes the control node QB to be low, then the third transistor T3, the fifth transistor T5, the tenth transistor T10 and the fifteenth transistor T15 are turned on, and at the same time, the cascade input signal CRIN causes the fourth transistor T4, the eighth transistor T8 and the ninth transistor T9 to be turned off, so that the cascade output signal terminal outputs a high level of the high-level power supply voltage VGH; the fourth node Q4 is low, then the fourteenth transistor T14 is turned on, and the scan output signal terminal GOUT outputs a low level of the output clock signal GCK.

[0184] In this way, the switch of the twelfth transistor T12 is controlled by the second clock signal CKB, and at time P1, the abnormal setting of the fourth node Q4 caused by the low level of the first clock signal CKA can be prevented.

[0185] In a fourth example, as shown in FIG14 , the shift register SR includes first to fifteenth transistors T1 to T15. A first electrode of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second electrode of the first transistor T1, a first electrode of the fourth transistor T4, a control terminal of the fifth transistor T5, a first electrode plate of the first capacitor C1, a control terminal of the third transistor T3, a control terminal of the tenth transistor T10, a first electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a control node QB are electrically connected to one another, and the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to cause the second power supply voltage V2 to be applied to the control node QB in response to a gating level of the first clock signal CKA. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal. A second electrode of the second transistor T2, the control terminal of the fourth transistor T4, the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. A first electrode of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. A second electrode of the third transistor T3, the second electrode plate of the second capacitor C2, the second electrode of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to the gate level of the control node QB. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to the gate level of the first node Q1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6. The fifth transistor T5 is configured to apply the first power supply voltage V1 to the first electrode of the sixth transistor T6 in response to the gate level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to apply the voltage of the first electrode of the sixth transistor T6 to the first node Q1 in response to the gate level of the second clock signal CKB. The second electrode of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to apply the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to apply the voltage of the second clock signal CKB to the cascade output signal terminal in response to the gate level of the second node Q2. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. A second electrode of the ninth transistor T9, a second electrode of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to the gate level of the first node Q1. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the third node Q3 in response to the gate level of the control node QB. The second electrode of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, apply the voltage of the control node QB to the control terminal of the fifteenth transistor T15. The first electrode of the twelfth transistor T12, the first electrode of the thirteenth transistor T13, and the third node Q3 are electrically connected to each other. The second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, the fourth node Q4, and the second electrode of the thirteenth transistor T13 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to, in response to the gate level of the second clock signal CKB, apply the voltage of the third node Q3 to the fourth node Q4. The control terminal of the thirteenth transistor T13 is electrically connected to the cascade input signal terminal. The thirteenth transistor T13 is configured to, in response to the gate level of the cascade input signal CRIN, load the voltage of the third node Q3 to the fourth node Q4. The first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second electrode of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to, in response to the gate level of the fourth node Q4, output the voltage of the output clock signal GCK to the scan output signal terminal GOUT. The first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to, in response to the gate level of the control node QB, output the second power supply voltage V2 to the scan output signal terminal GOUT. The second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.

[0186] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The active level of the output clock signal GCK is high.

[0187] In this way, by multiplexing the cascade input signal CRIN at the control terminal of the thirteenth transistor T13 , a narrow frame of the display panel PNL is achieved.

[0188] In a fifth example, as shown in FIG15 , the shift register SR includes first to sixteenth transistors T1 to T16. A first electrode of the first transistor T1 is electrically connected to the second power supply voltage terminal, a second electrode of the first transistor T1, a first electrode of the fourth transistor T4, a control terminal of the fifth transistor T5, a first electrode plate of the first capacitor C1, a control terminal of the third transistor T3, a control terminal of the tenth transistor T10, a first electrode of the eleventh transistor T11, a control terminal of the fifteenth transistor T15, and a control node QB are electrically connected to one another, and the control terminal of the first transistor T1 is electrically connected to the first clock signal terminal. The first transistor T1 is configured to apply the second power supply voltage V2 to the control node QB in response to a gating level of the first clock signal CKA. A first electrode of the second transistor T2 is electrically connected to the cascade input signal terminal. A second electrode of the second transistor T2, the control terminal of the fourth transistor T4, the second electrode of the sixth transistor T6, the first electrode of the seventh transistor T7, and the first node Q1 are electrically connected to each other. The control terminal of the second transistor T2 is electrically connected to the first clock signal terminal. The second transistor T2 is configured to apply the voltage of the cascade input signal CRIN to the first node Q1 in response to the gate level of the first clock signal CKA. A first electrode of the third transistor T3, the first electrode plate of the first capacitor C1, and the first power supply voltage terminal are electrically connected to each other. A second electrode of the third transistor T3, the second electrode plate of the second capacitor C2, the second electrode of the eighth transistor T8, and the cascade output signal terminal are electrically connected to each other. The third transistor T3 is configured to apply the first power supply voltage V1 to the cascade output signal terminal in response to the gate level of the control node QB. A first electrode of the fourth transistor T4 is electrically connected to the first clock signal terminal. The fourth transistor T4 is configured to apply the voltage of the first clock signal CKA to the control node QB in response to the gate level of the first node Q1. A first electrode of the fifth transistor T5 is electrically connected to the first power supply voltage terminal, and a second electrode of the fifth transistor T5 is electrically connected to the first electrode of the sixth transistor T6. The fifth transistor T5 is configured to apply the first power supply voltage V1 to the first electrode of the sixth transistor T6 in response to the gate level of the control node QB. The control terminal of the sixth transistor T6 is electrically connected to the second clock signal terminal. The sixth transistor T6 is configured to apply the voltage of the first electrode of the sixth transistor T6 to the first node Q1 in response to the gate level of the second clock signal CKB. The second electrode of the seventh transistor T7, the control terminal of the eighth transistor T8, the first electrode plate of the second capacitor C2, the control terminal of the ninth transistor T9, and the second node Q2 are electrically connected to each other. The control terminal of the seventh transistor T7 is electrically connected to the second power supply voltage terminal. The seventh transistor T7 is configured to apply the voltage of the first node Q1 to the second node Q2 in response to the second power supply voltage V2.A first electrode of the eighth transistor T8 is electrically connected to the second clock signal terminal. The eighth transistor T8 is configured to apply the voltage of the second clock signal CKB to the cascade output signal terminal in response to the gate level of the second node Q2. A first electrode of the ninth transistor T9 is electrically connected to the second power supply voltage terminal. A second electrode of the ninth transistor T9, a second electrode of the tenth transistor T10, and the third node Q3 are electrically connected to each other. The ninth transistor T9 is configured to apply the second power supply voltage V2 to the third node Q3 in response to the gate level of the first node Q1. A first electrode of the tenth transistor T10 is electrically connected to the first clock signal terminal. The tenth transistor T10 is configured to apply the voltage of the first clock signal CKA to the third node Q3 in response to the gate level of the control node QB. The second electrode of the eleventh transistor T11, the control terminal of the fifteenth transistor T15, and the second electrode plate of the fourth capacitor C4 are electrically connected to each other. The control terminal of the eleventh transistor T11 is electrically connected to the second power supply voltage terminal. The eleventh transistor T11 is configured to, in response to the second power supply voltage V2, apply the voltage of the control node QB to the control terminal of the fifteenth transistor T15. The first electrode of the twelfth transistor T12, the first electrode of the thirteenth transistor T13, and the third node Q3 are electrically connected to each other. The second electrode of the twelfth transistor T12, the control terminal of the fourteenth transistor T14, the first electrode plate of the third capacitor C3, the fourth node Q4, and the second electrode of the thirteenth transistor T13 are electrically connected to each other. The control terminal of the twelfth transistor T12 is electrically connected to the second clock signal terminal. The twelfth transistor T12 is configured to, in response to the gate level of the second clock signal CKB, apply the voltage of the third node Q3 to the fourth node Q4. The control terminal of the thirteenth transistor T13 is electrically connected to the cascade input signal terminal. The thirteenth transistor T13 is configured to, in response to the gate level of the cascade input signal CRIN, load the voltage of the third node Q3 to the fourth node Q4. The first electrode of the fourteenth transistor T14 is electrically connected to the output clock signal terminal. The second electrode of the fourteenth transistor T14, the second electrode plate of the third capacitor C3, the second electrode of the fifteenth transistor T15, and the scan output signal terminal GOUT are electrically connected to each other. The fourteenth transistor T14 is configured to, in response to the gate level of the fourth node Q4, output the voltage of the output clock signal GCK to the scan output signal terminal GOUT. The first electrode of the fifteenth transistor T15 is electrically connected to the second power supply voltage terminal. The fifteenth transistor T15 is configured to, in response to the gate level of the control node QB, output the second power supply voltage V2 to the scan output signal terminal GOUT. The second electrode plate of the fourth capacitor C4 is electrically connected to the first clock signal terminal.The first electrode of the sixteenth transistor T16, the control end of the sixteenth transistor T16 and the first clock signal end are electrically connected to each other, the second electrode of the sixteenth transistor T16 is electrically connected to the first electrode plate of the fourth capacitor C4, and the sixteenth transistor T16 is configured to respond to the selection level of the first clock signal CKA and load the voltage of the first clock signal CKA onto the first electrode plate of the fourth capacitor C4.

[0189] It should be noted that in this example, each transistor is a P-type transistor. The gating level of each signal is low. The first power supply voltage V1 is a high-level power supply voltage VGH, and the second power supply voltage V2 is a low-level power supply voltage VGL. The active level of the output clock signal GCK is high.

[0190] In this way, by providing the sixteenth transistor T16 between the fourth capacitor C4 and the first clock signal terminal, since the sixteenth transistor T16 is turned on only under the control of the gate level of the first clock signal CKA and is turned off under the control of the cut-off level of the first clock signal CKA, continuous charging or discharging of the fourth capacitor C4 can be avoided, thereby reducing the power consumption of the system.

[0191] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.< / n>

Claims

1. A shift register, wherein: The shift register includes an input circuit, a cascade output circuit, a control circuit, and a scan output circuit; The input circuit is used to control the levels of the first node and the control node under the control of the first clock signal and the cascade output signal of the previous stage cascade output circuit; The cascade output circuit is used to output a cascade output signal under the control of the first node, the control node and the second clock signal; The control circuit is used to control the level of the fourth node under the control of the first node, the control node, and the first clock signal; The scan output circuit is used to output a scan signal under the control of the control node, the fourth node, and the output clock signal; The effective level duration of the cascade output signal output by the cascade output circuit is shorter than the effective level duration of the scan signal output by the scan output circuit.

2. The shift register according to claim 1, wherein: The cascade output circuit includes a first cascade output sub-circuit and a second cascade output sub-circuit; The first electrode of the first cascade output sub-circuit is electrically connected to the first power supply voltage terminal, the second electrode is electrically connected to the cascade output signal terminal, and the control terminal is electrically connected to the control node. The first cascade output sub-circuit is configured to apply the first power supply voltage to the cascade output signal terminal in response to a strobe level of the control node; The first pole of the second cascade output sub-circuit is electrically connected to the second clock signal terminal, the second pole of the second cascade output sub-circuit is electrically connected to the cascade output signal terminal, the control terminal of the second cascade output sub-circuit is electrically connected to the first node, and the second cascade output sub-circuit is configured to load the voltage of the second clock signal to the cascade output signal terminal in response to the selection level of the first node.

3. The shift register according to claim 1, wherein: The scan output circuit includes a first scan output sub-circuit and a second scan output sub-circuit; The first scan output sub-circuit has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the scan output signal terminal, and a control terminal electrically connected to a control node, and the first scan output sub-circuit is configured to output the second power supply voltage to the scan output signal terminal in response to a strobe level of the control node; The first electrode of the second scan output sub-circuit is electrically connected to the output clock signal terminal, the second electrode is electrically connected to the scan output signal terminal, and the control terminal is electrically connected to the fourth node. The second scan output sub-circuit is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

4. The shift register according to claim 1, wherein: The input circuit includes a cascade input subcircuit, a first subcircuit, and a second subcircuit; The first terminal of the cascade input subcircuit is electrically connected to the cascade input signal terminal, the second terminal of the cascade input subcircuit is electrically connected to the first node, and the control terminal of the cascade input subcircuit is electrically connected to the first clock signal terminal. The cascade input subcircuit is configured to, in response to a gating level of the first clock signal, cause a voltage of the cascade input signal to be applied to the first node. The first sub-circuit is electrically connected to the second power supply voltage terminal, the second sub-circuit is electrically connected to the control node, and the control terminal is electrically connected to the first clock signal terminal. The first sub-circuit is configured to apply the second power supply voltage to the control node in response to a gating level of the first clock signal. The first pole of the second sub-circuit is electrically connected to the first clock signal terminal, the second pole is electrically connected to the control node, and the control terminal is electrically connected to the first node. The second sub-circuit is configured to load the voltage of the first clock signal to the control node in response to the selection level of the first node.

5. The shift register according to claim 1, wherein: The control circuit includes a third sub-circuit, a fourth sub-circuit and a fifth sub-circuit; The third sub-circuit has a first terminal electrically connected to the first clock signal terminal, a second terminal electrically connected to a third node, and a control terminal electrically connected to the control node. The third sub-circuit is configured to, in response to a gating level of the control node, load a voltage of the first clock signal to the third node. The fourth sub-circuit has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the first node, and is configured to, in response to a gating level of the first node, cause the second power supply voltage to be applied to the third node; The first electrode of the fifth sub-circuit is electrically connected to the third node, the second electrode is electrically connected to the fourth node, and the control end is electrically connected to any one of the second clock signal end and the second power supply voltage end. The fifth sub-circuit is configured to load the voltage of the third node to the fourth node in response to the selection level of the second clock signal or the second power supply voltage. The shift register according to claim 2 , wherein: The first cascade output sub-circuit includes a third transistor and a first capacitor; A first electrode of the third transistor, a first electrode plate of the first capacitor, and the first power supply voltage terminal are electrically connected, a second electrode of the third transistor is electrically connected to the cascade output signal terminal, a control terminal of the third transistor, a second electrode plate of the first capacitor, and the control node are electrically connected, and the third transistor is configured to cause the first power supply voltage to be applied to the cascade output signal terminal in response to a gating level of the control node; The second cascade output sub-circuit includes an eighth transistor and a second capacitor; The first electrode of the eighth transistor is electrically connected to the second clock signal terminal, the second electrode of the eighth transistor, the second electrode plate of the second capacitor and the cascade output signal terminal are electrically connected to each other, the control terminal of the eighth transistor, the first electrode plate of the second capacitor and the second node are electrically connected to each other, and the eighth transistor is configured to respond to the selection level of the second node so that the voltage of the second clock signal is loaded to the cascade output signal terminal.

7. The shift register according to claim 3, wherein: The first scan output sub-circuit includes a fifteenth transistor and a fourth capacitor; The first electrode of the fifteenth transistor is electrically connected to the second power supply voltage terminal, and the second electrode is electrically connected to the scan output signal terminal. The control terminal of the fifteenth transistor, the first electrode plate of the fourth capacitor, and the control node are electrically connected to each other. The fifteenth transistor is configured to output the second power supply voltage to the scan output signal terminal in response to a gating level of the control node. The second electrode plate of the fourth capacitor is electrically connected to the first clock signal terminal. The second scan output sub-circuit includes a fourteenth transistor and a third capacitor; The first electrode of the fourteenth transistor is electrically connected to the output clock signal terminal, and the second electrode is electrically connected to the scan output signal terminal. The control terminal of the fourteenth transistor, the first electrode plate of the third capacitor, and the fourth node are electrically connected to each other. The fourteenth transistor is configured to output the voltage of the output clock signal to the scan output signal terminal in response to the selection level of the fourth node.

8. The shift register according to claim 4, wherein: The cascade input subcircuit includes a second transistor; The second transistor has a first electrode electrically connected to the cascade input signal terminal, a second electrode electrically connected to the first node, and a control terminal electrically connected to the first clock signal terminal, and the second transistor is configured to, in response to a gating level of the first clock signal, load a voltage of the cascade input signal to the first node; The first sub-circuit includes a first transistor; The first transistor has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the control node, and a control terminal electrically connected to the first clock signal terminal, and the first transistor is configured to load the second power supply voltage to the control node in response to a gating level of the first clock signal; The second sub-circuit includes a fourth transistor; The first electrode of the fourth transistor is electrically connected to the first clock signal terminal, the second electrode is electrically connected to the control node, and the control terminal is electrically connected to the first node. The fourth transistor is configured to respond to the selection level of the first node so that the voltage of the first clock signal is loaded to the control node.

9. The shift register according to claim 5, wherein: The third sub-circuit includes a tenth transistor; The tenth transistor has a first electrode electrically connected to the first clock signal terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the control node, and the tenth transistor is configured to, in response to a gating level of the control node, load the voltage of the first clock signal to the third node; The fourth sub-circuit includes a ninth transistor; The ninth transistor has a first electrode electrically connected to the second power supply voltage terminal, a second electrode electrically connected to the third node, and a control terminal electrically connected to the first node, and the ninth transistor is configured to, in response to a gating level of the first node, load the second power supply voltage to the third node; The fifth sub-circuit includes a twelfth transistor; The first electrode of the twelfth transistor is electrically connected to the third node, the second electrode of the twelfth transistor is electrically connected to the fourth node, the control terminal of the twelfth transistor is electrically connected to any one of the second clock signal terminal and the second power supply voltage terminal, and the twelfth transistor is configured to respond to the selection level of the second clock signal or the second power supply voltage so that the voltage of the third node is loaded to the fourth node.

10. The shift register according to claim 7, wherein: The shift register further includes a sixteenth transistor; The first electrode of the sixteenth transistor, the control end of the sixteenth transistor and the first clock signal end are electrically connected to each other, the second electrode of the sixteenth transistor is electrically connected to the first electrode plate of the fourth capacitor, and the sixteenth transistor is configured to respond to the selection level of the first clock signal so that the voltage of the first clock signal is loaded onto the first electrode plate of the fourth capacitor.

11. The shift register according to claim 9, wherein: The control circuit further includes a thirteenth transistor; The first electrode of the thirteenth transistor is electrically connected to the third node, the second electrode of the thirteenth transistor is electrically connected to the fourth node, the control end of the thirteenth transistor is electrically connected to any one of the first node, the second node, and the cascade input signal end, and the thirteenth transistor is configured to respond to the selection level of the first node or the second node or the cascade input signal so that the voltage of the third node is loaded to the fourth node.

12. The shift register according to claim 9, wherein: The shift register further includes a seventeenth transistor; The first electrode of the seventeenth transistor is electrically connected to the second electrode of the tenth transistor, the second electrode of the seventeenth transistor is electrically connected to the third node, the control terminal of the seventeenth transistor is electrically connected to the second clock signal terminal, and the seventeenth transistor is configured to respond to the selection level of the second clock signal so that the voltage of the second electrode of the tenth transistor is loaded to the third node.

13. The shift register according to any one of claims 1 to 12, wherein: The shift register further includes a fifth transistor, a sixth transistor, and a seventh transistor; A first electrode of the fifth transistor is electrically connected to a first power supply voltage terminal, a second electrode of the fifth transistor is electrically connected to a first electrode of the sixth transistor, a control terminal of the fifth transistor is electrically connected to the control node, and the fifth transistor is configured to, in response to a gating level of the control node, cause the first power supply voltage to be applied to the first electrode of the sixth transistor; The second electrode of the sixth transistor, the second electrode of the second transistor, the first electrode of the seventh transistor, and the first node are electrically connected to each other, the control terminal of the sixth transistor is electrically connected to the second clock signal terminal, and the sixth transistor is configured to, in response to a gating level of the second clock signal, load a voltage of the first electrode of the sixth transistor to the first node; The second electrode of the seventh transistor is electrically connected to the second node, the control terminal of the seventh transistor is electrically connected to the second power supply voltage terminal, and the seventh transistor is configured to load the voltage of the first node to the second node in response to the second power supply voltage; The clock period of the first clock signal, the clock period of the second clock signal and the clock period of the output clock signal are all the same; The duration of the gating level of the first clock signal does not exceed 1 / 4 of a clock cycle; The duration of the gating level of the second clock signal does not exceed 1 / 4 of a clock cycle; The effective level of the output clock signal lasts for a period greater than 1 / 2 of a clock cycle; The gating level of the first clock signal is earlier than the gating level of the second clock signal by 1 / 2 clock cycle; The effective level of the output clock signal is earlier than the selection level of the second clock signal by 1 / 4 clock cycle.

14. A gate drive circuit, comprising a plurality of shift registers according to any one of claims 1 to 13 connected in cascade sequence; wherein: The cascade output signal terminal of the shift register at the previous stage is electrically connected to the cascade input signal terminal of the shift register at the next stage.

15. A display panel comprising a gate drive circuit and a first control line, a second control line and a third control line for driving the gate drive circuit; The gate drive circuit comprises a plurality of shift registers according to any one of claims 1 to 13 that are cascaded in sequence; the cascade output signal terminal of the shift register of the previous stage is electrically connected to the cascade input signal terminal of the shift register of the next stage; The first control line is electrically connected to the first clock signal terminal of the odd-numbered shift register, and is electrically connected to the second clock signal terminal of the even-numbered shift register; The second control line is electrically connected to the second clock signal terminal of the odd-numbered shift register, and is electrically connected to the first clock signal terminal of the even-numbered shift register; The third control trace is electrically connected to the output clock signal terminal of the shift register.

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