Data processing method, storage device, computer-readable storage medium and computer program product

Abstract

Disclosed in embodiments of the present disclosure are a data processing method, a storage device, a computer-readable storage medium, and a computer program product. The storage device further comprises a storage module. The data processing method comprises: in response to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between a storage module and a control module to perform a read operation and a write operation, and controlling a second path connected between the storage module and the control module to perform a read operation. Therefore, a two-read one-write function can be realized by means of the storage device, so that the area occupied by the storage device is reduced while high performance and the two-read one-write function are ensured, thereby reducing device costs.

Description

Data processing method, storage device, computer-readable storage medium, and computer program product

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] The embodiments of the present disclosure are based on and claim the priority of Chinese patent application with application number 202410384638.3, application date March 29, 2024, and application name “Data processing method, storage device, storage medium and computer program product”. The entire content of the Chinese patent application is hereby introduced into the present disclosure as a reference. Technical Field

[0003] The present disclosure relates to, but is not limited to, the field of communication technology, and in particular to a data processing method, a storage device, a computer-readable storage medium, and a computer program product. Background Art

[0004] Memory is an electronic device used to store programs and data. It is composed of multiple memory modules. The circuit structure of the memory module determines the read and write performance of the memory.

[0005] Memories such as static random access memory (SRAM) have read and write functions on a single port, but the port can only perform read operations or only perform write operations. Read and write operations cannot be performed simultaneously, resulting in low read and write performance. Summary of the Invention

[0006] In view of this, embodiments of the present disclosure provide at least one data processing method, storage device, computer-readable storage medium, and computer program product. Thus, a storage device can implement two-read-one-write functionality, thereby reducing the area occupied by the storage device and lowering device costs while maintaining high performance and two-read-one-write functionality.

[0007] The technical solution of the embodiment of the present disclosure is implemented as follows:

[0008] On the one hand, an embodiment of the present disclosure provides a data processing method applied to a control module in a storage device, wherein the storage device also includes a storage module. The data processing method includes: responding to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between the storage module and the control module to perform a read operation and a write operation, and at the same time controlling a second path connected between the storage module and the control module to perform a read operation.

[0009] On the other hand, an embodiment of the present disclosure provides a storage device, comprising: a storage module and a control module, wherein the storage module is composed of multiple eight-tube storage units; a first path and a second path are connected between the control module and the storage module; the control module is configured to perform read operations and write operations through the first path, and perform read operations through the second path, thereby realizing two reads and one write of data on the storage module.

[0010] On the other hand, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, which implements part or all of the steps in the above method when executed by a processor.

[0011] On the other hand, an embodiment of the present disclosure provides a computer program, including computer-readable codes. When the computer-readable codes are executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0012] On the other hand, an embodiment of the present disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, implements some or all of the steps in the above method.

[0013] In the disclosed embodiment, a first path having both read and write functions and a second path having a read function are constructed between the control module and the storage module. In this way, the control module can control the first path to implement one read operation and one write operation, and control the second path to implement one read operation, so that the storage device has two read and one write functions. While ensuring high performance and two read and one write functions, the area occupied by the storage device is reduced, thereby reducing the overall area of ​​the SRAM made based on the storage device, thereby reducing the chip cost.

[0014] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and are not intended to limit the technical solutions of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings herein are incorporated into and constitute a part of the specification. These drawings illustrate embodiments consistent with the present disclosure and, together with the specification, are used to explain the technical solutions of the present disclosure.

[0016] FIG1 is a schematic diagram of a structure of a storage device according to an embodiment of the present disclosure;

[0017] FIG2 is a schematic diagram of the composition structure of an eight-transistor storage unit in a storage device provided by an embodiment of the present disclosure;

[0018] FIG3 is a second schematic diagram of the composition structure of a storage device provided by an embodiment of the present disclosure;

[0019] FIG4 is a first schematic diagram of an implementation flow of a data processing method provided by an embodiment of the present disclosure;

[0020] FIG5 is a second schematic diagram of an implementation flow of a data processing method provided by an embodiment of the present disclosure;

[0021] FIG6 is a schematic diagram of a timing diagram of a write port and a read port operating simultaneously according to an embodiment of the present disclosure;

[0022] FIG7 is a schematic diagram of the working timing of a read port provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further elaborated in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limiting the present disclosure. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0024] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0025] The terms "first / second / third" involved are merely used to distinguish similar objects and do not represent a specific ordering of the objects. It is understandable that "first / second / third" can be interchanged with a specific order or sequence where permitted so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which the present disclosure pertains. The terms used herein are for the purpose of describing the present disclosure only and are not intended to limit the present disclosure.

[0027] In order to better understand the data processing method provided by the embodiments of the present disclosure, the solutions in the related art are first described below.

[0028] With the development of Moore's Law and the continuous advancement of integrated circuit technology, chips have placed higher requirements on the functions of various memories. To meet these demands, the circuit design of memories is also constantly evolving.

[0029] The earliest static memory circuit used a six-tube storage module, which was divided into high-performance single-port SRAM and high-density single-port SRAM according to requirements such as read and write performance and the physical area occupied.

[0030] High-performance single-port SRAM uses a storage module with a size ratio of 2:2:1 between the transmission tube, the pull-down N-type metal-oxide-semiconductor field-effect transistor (NMOS tube), and the pull-up NMOS tube. It has high read and write speeds and can meet the high-speed data processing requirements.

[0031] High-density single-port SRAM and high-performance single-port SRAM have the same functions. The difference is that high-density single-port SRAM uses a high-density 6-transistor bit cell (bit cell). It usually uses a storage module with a 1:1:1 ratio between the transmission transistor, pull-down NMOS transistor, and pull-up NMOS transistor. This design reduces the storage module area, but the disadvantage is that the read current is reduced and the performance is also degraded. This type of SRAM has a single-port read and write function. This port can only perform read operations or only write operations, not read and write operations simultaneously.

[0032] To this end, the present disclosure hopes to achieve the two-read and one-write functions based on a memory module with fewer transistors through a special design of peripheral circuits.

[0033] The present disclosure provides a storage device 10. As shown in FIG1 , the storage device 10 includes a storage module 12 and a control module 11. A first path 13 and a second path 14 are connected between the control module 11 and the storage module 12. The control module 11 is configured to perform read and write operations via the first path 13 and read via the second path 14, thereby implementing two reads and one write for data in the storage module 12.

[0034] The storage device 10 is used to store various types of data. The data that can be stored in the storage device 10 may include, but is not limited to, programs, code, and files. In one feasible implementation, the storage device 10 can be implemented as a storage device such as a hard disk, solid-state drive, mobile hard disk, USB flash drive, memory card, optical disk, or cloud storage.

[0035] The memory module 12 is composed of a plurality of eight-transistor memory cells. An eight-transistor memory cell may refer to a basic memory cell composed of eight transistors. Each memory cell can store one bit (the smallest unit of information). In one possible implementation, the memory module 12 may be an array composed of a large number of eight-transistor memory cells or memory elements. Therefore, the memory module 12 may also be referred to as an eight-transistor memory cell array, or an eight-transistor memory.

[0036] The first path 13 is a path that has both read and write functions. Therefore, the first path 13 can also be called a read-write path or a shared path. The second path 14 is a path that has only read functions. Therefore, the second path 14 can also be called a read path. In this way, the storage device 10 with the first path 13 and the second path 14 can achieve two read and one write functions.

[0037] In a feasible implementation, a first path 13 having both read and write functions and a second path 14 having a read function can be constructed between the control module 11 and the storage module 12; and the control logic of the two read and one write functions is determined and compiled into the control module 11; in this way, the control module 11 controls the first path 13 to implement one read operation and one write operation, and the second path 14 to implement one read operation, thereby realizing two reads and one write.

[0038] It should be noted that existing eight-element memories can only perform one read operation and one write operation, that is, they only have one read and one write function. However, the present disclosure optimizes the circuitry and processing logic of existing eight-element memories, adding a read function without changing the occupied area. This allows the optimized eight-element memory to perform two read operations and one write operation, that is, to have two read and one write functions. In this way, while maintaining high performance and two read and one write functions, the area occupied by the memory device can be reduced, thereby reducing the overall area of ​​the SRAM manufactured based on the memory device, thereby reducing chip costs.

[0039] In the disclosed embodiment, a first path having both read and write functions and a second path having a read function are constructed between the control module and the storage module. In this way, the control module can control the first path to implement one read operation and one write operation, and control the second path to implement one read operation, so that the storage device has two read and one write functions. While ensuring high performance and two read and one write functions, the area occupied by the storage device is reduced, thereby reducing the overall area of ​​the SRAM made based on the storage device, thereby reducing the chip cost.

[0040] In some embodiments, as shown in FIG2 , an eight-transistor memory cell 120 includes a latch 121, a first path 13, and a second path 14. The first path 13 includes a first transistor MNP0 and a second transistor MNP1; and the second path 14 includes a third transistor MNDR and a fourth transistor MNPR. A first end of the first transistor MNP0, a first end of the second transistor MNP1, and a first end of the third transistor MNDR are respectively connected to the latch. A second end of the first transistor MNP0 is connected to a first port, a second end of the second transistor MNP1 is connected to a second port, a second end of the third transistor MNDR is connected to a first end of a fourth transistor MNPR, and a second end of the fourth transistor MNPR is connected to a third port.

[0041] The first transistor MNP0, the second transistor MNP1, the third transistor MNDR, the fourth transistor MNPR, and the fifth transistor may all be NMOS transistors. The first transistor MNP0 and the second transistor MNP1 are used as transmission transistors to form a first path 13 (read-write path). The third transistor MNDR and the fourth transistor MNPR are used as transmission transistors to form a second path 14 (read path). In one feasible implementation, the first transistor MNP0, the second transistor MNP1, the third transistor MNDR, and the fourth transistor MNPR may all be NMOS transistors with transmission functions.

[0042] Latch 121 is used to store data. In one feasible implementation, latch 121 may include four fifth transistors, which may include the first pull-up transistor MPU0, the second pull-up transistor MPU1, the first pull-down transistor MND0, and the second pull-down transistor MND1 shown in FIG2 . In the configuration of latch 121, the transistors act as switches, controlling the flow of current in latch 121 by turning the transistors on and off, thereby enabling signal storage and transmission.

[0043] As shown in FIG2 , the first pull-up transistor MPU0, the second pull-up transistor MPU1, the first pull-down transistor MND0, and the second pull-down transistor MND1 can be interconnected to form a latch 121. The first end of the first transistor MNP0, the first end of the second transistor MNP1, and the first end of the third transistor MNDR are respectively connected to the latch 121, the second end of the first transistor MNP0 is connected to the first port, the second end of the second transistor MNP1 is connected to the second port, the second end of the third transistor MNDR is connected to the first end of the fourth transistor MNPR, and the second end of the fourth transistor MNPR is connected to the third port.

[0044] In the above embodiment, the first transistor MNP0 and the second transistor MNP1 can form a first path 13 to read the data stored in the latch 121 and write the data into the latch 121 at the same time; the third transistor MNDR and the fourth transistor MNPR can form a second path 14 to read the data stored in the latch 121; and the four transistors can form the latch 121 to store data.

[0045] In some embodiments, as shown in FIG2 , the first path 13 includes: a read / write word line RWWL and a first bit line RWBLB, a second bit line RWBL, a first port, and a second port. The first bit line RWBLB and the second bit line RWBL are a pair of complementary bit lines. The first end of the read / write word line RWWL is connected to the control module 11, and the second end of the read / write word line RWWL is connected to the control end of the first transistor MNP0 and the control end of the second transistor MNP1, respectively. The first port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, the second port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, and the second end of the first bit line RWBLB is connected to the first end of the second bit line RWBL. The second end of the first transistor MNP0 is connected, and the second end of the second bit line RWBL is connected to the second end of the second transistor MNP1; the control module 11 is used to control the read / write word line RWWL to connect to the first transistor MNP0 and the second transistor MNP1 to connect to the first path 13, and control at least one of the first bit line RWBLB and the second bit line RWBL to discharge, so as to read the data of at least one eight-transistor storage cell in the storage module 12 through the first port to implement a read operation; and control the first bit line RWBLB and the second bit line RWBL to write the data into at least one eight-transistor storage cell in the storage module 12 through the second port to implement a write operation.

[0046] Word lines control the conduction of bit lines. Bit lines are used to read and write memory cells in the memory module 12. The read / write word line RWWL controls the connection and disconnection of the first path 13. Specifically, the read / write word line RWWL controls the connection between the first transistor MNP0 and the second transistor MNP1, thereby connecting the memory module 12 to the first bit line RWBLB and the second bit line RWBL, thereby controlling the connection of the first path 13. The first bit line RWBLB and the second bit line RWBL form a pair of complementary bit lines for reading and writing data.

[0047] The first port is a port for performing read operations through the first path 13. The second port is a port for performing write operations through the first path 13. Data read from one or more eight-transistor storage cells in the storage module 12 can be transmitted to an external device through the first path 13 through the first port, and external data can be written to one or more eight-transistor storage cells in the storage module 12 through the first path 13 through the second port.

[0048] When performing a write operation through the first path 13, the first path 13 is used as a write path, the read / write word line RWWL is controlled to connect to the first path 13 (the first transistor MNP0 and the second transistor MNP1), and the data transmitted from the second port is written to the storage module 12 through the first bit line RWBLB and the second bit line RWBL. When performing a read operation through the first path 13, the first path 13 is used as a read path, the read / write word line RWWL is controlled to connect to the first path 13 (the first transistor MNP0 and the second transistor MNP1), and either the first bit line RWBLB or the second bit line RWBL is controlled to discharge, and the data read from the storage module 12 is transmitted to the first port through the first bit line RWBLB and the second bit line RWBL, and then transmitted to an external device. Controlling either the first bit line RWBLB or the second bit line RWBL to discharge may include: controlling the first bit line RWBLB to discharge, controlling the second bit line RWBL to discharge, and controlling the first bit line RWBLB and the second bit line RWBL to discharge.

[0049] Since data can be read when charge is moved out of the storage cell, when reading data through the first path 13, it is necessary to control the first bit line RWBLB and / or the second bit line RWBL to discharge so that the charge is moved out of the storage cell and the data of the first path 13 is read; when reading data through the second path 14, it is necessary to control the third bit line RBLB to discharge so that the charge is moved out of the storage cell and the data of the second path 14 is read.

[0050] In a feasible implementation, as shown in Figure 2, the first end of the read-write word line RWWL is connected to the control module 11, and the second end of the read-write word line RWWL is respectively connected to the control end of the first transistor MNP0 and the control end of the second transistor MNP1; the first port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, the second port is connected to the first end of the first bit line RWBLB and the first end of the second bit line RWBL, the second end of the first bit line RWBLB is connected to the second end of the first transistor MNP0, and the second end of the second bit line RWBL is connected to the second end of the second transistor MNP1.

[0051] In the above embodiment, the connection and disconnection of the first path 13 can be controlled by the read / write word line RWWL; and data can be read and written through a pair of complementary bit lines, namely the first bit line RWBLB and the second bit line RWBL.

[0052] In some embodiments, the second path 14 includes a read word line RWL, a third bit line RBLB and a third port; the first end of the read word line RWL is connected to the control module 11, and the second end of the read word line RWL is connected to the control end of the fourth transistor MNPR; the third port is connected to the first end of the third bit line RBLB, and the second end of the third bit line RBLB is connected to the second end of the fourth transistor MNPR; the control module 11 is used to control the read word line RWL to connect the third transistor MNDR and the fourth transistor MNPR to connect the second path 14, and control the third bit line RBLB to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module 12 through the third port to implement a read operation.

[0053] The read word line RWL is used to control the connection and disconnection of the second path 14; specifically, the read word line RWL is used to control the connection and disconnection of the third transistor MNDR and the fourth transistor MNPR to control the connection and disconnection of the second path 14. The third bit line RBLB is used to implement a read operation by discharging.

[0054] The third port is a port for performing a read operation through the second path 14. The third port can transmit data read from one or more eight-transistor storage units in the storage module 12 to an external device through the second path 14.

[0055] When a read operation is performed through the second path 14, the second path 14 is used as a read path, the read word line RWL is controlled to connect to the second path 14 (the third transistor MNDR and the fourth transistor MNPR), and the third bit line RBLB is controlled to discharge, and the data read from the storage module 12 is transmitted to the third port through the third bit line RBLB, and then transmitted to the external device.

[0056] In the above embodiment, the connection and disconnection of the second path 14 can be controlled by the read word line RWL; and data can be read through the third bit line RBLB.

[0057] In some embodiments, as shown in Figure 1, the storage device 10 includes an addressing module 15; the addressing module 15 is connected between the control module 11 and the storage module 12; the addressing module 15 is used to determine the storage unit corresponding to any address data from the multiple eight-tube storage units of the storage module 12.

[0058] The storage module 12 is used to quickly determine a storage unit corresponding to any address data from a plurality of eight-transistor storage units of the storage module 12 based on the instruction output by the control module 11 .

[0059] In the above embodiment, the addressing module 15 can quickly locate the storage unit corresponding to any address data, thereby achieving fast addressing and improving the data processing rate.

[0060] In some embodiments, as shown in Figure 3, the addressing module 15 includes a first addressing device 151 and a second addressing device 152; the first end of the first addressing device 151 is connected to the control module 11, and the second end of the first addressing device 151 is connected to the read and write word line RWWL and the read word line RWL in the first path 13; the first end of the second addressing device 152 is connected to the control module 11, and the second end of the second addressing device 152 is connected to the first bit line RWBLB and the second bit line RWBL in the first path 13; the first addressing device 151 is used to determine the row corresponding to any address data from the multiple eight-tube storage units of the storage module 12; the second addressing device 152 is used to determine the column corresponding to any address data from the multiple eight-tube storage units of the storage module 12.

[0061] The first addressing device 151 is used to determine the specific row corresponding to any address data from the multiple eight-transistor storage cells of the storage module 12. In one feasible implementation, the first addressing device 151 may be a row decoder. The second addressing device 152 is used to determine the specific column corresponding to any address data from the multiple eight-transistor storage cells of the storage module 12. In one feasible implementation, the second addressing device 152 may be a column selector.

[0062] In the above embodiment, the first addressing device 151 can determine the specific column corresponding to any address data from the multiple eight-tube storage units of the storage module 12, and the second addressing device 152 can determine the specific column corresponding to any address data from the multiple eight-tube storage units of the storage module 12, and then determine the eight-tube storage unit corresponding to any address data based on the specific row and the specific column.

[0063] In some embodiments, as shown in FIG3 , the storage device 10 includes a pre-charging circuit 16 ; the pre-charging circuit 16 is connected between the control module 11 and the storage module 12 ; the pre-charging circuit 16 is used to charge the bit line in the storage device 10 to a target voltage after the read and write operations are completed.

[0064] The precharge circuit 16 is used to charge the bit lines in the storage device 10 to a target voltage to provide a stable reference point for read and write operations, thereby improving data reading accuracy. The target voltage can be the power supply voltage or half the operating voltage of the storage device 10.

[0065] Since data is written when charges are moved into the memory cell, and data is read when charges are moved out of the memory cell, the bit line needs to be charged to an appropriate voltage after the read and write operations are completed.

[0066] In some embodiments, the control module 11 includes a pre-decoding circuit and a control circuit; the pre-decoding circuit is used to pre-decode any address data and transmit the decoded address data to the first addressing device 151; the control circuit is used to control the interaction of the various components in the storage device 10.

[0067] Any address data may refer to the address of the data to be read or the address to be written. The pre-decoding circuit is mainly used to pre-decode the address data and transmit the pre-decoded address data to the row decoder.

[0068] In some embodiments, as shown in Figure 3, the storage device 10 includes a first read circuit 17; a first end of the first read circuit 17 is connected to the first port, and a second end of the first read circuit 17 is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL; the first read circuit 17 is used to amplify and latch a signal carrying data read from the storage module 12 through the first path 13, and output a first processed signal from the first port.

[0069] The first read circuit 17 is used to transmit data read through the first path 13; specifically, it is used to transmit data read from the first bit line RWBLB and the second bit line RWBL to the first port. In one possible implementation, the first read circuit 17 may include, but is not limited to, a sense amplifier and a read circuit. The sense amplifier is used to amplify the weak signal read from the memory cell so that it can be read by external circuitry. Because the read current of the memory cell is very small, a sense amplifier is required to amplify this weak signal to ensure accurate data reading. The read circuit is responsible for latching the signal amplified by the sense amplifier and driving it to the first port.

[0070] In some embodiments, the storage device 10 includes a write circuit 18; a first end of the write circuit 18 is connected to the second port, and a second end of the write circuit 18 is connected to a first end of the first bit line RWBLB and a first end of the second bit line RWBL; the write circuit 18 is used to write data into the first bit line RWBLB and the second bit line RWBL based on the instruction of the control module 11, and then write into the storage module 12.

[0071] The write circuit 18 is used to transmit data to the column selector, and then write the data into the storage module 12 through the first path 13. In one feasible implementation, the write circuit 18 may include but is not limited to a first data input channel and a control gate to write data (usually a binary number 0 or 1) into a specific storage cell according to the instruction of the control module 11.

[0072] In some embodiments, the storage device 10 includes a second read circuit 19; a first end of the second read circuit 19 is connected to the control module 11, and a second end of the second read circuit 19 is connected to the third bit line RBLB; the second read circuit 19 is used to amplify and latch a signal carrying data read from the storage module 12 through the second path 14, and output a second processed signal from the second port.

[0073] Second read circuit 19 is used to transmit data read through second path 14; specifically, it is used to transmit data read from third bit line RBLB to a third port. In one feasible implementation, the structure of second read circuit 19 can be the same as that of first read circuit 17, or the second read circuit 19 and first read circuit 17 can be customized to meet different reading requirements.

[0074] In the above embodiment, the signal carrying the data read from the storage module 12 can be amplified and latched through the first reading circuit 17 and the second reading circuit 19 to ensure the reliability of signal transmission and improve the stability of data transmission; and the data can be written into a specific storage element through the writing circuit.

[0075] In some embodiments, as shown in FIG3 , the control module 11 may include a first pin ME_R1 , a second pin ME_R2 , a third pin ME_W, a fourth pin CLK_R1 , a fifth pin CLK_R2 , a sixth pin CLK_W, and a seventh pin ADR_W / R1 / R2 .

[0076] The first pin, ME_R1, triggers a read request for a read operation through the first path 13. The second pin, ME_R2, triggers a read request for a read operation through the second path 14. The third pin, ME_W, triggers a write request for a write operation through the first path 13. The fourth pin, CLK_R1, triggers a clock signal that synchronizes the reading of data from the first path 13. The fifth pin, CLK_R2, triggers a clock signal that synchronizes the reading of data from the second path 14. The sixth pin, CLK_W, triggers a clock signal that synchronizes the writing of data to the first path 13. The seventh pin, ADR_W / R1 / R2, is a pseudo-instruction in ARM assembly instructions. ADR_W / R1 / R2 generally represents the register configuration of an analog-to-digital converter (ADC) or digital-to-analog converter (DAC); specifically, ADR_W represents the write address register. R1 and R2 represent two different read address registers that can be used to store different configuration parameters, such as gain setting, reference voltage, input range, output format, etc.

[0077] It should be noted that the storage device 10 shown in FIG3 may be a 2R1W SRAM, that is, an SRAM capable of implementing two read and one write functions, where “2R” refers to two read operations and “1W” refers to one write operation.

[0078] The present disclosure provides a data processing method, which is applied to the control module 11 in the storage device 10 shown in Figure 3. As shown in Figure 4, the method includes the following steps 401:

[0079] Step 401: In response to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, control a first path connected between the storage module and the control module to perform a read operation and a write operation, and simultaneously control a second path connected between the storage module and the control module to perform a read operation.

[0080] The operation signal characterization requires two read operations and one write operation, that is, the operation signal characterization requires two read and one write functions.

[0081] In a feasible implementation, the operation signal may be triggered by a preset option on the menu bar, or may be triggered by a physical button.

[0082] In a feasible implementation, when the operation signal causes the first pin ME_R1 , the second pin ME_R2 and the third pin ME_W to change from low level to high level, it is determined that the operation signal requiring two reads and one write is triggered.

[0083] In a feasible implementation, the specific implementation of two reads and one write can be: through the control module, first control the first path to perform a read operation and then a write operation (completing one read and one write), and at the same time control the second path to perform a read operation (one read), thus achieving two reads and one write.

[0084] It should be noted that the operations of the two paths can be performed simultaneously or sequentially, and this disclosure does not limit this.

[0085] In some embodiments, the step 401 of “controlling the first path connected between the storage module and the control module to perform a read operation and a write operation” can be implemented by the following steps 4011 to 4012:

[0086] Step 4011: Control the read / write word line to connect to the first path, and control at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, and complete the current read operation.

[0087] In some embodiments, step 4011 may be specifically implemented as follows: controlling the read / write word line to connect to the first bit line and the second bit line in the first path; determining, through the positioning device, a first storage unit from a plurality of eight-transistor storage units of the storage device based on the first address data in the operation signal; controlling at least one of the first bit line and the second bit line to discharge, and reading the first data in the first storage unit.

[0088] Controlling the read / write word line to connect the first bit line and the second bit line in the first path refers to controlling the read / write word line to turn on the first transistor MNP0 and the second transistor MNP1 to connect the first bit line and the second bit line, thereby achieving connectivity of the first path.

[0089] The first data refers to the data to be read through the first path. The first address data refers to the address where the first data is located. The first storage unit is one or more eight-pipe storage cells storing the first data.

[0090] Determining the first storage unit from the multiple eight-transistor storage units of the storage device based on the first address data in the operation signal by the positioning device means that the row corresponding to the first address data is selected from the multiple eight-transistor storage units of the storage device by a row decoder, and the column corresponding to the first address data is selected from the multiple eight-transistor storage units of the storage device by a column selector, and then the first storage unit is obtained according to the selected row and column.

[0091] Since data can be read when charges are moved out of the memory cell, when reading data in the first path, it is necessary to control the first bit line and / or the second bit line to discharge so that charges are moved out of the memory cell to read data in the first path.

[0092] Controlling at least one of the first bit line and the second bit line to discharge to read the first data in the first storage cell includes the following three situations: In the first situation, the first bit line is controlled to discharge, and the first data in the first storage cell is transmitted to the first reading circuit via the column selector, and then transmitted to the first port via the first reading circuit to read the data in the first path. In the second situation, the second bit line is controlled to discharge, and the first data in the first storage cell is transmitted to the first reading circuit via the column selector, and then transmitted to the first port via the first reading circuit to read the data in the first path. In the third situation, the first bit line and the second bit line are controlled to discharge, and the first data in the first storage cell is transmitted to the first reading circuit via the column selector, and then transmitted to the first port via the first reading circuit to read the data in the first path.

[0093] Step 4012: Control the precharge circuit to charge the first bit line and the second bit line to a target voltage, and write the second data to be written by the operation signal into the storage module through the first path to complete this write operation.

[0094] Since step 4011 realizes reading of data of the first path by discharging any one of the first bit line and the second bit line, when performing a write operation here, it is necessary to control the precharge circuit to charge the first bit line and the second bit line to the target voltage to perform the write operation, and write the second data to be written into the storage module through the first path.

[0095] In some embodiments, the specific implementation method of "writing the second data to be written by the operation signal into the storage module through the first path" in the above step 4012 can be: using the positioning device, determining the second storage unit from the multiple eight-tube storage units of the storage device based on the second address data in the operation signal; and writing the second data into the second storage unit through the first path.

[0096] The second data refers to the data to be written. The second address data refers to the address where the second data is to be written. The second storage unit refers to one or more eight-pipe storage units where the second data is to be written.

[0097] Determining the second storage unit from the plurality of eight-transistor storage units of the storage device based on the second address data in the operation signal by the positioning device means selecting the row corresponding to the second address data from the plurality of eight-transistor storage units of the storage device by a row decoder, and selecting the column corresponding to the second address data from the plurality of eight-transistor storage units of the storage device by a column selector, and then obtaining the second storage unit according to the selected row and column.

[0098] Writing the second data into the second storage unit through the first path means transmitting the second data through the second port, via the write circuit, to the column selector, and then transmitting the second data to the second storage unit in the storage module through the column selector.

[0099] In some embodiments, the storage device includes a pre-charging circuit, the second path includes a read word line and a third bit line, and the read word line is used to control the third bit line to discharge; the specific implementation method of "controlling the second path connected between the storage module and the control module to perform a reading operation" in the above step 401 can be: controlling the pre-charging circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the third data to be read by the operation signal, and complete this reading operation.

[0100] In a feasible implementation, a specific implementation of controlling the pre-charging circuit to stop charging the third bit line may be: controlling the charging signal Pchg_R of the pre-charging circuit to turn off charging through the control module.

[0101] The third data refers to data to be read through the second path.

[0102] In one feasible implementation, the specific implementation of "controlling the read word line to connect to the second path and controlling the third bit line to discharge, so as to read the third data to be read by the operation signal" is: controlling the read word line to connect to the third bit line in the second path; determining, through the positioning device, a third storage unit from a plurality of eight-transistor storage units in the storage device based on the third address data in the operation signal; controlling the third bit line to discharge, and reading the third data in the third storage unit.

[0103] Controlling the read word line to connect to the third bit line in the second path refers to controlling the read word line to turn on the third transistor MNDR and the fourth transistor MNPR to connect to the third bit line, thereby achieving connectivity of the second path.

[0104] The third address data refers to the address where the third data is located. The third storage unit is an eight-pipe storage element storing the third data.

[0105] Determining the third storage unit from the multiple eight-transistor storage units of the storage device based on the third address data in the operation signal by the positioning device means that the row corresponding to the third address data is selected from the multiple eight-transistor storage units of the storage device by the row decoder, and the column corresponding to the third address data is selected from the multiple eight-transistor storage units of the storage device by the column selector, and then the third storage unit is obtained according to the selected row and column.

[0106] Controlling the third bit line to discharge and read the third data in the third storage unit refers to controlling the third bit line to discharge and transmitting the third data in the third storage unit to the second reading circuit via the column selector, and then transmitting the third data to the third port via the second reading circuit.

[0107] Based on the above embodiment, when the operation signal indicates that a read operation is required, the data processing method provided by the present disclosure further includes the following steps 402 to 403:

[0108] Step 402: When the operation signal indicates that a single read operation is required, control the first path to perform a read operation, and control the second path to perform a read operation.

[0109] In one feasible implementation, whether the operation signal is to perform a single read operation or a double read operation can be determined based on the pin change caused by the operation signal. Specifically, if the operation signal causes a change in either the first pin or the second pin, the operation signal is determined to perform a single read operation; if the operation signal causes changes in both the first pin and the second pin, the operation signal is determined to perform a double read operation.

[0110] In one feasible implementation, when the operation signal causes the first pin ME_R1 to change from a low level to a high level, it is determined that the operation signal requires a single read operation through the first path, and the first path is controlled to perform the read operation. When the operation signal causes the second pin ME_R2 to change from a low level to a high level, it is determined that the operation signal requires a single read operation through the second path, and the second path is controlled to perform the read operation.

[0111] In some embodiments, the storage device includes a pre-charging circuit, the first path includes a read-write word line, a first bit line, and a second bit line, and the read-write word line is used to control the first bit line and the second bit line to discharge; the specific implementation method of "controlling the first path to perform a reading operation" in step 402 can be: controlling the pre-charging circuit to stop charging the first bit line and the second bit line; controlling the read-write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal, thereby completing this reading operation.

[0112] In a feasible implementation, a specific implementation of controlling the pre-charging circuit to stop charging the first bit line and the second bit line may be: controlling the charging signal Pchg_RW of the pre-charging circuit to turn off charging through the control module.

[0113] It should be noted that the operation of "controlling the read / write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal" here is similar to the operation of "controlling the read / write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal" in the above-mentioned step 4011. For details, please refer to the description in step 4011, and the embodiment of the present disclosure will not be described in detail.

[0114] Specifically, the specific implementation method of "controlling the read / write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the fourth data to be read by the operation signal" can be: controlling the read / write word line to connect to the first bit line and the second bit line in the first path; determining the corresponding storage unit from the multiple eight-transistor storage units of the storage device based on the address data in the operation signal through the positioning device; controlling at least one of the first bit line and the second bit line to discharge, and reading the fourth data in the corresponding storage unit.

[0115] It should be noted that the implementation method of "controlling the second path to perform a read operation" in step 402 is similar to the implementation method of "controlling the second path connected between the storage module and the control module to perform a read operation" in step 401. For details, please refer to the description in step 401, and this embodiment of the present disclosure will not be described in detail.

[0116] Specifically, the specific implementation method of "controlling the second path to perform a read operation" in step 402 can be: controlling the precharge circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the data to be read by the operation signal, thereby completing this read operation.

[0117] Step 403 : When the operation signal indicates that two read operations are required, control the first path and the second path to perform read operations respectively.

[0118] In a feasible implementation, when the operation signal causes both the first pin ME_R1 and the second pin ME_R2 to change from low level to high level, it is determined that the operation signal indicates that two read operations are required. At this time, the first path and the second path are controlled to perform read operations simultaneously.

[0119] It should be noted that the implementation method of "controlling the first path to perform a read operation" here is similar to the implementation method of "controlling the first path to perform a read operation" in the above step 402. For details, please refer to the description in step 402, and this embodiment of the present disclosure will not be described in detail.

[0120] Specifically, the specific implementation method of "controlling the first path to perform a read operation" here can be: controlling the read / write word line to connect the first bit line and the second bit line in the first path; through the positioning device, determining the corresponding storage unit from the multiple eight-transistor storage units of the storage device based on the address data in the operation signal; controlling at least one of the first bit line and the second bit line to discharge, and reading the data in the corresponding storage unit.

[0121] It should be noted that the implementation method of "controlling the second path to perform a read operation" here is similar to the implementation method of "controlling the second path connected between the storage module and the control module to perform a read operation" in the above step 401. For details, please refer to the description in step 401, and this embodiment of the present disclosure will not be described in detail.

[0122] Specifically, the specific implementation method of "controlling the second path to perform a read operation" here can be: controlling the precharge circuit to stop charging the third bit line; controlling the read word line to connect to the second path, and controlling the third bit line to discharge, so as to read the data to be read by the operation signal, thereby completing this read operation.

[0123] It is worth mentioning that controlling the first path to perform a read operation and controlling the second path to perform a read operation may be performed simultaneously or sequentially, and this is not limited in the embodiment of the present disclosure.

[0124] Based on the above embodiment, when the operation signal indicates that a write operation is required, the data processing method provided by the present disclosure further includes the following steps 404 to 405:

[0125] Step 404: Control the precharge circuit to stop charging the first bit line and the second bit line.

[0126] In a feasible implementation, when the operation signal causes the third pin ME_W to change from a low level to a high level, it is determined that the operation signal indicates that a write operation is required, and the write operation is performed through the first path, which is specifically implemented through steps 404 to 405.

[0127] In a feasible implementation, a specific implementation of controlling the pre-charging circuit to stop charging the first bit line and the second bit line may be: controlling the charging signal Pchg_RW of the pre-charging circuit to turn off charging through the control module.

[0128] Step 405 : Control the read / write word line to connect to the first path, and write the fifth data to be written by the operation signal into the storage module through the first bit line and the second bit line, thereby completing this write operation.

[0129] It should be noted that the implementation method of step 405 is similar to the implementation method of "writing the second data to be written by the operation signal into the storage module through the first path" in the above-mentioned step 4012. For details, please refer to the description in step 4012, and this embodiment of the present disclosure will not be described in detail.

[0130] Specifically, the specific implementation method of "writing the fifth data to be written by the operation signal into the storage module through the first bit line and the second bit line" can be: through the positioning device, based on the address data in the operation signal, the corresponding storage unit is determined from the multiple eight-tube storage units of the storage device; and the data is written into the corresponding storage unit through the first bit line and the second bit line in the first path.

[0131] Based on the above embodiment, when the operation signal indicates that a write operation and a read operation are required, the data processing method provided by the present disclosure further includes the following step 406:

[0132] Step 406: Control the first path to perform a read operation and a write operation; or control the first path to perform a write operation and control the second path to perform a read operation.

[0133] In one feasible implementation, when an operation signal causes both the first pin ME_R1 and the third pin ME_W to transition from a low level to a high level, it is determined that the operation signal indicates a need for a write operation and a read operation to be performed through the first path, and in this case, the first path is controlled to perform the read and write operations. When an operation signal causes both the second pin ME_R2 and the third pin ME_W to transition from a low level to a high level, it is determined that the operation signal indicates a need for a write operation to be performed through the first path and a read operation to be performed through the second path, and in this case, the first path is controlled to perform the write operation, and the second path is controlled to perform the read operation.

[0134] It should be noted that the implementation method of "controlling the first path to perform read operations and write operations" in step 406 is similar to the implementation method of "controlling the first path connected between the storage module and the control module to perform read operations and write operations" in the above step 401. For details, please refer to the description in the above step 401, and this embodiment of the present disclosure will not be described in detail.

[0135] It should be noted that the implementation of "controlling the first path to perform a write operation" in step 406 is similar to the implementation described in steps 404 to 405 above. For details, please refer to the description in steps 404 to 405 above, and this embodiment of the disclosure will not be described in detail.

[0136] It should be noted that the implementation of "controlling the second path to perform a read operation" in step 406 is similar to the implementation of "controlling the second path to perform a read operation" in the above step 403. For details, please refer to the description in the above step 403, and this embodiment of the present disclosure will not be described in detail.

[0137] The present disclosure provides a data processing method, which is applied to the control module in the storage device shown in Figure 3. As shown in Figure 5, the method includes the following steps 501 to 503:

[0138] Step 501: respond to an externally triggered operation signal and determine a current operating mode based on the type of the operation signal.

[0139] The types of operation signals can be read type, write type, and read-write type. Further, the read type can include a first read type that performs a read operation once through the first path, a second read type that performs a read operation once through the second path, and a third read type that performs two read operations through the first path and the second path. The read-write type can include a first read-write type that performs a write operation once through the first path and a read operation once through the second path, a second read-write type that performs a write operation once and a read operation once through the first path, and a third read-write type that performs a write operation once and a read operation once through the first path.

[0140] In a feasible implementation, if the operation signal characterizes that a read operation needs to be performed once through the first path, then the type of the operation signal is determined to be the first read type (one read); if the operation signal characterizes that a read operation needs to be performed once through the second path, then the type of the operation signal is determined to be the second read type (one read); if the operation signal characterizes that two read operations need to be performed through the first path and the second path, then the type of the operation signal is determined to be the third read type (two reads).

[0141] Similarly, if the operation signal indicates that a write operation needs to be performed once through the first path and a read operation needs to be performed once through the second path, then the type of the operation signal is determined to be the first read-write type (one read and one write); if the operation signal indicates that a write operation and a read operation need to be performed once through the first path, then the type of the operation signal is determined to be the second read-write type (one read and one write); if the operation signal indicates a second read-write type that requires a write operation and a read operation through the first path and a read operation is performed once through the second path, then the type of the operation signal is determined to be the third read-write type (two reads and one write).

[0142] In a feasible implementation, if the type of the operation signal is the first read type, then the current working mode is determined to be the first mode; if the type of the operation signal is the second read type, then the current working mode is determined to be the second mode; if the type of the operation signal is the third read type, then the current working mode is determined to be the third mode; if the type of the operation signal is the write type, then the current working mode is determined to be the fourth mode; if the type of the operation signal is the first read-write type, then the current working mode is determined to be the fifth mode; if the type of the operation signal is the second read-write type, then the current working mode is determined to be the sixth mode; if the type of the operation signal is the third read-write type, then the current working mode is determined to be the seventh mode.

[0143] Step 502: Based on the current working mode, select a target path from the first path and the second path.

[0144] When the current working mode is the first mode, the first path is selected as the target path; when the current working mode is the second mode, the second path is selected as the target path; when the current working mode is the third mode, the first path and the second path are selected as the target paths; when the current working mode is the fourth mode, the first path is selected as the target path; when the current working mode is the fifth mode, the first path and the second path are selected as the target paths; when the current working mode is the sixth mode, the first path is selected as the target path; when the current working mode is the seventh mode, the first path and the second path are selected as the target paths.

[0145] Step 503: Process the operation signal based on the target path.

[0146] When the current operating mode is the first mode, a read operation is performed based on the first path to process the operation signal; when the current operating mode is the second mode, a read operation is performed based on the second path to process the operation signal; when the current operating mode is the third mode, two read operations are performed based on the first path and the second path to process the operation signal; when the current operating mode is the fourth mode, a write operation is performed based on the first path to process the operation signal; when the current operating mode is the fifth mode, a write operation is performed based on the first path and a read operation is performed based on the second path to process the operation signal; when the current operating mode is the sixth mode, a write operation and a read operation are performed based on the first path to process the operation signal; when the current operating mode is the seventh mode, a write operation and a read operation are performed based on the first path and a read operation is performed based on the second path to process the operation signal.

[0147] The following describes the application of the data processing method provided by the embodiment of the present disclosure in a practical scenario, taking a 2R1WSRAM storage device as an example.

[0148] As shown in FIG2 , the structure of the 2R1W SRAM provided by the present disclosure may include: a first transistor MNP0 and a second transistor MNP1 for forming a first path 13; a third transistor MNDR and a fourth transistor MNPR for forming a second path 14; and four fifth transistors for forming a latch. The four fifth transistors forming the latch are a first pull-up transistor MPU0, a second pull-up transistor MPU1, a first pull-down transistor MND0, and a second pull-down transistor MND1.

[0149] In the related art, the two NMOS transistors used as transmission tubes can only serve as a write path. However, in the present disclosure, they can be used as a shared path between the write path and one of the read paths. The read / write word line RWWL controls the opening and closing of the path. When used as a write path, the read / write word line RWWL is open, and data is written to the storage module via the complementary first bit line RWBLB and second bit line RWBL. When used as a read path, the read / write word line RWWL is open, and the storage module discharges one of the complementary first bit line RWBLB and second bit line RWBL through the two transmission tubes, thereby completing the information read operation. The two NMOS transistors MNPR and MNDR serve as another read path, controlling the discharge of the third bit line RBLB via the read word line RWL to perform the read operation.

[0150] As shown in FIG3 , the overall architecture of a 2R1W SRAM may include an eight-transistor memory cell array (memory module 12 ), a controller (control module 11 ), a precharge circuit 16 , a row decoder (a first addressing device 151 ), a column selector (a second addressing device 152 ), a write circuit 18 , a first read circuit 17 , and a second read circuit 19 .

[0151] Among them, the eight-tube memory cell array is a matrix (array) composed of multiple eight-tube memory cells, each of which can store one bit (the smallest unit of data), thus forming a memory array that can store a large amount of data and is used for read and write operations.

[0152] The controller (control module 11) includes a pre-decoding circuit and a control circuit. The pre-decoding circuit is primarily used to pre-decode address data and then send the pre-decoded address data to the row decoder. The control circuit is responsible for managing, coordinating, and controlling the functional implementation and timing of the circuits in various parts of the system. It is responsible for managing the interaction between the memory array and various other components (such as bit select circuits, sense amplifiers, and write circuits), ensuring that data arrives at the specified working sequence and is correctly read and written.

[0153] The precharge circuit 16 is used to charge each bit line of the memory array to the power supply voltage after the read / write phase. This process prepares for the subsequent read / write operation because the bit line needs to be charged to the appropriate voltage level before charge is transferred into or out of the memory array to write or read data.

[0154] The row decoder circuit (first addressing device 151) is used to post-decode the read and write addresses, thereby selecting a specific row for subsequent read and write operations.

[0155] The column select circuit (second addressing device 152), also known as a column selector, is responsible for selecting a specific bit (i.e., a specific memory array in the vertical direction) for read / write operations in a memory system. This circuit typically operates based on signals received from a controller to determine which specific bit to read / write.

[0156] The write circuit 18 writes data (usually 1 or 0) into a specific memory array according to the controller's instructions. The write circuit generally includes a data input channel and a control gate for writing data into the memory array.

[0157] The first read circuit 17 includes a sense amplifier and a read circuit. The sense amplifier plays a key role in static random access memory (SRAM), amplifying the weak signal read from the memory array so that it can be read by external circuits. Because the read current of the memory array is very small, a sense amplifier is required to amplify this weak signal to ensure accurate data reading. The read circuit is responsible for latching the signal amplified by the sense amplifier and driving it to the output port QB1 (first port).

[0158] The second read circuit 19 is used to latch the single-ended read signal of RBLB and drive it to the output port QB2 (second port).

[0159] 2R1W SRAM can include the following working modes:

[0160] The first is a write-only mode. In this mode, the memory enable signals ME_R1 = 0, ME_R2 = 0, ME_W = 1, and WEA = 1. The controller controls the precharge circuit's charge signal Pchg_RW to turn off charging, and controls the write circuit to write the signal DA to RWBL_W and RWBLB_W, which are then written to RWBL and RWLBLB via the column selector. At the same time, the address data in ADR_W opens a specific RWWL, selects a specific row in the eight-transistor memory module array, and writes data to the memory module in that row via the RWBL and RWLBLB that have already been written.

[0161] The second mode is a read-only port operation mode, which is further divided into read-only READ PORT1 (first port) and read-only READ PORT2 (third port).

[0162] In the read-only READ PORT1 working mode, ME_R1=1, ME_R2=0, ME_W=0, and WEA=0 in the memory enable signal are controlled by the controller to turn off charging by controlling the charging signal Pchg_RW of the pre-charge circuit, and to open a specific RWWL through the address data of ADR_R1 to select a specific row in the eight-transistor memory module array. The data in the memory module is read to the column selector through RWBL and RWLBLB, and the signals of RWBL and RWLBLB are transmitted to RWBL_R1 and RWLBLB_R1 through the column selector. Finally, the first read circuit 1 is controlled to amplify the signals RWBL_R1 and RWLBLB_R1 through the sense amplifier and finally driven to the output port QB1.

[0163] In the read-only READ PORT2 working mode, ME_R1=0, ME_R2=1, ME_W=0, and WEA=0 in the memory enable signal are used. The controller controls the charging signal Pchg_R of the pre-charge circuit to turn off charging, and turns on a specific RWL through the address data of ADR_R2 to select a specific row in the eight-transistor memory module array. The data in the memory module is read to the column selector through RBLB, and the signal of RBLB is transmitted to RWLBLB_R2 through the column selector. Finally, the second read circuit 2 is controlled to drive the signal RBLB_R2 to the output port QB2.

[0164] The third mode is a mode for reading from two read ports simultaneously. In this mode, ME_R1=1, ME_R2=1, ME_W=0, and WEA=0 in the memory enable signal.

[0165] For READ PORT1, the controller controls the charging signal Pchg_RW of the pre-charge circuit to turn off charging, and opens a specific RWWL through the address data of ADR_R1, selects a specific row in the eight-tube storage module array, reads the data in the storage module to the column selector through RWBL and RWLBLB, and then transmits the signals of RWBL and RWLBLB to RWBL_R1 and RWLBLB_R1 through the column selector. Finally, the first read circuit 1 is controlled to amplify the signals RWBL_R1 and RWLBLB_R1 through the sense amplifier and finally drive them to the output port QB1.

[0166] For READ PORT2, the controller controls the charging signal Pchg_R of the pre-charge circuit to be turned off, and opens a specific RWL through the address data of ADR_R2, selecting a specific row in the eight-transistor storage module array, reading the data in the storage module to the column selector through RBLB, and then passing the RBLB signal to RWLBLB_R2 through the column selector. Finally, the second read circuit 2 is controlled to drive the signal RBLB_R2 to the output port QB2.

[0167] The fourth mode is a mode in which a read port and a write port (second port) work simultaneously. This working mode is further divided into a mode in which the write port and the READ PORT1 read port work simultaneously, and a mode in which the write port and the READ PORT2 read port work simultaneously.

[0168] In the mode where the write port and READ PORT1 read port work simultaneously, ME_R1=1, ME_R2=0, ME_W=1, and WEA=1 in the memory enable signal are controlled by the controller to turn off the charging of the pre-charge circuit's charging signal Pchg_RW, and open a specific RWWL through the address data of ADR_R1 to select a specific row in the eight-tube memory module array. The data in the memory module is read to the column selector through RWBL and RWLBLB, and the signals of RWBL and RWLBLB are transmitted to RWBL_R1 and RWLBLB_R1 through the column selector. Finally, the read circuit 1 is controlled to amplify the signals RWBL_R1 and RWLBLB_R1 through the sense amplifier and finally driven to the output port QB1. At the same time, the write circuit is controlled to write the signal DA to RWBL_W and RWBLB_W. After amplification by the sense amplifier, RWWL is closed and RWBL and RWBLB are charged to a high level. Then, the column selector is opened to write the data of RWBL_W and RWBLB_W to RWBL and RWLBLB. At the same time, the address data of ADR_W is used to open a specific RWWL, select a specific row in the eight-transistor memory module array, and write the data to the memory module in that row through the RWBL and RWLBLB.

[0169] In the operating mode where both the write port and READ PORT2 are active, the memory enable signals ME_R1 = 0, ME_R2 = 1, ME_W = 1, and WEA = 1. Read and write operations are performed separately, unlike the previous sequential order. The read operation uses the controller to disable the precharge circuit's charge signal Pchg_R and, using the address data from ADR_R2, enable a specific RWL, selecting a specific row in the eight-transistor memory module array. The data in the memory module is read from the RBLB to the column selector, which then transmits the RBLB signal to RWLBLB_R2. Finally, the read circuit 1 is controlled to drive the signal RBLB_R2 to the output port QB2. In this mode, the write operation is the same as in the first operating mode.

[0170] The fifth mode is a simultaneous operation of two read ports and one write port, also known as the two-read, one-write mode. In this mode, the memory enable signals ME_R1 = 1, ME_R2 = 1, ME_W = 1, and WEA = 1. The write port and READ PORT1 operate in the same manner as in the fourth mode, with read-first followed by write. READ PORT2 operates in the same manner as in the second read-only mode.

[0171] As shown in Figure 6, the timing of the write port and the READ PORT1 read port working simultaneously is: read 1 and write 0 in the first cycle, and read 0 and write 1 in the second cycle. When CLK_W / CLK_R1 rises, the address data of ADR_R1 opens a specific RWWL through the decoder, selects a specific row in the eight-transistor memory module array, transfers the information in the memory module to RWBL and RWBLB, and transmits it to RWBL_R1 and RWBLB_R1 through the open column select circuit. It can be seen that at this time, since 1 is read in the first cycle, RWBL remains unchanged, and RWBLB drops to a certain voltage. When RWL / RWLB and RWBL_R1 / RWBLB_R1 reach a certain voltage difference, the controller controls the column select circuit to close. At this time, RWL / RWLB is charged back to VDD by the charging circuit, and RWBL_R1 / RWBLB_R1 is amplified to high and low levels by the sense amplifier in the read circuit 1, and is finally driven to the output end to see QB1, successfully reading 1. In addition, the controller controls the column selector to close the read port and open the write port at the same time. Before this, RWBL_W / RWBLB_W has been driven by the write circuit to change to high and low levels according to the input DA signal. After the column selector opens the write path, RWL / RWLB, which has been charged to a high level, is changed to the same high and low levels as RWBL_W / RWBLB_W through the column selector. At this time, the previously closed RWWL is again selected and pulled high according to the decoded address of ADR_W during the write phase, and is written to the storage module of the row through RWL / RWLB, and the write is completed at this time.

[0172] As shown in Figure 7, the operating sequence of READ PORT2 is: read 0 in the first cycle, read 1 in the second cycle. When CLK_R2 rises, the address data in ADR_R2 is decoded to open a specific RWL, select a specific row in the eight-transistor memory module array, transfer the information in the memory module to RBLB, and then transmit it to RBLB_R2 through the open column select circuit. Finally, it is driven to output port QB2 through the second read circuit 2, and the read is successful.

[0173] It should be noted that the purpose of the present disclosure is to design a circuit structure of a 2R1W SRAM based on an eight-tube storage cell. Unlike the current ten-tube storage cell that performs two reads and one write through three channels, the two channels (one write channel and one read channel) of the traditional eight-tube storage cell are optimized. In order to achieve the effect of two reads and one write under the ten-tube storage cell, the write channel is reused in one cycle and a write-first-then-read or read-first-then-write method is used to achieve the effect of one channel for reading and writing. In addition, the original other read port is added, so that the effect of two read ports and one write port is finally achieved externally. By sharing the read and write channels within one cycle, the read and write functions of two reads and one write are finally realized. While ensuring high performance and functionality, the area of ​​the storage cell is reduced while reducing the overall area of ​​the SRAM, thereby reducing the chip cost, thereby solving the problems of excessive area caused by the ten-tube storage cell and poor read and write functions caused by the eight-tube storage cell.

[0174] It should be noted that, in the embodiments of the present disclosure, if the above-mentioned data processing method is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the relevant technology can be embodied in the form of a software product, which is stored in a storage medium and includes a number of instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes various media that can store program codes, such as a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk. In this way, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software and firmware.

[0175] The present disclosure provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements some or all of the steps in the above method. The computer-readable storage medium may be transient or non-transient.

[0176] An embodiment of the present disclosure provides a computer program, including computer-readable codes. When the computer-readable codes are executed in a computer device, a processor in the computer device executes some or all of the steps for implementing the above method.

[0177] The present disclosure provides a computer program product, which includes a non-transitory computer-readable storage medium storing a computer program, and when the computer program is read and executed by a computer, implements some or all of the steps in the above method. The computer program product can be implemented specifically by hardware, software, or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium. In other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (SDK), etc.

[0178] It should be noted that the descriptions of the various embodiments above tend to emphasize the differences between the embodiments, and reference can be made to the similarities or similarities between them. The descriptions of the above embodiments of the device, storage medium, computer program, and computer program product are similar to the descriptions of the above-mentioned method embodiments and have similar beneficial effects as the method embodiments. For technical details not disclosed in the embodiments of the device, storage medium, computer program, and computer program product disclosed herein, please refer to the description of the method embodiments disclosed herein for understanding.

[0179] It should be understood that “one embodiment” or “an embodiment” mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present disclosure. Therefore, “in one embodiment” or “in an embodiment” appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in the various embodiments of the present disclosure, the size of the serial numbers of the above-mentioned steps / processes does not mean the order of execution, and the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The serial numbers of the embodiments of the present disclosure are for description only and do not represent the advantages and disadvantages of the embodiments.

[0180] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0181] In the several embodiments provided in the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of the devices or units can be electrical, mechanical or other forms.

[0182] The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed across multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the scheme of this embodiment.

[0183] In addition, all functional units in the embodiments of the present disclosure may be integrated into one processing unit, or each unit may be separately used as a unit, or two or more units may be integrated into one unit; the above-mentioned integrated units may be implemented in the form of hardware or in the form of hardware plus software functional units.

[0184] Those skilled in the art will understand that all or part of the steps of implementing the above-mentioned method embodiment can be completed by hardware related to program instructions, and the aforementioned program can be stored in a computer-readable storage medium. When the program is executed, it executes the steps of the above-mentioned method embodiment; and the aforementioned storage medium includes: mobile storage devices, read-only memories (ROM), magnetic disks or optical disks, and other media that can store program codes.

[0185] Alternatively, if the above-mentioned integrated unit of the present disclosure is implemented in the form of a software function module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the relevant technology, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the methods described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as mobile storage devices, ROMs, magnetic disks, or optical disks.

[0186] The above description is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or replacements within the technical scope disclosed in the present disclosure, and they should all be covered by the protection scope of the present disclosure. Industrial Applicability

[0187] The present disclosure provides a data processing method, a storage device, a computer-readable storage medium, and a computer program product. The storage device further includes a storage module. The data processing method includes: responding to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, controlling a first path connected between the storage module and the control module to perform a read operation and a write operation, and simultaneously controlling a second path connected between the storage module and the control module to perform a read operation. The above solution can implement two read and one write functions through the storage device, thereby reducing the area occupied by the storage device and lowering the device cost while ensuring high performance and two read and one write functions.

Claims

1. A data processing method, wherein: A control module applied to a storage device, wherein the storage device further includes a storage module, and the data processing method includes: In response to an externally triggered operation signal, when the operation signal indicates that two read operations and one write operation are required, the first path connected between the storage module and the control module is controlled to perform a read operation and a write operation, and the second path connected between the storage module and the control module is controlled to perform a read operation.

2. The data processing method according to claim 1, wherein: The storage device includes a precharge circuit, the first path includes a read / write word line, a first bit line and a second bit line, and the read / write word line is used to control the first bit line and the second bit line to discharge; The controlling of the first path connected between the storage module and the control module to perform a read operation and a write operation includes: Controlling the read / write word line to connect to the first path, and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, thereby completing the current read operation; The precharge circuit is controlled to charge the first bit line and the second bit line to a target voltage, and the second data to be written by the operation signal is written into the storage module through the first path to complete the current write operation.

3. The data processing method according to claim 2, wherein: The storage device includes a positioning device; The controlling the read / write word line to connect to the first path and controlling at least one of the first bit line and the second bit line to discharge, so as to read the first data to be read by the operation signal, includes: Controlling the read / write word lines to connect to the first bit line and the second bit line in the first path; determining, by the positioning device, a first storage unit from a plurality of eight-transistor storage units of the storage device based on first address data in the operation signal; At least one of the first bit line and the second bit line is controlled to discharge, and first data in the first memory cell is read.

4. The data processing method according to claim 2, wherein: The storage device includes a positioning device; Writing the second data to be written by the operation signal into the storage module through the first path includes: determining, by the positioning device, a second storage unit from a plurality of eight-transistor storage units of the storage device based on second address data in the operation signal; The second data is written into the second storage unit through the first path.

5. The data processing method according to any one of claims 1 to 4, wherein: The storage device includes a precharge circuit, the second path includes a read word line and a third bit line, and the read word line is used to control the third bit line to discharge; The controlling the second path connected between the storage module and the control module to perform a read operation includes: controlling the pre-charging circuit to stop charging the third bit line; The read word line is controlled to connect to the second path, and the third bit line is controlled to discharge, so as to read the third data to be read by the operation signal, thereby completing this read operation.

6. The data processing method according to any one of claims 1 to 5, wherein: In a case where the operation signal indicates that a read operation is required, the data processing method further includes: When the operation signal indicates that a single read operation is required, controlling the first path to perform a read operation, or controlling the second path to perform a read operation; When the operation signal indicates that two read operations are required, the first path and the second path are controlled to perform read operations respectively.

7. The data processing method according to claim 6, wherein: The storage device includes a precharge circuit, the first path includes a read / write word line, a first bit line and a second bit line, and the read / write word line is used to control the first bit line and the second bit line to discharge; The controlling the first path to perform a read operation includes: controlling the precharge circuit to stop charging the first bit line and the second bit line; The read / write word line is controlled to connect to the first path, and at least one of the first bit line and the second bit line is controlled to discharge, so as to read the fourth data to be read by the operation signal, thereby completing this read operation.

8. The data processing method according to any one of claims 1 to 7, wherein: The storage device includes a precharge circuit, the first path includes a read / write word line, a first bit line and a second bit line, and the read / write word line is used to control the first bit line and the second bit line to discharge; In a case where the operation signal indicates that a write operation is required, the data processing method further includes: controlling the precharge circuit to stop charging the first bit line and the second bit line; The read / write word line is controlled to connect to the first path, and the fifth data to be written by the operation signal is written into the storage module through the first bit line and the second bit line, thereby completing this write operation.

9. The data processing method according to any one of claims 1 to 8, wherein: In a case where the operation signal indicates that a read operation and a write operation need to be performed, the data processing method further includes: controlling the first path to perform a read operation and a write operation; or, The first path is controlled to perform a write operation, and the second path is controlled to perform a read operation.

10. A storage device, wherein: The storage device includes: a storage module and a control module; A first path and a second path are connected between the control module and the storage module; The control module is configured to perform a read operation and a write operation through the first path and perform a read operation through the second path, thereby realizing two reads and one write for the data of the storage module. The storage device according to claim 10 , wherein: The first path includes a first transistor, a second transistor, a first port and a second port, and the second path includes a third transistor, a fourth transistor and a third port; The first end of the first transistor, the first end of the second transistor, and the first end of the third transistor are respectively connected to the latch, the second end of the first transistor is connected to the first port, the second end of the second transistor is connected to the second port, the second end of the third transistor is connected to the first end of the fourth transistor, and the second end of the fourth transistor is connected to the third port.

12. The storage device according to claim 11, wherein The first path includes: a read / write word line and a first bit line and a second bit line, wherein the first bit line and the second bit line are a pair of complementary bit lines; The first end of the read / write word line is connected to the control module, and the second end of the read / write word line is connected to the control end of the first transistor and the control end of the second transistor respectively; The first port is connected to a first end of the first bit line and a first end of the second bit line, the second port is connected to a first end of the first bit line and a first end of the second bit line, the second end of the first bit line is connected to a second end of the first transistor, and the second end of the second bit line is connected to a second end of the second transistor; The control module is configured to control the read / write word line to connect the first transistor and the second transistor to connect the first path, and to control at least one of the first bit line and the second bit line to discharge, thereby reading data from at least one eight-transistor storage cell in the storage module through the first port to implement a read operation; and to control the first bit line and the second bit line to write data into at least one eight-transistor storage cell in the storage module through the second port to implement a write operation.

13. The storage device according to any one of claims 10 to 12, wherein: The second path includes a read word line and a third bit line; A first end of the read word line is connected to the control module, and a second end of the read word line is connected to the control end of the fourth transistor; The third port is connected to the first end of the third bit line, and the second end of the third bit line is connected to the second end of the fourth transistor; The control module is used to control the read word line to connect the third transistor and the fourth transistor to connect the second path, and control the third bit line to discharge, so as to read out the data of at least one eight-transistor storage unit in the storage module through the third port to realize the read operation.

14. The storage device according to any one of claims 10 to 13, wherein: The storage device includes an addressing module; The addressing module is connected between the control module and the storage module; The addressing module is used to determine the storage unit corresponding to any address data from the multiple eight-transistor storage units of the storage module.

15. The storage device according to claim 14, wherein: The addressing module includes a first addressing device and a second addressing device; A first end of the first addressing device is connected to the control module, and a second end of the first addressing device is connected to a read / write word line and a read word line in the first path; A first end of the second addressing device is connected to the control module, and a second end of the second addressing device is connected to the first bit line and the second bit line in the first path; The first addressing device is used to determine the row corresponding to any one of the address data from the multiple eight-transistor storage units of the storage module; The second addressing device is used to determine the column corresponding to any address data from the multiple eight-transistor storage units of the storage module.

16. The storage device according to any one of claims 10 to 15, wherein: The storage device includes a pre-charge circuit; The pre-charging circuit is connected between the control module and the storage module; The precharge circuit is used to charge the bit lines in the storage device to a target voltage after the read and write operations are completed.

17. The storage device according to any one of claims 10 to 15, wherein: The control module includes a pre-decoding circuit and a control circuit; The pre-decoding circuit is used to pre-decode any address data and transmit the decoded address data to the first addressing device; The control circuit is used to control the interaction of various components in the storage device.

18. The storage device according to claim 12, wherein: The memory device includes a first read circuit; A first end of the first reading circuit is connected to the first port, and a second end of the first reading circuit is connected to a first end of the first bit line and a first end of the second bit line; The first reading circuit is used to amplify and latch a signal carrying data read from the storage module through the first path, and output a first processed signal from the first port.

19. The storage device according to claim 12, wherein: The storage device includes a write circuit; A first end of the write circuit is connected to the second port, and a second end of the write circuit is connected to a first end of the first bit line and a first end of the second bit line; The write circuit is used to write data into the first bit line and the second bit line based on the instruction of the control module, and then write the data into the storage module.

20. The storage device according to claim 13, wherein The memory device includes a second read circuit; A first end of the second reading circuit is connected to the control module, and a second end of the second reading circuit is connected to the third bit line; The second reading circuit is used to amplify and latch a signal carrying data read from the storage module through the second path, and output a second processed signal from the second port.

21. A computer-readable storage medium having a computer program stored thereon, wherein: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

22. A computer program product comprising a computer program or instructions, wherein: When the computer program or instruction is executed by a processor, the steps of the method according to any one of claims 1 to 9 are implemented.

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