Interleaving method and communication apparatus

Abstract

An interleaving method and a communication apparatus. The method comprises: on the basis of a PBCH payload interleaver, interleaving a PBCH payload, so as to obtain a first interleaved sequence, wherein the PBCH payload interleaver comprises A positions and values corresponding to the A positions, the A positions correspond to A bits of the PBCH payload on a one-to-one basis, and the value G(j) corresponding to a jth position among the A positions indicates that the bit among the A bits that corresponds to the jth position is interleaved to the G(j) position of the A bits; acquiring a second interleaved sequence having a length of K, wherein the second interleaved sequence is obtained by cascading 24-bit cyclic redundancy check (CRC) to the first interleaved sequence, and K=A+24; and on the basis of a distributed cyclic redundancy check (DCRC) interleaver having the length of K, interleaving the second interleaved sequence, so as to obtain a third interleaved sequence. The method can support PBCH payload interleaving of a PBCH payload with more than 32 bits.

Description

Interleaving method and communication device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on March 26, 2024, with application number 202410358385.2 and application name “Interleaving Method and Communication Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of coding, and more particularly, to an interleaving method and a communication device. Background Art

[0003] The physical broadcast channel (PBCH) carries the minimum information required to access the system. Next-generation mobile communication technologies may modify the PBCH content based on new application scenarios. For example, it may indicate at least one relevant item in scenarios such as Integrated Sensing and Communication (ISAC), high-frequency, or extremely high-frequency communication.

[0004] As the demand for PBCH indication increases, the existing payload interleaver length is insufficient to support PBCH payloads with more bits. Therefore, the PBCH payload interleaver needs to be redesigned. Summary of the Invention

[0005] The embodiments of the present application provide an interleaving method and a communication device that can support PBCH payload interleaving for PBCH payloads exceeding 32 bits.

[0006] On the first aspect, an interleaving method is provided, which can be executed by a transmitting device. Unless otherwise specified, the "transmitting device" in this application can refer to the transmitting device itself (for example, a network device, a terminal device), or a component in the transmitting device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can implement all or part of the functions of the transmitting device.

[0007] The method includes: generating a physical broadcast channel (PBCH) payload of A bits, where A is greater than 32 and A is an integer multiple of 8; interleaving the PBCH payload based on a PBCH payload interleaver to obtain a first interleaving sequence, where the PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions correspond one-to-one to the A bits of the PBCH payload, a value G(j) corresponding to the j-th position of the A positions indicates that the first bit is interleaved to the G(j)-th position of the A bits, and the first bit is the bit corresponding to the j-th position of the A bits; obtaining a second interleaving sequence with a length of K, where the second interleaving sequence is obtained by concatenating the first interleaving sequence with a 24-bit cyclic redundancy check (CRC), where K=A+24; and interleaving the second interleaving sequence based on a distributed cyclic redundancy check (DCRC) interleaver with a length of K to obtain a third interleaving sequence.

[0008] The above technical solution can support PBCH payload interleaving for PBCH payloads exceeding 32 bits.

[0009] On the second aspect, a deinterleaving method is provided, which can be performed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0010] The method includes: obtaining a third interleaving sequence of K bits, wherein the third interleaving sequence is a sequence obtained by interleaving an A-bit physical broadcast channel (PBCH) payload through a PBCH interleaver of length A, concatenating a 24-bit cyclic redundancy check (CRC) and then interleaving the A-bit physical broadcast channel (PBCH) payload through a distributed cyclic redundancy check (DCRC) interleaver of length K, wherein A is greater than 32, and A is an integer multiple of 8, and K=A+24. The PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions correspond one-to-one to the A bits of the PBCH payload, and a value G(j) corresponding to the j-th position of the A positions indicates that a first bit is interleaved to the G(j)-th position of the A bits, and the first bit is the bit corresponding to the j-th position of the A bits; deinterleaving the third interleaving sequence based on the DCRC interleaver to obtain a second interleaving sequence; obtaining a first interleaving sequence with a length of A, wherein the first interleaving sequence is a sequence obtained by removing the last 24 bits of the second interleaving sequence; and deinterleaving the first interleaving sequence based on the PBCH payload interleaver to obtain the PBCH payload.

[0011] For the beneficial effects of the second aspect, please refer to the description of the first aspect and will not be repeated here.

[0012] On the third aspect, a decoding method is provided, which can be executed by a receiving device. Unless otherwise specified, the "receiving device" in this application can refer to the receiving device itself (for example, a network device, a terminal device), or a component in the receiving device (for example, a processor, a chip, or a chip system, etc.), or it can also be a logical module or software that can realize all or part of the functions of the receiving device.

[0013] The method includes: obtaining a codeword sequence, which is a sequence obtained by encoding a third interleaving sequence based on K bits, the third interleaving sequence is a sequence obtained by interleaving an A-bit PBCH payload through a PBCH interleaver with a length of A, concatenating a 24-bit cyclic redundancy check (CRC), and then interleaving through a distributed cyclic redundancy check (DCRC) interleaver with a length of K, wherein A is greater than 32, and A is an integer multiple of 8, K=A+24, the PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions correspond one-to-one to the A bits of the PBCH payload, the value G(j) corresponding to the j-th position of the A positions indicates that the first bit is interleaved to the G(j)-th position of the A bits, and the first bit is the bit corresponding to the j-th position of the A bits; decoding the codeword sequence to obtain partial bits or all bits of the third interleaving sequence, wherein the partial bits include 1 bit in the PBCH payload except for a half-frame indication, C bits related to a time or frequency indication, and N sfn The remaining bits other than the system frame number SFN bits, C is greater than or equal to 3, N sfn Greater than or equal to 10; deinterleave the third interleaved sequence based on the DCRC interleaver to obtain a second interleaved sequence; obtain a first interleaved sequence of length A, where the first interleaved sequence is a sequence obtained by removing the last 24 bits of the second interleaved sequence.

[0014] For example, the obtained codeword sequence can be the codeword sequence A received by the receiving device from the transmitting device, and the codeword sequence A can be the codeword sequence obtained after the PBCH payload is interleaved, cascaded 24-bit CRC, DCRC interleaved, encoded, rate matched and modulated.

[0015] Optionally, when the receiving device has not yet accessed the cell, that is, in the scenario of initial access to the cell, the receiving device can perform polarization decoding on the obtained codeword sequence to obtain all bits in the third interleaved sequence, including all bits of the PBCH payload, that is, 1 bit of the above-mentioned half-frame indication, C bits related to the time or frequency indication, N sfn SFN bits and remaining bits.

[0016] Optionally, after successfully accessing the cell, the receiving device can perform polarization decoding on the obtained codeword sequence to obtain part of the bits in the third interleaved sequence, which includes 1 bit in the PBCH payload except the half-frame indication, C bits related to the time or frequency indication, and N sfn The remaining bits besides the SFN bits.

[0017] In the above technical solution, if the receiving end device has successfully accessed the cell, due to the 1 bit of half-frame indication in the PBCH payload during initial access, C key bits and N sfn bits (the 1+C+N sfn bits can be regarded as frozen bits) are already known, so the receiving end device does not need to decode the obtained codeword sequence to obtain the above 1+C+N in the third interleaved sequence. sfn bits, it is only necessary to decode the obtained codeword sequence to obtain the third interleaved sequence except 1+C+N sfn bits, thereby improving the decoding performance of PBCH.

[0018] In certain implementations of the first, second, and third aspects, the PBCH payload includes 1 bit for half-frame indication, C bits related to time or frequency indication, and N bits for half-frame indication. sfn SFN bits, where C is greater than or equal to 3, N sfn Greater than or equal to 10.

[0019] In certain implementations of the first, second and third aspects, A=40, the value of the position in the A positions corresponding to 1 bit of the half-frame indication is 1, and the values ​​of the positions in the A positions corresponding to C bits related to the time or frequency indication include 8, 6, and 4.

[0020] The above technology is compatible with existing standards and retains the order of importance of key bits in existing standards.

[0021] In certain implementations of the first, second and third aspects, A=48, the value of the position in the A positions corresponding to 1 bit of the half-frame indication is 1, and the values ​​of the positions in the A positions corresponding to C bits related to the time or frequency indication include 9, 6, and 3.

[0022] The above technical solution is compatible with existing standards and retains the order of importance of key bits in existing standards.

[0023] In certain implementations of the first, second, and third aspects, the 1-bit half-frame indication is located at the 0th position of the third interleaved sequence, the C bits related to the time or frequency indication are located at the 1st position to the Cth position of the third interleaved sequence, and N sfnThe SFN bits are located in the C+1th position to the A-1th position of the third interleaving sequence, and the reliability is located in the last N sfn N sfn locations.

[0024] The above technical solution can achieve unequal error protection for key bits when the PBCH payload exceeds 32 bits, and achieve PBCH bit-hopping decoding in specific scenarios (such as the scenario of device access to the system), thereby effectively improving the PBCH decoding performance.

[0025] In certain implementations of the first, second, and third aspects, the 0th to Nth positions of the A positions of the PBCH payload interleaver are sfn -1 position and N sfn The SFN bits correspond one to one from the most significant bit MSB to the least significant bit LSB, and the Nth of the A positions of the PBCH payload interleaver is sfn The Nth position of the PBCH payload interleaver corresponds to 1 bit of the half-frame indication. sfn +1 position to Nth sfn +C positions and C bits related to time or frequency indication correspond one to one, and the A positions of the PBCH payload interleaver except the 0th position to the Nth position sfn The remaining positions outside the +C positions correspond one-to-one to the remaining bits in the PBCH payload.

[0026] In the above technique, the four types of bits are mapped one-to-one to the A positions of the PBCH payload interleaver. This method decouples the meaning of the PBCH payload interleaver from the original PBCH payload bits, ensuring compatibility. If the meaning of the i=28th position in the PBCH payload changes in the future, the PBCH payload interleaver will not be affected. Furthermore, this method can simplify the payload interleaver design.

[0027] In certain implementations of the first aspect, the second aspect, and the third aspect, the C bits related to time or frequency indication include bits indicating the time-frequency position of the synchronization signal block SSB.

[0028] In certain implementations of the first, second, and third aspects, the PBCH payload includes 1 bit indicating a half frame, C bits related to time or frequency indication, and N bits. sfn The remaining bits other than the SFN bits include bits indicating awareness and / or energy saving.

[0029] In certain implementations of the first, second, and third aspects, A=40, N sfn =10, C=4, and the corresponding PBCH payload interleaver is shown in Table #1.

[0030] Table #1

[0031] In certain implementations of the first, second, and third aspects, A=40, N sfn =11, C=4, and the corresponding PBCH payload interleaver is shown in Table #2.

[0032] Table #2

[0033] In certain implementations of the first, second, and third aspects, when A=40, the sequence corresponding to the DCRC interleaver with a length of 64 is {1, 4, 6, 8, 10, 11, 13, 15, 18, 19, 20, 22, 23, 26, 27, 29, 32, 34, 38, 39, 40, 2, 5, 7, 9, 12, 14, 16, 21, 24, 28, 30, 33, 35, 41, 0, 3, 17, 25, 31, 36, 42, 37, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}.

[0034] In certain implementations of the first, second, and third aspects, A=48, N sfn =10, C=4, and the corresponding PBCH payload interleaver is shown in Table #3.

[0035] Table #3

[0036] In certain implementations of the first, second, and third aspects, A=48, N sfn =11, C=4, and the corresponding PBCH payload interleaver is shown in Table #4.

[0037] Table #4

[0038] In certain implementations of the first, second, and third aspects, when A=48, the sequence corresponding to the DCRC interleaver of length 72 is {1, 3, 6, 9, 12, 14, 16, 18, 19, 21, 23, 26, 27, 28, 30, 31, 34, 35, 37, 40, 42, 46, 47, 48, 0, 2, 4, 7, 10, 13, 15, 17, 20, 22, 24, 29, 32, 36, 38, 41, 43, 49, 5, 8, 11, 25, 33, 39, 44, 50, 45, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71}.

[0039] In certain implementations of the first, second and third aspects, 8M bits in the PBCH payload come from the master information block MIB message, and 8N bits in the PBCH payload come from the L1 layer, A=8M+8N, and M and N are both positive integers.

[0040] In certain implementations of the first, second, and third aspects, the 1 bit of the half-frame indication and the C key bits are included in 8N bits, where N sfn SFN bits are included in 8N bits and 8M bits.

[0041] In certain implementations of the first, second, and third aspects, the PBCH payload includes 1 bit indicating a half frame, C bits related to time or frequency indication, and N bits. sfn The remaining bits except the SFN bits are included in the 8M bits.

[0042] In a fourth aspect, a communication device is provided, which is configured to execute the method provided by any of the above aspects or implementations thereof. Specifically, the device may include units and / or modules, such as a processing unit and / or a transceiver unit, configured to execute the method provided by any of the above aspects or implementations thereof.

[0043] In one implementation, the apparatus is a transmitting device or a receiving device. When the apparatus is a transmitting device or a receiving device, the transceiver unit may be a transceiver, an input / output interface, or a communication interface; and the processing unit may be at least one processor. Optionally, the transceiver is a transceiver circuit. Optionally, the input / output interface is an input / output circuit.

[0044] In another implementation, the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device. When the apparatus is a chip, chip system, or circuit used in a transmitting device or a receiving device, the transceiver unit may be an input / output interface, interface circuit, output circuit, input circuit, pin, or related circuit on the chip, chip system, or circuit; and the processing unit may be at least one processor, processing circuit, or logic circuit.

[0045] In a fifth aspect, a communication device is provided, which includes: a memory for storing programs; and at least one processor for executing computer programs or instructions stored in the memory to execute the method provided by any one of the above aspects or its implementation.

[0046] In one implementation, the apparatus is a transmitting end device or a receiving end device.

[0047] In another implementation, the apparatus is a chip, a chip system, or a circuit used in a transmitting device or a receiving device.

[0048] In a sixth aspect, a communication device is provided, comprising: at least one processor and a communication interface, wherein the at least one processor is configured to retrieve a computer program or instruction stored in a memory through the communication interface to execute the method provided by any one of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0049] In one implementation, the device further includes the memory.

[0050] In a seventh aspect, a processor is provided for executing the methods provided in the above aspects.

[0051] For the operations such as sending and acquiring / receiving involved in the processor, unless otherwise specified, or if they do not conflict with their actual functions or internal logic in the relevant descriptions, they can be understood as operations such as processor output, reception, and input, or as sending and receiving operations performed by the radio frequency circuit and antenna. This application does not limit this.

[0052] In an eighth aspect, a computer-readable storage medium is provided, which stores program code for execution by a device, and the program code includes a method for executing any one of the above aspects or its implementation method.

[0053] In a ninth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the method provided by any one of the above aspects or its implementation.

[0054] In a tenth aspect, a chip is provided, comprising a processor and a communication interface, wherein the processor reads instructions stored in a memory through the communication interface and executes the method provided by any of the above aspects or implementations thereof. The communication interface may be implemented in hardware or software.

[0055] Optionally, as an implementation method, the chip also includes a memory, in which a computer program or instruction is stored, and the processor is used to execute the computer program or instruction stored in the memory. When the computer program or instruction is executed, the processor is used to execute the method provided by any of the above aspects or its implementation methods.

[0056] When the method provided in this application is executed by a chip, this application does not limit the number of chips that implement the method. For example, the method can be executed by one chip or by two or more chips. Furthermore, when the number of chips implementing the method of this application is two or more, the chip manufacturers are not limited and can be the same manufacturer or different manufacturers.

[0057] In an eleventh aspect, a communication system is provided, comprising at least one of the transmitting device or the receiving device described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] FIG1 is a schematic diagram of a network architecture applicable to an embodiment of the present application.

[0059] FIG2 is a schematic diagram of the information transmission process.

[0060] FIG3 is a schematic diagram of 8×8 Polar code encoding.

[0061] FIG4 is a schematic flowchart of an interleaving method 400 provided in this application.

[0062] FIG5 is a schematic block diagram of a communication device 1000 provided in an embodiment of the present application.

[0063] FIG6 is a schematic block diagram of a communication device 1100 provided in an embodiment of the present application. DETAILED DESCRIPTION

[0064] To facilitate understanding of the embodiments of the present application, the following points are explained before introducing the embodiments of the present application.

[0065] "For indicating" or "indicating" can include direct indication and indirect indication, or "for indicating" or "indicating" can be explicitly and / or implicitly indicated. The various digital numbers such as first, second, etc. are only used for the convenience of description and are not used to limit the scope of the embodiments of the present application, such as distinguishing different messages, different information, etc. "Pre-definition" can be implemented by pre-saving corresponding codes, tables or other methods that can be used to indicate relevant information in the device. The present application does not limit its specific implementation method. The "protocol" involved may refer to a standard protocol in the field of communications, for example, it may include the long term evolution (LTE) protocol, the new radio (NR) protocol and related protocols used in future communication systems. The present application does not limit this. Words such as "exemplary", "for example", "exemplarily", "as (another) example" are used to indicate examples, illustrations or explanations. Any embodiment or design described as an "example" in this application should not be interpreted as being more preferred or more advantageous than other embodiments or design schemes. The terms "including", "comprising", "having" and their variations all mean "including but not limited to", unless otherwise specifically emphasized. "At least one" means one or more, and "more than one" means two or more. "At most one" means one or zero. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b and c can mean: a, or b, or c, or a and b, or a and c, or b and c, or a, b and c. Where a, b and c can be single or multiple, respectively. Descriptions of network element A sending a message, information, or data to network element B, or network element B receiving a message, information, or data from network element A, are intended to clarify the network element to which the message, information, or data is sent, and do not limit whether the messages, information, or data are sent directly or indirectly through other network elements. Phrases such as "when," "under the circumstances," "if," and "if" all imply that the device will take appropriate action under certain objective circumstances. They do not specify a time limit, do not require the device to perform a judgment action, and do not imply any other limitations.

[0066] In addition, the network architecture and business scenarios described in the embodiments of the present application are intended to more clearly illustrate the technical solutions of the embodiments of the present application, and do not constitute a limitation on the technical solutions provided in the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of network architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0067] A communication system to which the embodiments of the present application can be applied is described below.

[0068] The embodiments of the present application can be applied to various communication systems, including but not limited to: fifth generation (5G) system, LTE system, long term evolution-advanced (LTE-A) system, LTE frequency division duplex (FDD) system, LTE time division duplex (TDD) system, etc. It can also be applied to future communication systems, such as the sixth generation mobile communication system. In addition, it can also be applied to device to device (D2D) communication, vehicle-to-everything (V2X) communication, machine to machine (M2M) communication, machine type communication (MTC), Internet of Things (IoT) communication system, narrowband Internet of Things (NB-IoT) system or other communication systems. In addition, the present invention can also be extended to similar wireless communication systems, such as wireless-fidelity (WiFi), worldwide interoperability for microwave access (WIMAX), and communication systems related to the 3rd Generation Partnership Project (3GPP), without limitation.

[0069] A communication system applicable to embodiments of the present application may include one or more transmitting devices and one or more receiving devices. Optionally, one of the transmitting device and the receiving device may be a terminal device, and the other may be a network device. Optionally, both the transmitting device and the receiving device may be terminal devices. Optionally, both the transmitting device and the receiving device may be network devices.

[0070] Figure 1 is a schematic diagram of a network architecture applicable to an embodiment of the present application. As shown in Figure 1, the embodiment of the present application can be applied to both uplink data transmission and downlink data transmission. Figure 1 only takes uplink data transmission or downlink data transmission between a network device and two terminal devices (such as terminal device 1 and terminal device 2) as an example. In uplink data transmission, the transmitting device in this article is a terminal device, and the receiving device is a network device; conversely, in downlink data transmission, the transmitting device is a network device, and the receiving device is a terminal device. In addition, the applicability of the embodiments of the present application in other communication scenarios is not limited. For example, it can also be applied to sidelink communications.

[0071] The terminal device of the present application may also be referred to as user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, mobile terminal (MT), remote station, remote terminal, mobile device, user terminal, terminal, drone, wireless communication device, user agent or user device, etc. The terminal device in the embodiments of the present application may refer to a device that provides voice and / or data connectivity to a user and can be used to connect people, objects and machines, such as a handheld device with wireless connection function, a vehicle-mounted device, etc. The terminal device in the embodiments of the present application can be a mobile phone, a tablet computer, a laptop computer, a PDA, a mobile internet device (MID), a wearable device, a virtual reality (VR) device, an augmented reality (AR) device, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in remote medical surgery, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc.

[0072] The network device of the present application may be a device with wireless transceiver functions, and the network device may be a device that provides wireless communication function services, usually located on the network side, including but not limited to the next-generation base station (gNodeB, gNB) in the 5G system, the base station in the sixth-generation mobile communication system, the base station in the future mobile communication system, or the access node in the wireless fidelity (WiFi) system, the evolved node B (eNB) in the long-term evolution (LTE) system, the radio network controller (RNC), the node B (NB), the base station controller (BSC), the home base station (for example, home evolved NodeB or home Node B, HNB), the base band unit (BBU), the transmission reception point (TRP), the transmitting point (TP), the base transceiver station (BTS), the satellite, the drone, etc. In a network structure, the network device may include a centralized unit (CU) node, or a distributed unit (DU) node, or a RAN device including a CU node and a DU node, or a RAN device including a control plane CU node and a user plane CU node, and a DU node, or the network device may also be a wireless controller, relay station, vehicle-mounted device, and wearable device in a cloud radio access network (CRAN) scenario. In addition, the base station may be a macro base station, a micro base station, a relay node, a donor node, or a combination thereof. The base station may also refer to a communication module, a modem, or a chip for being set in the aforementioned device or apparatus. The base station may also be a mobile switching center and a device that performs the base station function in D2D, V2X, and M2M communications, a network-side device in a 6G network, or a device that performs the base station function in future communication systems. The base station can support networks with the same or different access technologies without limitation.

[0073] Unless otherwise specified, the device used to implement the function of a terminal device or network device in this application may refer to the terminal device or network device itself, or may refer to a device that can support the terminal device or network device to implement the function, such as a chip system or chip, specifically, a system on a chip (SoC) or a modem. The device can be installed in the terminal device or network device. In the embodiments of the present application, the chip system can be composed of chips, or it can include chips and other discrete devices.

[0074] It should also be noted that some embodiments herein use the 5G system as an example to describe specific solution details. It is understood that when this solution is applied to other communication systems, such as the LTE system or future communication systems, the messages, channels, or information in the solution can be replaced with messages, channels, or information in other communication systems that can implement corresponding functions, and this application does not limit this.

[0075] In addition, the embodiments of the present application can be applied to various application scenarios, such as high-throughput scenarios, high-reliability scenarios, low-latency scenarios, high-reliability and low-latency scenarios, or low-power scenarios. Among them, the high-throughput scenario can be, for example, an enhanced mobile broadband (eMBB) scenario, the high-reliability and low-latency scenario can be, for example, a URLLC (ultra reliable low latency communication) scenario, and the low-power scenario can be, for example, an M2M scenario, an MTC scenario, or an IoT scenario.

[0076] Figure 2 is a schematic diagram of the information transmission process. As shown in Figure 2, information is sent by the source, undergoes source coding, channel coding, modulation, air interface transmission, demodulation, channel decoding, source recovery and other processing, and arrives at the destination, completing the transmission of information from the source to the destination. Among them, the processing shown in the upper layer of Figure 2 (including source coding, channel coding and modulation, etc.) is performed at the transmitting end device, and the processing shown in the lower layer (including demodulation, channel decoding, source recovery, etc.) is performed at the receiving end device. The embodiments of the present application mainly relate to source coding, channel coding, channel decoding and source recovery shown in Figure 2.

[0077] The current NR physical broadcast channel (PBCH) payload length is 32 bits, of which 24 bits come from the master information block (MIB), and the remaining 8 bits are added by the L1 layer (i.e., the physical layer). The 6 bits from the 2nd to 7th bit from the MIB are the upper 6 bits of the system frame number (SFN), and the first 4 bits of the 8 bits from the L1 layer are the lower 4 bits of the system frame number, which together constitute the 10-bit SFN. The first bit of the remaining 4 bits from the L1 layer (i.e., the 5th bit of the 8 bits from the L1 layer) is the half-frame indicator, and the last 3 bits are used for the synchronization signaling block (SSB) timing indicator or Kssb indicator, or idle bits. The 32 bits of the PBCH payload have different uses and different reliability requirements for the polar code. A payload interleaver and a distributed cyclic redundancy check (DCRC) interleaver are used to perform two-layer interleaving on these 32 payloads. Finally, the four important timing bits (the one bit for the half-frame indicator and the three bits related to the SSB) are interleaved into the first four positions of the 32 bits to achieve better unequal error protection. The one bit for the half-frame indicator needs to be interleaved into the first position, and the 10-bit SFN is interleaved into the 10 least reliable positions of the 32 bits, excluding the first four positions. The meaning of the 32 bits in the current NR PBCH payload is shown in Table 1.

[0078] Table 1

[0079] Table 2 shows the current NR PBCH payload processing flow and results. As shown in Table 2, the 32 bits in the PBCH payload are first interleaved using the PBCH payload interleaver shown in Table 3. Afterwards, payload scrambling and a cascaded 24-bit cyclic redundancy check (CRC) are performed, and then interleaving is performed using the DCRC interleaver shown in Table 4. The interleaved sequence is then generated (i.e., the sequence corresponding to the second-to-last column in Table 2). The interleaved sequence is then fed into the Polar encoder for Polar encoding.

[0080] Table 2

[0081] Table 3

[0082] In Table 3, each j corresponds to a bit in the PBCH payload, and G(j) indicates that the bit corresponding to j needs to be interleaved to the G(j)th position. Specifically, for j = 0 to 9, the interleaving object is the 10 SFN bits from the most significant bit (MSB) to the least significant bit (LSB) according to the system frame number. The interleaving object for j = 10 is the 1 bit of the half-frame indication. The interleaving object for j = 11 to 13 is the 3 bits related to the SSB. The remaining 18 bits for j = 14 to 31 are the bits indicating non-timing information in the MIB.

[0083] It can be understood that the interleaving object corresponding to j=10 in Table 3 is 1 bit of the half-frame indication, and the corresponding value G(10)=0, but the initial position of the 1 bit of the half-frame indication in Table 1 is the 28th bit, so j=10, G(i)=0 in the PBCH payload interleaver in Table 3 can be replaced with i=28, G(i)=0. Similar replacements can also be made for other payload bits, which will not be repeated here.

[0084] Table 4

[0085] It can be understood that, since a 24-bit CRC is concatenated after PBCH payload interleaving, the length of the DCRC interleaver is 56. IL (m) represents the 56-bit sequence obtained by concatenating the 24-bit CRC (i.e., the sequence corresponding to the fourth column from the bottom in Table 2). IL The bits at (m) positions are interleaved to the mth position.

[0086] The following is a brief introduction to the Polar code used in the PBCH payload. Polar code is the first channel coding scheme rigorously proven to achieve Shannon channel capacity. It features excellent error correction performance and low decoding complexity. It has been selected by 3GPP as the coding scheme for control channels (uplink and downlink) in 5G eMBB scenarios.

[0087] Figure 3 is a schematic diagram of 8×8 Polar code encoding. The bits to be encoded are classified into two categories: frozen bits and information (data) bits, based on the reliability of the corresponding bit subchannel. Bit positions with lower reliability are designated as frozen bits, which are typically 0 and known to both the sender and receiver during actual transmission. Bit positions with higher reliability are designated as information bits, which carry information bits during actual transmission. As shown in Figure 3, u7, u6, u5, and u3 are the four bits with the highest reliability and are designated as information bits. U4, u2, u1, and u0 are the four bits with the lowest reliability and are designated as frozen bits.

[0088] It can be understood that the sequence of length 56 after two layers of interleaving in Table 2 (i.e. the sequence corresponding to the second to last column of Table 2) can be placed in 2 9 = In the 56 positions (i.e., information bits) with higher reliability in the 512-bit sub-channel, the bits in the remaining bit positions (i.e., frozen bits) with lower reliability are set to 0, and the actual bits to be encoded are the 512 bits corresponding to the 512 bit positions.

[0089] As shown in Figure 3, u0 to u7 on the far left are 8 bits to be encoded, of which u0 to u2 and u4 are information bits (the corresponding bit position reliability is low), and u3, u5 to u7 are frozen bits (the corresponding bit position reliability is high). After encoding, the 8 codeword bits 01010101 on the far right are recorded as c0 to c7 respectively. The transmitting device sends c0 to c7 to channel W.

[0090] In recent years, with the inclusion of polar codes in the 5G standard, research on polar code decoding has become a hot topic in the communications field. Currently, mainstream polar code decoding methods can be divided into two categories based on their decoding timing: sequential decoding and non-sequential decoding. Sequential decoding refers to decoding based on the natural timing of the polar code design. Non-sequential decoding, on the other hand, refers to decoding based on other polar code structures (such as the Tanner graph and Trellis graph) and outputting decoding results in parallel. Currently, the main sequential polar code decoding algorithms include SC decoding, Successive Cancellation List (SCL) decoding, Successive Cancellation Stack (SCS) decoding, and CRC-Aided Successive Cancellation List (CA-SCL) decoding. Non-sequential decoding methods mainly include Belief Propagation (BP) decoding. In terms of decoding performance, SC decoding suffers the worst. SCL decoding significantly improves upon the previous approach. Combined with CA-SCL after CRC checking, Polar codes can outperform low-density parity-check (LDPC) codes and concatenated codes (Turbo codes). Therefore, SCL and CA-SCL decoding are currently the primary methods used in practical systems.

[0091] The following is a brief description of the Polar code decoding process based on the description in Figure 3. The receiving device receives 8 codeword bits c0 to c7 from channel W, decodes the received codeword bits c0 to c7, and obtains the message sequence estimate For example, the decoding process is as follows: based on c0~c7, the decoding is Based on c0~c7 and Decoded And so on, based on c0~c7 and to Decode the last message bit At this point, all 8 message bits have been decoded. It is understandable that because the receiver knows that the 1st, 2nd, 3rd, and 5th positions are frozen bits, it can actually skip directly. and Do not decode, and Just set it to 0.

[0092] PBCH is used to carry the minimum amount of information required to access the system. The next generation of mobile communication technology standards (such as 6G) may modify or supplement the requirements of MIB / PBCH based on features such as energy saving, perception, and multi-beam concurrency. For example, information related to multi-beam and energy saving needs can be added to the PBCH payload, resulting in an increase in the number of PBCH payloads. As the number of PBCH payloads increases, the existing payload interleaver with a length of 32 is insufficient to support PBCH payloads exceeding 32 bits. Therefore, the PBCH payload interleaver needs to be redesigned.

[0093] In view of this, the present application provides an interleaving method that can effectively solve the above technical problems. The following describes an embodiment of the method proposed in the present application.

[0094] FIG4 is a schematic flow chart of an interleaving method 400 provided by the present application. The method includes the following steps.

[0095] It is understood that method 400 can be performed by a transmitting device and a receiving device. Unless otherwise specified, "transmitting device" or "receiving device" can refer to the transmitting device or receiving device itself, or can refer to a device that supports the transmitting device or receiving device to implement the function. For convenience of description, the following description uniformly uses the transmitting device and receiving device. The transmitting device can be a terminal device or a network device, and the receiving device can be a terminal device or a network device.

[0096] S410: The transmitting end device generates a PBCH payload of A bits, where A is greater than 32 and is an integer multiple of 8.

[0097] For example, A=40 or 48 or 56.

[0098] The generated A-bit PBCH payload includes 1 bit for half-frame indication, C bits related to time or frequency indication, N sfn System frame number SFN bits, and the remaining bits are used to indicate non-timing information (A-1-CN sfn ) bits, where C is greater than or equal to 3, N sfn Greater than or equal to 10.

[0099] Unless otherwise specified, the order of the bits in the generated PBCH payload is referred to as the original order of the PBCH payload in this application, and the C bits related to the time or frequency indication are referred to as C key bits in this application.

[0100] Unless otherwise specified, the A-bit PBCH payload in this application increases by X bits compared to the 32-bit PBCH payload corresponding to Table 1 (hereinafter referred to as the original PBCH payload), where X=A-32.

[0101] It can also be understood that when C is equal to 3, it means that the number of key bits in the PBCH payload is the same as the corresponding number of key bits in Table 1. When C is greater than 3, it means that the number of key bits in the PBCH payload is increased by X1 bits compared to the corresponding number of key bits in Table 1, where C = 3 + X1.

[0102] For example, the newly added X1 bit is used to indicate the time-frequency position of the SSB. Furthermore, the newly added X1 bit is used to indicate the frequency domain position of the SSB and / or the synchronization signal block index (SSB Index, SSBI) in a multi-beam scenario.

[0103] It is also understandable that when N sfn When N is equal to 10, it means that the number of SFN bits in the PBCH payload is the same as the number of SFN bits in Table 1. sfn When it is greater than 10, it means that the number of SFN bits in the PBCH payload is increased by X2 compared with the number of SFN bits in Table 1, where N sfn =10+X2.

[0104] It can also be understood that X1+X2≤X.

[0105] Illustratively, the remaining bits in the X bits except the X1 bit and the X2 bit include bits for indicating perception and / or energy saving information.

[0106] S420: The transmitting end device interleaves the PBCH payload based on the PBCH payload interleaver to obtain a first interleaving sequence.

[0107] Among them, the PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions correspond one-to-one to the A bits of the PBCH payload, the value G(j) corresponding to the j-th position of the A positions indicates that the first bit is interleaved to the G(j)-th position of the A bits, the first bit is the bit corresponding to the j-th position of the A bits of the PBCH payload, j and G(j) are both natural numbers less than A, that is, the ranges of j and G(j) are {0, 1, 2, 3, ..., A-1}.

[0108] It can be understood that the A positions each correspond to a number j, and the numbers j of the A positions are 0 to A-1 respectively, and the position numbered j indicates that the position is the j-th position among the A positions. Then, the A positions correspond one-to-one to the A bits of the PBCH payload, indicating that j=0 to A-1 respectively indicate a bit in a PBCH payload. In the present application, the j-th position among the A positions corresponds to a value G(j), and G(j) indicates that the first bit (the first bit is the bit corresponding to the j-th position among the A bits of the PBCH payload) is interleaved to the G(j)-th position of the A bits of the PBCH payload. The G(j)-th position can also be called the target position after the first bit is interleaved, that is, the target position of the first bit is the G(j)-th position among the A bits.

[0109] It can be understood that the interleaving based on the PBCH payload interleaver here can be based on the PBCH payload interleaver module / unit to realize the interleaving of the PBCH payload, for example, the interleaving of the PBCH payload can be realized by hardware or software or a combination of both, or, the interleaving based on the PBCH payload interleaver can also refer to interleaving based on the interleaver pattern. Interleaving based on the interleaver pattern can be understood as considering the essential content of the interleaving from the logical and standard expression. Therefore, the PBCH payload interleaver here can also be replaced by the interleaver pattern.

[0110] It can be understood that after the PBCH payload is interleaved, a 24-bit CRC needs to be concatenated. Therefore, if the length of the PBCH payload is A, the required DCRC interleaver length K is equal to A+24. When the length of the DCRC interleaver is determined, the DCRC interleaver can be uniquely determined by the DCRC interleaver mother sequence, and therefore, the DCRC deinterleaver can also be uniquely determined. Then, based on the interleaving result of the PBCH payload with a length of A after two layers of interleaving and the DCRC deinterleaver with a length of K, the corresponding interleaving result of the PBCH payload after PBCH payload interleaving can be inferred, thereby determining the value of the A position of the PBCH payload interleaver.

[0111] In this application, a DCRC interleaver with a length of K can be obtained based on a DCRC interleaver mother sequence. The length of the DCRC interleaver mother sequence is 164, and the mother sequence DcrcIntl is as follows:

[0112] DcrcIntl=

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[0120] Rows 70 to 92

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[0124] 36 44

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[0127] Lines 139 to 161

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[0129] Lines 162 to 164

[0130] 161 162 163

[0131] The method for determining a DCRC interleaver of length K based on the mother sequence is as follows: according to the DCRC interleaver mother sequence, determine the elements whose element values ​​are greater than or equal to 164-K (that is, skip the elements less than 164-K) to form a sequence of length K, and then subtract an offset equal to (164-K) from all element values ​​in the sequence to finally obtain a DCRC interleaver subsequence DcrcIntl_sub of length K.

[0132] %%DCRC interleaver A long sequence extraction

[0133] For example, A=40, then K=64, and the DCRC interleaver subsequence DcrcIntl_sub#1 with a length of 64 read from the mother sequence DcrcIntl is as follows:

[0134] DcrcIntl_sub#1={1 4 6 8 10 11 13 15 18 19 20 22 23 26 27 29 32 34 38 39 40 2 5 7 9 12 14 16 21 24 28 30 33 35 41 0 3 17 25 31 36 42 37 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63}

[0135] Among them, any value Π in the DCRC interleaver subsequence DcrcIntl_sub#1 with a length of 64 IL (m) represents the first position in the sequence obtained by interleaving the PBCH payload and concatenating the 24-bit CRC. IL The bits of (m) positions are interleaved to the mth position, where m is the value π IL (m) The position number in the DCRC interleaver subsequence DcrcIntl_sub#1 with a length of 64.

[0136] It can be understood that the value π IL (m) is any value contained in DcrcIntl_sub#1. For example, IL (m)=1 or 4 or 6 or 8.

[0137] From the above, we can see that m is the value Π IL (m) The position number in DcrcIntl_sub#1. Here, the position number is numbered from 0 for example. IL (m) = 1 is located at the 0th position of all values ​​of DcrcIntl_sub#1, then Π IL(m) = 1 corresponds to m = 0, for example, Π IL (m) = 15 is located at the 7th position of all values ​​of DcrcIntl_sub#1, then Π IL (m) = 15 corresponds to m = 7, for example, Π IL (m) = 0 is located at the 35th bit of all values ​​of DcrcIntl_sub#1, then Π IL (m)=0 corresponds to m=35. Based on the above example, the DCRC interleaver subsequence DcrcIntl_sub#1 with a length of 64 can be written as shown in Table 5.

[0138] Table 5

[0139] For example, A=48, then K=72, and the DCRC interleaver subsequence DcrcIntl_sub#2 with a length of 72 read from the mother DCRC interleaver mother sequence DcrcIntl is as follows:

[0140] DcrcIntl_sub#2={1 3 6 9 12 14 16 18 19 21 23 26 27 28 30 31 34 35 37 40 42 46 47 48 0 2 4 7 10 13 15 17 20 22 24 29 32 36 38 41 43 49 5 8 11 25 33 39 44 50 45 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71}

[0141] Among them, the DCRC interleaver subsequence DcrcIntl_sub#2 with a length of 72 has any value π IL (m) represents the first position in the sequence obtained by interleaving the PBCH payload and concatenating the 24-bit CRC. IL The bits of (m) positions are interleaved to the mth position, where m is the value π IL (m) The position number in the DCRC interleaver subsequence DcrcIntl_sub#2 with a length of 72. It can be understood that the DCRC interleaver subsequence DcrcIntl_sub#2 with a length of 72 can also be written as shown in Table 5, which is not repeated here.

[0142] In one possible implementation, the A positions of the PBCH payload interleaver correspond to the A bits of the PBCH payload in a one-to-one manner according to the original order of the PBCH payload. That is, the 0th position of the PBCH payload interleaver corresponds to the 0th bit (i.e., the first bit) in the original order of the PBCH payload, the 1st position of the PBCH payload interleaver corresponds to the 1st bit in the original order of the PBCH payload, and so on. The A-1th position of the PBCH payload interleaver corresponds to the A-1th bit in the original order of the PBCH payload.

[0143] Unless otherwise specified, the A positions of the PBCH payload interleaver in this application refer to the A positions corresponding to j=0 to A-1 described above.

[0144] In another possible implementation, the correspondence between the A positions of the PBCH payload interleaver and the A bits of the PBCH payload is as follows.

[0145] (1) The j=0th position to the j=Nth position among the A positions of the PBCH payload interleaver sfn -1 position and N in PBCH payload sfn The SFN bits correspond one to one from MSB to LSB.

[0146] (2) The jth position among the A positions of the PBCH payload interleaver is N sfn This position corresponds to the 1-bit half-frame indication in the PBCH payload.

[0147] (3) The jth position among the A positions of the PBCH payload interleaver is N sfn +1 position to j=Nth sfn The +C positions correspond one-to-one to the C key bits in the PBCH payload, where C = 3 + X1.

[0148] (4) Among the A positions of the PBCH payload interleaver, except the j=0 position to the j=N position sfn The remaining positions outside the +C positions correspond one-to-one to the remaining bits in the PBCH payload.

[0149] It can also be understood that the PBCH payload interleaver position j∈J occupied in (1) sfn , J sfn =[0,1,2,3,..,N sfn -1]; j∈J of the PBCH payload interleaver positions occupied in (2) hrf , J hrf =N sfn ; j∈J of the PBCH payload interleaver positions occupied in (3) ssb , J ssb =[Nsfn +1 - ,N sfn +2,N sfn +3,…,N sfn +C]; j∈J of the PBCH payload interleaver positions occupied in (4) other , J other =[N sfn +5,N sfn +6,N sfn +7,…,A-1].

[0150] It can be understood that the difference between the above two implementations is that the same bit in the PBCH payload corresponds to different positions of the PBCH payload interleaver, but the values ​​corresponding to the different positions are the same. For example, if bit #1 in the PBCH payload corresponds to the 4th position of the PBCH payload interleaver in the first implementation, the value corresponding to the 4th position is G(4) = 34. If bit #1 in the PBCH payload corresponds to the 5th position of the PBCH payload interleaver in the second implementation, the value corresponding to the 5th position is G(5) = 34.

[0151] The following specifically describes how to determine the values ​​corresponding to the A positions in the PBCH interleaver based on the correspondence between the A positions of the PBCH payload interleaver and the A bits of the PBCH payload in the second implementation manner.

[0152] (1) The values ​​corresponding to the A1 positions in the PBCH interleaver are determined based on the distributed cyclic redundancy check DCRC interleaver of length K and the target position of A1 bits. A1 bits are the bits corresponding to the A1 positions in the PBCH payload. A1 bits include 1 bit for half-frame indication, C bits related to time or frequency indication, and N sfn System frame number SFN bits, the DCRC interleaver includes K positions and values ​​corresponding to the K positions, the i-th position of the DCRC interleaver indicates that the second bit is interleaved to the i-th position, the second bit is the PBCH payload based on the PBCH payload interleaver interleaved at the P(i)-th position, P(i) is the value corresponding to the i-th position, i and P(i) are both natural numbers less than K, where,

[0153] a) The target position of the 1-bit half-frame indication is the 0th position (ie, the first position).

[0154] b) The target positions of the C bits related to the time or frequency indication are the 1st position to the Cth position.

[0155] c)N sfn The target position of the SFN bits is the C+1th position to the A-1th position, and the reliability is in the last Nsfn N sfn locations.

[0156] (2) The values ​​corresponding to the remaining A2 positions in the PBCH interleaver are the remaining values ​​from 0 to A-1 except the value corresponding to the A1 position, and A2=A-A1.

[0157] Based on the above-mentioned correspondence between the possible A positions of the PBCH payload interleaver and the A bits of the PBCH payload, the values ​​corresponding to the A positions in the PBCH payload interleaver are specifically described below.

[0158] (1) Determine j∈J sfn The corresponding N sfn The position of the SFN bits after payload interleaving G(j)

[0159] Step a: Determine N sfn The target positions of the SFN bits after the two layers of interleaving, namely the payload interleaver and the DCRC interleaver, are sorted in descending order of reliability, denoted as J sfn_target .

[0160] Among them, J sfn_target It can be obtained as follows: Since the 0th position (i.e. the first position) to the Cth position are the target positions after the 1 bit of the half-frame indication and the C key bits are interleaved, jsfn_target includes the N bits with the lowest reliability selected from the C+1th position to the A-1th position. sfn For example, the N with the lowest reliability sfn The positions are obtained according to the reliability sequence in the 5G standard.

[0161] It can be understood that when j∈J sfn When G(j)∈J sfn_target .

[0162] Step b: Determine N sfn The importance of the SFN bits, and according to N sfn The importance of SFN bits is ranked from low to high. sfn Sort by J sfn_ordered , where J sfn =[0,1,2,3,..,N sfn -1] corresponds to N sfn The SFN bits are arranged from the most significant bit (MSB) to the least significant bit (LSB).

[0163] Step c: N sfn J sfn_target The DCRC deinterleaver is performed at the position (since the DCRC interleaver is given, the DCRC deinterleaver can also be uniquely determined), and J is obtained.sfn_target_deDCRC , J sfn_target_deDCRC N sfn The position of the SFN bits after PBCH payload interleaving (before DCRC interleaving).

[0164] Step d: J sfn_ordered With J sfn_target_deDCRC One-to-one correspondence according to the reliability order, that is, J sfn_target_deDCRC Place J in the most reliable position sfn_ordered The most significant bit indicated in J sfn_target_deDCRC Place J in the position with the second highest reliability sfn_ordered The next most significant bit is indicated in , and so on.

[0165] The following example illustrates this. For example, A=40, C=4, N sfn =10.

[0166] Step a: Since the 0th position (i.e., the first position) to the 4th position are the target positions after the 1 bit of the half-frame indication and the 4 key bits are interleaved, N is selected from the 5th position to the 39th position. sfn = 10 positions with the lowest reliability, and the 10 positions are J according to their reliability from low to high. sfn_target ={23,5,26,14,24,17,16,27,6,7}.

[0167] Step b: Determine the importance of the 10 SFN bits and sort the J bits according to their importance from high to low. sfn Sort by J sfn ={0,1,2,3,4,5,6,7,8,9} corresponds to the most significant bit (MSB) to the least significant bit (LSB) of the SFN bit, for example, the sorting result is J sfn_ordered ={8,7,9,6,5,4,3,2,1,0}.

[0168] Step c: N sfn J sfn_target Perform DCRC deinterleaving at position to obtain J sfn_target_deDCRC ={7,11,14,27,9,34,32,16,13,15}.

[0169] Specifically, A=40, then the corresponding DCRC interleaver is the DCRC interleaver with a length of 64 shown in Table 5. Based on the interleaver shown in Table 5, the corresponding deinterleaver can be obtained.

[0170] Step d: J sfn_ordered With J sfn_target_deDCRCAccording to the reliability order, the values ​​G(j) corresponding to the 0th position to the 9th position (i.e., the first 10 positions) of the PBCH payload interleaver can be obtained. The specific values ​​are shown in Table 6.

[0171] Table 6

[0172] (2) Determine j∈J hrf The position G(j) of the 1-bit indicated by the corresponding half-frame after payload interleaving

[0173] Step a: Determine the target position of the half-frame indication bit after the payload interleaver and DCRC interleaver, denoted as J hrf_target ,J hrf_target =0, that is, fixed to the first position.

[0174] Step b: J hrf_target Perform DCRC deinterleaving to obtain J hrf_target_deDCRC =1, J hrf_target_deDCRC The position of the 1-bit half-frame indicator after PBCH payload interleaving.

[0175] Step c: J hrf =N sfn With J hrf_target_deDCRC =1. That is, the Nth position in A sfn The value of each position is 1.

[0176] Continuing with the example in (1), the value G(j) corresponding to the 10th position of the payload interleaver can be obtained through the description in (2). The specific values ​​are shown in Table 7.

[0177] Table 7

[0178] (3) Determine j∈J ssb The position G(j) of the corresponding C key bits after payload interleaving

[0179] Step a: Determine the target position of C key bits after the two layers of interleaving, namely the payload interleaver and the DCRC interleaver, and sort them in order of reliability from low to high, denoted as J ssb_target .

[0180] Among them, J ssb_target It can be obtained as follows: As described above, the first position (i.e., the position after the first position) to the Cth position are the target positions after the C key bits are interleaved. Therefore, J ssb_target Including the 1st position to the D-1th position.

[0181] It can be understood that when j∈J ssbWhen G(j)∈J ssb_target .

[0182] Step b: Determine the importance of the C key bits and sort the J bits according to the importance of the C key bits from low to high. ssb Sort from low to high, recorded as J ssb_ordered , where J ssb =[N sfn +1,N sfn +2,N sfn +3,…,N sfn +C] correspond to the most significant bit (MSB) to the least significant bit (LSB) of C key bits respectively.

[0183] Step c: J ssb_target Perform DCRC deinterleaving on the C positions in the ssb_target_deDCRC , J ssb_target_deDCRC is the position of the C key bits after PBCH payload interleaving.

[0184] Step d: J ssb_ordered With J ssb_target_deDCRC One-to-one correspondence according to the reliability order, that is, J ssb_target_deDCRC Place J in the most reliable position ssb_ordered The most significant bit indicated in J ssb_target_deDCRC Place J in the position with the second highest reliability ssb_ordered The next most significant bit is indicated in , and so on.

[0185] The explanation continues based on the example in (1).

[0186] Step a: Determine the target position of C=4 key bits after the two layers of interleaving by the payload interleaver and the DCRC interleaver, denoted as J ssb_target , J ssb_target ={1,2,3,4}.

[0187] Step b: Determine the importance of the four key bits and sort J according to the importance of the four key bits from high to low. ssb Sort by J ssb ={11,12,13,14} respectively correspond to the highest bit (MSB) to the lowest bit (LSB) of the 4 key bits. For example, the sorting result J ssb_ordered ={14,13,12,11}.

[0188] Step c: J ssb_target Perform DCRC deinterleaving on the C positions in the ssb_target_deDCRC ={4,6,8,10}.

[0189] Step d: J ssb_ordered With Jssb_target The values ​​G(j) corresponding to the 11th to 14th positions of the payload interleaver are obtained in a one-to-one correspondence according to the reliability order. The specific values ​​are shown in Table 8.

[0190] Table 8

[0191] (4) Determine j∈J other The position of the corresponding bit after payload interleaving G(j)

[0192] Step a: Determine J other The target position of the corresponding bit after the two layers of interleaving, namely the payload interleaver and the DCRC interleaver, is denoted as J other_target .

[0193] Among them, J other_target It can be obtained by removing J from A positions. sfn_targett_deDCRC 、J hrf_targett_deDCRC 、J ssb_target_deDCRC The remaining positions are J other_target .

[0194] Step b: J other With J other_target One to one correspondence.

[0195] The explanation continues based on the example in (1).

[0196] Step a: Remove J from 40 positions sfn_targett_deDCRC 、J hrf_targett_deDCRC 、J ssb_target_deDCRC The remaining 25 positions indicated by J other_target =[0,2,3,5,12,17,18,19,20,21,22,23,24,25,26,28,29,30,31,33,35,36,37,38,39].

[0197] Step b: J other With J other_target Thus, the values ​​G(j) corresponding to the 15th to 39th positions of the payload interleaver are obtained, and the specific values ​​are shown in Table 9.

[0198] Table 9

[0199] The above describes in detail how to determine the value of A positions. It should be noted that J in (3) ssb_ordered ={14,13,12,11} is only one possible example. When the importance of the four key bits exists in other possibilities, such as J ssb={11,12,13,14}, where {11,12,13} correspond to the most significant bit (MSB) to the least significant bit (LSB) of the 3 bits in the original PBCH payload shown in Table 1, and 14 corresponds to a newly added 1-bit key bit for indicating whether to use multi-beam concurrency. The importance of this newly added key bit is greater than the 3 bits in the original PBCH payload. Therefore, J is sorted according to the importance of the 4 key bits from high to low. ssb The sorting result is jssb_ordered = {13, 12, 11, 14}. The corresponding values ​​of the payload interleaver G(j) are shown in Table 10. It can be seen that the only difference between Table 10 and Table 9 is the values ​​corresponding to the 11th to 14th positions.

[0200] Table 10

[0201] Similarly, N in (1) sfn The definition of the importance between the SFN bits may also change, then the values ​​corresponding to the first 10 positions in the A positions will also change, which will not be repeated here.

[0202] In the above example, A=40,C=4,N sfn =10 corresponding to the specific form of the PBCH payload interleaver. A, C, N sfn The possible specific form of the payload interleaver when it is other values.

[0203] For example, A=40, C=3, N sfn =10, the corresponding payload interleaver is shown in Table 11.

[0204] Table 11

[0205] For example, A=40, C=5, N sfn =10, the corresponding payload interleaver is shown in Table 12.

[0206] Table 12

[0207] For example, A=40, C=6, N sfn =10, the corresponding payload interleaver is shown in Table 13.

[0208] Table 13

[0209] For example, A=40, C=7, N sfn =10, the corresponding payload interleaver is shown in Table 14.

[0210] Table 14

[0211] For example, A=40, C=8, N sfn =10, the corresponding payload interleaver is shown in Table 15.

[0212] Table 15

[0213] For example, A=40, C=9, N sfn =10, the corresponding payload interleaver is shown in Table 16.

[0214] Table 16

[0215] For example, A=40, C=10, N sfn =10, the corresponding payload interleaver is shown in Table 17.

[0216] Table 17

[0217] For example, A=40, C=11, N sfn =10, the corresponding payload interleaver is shown in Table 18.

[0218] Table 18

[0219] For example, A=48, N sfn =10, the corresponding payload interleaver when C=3 to 10 is shown in Table 19, and the corresponding payload interleaver when C=11 to 19 is shown in Table 20.

[0220] Table 19

[0221] Table 20

[0222] In the above example, N sfn are all equal to 10. The following example illustrates N sfn The specific form of the PBCH payload interleaver when it is not equal to 10.

[0223] For example, A=40, C=4, N sfn =11 for explanation.

[0224] (1) Determine j∈J sfn The corresponding N sfn The position of the SFN bits after payload interleaving G(j)

[0225] Step a: Since the 0th position (i.e. the first position) to the 4th position are the target positions after the 1 bit of the half-frame indication and the 4 key bits are interleaved, it is necessary to select N from the 5th position to the 39th position. sfn = 11 positions with the lowest reliability, and the 11 positions are J in descending order of reliability. sfn_target ={23,5,26,14,24,17,16,27,6,7,19}.

[0226] Step b: Determine the importance of the 11 SFN bits and sort the J bits according to their importance from high to low. sfn Sort by J sfn ={0,1,2,3,4,5,6,7,8,9,10} respectively correspond to the most significant bit (MSB) to the least significant bit (LSB) of the SFN bit. For example, the sorting result is J sfn_ordered ={9,8,10,7,6,5,4,3,2,1,0}.

[0227] Step c: N sfn J sfn_target Perform DCRC deinterleaving at position to obtain J sfn_target_deDCRC ={7,11,14,27,9,34,32,16,13,15,39}.

[0228] Step d: J sfn_ordered With J sfn_target_deDCRC According to the one-to-one correspondence in the order of reliability, the values ​​G(j) corresponding to the 0th position to the 10th position (i.e., the first 11 positions) of the payload interleaver can be obtained. The specific values ​​are shown in Table 21.

[0229] Table 21

[0230] (2) Determine j∈J hrf =11 corresponds to the position G(j) of the 1-bit half-frame indication after payload interleaving

[0231] Step a: Determine the target position of the half-frame indication bit after the payload interleaver and DCRC interleaver, denoted as J hrf_target ,J hrf_target =0, that is, fixed to the first position.

[0232] Step b: J hrf_target Perform DCRC deinterleaving to obtain J hrf_target_deDCRC =1.

[0233] Step c: J hrf =N sfn With J hrf_target_deDCRC=1. That is, the value of the 11th position in the A positions is 0. Thus, the value G(j) corresponding to the 11th position of the payload interleaver is shown in Table 22.

[0234] Table 22

[0235] (3) Determine j∈J ssb The position G(j) of the corresponding C key bits after payload interleaving

[0236] Step a: Determine the target position of C=4 key bits after the two layers of interleaving by the payload interleaver and the DCRC interleaver, denoted as J ssb_target , J ssb_target ={1,2,3,4}.

[0237] Step b: Determine the importance of the four key bits and sort J according to the importance of the four key bits from high to low. ssb Sort by J ssb ={12,13,14,15} respectively correspond to the highest bit (MSB) to the lowest bit (LSB) of the 4 key bits. For example, the sorting result J ssb_ordered ={15,14,13,12}.

[0238] Step c: J ssb_target Perform DCRC deinterleaving on the C positions in the ssb_target_deDCRC ={4,6,8,10}.

[0239] Step d: J ssb_ordered With J ssb_target_deDCRC The values ​​G(j) corresponding to the 12th to 15th positions of the payload interleaver are obtained in a one-to-one correspondence according to the reliability order. The specific values ​​are shown in Table 23.

[0240] Table 23

[0241] (4) Determine j∈J other The position of the corresponding bit after payload interleaving G(j)

[0242] Step a: Remove J from 40 positions sfn_targett_deDCRC 、J hrf_targett_deDCRC 、J ssb_target_deDCRC The remaining 24 positions indicated by J other_target =[0,2,3,5,12,17,18,19,20,21,22,23,24,25,26,28,29,30,31,33,35,36,37,38].

[0243] Step b: J other With Jother_target Thus, the values ​​G(j) corresponding to the 15th to 39th positions of the payload interleaver are obtained, and the specific values ​​are shown in Table 24.

[0244] Table 24

[0245] In the above example, A=40,C=4,N sfn =11 corresponding to the specific form of the PBCH payload interleaver. A, C, N sfn The possible specific form of the payload interleaver when it is other values.

[0246] For example, A=40, N sfn =11, C=3, and the corresponding payload interleaver is shown in Table 25.

[0247] Table 25

[0248] For example, A=40, N sfn =11, C=5, and the corresponding payload interleaver is shown in Table 26.

[0249] Table 26

[0250] For example, A=40, N sfn =11, C=6, and the corresponding payload interleaver is shown in Table 27.

[0251] Table 27

[0252] For example, A=40, N sfn =11, C=7, and the corresponding payload interleaver is shown in Table 28.

[0253] Table 28

[0254] For example, A=40, N sfn =11, C=8, and the corresponding payload interleaver is shown in Table 29.

[0255] Table 29

[0256] For example, A=40, N sfn =11, C=9, and the corresponding payload interleaver is shown in Table 30.

[0257] Table 30

[0258] For example, A=40, N sfn =11, C=10, and the corresponding payload interleaver is shown in Table 31.

[0259] Table 31

[0260] For example, A=40, N sfn =12, C=3, and the corresponding payload interleaver is shown in Table 32.

[0261] Table 32

[0262] For example, A=40, N sfn =12, C=4, and the corresponding payload interleaver is shown in Table 33.

[0263] Table 33

[0264] For example, A=40, N sfn =12, C=5, and the corresponding payload interleaver is shown in Table 34.

[0265] Table 34

[0266] For example, A=40, N sfn =12, C=6, and the corresponding payload interleaver is shown in Table 35.

[0267] Table 35

[0268] For example, A=40, N sfn =12, C=7, and the corresponding payload interleaver is shown in Table 36.

[0269] Table 36

[0270] For example, A=40, N sfn =12, C=8, and the corresponding payload interleaver is shown in Table 37.

[0271] Table 37

[0272] For example, A=40, N sfn =12, C=9, and the corresponding payload interleaver is shown in Table 38.

[0273] Table 38

[0274] For example, A=40, N sfn =13, C=3, and the corresponding payload interleaver is shown in Table 39.

[0275] Table 39

[0276] For example, A=40, N sfn =13, C=4, and the corresponding payload interleaver is shown in Table 40.

[0277] Table 40

[0278] For example, A=40, N sfn =13, C=5, and the corresponding payload interleaver is shown in Table 41.

[0279] Table 41

[0280] For example, A=40, N sfn =13, C=6, and the corresponding payload interleaver is shown in Table 42.

[0281] Table 42

[0282] For example, A=40, N sfn =13, C=6, and the corresponding payload interleaver is shown in Table 43.

[0283] Table 43

[0284] For example, A=40, N sfn =13, C=6, and the corresponding payload interleaver is shown in Table 44.

[0285] Table 44

[0286] For example, A=48, N sfn =11, the corresponding payload interleaver when C=3 to 10 is shown in Table 45, and the corresponding payload interleaver when C=11 to 18 is shown in Table 46.

[0287] Table 45

[0288] Table 46

[0289] For example, A=48, N sfn =12, the corresponding payload interleaver when C=3 to 10 is shown in Table 47, and the corresponding payload interleaver when C=11 to 17 is shown in Table 48.

[0290] Table 47

[0291] Table 48

[0292] For example, A=48, N sfn =13, the corresponding payload interleaver when C=3 to 10 is shown in Table 49, and the corresponding payload interleaver when C=11 to 16 is shown in Table 50.

[0293] Table 49

[0294] Table 50

[0295] It can be understood that the minimum value of j and G(j) in the interleaver involved in this application is 0 (i.e., numbering starts from 0). If the minimum value of j and G(j) in the interleaver actually used is both 1 (i.e., numbering starts from 1), then the interleaver in the embodiment of this application can be simply adjusted by adding 1 to j and G(j) in all interleaver examples in this application. In this case, the corresponding range of j and G(j) is 1 to A, that is, the range of j and G(j) is {1, 2, 3, ..., A}.

[0296] S430: The transmitting end device obtains a second interleaving sequence of length K, where the second interleaving sequence is obtained by concatenating the first interleaving sequence with a 24-bit CRC, where K=A+24.

[0297] S440: The transmitting end device interleaves the second interleaved sequence based on a DCRC interleaver with a length of K to obtain a third interleaved sequence of K bits.

[0298] It can be understood that after the two-layer interleaving of S420 and S440, the 1 bit of the half-frame indication in the PBCH payload is located at the 0th position of the third interleaving sequence, the C bits related to the time or frequency indication in the PBCH payload are located at the 1st position to the Cth position of the third interleaving sequence, and the N bits in the PBCH payload are located at the 1st position to the Cth position of the third interleaving sequence. sfn The SFN bits are located in the C+1th position to the A-1th position of the third interleaving sequence, and the reliability is located in the last N sfn N sfn locations.

[0299] S450: The receiving device obtains a third interleaving sequence.

[0300] It is understood that between S440 and S450, steps S4401 to S4405 may also be included:

[0301] S4401: The transmitting end device performs encoding based on the third interleaved sequence to obtain codeword sequence #1.

[0302] For example, the K bits in the third interleaved sequence can be placed in 2 9=512 bits in the subchannel with higher reliability (i.e., information bits), and the bits in the remaining 512-K bit positions with lower reliability (i.e., frozen bits) are set to 0. The actual bits to be coded are the 512 bits corresponding to the 512 bit positions. The transmitting device performs Polar coding on the bits to be coded to obtain codeword sequence #1.

[0303] S4402: The transmitting end device performs rate matching and modulation based on codeword sequence #1 to obtain codeword sequence #2.

[0304] For example, the transmitting device performs rate matching on the codeword sequence #1, then modulates the rate-matched sequence to obtain the codeword sequence #2, and then maps the modulated codeword sequence #2 to the physical resource for transmission. For example, the modulation method can be QPSK (quaternary phase shift keying), and the modulated QPSK symbol (i.e., codeword sequence #2) is mapped to the physical resource for transmission.

[0305] S4403: The transmitting device sends codeword sequence #2 to the receiving device. Correspondingly, the receiving device receives codeword sequence #2 from the transmitting device.

[0306] It should be noted that since codeword sequence #2 may introduce channel noise signals during transmission, the codeword sequence #2 output or sent by the transmitting device may be different from the codeword sequence #2 received by the receiving device.

[0307] It can be understood that codeword sequence #2 is the signal received by the receiving device.

[0308] S4404: The receiving end device performs demodulation and rate matching based on codeword sequence #2 to obtain codeword sequence #1.

[0309] Among them, demodulation and rate matching can be regarded as the inverse operations of modulation and rate matching. In S4402, rate matching is performed first and then modulation is performed. In this step, demodulation is performed first and then rate matching is performed, thereby obtaining codeword sequence #1.

[0310] It can be understood that since the codeword sequence #2 received by the receiving end may be different from the codeword sequence #2 sent by the transmitting end, the codeword sequence #1 after rate matching at the receiving end may also be different from the codeword sequence #1 at the transmitting end.

[0311] For example, in S450, the receiving end device obtains the third interleaved sequence, including: the receiving end device decodes the codeword sequence #1, for example, the codeword sequence #1 includes 512 codeword bits c0 to c511, and the decoded 512-bit message sequence estimation value is The 0 bits at the frozen bits in the message sequence estimation value are removed to obtain a third interleaved sequence.

[0312] Optionally, when the receiving end device has not yet accessed the cell, that is, in the scenario of initial access to the cell, the receiving end can decode based on c0~c511 (that is, codeword sequence #1) to obtain Based on c0~c511 and Decoded And so on, based on c0~c511 and to Decode the last message bit The decoding is now complete.

[0313] Optionally, if the receiving device has successfully accessed the cell, it can also decode based on the above method to obtain a 512-bit message sequence estimate. The difference is that in the scenario of initial access to the cell, 1 bit of the half-frame indication in the PBCH payload, C key bits, and N bits have been decoded. sfn bits of information, so in this scenario, there is no need to decode to obtain the estimated values ​​corresponding to these bits This can improve the PBCH decoding performance after the device is connected to the system.

[0314] Optionally, in the process of decoding to obtain the 512-bit message sequence estimate, since the receiving device knows the frozen bits, these positions can be directly skipped in the actual decoding and the values ​​on the frozen bits can be set to known values, such as the known value 0.

[0315] S460: The receiving end device deinterleaves the third interleaved sequence based on a DCRC interleaver with a length of K to obtain a second interleaved sequence.

[0316] It can be understood that the DCRC interleaver with a length of K can be uniquely determined by the DCRC interleaver mother sequence, and the corresponding deinterleaver can also be uniquely determined. Then, the receiving device uses the DCRC deinterleaver with a length of K to deinterleave the third interleaved sequence to obtain the second interleaved sequence.

[0317] S470: The receiving end device obtains a first interleaved sequence of length A, where the first interleaved sequence is obtained by removing the last 24 bits of the second interleaved sequence.

[0318] S480: The receiving end device deinterleaves the first interleaved sequence based on the PBCH payload interleaver to obtain a PBCH payload.

[0319] It can be understood that the receiving device knows the original order of the PBCH payload. Therefore, the receiving device can deinterleave the first interleaving sequence based on the original order of the PBCH payload and the PBCH payload deinterleaver corresponding to the PBCH payload interleaver to obtain the PBCH payload in the original order.

[0320] For example, the initial position corresponding to the 1 bit of the half-frame indication in the PBCH payload generated in S410 is the 28th bit (the position number starts from 0), and at the same time, j=10 in the PBCH payload interleaver corresponds to the 1 bit of the half-frame indication in the PBCH payload, then the bit at the G(10)th position in the first interleaving sequence is placed at the 28th position, thereby completing the deinterleaving of the 1 bit, where G(10) is the value corresponding to j=10 in the PBCH payload interleaver.

[0321] Optionally, there is no need to deinterleave the first interleaved sequence in S480. Since the receiving device already knows the meaning of the bits at each position in the obtained first interleaved sequence, the receiving device can directly use these bits for subsequent operations without deinterleaving the first interleaved sequence to restore it to the original order of the PBCH payload.

[0322] The method proposed in this application is described in detail above. The technical solution proposed in this application supports PBCH payload interleaving with longer payloads, which can achieve the effect of protecting key bits and improving PBCH decoding performance.

[0323] Optionally, in the present application, 8M bits of the A-bit PBCH payload come from the MIB message, and 8N bits of the PBCH payload come from the L1 layer, A=8M+8N, where M and N are both positive integers.

[0324] For example, the 1 bit indicating the half frame and C key bits in the PBCH payload are included in 8N bits. sfn SFN bits are included in 8N bits and 8M bits. In the PBCH payload, except for 1 bit indicating half frame, C key bits and N sfn The remaining bits except the SFN bits are included in the 8M bits.

[0325] Optionally, the X (X=A-32) bits added to the A-bit PBCH payload compared to the 32-bit PBCH payload corresponding to Table 1 (hereinafter referred to as the original PBCH payload) can come from the MIB message and / or from the L1 layer. This application does not limit the source of the added X bits. However, it should be noted that the number of bits added from the MIB or L1 layer is an integer multiple of 8, that is, X=8a+8b, where 8a bits come from the master information block MIB message and 8b bits come from the L1 layer, and a and b are natural numbers and cannot be 0 at the same time.

[0326] In one possible implementation, the X bits are all added from the L1 layer (ie, a=0). The X bits include X1 key bits and X2 SFN bits. For details about X1 and X2, refer to the definition in S410 and will not be repeated here.

[0327] For example, if A=40, then X=8, where the A-bit PBCH payload specifically includes:

[0328] 1) 24 bits from MIB in the original PBCH payload

[0329] 2) 8 bits added from the L1 layer in the original PBCH payload

[0330] 3) Newly added X=8 bits of PBCH payload And all 8 bits are newly added from the L1 layer.

[0331] For example, the 8 bits are used for multi-beam indication, wherein the b1 bit is used for SSBI indication, such as b1=3, and the payload position is The b2 bit is used to indicate the frequency domain position. For example, if b2=2, the payload position is b3 bit is used for padding, such as b3=3, the padding position is

[0332] It can be understood that the above payload position is the highest bit, The lowest bit.

[0333] In another possible implementation, the X bits all come from the MIB message (ie, b=0). The X bits are used to indicate non-time sequence information such as energy saving perception.

[0334] For example, if A=40, then X=8, where the A-bit PBCH payload specifically includes:

[0335] 1) 32 bits from the MIB in, The original 24 bits from the MIB in the PBCH payload, It is a newly added 8-bit field from the MIB.

[0336] For example, the 8 bits are used for system energy-saving awareness indication, wherein the a1 bit is used for energy-saving indication, such as a1=1, and the payload position is The a2 bit is used for SIB1 to carry instructions. If a2=1, the payload position is The a3 bit is used to indicate the sensing information and base station position indication. For example, if a3=5, the payload position is The a4 bit is used for padding. If a4=1, the padding position is

[0337] 2) 8 bits added from the L1 layer in the original PBCH payload

[0338] In another possible implementation, part of the X bits comes from the L1 layer addition, and part comes from the MIB message (ie, both a and b are not 0), and the length of the X bits is at least 16.

[0339] For example, A=48, X=8, a=b=1, wherein the PBCH payload of A bits specifically includes:

[0340] 1) 32 bits from the MIB in, The original 24 bits from the MIB in the PBCH payload, It is a newly added 8-bit field from the MIB.

[0341] For example, the 8 bits are used for system energy-saving awareness indication, wherein the a1 bit is used for energy-saving indication, such as a1=1, and the payload position is The a2 bit is used for SIB1 to carry instructions. If a2=1, the payload position is The a3 bit is used to indicate the sensing information and base station position indication. For example, if a3=5, the payload position is The a4 bit is used for padding. If a4=1, the padding position is

[0342] 2) 8 bits added from the L1 layer in the original PBCH payload

[0343] 3) New 8 bits added from the L1 layer

[0344] For example, the 8 bits are used for multi-beam indication, wherein the b1 bit is used for SSBI indication, such as b1=3, and the payload position is The b2 bit is used to indicate the frequency domain position. For example, if b2=2, the payload position is b3 bit is used for padding, such as b3=3, the padding position is

[0345] It is understood that the steps in the above figures are merely illustrative and not intended to be strict limitations. Furthermore, the sequence numbers of the above processes do not necessarily indicate the order in which they are to be executed. The order in which each process is to be executed should be determined by its function and inherent logic, and should not constitute any limitation on the implementation of the embodiments of this application.

[0346] It can also be understood that some optional features in the various embodiments of the present application may not depend on other features in certain scenarios, and may also be combined with other features in certain scenarios, without limitation.

[0347] It can also be understood that in the above-mentioned various method embodiments, the methods and operations implemented by a device (a transmitting device or a receiving device) can also be implemented by components of the device (such as chips or circuits), without limitation.

[0348] The above text, in conjunction with Figures 1 to 4, describes in detail the method embodiments provided by the present application. The following text, in conjunction with Figures 4 and 5, describes the device embodiments of the present application. It will be understood that in order to implement the functions in the above embodiments, the devices in Figures 4 and 5 include hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily appreciate that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. It will be understood that the technical features described in the above method embodiments are also applicable to the following device embodiments.

[0349] Figures 5 and 6 are schematic diagrams of possible apparatuses provided in embodiments of the present application. These apparatuses can be used to implement the functions of the transmitting device or the receiving device in the above method embodiments, thereby also achieving the beneficial effects of the above method embodiments.

[0350] Figure 5 is a schematic block diagram of a communication device 1000 provided in an embodiment of the present application. As shown in Figure 5, the device 1000 may include a communication unit 1010 and a processing unit 1020. The communication unit 1010 can communicate with the outside world, and the processing unit 1020 is used to process data. The communication unit 1010 may also be referred to as a communication interface or a transceiver unit.

[0351] In one possible design, the device 1000 can implement steps or processes corresponding to those performed by the sending end device in the above method embodiment, wherein the processing unit 1020 is used to perform processing-related operations of the sending end device in the above method embodiment, and the communication unit 1010 is used to perform sending-related operations of the sending end device in the above method embodiment.

[0352] In another possible design, the device 1000 can implement steps or processes corresponding to those performed by the receiving device in the above method embodiment, wherein the communication unit 1010 is used to perform reception-related operations of the receiving device in the above method embodiment, and the processing unit 1020 is used to perform processing-related operations of the receiving device in the above method embodiment.

[0353] It can be understood that the device 1000 here is embodied in the form of a functional unit. The term "unit" here can refer to an application specific integrated circuit (ASIC), an electronic circuit, a processor (such as a shared processor, a dedicated processor or a group processor, etc.) and a memory for executing one or more software or firmware programs, a combined logic circuit and / or other suitable components that support the described functions. In an optional example, those skilled in the art can understand that the device 1000 can be specifically the sending end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the sending end device in the above method embodiment, or the device 1000 can be specifically the receiving end device in the above embodiment, and can be used to execute the various processes and / or steps corresponding to the receiving end device in the above method embodiment. To avoid repetition, it will not be repeated here.

[0354] The apparatus 1000 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the transmitting end device in the above-mentioned method, or the apparatus 1000 of each of the above-mentioned solutions has the function of implementing the corresponding steps performed by the receiving end device in the above-mentioned method. The functions can be implemented by hardware, or can be implemented by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-mentioned functions; for example, the communication unit can be replaced by a transceiver (for example, the transmitting unit in the communication unit can be replaced by a transmitter, and the receiving unit in the communication unit can be replaced by a receiver), and other units, such as the processing unit, can be replaced by a processor, respectively performing the transmitting and receiving operations and related processing operations in each method embodiment.

[0355] In addition, the above-mentioned communication unit can also be a transceiver circuit (for example, it can include a receiving circuit and a transmitting circuit), and the processing unit can be a processing circuit. In an embodiment of the present application, the device in Figure 5 can be a receiving end device or a transmitting end device in the aforementioned embodiment, or it can be a chip or a chip system, such as a system on chip (SoC). Among them, the communication unit can be an input and output circuit, a communication interface; the processing unit is a processor or microprocessor or integrated circuit integrated on the chip. This is not limited here.

[0356] Figure 6 is a schematic block diagram of a communication device 1100 provided in an embodiment of the present application. The device 1100 includes a processor 1110 and a transceiver 1120. The processor 1110 and the transceiver 1120 communicate with each other via an internal connection path. The processor 1110 is configured to execute instructions to control the transceiver 1120 to transmit and / or receive signals.

[0357] Optionally, the apparatus 1100 may further include a memory 1130, which communicates with the processor 1110 and the transceiver 1120 via an internal connection path. The memory 1130 is used to store instructions, and the processor 1110 can execute the instructions stored in the memory 1130. In one possible implementation, the apparatus 1100 is used to implement the various processes and steps corresponding to the transmitting end device in the above-mentioned method embodiment. In another possible implementation, the apparatus 1100 is used to implement the various processes and steps corresponding to the receiving end device in the above-mentioned method embodiment.

[0358] Optionally, the memory 1130 may be integrated into the processor 1110 .

[0359] In one possible scenario, the apparatus 1100 includes at least one processor integrated with a memory, and other memories in addition to the memory integrated on the processor.

[0360] It is understood that apparatus 1100 may specifically be the transmitting device or receiving device in the above-described embodiments, or may be a chip or chip system. Correspondingly, transceiver 1120 may be the transceiver circuit of the chip, without limitation herein. Specifically, apparatus 1100 may be used to execute the various steps and / or processes corresponding to the transmitting device or receiving device in the above-described method embodiments.

[0361] Optionally, the memory 1130 may include a read-only memory and a random access memory, and provide instructions and data to the processor. The memory may include a non-volatile random access memory. For example, the memory may also store device type information. The processor 1110 may be configured to execute instructions stored in the memory. When the processor 1110 executes the instructions stored in the memory, the processor 1110 is configured to perform the various steps and / or processes of the above-described method embodiments corresponding to the transmitting device or the receiving device.

[0362] During implementation, each step of the above method can be completed by an integrated logic circuit of the hardware in the processor or by instructions in the form of software. The steps of the method disclosed in conjunction with the embodiments of the present application can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it will not be described in detail here.

[0363] It should be noted that the processor in the embodiments of the present application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above-mentioned method embodiment can be completed by hardware integrated logic circuits in the processor or by software instructions. The above-mentioned processor can be a general-purpose processor, digital signal processing (DSP), ASIC, field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component. The processor in the embodiments of the present application can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in the embodiments of the present application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory, and the processor reads the information in the memory and, in conjunction with its hardware, completes the steps of the above-mentioned method.

[0364] It is understood that the memory in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example and not limitation, many forms of RAM are available, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), and direct RAM bus RAM (DR RAM). It should be noted that the memory of the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0365] Optionally, the memory (eg, 1130 ) in the embodiment of the present application may be integrated into the processor (eg, 1110 ).

[0366] In addition, the present application also provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the operations and / or processes performed by the sending device or the receiving device in each method embodiment of the present application are executed.

[0367] The present application also provides a computer program product, which includes computer program code or instructions. When the computer program code or instructions are run on a computer, the operations and / or processes performed by the sending device or the receiving device in the various method embodiments of the present application are executed.

[0368] In addition, the present application further provides a chip, the chip including a processor. A memory for storing a computer program is provided independently of the chip, and the processor is configured to execute the computer program stored in the memory, so that the operations and / or processing performed by the transmitting device or the receiving device in any method embodiment are performed.

[0369] Furthermore, the chip may further include a communication interface. The communication interface may be an input / output interface, or an interface circuit, etc. Furthermore, the chip may further include a memory.

[0370] In addition, the present application also provides a communication system, including a transmitting device and a receiving device in the embodiments of the present application.

[0371] It should also be noted that the memory described herein is intended to comprise, but not be limited to, these and any other suitable types of memory.

[0372] Those skilled in the art will appreciate that the various exemplary units and algorithmic steps described in conjunction with the embodiments disclosed herein can be implemented using electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented using hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this application. Those skilled in the art will clearly understand that, for ease of description and brevity, the specific operating processes of the systems, devices, and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units described is merely a logical functional division. In actual implementation, other divisions may be used, such as multiple units or components being combined or integrated into another system, or some features being omitted or not implemented. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interface, or indirect coupling or communication connection between devices or units, which may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment. In addition, the functional units in the various embodiments of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0373] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a ROM, a RAM, a magnetic disk, or an optical disk.

[0374] It should be understood that references to "embodiments" throughout this specification mean that a particular feature, structure, or characteristic associated with the embodiment is included in at least one embodiment of the present application. Therefore, various embodiments throughout this specification do not necessarily refer to the same embodiment. Furthermore, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0375] It can also be understood that in this application, "when", "if" and "if" all mean that the network element will make corresponding processing under certain objective circumstances, which is not a time limit, and does not require the network element to have a judgment action when implementing it, nor does it mean that there are other limitations.

[0376] It is also understood that in each embodiment of the present application, "A corresponds to B" means that B is associated with A, and B can be determined based on A. However, it is also understood that determining B based on A does not mean determining B based solely on A, and B can also be determined based on A and / or other information.

Claims

1. A method of interleaving, characterized in that: The method comprises: Generate a physical broadcast channel (PBCH) payload of A bits, where A is greater than 32 and is an integer multiple of 8; Interleaving the PBCH payload based on a PBCH payload interleaver to obtain a first interleaved sequence, the PBCH payload interleaver including A positions and values ​​corresponding to the A positions, the A positions corresponding one-to-one to A bits of the PBCH payload, a value G(j) corresponding to a j-th position of the A positions indicating that a first bit is interleaved to a G(j)-th position of the A bits, the first bit being the bit corresponding to the j-th position of the A bits; Obtain a second interleaved sequence of length K, where the second interleaved sequence is obtained by concatenating the first interleaved sequence with a 24-bit cyclic redundancy check (CRC), where K=A+24; The second interleaved sequence is interleaved based on a distributed cyclic redundancy check DCRC interleaver with a length of K to obtain a third interleaved sequence.

2. A deinterleaving method, characterized in that: The method comprises: Obtain a K-bit third interleaved sequence, where the third interleaved sequence is a sequence obtained by interleaving an A-bit physical broadcast channel (PBCH) payload through a PBCH payload interleaver of length A, concatenating a 24-bit cyclic redundancy check (CRC) and then interleaving the sequence through a distributed cyclic redundancy check (DCRC) interleaver of length K, where A is greater than 32 and is an integer multiple of 8, and K=A+24. The PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions correspond one-to-one to the A bits of the PBCH payload, and a value G(j) corresponding to the j-th position of the A positions indicates that a first bit is interleaved to the G(j)-th position of the A bits, where the first bit is the bit corresponding to the j-th position of the A bits. Deinterleaving the third interleaved sequence based on the DCRC interleaver to obtain a second interleaved sequence; Obtain a first interleaved sequence of length A, where the first interleaved sequence is a sequence obtained by removing the last 24 bits of the second interleaved sequence; The first interleaved sequence is deinterleaved based on the PBCH payload interleaver to obtain the PBCH payload.

3. A decoding method, characterized in that: The method comprises: Obtain a codeword sequence, where the codeword sequence is a sequence obtained by encoding a third interleaving sequence based on K bits, the third interleaving sequence being a sequence obtained by interleaving an A-bit physical broadcast channel (PBCH) payload through a PBCH interleaver of length A, concatenating a 24-bit cyclic redundancy check (CRC) and then interleaving through a distributed cyclic redundancy check (DCRC) interleaver of length K, wherein A is greater than 32, and A is an integer multiple of 8, and K=A+24. The PBCH payload interleaver includes A positions and values ​​corresponding to the A positions, the A positions corresponding one-to-one to the A bits of the PBCH payload, and a value G(j) corresponding to the j-th position of the A positions indicates that a first bit is interleaved to the G(j)-th position of the A bits, where the first bit is the bit corresponding to the j-th position of the A bits; Decode the codeword sequence to obtain some or all bits of the third interleaved sequence, wherein the some bits include 1 bit in the PBCH payload except the half-frame indication, C bits related to the time or frequency indication, and N sfn The remaining bits outside the system frame number SFN bits, the C is greater than or equal to 3, the N sfn Greater than or equal to 10; Deinterleaving the third interleaved sequence based on the DCRC interleaver to obtain a second interleaved sequence; A first interleaved sequence of length A is obtained, where the first interleaved sequence is obtained by removing the last 24 bits of the second interleaved sequence.

4. The method according to any one of claims 1 to 3, characterized in that The PBCH payload includes 1 bit for half-frame indication, C bits related to time or frequency indication, and N sfn SFN bits, wherein C is greater than or equal to 3, and N sfn Greater than or equal to 10.

5. The method according to claim 4, characterized in that A=40, The value of the position corresponding to the 1 bit of the half-frame indication in the A positions is 1, The values ​​of the positions in the A positions corresponding to the C bits related to the time or frequency indication include 8, 6, and 4.

6. The method according to claim 4, characterized in that A=48, The value of the position corresponding to the 1 bit of the half-frame indication in the A positions is 1, The values ​​of the positions in the A positions corresponding to the C bits related to time or frequency indication include 9, 6, and 3.

7. The method according to any one of claims 4 to 6, characterized in that The 1 bit of the half-frame indication is located at the 0th position of the third interleaving sequence, The C bits related to the time or frequency indication are located at the 1st position to the Cth position of the third interleaved sequence, The N sfn The SFN bits are located in the C+1th position to the A-1th position of the third interleaving sequence, and the reliability is located in the last N sfn N sfn locations.

8. The method according to any one of claims 4 to 7, characterized in that The 0th to Nth positions of the PBCH payload interleaver sfn -1 position and the N sfn The SFN bits correspond one to one from the most significant bit MSB to the least significant bit LSB. The Nth PBCH payload interleaver sfn The position corresponds to 1 bit of the half-frame indication, The Nth PBCH payload interleaver sfn +1 position to Nth sfn +C positions correspond one-to-one to the C bits related to time or frequency indication, The PBCH payload interleaver except the 0th position to the Nth position sfn The remaining positions outside the +C positions correspond one-to-one to the remaining bits in the PBCH payload.

9. The method according to any one of claims 4 to 8, characterized in that The C bits related to time or frequency indication include bits indicating the time-frequency position of the synchronization signal block SSB.

10. The method according to any one of claims 4 to 9, characterized in that The PBCH payload includes 1 bit of the half-frame indication, the C bits related to the time or frequency indication, and the N sfn The remaining bits other than the SFN bits include bits indicating awareness and / or energy saving.

11. The method according to any one of claims 4 to 10, characterized in that A=40, N sfn =10, and the corresponding PBCH payload interleaver when C=4 is shown in Table #1. Table #1 12. The method according to any one of claims 4 to 10, characterized in that A=40, N sfn =11, and the corresponding PBCH payload interleaver when C=4 is shown in Table #2. Table #2 13. The method according to any one of claims 4 to 12, characterized in that When A=40, the sequence corresponding to the DCRC interleaver with a length of 64 is {1, 4, 6, 8, 10, 11, 13, 15, 18, 19, 20, 22, 23, 26, 27, 29, 32, 34, 38, 39, 40, 2, 5, 7, 9, 12, 14, 16, 21, 24, 28, 30, 33, 35, 41, 0, 3, 17, 25, 31, 36, 42, 37, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63}.

14. The method according to any one of claims 4 to 10, characterized in that A=48, N sfn =10, and the corresponding PBCH payload interleaver when C=4 is shown in Table #3. Table #3 15. The method according to any one of claims 4 to 10, characterized in that A=48, N sfn =11, the corresponding PBCH payload interleaver when C=4 is shown in Table #4. Table #4 16. The method according to any one of claims 4 to 10, 14 and 15, characterized in that When A=48, the sequence corresponding to the DCRC interleaver with a length of 72 is {1, 3, 6, 9, 12, 14, 16, 18, 19, 21, 23, 26, 27, 28, 30, 31, 34, 35, 37, 40, 42, 46, 47, 48, 0, 2, 4, 7, 10, 13, 15, 17, 20, 22, 24, 29, 32, 36, 38, 41, 43, 49, 5, 8, 11, 25, 33, 39, 44, 50, 45, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71}.

17. The method according to any one of claims 4 to 16, characterized in that The 8M bits in the PBCH payload come from the master information block MIB message, and the 8N bits in the PBCH payload come from the L1 layer, where A=8M+8N, and both M and N are positive integers.

18. The method according to claim 17, characterized in that The 1 bit of the half-frame indication and the C bits related to the time or frequency indication are included in the 8N bits. sfn SFN bits are included in the 8N bits and the 8M bits.

19. The method according to claim 17 or 18, characterized in that The PBCH payload includes 1 bit of the half-frame indication, the C bits related to the time or frequency indication, and the N sfn The remaining bits except the SFN bits are included in the 8M bits.

20. A communication device, characterized in that: It includes a processor and an interface circuit, wherein the interface circuit is used to receive signals from other communication devices outside the communication device and transmit them to the processor or send signals from the processor to other communication devices outside the communication device, and the processor is used to implement the method as described in any one of claims 1 to 19 through a logic circuit or executing code instructions.

21. The communication device according to claim 20, wherein: The communication device is a chip or a chip system.

22. A computer-readable storage medium, characterized in that The storage medium stores a computer program or instruction, and when the computer program or instruction is executed by the communication device, the method according to any one of claims 1 to 19 is implemented.

23. A computer program product, characterized in that The invention comprises a computer program which, when being executed, implements the method according to any one of claims 1 to 19.

24. A communication system, characterized in that: It includes a sending end device and a receiving end device, wherein, The sending end device is used to perform the method according to any one of claims 1, 4 to 19, The receiving end device is used to execute the method as described in any one of claims 2, 4 to 19, or the receiving end device is used to execute the method as described in any one of claims 3 to 19.

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