Transceiver for back-channel communication

Abstract

A transceiver is provided. The transceiver includes a voltage divider, a switching circuit, a voltage pull-up circuit, and a rise time circuit. The voltage divider couples an out-wire terminal to a receive terminal and reduces an input voltage of an input signal received by the out-wire terminal. The switching circuit provides an output signal to the out-wire terminal and is controlled by a transmit signal received at a transmit terminal. The voltage pull-up circuit is coupled to a supply voltage and the out-wire terminal and controls an output voltage of the output signal. The rise time circuit is coupled to the supply voltage, the transmit terminal, and the out-wire terminal and controls a rise time of the output signal. A network device may include a pair of transceivers to communicate with adjacent network devices in a point-to-point network configuration.

Description

[0001] Transceiver for back-channel communication

[0002] FIELD OF THE INVENTION

[0003] The present disclosure is generally directed to a transceiver, and more particularly, to a transceiver for facilitating serial back-channel communication between network devices.

[0004] BACKGROUND OF THE INVENTION

[0005] Commercial environments (such as office spaces or schools) often include a series of network devices for monitoring the environment and controlling lighting systems or other systems within the environment. The devices are typically coupled together via a controller area network (CAN) bus in a parallel configuration. However, in this configuration, network failures (such as missing terminations and / or failing network devices) are difficult to diagnose. U.S. Patent Publication No. 2019 / 0116480 discloses a low power control and monitoring network with a device that has a CPU with a minimum power consumption state and a wake up circuit for waking up the CPU and a transceiver of the device and for waking up the CPU of another device.

[0006] SUMMARY OF THE INVENTION

[0007] The present disclosure is generally directed to a transceiver for facilitating serial back-channel communication between network devices. The network devices, such as relay switches, lighting controllers, motion sensors, etc., may already be connected in parallel via a controller area network (CAN) bus. Each of the network devices includes at least one transceiver to serially connect to another device via a wired connection. The transceiver is bidirectional, enabling a bidirectional point-to-point communication network for diagnosing network failures. Further, the transceiver compensates for series resistance and wire capacitance up to one thousand feet. In a point-to-point network, most network devices will include two transceivers to serially connect to other network devices.

[0008] The transceiver includes a transmit terminal, a receive terminal, and an out- wire terminal. Further, the transceiver includes voltage divider, a switching circuit, a voltage pull-up circuit, and a rise time circuit. In transmit mode, a microcontroller of the network device provides a transmit signal to the transmit terminal. The transmit signal may be a 3.3- volt high level signal. The transmit signal is provided to the switching circuit. The switching circuit includes a switching transistor having a base arranged to receive the transmit signal. The switching circuit provides an output signal to the out-wire terminal for transmission to another network device. An output voltage and a rise time of the output signal is controlled by a rise time circuit and a voltage pull-up circuit. The output signal may be a 24-volt high level signal.

[0009] In receive mode, the out-wire terminal receives an input signal from another network device. The input signal may be a 24-volt high level signal. The voltage divider produces a receive signal by reducing an input voltage of the input signal so that the receive signal may be processed by the microcontroller. The receive signal may be a 3.3-volt high level signal following voltage reduction. The receive terminal receives the receive signal from the voltage divider and provides the input signal to an analog-to-digital converter (ADC). The ADC processes the receive signal into a converted signal, and provides the converted signal to the microcontroller for further processing.

[0010] Generally, in one aspect, a transceiver is provided. The transceiver includes a voltage divider configured to couple an out- wire terminal to a receive terminal. The voltage divider reduces an input voltage of an input signal received by the out- wire terminal.

[0011] The transceiver further includes a switching circuit. The switching circuit is configured to provide an output signal to the out-wire terminal. The switching circuit is controlled by a transmit signal received at a transmit terminal.

[0012] The transceiver further includes a voltage pull-up circuit. The voltage pull-up circuit is coupled to a supply voltage and the out-wire terminal. The voltage pull-up circuit is configured to control an output voltage of the output signal.

[0013] The transceiver further includes a rise time circuit. The rise time circuit is coupled to the supply voltage, the transmit terminal, and the out-wire terminal. The rise time circuit is configured to control a rise time of the output signal.

[0014] According to an example, the switching circuit includes a switching transistor.

[0015] According to an example, the voltage pull-up circuit includes a pull-up resistor.

[0016] According to an example, the rise time circuit includes a rise time transistor. A base of the rise time transistor is coupled to the transmit terminal via a rise time capacitor and a first rise time resistor. A second rise time resistor couples the base of the rise time transistor to an emitter of the rise time transistor. A collector of the rise time transistor is coupled to the out- wire terminal.

[0017] According to an example, the input signal received at the out-wire terminal is a 24-volt high level signal.

[0018] According to an example, the input signal following reduction by the voltage divider is a 3.3-volt high level signal.

[0019] According to an example, the transmit signal is a 3.3-volt high level signal.

[0020] According to an example, the output signal is a 24-volt high level signal.

[0021] Generally in another aspect, a network device is provided. The network device includes the transceiver.

[0022] According to an example, a microcontroller provides the transmit signal to the transmit terminal of the transceiver.

[0023] According to an example, the input signal is provided to a microcontroller via an ADC.

[0024] According to an example, the out-wire terminal is coupled, via a first wired connection, to a second network device.

[0025] According to an example, the network device further includes a second transceiver communicatively coupled, via a second wired connection, to a third network device.

[0026] According to an example, the first wired connection is a category 5 (CAT5) connection.

[0027] According to an example, a length of the first wired connection is less than or equal to one thousand feet.

[0028] It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.

[0029] In various implementations, a processor or controller may be associated with one or more storage media (generically referred to herein as “memory,” e.g., volatile and non-volatile computer memory such as RAM, PROM, EPROM, EEPROM, floppy disks, compact disks, optical disks, magnetic tape, SSD, etc.). In some implementations, the storage media may be encoded with one or more programs that, when executed on one or more processors and / or controllers, perform at least some of the functions discussed herein.

[0030] Various storage media may be fixed within a processor or controller or may be transportable, such that the one or more programs stored thereon can be loaded into a processor or controller so as to implement various aspects as discussed herein. The terms “program” or “computer program” are used herein in a generic sense to refer to any type of computer code (e.g., software or microcode) that can be employed to program one or more processors or controllers.

[0031] These and other aspects of the various embodiments will be apparent from and elucidated with reference to the embodiment s) described hereinafter.

[0032] BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In the drawings, like reference characters generally refer to the same parts throughout the different views. Also, the drawings are not necessarily to scale, emphasis instead generally being placed upon illustrating the principles of the various embodiments.

[0034] FIG. l is a schematic view of a communication system for a plurality of network devices, in accordance with an example.

[0035] FIG. 2A is a schematic view of a communication system for a plurality of network devices wherein back-channel data is transmitted from left to right, in accordance with an example.

[0036] FIG. 2B is a schematic view of a back-channel communication system for a plurality of network devices wherein back-channel data is transmitted from right to left, in accordance with an example.

[0037] FIG. 3 is a functional block diagram of a network device of a communication system, in accordance with an example.

[0038] FIG. 4A is a circuit schematic of a transceiver, in accordance with an example. FIG. 4B is a further circuit schematic of the transceiver of FIG. 4A, in accordance with an example.

[0039] FIG. 5 is a voltage plot of an output signal and the transmit signal, in accordance with an example.

[0040] FIG. 6 is a further voltage plot of the output signal and the transmit signal, in accordance with an example. FIG. 7 is a voltage plot of the input signal and the receive signal, in accordance with an example.

[0041] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0042] The present disclosure is generally directed to a transceiver for facilitating serial back-channel communication between network devices. The network devices, such as relay switches, lighting controllers, motion sensors, etc., may already be connected in parallel via a controller area network (CAN) bus. Each of the network devices includes at least one transceiver to serially connect to another device via a wired connection. The transceiver is bidirectional, enabling a bidirectional point-to-point communication network for diagnosing network failures. Further, the transceiver compensates for series resistance and wire capacitance up to one thousand feet. In a point-to-point network, most network devices will include two transceivers to serially connect to other network devices.

[0043] Turning now to the figures, FIG. l is a schematic illustrating a communication system 1, including a plurality of network devices 10, according to various embodiments of the present disclosure. In some examples, the network devices 10 are installed in a commercial building, such as an office building or a school. Each of the network devices 10 may be one of a wide array of different types of devices, such as relay switches, lighting controllers, motion sensors, etc. In some examples, the network devices 10 are integrated into a connected lighting system. In the connected lighting system, lighting properties of one or more luminaires may be controlled by a controller. The controller may control the luminaires according to information gathered by a variety of input sources, such as sensors or user interfaces. Further, in some examples, the lighting properties of the luminaires may be directly controlled by the input sources.

[0044] In the example of FIG. 1, the network devices 10 are connected in parallel by a controller area network (CAN) bus 3. The CAN bus 3 is terminated at each end by a termination 5a, 5b coupled to ground. However, in this configuration, network failures are difficult to diagnose. These failures could include missing or damaged terminations 5a, 5b and / or malfunctioning network devices 10.

[0045] In order to provide information for diagnosis of these network failures, a serial back-channel network is employed, as illustrated in FIG. 1. In this back-channel network, the network devices 10 are serially connected via wired connections 20. These wired connections 20 are facilitated by a pair of transceivers 100 (as shown in more detail in FIG. 3) in each network device 10. As shown in FIG. 1, a first network device 10a is connected to a second network device 10b via a first wired connection 20a having a first length 16a, the second network device 10b is connected to a third network device 10c via a second wired connection 20b having a second length 16b, the third network device 10c is connected to a fourth network device lOd via a third wired connection 20c having a third length 16c, and so on. Cumulatively, all of the wired connections 20 may have a total length of up to one thousand feet, as the series resistance and the wire capacitance of cable in excess of one hundred feet may increase rise time and reduce pulse width of signals transmitted by the transceivers 100 to an undesirable degree. In some non-limiting examples, the wired connections 20 are embodied as category 5 (CAT5) cables plugged into registered jack (RJ) 45 connectors of the network devices 10. However, in other examples, the wired connections 20 may be embodied as any appropriate type of cabling coupled to the network devices 10 via any appropriate type of connectors. In some examples, the signals conveyed by the wired connections 20 are 24- volt high level signals.

[0046] FIG. 2A illustrates an example of the communication system 1. In the example of FIG. 2A, back-channel data transmitted by the network devices 10 travels in the left-tori ght manner. As shown in FIG. 2 A, the first network device 10a transmits a signal to the second network device 10b via the first wired connection 20a. The second network device 10b transmits a signal to the third network device 10c via the second wired connection 20b. The third network device 10c transmits a signal to the fourth network device 10c via the second wired connection 20c, and so on. Thus, in some example, malfunctions of the second network device 10b may be detected in part by data received (or not received) by the third network device 10c.

[0047] FIG. 2B illustrates a variation of FIG. 2 A. In the example of FIG. 2B, back- channel data transmitted by the network devices 10 travels in the right-to-left manner. As shown in FIG. 2 A, the fourth network device lOd transmits a signal to the third network device 10c via the third wired connection 20c. The third network device 10c transmits a signal to the second network device 10b via the second wired connection 20b. The second network device 10b transmits a signal to the first network device 10a via the first wired connection 20a, and so on. Thus, in some examples, malfunctions of the second network device 10b may be detected in part by data received (or not received) by the first network device 10a.

[0048] FIG. 3 illustrates a functional block diagram of a non-limiting example of a network device 10, according to various embodiments of the present disclosure. As shown in FIG. 3, the network device 10 includes a microcontroller 12, two analog-to-digital converters (ADC) 14a, 14b, and two transceivers 100a, 100b. In some examples, the two ADCs 14a, 14b may be integrated into a single component. In some non-limiting examples, one or both of the two ADCs 14a, 14b may be functional peripheral components integrated into the microcontroller 12. In other non-limiting examples, one or both of the two ADCs 14a, 14b may be separate components arranged externally to the microcontroller 12. Similarly, aspects of the two transceivers 100a, 100b may also be integrated into one or more common components. Further, in some examples, the functionality of the microcontroller 12 may be divided into multiple components. Each of the transceivers 100a, 100b are configured to be bidirectional. However, during operation, one of the transceivers 100a, 100b will function as a transmitter, while the other will function as a receiver. For example, the first transceiver 100a may function as a transmitter while the second transceiver 100b may function as a receiver. Alternatively, the first transceiver 100a may function as a receiver, while the second transceiver 100b may function as a transmitter.

[0049] As shown in FIG. 3, in transmit mode, the first transceiver 100a receives a first transmit signal 120a from the microcontroller 12. In some examples, the first transmit signal 120a is a 3.3-volt high level signal. The first transceiver 100a then transmits a first output signal 118a to another network device 10 via a first wired connection 20a. The first output signal 118a is generated based on the first transmit signal 120a. In some examples, the first output signal is a 24-volt high level signal. In receive mode, the first transceiver 100a receives a first input signal 116a from another network device 10 via the first wired connection 20a. In some examples, the first input signal 116a is a 24-volt high level signal. The first transceiver 100a then transmits a first receive signal 148a to the first ADC 14a. The first receive signal 148a is generated based on the first input signal 16a. In some examples, the first receive signal 148a is a 3.3-volt high level signal. The ADC 14a then generates a first converted signal 150a based on the first receive signal 148a and transmits the first converted signal 150a to the microcontroller 12. The ADC 14a is used to set the ground of the signal provided to the microcontroller 12, and may be particularly useful when the signal was received over a very long wired connection.

[0050] Similarly, in transmit mode, the second transceiver 100b receives a second transmit signal 120b from the microcontroller 12. In some examples, the second transmit signal 120b is a 3.3-volt high level signal. The second transceiver 100b then transmits a second output signal 118b to another network device 10 via a second wired connection 20b. The second output signal 118b is generated based on the second transmit signal 120b. In some examples, the second output signal is a 24-volt high level signal. In receive mode, the second transceiver 100b receives a second input signal 116b from another network device 10 via the second wired connection 20. In some examples, the second input signal 116b is a 24- volt high level signal. The second transceiver 100b then transmits a second receive signal 148b to the second ADC 14b. The second receive signal 148b is generated based on the second input signal 16b. In some examples, the second receive signal 148b is a 3.3-volt high level signal. The second ADC 14b then generates a second converted signal 150b based on the second receive signal 148b and transmits the second converted signal 150b to the microcontroller 12.

[0051] In some examples, the first output signal 118a transmitted by the first transceiver 100a may be at least partly based on the second input signal 116b received by the second transceiver 100b. Similarly, the second output signal 118b transmitted by the second transceiver 100b may be at least partly based on the first input signal 116a received by the first transceiver 100a. For example, the output signals 118a, 118b may be indicative of the status (such as malfunctioning) of the network device 10 which provided the input signals 116a, 116b.

[0052] FIGS. 4A and 4B illustrate a circuit schematic of a transceiver 100. FIG. 4A labels various subcircuits of the transceiver 100, while FIG. 4B labels many of the components comprising the subcircuits. Generally, the transceiver 100 is defined by an out- wire terminal 102, a receive terminal 104, and a transmit terminal 106. The out-wire terminal 102 is coupled to a wired connection 20 to connect the transceiver 100 to another network device 10. As shown in FIGS. 4A and 4B, the out-wire terminal 102 is configured to both receive the input signals 116 as well as to transmit the output signals 118. The receive terminal 104 is configured to provide the receive signal 148 to an ADC 14. The transmit terminal 106 is configured to receive the transmit signal 120 from the microcontroller 12.

[0053] Further, as shown in FIG. 4A, the transceiver 100 may also be defined by a series of subcircuits, including a voltage divider 108, a switching circuit 110, a voltage pull- up circuit 112, and a rise time circuit 114. The voltage divider 108 is used in the receive aspect of the transceiver, while the switching circuit 110, the voltage pull-up circuit 112, and the rise time circuit 114 are used in the transmit aspect.

[0054] As shown in FIG. 4B, the voltage divider 108 includes a first divider resistor 156 (R2) and a second divider resistor 158 (R3). The first divider resistor 156 is coupled between the out-wire terminal 102 and the receive terminal 104. The second divider resistor 158 is coupled between the receive terminal 104 and ground. Accordingly, the voltage divider 108 is arranged to reduce an input voltage 122 of the input signal 116 to a generate a receive signal 148 with a receive voltage 154 acceptable by the ADC 14 and the microcontroller 12. In some examples, the input signal 116 is a 24-volt high level signal, while the receive signal 148 is a 3.3-volt high level signal.

[0055] As shown in FIG. 4A, the switching circuit 110 is coupled to the transmit terminal 120, supply voltage 124, and the out- wire terminal 102 (via diode 162 (D2)). In some examples, the supply voltage is 24 volts. As shown in FIG. 4B, the switching circuit 114 includes a switching transistor 130 (Q2) and a switching resistor 160 (R6). In the example of FIG. 4A, the switching transistor 130 is embodied as a PNP bipolar junction transistor (BJT). Generally, the transmit terminal 106 provides the transmit signal 120 to a base of the switching transistor 130. Accordingly, the switching transistor 130 generates a digital output signal 118 which switches high when the transmit signal 120 is low, and vice versa. In some examples, the transmit signal 120 is a 3.3-volt high level signal, while the output signal 118 is a 24-volt high level signal.

[0056] The output voltage 126 of the output signal 124 is controlled by the voltage pull-up circuit 112 and the rise time circuit 114. As shown in FIG. 4B, the voltage pull-up circuit 112 includes a pull-up resistor 132. The pull-up resistor 132 is coupled between the supply voltage 124 and the output terminal 102. Accordingly, the pull-up resistor 132 is configured to increase the output voltage 126 of the output signal 118 to a voltage level closer to the supply voltage 124, in this case, 24 volts.

[0057] As also shown in FIG. 4A, the rise time circuit 114 is coupled to the transmit terminal 120, supply voltage 124, and the out- wire terminal 102. Generally, the rise time circuit 114 is configured to greatly reduce the rise time 128 of the output signal 118. Without the rise time circuit 114, the capacitance of the wired connections 20 between network devices 10 will cause a lengthy rise time from low voltage to high voltage. As shown in FIG. 4B, the rise time circuit 114 includes a rise time transistor 134 (QI), a rise time capacitor 142 (Cl), a first rise time resistor 144 (R5), and a second rise time resistor 146 (R4). A base 136 of the rise time transistor 134 is coupled to the transmit terminal 120 via the rise time capacitor 142 and the first rise time resistor 144. The second rise time resistor 146 is coupled between the supply voltage 124 and the base 136 of the rise time transistor 134. An emitter 138 of the rise time transistor 134 is coupled to the supply voltage 124, while a collector 140 of the rise time transistor 134 is coupled to the output terminal 118. During the low to high transition of the switching circuit 110, the rise time transistor 134 is on, pulling up the output voltage 126 of the output signal 118 as the rise time capacitor charges 142. The pull-up resistor 132 is bypassed while the transmit signal 120 charges the rise time capacitor 142. Once the rise time capacitor 142 is fully charged, the rise time transistor 134 turns off, and the output voltage 126 of the output signal 118 remains pulled up towards the supply voltage 124 by the pull-up resistor 132.

[0058] The benefits of the rise time circuit are illustrated in FIGS. 5 and 6. FIG. 5 is a voltage plot of an output signal 116 and the transmit signal 120 if the rise time circuit 114 was not implemented. As shown in FIG. 5, the transmit voltage 152 of the transmit signal 120 ranges between 0 and 3.3 volts, while the output voltage 126 of the output signal 118 ranges between approximately 0.5 volts and 18 volts. When the transmit signal 120 switches low, the output signal 118 switches high, and vice versa. Notably, the rise time 128 of the output signal 118 greatly reduces the pulse width of the output signal 118. FIG. 6 shows the output signal 116 and the transmit signal 120 with the rise time circuit 114 implemented, greatly reducing the rise time.

[0059] FIG. 7 is a voltage plot of the input signal 116 and the receive signal 148. As shown in FIG. 7, the input voltage 122 of the input signal 122 ranges between 0 and 18 volts, while the receive voltage 154 of the receive signal 148 ranges between approximately 0.2 volts and 2.4 volts. When the transmit signal 120 switches low, the output signal 118 switches high, and vice versa.

[0060] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0061] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”

[0062] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified.

[0063] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e. “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.”

[0064] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified.

[0065] It should also be understood that, unless clearly indicated to the contrary, in any methods claimed herein that include more than one step or act, the order of the steps or acts of the method is not necessarily limited to the order in which the steps or acts of the method are recited.

[0066] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively.

[0067] The above-described examples of the described subject matter can be implemented in any of numerous ways. For example, some aspects may be implemented using hardware, software, or a combination thereof. When any aspect is implemented at least in part in software, the software code can be executed on any suitable processor or collection of processors, whether provided in a single device or computer or distributed among multiple devices / computers.

[0068] The present disclosure may be implemented as a system, a method, and / or a computer program product at any possible technical detail level of integration. The computer program product may include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present disclosure. The computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium may be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non- exhaustive list of more specific examples of the computer readable storage medium includes the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission media (e.g., light pulses passing through a fiber-optic cable), or electrical signals transmitted through a wire.

[0069] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0070] Computer readable program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state-setting data, configuration data for integrated circuitry, or either source code or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C++, or the like, and procedural programming languages, such as the “C” programming language or similar programming languages. The computer readable program instructions may execute entirely on the user’s computer, partly on the user's computer, as a stand-alone software package, partly on the user’s computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider). In some examples, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate arrays (FPGA), or programmable logic arrays (PLA) may execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0071] Aspects of the present disclosure are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to examples of the disclosure. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0072] The computer readable program instructions may be provided to a processor of a, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions may also be stored in a computer readable storage medium that can direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium having instructions stored therein comprises an article of manufacture including instructions which implement aspects of the function / act specified in the flowchart and / or block diagram or blocks.

[0073] The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks. The flowchart and block diagrams in the Figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various examples of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the Figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustration, and combinations of blocks in the block diagrams and / or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts or carry out combinations of special purpose hardware and computer instructions.

[0074] Other implementations are within the scope of the following claims and other claims to which the applicant may be entitled.

[0075] While various examples have been described and illustrated herein, those of ordinary skill in the art will readily envision a variety of other means and / or structures for performing the function and / or obtaining the results and / or one or more of the advantages described herein, and each of such variations and / or modifications is deemed to be within the scope of the examples described herein. More generally, those skilled in the art will readily appreciate that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual parameters, dimensions, materials, and / or configurations will depend upon the specific application or applications for which the teachings is / are used. Those skilled in the art will recognize, or be able to ascertain using no more than routine experimentation, many equivalents to the specific examples described herein. It is, therefore, to be understood that the foregoing examples are presented by way of example only and that, within the scope of the appended claims and equivalents thereto, examples may be practiced otherwise than as specifically described and claimed. Examples of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the scope of the present disclosure.

Claims

CLAIMS1. A transceiver (100), comprising: a voltage divider (108) configured to couple an out-wire terminal (102) to a receive terminal (104), wherein the voltage divider (108) reduces an input voltage (122) of an input signal (116) received by the out- wire terminal (102); a switching circuit (110) configured to provide an output signal (118) to the out-wire terminal (102), wherein the switching circuit (110) is controlled by a transmit signal (120) received at a transmit terminal (106); a voltage pull-up circuit (112) coupled to a supply voltage (124) and the out- wire terminal (102), wherein the voltage pull-up circuit (112) is configured to control an output voltage (126) of the output signal (118); and a rise time circuit (114) coupled to the supply voltage (124), the transmit terminal (106), and the out- wire terminal (102), wherein the rise time circuit (114) is configured to control a rise time (128) of the output signal (118).

2. The transceiver (100) of claim 1, wherein the switching circuit (110) comprises a switching transistor (130).

3. The transceiver (100) of claim 1, wherein the voltage pull-up circuit (112) comprises a pull-up resistor (132).

4. The transceiver (100) of claim 1, wherein the rise time circuit (114) comprises a rise time transistor (134), wherein a base (136) of the rise time transistor (134) is coupled to the transmit terminal (106) via a rise time capacitor (142) and a first rise time resistor (144), wherein a second rise time resistor (146) couples the base (136) of the rise time transistor (134) to an emitter (138) of the rise time transistor (134), and wherein a collector (140) of the rise time transistor (134) is coupled to the out-wire terminal (102).

5. The transceiver (100) of claim 1, wherein the input signal (116) received at the out-wire terminal is a 24-volt high level signal.

6. The transceiver (100) of claim 1, wherein the input signal (116) following reduction by the voltage divider is a 3.3-volt high level signal.

7. The transceiver (100) of claim 1, wherein the transmit signal (120) is a 3.3- volt high level signal.

8. The transceiver (100) of claim 1, wherein the output signal (118) is a 24-volt high level signal.

9. A network device (10), wherein the network device (10) comprises the transceiver (100) of claim 1.

10. The network device (10) of claim 9, wherein a microcontroller (12) provides the transmit signal (120) to the transmit terminal (106) of the transceiver (100).

11. The network device (10) of claim 9, wherein the input signal (116) is provided to a microcontroller (12) via an analog-to-digital converter (ADC) (14).

12. The network device (10) of claim 11, wherein the out-wire terminal (102) is coupled, via a first wired connection (20), to a second network device (10b).

13. The network device (10) of claim 12, further comprising a second transceiver (100b) communicatively coupled, via a second wired connection (20b), to a third network device (10c).

14. The network device (10) of claim 12, wherein the first wired connection (20) is a category 5 (CAT5) connection.

15. The network device (10) of claim 12, wherein a length (16) of the first wired connection (20) is less than or equal to one thousand feet.

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