Image sensor and imaging device

Abstract

The present invention improves image quality in an image sensor using a single-slope type ADC.　A differential amplifier compares an analog signal with a predetermined reference signal and outputs a first output signal indicating a comparison result. An amplification unit amplifies the first output signal and outputs the amplified first output signal as a second output signal. An output unit inverts and outputs the second output signal. A current suppression unit is composed from a predetermined number of metal-oxide-semiconductor (MOS) transistors connected in series to one of a power supply terminal and a ground terminal of the output unit. A quantization error correction unit controls the gate voltage of each of the MOS transistors.

Description

Image sensor and imaging device

[0001] The present technology relates to an image sensor, and more particularly to an image sensor and an imaging device that use a comparator.

[0002] Conventional image sensors and the like use a single-slope analog-to-digital converter (ADC) consisting of a comparator and a counter. In this single-slope ADC, the comparator can cause image quality degradation, such as streaking, due to fluctuations in the power supply voltage. To address this issue, an image sensor has been proposed that maintains a constant current flowing through an amplifier in the comparator by adding a clipping section (see, for example, Patent Document 1). The comparator in this image sensor includes a differential amplifier, an amplifier, and an output section. The differential amplifier and amplifier are connected to an analog power supply, and the output section is connected to a digital power supply.

[0003] JP 2012-147339 A

[0004] The conventional technology described above aims to prevent degradation of image quality due to voltage fluctuations in the analog power supply by maintaining a constant current flowing through the amplifier in the comparator. However, in the image sensor described above, there is a risk of image quality degradation due to voltage fluctuations in the digital power supply in the subsequent stage.

[0005] The present technology was developed in light of these circumstances, and aims to improve image quality in image sensors that use single-slope ADCs.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is an image sensor including: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result, an amplifier unit that amplifies the first output signal and outputs it as a second output signal, an output unit that inverts the second output signal and outputs it as a third output signal, a current suppression unit that is composed of a predetermined number of MOS (Metal-Oxide-Semiconductor) transistors connected in series to one of a power supply terminal and a ground terminal of the output unit, and a quantization error correction unit that controls the gate voltages of the MOS transistors, thereby improving image quality.

[0007] In addition, in the first aspect, the present invention may further include a temperature detection circuit that detects temperature, and the quantization error correction unit may control the gate voltage of the current suppression unit to a voltage value corresponding to the detected temperature. This brings about an effect of improving streaking even when the peak current at the time of inversion of the third output signal depends on temperature.

[0008] In this first aspect, the predetermined number of MOS transistors may include first and second MOS transistors connected in series, thereby providing an effect of further suppressing the peak current when the output signal of the output section is inverted.

[0009] In this first aspect, the current suppressing unit may further include a first short-circuiting transistor that short-circuits the connection node between the first and second MOS transistors and a predetermined voltage when the third output signal is inverted, thereby achieving an effect of speeding up the inversion operation of the output unit.

[0010] In this first aspect, the current suppressing unit may further include a second short-circuiting transistor that short-circuits the drain and source of the first MOS transistor when the third output signal is inverted, thereby achieving an effect of making the inversion operation of the output unit faster than the above.

[0011] In this first aspect, the current suppressing unit may further include a first short-circuiting transistor that short-circuits the connection node between the first and second MOS transistors and a predetermined voltage when the third output signal is inverted, and a second short-circuiting transistor that short-circuits the drain and source of the first MOS transistor when the third output signal is inverted, thereby achieving an effect of speeding up the inversion operation of the output unit.

[0012] In addition, in the first aspect, the digital signal conversion device may further include a pixel array unit in which a plurality of pixels are arranged in a two-dimensional lattice pattern, a comparator is arranged for each column of the pixel array unit, and the differential amplifier, the amplifying unit, the output unit, and the current suppressing unit are provided for each comparator, thereby achieving the effect of converting an analog signal into a digital signal for each column.

[0013] In this first aspect, the columns may include a first column and a second column, and the quantization error correction unit may separately control the gate voltage of the MOS transistor corresponding to the first column and the gate voltage of the MOS transistor corresponding to the second column, thereby suppressing vertical stripes.

[0014] In this first aspect, the MOS transistor may be an nMOS transistor, which has the effect of suppressing a peak current when the output signal of the output section is inverted from a high level to a low level.

[0015] According to a second aspect of the present technology, there is provided an imaging device including: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result, an amplifier that amplifies the first output signal and outputs it as a second output signal, an output unit that inverts the second output signal and outputs it, a current suppression unit that is composed of a predetermined number of MOS transistors connected in series to one of a power supply terminal and a ground terminal of the output unit, a quantization error correction unit that controls the gate voltages of the MOS transistors, a counter that counts a count value over a time until the output signal of the output unit is inverted, and a signal processing circuit that processes a digital signal indicating the count value, thereby improving the image quality of image data captured by the imaging device.

[0016] 1 is a block diagram showing an example of a configuration of an imaging device according to a first embodiment of the present technology. FIG. 2 is a block diagram showing an example of a configuration of an image sensor according to the first embodiment of the present technology. FIG. 3 is a circuit diagram showing an example of a configuration of a pixel according to the first embodiment of the present technology. FIG. 4 is a block diagram showing an example of a configuration of a column signal processing unit according to the first embodiment of the present technology. FIG. 5 is a circuit diagram showing an example of a configuration of a quantization error correction unit according to the first embodiment of the present technology. FIG. 6 is a truth table showing an example of an operation of the quantization error correction unit according to the first embodiment of the present technology. FIG. 7 is a circuit diagram showing an example of a configuration of a comparator according to the first embodiment of the present technology. FIG. 8 is a circuit diagram showing an example of a configuration of a comparator in a comparative example. FIG. 9 is a timing chart showing an example of an operation of an image sensor in a comparative example. FIG. 10 is a diagram showing an example of image data in a comparative example. FIG. 11 is a graph showing an example of an operation waveform of an output signal of a comparator in a comparative example. FIG. 12 is a timing chart showing an example of an operation of an image sensor according to the first embodiment of the present technology. FIG. 13 is a block diagram showing an example of a configuration of an image sensor according to a second embodiment of the present technology. FIG. 14 is a circuit diagram showing an example of a configuration of a quantization error correction unit according to the second embodiment of the present technology. FIG. 15 is a truth table showing an example of an operation of a temperature detection unit and a temperature correction circuit according to the second embodiment of the present technology. FIG. 10 is a circuit diagram showing a configuration example of a comparator according to a fourth embodiment of the present technology. FIG. 11 is a circuit diagram showing a configuration example of a comparator according to a fifth embodiment of the present technology. FIG. 12 is a block diagram showing a configuration example of a column ADC according to a sixth embodiment of the present technology. FIG. 13 is a block diagram showing a configuration example of a quantization error correction unit according to the sixth embodiment of the present technology. FIG. 14 is a diagram showing an example of image data according to the first embodiment and the sixth embodiment of the present technology. FIG. 15 is a graph showing an example of an operation waveform of an output signal of a comparator according to the first embodiment and the sixth embodiment of the present technology. FIG. 16 is a block diagram showing an example of a schematic configuration of a vehicle control system. FIG. 17 is an explanatory diagram showing an example of installation positions of an outside-vehicle information detection unit and an imaging unit.

[0017] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order. 1. First embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit) 2. Second embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit, and the gate voltage is controlled to a value according to temperature) 3. Third embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit, and a short-circuit transistor is added) 4. Fourth embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit, and a short-circuit transistor is added) 5. Fifth embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit, and two short-circuit transistors are added) 6. Sixth embodiment (an example in which a current suppression unit made up of nMOS transistors is connected to the ground terminal of the output unit, and the gate voltage of the current suppression unit is controlled to different voltage values ​​for odd and even columns) 7. Application example to a moving body

[0018] 1 is a block diagram showing an example of the configuration of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device for capturing image data, and includes an optical unit 110, an image sensor 200, and a DSP (Digital Signal Processing) circuit 120. The imaging device 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. Examples of the imaging device 100 include digital cameras such as digital still cameras, as well as smartphones, personal computers, and in-vehicle cameras that have an imaging function.

[0019] The optical unit 110 collects light from a subject and guides it to the image sensor 200. The image sensor 200 generates image data by photoelectric conversion in synchronization with a vertical synchronization signal. The vertical synchronization signal is a periodic signal with a predetermined frequency that indicates the timing of imaging. The image sensor 200 supplies the generated image data to the DSP circuit 120 via a signal line 209.

[0020] The DSP circuit 120 performs predetermined signal processing on image data from the image sensor 200. The DSP circuit 120 outputs the processed image data to a frame memory 160 or the like via a bus 150. The DSP circuit 120 is an example of a signal processing unit as defined in the claims.

[0021] The display unit 130 displays image data. For example, a liquid crystal panel or an organic EL (Electro Luminescence) panel is assumed as the display unit 130. The operation unit 140 generates an operation signal in accordance with a user's operation.

[0022] The bus 150 is a common path for the optical unit 110, image sensor 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170, and power supply unit 180 to exchange data with one another.

[0023] The frame memory 160 holds image data. The storage unit 170 stores various data such as image data. The power supply unit 180 supplies power to the image sensor 200, the DSP circuit 120, the display unit 130, and the like.

[0024] 2 is a block diagram showing a configuration example of an image sensor 200 according to the first embodiment of the present technology. The image sensor 200 includes a pixel driving unit 210, a control unit 220, a pixel array unit 230, a column signal processing unit 300, and an output unit 250. These circuits may be arranged on a single semiconductor chip, or may be distributed across multiple stacked semiconductor chips.

[0025] A plurality of pixels 240 are arranged in a two-dimensional lattice pattern in the pixel array section 230. Each of the pixels 240 generates an analog pixel signal by photoelectric conversion of incident light and outputs the signal to the column signal processing section 300.

[0026] The pixel driving section 210 sequentially selects and drives rows in the pixel array section 230 to output pixel signals.

[0027] The column signal processing unit 300 performs signal processing such as AD (Analog to Digital) conversion on pixel signals for each column, and supplies the processed digital signals to the output unit 250.

[0028] The output section 250 outputs image data obtained by arranging the digital signals from the column signal processing section 300 to the DSP circuit 120 via a signal line 209 .

[0029] 3 is a circuit diagram showing an example of a configuration of a pixel 240 according to the first embodiment of the present technology. The pixel 240 includes a photoelectric conversion element 241, a transfer transistor 242, a reset transistor 243, a floating diffusion layer 244, an amplification transistor 245, and a selection transistor 246.

[0030] The photoelectric conversion element 241 generates electric charges by photoelectric conversion of incident light. The transfer transistor 242 transfers electric charges from the photoelectric conversion element 241 to the floating diffusion layer 244 in accordance with a transfer signal TRG from the pixel driving unit 210.

[0031] The reset transistor 243 initializes the amount of charge stored in the photoelectric conversion element 241 and the floating diffusion layer 244 in accordance with a reset signal RST from the pixel driving section 210 .

[0032] The floating diffusion layer 244 accumulates the transferred charges and generates a voltage according to the amount of accumulated charges.

[0033] The amplifying transistor 245 constitutes a source follower circuit and outputs a voltage corresponding to the voltage of the floating diffusion layer 244 to the selection transistor 246 .

[0034] The selection transistor 246 outputs the pixel signal of the voltage from the amplification transistor 245 to the column signal processing unit 300 via the vertical signal line VSL in accordance with the selection signal SEL from the pixel driving unit 210. The vertical signal line VSL is wired for each column.

[0035] The circuit configuration of the pixel 240 is not limited to the example shown in the figure, as long as it can generate a pixel signal.

[0036] 4 is a block diagram showing an example of a configuration of a column signal processing unit 300 according to the first embodiment of the present technology. The column signal processing unit 300 includes a plurality of load MOS current sources 310, a quantization error correction unit 400, a reference signal output unit 320, a clock output unit 330, and a column ADC 340.

[0037] The load MOS current source 310 is provided for each column and connected to the vertical signal line VSL of the corresponding column.

[0038] An ADC 350 is arranged for each column in the column ADC 340. The ADC 350 is a single-slope ADC and includes a comparator 500 and a counter 351.

[0039] The quantization error correction section 400 corrects the quantization error by supplying a control voltage to each of the comparators 500. The quantization error correction section 400 will be described in detail later.

[0040] The reference signal output section 320 generates a predetermined reference signal and outputs it to each of the comparators 500. As the reference signal, for example, a sawtooth ramp signal RAMP is used.

[0041] The clock output unit 330 generates a clock signal CLK and outputs it to each of the counters 351 .

[0042] The comparator 500 in the ADC 350 compares the pixel signal Ain input via the vertical signal line VSL with the ramp signal RAMP and outputs the comparison result to the counter 351. The counter 351 counts a count value in synchronization with the clock signal CLK over a period until the comparison result is inverted. The counter 351 outputs a digital signal DOUT indicating the count value to the output unit 250.

[0043] 5 is a circuit diagram showing an example of the configuration of the quantization error correction unit 400 according to the first embodiment of the present technology. The quantization error correction unit 400 includes resistors 411 to 417, a current source 420, nMOS (n-channel MOS) transistors 431 to 435, and pMOS (p-channel MOS) transistors 441 to 447. The quantization error correction unit 400 further includes a decoder 450, inverters 461 and 462, and NAND (negative AND) gates 463 and 464.

[0044] In the figure, the magnitude relationship between the power supply voltages VDDH and VDDL and the ground voltages VSSH and VSSL is expressed by, for example, the following equation: VDDH>VDDL>VSSH=VSSL

[0045] The current source 420 is connected to the power supply voltage VDDH and supplies a constant current. The resistors 411 to 416 are connected in series between the current source 420 and the nMOS transistor 431. The voltage at the connection node of the resistors 411 and 412 is "V01," and the voltage at the connection node of the resistors 412 and 413 is "V02." The voltage at the connection node of the resistors 413 and 414 is "V03," and the voltage at the connection node of the resistors 414 and 415 is "V04." The voltage at the connection node of the resistors 415 and 416 is "VM."

[0046] The source and back gate of the nMOS transistor 431 are connected to the ground voltage VSSH, and the control signal XSTB from the control unit 220 is input to the gate of the nMOS transistor 431 .

[0047] The pMOS transistor 441 outputs a voltage V01 to the gate of the nMOS transistor 432 in accordance with a signal from the decoder 450. The pMOS transistor 442 outputs a voltage V02 to the gate of the nMOS transistor 432 in accordance with a signal from the decoder 450. The pMOS transistor 443 outputs a voltage V03 to the gate of the nMOS transistor 432 in accordance with the signal from the decoder 450. The pMOS transistor 444 outputs a voltage V04 to the gate of the nMOS transistor 432 in accordance with the signal from the decoder 450.

[0048] The decoder 450 decodes the 2-bit control signal DEC<1:0> from the control unit 220. Based on the decoding result, the decoder 450 turns on one of the pMOS transistors 441 to 444, and causes the nMOS transistor 432 to output one of the voltages V01 to V04.

[0049] The nMOS transistor 432 and the resistor 417 are connected in series between the power supply voltage VDDH and the nMOS transistor 433. The voltage at the connection node between the nMOS transistor 432 and the resistor 417 is defined as "VSF."

[0050] The source and back gate of the nMOS transistor 433 are connected to the ground voltage VSSH, and the control signal XSTB is input to the gate thereof.

[0051] The inverter 461 inverts the control signal EN from the control unit 220 and outputs it to the NAND gate 464 .

[0052] The inverter 462 inverts the control signal XSTB and outputs it to the gate of the nMOS transistor 435 .

[0053] The NAND gate 463 outputs the NAND of the control signal EN from the control unit 220 and the control signal XSTB to the gate of the pMOS transistor 445 .

[0054] The NAND gate 464 outputs the NAND of the control signal XSTB and the inverted signal from the inverter 461 to the gate of the pMOS transistor 446 .

[0055] The pMOS transistor 445 is inserted between the connection node of the nMOS transistor 432 and the resistor 417 and the connection node of the pMOS transistor 446 and the nMOS transistor 435 .

[0056] The pMOS transistor 446 and the nMOS transistor 435 are connected in series between the connection node of the resistors 415 and 416 and the ground voltage VSSH. The voltage at the connection node of the pMOS transistor 446 and the nMOS transistor 435 is output to the comparator 500 as the "control voltage VREF1."

[0057] The source of the pMOS transistor 447 is connected to the power supply voltage VDDL. The drain of the pMOS transistor 447 outputs the control voltage TIEH to the comparator 500.

[0058] The gate and drain of the nMOS transistor 434 are connected to the gate of the pMOS transistor 447. The source of the nMOS transistor 434 is connected to the ground voltage VSSL.

[0059] FIG. 6 is a truth table showing an example of the operation of the quantization error correction unit 400 according to the first embodiment of the present technology.

[0060] When the control signal XSTB is at a low level, the quantization error correction unit 400 outputs the ground voltage VSSH as the control voltage VREF1 regardless of the values ​​of the control signals EN and DEC<1:0>.

[0061] When the control signal XSTB is at a high level and the control signal EN is at a low level, the quantization error correction unit 400 outputs the voltage VM as the control voltage VREF1 regardless of the value of the control signals DEC<1:0>.

[0062] When the control signals XSTB and EN are at a high level and the 1st bit and the 0th bit of the control signal DEC are both at a low level, the quantization error correction unit 400 outputs the voltage V01 as the control voltage VREF1.

[0063] When the control signals XSTB and EN are at a high level, the 1st bit of the control signal DEC is at a low level, and its 0th bit is at a high level, the quantization error correction unit 400 outputs the voltage V02 as the control voltage VREF1.

[0064] When the control signals XSTB and EN are at high level, the 1st bit of the control signal DEC is at high level, and its 0th bit is at low level, the quantization error correction unit 400 outputs the voltage V03 as the control voltage VREF1.

[0065] When the control signals XSTB and EN are at a high level and the 1st bit and the 0th bit of the control signal DEC are both at a high level, the quantization error correction unit 400 outputs the voltage V04 as the control voltage VREF1.

[0066] As shown in the figure, the quantization error correction unit 400 can control the control voltage VREF1 in multiple stages. The control voltage VREF1 is adjusted to an optimal value by the control unit 220 in a drive mode for performing various tests and calibrations, for example, before shipping from the factory.

[0067] 7 is a circuit diagram showing an example of a configuration of a comparator 500 according to the first embodiment of the present technology. The comparator 500 includes a differential amplifier 510, an amplifying unit 520, an output unit 530, and a current suppressing unit 540 including nMOS transistors 541 and 542.

[0068] The differential amplifier 510 compares the pixel signal (i.e., analog signal) Ain input via the vertical signal line VSL with the ramp signal RAMP, and outputs an output signal VOUT1 indicating the comparison result to the amplifier section 520.

[0069] The amplifier section 520 amplifies the output signal VOUT1 and outputs it to the output section 530 as an output signal VOUT2.

[0070] The output section 530 inverts the output signal VOUT2 and outputs it to the counter 351 as an output signal VOUT3.

[0071] The nMOS transistors 541 and 542 are connected in series between the ground terminal of the output section 530 and the ground voltage VSSL. A control voltage VREF1 is input to the gate of the nMOS transistor 541, and a control voltage TIEH is input to the gate of the nMOS transistor 542. The quantization error correction section 400 can control these control voltages (in other words, gate voltages). The nMOS transistors 541 and 542 are examples of the first and second MOS transistors set forth in the claims.

[0072] The differential amplifier 510 also includes pMOS transistors 511 to 514 , nMOS transistors 515 and 516 , a tail current source 517 , and capacitors 518 and 519 .

[0073] The pMOS transistors 511 and 512 are connected in parallel to the power supply voltage VDDH. The gate of the pMOS transistor 511 is connected to its own drain and the gate of the pMOS transistor 512.

[0074] The nMOS transistor 515 is inserted between the pMOS transistor 511 and the tail current source 517. The ramp signal RAMP is input to the gate of the nMOS transistor 515 via a capacitor 518.

[0075] The nMOS transistor 516 is inserted between the pMOS transistor 512 and a tail current source 517. The pixel signal Ain is input to the gate of the nMOS transistor 516 via a capacitor 519.

[0076] The pMOS transistor 513 shorts the gate and drain of the nMOS transistor 515 in accordance with a control signal XS1 from the control unit 220. The pMOS transistor 514 shorts the gate and drain of the nMOS transistor 516 in accordance with a control signal XS1 from the control unit 220. These pMOS transistors 513 and 514 implement an auto-zero operation.

[0077] The amplifier section 520 includes a pMOS transistor 521 , nMOS transistors 522 and 523 , and a capacitor 524 .

[0078] The pMOS transistor 521 and the nMOS transistor 523 are connected in series between the power supply voltage VDDH and the ground voltage VSSH. An output signal VOUT1 is input to the gate of the pMOS transistor 521. An output signal VOUT2 is output to the output section 530 from the connection node between the pMOS transistor 521 and the nMOS transistor 523.

[0079] The nMOS transistor 522 is inserted between the connection node of the pMOS transistor 521 and the nMOS transistor 523 and the gate of the nMOS transistor 523. The control signal S2 from the control unit 220 is input to the gate of the nMOS transistor 522.

[0080] The capacitor 524 is inserted between the gate of the nMOS transistor 523 and the ground voltage VSSH.

[0081] The output section 530 includes a pMOS transistor 531 and an nMOS transistor 532. The pMOS transistor 531 and the nMOS transistor 532 are connected in series between the power supply voltage VDDL and the nMOS transistor 541. An output signal VOUT2 is input to the gates of the pMOS transistor 531 and the nMOS transistor 532. An output signal VOUT3 is output to the counter 351 from the connection node of the pMOS transistor 531 and the nMOS transistor 532.

[0082] When the output signal VOUT3 of the output unit 530 is inverted from high level to low level, the current that flows from the power supply voltage VDDL to the ground voltage VSSL is defined as "I_VSSL."

[0083] Although nMOS transistors 541 and 542 are connected in series to the ground terminal of output section 530, the present invention is not limited to this configuration. When output signal VOUT3 is inverted from low level to high level, a pMOS transistor is connected to the power supply terminal of output section 530 instead of an nMOS transistor.

[0084] Furthermore, the number of MOS transistors connected to the output section 530 is not limited to two, but may be one, or three or more.

[0085] Here, in order to explain the effect of adding nMOS transistors 541 and 542, a configuration in which these transistors are removed will be considered as a comparative example.

[0086] 8 is a circuit diagram showing an example of the configuration of a comparator 500 in a comparative example. The circuit configuration of this comparative example is equivalent to that shown in FIG.

[0087] In this comparative example, the nMOS transistors 541 and 542 are omitted from FIG. 7, and the ground terminal of the output section 530 is connected to the ground voltage VSSL.

[0088] The amplifier unit 520 also includes a pMOS transistor 521 and nMOS transistors 522 and 525. The pMOS transistor 521 and nMOS transistor 522 are connected in series between the power supply voltage VDDH and the ground voltage VSSH. The nMOS transistor 525 is inserted between the power supply voltage VDDH and the connection node between the pMOS transistor 521 and the nMOS transistor 522. A clip voltage CLIP from the control unit 220 is input to the gate of the nMOS transistor 525.

[0089] Furthermore, the parasitic capacitance of the wiring that transmits the output signals VOUT2 and VOUT3 is C Ｌ２ and C Ｌ３ Let's say.

[0090] 9 is a timing chart showing an example of the operation of the image sensor 200 in the comparative example. At timing t3, the control unit 220 sets the control signal XS1 to a low level over the pulse period. This causes an auto-zero operation to be performed, which equalizes the input voltages of the differential amplifier 510.

[0091] Then, at timing t4, the ramp signal RAMP starts to fall, and at timing t5, when it becomes identical to the pixel signal Ain, the output signal VOUT3 is inverted from high to low. The dotted line in the figure indicates the trajectory of the potential of the vertical signal line VSL (i.e., the potential of the pixel signal Ain). At timing t7, the ramp signal RAMP starts to fall, and at timing t8, when it becomes identical to the pixel signal Ain, the output signal VOUT3 is inverted from high to low.

[0092] The clip voltage CLIP is a voltage at which the nMOS transistor 525 operates in the saturation region. Application of this voltage keeps the current I2 flowing through the amplifier 520 constant, as shown in the figure. The current flowing through the power supply voltage VDDH, which is the power supply on the analog side, remains constant before and after output inversion, reducing image quality degradation caused by voltage fluctuations in the analog power supply (VDDH).

[0093] However, the VDDL power supply on the digital side used in the output section of the comparator in this comparative example is not subject to image quality improvement. Therefore, the deterioration of image quality due to voltage fluctuations in the digital power supply remains unresolved. The following three measures can be considered to solve this problem: (i) Reducing the wiring resistance of the digital power supply in the output section; (ii) Reducing the parasitic capacitance around the output section; and (iii) Adjusting the circuit constants of the output section.

[0094] However, taking these measures would result in new problems such as an increase in chip size.

[0095] Here, we will explain the problem of image quality degradation caused by voltage fluctuations in the digital power supply from the perspective of streaking.

[0096] 10 is a diagram showing an example of image data in a comparative example, where "a" in the figure shows ideal image data without streaking, and "b" in the figure shows image data captured by the image sensor of the comparative example.

[0097] In the image data of FIG. 1B, the black area indicated by the dotted line is no different from the ideal image data, and no streaking occurs within that area. On the other hand, the area indicated by the solid line, where the left half is black and the right half is white, results in an image in which the black appears darker than in the ideal image data, and streaking occurs within that area. Focusing on this solid line, streaking related to the inversion time of the output signal VOUT3 is determined.

[0098] In the circuit of the comparative example illustrated in FIG. 8, when there is no wiring resistance in the ground voltage VSSL on the digital power supply side, the time T ｆ０ is expressed by the following formula: In the above formula, C Ｌ２ and C Ｌ３ is the parasitic capacitance illustrated in FIG. ２ is the parasitic capacitance C Ｌ２ is the charging current, and ΔI Ｎ３ is the discharge current that flows through the nMOS transistor 532 when the output signal VOUT3 falls. The power supply voltage VDDL is the voltage value of the digital power supply.

[0099] Next, when there is wiring resistance in the ground voltage VSSL, the time from when the output signal VOUT2 of the amplifier unit 520 starts to change until the output signal VOUT3 is inverted in the black region indicated by the dotted line in b of FIG. 10 is defined as T ｆ１ In addition, in the region of the solid line b in FIG. 10, the left half of which is black and the right half of which is white, the time from when the output signal VOUT2 of the amplifier unit 520 starts to change until the output signal VOUT3 is inverted is defined as T ｆ２ Let's say.

[0100] As illustrated in FIG. ｆ１ and T ｆ２ There is a difference between these times T ｆ１ and Tｆ２ is expressed by the following formula:

[0101] In Equation 2 and Equation 3, Δ ＤＲＯＰ１ and Δ ＤＲＯＰ２ is the fluctuation voltage of the ground voltage VSSL in the black area indicated by the dotted line in FIG. 10b and in the area indicated by the solid line with the left half black and the right half white.

[0102] From Equation 2 and Equation 3, the time difference ΔT between the black area in the dotted line row in b of FIG. 10 and the black area in the left half and the white area in the solid line row in b of FIG. 10 is ｆ＿ｓｔｋｎ is expressed by the following formula:

[0103] This time difference ΔT ｆ＿ｓｔｋｎ is considered as one of the streaking factors, the streaking amount Δ ｓｔｋｎ is expressed in LSB (Least Significant Bit) terms by the following formula: In the above formula, T ＣＮＴ is the period of one count of the counter 351. ＣＮＴ is the counter frequency of the counter 351 (i.e., the frequency of the clock signal CLK).

[0104] In addition, the wiring resistance of the ground voltage VSSL is R ＶＳＳＬ Then, the fluctuating voltage Δ ＤＲＯＰ１ and Δ ＤＲＯＰ２ is the peak current I during the inversion operation of the output section 530 in the comparator 500 ＿ＰＥＡＫ０ and wiring resistance R ＶＳＳＬ Therefore, the streaking amount Δ associated with the digital power supply fluctuation of the output section 530 is proportional to ｓｔｋｎ０ is expressed by the following formula: In the above formula, Vth Ｎ is the threshold voltage of the nMOS transistor 532, λ is a correction term for the channel length modulation effect, μ is the charge mobility, and Cox is the gate oxide capacitance per unit area. W Ｎ / L Ｎ is the aspect ratio of the nMOS transistor 532.

[0105] That is, based on the relationship shown in Equation 6, the following measures must be taken to suppress streaking in the comparative example: (i) parasitic capacitance C Ｌ２ (ii) An increase in the operating current of the amplifier 520 (iii) A decrease in the counter frequency (iv) A decrease in the wiring resistance R ＶＳＳＬ (v) Reduction of peak current when the output section 530 is inverted

[0106] However, these countermeasures have the trade-off drawback of increasing the circuit scale and chip size, as well as increasing current consumption. Furthermore, it is suggested that streaking in the output section 530 will tend to increase as more pixels and faster speeds are implemented in the future.

[0107] Therefore, in the first embodiment, the peak current I ＿ＰＥＡＫ In order to suppress this, as shown in FIG. 7, nMOS transistors 541 and 542 are connected in series to the output section 530, and their gate voltages are controlled.

[0108] In this case, the peak current I ＿ＰＥＡＫ is expressed by the following formula: In the above equation, Δ ＤＳ is the source voltage of the nMOS transistor 532 at the moment when the output signal VOUT3 of the comparator is inverted, and this voltage is adjusted by the control voltage VREF1 from the quantization error correction unit 400.

[0109] In addition, the streaking amount Δ ｓｔｋｎ is expressed by the following formula:

[0110] For example, Δ ＤＳ is set to 0.2 V, α is set to 1.3, λ is set to 0.2, VDDL is set to 1.1 V, and Vth Ｎ is set to 0.2 V. In this case, from Equation 7 and Equation 8, the peak current I ＿ＰＥＡＫ is suppressed to about 60% of the value in the comparative example. Therefore, the amount of streaking can be reduced to about 60% of the value in the comparative example.

[0111] For this reason, it is possible to improve image quality by simply adding a simple circuit to the output section 530 in the comparator 500 as in the first embodiment, thereby improving the streaking caused by voltage fluctuations in the digital power supply, which was an issue in the comparative example. In addition, since the wiring resistance value of the digital power supply can be increased by the amount that streaking can be reduced within the specifications, it is possible to reduce the power supply wiring area on the chip and thereby expect to reduce the chip size.

[0112] Furthermore, the first embodiment is not limited to the comparator 500 illustrated in FIG. 7, and is applicable to various comparators such as those described in Japanese Patent Application Laid-Open No. 2009-124514, WO 2019 / 150917, and Japanese Patent Application Laid-Open No. 2022-38476.

[0113] [Example of Operation of Image Sensor] FIG. 12 is a timing chart showing an example of operation of the image sensor 200 according to the first embodiment of the present technology.

[0114] The image sensor 200 performs exposure using a rolling shutter method, and reads out pixel signals from each row after the exposure of that row is completed.

[0115] At timing t1, the pixel driving unit 210 sets the selection signal SEL for the selected row to high level. Immediately thereafter, at timing t2, the pixel driving unit 210 sets the reset signal RST to high level over a pulse period, thereby initializing each pixel in the row. The level of the pixel signal Ain at this time is referred to as the "reset level."

[0116] Furthermore, the control unit 220 sets the control signal XS1 to a low level and the control signal S2 to a high level over a pulse period from timing t3, thereby performing an auto-zero operation.

[0117] At timing t4, the ramp signal RAMP starts to fall, and at timing t5 when it becomes equal to the reset level, the output signals VOUT1, VOUT2, and VOUT3 are inverted.

[0118] Then, at timing t6, the pixel driving unit 210 sets the transfer signal TRG to a high level for the pulse period. This causes charge to be transferred from each pixel in the selected row. The pixel signal Ain at this time has a level corresponding to the amount of accumulated charge, and this level is referred to as the "signal level."

[0119] At timing t7, the ramp signal RAMP starts to fall, and at timing t8 when it becomes equal to the signal level, the output signals VOUT1, VOUT2, and VOUT3 are inverted.

[0120] At the inverted timings t5 and t8, the peak current of I_VSSL is smaller than that of the comparative example illustrated in FIG.

[0121] As described above, according to the first embodiment of the present technology, the nMOS transistors 541 and 542 are connected in series to the ground terminal of the inverter in the comparator 500, and the gate voltages of these transistors are controlled by the quantization error correction unit 400. This makes it possible to suppress the peak current at the time of inversion of the output unit 530, improve streaking, and thereby improve image quality.

[0122] 2. Second Embodiment In the first embodiment described above, the quantization error correction unit 400 suppresses the peak current during inversion of the output unit 530 by controlling the gate voltages of the nMOS transistors 541 and 542. However, this peak current may fluctuate depending on the temperature. For this reason, it is preferable to control the gate voltage of the current suppression unit 540 depending on the temperature. The image sensor 200 in this second embodiment differs from the first embodiment in that it detects the temperature and controls the gate voltage of the nMOS transistor to a voltage value depending on the temperature.

[0123] 13 is a block diagram showing an example of a configuration of an image sensor 200 according to a second embodiment of the present technology. The image sensor 200 according to the second embodiment differs from the image sensor 200 according to the first embodiment in that it further includes a temperature detection unit 260.

[0124] The temperature detection unit 260 detects the temperature and supplies a 2-bit digital signal DET<1:0> indicating the detected temperature to the quantization error correction unit 400 in the column signal processing unit 300.

[0125] 14 is a circuit diagram showing an example of a configuration of a quantization error correction unit 400 according to the second embodiment of the present technology. The quantization error correction unit 400 according to the second embodiment differs from the first embodiment in that it further includes a temperature correction circuit 470.

[0126] The temperature correction circuit 470 controls the gate voltage of the nMOS transistor 541 to a voltage value corresponding to the detected temperature. The temperature correction circuit 470 receives as input the digital signal DET<1:0> from the temperature detection unit 260, the 2-bit digital signal DEC′<1:0> from the control unit 220, and the control signal MUX from the control unit 220.

[0127] When the control signal MUX is at a low level, the temperature correction circuit 470 supplies the value of the digital signal DEC'<1:0> as is as DEC<1:0> to the decoder 450. On the other hand, when the control signal MUX is at a high level, the temperature correction circuit 470 supplies the value of the digital signal DET<1:0> as is as DEC<1:0> to the decoder 450.

[0128] 15 is a truth table showing an example of the operation of the temperature detection unit 260 and the temperature correction circuit 470 according to the second embodiment of the present technology. In the drawing, "a" indicates the operation of the temperature detection unit 260, and "b" indicates the operation of the temperature correction circuit 470.

[0129] As shown in the example of a in the figure, when the detected temperature Ta is equal to or lower than T0, the temperature detection unit 260 outputs both the first bit and the zeroth bit of DET<1:0> at a high level. When the temperature Ta is higher than T0 and equal to or lower than T1, the temperature detection unit 260 outputs the first bit of DET<1:0> at a high level and the zeroth bit at a low level.

[0130] When the temperature Ta is higher than T1 and lower than or equal to T2, the temperature detection unit 260 outputs the first bit of DET<1:0> at a low level and the zeroth bit at a high level. When the temperature Ta is higher than T2, the temperature detection unit 260 outputs both the first bit and the zeroth bit of DET<1:0> at a low level.

[0131] As shown in FIG. 1B, when the control signal MUX is at a low level, the temperature correction circuit 470 supplies the value of the digital signal DEC'<1:0> as is as DEC<1:0> to the decoder 450. On the other hand, when the control signal MUX is at a high level, the temperature correction circuit 470 supplies the value of the digital signal DET<1:0> as is as DEC<1:0> to the decoder 450. One of the voltages V01 to V04 is generated as the control voltage VREF1 by this DEC<1:0>.

[0132] 13 to 15, the temperature correction circuit 470 controls the gate voltage of the nMOS transistor 541 to a voltage value according to the temperature. Therefore, even if the peak current at the time of inversion of the output section 530 depends on the temperature, streaking can be improved.

[0133] As described above, according to the second embodiment of the present technology, the temperature correction circuit 470 controls the gate voltage of the nMOS transistor 541 to a voltage value according to the temperature, and therefore, even if the peak current at the time of inversion of the output unit 530 depends on the temperature, streaking can be improved.

[0134] 3. Third Embodiment In the first embodiment described above, nMOS transistors 541 and 542 are connected in series to the ground terminal of output unit 530, but it may be preferable to perform the inversion operation of output unit 530 faster than in the first embodiment. Image sensor 200 in this third embodiment differs from the first embodiment in that the connection node of nMOS transistors 541 and 542 is short-circuited to ground voltage VSSL when output signal VOUT3 of output unit 530 is inverted.

[0135] 16 is a circuit diagram showing a configuration example of a comparator 500 according to the third embodiment of the present technology. The comparator 500 according to the third embodiment differs from the comparator 500 according to the first embodiment in that an nMOS transistor 551 is further provided in the current suppression unit 540.

[0136] The nMOS transistor 551 short-circuits the connection node between the nMOS transistors 541 and 542 and the ground voltage VSSL when the output signal VOUT3 of the output section 530 is inverted from low level to high level. The nMOS transistor 551 is an example of a first short-circuit transistor recited in the claims.

[0137] When the output signal VOUT3 is inverted, the nMOS transistor 551 short-circuits the connection node between the nMOS transistors 541 and 542 and the ground voltage VSSL, thereby turning on the nMOS transistor 542. This makes it possible to slightly increase the peak current during inversion compared to the case where the nMOS transistor 551 is not present, and to perform the inversion operation faster than in the first embodiment.

[0138] The second embodiment can be applied to the third embodiment.

[0139] As described above, according to the third embodiment of the present technology, when the output signal VOUT3 is inverted, the nMOS transistor 551 causes the nMOS transistor 542 to become conductive, so that the inversion operation of the output unit 530 can be performed faster than in the first embodiment.

[0140] 4. Fourth Embodiment In the first embodiment described above, nMOS transistors 541 and 542 are connected in series to the ground terminal of output section 530, but it may be preferable to perform the inversion operation of output section 530 faster than in the first embodiment. Image sensor 200 in this fourth embodiment differs from the first embodiment in that the drain and source of nMOS transistor 541 are short-circuited when output signal VOUT3 of output section 530 is inverted.

[0141] 17 is a circuit diagram showing a configuration example of a comparator 500 according to the fourth embodiment of the present technology. The comparator 500 according to the fourth embodiment differs from the first embodiment in that an nMOS transistor 552 is further provided in the current suppression unit 540.

[0142] When the output signal VOUT3 of the output section 530 is inverted from low level to high level, the nMOS transistor 552 short-circuits the drain and source of the nMOS transistor 541. The nMOS transistor 552 is an example of a second short-circuit transistor recited in the claims.

[0143] When the output signal VOUT3 is inverted, the nMOS transistor 552 shorts the drain and source of the nMOS transistor 541, causing the nMOS transistor 541 to become conductive. This increases the peak current during inversion slightly compared to when the nMOS transistor 552 is not present, making it possible to perform the inversion operation faster than in the first embodiment.

[0144] The second embodiment can be applied to the fourth embodiment.

[0145] As described above, according to the fourth embodiment of the present technology, when the output signal VOUT3 is inverted, the nMOS transistor 552 makes the nMOS transistor 541 conductive, so that the inversion operation of the output unit 530 can be performed faster than in the first embodiment.

[0146] 5. Fifth Embodiment In the first embodiment described above, nMOS transistors 541 and 542 are connected in series to the ground terminal of output unit 530, but it may be preferable to perform the inversion operation of output unit 530 faster than in the first embodiment. Image sensor 200 in this fifth embodiment differs from the first embodiment in that, during inversion, the connection node of nMOS transistors 541 and 542 is short-circuited to ground voltage VSSL, and the drain and source of nMOS transistor 541 are short-circuited.

[0147] 18 is a circuit diagram showing a configuration example of a comparator 500 according to a fifth embodiment of the present technology. The comparator 500 according to the fifth embodiment differs from the first embodiment in that it further includes nMOS transistors 551 and 552 in the current suppression unit 540.

[0148] When the output signal VOUT3 is inverted, the nMOS transistor 551 short-circuits the connection node between the nMOS transistors 541 and 542 and the ground voltage VSSL. When the output signal VOUT3 is inverted, the nMOS transistor 552 short-circuits the drain and source of the nMOS transistor 541. Because the nMOS transistors 541 and 542 are conductive, the peak current during inversion is slightly increased compared to when the nMOS transistors 551 and 552 are not present, and the inversion operation can be performed faster than in the first embodiment.

[0149] The second embodiment can be applied to the fifth embodiment.

[0150] As described above, according to the fifth embodiment of the present technology, when the output signal VOUT3 is inverted, the nMOS transistors 551 and 552 cause the nMOS transistors 541 and 542 to conduct, so that the inversion operation of the output section 530 can be performed faster than in the first embodiment.

[0151] 6. Sixth Embodiment In the first embodiment described above, the quantization error correction unit 400 supplies the same control voltage VREF1 to each comparator 500 in all columns. However, due to physical constraints such as column pitch, the comparators 500 may be arranged in a staggered pattern. In this case, differences in wiring loads on the output side of the comparators 500 occur between the even and odd columns, and these differences result in differences in delay times for the inversion operations of the output signal VOUT3 between the even and odd columns. This difference in delay time may cause vertical stripes to appear in the image data. The image sensor 200 in this sixth embodiment differs from the first embodiment in that the gate voltages of the current suppression units 540 are controlled separately for the even and odd columns to suppress vertical stripes.

[0152] FIG. 19 is a block diagram showing an example configuration of a column ADC 340 according to a sixth embodiment of the present technology. In the sixth embodiment, the comparators 500 in each column are arranged in a staggered manner. The axis parallel to the column direction is the Y axis, and the representative position (e.g., center position) of the comparators 500 on the Y axis in odd-numbered columns is Y1, and the representative position of the comparators 500 in even-numbered columns is Y2. The positions of the counters 351 in each column on the Y axis are the same, and Y2 is a position closer to the counter 351 than Y1. When the comparators 500 are arranged in a staggered manner in this manner, a difference in wiring load occurs between the wiring 509-1 transmitting the output signal VOUT of the odd-numbered columns and the wiring 509-2 transmitting the output signal VOUT of the even-numbered columns. This difference causes a difference in the delay time of the inversion operation of the output signal VOUT3 between the even-numbered columns and the odd-numbered columns.

[0153] The time until the output signal VOUT3 of the odd-numbered column is inverted is T ｆ４ The time until the output signal VOUT3 of the even-numbered column is inverted is T ｆ５ Then, these times are expressed by the following formula: In Formula 10 and Formula 11, C Ｌ３＿４ and C Ｌ３＿５ is the parasitic capacitance of each of the wirings 509-1 and 509-02.

[0154] From Equation 10 and Equation 11, T ｆ４ and T ｆ５ Time difference ΔT ｆ＿ｆｉｘｅｄ is expressed by the following formula:

[0155] This time difference ΔT ｆ＿ｆｉｘｅｄ is considered as one of the vertical streak factors, the vertical streak amount Δ ｆｉｘｅｄ０ is expressed in LSB terms by the following formula:

[0156] From the relationship shown in Equation 13, when the control voltage VREF1 of all columns is set to the same voltage value as in the first embodiment, the following measures must be taken to suppress vertical stripes: (i) Lowering the power supply voltage VDDL on the digital side (ii) Increasing the discharge current of the amplifier unit 520 (iii) Decreasing the counter frequency (iv) Parasitic capacitance C Ｌ３＿４and C Ｌ３＿５ Reduction of

[0157] However, these countermeasures have the trade-off of increasing circuit scale, chip size, and current consumption. Furthermore, it is suggested that vertical stripes will tend to increase as speeds continue to increase.

[0158] Therefore, in the sixth embodiment, the quantization error correction unit 400 calculates the time difference ΔT ｆ＿ｆｉｘｅｄ In this case, the control voltage VREF1 is supplied to the odd-numbered columns, and the control voltage VREF2, which is different from VREF1, is supplied to the even-numbered columns so that the vertical stripe amount Δ ｆｉｘｅｄ is expressed by the following formula:

[0159] In Equation 14, I Ｎ３＿４ and I Ｎ３＿５ are discharge currents when the output signals VOUT3 of the odd and even columns are inverted. These currents are expressed by the following equations: In Equation 15 and Equation 16, Δ ＤＳ＿４ and Δ ＤＳ＿５ is the source voltage of the nMOS transistor 532 at the moment when the output signals VOUT3 of the odd and even columns are inverted.

[0160] Although the comparators 500 are arranged in a staggered pattern in Y1 and Y2 for odd-numbered and even-numbered columns, the arrangement is not limited to this. For example, the comparators 500 for the 4n (n is an integer) and 4n+1 columns may be arranged in Y1, and the comparators 500 for the 4n+2 and 4n+3 columns may be arranged in Y2. In this case, a control voltage VREF1 is supplied to the 4n and 4n+1 columns, and a control voltage VREF2 is supplied to the 4n+2 and 4n+3 columns.

[0161] The odd-numbered columns and the even-numbered columns are examples of the first columns and second columns set forth in the claims.

[0162] 20 is a block diagram showing an example configuration of a quantization error correction unit 400 according to the sixth embodiment of the present technology. The quantization error correction unit 400 according to the sixth embodiment includes an odd-numbered column correction unit 401 and an even-numbered column correction unit 402.

[0163] The odd-numbered column correction unit 401 receives control signals DEC1<1:0>, XSTB, and EN from the control unit 220. The odd-numbered column correction unit 401 generates control voltages VREF1 and TIEH in accordance with these control signals and supplies them to the odd-numbered columns in the column ADC 340.

[0164] The even-numbered column correction unit 402 receives control signals DEC2<1:0>, XSTB, and EN from the control unit 220. The even-numbered column correction unit 402 generates control voltages VREF2 and TIEH in accordance with these control signals and supplies them to the even-numbered columns in the column ADC 340.

[0165] 5 is provided in each of the odd-numbered column correction unit 401 and the even-numbered column correction unit 402. However, the circuit that generates the control voltage TIEH can be shared by the odd-numbered column correction unit 401 and the even-numbered column correction unit 402.

[0166] 21 is a diagram showing an example of image data in the first embodiment and the sixth embodiment of the present technology. In the figure, "a" shows an example of image data when the comparators 500 are arranged in a staggered manner in the first embodiment. In the figure, "b" shows an example of image data in the sixth embodiment.

[0167] As shown in FIG. 1A, when the comparators 500 are arranged in a staggered manner in the first embodiment, the time difference ΔT ｆ＿ｆｉｘｅｄ This may result in vertical streaks.

[0168] In contrast, in the sixth embodiment, the quantization error correction unit 400 controls the gate voltage of the current suppression unit 540 separately for odd and even columns, so that vertical stripes can be suppressed as illustrated in b in the same figure.

[0169] 22 is a graph showing an example of an operational waveform of the output signal VOUT3 of the comparator 500 in the first embodiment and the sixth embodiment of the present technology. The vertical axis in the figure indicates the level of the output signal VOUT3, and the horizontal axis indicates the time from the point in time when the output signal VOUT3 starts to invert from a high level to a low level. In the figure, "a" shows an example of an operational waveform of the output signal VOUT3 in the first embodiment, and "b" in the figure shows an example of an operational waveform of the output signal VOUT3 in the sixth embodiment.

[0170] As shown in FIG. 10A, when the comparators 500 are arranged in a staggered manner in the first embodiment, a difference occurs in the delay time when the comparators 500 are inverted between odd-numbered columns and even-numbered columns.

[0171] On the other hand, in the sixth embodiment, the quantization error correction unit 400 calculates the time difference ΔT ｆ＿ｆｉｘｅｄ The gate voltages of the current suppressing units 540 are controlled separately for the odd-numbered columns and the even-numbered columns so that the difference is small.

[0172] For example, the parasitic capacitance C Ｌ３＿４ and C Ｌ３＿５ are 5.0 and 1.0 femtofarads (fF), respectively, and the unadjusted discharge current I Ｎ３＿４ and I Ｎ３＿５ In this case, the discharge current I Ｎ３＿５ The control voltage is adjusted so that the current is 10 uA to 2 uA.

[0173] As a result, as shown in FIG. 1B, the difference in delay time when inverting between odd-numbered columns and even-numbered columns becomes smaller, and the amount of vertical streaks is reduced.

[0174] It should be noted that each of the second to fifth embodiments can be applied to the sixth embodiment.

[0175] As described above, according to the sixth embodiment of the present technology, the quantization error correction unit 400 controls the gate voltage of the current suppression unit 540 separately for odd and even columns, thereby making it possible to suppress vertical streaks when the comparators 500 are arranged in a staggered pattern.

[0176] 7. Application Examples to Mobile Bodies The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure may be realized as a device mounted on any type of mobile body, such as an automobile, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot.

[0177] FIG. 23 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a mobile object control system to which the technology according to the present disclosure can be applied.

[0178] The vehicle control system 12000 includes a plurality of electronic control units connected via a communication network 12001. In the example shown in Fig. 23, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an outside-vehicle information detection unit 12030, an inside-vehicle information detection unit 12040, and an integrated control unit 12050. Also shown as functional components of the integrated control unit 12050 are a microcomputer 12051, an audio / video output unit 12052, and an in-vehicle network I / F (Interface) 12053.

[0179] The drivetrain control unit 12010 controls the operation of devices related to the drivetrain of the vehicle in accordance with various programs. For example, the drivetrain control unit 12010 functions as a control device for a drive force generating device for generating a drive force of the vehicle, such as an internal combustion engine or a drive motor, a drive force transmission mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a braking force of the vehicle.

[0180] The body system control unit 12020 controls the operation of various devices equipped in the vehicle body according to various programs. For example, the body system control unit 12020 functions as a control device for a keyless entry system, a smart key system, a power window device, or various lamps such as headlamps, backup lamps, brake lamps, turn signals, and fog lamps. In this case, radio waves transmitted from a portable device that serves as a key or signals from various switches can be input to the body system control unit 12020. The body system control unit 12020 receives these radio waves or signals and controls the vehicle's door lock device, power window device, lamps, etc.

[0181] The outside-vehicle information detection unit 12030 detects information outside the vehicle equipped with the vehicle control system 12000. For example, an imaging unit 12031 is connected to the outside-vehicle information detection unit 12030. The outside-vehicle information detection unit 12030 causes the imaging unit 12031 to capture images outside the vehicle and receives the captured images. The outside-vehicle information detection unit 12030 may perform object detection processing or distance detection processing for people, cars, obstacles, signs, characters on the road surface, etc. based on the received images.

[0182] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output the electrical signal as an image or as distance measurement information. The light received by the imaging unit 12031 may be visible light or invisible light such as infrared light.

[0183] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, a driver state detection unit 12041 that detects the state of the driver is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that captures an image of the driver, and the in-vehicle information detection unit 12040 may calculate the degree of fatigue or concentration of the driver based on the detection information input from the driver state detection unit 12041, or may determine whether the driver is dozing off.

[0184] The microcomputer 12051 can calculate control target values ​​for the driving force generating device, steering mechanism, or braking device based on the information inside and outside the vehicle acquired by the outside-vehicle information detection unit 12030 or the inside-vehicle information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of an ADAS (Advanced Driver Assistance System), including vehicle collision avoidance or impact mitigation, following driving based on the distance between vehicles, maintaining vehicle speed, vehicle collision warning, vehicle lane departure warning, etc.

[0185] In addition, the microcomputer 12051 can perform cooperative control for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation, by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the surroundings of the vehicle obtained by the outside vehicle information detection unit 12030 or the inside vehicle information detection unit 12040.

[0186] Furthermore, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information outside the vehicle acquired by the outside information detection unit 12030. For example, the microcomputer 12051 can control the headlamps according to the position of a preceding vehicle or an oncoming vehicle detected by the outside information detection unit 12030, and perform cooperative control aimed at preventing glare, such as switching from high beams to low beams.

[0187] The audio / video output unit 12052 transmits at least one of audio and video output signals to an output device capable of visually or audibly notifying information to vehicle occupants or the outside of the vehicle. In the example of Fig. 23, the output devices are exemplified by an audio speaker 12061, a display unit 12062, and an instrument panel 12063. The display unit 12062 may include, for example, at least one of an on-board display and a head-up display.

[0188] FIG. 24 is a diagram showing an example of the installation position of the imaging unit 12031.

[0189] In FIG. 24, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104, and 12105.

[0190] The imaging units 12101, 12102, 12103, 12104, and 12105 are provided, for example, at positions such as the front nose, side mirrors, rear bumper, back door, and the top of the windshield inside the vehicle cabin of the vehicle 12100. The imaging unit 12101 provided on the front nose and the imaging unit 12105 provided on the top of the windshield inside the vehicle cabin mainly acquire images of the front of the vehicle 12100. The imaging units 12102 and 12103 provided on the side mirrors mainly acquire images of the sides of the vehicle 12100. The imaging unit 12104 provided on the rear bumper or back door mainly acquires images of the rear of the vehicle 12100. The imaging unit 12105 provided on the top of the windshield inside the vehicle cabin is mainly used to detect preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, lanes, etc.

[0191] 24 shows an example of the imaging ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided on the front nose, imaging ranges 12112 and 12113 indicate the imaging ranges of the imaging units 12102 and 12103 provided on the side mirrors, respectively, and imaging range 12114 indicates the imaging range of the imaging unit 12104 provided on the rear bumper or back door. For example, by overlaying the image data captured by the imaging units 12101 to 12104, an overhead image of the vehicle 12100 viewed from above can be obtained.

[0192] At least one of the image capturing units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the image capturing units 12101 to 12104 may be a stereo camera made up of multiple image capturing elements, or may be an image capturing element having pixels for phase difference detection.

[0193] For example, based on the distance information obtained from the imaging units 12101 to 12104, the microcomputer 12051 can calculate the distance to each three-dimensional object within the imaging ranges 12111 to 12114 and the change in this distance over time (relative speed with respect to the vehicle 12100), thereby extracting as a preceding vehicle, in particular, the three-dimensional object that is the closest three-dimensional object on the path of the vehicle 12100 and traveling in approximately the same direction as the vehicle 12100 at a predetermined speed (e.g., 0 km / h or higher). Furthermore, the microcomputer 12051 can set a vehicle-to-vehicle distance to be maintained in advance in front of the preceding vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. In this way, cooperative control can be performed for the purpose of autonomous driving, which allows the vehicle to travel autonomously without relying on driver operation.

[0194] For example, the microcomputer 12051 classifies and extracts three-dimensional object data regarding three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from the imaging units 12101 to 12104, and can use the data for automatic obstacle avoidance. For example, the microcomputer 12051 distinguishes obstacles around the vehicle 12100 into obstacles that are visible to the driver of the vehicle 12100 and obstacles that are difficult to see. The microcomputer 12051 then determines a collision risk that indicates the risk of collision with each obstacle, and when the collision risk is equal to or greater than a set value and a collision is possible, the microcomputer 12051 can provide driving assistance for collision avoidance by outputting an alarm to the driver via the audio speaker 12061 or the display unit 12062, or by performing forced deceleration or avoidance steering via the drive system control unit 12010.

[0195] At least one of the image capturing units 12101 to 12104 may be an infrared camera that detects infrared rays. For example, the microcomputer 12051 can recognize a pedestrian by determining whether a pedestrian is present in the images captured by the image capturing units 12101 to 12104. Such pedestrian recognition is performed, for example, by extracting feature points from the images captured by the image capturing units 12101 to 12104 as infrared cameras and performing pattern matching on a series of feature points that indicate the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that a pedestrian is present in the images captured by the image capturing units 12101 to 12104 and recognizes the pedestrian, the audio / image output unit 12052 controls the display unit 12062 to superimpose a rectangular outline on the recognized pedestrian for emphasis. The audio / image output unit 12052 may also control the display unit 12062 to display an icon or the like indicating the pedestrian at a desired position.

[0196] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to, for example, the image capturing unit 12031 of the above-described configuration. Specifically, the image capturing device 100 of FIG. 1 can be applied to the image capturing unit 12031. By applying the technology according to the present disclosure to the image capturing unit 12031, it is possible to obtain a captured image that is easier to see, thereby reducing driver fatigue.

[0197] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology having the same name correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist thereof.

[0198] The effects described in this specification are merely examples and are not limiting, and other effects may also be obtained.

[0199] The present technology may also be configured as follows: (1) An image sensor comprising: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result; an amplifier unit that amplifies the first output signal and outputs it as a second output signal; an output unit that inverts the second output signal and outputs it as a third output signal; a current suppression unit composed of a predetermined number of MOS (Metal-Oxide-Semiconductor) transistors connected in series to one of a power supply terminal and a ground terminal of the output unit; and a quantization error correction unit that controls the gate voltages of the MOS transistors. (2) The image sensor according to (1), further comprising a temperature detection circuit that detects temperature, wherein the quantization error correction unit controls the gate voltage of the current suppression unit to a voltage value corresponding to the detected temperature. (3) The image sensor according to (1) or (2), wherein the predetermined number of MOS transistors include first and second MOS transistors connected in series. (4) The image sensor according to (3), wherein the current suppression unit further comprises a first short-circuiting transistor that short-circuits the connection node of the first and second MOS transistors with a predetermined voltage when the third output signal is inverted. (5) The image sensor according to (3), wherein the current suppression unit further comprises a second short-circuiting transistor that short-circuits the drain and source of the first MOS transistor with a predetermined voltage when the third output signal is inverted. (6) The image sensor according to (3), wherein the current suppression unit further comprises a first short-circuiting transistor that short-circuits the connection node of the first and second MOS transistors with a predetermined voltage when the third output signal is inverted, and a second short-circuiting transistor that short-circuits the drain and source of the first MOS transistor with a predetermined voltage when the third output signal is inverted. (7) The image sensor according to any one of (1) to (6), further comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional lattice, wherein a comparator is arranged for each column of the pixel array section, and the differential amplifier, the amplification section, the output section, and the current suppression section are provided for each of the comparators.(8) The image sensor according to (7), wherein the columns include a first column and a second column, and the quantization error correction unit individually controls the gate voltage of the MOS transistor corresponding to the first column and the gate voltage of the MOS transistor corresponding to the second column. (9) The image sensor according to any of (1) to (8), wherein the MOS transistors are nMOS transistors. (10) An imaging device comprising: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result; an amplifier that amplifies the first output signal and outputs it as a second output signal; an output unit that inverts the second output signal and outputs it as a third output signal; a current suppression unit composed of a predetermined number of MOS transistors connected in series to one of a power supply terminal and a ground terminal of the output unit; a quantization error correction unit that controls the gate voltage of each of the MOS transistors; a counter that counts a count value over a time period until the output signal of the output unit is inverted; and a signal processing circuit that processes a digital signal indicating the count value.

[0200] 100 Imaging device 110 Optical unit 120 DSP circuit 130 Display unit 140 Operation unit 150 Bus 160 Frame memory 170 Storage unit 180 Power supply unit 200 Image sensor 210 Pixel driving unit 220 Control unit 230 Pixel array unit 240 Pixel 241 Photoelectric conversion element 242 Transfer transistor 243 Reset transistor 244 Floating diffusion layer 245 Amplification transistor 246 Selection transistor 250 Output unit 260 Temperature detection unit 300 Column signal processing unit 310 Load MOS current source 320 Reference signal output unit 330 Clock output unit 340 Column ADC 350 ADC 351 Counter 400 Quantization error correction unit 401 Odd column correction unit 402 Even column correction unit 411 to 417 Resistors 420 Current source 431 to 435, 515, 516, 522, 523, 525, 532, 541, 542, 551, 552 nMOS transistors 441 to 447, 511 to 514, 521, 531 pMOS transistors 450 Decoder 461, 462 Inverter 463, 464 NAND (negative AND) gate 470 Temperature compensation circuit 500 Comparator 510 Differential amplifier 517 Tail current source 518, 519, 524 Capacitor 520 Amplifying section 530 Inverter 540 Current suppressing section 12031 Imaging section

Claims

1. An image sensor comprising: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result; an amplifier unit that amplifies the first output signal and outputs it as a second output signal; an output unit that inverts the second output signal and outputs it as a third output signal; a current suppression unit consisting of a predetermined number of MOS (Metal-Oxide-Semiconductor) transistors connected in series to one of the power supply terminal and ground terminal of the output unit; and a quantization error correction unit that controls the gate voltage of each of the MOS transistors.

2. The image sensor according to claim 1, further comprising a temperature detection circuit that detects temperature, wherein the quantization error correction section controls the gate voltage of the current suppression section to a voltage value according to the detected temperature.

3. The image sensor according to claim 1, wherein the predetermined number of MOS transistors includes first and second MOS transistors connected in series.

4. The image sensor according to claim 3, wherein the current suppression section further comprises a first short-circuit transistor that short-circuits the connection node of the first and second MOS transistors to a predetermined voltage when the third output signal is inverted.

5. The image sensor according to claim 3, wherein the current suppression section further comprises a second short-circuit transistor that short-circuits the drain and source of the first MOS transistor when the third output signal is inverted.

6. The image sensor according to claim 3, wherein the current suppression section further comprises: a first short-circuit transistor that short-circuits the connection node of the first and second MOS transistors with a predetermined voltage when the third output signal is inverted; and a second short-circuit transistor that short-circuits the drain and source of the first MOS transistor when the third output signal is inverted.

7. The image sensor according to claim 1, further comprising a pixel array section in which a plurality of pixels are arranged in a two-dimensional lattice, a comparator is arranged for each column of said pixel array section, and said differential amplifier, said amplification section, said output section and said current suppression section are provided for each of said comparators.

8. The image sensor according to claim 7, wherein the columns include a first column and a second column, and the quantization error correction unit controls the gate voltage of the MOS transistor corresponding to the first column and the gate voltage of the MOS transistor corresponding to the second column individually.

9. The image sensor according to claim 1, wherein the MOS transistor is an nMOS transistor.

10. An imaging device comprising: a differential amplifier that compares an analog signal with a predetermined reference signal and outputs a first output signal indicating the comparison result; an amplifier section that amplifies the first output signal and outputs it as a second output signal; an output section that inverts the second output signal and outputs it as a third output signal; a current suppression section consisting of a predetermined number of MOS transistors connected in series to one of the power supply terminal and the ground terminal of the inverter; a quantization error correction section that controls the gate voltage of each of the MOS transistors; a counter that counts a count value over a period of time until the output signal of the output section is inverted; and a signal processing circuit that processes a digital signal indicating the count value.

Images