Display device and method for manufacturing same

Abstract

Provided are a display device and a method for manufacturing same. A display device, according to one embodiment of the present invention, comprises: a substrate; a pixel electrode disposed on the substrate; an organic film disposed on the pixel electrode; and a light-emitting element disposed on the organic film. The light emitting element comprises: a semiconductor stack; a protective film disposed on a side surface of the semiconductor stack; and a contact electrode disposed on the protective film. A portion of the side surface of the semiconductor stack is exposed without being covered by the contact electrode, and the contact electrode is disposed spaced apart from the top surface of the semiconductor stack.

Description

Display device and method of manufacturing the same

[0001] The present invention relates to a display device and a method for manufacturing the same.

[0002] As the information society develops, demand for display devices for displaying images is increasing in various forms. Display devices can be flat panel displays such as liquid crystal displays (LCDs), field emission displays (FEDs), and light emitting displays (LEDs).

[0003] The light-emitting display device may include an organic light-emitting display device including an organic light-emitting diode element as a light-emitting element, and an ultra-small light-emitting display device including a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the ultra-small light-emitting diode element is made of an inorganic material, it has the advantage of having a longer lifespan due to fewer deterioration issues compared to an organic light-emitting diode element.

[0004] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can prevent a contact electrode exposed on the upper surface of a semiconductor stack from being peeled off by a chemical solution or the like.

[0005] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0006] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a pixel electrode disposed on the substrate, an organic film disposed on the pixel electrode, and a light-emitting element disposed on the organic film. The light-emitting element includes a semiconductor stack, a protective film disposed on a side surface of the semiconductor stack, and a contact electrode disposed on the protective film. A portion of a side surface of the semiconductor stack is exposed and not covered by the contact electrode, and the contact electrode is disposed away from an upper surface of the semiconductor stack.

[0007] The semiconductor stack may further include a first semiconductor layer disposed on the organic film and including a semiconductor material layer doped with a first conductive dopant, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer and including a semiconductor material layer doped with a second conductive dopant. The contact electrode may be disposed on an entire side surface of the first semiconductor layer and an entire side surface of the active layer, and may be disposed on a portion of a side surface of the second semiconductor layer.

[0008] The light-emitting element may further include a conductive layer disposed between the organic film and the semiconductor stack, and a contact electrode disposed on the protective film and connected to the conductive layer exposed without being covered by the protective film.

[0009] The distance between the upper surface of the semiconductor stack and the contact electrode in the height direction of the light-emitting element may be greater than 100 nm.

[0010] The light-emitting element may further include light extraction patterns formed in a concave cross-sectional shape on the upper surface of the semiconductor stack.

[0011] The distance between the upper surface of the semiconductor stack and the contact electrode in the height direction of the light emitting element may be greater than the maximum length of any one of the light extraction patterns in the height direction of the light emitting element.

[0012] The protective film may include a first side region that is exposed and not covered by the contact electrode on a side surface of the light-emitting element and a second side region that is covered by the contact electrode. The surface roughness of the first side region may be greater than the surface roughness of the second side region.

[0013] The organic film may further include a connecting electrode connected to the pixel electrode through a connecting hole penetrating the organic film and connected to the contact electrode disposed on the side of the light-emitting element.

[0014] The distance between the upper surface of the semiconductor stack and the connecting electrode in the height direction of the light-emitting element may be greater than 100 nm.

[0015] According to one embodiment of the present invention for solving the above problem, a display device includes a substrate, a pixel electrode disposed on the substrate, an organic film disposed on the pixel electrode, and a light-emitting element disposed on the organic film. The light-emitting element includes a semiconductor stack, a conductive layer disposed between the organic film and the semiconductor stack, a protective film disposed on side surfaces of the conductive layer and side surfaces of the semiconductor stack, a first contact electrode disposed on the protective film and connected to a conductive layer exposed without being covered by the protective film, and a second contact electrode disposed on the protective film and connected to the second semiconductor layer through a hole penetrating the conductive layer, the first semiconductor layer, and the active layer. Each of the first contact electrode and the second contact electrode is disposed apart from an upper surface of the semiconductor stack.

[0016] Among the side surfaces of the semiconductor stack, a part of the first side surface may be exposed without being covered by the first contact electrode, and among the side surfaces of the semiconductor stack, a part of the second side surface may be exposed without being covered by the second contact electrode.

[0017] The semiconductor stack may further include a first semiconductor layer disposed on the organic film and including a semiconductor material layer doped with a first conductive dopant, an active layer disposed on the first semiconductor layer, and a second semiconductor layer disposed on the active layer and including a semiconductor material layer doped with a second conductive dopant. The first contact electrode may be disposed on a first side of the first semiconductor layer and a first side of the active layer, and may be disposed on a portion of the first side of the second semiconductor layer, and the second contact electrode may be disposed on a second side of the first semiconductor layer and a second side of the active layer, and may be disposed on a portion of the second side of the second semiconductor layer.

[0018] The distance between the upper surface of the semiconductor stack and the first contact electrode or the second contact electrode in the height direction of the light-emitting element may be greater than 100 nm.

[0019] The light-emitting element may further include a light extraction pattern formed in a concave cross-sectional shape on the upper surface of the semiconductor stack.

[0020] A distance between the upper surface of the semiconductor stack and the first contact electrode or the second contact electrode in the height direction of the light emitting element may be greater than the maximum length of the light extraction pattern in the height direction of the light emitting element.

[0021] The protective film includes a first side region that is exposed and not covered by the first contact electrode or the second contact electrode on the side of the light-emitting element and a second side region that is covered by the contact electrode, and the surface roughness of the first side region may be greater than the surface roughness of the second side region.

[0022] The device may further include a first connecting electrode connected to the first pixel electrode through a first connecting hole penetrating the organic film and connected to the first contact electrode disposed on a side of the light-emitting element, and a second connecting electrode connected to the common electrode through a second connecting hole penetrating the organic film and connected to the second contact electrode disposed on another side of the light-emitting element.

[0023] The distance between the upper surface of the semiconductor stack and the first connection electrode or the second connection electrode in the height direction of the light-emitting element may be greater than 100 nm.

[0024] According to an embodiment of the present invention for solving the above problem, a method for manufacturing a display device comprises the steps of forming a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer on a semiconductor substrate, etching the second semiconductor material layer, the active material layer, the first semiconductor material layer, and the conductive material layer to form light-emitting elements each including a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer, forming a hole penetrating the conductive layer, the first semiconductor layer, and the active layer in each of the light-emitting elements, forming a protective material layer surrounding each of the light-emitting elements and patterning the protective material layer to form a protective film, forming a mask pattern on the protective film and forming a contact electrode layer, removing the mask pattern to lift off the conductive layer to form a first contact electrode connected to the conductive layer in each of the light-emitting elements, and a second contact electrode connected to the second semiconductor layer in the hole, transferring the light-emitting elements onto an organic film disposed on the pixel electrodes and the common electrodes so that the conductive layer faces pixel electrodes and common electrodes in each of the light-emitting elements, and forming a first contact electrode on each of the light-emitting elements. A step of forming a first connection electrode connecting the contact electrode to one of the pixel electrodes, and a second connection electrode connecting the second contact electrode to one of the common electrodes.

[0025] The mask pattern may include a first sub-mask pattern region formed to extend in a first direction and have a first thickness, and a second sub-mask pattern region formed to have a thickness smaller than the first thickness and to have a thickness that gradually decreases along a second direction intersecting the first direction as it moves away from the first sub-mask pattern region.

[0026] Specific details of other embodiments are included in the detailed description and drawings.

[0027] According to the display device and the manufacturing method thereof according to the embodiments, the contact electrode of the light-emitting element is spaced apart from the upper surface of the semiconductor stack, thereby preventing the contact electrode exposed on the upper surface of the semiconductor stack from being peeled off by a chemical solution or the like.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] Figure 1 is a perspective view showing a display device according to one embodiment.

[0030] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0031] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0032] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0033] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0034] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5.

[0035] Figure 7 is a cross-sectional view showing in detail an example of area A1 of Figure 6.

[0036] Figure 8 is an image showing the first side area.

[0037] Figure 9 is an enlarged image showing the S1 area of ​​the first side area.

[0038] Figure 10 is an image showing the second side area.

[0039] Figure 11 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0040] Figure 12 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0041] Fig. 13 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5.

[0042] Figure 14 is a cross-sectional view showing another example of area A2 of Figure 13 in detail.

[0043] FIG. 15 is a layout diagram showing pixels of a display area according to one embodiment.

[0044] Fig. 16 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 15.

[0045] Figure 17 is a cross-sectional view showing in detail an example of area B1 of Figure 16.

[0046] Fig. 18 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 15.

[0047] Figure 19 is a cross-sectional view showing another example of area B2 of Figure 18 in detail.

[0048] Fig. 20 is a flowchart showing a method for manufacturing a display device according to one embodiment.

[0049] FIGS. 21 to 29 are exemplary drawings for explaining a method of manufacturing a display device according to one embodiment.

[0050] Fig. 30 is a layout diagram showing the light emitting element and the second mask pattern of step S140 of Fig. 20.

[0051] Fig. 31 is a cross-sectional view showing an example of a cross-section corresponding to line I3-I3' of Fig. 30.

[0052] FIG. 32 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0053] FIGS. 33 and 34 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0054] FIG. 35 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment.

[0055] FIG. 36 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0056] FIG. 37 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0057] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0058] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer, or where the other layer or layer is interposed therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0059] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0060] Specific embodiments are described below with reference to the attached drawings.

[0061] Figure 1 is a perspective view showing a display device according to one embodiment.

[0062] Referring to FIG. 1, the display device (10) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as a mobile phone, a smart phone, a tablet personal computer, a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an electronic book, a portable multimedia player (PMP), a navigation system, an Ultra Mobile PC (UMPC), etc., as well as a television, a laptop, a monitor, a billboard, an Internet of Things (IOT), etc.

[0063] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and an ultra-small light-emitting display device using an ultra-small light-emitting diode (micro or nano light emitting diode (micro LED or nano LED)). Hereinafter, the display device (10) is described mainly as an ultra-small light-emitting display device, but the present invention is not limited thereto. Meanwhile, for the convenience of explanation, an ultra-small light-emitting diode is described as a light-emitting element below.

[0064] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0065] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) intersecting the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed to be rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a square, and may be formed in another polygonal, circular, or oval shape. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include a curved portion formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display panel (100) may be formed to be flexible so as to be bent, curved, folded, or rolled.

[0066] The substrate (SUB) of the display panel (100) may include a main area (MA) and a sub area (SBA).

[0067] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) that is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of sub-pixels. For example, each of the pixels may include a first sub-pixel that emits light of a first color, a second sub-pixel that emits light of a second color, and a third sub-pixel that emits light of a third color, but the embodiments of the present specification are not limited thereto.

[0068] The sub-area (SBA) may protrude in a second direction (DR2) from one side of the main area (MA). In FIG. 1, the sub-area (SBA) is illustrated as being unfolded, but the sub-area (SBA) may be bent, in which case it may be disposed on the lower surface of the display panel (100). When the sub-area (SBA) is bent, it may overlap with the main area (MA) in the third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be disposed in the sub-area (SBA).

[0069] The display driving circuit (250) can generate signals and voltages for driving the display panel (100). The display driving circuit (250) can be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) can be attached to the circuit board (300) using a COF (chip on film) method.

[0070] The circuit board (300) may be attached to one end of the sub-area (SBA) of the display panel (100). As a result, the circuit board (300) may be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) may receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF).

[0071] The power supply circuit (500) can generate multiple panel driving voltages according to an external power voltage. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to a circuit board (300) using a COF method.

[0072] Fig. 2 is a layout diagram showing a display device according to one embodiment. Fig. 2 illustrates that the sub-area (SBA) is unfolded rather than bent.

[0073] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0074] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) surrounding the display area (DA). The display area (DA) may occupy most of the area of ​​the main area (MA). The display area (DA) may be positioned at the center of the main area (MA).

[0075] The display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of sub-pixels (SPX). A pixel (PX) may be defined as a sub-pixel group that is the smallest unit capable of expressing white gradation.

[0076] A non-display area (NDA) may be positioned adjacent to a display area (DA). The non-display area (NDA) may be an area outside the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0077] The first scan driver (SDC1) and the second scan driver (SDC2) may be positioned in the non-display area (NDA). The first scan driver (SDC1) may be positioned on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be positioned on the other side (e.g., the right side) of the display panel, but the embodiments of the present specification are not limited thereto.

[0078] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can be electrically connected to the display driving circuit (250) via scan fan out lines. Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) can receive a scan control signal from the display driving circuit (250), generate scan signals according to the scan control signal, and output the scan signals to the scan lines.

[0079] The sub-area (SBA) may protrude from one side of the main area (MA) in a second direction (DR2). The length of the sub-area (SBA) in the second direction (DR2) may be shorter than the length of the main area (MA) in the second direction (DR2). The length of the sub-area (SBA) in the first direction (DR1) may be shorter than the length of the main area (MA) in the first direction (DR1) or may be substantially the same as the length of the main area (MA) in the first direction (DR1). The sub-area (SBA) may be curved and may be disposed at a lower portion of the display panel (100). In this case, the sub-area (SBA) may overlap the main area (MA) in the third direction (DR3).

[0080] The sub-area (SBA) may include a connection area (CA), a pad area (PA), and a bending area (BA).

[0081] The connection area (CA) is an area that protrudes in the second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) may be in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0082] The pad area (PA) is an area where pads (PD) and a display driving circuit (250) are arranged. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. The circuit board (300) can be attached to the pads (PD) of the pad area (PA) using a conductive adhesive such as an anisotropic conductive film. One side of the pad area (PA) can be in contact with the bending area (BA).

[0083] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) can be positioned below the connection area (CA) and below the main area (MA). The bending area (BA) can be positioned between the connection area (CA) and the pad area (PA). One side of the bending area (BA) can be in contact with the connection area (CA), and the other side of the bending area (BA) can be in contact with the pad area (PA).

[0084] FIG. 3 is a block diagram showing a display device according to one embodiment.

[0085] Referring to FIG. 3, the display area (DA) includes a plurality of pixels (PX), a plurality of scan lines (SL), a plurality of emission control lines (EL), and a plurality of data lines (DL).

[0086] A plurality of pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). For example, the plurality of pixels (PX) may be arranged along rows and columns of a matrix form in the first direction (DR1) and the second direction (DR2). A plurality of scan lines (SL) and a plurality of emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). A plurality of data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). The plurality of scan lines (SL) include a plurality of write scan lines (GWL), a plurality of control scan lines (GCL), a plurality of initialization scan lines (GIL), and a plurality of bias scan lines (GBL).

[0087] Each of the plurality of sub-pixels (SPX) may be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines (GCL), one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of emission control lines (EL), and one of the plurality of data lines (DL). Each of the plurality of sub-pixels (SPX) may be supplied with a data voltage of the data line (DL) according to a write scan signal of the write scan line (GWL), and may emit light through a light-emitting element according to the data voltage.

[0088] The non-display area (NDA) includes a first scan driver (SDC1), a second scan driver (SDC2), and a display driver circuit (250).

[0089] Each of the first scan driving unit (SDC1) and the second scan driving unit (SDC2) may include a write scan signal output unit (611), an initialization scan signal output unit (612), a bias scan signal output unit (613), and a light emission signal output unit (614). Each of the write scan signal output unit (611), the initialization scan signal output unit (612), the bias scan signal output unit (613), and the light emission signal output unit (614) may receive a scan timing control signal (SCS) from the timing control circuit (400). The write scan signal output unit (611) may generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (400) and sequentially output the write scan signals to the write scan lines (GWL). The initialization scan signal output unit (612) may generate initialization scan signals according to the scan timing control signal (SCS) and sequentially output the initialization scan signals to the initialization scan lines (GIL). The bias scan signal output unit (613) can generate bias scan signals according to a scan timing control signal (SCS) and sequentially output them to bias scan lines (EBLs). The emission signal output unit (614) can generate emission control signals according to a scan timing control signal (SCS) and sequentially output them to emission control lines (ELs).

[0090] In one embodiment, each of the plurality of sub-pixels (SPX) may be connected to one of the control scan lines. In this case, the control scan signal output units of the first scan driver (SDC1) and the second scan driver (SDC2) may generate control scan signals according to a scan timing control signal (SCS) and sequentially output the control scan signals to the control scan lines.

[0091] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0092] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs the converted data voltages to the data lines (DL). In this case, the sub-pixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and the data voltages can be supplied to the selected sub-pixels (SPX).

[0093] The timing control circuit (251) can receive digital video data and timing signals from the outside. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) for controlling the display panel (100) according to the timing signals. The timing control circuit (400) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output digital video data (DATA) and a data timing control signal (DCS) to the data driving circuit (252).

[0094] The power supply circuit (500) can generate a plurality of panel driving voltages according to an external power voltage. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0095] Fig. 4 is an equivalent circuit diagram showing a sub-pixel according to one embodiment.

[0096] Referring to FIG. 4, a sub-pixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), an emission line (EL), and a data line (DL). For example, the sub-pixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), an emission line (EL), and a data line (DL).

[0097] A sub-pixel (SPX) according to one embodiment includes a driving transistor (DT), switch elements, a capacitor (C1), and a light-emitting element (LE). The switch elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0098] A driving transistor (DT) includes a gate electrode, a conductive layer, and a second electrode. The driving transistor (DT) controls a drain-source current (Ids, hereinafter referred to as “driving current”) flowing between the conductive layer and the second electrode according to a data voltage applied to the gate electrode.

[0099] The light emitting element (LE) may be a micro light emitting diode.

[0100] The light emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light emitting element (LE) may be connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power voltage (VSS) is applied.

[0101] A capacitor (C1) is formed between a gate electrode of a driving transistor (DT) and a first power line (VDL) to which a first power voltage (VDD) is applied. The first power voltage (VDD) may be a voltage of a higher level than a second power voltage (VSS). One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0102] As shown in Fig. 4, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0103] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to a write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to an initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to a bias scan line (GBL). In addition, the gate electrode of the fifth transistor (ST5) and the gate electrode of the sixth transistor (ST6) may be connected to an emission control line (EL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, and ST6) are formed as p-type MOSFETs, they may be turned on when a scan signal of a gate low voltage and an emission signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the emission line (EL), respectively. One electrode of the third transistor (ST3) and one electrode of the fourth transistor (ST4) can be connected to the initialization voltage line (VIL) and the voltage line (VAIL), respectively.

[0104] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. The active layers of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layers of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductors.

[0105] In this case, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) can be turned on when a write scan signal of a gate high voltage is applied, and the third transistor (ST3) can be turned on when an initialization scan signal of a gate high voltage is applied. In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, and therefore can be turned on when a scan signal of a gate low voltage and a light emission signal are applied.

[0106] Alternatively, the fourth transistor (ST4) may be formed as an n-type MOSFET, and thus, the active layer of each of the fourth transistors (ST4) may be formed of an oxide semiconductor. When the fourth transistor (ST4) is formed as an n-type MOSFET, it may be turned on when a bias scan signal of a gate high voltage is applied.

[0107] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layers of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may be formed of an oxide semiconductor.

[0108] FIG. 5 is a layout diagram showing pixels of a display area according to one embodiment.

[0109] Referring to FIG. 5, each of the plurality of pixels (PX) of the display area (DA) may include three sub-pixels (SPX1, SPX2, SPX3), but the embodiment of the present specification is not limited thereto and may include four sub-pixels. When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), it may include a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3).

[0110] A plurality of pixels (PX) can be arranged in a matrix form. In each of the plurality of pixels (PX), a first sub-pixel (SPX1), a second sub-pixel (SPX2), and a third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0111] When each of the plurality of pixels (PX) includes three sub-pixels (SPX1, SPX2, SPX3), the first sub-pixel (SPX1) can emit light of a first color, the second sub-pixel (SPX2) can emit light of a second color, and the third sub-pixel (SPX3) can emit light of a third color. Here, the light of the first color may be light in a red wavelength band, the light of the second color may be light in a green wavelength band, and the light of the third color may be light in a blue wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in a wavelength band of approximately 600 nm to 750 nm.

[0112] Alternatively, when each of the plurality of pixels (PX) includes four sub-pixels, the first sub-pixel may emit light of a first color, the second and fourth sub-pixels may emit light of a second color, and the third sub-pixel may emit light of a third color. Alternatively, the first sub-pixel may emit light of a first color, the second sub-pixel may emit light of a second color, the third sub-pixel may emit light of a third color, and the fourth sub-pixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0113] The first sub-pixel (SPX1) includes a first pixel electrode (PXE1), a plurality of light-emitting elements (LEs), and a first light conversion layer (QDL1). The second sub-pixel (SPX2) includes a second pixel electrode (PXE2), a plurality of light-emitting elements (LEs), and a second light conversion layer (QDL2). The third sub-pixel (SPX3) includes a third pixel electrode (PXE3), a plurality of light-emitting elements (LEs), and a light-transmitting portion (TPL).

[0114] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first sub-pixel (SPX1), the area of ​​the second sub-pixel (SPX2), and the area of ​​the third sub-pixel (SPX3) may be set according to the light conversion efficiency of the first light conversion layer (QDL1) and the light conversion efficiency of the second light conversion layer (QDL2). For example, the lower the light conversion efficiency, the larger the area of ​​the sub-pixel.

[0115] For example, as shown in FIG. 5, when the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1). In addition, since the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), whereas the first light conversion layer (QDL1) must convert the light, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3).

[0116] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to a first electrode of a fourth transistor (ST4 of FIG. 4) and a second electrode of a sixth transistor (ST6 of FIG. 4) of the corresponding sub-pixel.

[0117] A plurality of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The same number of light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light emitting elements (LEs) may be arranged on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light emitting elements (LEs) may emit light of a third color, i.e., light in a blue wavelength band, but the embodiments of the present specification are not limited thereto.

[0118] Each of the plurality of light emitting elements (LEs) may have a circular planar shape, but the embodiments of the present specification are not limited thereto. For example, each of the plurality of light emitting elements (LEs) may have a rectangular planar shape.

[0119] The first light conversion layer (QDL1) can completely overlap the first pixel electrode (PXE1) and the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1). The area of ​​the first light conversion layer (QDL1) can be larger than the area of ​​the first pixel electrode (PXE1). The first light conversion layer (QDL1) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the first light conversion layer (QDL1) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the first sub-pixel (SPX1) into first light.

[0120] The second light conversion layer (QDL2) can completely overlap the second pixel electrode (PXE2) and the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2). The area of ​​the second light conversion layer (QDL2) can be larger than the area of ​​the second pixel electrode (PXE2). The second light conversion layer (QDL2) can convert or shift the peak wavelength of incident light into light of another specific peak wavelength and emit the light. For example, the second light conversion layer (QDL2) can convert or shift third light emitted from the plurality of light emitting elements (LEs) of the second sub-pixel (SPX2) into second light.

[0121] The light transmitting layer (TPL) can completely overlap the third pixel electrode (PXE3) and the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3). The light transmitting layer (TPL) can directly transmit incident light. For example, the light transmitting layer (TPL) can directly transmit third light emitted from the plurality of light emitting elements (LEs) of the third sub-pixel (SPX3).

[0122] When the light-emitting element (LE) of the first sub-pixel (SPX1) emits light of a first color, the light-emitting element (LE) of the second sub-pixel (SPX2) emits light of a second color, and the light-emitting element (LE) of the third sub-pixel (SPX3) emits light of a third color, the light conversion layers (QDL1, QDL2) and the light transmitting layer (TPL) may be omitted.

[0123] Fig. 6 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5. Fig. 7 is a cross-sectional view showing in detail an example of area A1 of Fig. 6.

[0124] Referring to FIGS. 6 and 7, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a flexible substrate that can be stretched. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0125] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film for protecting the transistors of the thin film transistor layer (TFTL) and the light-emitting layer (172) of the light-emitting element layer (EML) from moisture penetrating through the substrate (SUB), which is vulnerable to moisture permeation. The barrier film (BR) may be formed of a plurality of inorganic films that are alternately laminated.

[0126] A thin film transistor (TFT1) may be arranged on the barrier film (BR). The thin film transistor (TFT1) may be the fourth transistor (ST4) or the sixth transistor (ST6) illustrated in FIG. 4. The thin film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0127] A first active layer (ACT1) of a thin film transistor (TFT1) may be disposed on the barrier film (BR). The first active layer (ACT1) of the thin film transistor (TFT1) may include polycrystalline silicon, single-crystalline silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin film transistor (TFT1) may be formed of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0128] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region overlapping the first gate electrode (G1) in a third direction (DR3) that is a thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions in which ions are doped into a semiconductor material to have conductivity.

[0129] A first gate insulating film (131) may be disposed on the barrier layer (BR) and the first channel region (CHA1), the first source region (S1), and the first drain region (D1) of the thin film transistor (TFT1).

[0130] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) of a thin film transistor (TFT1) and a first capacitor electrode (CAE1). The first gate electrode (G1) may overlap the first active layer (ACT1) in the third direction (DR3). Although FIG. 6 illustrates that the first gate electrode (G1) and the first capacitor electrode (CAE1) are disposed apart from each other, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0131] A second gate insulating film (132) may be disposed on the first gate insulating film (131) and the first gate electrode (G1) and first capacitor electrode (CAE1) of the thin film transistor (TFT1).

[0132] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed therebetween.

[0133] A first interlayer insulating film (141) may be placed on the second gate insulating film (132) and the second capacitor electrode (CAE2).

[0134] A first data metal layer may be disposed on an interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141).

[0135] A first planarizing organic film (160) may be placed on the first interlayer insulating film (141) and the first source connection electrode (PCE1) to planarize the step caused by the thin film transistor (TFT1).

[0136] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) penetrating the first planarization organic film (160).

[0137] A second planarization organic film (180) may be placed on the first planarization organic film (160) and the second source connection electrode (PCE2).

[0138] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), the third gate insulating film (133), and the interlayer insulating film (141) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon oxide nitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0139] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0140] The first planarization organic film (160) and the second planarization organic film (180) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0141] A light-emitting element layer may be arranged on the second planarizing organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), light-emitting elements (LE), a common electrode (CE), and an organic film (190).

[0142] A pixel electrode layer may be disposed on the second planarization organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a second source connection electrode (PCE2) through a connection hole (CT1 / CT2 / CT3 of FIG. 5) penetrating the second planarization organic film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a first source region (S1) or a first drain region (D1) of a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin film transistor (TFT1) can be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0143] The pixel electrode layer may be formed as a single layer or multiple layers made of one or an alloy of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). For example, in order to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu) having a low surface resistance.

[0144] A first organic film (210) may be disposed on the second planarizing organic film (180) and each of the pixel electrodes (PXE1, PXE2, PXE3). The first organic film (210) serves to temporarily fix or adhere the plurality of light emitting elements (LEs) to prevent the plurality of light emitting elements (LEs) from tilting and falling over or falling over during the process of transferring the plurality of light emitting elements (LEs) to the display panel (100). That is, the first organic film (210) may be a film for temporarily adhering the plurality of light emitting elements (LEs) onto each of the pixel electrodes (PXE1, PXE2, PXE3). To facilitate the temporary adhering, the thickness of the first organic film (210) may be greater than the thickness of each of the pixel electrodes (PXE1, PXE2, PXE3) and may be greater than the thickness of the contact electrode (CTE).

[0145] The first organic film (210) may be a photosensitive organic film such as a photoresist. Alternatively, the first organic film (210) may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0146] A plurality of light emitting elements (LE) may be arranged on the first organic film (210). In FIGS. 6 and 7, it is exemplified that each of the plurality of light emitting elements (LE) is a vertical type micro LED extending in a third direction (DR3). The vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged in the third direction (DR3), which is a vertical direction.

[0147] Each of the plurality of light emitting elements (LEs) may have a cross-sectional shape of a reverse taper. That is, each of the plurality of light emitting elements (LEs) may have a cross-sectional shape of a trapezoid in which the width of the upper surface is wider than the width of the lower surface.

[0148] Each of the plurality of light emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3) of several to several hundred μm, respectively. For example, each of the plurality of light emitting elements (LE) may have a length in the first direction (DR1), a length in the second direction (DR2), and a length in the third direction (DR3) of approximately 100 μm or less, respectively.

[0149] Each of the plurality of light emitting elements (LEs) can be grown and formed on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light emitting elements (LEs) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100). Alternatively, the plurality of light emitting elements (LEs) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) through an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0150] A light emitting element (LE) may include a conductive layer (E1), a semiconductor stack (STC), a contact electrode (CTE), and a passivation layer (INS). The semiconductor stack (STC) may include a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) sequentially arranged in a third direction (DR3).

[0151] The conductive layer (E1) may be disposed on the lower surface of the first semiconductor layer (SEM1). In Fig. 7, the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), but the embodiment of the present specification is not limited thereto. For example, the conductive layer (E1) may be disposed on a portion of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0152] The first semiconductor layer (SEM1) may be disposed on the conductive layer (E1). The first semiconductor layer (SEM1) may be formed of a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), or the like, for example, gallium nitride (GaN).

[0153] The active layer (MQW) can be disposed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light by the combination of electron-hole pairs in response to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0154] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately laminated. In this case, the well layers may be formed of indium gallium nitride (InGaN), and the barrier layer may be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments of the present specification are not limited thereto.

[0155] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials having a large band gap energy and semiconductor materials having a small band gap energy are alternately laminated, or may include different group 3 to group 5 semiconductor materials depending on the wavelength of the emitted light.

[0156] For example, when the active layer (MQW) includes indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer may shift toward a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer may shift toward a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of the light-emitting element (LE) that emits the third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0157] A second semiconductor layer (SEM2) may be disposed on the first semiconductor layer (SEM1). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), or tin (Sn), for example, gallium nitride (GaN).

[0158] An electron blocking layer may be disposed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer that suppresses or prevents too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer may be omitted.

[0159] The superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN). The superlattice layer may be omitted.

[0160] Light extraction patterns (LEPs) can be formed on the upper surface of the semiconductor stack (STC). For example, the light extraction patterns (LEPs) can be formed on the upper surface of the second semiconductor layer (SEM2).

[0161] Light extraction patterns (LEPs) may be patterns for increasing the efficiency of light emitted from the upper surface of the light emitting element (LE). The light extraction patterns (LEPs) may be concave patterns formed in a hemisphere or a semi-ellipse. The light extraction patterns (LEPs) may be concave patterns having a cross-sectional shape of a semicircle or a semi-ellipse. The maximum length (Lmax) of the light extraction patterns (LEPs) in the third direction (DR3) may be approximately 100 nm. In addition, the distance between adjacent light extraction patterns (LEPs) may be approximately 100 nm or less.

[0162] The light extraction patterns (LEPs) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. Alternatively, the light extraction patterns (LEPs) can be formed of an inorganic film such as silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0163] The protective film (INS) may be a film for protecting the lower surface and side surfaces (e.g., the outer surface) of the light emitting element (LE). The protective film (INS) may be disposed on the lower surface and side surfaces of the conductive layer (E1) and the side surfaces of the semiconductor stack (STC). Specifically, the protective film (INS) may be disposed on the lower surface and side surfaces of the conductive layer (E1), the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2). The protective film (INS) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0164] A plurality of contact electrodes (CTEs) may be disposed on the protective film (INS). Each of the plurality of contact electrodes (CTEs) may be disposed between the first organic film (210) and the protective film (INS). Each of the plurality of contact electrodes (CTEs) may be in contact with the first organic film (210).

[0165] Although FIGS. 6 and 7 illustrate that the contact electrode (CTE) of each of the light-emitting elements (LE) is disposed on the first organic film (210), the embodiment of the present specification is not limited thereto. For example, the first organic film (210) may be disposed on the lower surface and a portion of the side surface of the contact electrode (CTE) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surface of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surface of the first semiconductor layer (SEM1), the side surface of the active layer (MQW), and the side surface of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the first organic film (210) may be disposed on a portion of the side surface of the second semiconductor layer (SEM2).

[0166] Each of the plurality of contact electrodes (CTE) can be connected to a conductive layer (E1) that is exposed and not covered by a protective film (INS). As a result, even if one of the plurality of contact electrodes (CTE) is not connected to the conductive layer (E1) due to a process error, the occurrence of a defect in which the light emitting element (LE) does not light up can be prevented by connecting another contact electrode (CTE) to the conductive layer (E1).

[0167] When a plurality of contact electrodes (CTEs) are formed of a metal with high reflectivity, light emitted from the active layer (MQW) of the light emitting element (LE) that propagates in the lateral direction of the light emitting element (LE) can be reflected by the plurality of contact electrodes (CTEs) and emitted to the upper surface of the light emitting element (LE). Therefore, since light loss of the light emitting element (LE) can be reduced, the light efficiency of the light emitting element (LE) can be increased. Therefore, in order to increase the light efficiency of the light emitting element (LE), it is preferable that each of the plurality of contact electrodes (CTEs) be arranged to cover most of the lateral surface (e.g., the outer peripheral surface) of the semiconductor stack (STC).

[0168] The plurality of contact electrodes (CTEs) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, the plurality of contact electrodes (CTEs) may be formed as a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) to increase reflectivity.

[0169] Each of the plurality of contact electrodes (CTEs) may be disposed on a side surface (e.g., an outer surface) of the semiconductor stack (STC). Among the side surfaces of the semiconductor stack (STC), a region adjacent to a top surface of the semiconductor stack (STC) may be covered by a protective film (INS), but may be exposed without being covered by the plurality of contact electrodes (CTEs). For example, a separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3). Here, the third direction (DR3) may be substantially the same as a height direction (or thickness direction) of the light emitting element (LE). In this way, when the contact electrode (CTE) is spaced apart from the upper surface of the semiconductor stack (STC), the contact electrode (CTE) exposed to the upper surface of the semiconductor stack (STC) during the manufacturing process can be prevented from being peeled off by a chemical solution or the like.

[0170] The connecting electrode (BE) connects the contact electrode (CTE) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3). The connecting electrode (BE) can be connected to the pixel electrode (PXE1 / PXE2 / PXE3) exposed through a connecting hole (BH) penetrating the first organic film (210). In addition, the connecting electrode (BE) can be disposed on the upper surface of the first organic film (210) and the contact electrode (CTE).

[0171] The connecting electrode (BE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, the connecting electrode (BE) may be made of a transparent conductive material (TCO), such as indium tin oxide (ITO) and indium zinc oxide (IZO).

[0172] The connection electrode (BE) may be arranged on a side surface (e.g., an outer surface) of the semiconductor stack (STC). Among the side surfaces of the semiconductor stack (STC), a region adjacent to a top surface of the semiconductor stack (STC) may be exposed without being covered by the connection electrode (BE). For example, a separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3).

[0173] The separation distance (DS2) between the upper surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be greater than the separation distance (DS1) between the upper surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3), but the embodiment of the present specification is not limited thereto. For example, the separation distance (DS2) between the upper surface of the semiconductor stack (STC) and the connection electrode (BE) in the third direction (DR3) may be smaller than the separation distance (DS1) between the upper surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3). In this case, the connection electrode (BE) may cover at least a part of the protective film (INS) that is exposed and not covered by the contact electrode (CTE). Alternatively, the connection electrode (BE) may be arranged to cover the entirety of the protective film (INS) that is exposed and not covered by the contact electrode (CTE). As another example, the separation distance (DS2) between the top surface of the semiconductor stack (STC) and the connecting electrode (BE) in the third direction (DR3) may be substantially equal to the separation distance (DS1) between the top surface of the semiconductor stack (STC) and the contact electrode (CTE) in the third direction (DR3).

[0174] The second organic film (211) may be arranged to cover a portion of the side surface of the plurality of light emitting elements (LE). In addition, the second organic film (211) may be arranged to cover the connection electrode (BE). The second organic film (211) may be arranged on the first organic film (210).

[0175] The third organic film (212) may be disposed on the second organic film (211). The third organic film (212) may be disposed to cover another portion of a side surface of each of the plurality of light-emitting elements (LE). The third organic film (212) may be disposed on the protective film (INS), the contact electrode (CTE), and the connection electrode (BE) that are not covered by the second organic film (211) and are exposed as shown in FIG. 7, but the embodiment of the present specification is not limited thereto. For example, the entire connection electrode (BE) may be covered by the second organic film (211). The upper surface of each of the plurality of light-emitting elements (LE) may be exposed and not covered by the third organic film (212).

[0176] The second organic film (211) and the third organic film (212) are layers for leveling the steps caused by the plurality of light-emitting elements (LE). If the height of the second organic film (211) is arranged to cover most of the side surfaces of each of the plurality of light-emitting elements (LE), the third organic film (212) may be omitted.

[0177] The second organic film (211) and the third organic film (212) can be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0178] A common electrode (CE) may be disposed on the upper surface of each of the plurality of light emitting elements (LE) and the upper surface of the third organic film (212). The common electrode (CE) may be a common layer formed in common on the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). The common electrode (CE) may be made of a transparent metal material (TCO, Transparent Conductive Material), such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide), which can transmit light.

[0179] The pixel electrodes (PXE1, PXE2, PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode (CE) may be referred to as cathode electrodes or second electrodes.

[0180] The first capping layer (CAP1) can be disposed on the common electrode (CE).

[0181] A light-shielding layer (BM), a first light conversion layer (QDL1), a second light conversion layer (QDL2), and a light-transmitting layer (TPL) may be disposed on a first capping layer (CAP1). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light-transmitting layer (TPL) may be formed by the partitioning of the light-shielding layer (BM). Therefore, in the first sub-pixel (SPX1), the first light conversion layer (QDL1) may be disposed on the first capping layer (CAP1), in the second sub-pixel (SPX2), the second light conversion layer (QDL2) may be disposed on the first capping layer (CAP1), and in the third sub-pixel (SPX3), the light-transmitting layer (TPL) may be disposed on the first capping layer (CAP1). The light-shielding layer (BM) may not overlap with a plurality of light-emitting elements (LE) in the third direction (DR3).

[0182] The first light conversion layer (QDL1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band). The first light conversion layer (QDL1) can include a first base resin (BRS1) and a first wavelength conversion particle (WCP1). The first base resin (BRS1) can include a light-transmitting organic material. The first wavelength conversion particle (WCP1) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into first light (light in the red wavelength band).

[0183] The second light conversion layer (QDL2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band). It can include a second base resin (BRS2) and second wavelength conversion particles (WCP2). The second base resin (BRS2) can include a light-transmitting organic material. The second wavelength conversion particles (WCP2) can convert a portion of the third light (light in the blue wavelength band) incident from the light emitting element (LE) into second light (light in the green wavelength band).

[0184] The optically transparent layer (TPL) may include a light-transmitting organic material.

[0185] For example, the first base resin (BRS1), the second base resin (BRS2), and the light transmitting layer (TPL) may include an epoxy resin, an acrylic resin, a cardo resin, or an imide resin. The first and second wavelength conversion particles (WCP1, WCP2) may be quantum dots (QDs), quantum rods, fluorescent materials, or phosphorescent materials.

[0186] The light-blocking layer (BM) may include a first light-blocking layer (BM1) and a second light-blocking layer (BM2) that are sequentially laminated. The length of the first light-blocking layer (BM1) in the first direction (DR1) or the length of the second direction (DR2) may be wider than the length of the second light-blocking layer (BM2) in the first direction (DR1) or the length of the second light-blocking layer (BM2) in the second direction (DR2). The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may be formed of an organic film such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin. The first light-blocking layer (BM1) and the second light-blocking layer (BM2) may include a light-blocking material to prevent light from a light-emitting element (LE) of a sub-pixel from propagating to an adjacent sub-pixel. For example, the first shading layer (BM1) and the second shading layer (BM2) may include an inorganic black pigment such as carbon black or an organic black pigment.

[0187] The second capping layer (CAP2) may be disposed on the first capping layer (CAP1) and the light-shielding layer (BM). The second capping layer (CAP2) may be disposed on the side surface and the upper surface of the light-shielding layer (BM). That is, the second capping layer (CAP2) may be disposed on the side surface of the first light-shielding layer (BM1) and the side surface and the upper surface of the second light-shielding layer (BM2).

[0188] A reflective film (RF) may be disposed between a light-shielding layer (BM) and a first light conversion layer (QDL1), between a light-shielding layer (BM) and a second light conversion layer (QDL2), and between a light-shielding layer (BM) and a light-transmitting layer (TPL). The reflective film (RF) may be disposed on a second capping layer (CAP2) disposed on a side surface of the first light-shielding layer (BM1) and a side surface of the second light-shielding layer (BM2). The reflective film (RF) serves to reflect light that propagates in a lateral direction in the first light-conversion layer (QDL1), the second light-conversion layer (QDL2), and the light-transmitting layer (TPL).

[0189] The reflective film (RF) may include a highly reflective metal material, such as aluminum (Al). The thickness of the reflective film (RF) may be approximately 0.1 μm.

[0190] Alternatively, the reflective film (RF) may include M pairs of first and second layers having different refractive indices (M is an integer greater than or equal to 2) to function as Distributed Bragg Reflectors (DBR). In this case, the M first layers and the M second layers may be arranged alternately. The first and second layers may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx).

[0191] The third capping layer (CAP3) can be disposed on the second capping layer (CAP2), the first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL).

[0192] The first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3) may be formed of an inorganic film, for example, silicon nitride (SiNx), silicon oxynitride (SiON), silicon oxide (SiOx), titanium oxide (TiOx), or aluminum oxide (AlOx). The first light conversion layer (QDL1), the second light conversion layer (QDL2), and the light transmitting layer (TPL) may be encapsulated by the first capping layer (CAP1), the second capping layer (CAP2), and the third capping layer (CAP3).

[0193] A fourth organic film (213) may be disposed on the second capping layer (CAP2). A plurality of color filters (CF1, CF2, CF3) may be disposed on the fourth organic film (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0194] The first color filter (CF1) arranged in the first sub-pixel (SPX1) can transmit the first light (light in the red wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the first color filter (CF1) can transmit the first light (light in the red wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the first sub-pixel (SPX1) can emit the first light (light in the red wavelength band).

[0195] The second color filter (CF2) arranged in the second sub-pixel (SPX2) can transmit the second light (light in the green wavelength band) and absorb or block the third light (light in the blue wavelength band). Therefore, the second color filter (CF2) can transmit the second light (light in the green wavelength band) converted by the first light conversion layer (QDL1) among the third light (light in the blue wavelength band) emitted from the light-emitting element (LE), and absorb or block the third light (light in the blue wavelength band) not converted by the first light conversion layer (QDL1). Therefore, the second sub-pixel (SPX2) can emit the second light (light in the green wavelength band).

[0196] The third color filter (CF3) arranged in the third sub-pixel (SPX3) can transmit the third light (light in the blue wavelength band). Therefore, the third color filter (CF3) can transmit the third light (light in the blue wavelength band) emitted from the light-emitting element (LE) passing through the light-transmitting layer (TPL). Therefore, the third sub-pixel (SPX3) can emit the third light (light in the blue wavelength band).

[0197] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap with the bank (190) and the light-shielding layer (BM) in the third direction (DR3).

[0198] A fifth organic film (214) for planarization may be placed on a plurality of color filters (CF1, CF2, CF3).

[0199] The fourth organic film (213) and the fifth organic film (214) can be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0200] Fig. 8 is an image showing the first side area. Fig. 9 is an image showing an enlarged view of the S1 area of ​​the first side area. Fig. 10 is an image showing the second side area.

[0201] Referring to FIGS. 7 to 10, the protective film (INS) includes a first side region (INS1) that is exposed and not covered by the contact electrode (CTE) and a second side region (INS2) that is covered by the contact electrode (CTE). Since the first side region (INS1) is exposed and not covered by the contact electrode (CTE), it is exposed to the etchant, whereas the second side region (INS2) is covered by the contact electrode (CTE), it may not be exposed to the etchant. Therefore, the surface roughness of the first side region (INS1) may be greater than the surface roughness of the second side region (INS2), as shown in FIGS. 8 to 10. That is, the surface of the second side region (INS2) may be smoother than the surface of the first side region (INS1).

[0202] In summary, by forming the surface of the first side region (INS1) to have a rough shape rather than a smooth one, the efficiency of light emitted from the first side region (INS1) of the light emitting element (LE) can be increased.

[0203] Figure 11 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0204] The embodiment of FIG. 11 differs from the embodiment of FIG. 7 in that the light emitting element (LE) includes a single contact electrode (CTE) rather than multiple contact electrodes (CTEs). In FIG. 11, descriptions that overlap with the embodiment of FIG. 7 will be omitted, and differences from the embodiment of FIG. 7 will be mainly described.

[0205] Referring to Fig. 11, a plurality of regions of the conductive layer (E1) can be exposed without being covered by the protective film (INS). The contact electrode (CTE) can be connected to the conductive layer (E1) in each of the plurality of regions of the conductive layer (E1). Accordingly, even if the contact electrode (CTE) is not connected to the conductive layer (E1) in one of the plurality of regions due to a process error, the occurrence of a defect in which the light-emitting element (LE) does not light up can be prevented by connecting to the conductive layer (E1) in another region.

[0206] Figure 12 is a cross-sectional view showing another example of area A1 of Figure 6 in detail.

[0207] The embodiment of FIG. 12 differs from the embodiment of FIG. 7 in that the light emitting element (LE) includes a single contact electrode (CTE) rather than multiple contact electrodes (CTEs). In FIG. 12, descriptions that overlap with the embodiment of FIG. 7 will be omitted, and differences from the embodiment of FIG. 7 will be mainly described.

[0208] Referring to FIG. 12, the conductive layer (E1) may be exposed without being covered by the protective film (INS). The contact electrode (CTE) may be connected to the exposed conductive layer (E1) without being covered by the protective film (INS).

[0209] Fig. 13 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I1-I1' of Fig. 5. Fig. 14 is a cross-sectional view showing in detail another example of area A2 of Fig. 13.

[0210] The embodiments of FIGS. 13 and 14 differ from the embodiments of FIGS. 6 and 7 in that each of the organic films (210) is disposed on a portion of the upper surface of the pixel electrode (PXE). In FIGS. 13 and 14, descriptions that overlap with the embodiments of FIGS. 6 and 7 will be omitted, and descriptions will be focused on differences from the embodiments of FIGS. 6 and 7.

[0211] Referring to FIGS. 13 and 14, since each of the organic films (210) is disposed on a portion of the upper surface of the pixel electrode (PXE), there is no need to form a connecting hole (BH) for exposing the pixel electrode (PXE). The connecting electrode (BE) may be disposed on the upper surface of the pixel electrode (PXE) that is not covered by the organic film (210). The connecting electrode (BE) may be disposed on the upper surface and side surfaces of the organic film (210).

[0212] FIG. 15 is a layout diagram showing pixels of a display area according to one embodiment.

[0213] The embodiment of FIG. 15 differs from the embodiment of FIG. 5 in that the light emitting elements (LEs) are arranged on the pixel electrodes (PXE1 / PXE2 / PXE3) and the common electrodes (CE1 / CE2 / CE3) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). In FIG. 15, descriptions that overlap with the embodiment of FIG. 5 will be omitted, and descriptions will be focused on differences from the embodiment of FIG. 5.

[0214] Referring to FIG. 15, pixel electrodes (PXE1 / PXE2 / PXE3) and common electrodes (CE1 / CE2 / CE3) may be arranged in the second direction (DR2) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3). Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE1, CE2, CE3) may have a rectangular planar shape, but the embodiment of the present specification is not limited thereto. The area of ​​the first pixel electrode (PXE1) may be the same as the area of ​​the first common electrode (CE1), the area of ​​the second pixel electrode (PXE2) may be the same as the area of ​​the second common electrode (CE2), and the area of ​​the third pixel electrode (PXE3) may be the same as the area of ​​the third common electrode (CE3), but the embodiment of the present specification is not limited thereto.

[0215] When the light conversion efficiency of the second light conversion layer (QDL2) is lower than the light conversion efficiency of the first light conversion layer (QDL1), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1), and the area of ​​the second common electrode (CE2) may be larger than the area of ​​the first common electrode (CE1). In addition, while the light transmitting layer (TPL) directly transmits the light of the light emitting element (LE), the first light conversion layer (QDL1) must convert the light, and therefore, the area of ​​the first pixel electrode (PXE1) may be larger than the area of ​​the third pixel electrode (PXE3), and the area of ​​the first common electrode (CE1) may be larger than the area of ​​the third common electrode (CE3).

[0216] The first common electrode (CE1) can be connected to a second power line (VSL) to which a second driving voltage (VSS) is applied through a first common connection hole (CT4). The second common electrode (CE2) can be connected to the second power line (VSL) through a second common connection hole (CT5). The third common electrode (CE3) can be connected to the second power line (VSL) through a third common connection hole (CT6). Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE1, CE2, and CE3).

[0217] In each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3), the pixel electrodes (PXE1 / PXE2 / PXE3) and the common electrodes (CE1 / CE2 / CE3) and the light-emitting elements (LE) are disposed on the pixel electrodes (PXE1 / PXE2 / PXE3) and the common electrodes (CE1 / CE2 / CE3), so that the length of the light-emitting elements (LE) in the second direction (DR2) can be longer than the length in the first direction (DR1).

[0218] Fig. 16 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 15. Fig. 17 is a cross-sectional view showing in detail an example of area B1 of Fig. 16.

[0219] The embodiments of FIGS. 16 and 17 differ from the embodiments of FIGS. 6 and 7 in that the light emitting element (LE) is a flip-type micro LED. In FIGS. 16 and 17, descriptions that overlap with the embodiments of FIGS. 6 and 7 will be omitted, and differences from the embodiments of FIGS. 6 and 7 will be mainly described.

[0220] Referring to FIGS. 16 and 17, a pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) and common electrodes (CE1, CE2, CE3) can be placed on a second planarizing organic film (180).

[0221] The light emitting element (LE) may be a flip-type micro LED. A flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one surface (e.g., the lower surface) of the light emitting element (LE).

[0222] The semiconductor stack (STC) of the light emitting element (LE) may further include a third semiconductor layer (SEM3). The third semiconductor layer (SEM3) is a semiconductor material layer having an n-type dopant lower than a predetermined threshold value and may be referred to as an undoped semiconductor layer. For example, the third semiconductor layer (SEM3) may be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), or indium nitride (InN) having an n-type dopant lower than a predetermined threshold value.

[0223] The third semiconductor layer (SEM3) may be disposed on the second semiconductor layer (SEM2). In this case, the light extraction pattern (LEP) may be formed on the upper surface of the third semiconductor layer (SEM3).

[0224] Although FIG. 17 illustrates that the protective film (INS) is disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), the side surfaces of the second semiconductor layer (SEM2), and the side surfaces of the third semiconductor layer (SEM3) of the semiconductor stack (STC), the embodiment of the present specification is not limited thereto. For example, the protective film (INS) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of the semiconductor stack (STC), but may not be disposed on the side surfaces of the third semiconductor layer (SEM3).

[0225] A hole (LEH) can be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of the present specification are not limited thereto. For example, the hole (LEH) may have a polygonal planar shape, such as an ellipse or a square.

[0226] Additionally, the protective film (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), and the sidewall of the active layer (MQW). The protective film (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH). Therefore, the second semiconductor layer (SEM2) may be exposed without being covered by the protective film (INS).

[0227] The first contact electrode (CTE1) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). The first contact electrode (CTE1) may be disposed on the lower surface of the conductive layer (E1) that is exposed and not covered by the protective film (INS). Therefore, the first contact electrode (CTE1) may be electrically connected to the conductive layer (E1).

[0228] The second contact electrode (CTE2) may be disposed on at least one side of the semiconductor stack (STC) and on at least one side and the lower surface of the conductive layer (E1). In this case, the first contact electrode (CTE1) may be disposed on the first side of the semiconductor stack (STC) and the first side of the conductive layer (E1), while the second contact electrode (CTE2) may be disposed on the second side of the semiconductor stack (STC) and the second side of the conductive layer (E1).

[0229] The second contact electrode (CTE2) can be disposed on the passivation layer (INS) disposed in the hole (LEH) and the second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the passivation layer (INS). Therefore, the second contact electrode (CTE2) can be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0230] Although FIGS. 16 and 17 illustrate that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light-emitting elements (LE) are disposed on the first organic film (210), the embodiment of the present specification is not limited thereto. For example, the first organic film (210) may be disposed on a portion of the lower surface and side surface of the first contact electrode (CTE1) of each of the light-emitting elements (LE) and a portion of the lower surface and side surface of the second contact electrode (CTE2) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surfaces of the conductive layer (E1) of each of the light-emitting elements (LE). Alternatively, the first organic film (210) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of each of the light-emitting elements (LE). In this case, the first organic film (210) may be disposed on a portion of each of the side surfaces of the second semiconductor layer (SEM2).

[0231] On each of the sides of the semiconductor stack (STC), an area adjacent to the upper surface of the semiconductor stack (STC) is covered by a protective film (INS), but may be exposed without being covered by the first contact electrode (CTE1) or the second contact electrode (CTE2). For example, a separation distance (DS1_1) between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3) may be greater than approximately 100 nm. In addition, a separation distance (DS1_1) between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3) may be greater than a maximum length (Lmax) of the light extraction pattern in the third direction (DR3). In this way, when the first contact electrode (CTE1) is spaced apart from the upper surface of the semiconductor stack (STC), the first contact electrode (CTE1) exposed to the upper surface of the semiconductor stack (STC) during the manufacturing process can be prevented from being peeled off by a chemical solution or the like.

[0232] In addition, the separation distance (DS1_1) between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the separation distance (DS1_1) between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3) may be greater than the maximum length (Lmax) of the light extraction pattern in the third direction (DR3). In this way, when the second contact electrode (CTE2) is spaced apart from the upper surface of the semiconductor stack (STC), the second contact electrode (CTE2) exposed to the upper surface of the semiconductor stack (STC) during the manufacturing process can be prevented from being peeled off by a chemical solution or the like.

[0233] Each of the first contact electrode (CTE1) and the second contact electrode (CTE2) may be disposed on three sides of the semiconductor stack (STC). For example, when the semiconductor stack (STC) includes first to fourth sides, the first contact electrode (CTE1) may be disposed on the first side, the second side, and the third side, and the second contact electrode (CTE2) may be disposed on the second side, the third side, and the fourth side.

[0234] The first connection electrode (BE1) connects the first contact electrode (CTE1) of the light emitting element (LE) and the pixel electrode (PXE1 / PXE2 / PXE3). The first connection electrode (BE1) can be connected to the pixel electrode (PXE1 / PXE2 / PXE3) exposed through the first connection hole (BH1) penetrating the first organic film (210). In addition, the first connection electrode (BE1) can be disposed on the upper surface of the first organic film (210) and the first contact electrode (CTE1).

[0235] The first connection electrode (BE1) may include a first sub-connection electrode (BE11) and a second sub-connection electrode (BE12) disposed on the first sub-connection electrode (BE11). The first sub-connection electrode (BE11) and the second sub-connection electrode (BE12) may include the same material or different materials. Each of the first sub-connection electrode (BE11) and the second sub-connection electrode (BE12) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the first sub-connection electrode (BE11) and the second sub-connection electrode (BE12) may be made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0236] The second connection electrode (BE2) connects the second contact electrode (CTE2) of the light emitting element (LE) and the common electrode (CE1 / CE2 / CE3). The second connection electrode (BE2) may be connected to the common electrode (CE1 / CE2 / CE3) exposed through the second connection hole (BH2) penetrating the first organic film (210). In addition, the second connection electrode (BE2) may be disposed on the upper surface of the first organic film (210) and the second contact electrode (CTE2).

[0237] The second connection electrode (BE2) may include a third sub-connection electrode (BE21) and a fourth sub-connection electrode (BE22) disposed on the third sub-connection electrode (BE21). The third sub-connection electrode (BE21) and the fourth sub-connection electrode (BE22) may include the same material or different materials. Each of the third sub-connection electrode (BE21) and the fourth sub-connection electrode (BE22) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Alternatively, each of the third sub-connection electrode (BE21) and the fourth sub-connection electrode (BE22) may be made of a transparent metal material (TCO, Transparent Conductive Material) such as ITO (Indium Tin Oxide) and IZO (Indium Zinc Oxide).

[0238] As shown in FIGS. 16 and 17, the conductive layer (E1) of the light-emitting element (LE) can be connected to the pixel electrodes (PXE1 / PXE2 / PXE3) through the first contact electrode (CTE1) and the first connection electrode (BE1). In addition, the second semiconductor layer (SEM2) of the light-emitting element (LE) can be connected to the common electrodes (CE1 / CE2 / CE3) through the second contact electrode (CTE2) and the second connection electrode (BE2) formed in the hole (LEH).

[0239] In addition, on each of the sides of the semiconductor stack (STC), an area adjacent to the upper surface of the semiconductor stack (STC) may be exposed without being covered by the first connection electrode (BE1) or the second connection electrode (BE2). For example, a distance DS2_1 between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may be greater than approximately 100 nm. In addition, a distance DS2_1 between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may be greater than a maximum length Lmax of the light extraction pattern in the third direction (DR3). In this way, when the first connection electrode (BE1) is spaced apart from the upper surface of the semiconductor stack (STC), the first connection electrode (BE1) exposed to the upper surface of the semiconductor stack (STC) may be prevented from being peeled off by a chemical solution or the like during the manufacturing process.

[0240] In addition, the distance DS2_1 between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may be greater than the distance DS1_1 between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3), but the embodiment of the present specification is not limited thereto. For example, the distance DS2_1 between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may be smaller than the distance DS1_1 between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3). In this case, the first connection electrode (BE1) may cover at least a portion of the protective film (INS) that is exposed and not covered by the first contact electrode (CTE1). Alternatively, the first connection electrode (BE1) may be arranged to cover the entirety of the exposed protective film (INS) that is not covered by the first contact electrode (CTE1). As another example, the separation distance (DS2_1) between the upper surface of the semiconductor stack (STC) and the first connection electrode (BE1) in the third direction (DR3) may be substantially equal to the separation distance (DS1_1) between the upper surface of the semiconductor stack (STC) and the first contact electrode (CTE1) in the third direction (DR3).

[0241] In addition, the separation distance (DS2_1) between the upper surface of the semiconductor stack (STC) and the second connection electrode (BE2) in the third direction (DR3) may be greater than approximately 100 nm. In addition, the separation distance (DS2_1) between the upper surface of the semiconductor stack (STC) and the second connection electrode (BE2) in the third direction (DR3) may be greater than the maximum length (Lmax) of the light extraction pattern in the third direction (DR3). In this way, when the second connection electrode (BE2) is spaced apart from the upper surface of the semiconductor stack (STC), the second connection electrode (BE2) exposed to the upper surface of the semiconductor stack (STC) during the manufacturing process can be prevented from being peeled off by a chemical solution or the like.

[0242] In addition, the distance DS2_1 between the upper surface of the semiconductor stack (STC) and the second connection electrode (BE2) in the third direction (DR3) may be greater than the distance DS1_1 between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3), but the embodiment of the present specification is not limited thereto. For example, the distance DS2_1 between the upper surface of the semiconductor stack (STC) and the second connection electrode (BE2) in the third direction (DR3) may be smaller than the distance DS1_1 between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3). In this case, the second connection electrode (BE2) may cover at least a portion of the protective film (INS) that is exposed and not covered by the second contact electrode (CTE2). Alternatively, the second connection electrode (BE2) may be arranged to cover the entirety of the exposed protective film (INS) that is not covered by the second contact electrode (CTE2). As another example, the separation distance (DS2_1) between the upper surface of the semiconductor stack (STC) and the second connection electrode (BE2) in the third direction (DR3) may be substantially equal to the separation distance (DS2_1) between the upper surface of the semiconductor stack (STC) and the second contact electrode (CTE2) in the third direction (DR3).

[0243] Fig. 18 is a cross-sectional view showing another example of a cross-section of a display panel corresponding to line I2-I2' of Fig. 15. Fig. 19 is a cross-sectional view showing another example of area B2 of Fig. 18 in detail.

[0244] The embodiments of FIGS. 18 and 19 differ from the embodiments of FIGS. 16 and 17 in that each of the organic films (210) is disposed on a portion of the upper surface of the pixel electrodes (PXE1 / PXE2 / PXE3) and a portion of the upper surface of the common electrode (CE). In FIGS. 18 and 19, descriptions that overlap with the embodiments of FIGS. 16 and 17 will be omitted, and descriptions will be focused on differences from the embodiments of FIGS. 16 and 17.

[0245] Referring to FIGS. 18 and 19, since each of the organic films (210) is disposed on a portion of the upper surface of each of the pixel electrodes (PXE1, PXE2, PXE3) and a portion of each of the common electrodes (CE1, CE2, CE3), there is no need to form a first connection hole (BH1) for exposing each of the pixel electrodes (PXE1, PXE2, PXE3) and a second connection hole (BH2) for exposing each of the common electrodes (CE1, CE2, CE3).

[0246] Each of the first connection electrodes (BE1) may be disposed on an upper surface of a pixel electrode (PXE1 / PXE2 / PXE3) that is not covered by the organic film (210). Each of the second connection electrodes (BE2) may be disposed on an upper surface of a common electrode (CE1 / CE2 / CE3) that is not covered by the organic film (210). In addition, each of the first connection electrode (BE1) and the second connection electrodes (BE2) may be disposed on an upper surface and at least one side surface of the organic film (210).

[0247] Fig. 20 is a flowchart showing a method for manufacturing a display device according to one embodiment. Figs. 21 to 29 are exemplary drawings for explaining a method for manufacturing a display device according to one embodiment. Fig. 30 is a layout diagram showing a light-emitting element and a second mask pattern of step S140 of Fig. 20. Fig. 31 is a cross-sectional view showing an example of a cross-section corresponding to line I3-I3' of Fig. 30.

[0248] Hereinafter, a method for manufacturing a display device according to one embodiment will be described in detail with reference to FIGS. 20 to 31. For convenience of explanation, cross-sections corresponding to the line I2-I2' of FIG. 15 are illustrated in FIGS. 21 to 29.

[0249] First, as shown in Fig. 21, a third semiconductor material layer (SEML3), a second semiconductor material layer (SEML2), an active material layer (MQWL), a first semiconductor material layer (SEML1), and a conductive material layer (EL1) are formed on a semiconductor substrate (SSUB). (S110 of Fig. 20)

[0250] The semiconductor substrate (SSUB) may be a silicon wafer substrate or a sapphire substrate. A light extraction pattern layer (LEPL) is formed on one surface of the semiconductor substrate (SSUB). The light extraction pattern layer (LEPL) may include convex patterns formed in a hemisphere or a semi-ellipse. The light extraction pattern layer (LEPL) may include convex patterns having a cross-sectional shape of a semicircle or a semi-ellipse. The light extraction pattern layer (LEPL) may be formed of a semiconductor material layer, an organic film, or an inorganic film.

[0251] Then, a third semiconductor material layer (SEML3) is formed on the light extraction pattern layer (LEPL). Due to the light extraction pattern layer (LEPL), light extraction patterns (LEP of FIG. 17) can be formed on one surface of the third semiconductor material layer (SEML3). The second semiconductor material layer (SEML2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), or tin (Sn). The third semiconductor material layer (SEML3) may be a semiconductor material layer in which an n-type dopant is lower than an appropriate threshold value (for example, a predetermined threshold value) and may be an undoped semiconductor layer. For example, the third semiconductor material layer (SEML3) can be indium aluminum gallium nitride (InAlGaN), gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), aluminum nitride (AlN), and / or indium nitride (InN) having an n-type dopant lower than a suitable threshold (e.g., a predetermined threshold).

[0252] Then, an active material layer (MQWL) is formed on the second semiconductor material layer (SEML2), and a first semiconductor material layer (SEML1) is formed on the active material layer (MQWL). The active material layer (MQWL) may include the same semiconductor material layer as the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2). For example, when the first semiconductor material layer (SEML1) and the second semiconductor material layer (SEML2) include gallium nitride (GaN), the active material layer (MQWL) may also include gallium nitride (GaN). For example, the active material layer (MQWL) may include at least one of gallium nitride (GaN), indium gallium nitride (InGaN), and aluminum gallium nitride (AlGaN). The first semiconductor material layer (SEML1) may be a semiconductor material layer doped with a first conductive dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc.

[0253] The light extraction pattern layer (LEPL), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) can be formed on a semiconductor substrate (SSUB) through an epitaxial growth process. As the epitaxial growth process, a method for forming the light extraction pattern layer (LEPL), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), and the first semiconductor material layer (SEML1) can be used, such as electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-type thermal evaporation, sputtering, and metal-organic chemical vapor deposition (MOCVD). Preferably, metal-organic chemical vapor deposition (MOCVD) may be used, but the embodiments of the present disclosure are not limited thereto.

[0254] Then, a conductive material layer (EL1) is formed on the first semiconductor material layer (SEML1). The conductive material layer (EL1) can be formed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0255] Secondly, as shown in Fig. 22, the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) are etched to form light emitting elements (LE). (S120 of Fig. 20)

[0256] After forming a mask pattern on the conductive material layer (EL1), the third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) are etched according to the mask pattern. The mask pattern can be removed after forming the light emitting elements (LE).

[0257] The third semiconductor material layer (SEML3), the second semiconductor material layer (SEML2), the active material layer (MQWL), the first semiconductor material layer (SEML1), and the conductive material layer (EL1) can be etched by a dry etching method, a wet etching method, a reactive ion etching (RIE), a deep reactive ion etching (DRIE), an inductively coupled plasma reactive ion etching (ICP-RIE), or the like. In the case of the dry etching method, anisotropic etching is possible and thus may be suitable for vertical etching. When the dry etching method is used, the etching gas may be, but is not limited to, chlorine (Cl2) or oxygen (O2) gas.

[0258] Then, a hole (LEH) is formed in each of the light emitting elements (LE) to penetrate the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) and expose the second semiconductor layer (SEM2).

[0259] Thirdly, as shown in Fig. 23, a protective material layer (INSL) surrounding the light emitting elements (LE) is formed, and a first mask pattern (MP1) is formed on the protective material layer (INSL). (S130 of Fig. 20)

[0260] The protective layer (INSL) can be fully deposited on one surface of the semiconductor substrate (SSUB). The protective layer (INSL) can be formed to cover one surface and side surfaces of the light emitting elements (LEs). The protective layer (INSL) can be formed on one surface of the semiconductor substrate (SSUB) exposed between the light emitting elements (LEs).

[0261] The first mask pattern (MP1) may be formed to expose a portion of the hole (LEH) of each of the light-emitting elements (LE). For example, the first mask pattern (MP1) may be formed so as not to cover the protective material layer (INSL) disposed on the bottom surface of the hole (LEH) of each of the light-emitting elements (LE). In addition, the first mask pattern (MP1) may be formed to expose a portion of the protective material layer (INSL) disposed on one surface of each of the light-emitting elements (LE).

[0262] Fourth, as shown in Fig. 24, the protective material layer (INSL) not covered by the first mask pattern (MP1) is etched to form a second mask pattern (MP2). (S140 of Fig. 20)

[0263] The protective material layer (INSL) not covered by the first mask pattern (MP1) can be etched by dry etching. The protective material layer (INSL) disposed on one surface of each of the light emitting elements (LE) is etched, thereby exposing the conductive layer (E1) without being covered by the protective material layer (INSL). In addition, the protective material layer (INSL) disposed between the light emitting elements (LE) is etched, thereby exposing the semiconductor substrate (SSUB).

[0264] In addition, when a large upper and lower voltage difference is formed in dry etching and the protective material layer (INSL) is etched, the etching gas proceeds in the third direction (DR3) and etches the protective material layer (INSL). As a result, the protective material layer (INSL) arranged on the sidewall of the hole (LEH) of each of the light emitting elements (LE) can remain without being etched even if it is not protected by the first mask pattern (MP1). Accordingly, the protective material layer (INSL) arranged on the bottom surface of the hole (LEH) of each of the light emitting elements (LE) is etched, and the second semiconductor material layer (SEML2) in the hole (LEH) of each of the light emitting elements (LE) can be exposed without being covered by the protective material layer (INSL).

[0265] Then, the first mask pattern (MP1) can be removed by an ashing process.

[0266] Then, the second mask pattern (MP2) may be formed on a portion of one surface of each of the light emitting elements (LE) and between the light emitting elements (LE), as shown in FIGS. 24, 30, and 31. The thickness (T1) of the second mask pattern (MP2) disposed on one surface of each of the light emitting elements (LE) may be different from the thickness (T2 / T3) of the second mask pattern (MP2) disposed between the light emitting elements (LE).

[0267] Referring to FIGS. 30 and 31, the second mask pattern (MP2) may include a first sub-mask pattern region (MP21) having a first thickness (T1) in a third direction (DR3) and a second sub-mask pattern region (MP22) having a thickness lower than the first thickness (T1). The second sub-mask pattern region (MP22) may be formed to have a gradually decreasing thickness along the second direction (DR2) as it moves away from the first sub-mask pattern region (MP21) by controlling a developing time.

[0268] Fifth, as shown in Fig. 25, a contact electrode layer (CTEL) is deposited on one side of a semiconductor substrate (SSUB). (S150 in Fig. 20)

[0269] A contact electrode layer (CTEL) may be formed to cover one surface and side surfaces of the light emitting elements (LE). The contact electrode layer (CTEL) may be arranged to cover the second mask pattern (MP2). The contact electrode layer (CTEL) may be formed on one surface of the semiconductor substrate (SSUB) exposed between the light emitting elements (LE).

[0270] Sixth, as shown in FIG. 26, the second mask pattern (MP2) is removed through a lift-off process, and first contact electrodes (CTE1) and second contact electrodes (CTE2) are formed. (S160 of FIG. 20)

[0271] To remove the second mask pattern (MP2) through a lift-off process, the second mask pattern (MP2) may be formed of a negative photoresist. In this case, only the second mask pattern (MP2) and the contact electrode layer (CTEL) disposed on the second mask pattern (MP2) may be removed through a solvent ashing process using alcohol.

[0272] When the second mask pattern (MP2) is removed, the first contact electrode (CTE1) connected to the conductive layer (E1) and the second contact electrode (CTE2) connected to the second semiconductor layer (SEM2) are positioned apart from each other, and thus can be electrically isolated from each other. In addition, the first contact electrode (CTE1) and the second contact electrode (CTE2) can be exposed without covering the protective material layer (INSL) positioned on the side of the third semiconductor layer (SEML3).

[0273] Meanwhile, by lowering the thickness (T2 / T3) of the second mask pattern (MP2) disposed between the light-emitting elements (LE) than the thickness (T1) of the second mask pattern (MP2) disposed on one surface of each of the light-emitting elements (LE), the area that the first contact electrode (CTE1) and the second contact electrode (CTE2) cover on the protective material layer (INSL) disposed on the side surface of the semiconductor stack (STC) can be increased. As a result, among the light emitted from the active layer (MQW) of the light-emitting element (LE), light that propagates in the side direction of the light-emitting element (LE) can be reflected and emitted to the upper surface of the light-emitting element (LE) due to the first contact electrode (CTE1) and the second contact electrode (CTE2). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased.

[0274] Then, in order to form unevenness on the surface of the protective film (INS) and increase the surface roughness, the protective film (INS) exposed on the side surfaces of the semiconductor stack (STC) and not covered by the first contact electrode (CTE1) and the second contact electrode (CTE2) may be exposed to an etchant at a predetermined temperature for a predetermined period of time. The etchant may be tetramethylammonium hydroxide (TMAH), but the embodiments of the present specification are not limited thereto. The predetermined temperature may be approximately 90°C, and the predetermined period of time may be approximately 3 to 30 minutes. When the period of exposing the protective film (INS) to the etchant is less than 3 minutes and greater than 30 minutes, unevenness may not be formed on the surface of the protective film (INS).

[0275] Seventh, as shown in Fig. 27, an insulating film (FL) is formed between the light-emitting elements (LE), the light-emitting elements (LE) are transferred to the first organic film (210) placed on the pixel electrodes (PXE), and the semiconductor substrate (SSUB) is removed. (S170 of Fig. 20)

[0276] In order to prevent the light emitting elements (LEs) from being detached or moved from the semiconductor substrate (SSUB) due to external impact during the transfer process, an insulating film (FL) may be formed between the light emitting elements (LEs). The insulating film (FL) may be formed of an organic film or an inorganic film.

[0277] Although FIG. 27 illustrates that the insulating film (FL) fills the entire space between the light-emitting elements (LE), the embodiments of the present specification are not limited thereto. For example, the insulating film (FL) may fill part of the space between the light-emitting elements (LE).

[0278] The light emitting elements (LEs) may be moved onto the first organic film (210) disposed on the pixel electrodes (PXE). At this time, the light emitting elements (LEs) may be temporarily fixed by being embedded in the first organic film (210). In FIG. 27, it is exemplified that the first contact electrode (CTE1) and the second contact electrode (CTE2) of each of the light emitting elements (LEs) are disposed on the first organic film (210), but the embodiment of the present specification is not limited thereto. For example, the first organic film (210) may be disposed on a lower surface and a part of a side surface of the first contact electrode (CTE1) of each of the light emitting elements (LEs) and a part of a lower surface and a part of a side surface of the second contact electrode (CTE2) of each of the light emitting elements (LEs). Alternatively, the first organic film (210) may be disposed on the side surfaces of the conductive layer (E1) of each of the light emitting elements (LEs). Alternatively, the first organic film (210) may be disposed on the side surfaces of the first semiconductor layer (SEM1), the side surfaces of the active layer (MQW), and the side surfaces of the second semiconductor layer (SEM2) of each of the light emitting elements (LE). In this case, the first organic film (210) may be disposed on a portion of each of the side surfaces of the second semiconductor layer (SEM2).

[0279] When the fluidity of the first organic film (210) is low or the first organic film (210) is hard, the depth at which the light emitting element (LE) is inserted or embedded in the first organic film (210) may be very small, or the light emitting element (LE) may be placed on the first organic film (210) without being inserted or embedded in the first organic film (210).

[0280] When the first organic film (210) is a photosensitive organic film such as a photoresist, after the first organic film (210) is cured (soft baked) at a first temperature, at least a portion of each of the plurality of light-emitting elements (LE) is inserted into the first organic film (210). Then, the first organic film (210) can be completely cured at a second temperature higher than the first temperature. The first temperature may be approximately 100 degrees, and the second temperature may be approximately 230 degrees, but the embodiments of the present specification are not limited thereto. In addition, the process of completely curing the first organic film (210) at the second temperature may be performed for approximately 30 minutes.

[0281] Then, the semiconductor substrate (SSUB) is removed by a laser lift-off process. Alternatively, if the light-emitting elements (LEs) are transferred to a separate transfer substrate rather than the semiconductor substrate (SSUB), the transfer substrate may be removed instead of the semiconductor substrate (SSUB).

[0282] Eighth, as shown in Fig. 28, the insulating film (FL) is removed, first connection electrodes (BE1) and second connection electrodes (BE2) are formed, and a second organic film (211) and a third organic film (212) are formed. (S180 of Fig. 20)

[0283] The insulating film (FL) can be removed using a chemical solution. The insulating film (FL) can be an organic film or an inorganic film, and the chemical solution can be hydrochloric acid (HCl) and tetramethylammonium hydroxide (TMAH), but the embodiments of the present specification are not limited thereto.

[0284] When the first contact electrode (CTE1) and the second contact electrode (CTE2) are arranged to cover the entire side surface of the semiconductor stack (STC), the first contact electrode (CTE1) and the second contact electrode (CTE2) exposed on the upper surface of the semiconductor stack (STC) can be exposed to the chemical solution. The chemical solution can penetrate between the first contact electrode (CTE1) and the protective film (INS) and between the second contact electrode (CTE2) and the protective film (INS), and thus the first contact electrode (CTE1) and the second contact electrode (CTE2) can be peeled from the protective film (INS).

[0285] However, in one embodiment of the present specification, since the first contact electrode (CTE1) and the second contact electrode (CTE2) are each spaced apart from the upper surface of the semiconductor stack (STC), the first contact electrode (CTE1) and the second contact electrode (CTE2) may be protected by the insulating film (FL) and may not be exposed to the chemical solution. Therefore, the first contact electrode (CTE1) and the second contact electrode (CTE2) may be prevented from being peeled off by the chemical solution.

[0286] Then, first connection electrodes (BE1) for connecting the first contact electrode (CTE1) and the pixel electrode (PXE) of the light-emitting element (LE) disposed on the first organic film (210) and second connection electrodes (BE2) for connecting the second contact electrode (CTE2) and the common electrode (PXE) are formed.

[0287] Then, a second organic film (211) and a third organic film (212) are formed to fix the light emitting elements (LEs) and to level the steps caused by the light emitting elements (LEs).

[0288] Ninth, as shown in Fig. 29, a light-shielding layer, a wavelength conversion layer, a light-transmitting layer, and a color filter layer are formed sequentially. (S190 of Fig. 20)

[0289] A first capping layer (CPL1) is formed on the third organic film (212) and the light-emitting elements (LE), and a first light-blocking layer (BM1) and a second light-blocking layer (BM2) are formed on the first capping layer (CPL1) so as not to overlap with the light-emitting elements (LE) in the third direction (DR). Then, a second capping layer (CPL2) covering the first light-blocking layer (BM1), the second light-blocking layer (BM2), and the first capping layer (CPL1) is formed. Then, a reflective film (RF) is formed covering the second capping layer (CPL2) disposed on the first light-blocking layer (BM1) and the second light-blocking layer (BM2).

[0290] Then, a first light conversion layer (QDL1) is formed on each of the first sub-pixels (SPX1), a second light conversion layer (QDL2) is formed on each of the second sub-pixels (SPX2), and a light transmitting layer (TPL) is formed on each of the third sub-pixels (SPX3). Then, a third capping layer (CPL3) is formed to cover the first light conversion layers (QDL1), the second light conversion layers (QDL2), and the light transmitting layers (TPL). Then, a fourth organic film (213) is formed on the third capping layer (CPL3).

[0291] Then, a first color filter (CF1) is formed on the fourth organic film (213) to overlap the first light conversion layers (QDL1) in the third direction (DR3), a second color filter (CF2) is formed to overlap the second light conversion layers (QDL2) in the third direction (DR3), and a third color filter (CF3) is formed to overlap the light transmitting layers (TPL) in the third direction (DR3). The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) can all be formed in the region overlapping the first light-blocking layer (BM1) and the second light-blocking layer (BM2) in the third direction (DR3).

[0292] Then, a fifth organic film (214) is formed on the first color filter (CF1), the second color filter (CF2), and the third color filter (CF3).

[0293] FIG. 32 is an exemplary drawing showing a smartwatch including a display device according to one embodiment.

[0294] Referring to FIG. 32, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0295] FIGS. 33 and 34 are exemplary drawings showing a virtual reality device including a display device according to one embodiment.

[0296] Referring to FIGS. 33 and 34, a head-mounted display device (1000_2) according to one embodiment includes a first display device (10_2), a second display device (10_3), a display device storage unit (1100), a storage unit cover (1200), a first eyepiece lens (1210), a second eyepiece lens (1220), a head-mounted band (1300), a middle frame (1400), a first optical member (1510), a second optical member (1520), and a control circuit board (1600).

[0297] The first display device (10_2) provides an image to the user's left eye, and the second display device (10_3) provides an image to the user's right eye. Since each of the first display device (10_2) and the second display device (10_3) is substantially the same as the display device (10) described in conjunction with FIGS. 1 and 2, descriptions of the first display device (10_2) and the second display device (10_3) are omitted.

[0298] The first optical member (1510) may be positioned between the first display device (10_2) and the first eyepiece lens (1210). The second optical member (1520) may be positioned between the second display device (10_3) and the second eyepiece lens (1220). Each of the first optical member (1510) and the second optical member (1520) may include at least one convex lens.

[0299] The middle frame (1400) is disposed between the first display device (10_2) and the control circuit board (1600), and may be disposed between the second display device (10_3) and the control circuit board (1600). The middle frame (1400) serves to support and fix the first display device (10_2), the second display device (10_3), and the control circuit board (1600).

[0300] The control circuit board (1600) may be placed between the middle frame (1400) and the display device housing (1100). The control circuit board (1600) may be connected to the first display device (10_2) and the second display device (10_3) via connectors. The control circuit board (1600) may convert an image source input from the outside into digital video data (DATA) and transmit the digital video data (DATA) to the first display device (10_2) and the second display device (10_3) via the connectors.

[0301] The control circuit board (1600) can transmit digital video data (DATA) corresponding to a left-eye image optimized for the user's left eye to the first display device (10_2) and digital video data (DATA) corresponding to a right-eye image optimized for the user's right eye to the second display device (10_3). Alternatively, the control circuit board (1600) can transmit the same digital video data (DATA) to the first display device (10_2) and the second display device (10_3).

[0302] The display device storage unit (1100) serves to store the first display device (10_2), the second display device (10_3), the middle frame (1400), the first optical member (1510), the second optical member (1520), and the control circuit board (1600). The storage unit cover (1200) is arranged to cover an open surface of the display device storage unit (1100). The storage unit cover (1200) may include a first eyepiece (1210) for the user's left eye and a second eyepiece (1220) for the user's right eye. In FIGS. 33 and 34, the first eyepiece (1210) and the second eyepiece (1220) are separately arranged, but the embodiment of the present specification is not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0303] The first eyepiece (1210) can be aligned with the first display device (10_2) and the first optical member (1510), and the second eyepiece (1220) can be aligned with the second display device (10_3) and the second optical member (1520). Accordingly, the user can view the image of the first display device (10_2) enlarged into a virtual image by the first optical member (1510) through the first eyepiece (1210), and can view the image of the second display device (10_3) enlarged into a virtual image by the second optical member (1520) through the second eyepiece (1220).

[0304] The head-mounted band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be positioned respectively for the user's left and right eyes. If the display device storage unit (1200) is implemented in a lightweight and compact form, the head-mounted display device (1000) may be equipped with a glasses frame as shown in FIG. 35 instead of the head-mounted band (800).

[0305] In addition, the head-mounted display device (1000) may further include a battery for supplying power, an external memory slot for storing external memory, and an external connection port and wireless communication module for receiving a video source. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0306] Fig. 35 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. Fig. 35 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0307] Referring to FIG. 35, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. The virtual reality device (1000_3) according to one embodiment may include a display device (10_4), a left-eye lens (10a), a right-eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device storage unit (50).

[0308] In Fig. 35, it is exemplified that the virtual reality device (1000_3) is a glasses-type display device including glasses frame legs (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that illustrated in Fig. 35, and can be applied in various forms in various other electronic devices.

[0309] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user may view a virtual reality image displayed on the display device (10_4) through the right eye.

[0310] In FIG. 35, the display device housing (50) is exemplified as being arranged at the right end of the support frame (20), but the embodiment of the present specification is not limited thereto. For example, the display device housing (50) may be arranged at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected by the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user may view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be arranged at both the left end and the right end of the support frame (20), in which case the user may view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0311] Fig. 36 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment. Fig. 36 shows an automobile to which display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment are applied.

[0312] Referring to FIG. 36, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to a dashboard of a vehicle, a center fascia of a vehicle, or a CID (Center Information Display) placed on a dashboard of a vehicle. In addition, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0313] FIG. 37 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0314] Referring to FIG. 37, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light at the same time. Therefore, a user positioned at the front of the transparent display device can not only view the image (IM) displayed on the display device (10_5), but also view an object (RS) or background positioned at the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) can include a light-transmitting portion that can transmit light or can be formed of a material that can transmit light.

[0315] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A pixel electrode disposed on the substrate; An organic film disposed on the pixel electrode; and It comprises a light-emitting element disposed on the organic film, The above light emitting element, semiconductor stack; A protective film disposed on the side of the semiconductor stack; and It includes a contact electrode disposed on the above protective film, A display device in which a portion of a side surface of the semiconductor stack is exposed and not covered by the contact electrode, and the contact electrode is positioned away from the upper surface of the semiconductor stack.

2. In paragraph 1, The above semiconductor stack, A first semiconductor layer disposed on the organic film and including a first semiconductor material layer doped with a first conductive dopant; An active layer disposed on the first semiconductor layer; and It further comprises a second semiconductor layer disposed on the above active layer and including a second semiconductor material layer doped with a second conductive dopant, A display device in which the contact electrode is disposed on the entire side surface of the first semiconductor layer and the entire side surface of the active layer, and on a portion of the side surface of the second semiconductor layer.

3. In paragraph 1, The above light emitting element, Further comprising a conductive layer disposed between the organic film and the semiconductor stack, A display device in which the above contact electrode is disposed on the protective film and is connected to an exposed conductive layer that is not covered by the protective film.

4. In paragraph 3, A display device in which the distance between the upper surface of the semiconductor stack and the contact electrode in the height direction of the light-emitting element is greater than 100 nm.

5. In paragraph 3, A display device wherein the light emitting element further includes light extraction patterns having a concave cross-sectional shape on the upper surface of the semiconductor stack.

6. In paragraph 5, A display device in which a distance between the upper surface of the semiconductor stack and the contact electrode in the height direction of the light emitting element is greater than the maximum length of any one of the light extraction patterns in the height direction of the light emitting element.

7. In paragraph 3, The protective film includes a first side region that is exposed and not covered by the contact electrode on the side of the light-emitting element and a second side region that is covered by the contact electrode, A display device in which the surface roughness of the first side region is greater than the surface roughness of the second side region.

8. In paragraph 3, A display device further comprising a connecting electrode connected to the pixel electrode through a connecting hole penetrating the organic film and connected to the contact electrode disposed on a side of the light-emitting element.

9. In paragraph 8, A display device in which the distance between the upper surface of the semiconductor stack and the connecting electrode in the height direction of the light-emitting element is greater than 100 nm.

10. Substrate; A pixel electrode disposed on the substrate; An organic film disposed on the pixel electrode and the common electrode; and It comprises a light-emitting element disposed on the organic film, The above light emitting element, semiconductor stack; A conductive layer disposed between the organic film and the semiconductor stack; A protective film disposed on the side surfaces of the conductive layer and the side surfaces of the semiconductor stack; a first contact electrode disposed on the protective film and connected to the exposed conductive layer not covered by the protective film; and A second contact electrode is disposed on the protective film and is disposed in a hole penetrating the conductive layer and a portion of the semiconductor stack, A display device in which each of the first contact electrode and the second contact electrode is positioned apart from the upper surface of the semiconductor stack.

11. In paragraph 10, A display device wherein a part of a first side among the side surfaces of the semiconductor stack is exposed without being covered by the first contact electrode, and a part of a second side among the side surfaces of the semiconductor stack is exposed without being covered by the second contact electrode.

12. In paragraph 10, The above semiconductor stack, A first semiconductor layer disposed on the organic film and including a first semiconductor material layer doped with a first conductive dopant; An active layer disposed on the first semiconductor layer; and It further comprises a second semiconductor layer disposed on the above active layer and including a second semiconductor material layer doped with a second conductive dopant, The first contact electrode is disposed on the first side of the first semiconductor layer and the first side of the active layer, and is disposed on a portion of the first side of the second semiconductor layer. A display device in which the second contact electrode is disposed on the second side of the first semiconductor layer and the second side of the active layer, and is disposed on a portion of the second side of the second semiconductor layer.

13. In paragraph 10, A display device in which a distance between the upper surface of the semiconductor stack and the first contact electrode or the second contact electrode in the height direction of the light-emitting element is greater than 100 nm.

14. In paragraph 10, A display device wherein the light emitting element further includes a light extraction pattern having a concave cross-sectional shape on the upper surface of the semiconductor stack.

15. In paragraph 14, A display device in which a distance between the upper surface of the semiconductor stack and the first contact electrode or the second contact electrode in the height direction of the light emitting element is greater than the maximum length of the light extraction pattern in the height direction of the light emitting element.

16. In paragraph 10, The protective film includes a first side region that is exposed and not covered by the first contact electrode or the second contact electrode on the side of the light-emitting element and a second side region that is covered by the contact electrode, A display device in which the surface roughness of the first side region is greater than the surface roughness of the second side region.

17. In paragraph 10, A first connecting electrode connected to the pixel electrode through a first connecting hole penetrating the organic film and connected to the first contact electrode disposed on a side of the light-emitting element; and A display device further comprising a second connecting electrode connected to the common electrode through a second connecting hole penetrating the organic film and connected to the second contact electrode disposed on another side of the light-emitting element.

18. In paragraph 17, A display device in which a distance between the upper surface of the semiconductor stack and the first connection electrode or the second connection electrode in the height direction of the light-emitting element is greater than 100 nm.

19. A step of forming a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer on a semiconductor substrate; A step of etching a second semiconductor material layer, an active material layer, a first semiconductor material layer, and a conductive material layer to form light-emitting elements each including a second semiconductor layer, an active layer, a first semiconductor layer, and a conductive layer; A step of forming a hole penetrating the conductive layer, the first semiconductor layer, and the active layer in each of the light-emitting elements; A step of forming a protective material layer surrounding each of the light-emitting elements and patterning the protective material layer to form a protective film; A step of forming a mask pattern on the protective film and forming a contact electrode layer; A step of removing the mask pattern to lift off and form a first contact electrode connected to the conductive layer in each of the light-emitting elements, and a second contact electrode connected to the second semiconductor layer in the hole; A step of transferring the light emitting elements onto an organic film disposed on the pixel electrodes and the common electrodes so that the conductive layer faces the pixel electrodes and the common electrodes in each of the light emitting elements; and A method for manufacturing a display device, comprising the step of forming a first connection electrode connecting the first contact electrode of each of the light-emitting elements to one of the pixel electrodes, and a second connection electrode connecting the second contact electrode to one of the common electrodes.

20. In paragraph 19, The above mask pattern is, A first sub-mask pattern region extending in a first direction and formed to have a first thickness; and A method for manufacturing a display device, comprising a second sub-mask pattern region having a thickness smaller than the first thickness and formed to have a thickness that gradually decreases along a second direction intersecting the first direction as it moves away from the first sub-mask pattern region.

Images