Array substrate, manufacturing method thereof and display device

Abstract

An array substrate, a manufacturing method thereof, and a display device, the array substrate comprising: a substrate; a thin film transistor disposed on the substrate; a first passivation layer, an organic film layer, and a pixel electrode disposed on the thin film transistor; and a connection structure for connecting a source electrode of the thin film transistor and the pixel electrode, wherein the connection structure is disposed in a via structure exposing the pixel electrode and the source electrode, or the connection structure is disposed between the pixel electrode and the source electrode.

Description

TECHNICAL FIELD

[0001] The embodiment of the present disclosure relates to, but is not limited to, the technical field of display, and in particular to an array substrate, a preparation method thereof, and a display device. BACKGROUND

[0002] In recent years, liquid crystal display (LCD) has been rapidly developed due to its small size, low power consumption, and no radiation. The liquid crystal display panel includes a thin film transistor (TFT) array substrate and a color filter (CF) substrate in a cell. Liquid crystal (LC) molecules are arranged between the array substrate and the color filter substrate. An electric field for driving the liquid crystal to deflect is formed by controlling a common electrode and a pixel electrode, so as to realize gray scale display.

[0003] The present disclosure has found that some array substrates have a problem that the pixel electrode and the source electrode cannot be effectively connected. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein.

[0005] In one aspect, the present disclosure provides an array substrate, comprising:

[0006] a substrate;

[0007] a thin film transistor disposed on the substrate;

[0008] a first passivation layer, an organic film layer, and a pixel electrode disposed on the thin film transistor;

[0009] a connection structure for connecting a source electrode of the thin film transistor and the pixel electrode, wherein the connection structure is disposed in a via structure exposing the pixel electrode and the source electrode, or the connection structure is disposed between the pixel electrode and the source electrode.

[0010] In another aspect, the present disclosure further provides a display device, comprising the array substrate in the above embodiment.

[0011] In another aspect, the present disclosure further provides a preparation method of an array substrate, comprising:

[0012] forming a substrate, and forming a thin film transistor on the substrate;

[0013] Forming a first passivation layer, an organic film layer and a pixel electrode on a thin film transistor, forming a via structure exposing the pixel electrode and a source electrode of the thin film transistor, and forming a connection structure for connecting the source electrode and the pixel electrode in the via structure exposing the pixel electrode and the source electrode of the thin film transistor; or forming a first passivation layer, an organic film layer and a pixel electrode on a thin film transistor, and forming a connection structure for connecting the source electrode and the pixel electrode between the pixel electrode and the source electrode; or forming a first passivation layer, an organic film layer and a pixel electrode on a thin film transistor, and forming a via structure exposing the source electrode, the pixel electrode being connected with the source electrode through the via structure exposing the source electrode.

[0014] Of course, practicing any of the products or methods of the present disclosure does not necessarily achieve all of the above-mentioned advantages at the same time.

[0015] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are included to provide a further understanding of the technical solutions of the present disclosure, together with the embodiments of the present disclosure to explain the technical solutions of the present disclosure, and do not constitute limitations to the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the true proportions, and the purpose is only to schematically illustrate the present disclosure.

[0017] FIG. 1A Structure diagram of an array substrate in some technologies;

[0018] FIG. 1B Structure diagram of an array substrate in some technologies after forming an organic film layer;

[0019] FIG. 1C Structure diagram of an array substrate in some technologies after etching a first passivation layer;

[0020] FIG. 1D Structure diagram of an array substrate in some technologies after ashing an organic film layer;

[0021] FIG. 2A Structure diagram of an array substrate in an exemplary embodiment of the present disclosure;

[0022] FIG. 2B Structure diagram of an array substrate in an exemplary embodiment of the present disclosure after forming a pixel electrode;

[0023] FIG. 2C Structure diagram of an array substrate in an exemplary embodiment of the present disclosure after forming a second passivation layer;

[0024] FIG. 2DThis is a schematic diagram of etching the second passivation layer and the first passivation layer in an exemplary embodiment of the present disclosure;

[0025] FIG. 3A This is a schematic diagram of the structure of the array substrate in another exemplary embodiment of the present disclosure;

[0026] FIG. 3B This is a schematic diagram showing the formation of an organic film layer in another exemplary embodiment of this disclosure;

[0027] FIG. 3C This is a schematic diagram of the first passivation layer after etching in another exemplary embodiment of this disclosure;

[0028] FIG. 3D This is a schematic diagram of the organic film layer after ashing treatment in another exemplary embodiment of this disclosure;

[0029] FIG. 4A This is a schematic diagram of the structure of the array substrate in yet another exemplary embodiment of the present disclosure;

[0030] FIG. 4B This is a schematic diagram showing the formation of the first passivation layer in yet another exemplary embodiment of this disclosure;

[0031] FIG. 4C This is a schematic diagram of the first passivation layer after etching in yet another exemplary embodiment of this disclosure;

[0032] FIG. 4D This is a schematic diagram of the formation of an organic film layer in yet another exemplary embodiment of this disclosure.

[0033] Explanation of reference numerals in the attached figures:

[0034] 10—Substrate; 11—Gate electrode; 12—Gate insulating layer;

[0035] 13—Active layer; 14—Source electrode; 15—Drain electrode;

[0036] 16—First passivation layer; 17—Organic film layer; 18—Pixel electrode;

[0037] 19—Second passivation layer; 20—Common electrode; 21—Etching layer;

[0038] 22—Connection structure. Detailed Implementation

[0039] This document describes several embodiments, but these descriptions are exemplary and not limiting. Many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the accompanying drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0040] In describing representative embodiments, this disclosure may present methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. Other sequences of steps are possible, as will be understood by those skilled in the art. Furthermore, schemes for the method and / or process should not be limited to performing the steps in the written order, and those skilled in the art will readily understand that these orders can be varied while still remaining within the spirit and scope of the embodiments of this disclosure.

[0041] Unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar terms used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0042] In this document, a transistor is defined as a device comprising at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (or drain terminal, drain region, or drain electrode) and the source electrode (or source terminal, source region, or source electrode), through which current can flow. In this document, the channel region refers to the area through which current primarily flows.

[0043] In this paper, when using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" can sometimes be interchanged. Therefore, in this paper, the "source electrode" and "drain electrode" can be interchanged.

[0044] In this document, "electrical connection" includes the situation where constituent elements are connected together by a component that has some electrical function. There are no particular restrictions on the "component that has some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. The "component that has some electrical function" can be, for example, an electrode or wiring, a switching element such as a transistor, or other functional elements such as a resistor, inductor, or capacitor.

[0045] The "patterning process" mentioned in the embodiments of this disclosure includes processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping, which are mature fabrication processes in some technologies. Deposition can employ known processes such as sputtering, evaporation, and chemical vapor deposition; coating can employ known coating processes; and etching can employ known methods, without limitation. In the description of the embodiments of this disclosure, it should be understood that a "thin film" refers to a thin film made of a certain material on a substrate using deposition or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer". If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern".

[0046] FIG. 1A These are schematic diagrams of the structure of array substrates in some technologies, such as... FIG. 1A As shown, the array substrate may include: a substrate 10, a gate electrode 11 disposed on the substrate 10, a gate insulator (GI) 12 covering the gate electrode 11, an active layer 13, a source electrode 14, and a drain electrode 15 disposed on the gate insulator 12, a conductive channel forming between the source electrode 14 and the drain electrode 15, a first passivation layer (PVX) 16 covering the source electrode 14, the drain electrode 15, and the conductive channel, a first via exposing the source electrode 14 is formed on the first passivation layer 16, and an organic film layer covering the first passivation layer 16. Film (ORG) 17, an organic film layer 17 has a second via formed thereon, which communicates with the first via to form a via structure that exposes the source electrode 14 (i.e., the via structure penetrates the organic film layer 17 and the first passivation layer 16, and exposes the source electrode 14). A pixel electrode 18 is disposed on the organic film layer 17, a second passivation layer 19 is disposed on the pixel electrode 18, and a common electrode 20 is disposed on the second passivation layer 19. The common electrode 20 is used to provide a common voltage, the pixel electrode 18 is used to provide a pixel voltage for display, and the multidimensional electric field generated between the common electrode and the pixel electrode drives the liquid crystal deflection.

[0047] The inventors of this publication have discovered through research that, as FIG. 1B andFIG. 1C As shown, after the masking process of the organic film layer 17 is completed and the etching process of the first passivation layer 16 is performed, the following will be produced: FIG. 1C The undercut problem shown (i.e., the slope angle after etching is greater than 90°) causes the first passivation layer 16 to be recessed inward from the organic film layer 17, which can lead to the pixel electrode 18 being disconnected when connected to the source electrode 14, reducing the yield. Next, the organic film layer 17 can be retracted by adding a photoresist ashing process. At this time, as... FIG. 1D As shown, the first passivation layer 16 is not recessed inward relative to the organic film layer 17. However, during the photoresist ashing process on the organic film layer 17, some metal in the source electrode 14 (i.e., the metal located at the first via position on the first passivation layer 16) undergoes oxidation and corrosion, resulting in a corrosion layer 21. Furthermore, as... FIG. 1A As shown, because some array substrates are prone to having an etched layer 21 between the pixel electrode 18 and the source electrode 14 at the via structure, the pixel electrode 18 will still be disconnected (open) when connected to the source electrode 14, reducing the yield.

[0048] This disclosure provides an array substrate, such as... FIG. 2A or FIG. 3A As shown, the array substrate may include:

[0049] Base 10;

[0050] Thin-film transistor disposed on substrate 10;

[0051] A first passivation layer 16, an organic film layer 17, and a pixel electrode 18 are disposed on a thin-film transistor;

[0052] A connection structure 22 for connecting the source electrode 14 and the pixel electrode 18 of a thin-film transistor, wherein the connection structure 22 is disposed in a via structure exposing the pixel electrode 18 and the source electrode 14, or the connection structure 22 is disposed between the pixel electrode 18 and the source electrode 14.

[0053] In one exemplary embodiment, such as FIG. 2A or FIG. 3A As shown, a thin-film transistor may include a gate electrode 11, an active layer 13, a source electrode 14, and a drain electrode 15. The gate electrode 11 is disposed on a substrate 10 and is covered by a gate insulating layer 12. The active layer 13, the source electrode 14, and the drain electrode 15 are disposed on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0054] In one exemplary embodiment, such as FIG. 2AAs shown, the array substrate may further include: a second passivation layer 19 disposed on the side of the pixel electrode 18 away from the substrate 10; a connection structure 22 disposed in a via structure exposing the pixel electrode 18 and the source electrode 14, which may include: a first via exposed on the first passivation layer 16; a second via communicating with the first via on the organic film layer 17; a third via communicating with the second via on the pixel electrode 18; a fourth via communicating with the third via and exposing the pixel electrode 18 on the second passivation layer 19; the fourth via, the third via, the second via, and the first via forming a via structure exposing the pixel electrode 18 and the source electrode 14; and the connection structure 22 connected to the pixel electrode 18 and the source electrode 14 through the via structure.

[0055] In this way, by using a via structure to expose both the source electrode and the pixel electrode, and setting a connection structure at the location of the via structure, on the one hand, the connection structure can connect to the source electrode exposed in the via structure and the pixel electrode exposed in the via structure; on the other hand, the connection structure can cover the source electrode exposed in the via structure and the pixel electrode exposed in the via structure. Thus, effective connection between the pixel electrode and the source electrode can be guaranteed, improving the yield rate.

[0056] In one exemplary embodiment, such as FIG. 2A As shown, the array substrate may further include: a second passivation layer 19 disposed on the side of the pixel electrode 18 away from the substrate 10, and a common electrode 20 disposed on the side of the second passivation layer 19 away from the substrate 10; wherein, the connection structure 22 and the common electrode 20 may be disposed in the same layer and with the same material. Thus, the common electrode and the connection structure can be formed using a single patterning process.

[0057] In one exemplary embodiment, the material of the connection structure may include indium tin oxide or indium zinc oxide.

[0058] In one exemplary embodiment, such as FIG. 3A As shown, the connection structure 22 is disposed between the pixel electrode 18 and the source electrode 14, and may include: the connection structure 22 is disposed on the side of the source electrode 14 away from the substrate 10; a first passivation layer 16 is disposed on the side of the connection structure 22 away from the substrate 10, and has a first via exposed to the connection structure 10; a second via is formed on the organic film layer 17 communicating with the first via; the second via and the first via form a via structure exposing the connection structure 22; the pixel electrode 18 is connected to the connection structure 22 through the via structure, and the connection structure 22 is connected to the source electrode 14.

[0059] In one exemplary embodiment, the material of the connecting structure is an oxidizing and corrosion-resistant material that is also conductive.

[0060] In one exemplary embodiment, the material that is resistant to oxidation and corrosion and is conductive includes any one of chromium-cobalt alloy, nickel-chromium alloy, and tellurium-nickel-chromium alloy.

[0061] In one exemplary embodiment, the array substrate may also include other film layers, such as common electrode (Com) leads, planarization layers, or touch leads, etc., which are not limited here.

[0062] In one exemplary embodiment, an organic film layer is disposed on the side of the pixel electrode close to the substrate, serving to separate the Touch / Com line (e.g., disposed in the same layer and material as the source electrode and drain electrode) from the material of the pixel electrode source.

[0063] In one exemplary embodiment, the organic film layer may be made of organic materials such as polyimide, naphthoquinone diazide compound, etc.

[0064] In one exemplary embodiment, a first passivation layer is disposed on the side of the organic film layer near the substrate to prevent the organic film layer from contaminating the conductive channel.

[0065] The array substrate provided in this disclosure will be described in detail below, taking as an example that the connection structure for connecting the source electrode and pixel electrode of the thin-film transistor is set in a via structure that exposes the pixel electrode and the source electrode.

[0066] FIG. 2A This is a schematic diagram of the structure of an array substrate in an exemplary embodiment of the present disclosure, as shown below. FIG. 2A As shown, the array substrate may include:

[0067] Base 10;

[0068] A gate electrode 11 disposed on a substrate 10;

[0069] A gate insulating layer 12 covering the gate electrode 11;

[0070] An active layer 13, a source electrode 14, and a drain electrode 15 are disposed on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0071] A first passivation layer 16 covers the source electrode 14, the drain electrode 15 and the conductive channel, and a first via is formed on the first passivation layer 16 to expose the source electrode 14.

[0072] An organic film layer 17 covers the first passivation layer 16, and a second via is formed on the organic film layer 17, which is connected to the first via.

[0073] A pixel electrode 18 is disposed on the organic film layer 17. A third via is formed on the pixel electrode 18. The first end of the pixel electrode 18 extends into the second via, and the second end of the pixel electrode 18 extends into the second via. The third via is located between the first end and the second end of the pixel electrode 18 and is connected to the first via.

[0074] A second passivation layer 19 is disposed on the pixel electrode 18. A fourth via is formed on the second passivation layer 19. The first end of the second passivation layer 19 extends into the third via, and the second end of the second passivation layer 19 extends into the third via. The fourth via is located between the first end and the second end of the second passivation layer 19. The fourth via is connected to the first via and exposes the pixel electrode 18.

[0075] A common electrode 20 and a connection structure 22 are disposed on the second passivation layer 19. The connection structure 22 is located within a via structure, wherein the via structure is formed by a fourth via on the second passivation layer 19, a third via on the pixel electrode 18, a second via on the organic film layer 17, and a first via on the first passivation layer 16 (i.e., the via structure penetrates the second passivation layer 19, the pixel electrode 18, the organic film layer 17, and the first passivation layer 16), and exposes the source electrode 14 and the pixel electrode 18; the connection structure 22 is disposed at the location of the via structure, and is connected to the source electrode 14 exposed in the via structure on the one hand, and to the pixel electrode 18 exposed in the via structure on the other hand, i.e., the connection structure 22 is simultaneously connected to the source electrode 14 and the pixel electrode 18 through the via structure.

[0076] In one exemplary embodiment, such as FIG. 2A As shown, the gate electrode 11, active layer 13, source electrode 14 and drain electrode 15 can form a thin film transistor.

[0077] In one exemplary embodiment, such as FIG. 2A As shown, the pixel electrode 18 can be a plate-shaped electrode, and the common electrode 20 can be a slit electrode. The common electrode 20 and the pixel electrode 18 together form a multi-dimensional electric field to drive the liquid crystal deflection.

[0078] In one exemplary embodiment, the common electrode 20 and the connection structure 22 can be disposed in the same layer and made of the same material. For example, both the common electrode 20 and the connection structure 22 can be made of conductive materials such as indium tin oxide (ITO) or indium zinc oxide (IZO). Here, being disposed in the same layer means that it can be fabricated using a single patterning process. A single patterning process refers to a process in which the required layer structure is formed in a single exposure. A single patterning process may include processes such as depositing a film layer, coating photoresist, mask exposure, development, etching, and photoresist stripping.

[0079] The following is an example FIG. 2ATaking the array substrate shown as an example, the technical solution of the present disclosure is explained through the fabrication process of an array substrate provided in the embodiments of the present disclosure.

[0080] like FIG. 2A to FIG. 2D As shown, a method for fabricating an array substrate provided in this embodiment may include:

[0081] S21. A gate electrode 11 is formed on the substrate 10.

[0082] S22. A gate insulating layer 12 is formed to cover the gate electrode 11, and an active layer 13, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 12, with a conductive channel formed between the source electrode 14 and the drain electrode 15.

[0083] S23, forming a first passivation layer 16 covering the source electrode 14, the drain electrode 15, and the conductive channel.

[0084] S24. An organic film layer 17 covering the first passivation layer 16 is formed, and a second via is formed on the organic film layer 17.

[0085] S25. A pixel electrode 18 is formed on the organic film layer 17. A third via is formed on the pixel electrode 18. The first end of the pixel electrode 18 extends into the second via, and the second end of the pixel electrode 18 extends into the second via. The third via is located between the first end and the second end of the pixel electrode 18, and the third via is connected to the second via.

[0086] S26. A second passivation layer 19 is formed on the pixel electrode 18, and a fourth via exposed on the second passivation layer and a first via exposed on the first passivation layer are formed to expose the pixel electrode 18.

[0087] The first via is connected to the second via, the first end of the second passivation layer 19 extends into the third via, the second end of the second passivation layer 19 extends into the third via, and the fourth via is located between the first end and the second end of the second passivation layer 19. The fourth via is connected to the first via. The via structure can be formed by the first via, the second via, the third via and the fourth via. The second passivation layer 19, the pixel electrode 18, the organic film layer 17 and the first passivation layer 16 in the via structure are etched away, and the source electrode 14 and the pixel electrode 18 are exposed at the same time.

[0088] S27. A common electrode 20 and a connection structure 22 are formed on the second passivation layer 19. The connection structure 22 is located within the via structure (formed by the first via, the second via, the third via, and the fourth via). On the one hand, it is connected to the source electrode 14 exposed in the via structure, and on the other hand, it is connected to the pixel electrode 18 exposed in the via structure. That is, the connection structure 22 is connected to both the source electrode 14 and the pixel electrode 18 through the via structure.

[0089] In one exemplary embodiment, step S21 may include:

[0090] S211, Deposit a first metal thin film on the substrate.

[0091] S212. Coat a layer of photoresist on the first metal film, and use a halftone or grayscale mask to perform step exposure and development on the photoresist, forming an unexposed area (photoresist with a first thickness) at the gate electrode position, and forming a fully exposed area (no photoresist) at other positions.

[0092] S213. The fully exposed area is etched by an etching process to remove the first metal film in the area and form a gate electrode on the substrate.

[0093] In one exemplary embodiment, the substrate may be glass, plastic, or a flexible transparent sheet.

[0094] In one exemplary embodiment, the first metal thin film can be made of metallic materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum-doped zinc oxide (AlZnO), etc., and can be a single-layer structure or a multi-layer composite structure.

[0095] In one exemplary embodiment, step S22 may include:

[0096] S221. A gate insulating film, a semiconductor film, and a second metal film are sequentially deposited on a substrate on which a gate electrode is formed.

[0097] S222. A layer of photoresist is coated on the second metal film. The photoresist is subjected to step exposure and development using a halftone or grayscale mask. Unexposed areas (photoresist with a first thickness) are formed at the source and drain electrode locations, partially exposed areas (photoresist with a second thickness) are formed at the conductive channel locations, and fully exposed areas (no photoresist) are formed at other locations. The first thickness is greater than the second thickness.

[0098] S223. The fully exposed area is etched through the first etching process to remove the second metal film and semiconductor film in the area.

[0099] S224. The photoresist in part of the exposed area is removed by an ashing process to expose the second metal film.

[0100] S225. The second metal film in a partially exposed area is etched by a second etching process to remove the second metal film in that area, and the remaining photoresist is stripped off. A gate insulating layer, an active layer, a source electrode, and a drain electrode are formed on the substrate. A conductive channel is formed between the source electrode and the drain electrode. A semiconductor film is retained below the source electrode and the drain electrode.

[0101] In one exemplary embodiment, the gate insulating film may be made of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure, and may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0102] In one exemplary embodiment, the second metal thin film may be one or more of the following metal materials: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc., and may be a single-layer, double-layer, or multi-layer structure, and may be deposited using a radio frequency magnetron sputtering method.

[0103] In one exemplary embodiment, step S23 may include:

[0104] S231. A first passivation film is deposited on a substrate on which the gate insulating layer, active layer, source electrode and drain electrode are formed.

[0105] S232. A layer of photoresist is coated on the first passivation film. The photoresist is exposed and developed using a single-tone mask to form a fully exposed area (without photoresist) at the first via location and an unexposed area (with photoresist) is formed at other locations.

[0106] In one exemplary embodiment, the first passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0107] In one exemplary embodiment, step S24 may include:

[0108] S241. Deposit an organic film on the first passivation layer.

[0109] S242. Coat a layer of photoresist on the organic film, expose and develop the photoresist using a monochrome mask, form an exposed area with no photoresist at the second via position, and form unexposed areas at other positions while retaining the photoresist.

[0110] S243. The fully exposed area is etched by an etching process to remove the organic film in the area, forming an organic film layer with a second via, which is connected to the first via.

[0111] In one exemplary embodiment, the organic membrane film may be made of organic materials such as polyimide, naphthoquinone diazide compound, etc.

[0112] In one exemplary embodiment, step S25 may include:

[0113] S251. Deposit a first transparent conductive film on the organic film layer and the first passivation layer.

[0114] S252. Coat a layer of photoresist on the first transparent conductive film, expose and develop the photoresist using a monochrome mask, form a fully exposed area (without photoresist) at the third via position, form unexposed areas at other positions, and retain the photoresist.

[0115] S253. The fully exposed area is etched by an etching process to remove the first transparent conductive film in the area, forming a pixel electrode with a third via. The first end of the pixel electrode is inserted into the second via, the second end of the pixel electrode is inserted into the second via, and the third via is located between the first end and the second end of the pixel electrode, and the third via is connected to the first via.

[0116] In one exemplary embodiment, the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0117] In one exemplary embodiment, step S26 may include:

[0118] S261. Deposit a second passivation film on the pixel electrode and the organic film layer.

[0119] S262. Coat a layer of photoresist on the second passivation film, expose and develop the photoresist using a single-tone mask, form a fully exposed area (without photoresist) at the fourth via position, and form unexposed areas (with photoresist) at other positions.

[0120] S263. The fully exposed areas of the second passivation film and the first passivation film are etched by an etching process to remove the second passivation film and the first passivation film in the area, forming a second passivation layer with a fourth via and a first passivation layer with a first via. The first end of the second passivation layer extends into the third via, and the second end of the second passivation layer extends into the third via. The fourth via is located between the first end and the second end of the second passivation layer and is connected to the first via. The first via exposes the source electrode. The via structure can be formed by the first via, the second via, the third via, and the fourth via. The second passivation layer, the pixel electrode, the organic film layer, and the first passivation layer in the via structure are etched away, and the source electrode and the pixel electrode are exposed at the same time.

[0121] In one exemplary embodiment, the second passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0122] In one exemplary embodiment, step S27 may include:

[0123] S271, Deposit a second transparent conductive film on the second passivation layer.

[0124] S272. Coat a layer of photoresist on the second transparent conductive film, expose and develop the photoresist using a monochrome mask, form unexposed areas at the common electrode and connection structure locations while retaining the photoresist, and form exposed areas without photoresist at other locations.

[0125] S273. The fully exposed area is etched by an etching process to remove the second transparent conductive film in the area, forming a common electrode and a connection structure; wherein, the common electrode is a slit electrode; the connection structure is set at the location of the via structure, and is connected to the source electrode exposed in the via structure on the one hand, and to the pixel electrode exposed in the via structure on the other hand, that is, the connection structure is connected to both the source electrode and the pixel electrode through the via structure.

[0126] In one exemplary embodiment, the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0127] Although the fabrication process of the array substrate in this embodiment of the present disclosure was illustrated using a seven-step patterning process as an example, in actual implementation, the array substrate in this embodiment of the present disclosure can also be fabricated by other methods. For example, the gate electrode, gate insulating layer, active layer, source electrode, and drain electrode can be fabricated using a two-step patterning process, where the gate electrode is first formed using a one-step patterning process, and then the gate insulating layer, active layer, source electrode, and drain electrode are formed using another patterning process. Alternatively, the gate insulating layer, active layer, source electrode, and drain electrode can also be fabricated using a two-step patterning process, where the gate insulating layer and active layer are first formed using a one-step patterning process, and then the source electrode and drain electrode are formed using another patterning process. Furthermore, the common electrode and connection structure can also be fabricated using a two-step patterning process, where the common electrode is first formed using a one-step patterning process, and then the connection structure is formed using another patterning process.

[0128] This disclosure provides an array substrate with a via structure penetrating a second passivation layer, a pixel electrode, an organic film layer, and a first passivation layer. The via structure simultaneously exposes both the source electrode and the pixel electrode. A connection structure is provided at the location of the via structure, connecting to both the source electrode and the pixel electrode through the via structure. This eliminates the need for etching the first passivation layer after the organic film masking process, thus avoiding undercutting issues. Furthermore, there is no need for an ashing process to revert the organic film layer, preventing oxidation and corrosion of some metal in the source electrode (i.e., the metal located at the first via on the first passivation layer), thus preventing the formation of a corrosion layer. The connection structure connects to both the exposed source electrode and the exposed pixel electrode through the via structure, ensuring effective connection between the pixel electrode and the source electrode and improving yield.

[0129] The array substrate provided in this disclosure will be described in detail below, taking as an example that the connection structure for connecting the source electrode and the pixel electrode of the thin-film transistor is disposed between the pixel electrode and the source electrode.

[0130] FIG. 3A This is a schematic diagram of the structure of the array substrate in another exemplary embodiment of the present disclosure, as shown below. FIG. 3A As shown, another array substrate provided in this embodiment may include:

[0131] Base 10;

[0132] A gate electrode 11 disposed on a substrate 10;

[0133] A gate insulating layer 12 covering the gate electrode 11;

[0134] An active layer 13, a source electrode 14, and a drain electrode 15 are disposed on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0135] A connection structure 22 covering the source electrode 14 and the drain electrode 15;

[0136] A first passivation layer 16 covers the connection structure 22 and the conductive channel. A first via is formed on the first passivation layer 16 to expose the connection structure 22. At the location of the first via, the second connection structure is connected to the source electrode.

[0137] An organic film (ORG) 17 covers the first passivation layer 16. A second via is formed on the organic film 17. The second via communicates with the first via to form a via structure that exposes the connection structure 22 (i.e., the via structure penetrates the organic film 17 and the first passivation layer 16 and exposes the connection structure 22).

[0138] A pixel electrode 18 is disposed on the organic film layer 17. The pixel electrode 18 is recessed in the direction towards the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode 18 is disposed in the via structure. The bottom of the first groove is connected to the connection structure 22. That is, the connection structure 22 is connected to the source electrode 14 on one hand, and connected to the pixel electrode 18 through the via structure on the other hand. That is, the pixel electrode 18 is connected to the source electrode 14 through the second connection structure 22 and the via structure.

[0139] A second passivation layer 19 covers the pixel electrode 18 and the organic film layer 17. The second passivation layer 19 is recessed in the direction towards the substrate at the location of the first groove to form a second groove. The second groove formed by the second passivation layer 19 is disposed in the first groove.

[0140] A common electrode 20 is disposed on the second passivation layer 19.

[0141] In one exemplary embodiment, the gate electrode 11, the active layer 13, the source electrode 14, and the drain electrode 15 may form a thin-film transistor.

[0142] In one exemplary embodiment, a first passivation layer is disposed on the side of the organic film layer near the substrate to prevent the organic film layer from contaminating the conductive channel.

[0143] In one exemplary embodiment, the pixel electrode 18 can be a plate-shaped electrode, and the common electrode 20 can be a slit electrode. The common electrode 20 and the pixel electrode 18 together form a multidimensional electric field to drive the liquid crystal deflection.

[0144] In one exemplary embodiment, the connection structure may be made of materials that are resistant to oxidation and corrosion and are conductive, such as chromium-cobalt alloy, nickel-chromium alloy, or tellurium-nickel-chromium alloy.

[0145] The following is an example FIG. 3A Taking the array substrate shown as an example, the technical solution of this disclosure is explained through another array substrate fabrication process provided in this embodiment.

[0146] like FIG. 3A to FIG. 3D As shown, another method for fabricating an array substrate provided in this disclosure embodiment may include:

[0147] S31. A gate electrode 11 is formed on the substrate 10.

[0148] S32. A gate insulating layer 12 is formed to cover the gate electrode 11, and an active layer 13, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 12, with a conductive channel formed between the source electrode 14 and the drain electrode 15.

[0149] S33, forming a connection structure 22 covering the source electrode 14 and the drain electrode 15.

[0150] S34. A first passivation layer 16 is formed to cover the connection structure 22 and the conductive channel, and an organic film layer 17 is formed to cover the first passivation layer 16. A first via is formed on the first passivation layer 16 to expose the connection structure 22. The connection structure 23 is connected to the source electrode 14 at the location of the first via. A second via is formed on the organic film layer 17. The second via communicates with the first via to form a via structure that exposes the connection structure 22 (i.e., the via structure penetrates the organic film layer 17 and the first passivation layer 16 and exposes the connection structure 22).

[0151] S35. A pixel electrode 18 is formed on the organic film layer 17. The pixel electrode 18 is recessed in the direction towards the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode 18 is disposed in the via structure. The bottom of the first groove is connected to the connection structure 22. That is, the connection structure 22 is connected to the source electrode 14 on one hand and to the pixel electrode 18 through the via structure on the other hand. That is, the connection structure 22 is connected to both the source electrode 14 and the pixel electrode 18.

[0152] S36. A second passivation layer 19 is formed covering the pixel electrode 18. The second passivation layer 19 is recessed in the direction towards the substrate at the location of the first groove to form a second groove. The second groove formed by the second passivation layer 19 is disposed in the first groove.

[0153] S37. A common electrode 20 is formed on the second passivation layer 19.

[0154] In one exemplary embodiment, step S31 may include:

[0155] S311. Deposit a first metal thin film on the substrate.

[0156] S312. A layer of photoresist is coated on the first metal film. The photoresist is subjected to step exposure and development using a halftone or grayscale mask. An unexposed area with a first thickness of photoresist is formed at the gate electrode position, and a fully exposed area without photoresist is formed at other positions.

[0157] S313. The fully exposed area is etched by an etching process to remove the first metal film in the area and form a gate electrode on the substrate.

[0158] In one exemplary embodiment, the substrate may be glass, plastic, or a flexible transparent sheet.

[0159] In one exemplary embodiment, the first metal thin film can be made of metallic materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum-doped zinc oxide (AlZnO), etc., and can be a single-layer structure or a multi-layer composite structure.

[0160] In one exemplary embodiment, step S32 may include:

[0161] S321. A gate insulating film, a semiconductor film, and a second metal film are sequentially deposited on a substrate on which a gate electrode is formed.

[0162] S322. A layer of photoresist is coated on the second metal film. A halftone or grayscale mask is used to perform step exposure and development on the photoresist. Unexposed areas with a first thickness are formed at the source and drain electrode locations. Partially exposed areas with a second thickness are formed at the conductive channel locations. Fully exposed areas with no photoresist are formed at other locations. The first thickness is greater than the second thickness.

[0163] S323. The fully exposed area is etched through the first etching process to remove the second metal film and semiconductor film in the area.

[0164] S324. The photoresist in part of the exposed area is removed by an ashing process to expose the second metal film.

[0165] S325. The second metal film in a partially exposed area is etched by a second etching process to remove the second metal film in that area, and the remaining photoresist is stripped off. A gate insulating layer, an active layer, a source electrode, and a drain electrode are formed on the substrate. A conductive channel is formed between the source electrode and the drain electrode. A semiconductor film is retained below the source electrode and the drain electrode.

[0166] In one exemplary embodiment, the gate insulating film may be made of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure, and may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0167] In one exemplary embodiment, the second metal thin film may be one or more of the following metal materials: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc., and may be a single-layer, double-layer, or multi-layer structure, and may be deposited using a radio frequency magnetron sputtering method.

[0168] In one exemplary embodiment, step S33 may include:

[0169] S331. An antioxidant conductive film is deposited on the source electrode and the drain electrode, and a connection structure is formed on the side of the source electrode and the drain electrode away from the substrate.

[0170] In one exemplary embodiment, the antioxidant conductive film can be made of materials that are resistant to oxidation and corrosion and conductive, such as chromium-cobalt alloy, nickel-chromium alloy, or tellurium-nickel-chromium alloy. It can be a single-layer, double-layer, or multi-layer structure and can be deposited using a radio frequency magnetron sputtering method.

[0171] In one exemplary embodiment, such as FIG. 3B to 3D As shown, step S34 may include:

[0172] S341. A first passivation film is deposited on a substrate having a gate insulating layer, an active layer, a source electrode, a drain electrode, and a connection structure 22.

[0173] S342. Coat a layer of photoresist on the first passivation film, expose and develop the photoresist using a single-tone mask, form a fully exposed area (without photoresist) at the connection structure location, and form an unexposed area (with photoresist retained) at other locations.

[0174] S343, Deposit an organic film on the first passivation film;

[0175] S344. Coat a layer of photoresist on an organic film, and use a halftone or grayscale mask to perform step exposure and development on the photoresist. Form a partially exposed area (photoresist with a second thickness) and a fully exposed area (no photoresist) at the second via location, and form an unexposed area (photoresist with a first thickness, the first thickness being greater than the second thickness) at other locations.

[0176] S345. The fully exposed area of ​​the organic film is etched using an etching process to remove the organic film in that area, such as... FIG. 3C As shown, an organic film layer 17 with a second through-hole to be processed is formed;

[0177] S346. The fully exposed area of ​​the first passivation film is etched by an etching process to remove the first passivation film in that area, forming a first passivation layer 16 with a first via hole. The first via hole exposes a connection structure 22, and the connection structure 22 is connected to the source electrode 14 at the location of the first via hole.

[0178] S347. The photoresist in part of the exposed area of ​​the organic film is removed by an ashing process, so that the organic film can be retracted, such as... FIG. 3D As shown, an organic film layer 17 with a second via is formed. The second via communicates with the first via to form a via structure that exposes the connection structure 22 (i.e., the via structure penetrates the organic film layer 17 and the first passivation layer 16 and exposes the connection structure 22).

[0179] In one exemplary embodiment, the first passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0180] In one exemplary embodiment, the organic membrane film may be made of organic materials such as polyimide, naphthoquinone diazide compound, etc.

[0181] In one exemplary embodiment, step S35 may include:

[0182] S351. Deposit a first transparent conductive film on the organic film layer and the connection structure;

[0183] S352. A layer of photoresist is coated on the first transparent conductive film. The photoresist is exposed and developed using a single-tone mask to form a fully exposed area (without photoresist) at the pixel electrode position and an unexposed area (with photoresist retained) at other positions.

[0184] S353. The fully exposed area is etched by an etching process to remove the first transparent conductive film in the area and form a pixel electrode. The pixel electrode 18 is recessed in the direction of the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode 18 is disposed in the via structure. The bottom of the first groove is connected to the connection structure 22. That is, the connection structure 22 is connected to the source electrode 14 on one hand and to the pixel electrode 18 through the via structure on the other hand. That is, the connection structure 22 is connected to both the source electrode 14 and the pixel electrode 18.

[0185] In one exemplary embodiment, the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0186] In one exemplary embodiment, step S36 may include:

[0187] S361. Deposit a second passivation film on the pixel electrode and the organic film layer.

[0188] In one exemplary embodiment, the second passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0189] In one exemplary embodiment, step S37 may include:

[0190] S371. Deposit a second transparent conductive film on the second passivation layer;

[0191] S372. Coat a layer of photoresist on the second transparent conductive film, expose and develop the photoresist using a single-tone mask, form an unexposed area (with photoresist retained) at the common electrode position, and form a fully exposed area (without photoresist) at other positions.

[0192] S373. The fully exposed area is etched by an etching process to remove the second transparent conductive film in the area, forming a common electrode; wherein the common electrode can be a slit electrode.

[0193] In one exemplary embodiment, the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0194] Of course, in actual implementation, the other array substrate provided in this embodiment can also be fabricated by other methods. For example, the gate electrode, gate insulating layer, active layer, source electrode, and drain electrode can be fabricated using a two-stage patterning process, where the gate electrode is first formed using a first patterning process, and then the gate insulating layer, active layer, source electrode, and drain electrode are formed using a second patterning process. Alternatively, the gate insulating layer, active layer, source electrode, and drain electrode can also be fabricated using a two-stage patterning process, where the gate insulating layer and active layer are first formed using a first patterning process, and then the source electrode and drain electrode are formed using a second patterning process.

[0195] Another array substrate provided in this disclosure has a via structure that penetrates the organic film layer and the first passivation layer, exposing the connection structure. An oxidation-resistant and conductive connection structure is provided between the source electrode and the pixel electrode. This connection structure connects to the source electrode on one side and to the pixel electrode on the other, thus connecting the pixel electrode to the source electrode via the connection structure and the via structure. Although etching the first passivation layer after the organic film masking process may cause undercutting issues, the organic film layer is subsequently ashingd to remove it. Furthermore, because the connection structure is oxidation-resistant and conductive, and covers the source electrode, it protects the metal in the source electrode from oxidation and corrosion, preventing the formation of a corrosion layer. Moreover, the connection structure's connection to both the source and pixel electrodes ensures effective connection between the pixel and source electrodes, improving yield.

[0196] The array substrate provided in this disclosure will be described in detail below, taking the direct connection between the pixel electrode and the source electrode as an example.

[0197] FIG. 4A This is a schematic diagram of the structure of the array substrate in another exemplary embodiment of the present disclosure, as shown below. FIG. 4A As shown, another array substrate provided in this embodiment may include:

[0198] Base 10;

[0199] A gate electrode 11 disposed on a substrate 10;

[0200] A gate insulating layer 12 covering the gate electrode 11;

[0201] An active layer 13, a source electrode 14, and a drain electrode 15 are disposed on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0202] A first passivation layer 16 covers the source electrode 14, the drain electrode 15 and the conductive channel, and a first via is formed on the first passivation layer 16 to expose the source electrode 14.

[0203] An organic film layer 17 covers the first passivation layer 16. A second via is formed on the organic film layer 17. The second via is connected to the first via to form a via structure that exposes the source electrode 14 (i.e., the via structure penetrates the organic film layer 17 and the first passivation layer 16 and exposes the source electrode 14). The organic film layer 17 extends into the first via on both sides near the source electrode 14.

[0204] A pixel electrode 18 is disposed on the organic film layer 17. The pixel electrode 18 is recessed in the direction towards the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode 18 is disposed in the via structure. The bottom of the first groove is connected to the source electrode 14, that is, the pixel electrode 18 is connected to the source electrode 14 through the via structure.

[0205] A second passivation layer 19 covers the pixel electrode 18 and the organic film layer 17. The second passivation layer 19 is recessed in the direction towards the substrate at the location of the first groove to form a second groove. The second groove formed by the second passivation layer 19 is disposed in the first groove.

[0206] A common electrode 20 is disposed on the second passivation layer 19.

[0207] In one exemplary embodiment, such as FIG. 4A As shown, the gate electrode 11, active layer 13, source electrode 14 and drain electrode 15 can form a thin film transistor.

[0208] In one exemplary embodiment, such as FIG. 4A As shown, the pixel electrode 18 can be a plate-shaped electrode, and the common electrode 20 can be a slit electrode. The common electrode 20 and the pixel electrode 18 together form a multi-dimensional electric field to drive the liquid crystal deflection.

[0209] In one exemplary embodiment, the connection structure may be made of materials that are resistant to oxidation and corrosion and are conductive, such as chromium-cobalt alloy, nickel-chromium alloy, or tellurium-nickel-chromium alloy.

[0210] The following is an example FIG. 4A Taking the array substrate shown as an example, the technical solution of the present disclosure is explained through the fabrication process of an array substrate provided in the embodiments of the present disclosure.

[0211] like FIG. 4A to FIG. 4D As shown, another method for fabricating an array substrate provided in this disclosure embodiment may include:

[0212] S41. A gate electrode 11 is formed on the substrate 10;

[0213] S42. A gate insulating layer 12 covering the gate electrode 11 is formed, and an active layer 13, a source electrode 14 and a drain electrode 15 are formed on the gate insulating layer 12, and a conductive channel is formed between the source electrode 14 and the drain electrode 15.

[0214] S43. A first passivation layer 16 is formed to cover the source electrode 14, the drain electrode 15 and the conductive channel. A first via is formed on the first passivation layer 16 to expose the source electrode 14.

[0215] S44. An organic film layer 17 covering the first passivation layer 16 is formed. A second via is formed on the organic film layer 17. The second via is connected to the first via to form a via structure that exposes the source electrode 14 (i.e., the via structure penetrates the organic film layer 17 and the first passivation layer 16 and exposes the source electrode 14). The organic film layer 17 extends into the first via on both sides near the source electrode 14.

[0216] S45. A pixel electrode 18 is formed on the organic film layer 17. The pixel electrode 18 is recessed in the direction towards the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode 18 is disposed in the via structure. The bottom of the first groove is connected to the source electrode 14, that is, the pixel electrode 18 is connected to the source electrode 14 through the via structure.

[0217] S46. A second passivation layer 19 is formed covering the pixel electrode 18 and the organic film layer 17. The second passivation layer 19 is recessed in the direction towards the substrate at the location of the first groove to form a second groove. The second groove formed by the second passivation layer 19 is disposed in the first groove.

[0218] S47. A common electrode 20 is formed on the second passivation layer 19.

[0219] In one exemplary embodiment, step S41 may include:

[0220] S411, Deposit a first metal thin film on the substrate.

[0221] S412. A layer of photoresist is coated on the first metal film. The photoresist is subjected to step exposure and development using a halftone or grayscale mask. An unexposed area with a first thickness of photoresist is formed at the gate electrode position, and a fully exposed area without photoresist is formed at other positions.

[0222] S413. The fully exposed area is etched by an etching process to remove the first metal film in the area and form a gate electrode on the substrate.

[0223] In one exemplary embodiment, the substrate may be glass, plastic, or a flexible transparent sheet.

[0224] In one exemplary embodiment, the first metal thin film can be made of metallic materials such as aluminum, copper, molybdenum, titanium, niobium, silver, gold, tantalum, tungsten, chromium, etc., or conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), aluminum-doped zinc oxide (AlZnO), etc., and can be a single-layer structure or a multi-layer composite structure.

[0225] In one exemplary embodiment, step S42 may include:

[0226] S421. A gate insulating film, a semiconductor film, and a second metal film are sequentially deposited on a substrate on which a gate electrode is formed.

[0227] S422. A layer of photoresist is coated on the second metal film. A halftone or grayscale mask is used to perform stepped exposure and development on the photoresist, forming unexposed areas with a first thickness at the source and drain electrode locations, partially exposed areas with a second thickness at the conductive channel locations, and fully exposed areas with no photoresist at other locations. The first thickness is greater than the second thickness.

[0228] S423. The fully exposed area is etched through the first etching process to remove the second metal film and semiconductor film in the area.

[0229] S424. The photoresist in part of the exposed area is removed by an ashing process to expose the second metal film.

[0230] S425. The second metal film in a partially exposed area is etched by a second etching process to remove the second metal film in that area, and the remaining photoresist is stripped off. A gate insulating layer, an active layer, a source electrode, and a drain electrode are formed on the substrate. A conductive channel is formed between the source electrode and the drain electrode. A semiconductor film is retained below the source electrode and the drain electrode.

[0231] In one exemplary embodiment, the gate insulating film may be made of silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure, and may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0232] In one exemplary embodiment, the second metal thin film may be one or more of the following metal materials: aluminum, copper, molybdenum, niobium, titanium, silver, gold, tantalum, tungsten, chromium, etc., and may be a single-layer, double-layer, or multi-layer structure, and may be deposited using a radio frequency magnetron sputtering method.

[0233] In one exemplary embodiment, such as FIG. 4B to FIG. 4D As shown, step S43 may include:

[0234] S431, such as FIG. 4B As shown, a first passivation film is deposited on the source electrode 14, the drain electrode, and the conductive channel;

[0235] S432. Coat a layer of photoresist on the first passivation film, expose and develop the photoresist using a single-tone mask, form an exposed area with no photoresist at the first via location, and form unexposed areas at other locations while retaining the photoresist.

[0236] S433. The fully exposed area is etched using an etching process to remove the first passivation film in that area, such as... FIG. 4C As shown, a first passivation layer 16 with a first via is formed, and the first via exposes the source electrode.

[0237] In one exemplary embodiment, the first passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0238] In one exemplary embodiment, step S44 may include:

[0239] S441. Deposit an organic thin film on the first passivation layer;

[0240] S442. Coat a layer of photoresist on the organic film, expose and develop the photoresist using a monochrome mask, form an exposed area with no photoresist at the second via position, and form unexposed areas at other positions while retaining the photoresist.

[0241] S443. The fully exposed area is etched by an etching process to remove the organic film in the area, forming an organic film layer with a second via. The second via is connected to the first via to form a via structure that exposes the source electrode (i.e., the via structure penetrates the organic film layer and the first passivation layer and exposes the source electrode). The organic film layer extends into the first via on both sides near the source electrode.

[0242] In one exemplary embodiment, the organic membrane film may be made of organic materials such as polyimide, naphthoquinone diazide compound, etc.

[0243] In one exemplary embodiment, step S45 may include:

[0244] S451. Deposit a first transparent conductive film on the organic film layer;

[0245] S452. Coat a layer of photoresist on the first transparent conductive film, expose and develop the photoresist using a single-tone mask, form an exposed area with no photoresist at the pixel electrode position, and form an unexposed area at other positions while retaining the photoresist.

[0246] S453. The exposed area is etched by an etching process to remove the first transparent conductive film in the area and form a pixel electrode. The pixel electrode is recessed in the direction of the substrate at the location of the via structure to form a first groove. The first groove formed by the pixel electrode is set in the via structure. The bottom of the first groove is connected to the source electrode, that is, the pixel electrode is connected to the source electrode through the via structure.

[0247] In one exemplary embodiment, the first transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0248] In one exemplary embodiment, step S46 may include:

[0249] S461. A second passivation film is deposited on the pixel electrode and the organic film layer to form a second passivation layer covering the pixel electrode and the organic film layer. The second passivation layer is recessed in the direction towards the substrate at the location of the first groove to form a second groove. The second groove formed by the second passivation layer is disposed in the first groove.

[0250] In one exemplary embodiment, the second passivation film may be one or more of inorganic materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (Si(ON)x), and may be a single-layer, double-layer, or multi-layer structure. It may be deposited by chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD).

[0251] In one exemplary embodiment, step S47 may include:

[0252] S471. Deposit a second transparent conductive film on the second passivation layer;

[0253] S472. Coat a layer of photoresist on the second transparent conductive film, expose and develop the photoresist using a single-tone mask, form an unexposed area at the common electrode position while retaining the photoresist, and form exposed areas at other positions without photoresist.

[0254] S383. The exposed area is etched by an etching process to remove the second transparent conductive film in the area and form a common electrode; wherein the common electrode is a slit electrode.

[0255] In one exemplary embodiment, the second transparent conductive film may be indium tin oxide (ITO) or indium zinc oxide (IZO), and may be deposited using a radio frequency magnetron sputtering method.

[0256] Of course, in actual implementation, the array substrate provided in this embodiment can also be fabricated by other methods. For example, the gate electrode, gate insulating layer, active layer, source electrode, and drain electrode can be fabricated using a two-stage patterning process, where the gate electrode is first formed using a first patterning process, and then the gate insulating layer, active layer, source electrode, and drain electrode are formed using a second patterning process. Alternatively, the gate insulating layer, active layer, source electrode, and drain electrode can also be fabricated using a two-stage patterning process, where the gate insulating layer and active layer are first formed using a first patterning process, and then the source electrode and drain electrode are formed using a second patterning process.

[0257] Another array substrate provided in this disclosure, during its fabrication, involves first etching the first passivation layer and then applying an organic film mask. This eliminates the undercutting problem, thus avoiding the need for a photoresist ashing process to revert the organic film layer. Consequently, it prevents oxidation and corrosion of the metal in the source electrode. On one hand, by penetrating the organic film layer and the first passivation layer and exposing the via structure of the source electrode, effective connection between the pixel electrode and the source electrode can be achieved, improving yield. On the other hand, compared to current array substrate fabrication methods, the fabrication process of this array substrate also saves an ashing process, reducing production costs and improving production efficiency.

[0258] Based on the foregoing embodiments, taking the example that the connection structure for connecting the source electrode and pixel electrode of the thin-film transistor is disposed in a via structure exposing the pixel electrode and the source electrode, this disclosure also provides a method for fabricating an array substrate, which may include:

[0259] S51: Forming a substrate, and forming a thin-film transistor on the substrate;

[0260] S52: A first passivation layer, an organic film layer, and a pixel electrode are formed on the thin-film transistor, and a via structure is formed that exposes the pixel electrode and the source electrode of the thin-film transistor, and a connection structure for connecting the source electrode and the pixel electrode is formed in the via structure that exposes the pixel electrode and the source electrode of the thin-film transistor.

[0261] In one exemplary embodiment, step S52 may include:

[0262] S521: Forming the first passivation layer covering the thin-film transistor;

[0263] S522: An organic film layer covering the first passivation layer is formed, and a second via is formed on the organic film layer;

[0264] S523: A pixel electrode is formed on the organic film layer, and a third via is formed on the pixel electrode, which is connected to the second via.

[0265] S524: Form a second passivation layer disposed on the pixel electrode;

[0266] S525: Through a single etching process, a fourth via exposed to the pixel electrode is formed on the second passivation layer and a first via exposed to the source electrode is formed on the first passivation layer. The fourth via is connected to the first via, and the first via is connected to the second via. The first via, the second via, the third via and the fourth via form a via structure that exposes the pixel electrode and the source electrode of the thin film transistor.

[0267] S526: A connection structure for connecting the source electrode and the pixel electrode is formed in a via structure that exposes the pixel electrode and the source electrode of the thin-film transistor.

[0268] In one exemplary embodiment, step S525 may include:

[0269] S5251: A common electrode is formed on the second passivation layer through a single patterning process, and a connection structure for connecting the source electrode and the pixel electrode is formed in the via structure that exposes the pixel electrode and the source electrode of the thin film transistor.

[0270] Based on the foregoing embodiments, taking the example of a connection structure for connecting the source electrode and pixel electrode of a thin-film transistor being disposed between the pixel electrode and the source electrode, this disclosure also provides a method for fabricating an array substrate, which may include:

[0271] S61: Forming a substrate, on which a thin-film transistor is formed;

[0272] S62: A first passivation layer, an organic film layer, and a pixel electrode are formed on the thin-film transistor, and a connection structure for connecting the source electrode and the pixel electrode is formed between the pixel electrode and the source electrode.

[0273] In one exemplary embodiment, step S62 may include:

[0274] S621: Forms a connection structure covering the source electrode and the drain electrode of the thin-film transistor;

[0275] S622: A first passivation layer covering the connection structure is formed, and an organic film layer covering the first passivation layer is formed. A second via is formed on the organic film layer. A first via is formed on the first passivation layer that communicates with the second via and exposes the connection structure. The second via and the first via form a via structure that exposes the connection structure. The connection structure is connected to the source electrode.

[0276] S623: A pixel electrode is formed on the organic film layer, and the pixel electrode is connected to the connection structure through a via structure;

[0277] S624: Forms a second passivation layer covering the pixel electrode.

[0278] In one exemplary embodiment, step S622 may include:

[0279] S6221: Deposit a first passivation film on the connection structure;

[0280] S6222: A layer of photoresist is coated on the first passivation film. The photoresist is exposed and developed using a mask. An exposed area is formed at the connection structure location, and an unexposed area is formed at other locations.

[0281] S6223: Depositing an organic film on a first passivation film coated with photoresist;

[0282] S6224: A layer of photoresist is coated on an organic film, and the photoresist is exposed and developed using a mask. Partially exposed areas and fully exposed areas are formed at the second via location, and unexposed areas are formed at other locations.

[0283] S6225: The fully exposed area of ​​the organic film is etched away using an etching process;

[0284] S6226: The fully exposed area of ​​the first passivation film is etched by an etching process to form a first passivation layer with a first via.

[0285] S6227: The photoresist in part of the exposed area of ​​the organic film is removed by an ashing process to form an organic film layer with a second via.

[0286] Based on the foregoing embodiments, taking the direct connection between the pixel electrode and the source electrode as an example, this disclosure also provides a method for fabricating an array substrate, which may include:

[0287] S71: Forming a substrate, on which thin-film transistors are formed;

[0288] S72: A first passivation layer, an organic film layer, and a pixel electrode are formed on the thin-film transistor, and a via structure is formed to expose the source electrode. The pixel electrode is connected to the source electrode through the via structure that exposes the source electrode.

[0289] In one exemplary embodiment, step S72 may include:

[0290] S721: A first passivation layer is formed covering the thin-film transistor, and a first via is formed on the first passivation layer to expose the source electrode;

[0291] S722: An organic film layer covering the first passivation layer is formed, and a second via is formed on the organic film layer. The second via is connected to the first via to form a via structure that exposes the source electrode.

[0292] S723: A pixel electrode is formed on the organic film layer, and the pixel electrode is connected to the source electrode through a via structure that exposes the source electrode.

[0293] S724: Forms a second passivation layer covering the pixel electrode and the organic film layer.

[0294] This disclosure also provides a display device, including the array substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0295] In the description of the embodiments of this disclosure, it should be understood that the terms "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0296] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure, i.e., features within the embodiments, can be combined with each other to obtain new embodiments.

[0297] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of this disclosure.

Claims

1. An array substrate, comprising: Base; Thin-film transistors mounted on a substrate; A first passivation layer, an organic film layer, and a pixel electrode are sequentially disposed on a thin-film transistor; A second passivation layer is disposed on the side of the pixel electrode away from the substrate; A common electrode and a connection structure are disposed on the side of the second passivation layer away from the substrate. The connection structure is disposed in the same layer and made of the same material as the common electrode and is formed by a single patterning process. The connection structure is used to connect the source electrode of the thin-film transistor and the pixel electrode, wherein the connection structure is disposed in a via structure that exposes the pixel electrode and the source electrode.

2. The array substrate according to claim 1, further comprising: The connection structure is disposed within a via structure exposing the pixel electrode and the source electrode, comprising: a first via exposing the source electrode on the first passivation layer; a second via communicating with the first via on the organic film layer; a third via communicating with the second via on the pixel electrode; and a fourth via communicating with the third via and exposing the pixel electrode on the second passivation layer; the fourth via, the third via, the second via, and the first via forming a via structure exposing the pixel electrode and the source electrode; the connection structure is connected to the pixel electrode and the source electrode through the via structure.

3. The array substrate according to claim 1, wherein, The material of the connecting structure includes indium tin oxide or indium zinc oxide.

4. The array substrate according to claim 1, wherein, The connecting structure is made of a material that is resistant to oxidation and corrosion and is conductive.

5. The array substrate according to claim 4, wherein, The oxidizing and corrosion-resistant and conductive material includes any one of chromium-cobalt alloy, nickel-chromium alloy, and tellurium-nickel-chromium alloy.

6. The array substrate according to claim 1, wherein, The thin-film transistor includes a gate electrode, an active layer, a source electrode, and a drain electrode. The gate electrode is disposed on the substrate and covered with a gate insulating layer. The active layer, the source electrode, and the drain electrode are disposed on the gate insulating layer, and a conductive channel is formed between the source electrode and the drain electrode.

7. An array substrate, comprising: Base; A thin-film transistor disposed on a substrate, wherein a conductive channel is formed between the source electrode and the drain electrode of the thin-film transistor; A connection structure covering the source and drain electrodes of the thin-film transistor; A first passivation layer covering the connection structure and the conductive channel; An organic film layer covering the first passivation layer; Pixel electrodes are disposed on the side of the organic film layer away from the substrate; The connection structure connects the source electrode of the thin-film transistor and the pixel electrode through a via structure disposed in the first passivation layer and the organic film layer, and the connection structure is exposed. The connection structure is disposed between the pixel electrode and the source electrode.

8. The array substrate according to claim 7, wherein, The connection structure is disposed between the pixel electrode and the source electrode, and includes: The connection structure is disposed on the side of the source electrode away from the substrate; the first passivation layer is disposed on the side of the connection structure away from the substrate, and a first via is formed to expose the connection structure; a second via is formed on the organic film layer and communicates with the first via; the second via and the first via form a via structure that exposes the connection structure; the pixel electrode is connected to the connection structure through the via structure, and the connection structure is connected to the source electrode.

9. A display device, comprising: The array substrate as described in any one of claims 1 to 8.

10. A method for fabricating an array substrate, comprising: A substrate is formed, and a thin-film transistor is formed on the substrate; A first passivation layer, an organic film layer, and a pixel electrode are formed on a thin-film transistor, and a via structure is formed to expose the pixel electrode and the source electrode of the thin-film transistor. A connection structure for connecting the source electrode and the pixel electrode is formed in the via structure that exposes the pixel electrode and the source electrode of the thin-film transistor.

11. The preparation method according to claim 10, wherein, The process of forming a first passivation layer, an organic film layer, and a pixel electrode disposed on a thin-film transistor, and forming a via structure exposing the pixel electrode and the source electrode of the thin-film transistor, and forming a connection structure for connecting the source electrode and the pixel electrode in the via structure exposing the pixel electrode and the source electrode of the thin-film transistor, includes: Forming the first passivation layer covering the thin-film transistor; An organic film layer is formed covering the first passivation layer, and a second via is formed on the organic film layer; A pixel electrode is formed on the organic film layer, and a third via is formed on the pixel electrode, which communicates with the second via. A second passivation layer is formed on the pixel electrode; Through a single etching process, a fourth via exposed on the second passivation layer and a first via exposed on the first passivation layer are formed, the fourth via being connected to the first via and the first via being connected to the second via. The first via, the second via, the third via and the fourth via form the via structure that exposes the pixel electrode and the source electrode of the thin-film transistor. A connection structure for connecting the source electrode and the pixel electrode is formed in the via structure that exposes the pixel electrode and the source electrode of the thin-film transistor.

12. The preparation method according to claim 11, wherein, The method of forming a connection structure for connecting the source electrode and the pixel electrode in the via structure that exposes the pixel electrode and the source electrode of the thin-film transistor includes: A common electrode is formed on the second passivation layer through a single patterning process, and a connection structure for connecting the source electrode and the pixel electrode is formed in the via structure that exposes the pixel electrode and the source electrode of the thin film transistor.

13. A method for fabricating an array substrate, comprising: A substrate is formed, and a thin-film transistor is formed on the substrate; A first passivation layer, an organic film layer, and a pixel electrode are formed on a thin-film transistor, and a connection structure for connecting the source electrode and the pixel electrode is formed between the pixel electrode and the source electrode.

14. The preparation method according to claim 13, wherein, The process of forming a first passivation layer, an organic film layer, and a pixel electrode on a thin-film transistor, and forming a connection structure between the pixel electrode and the source electrode for connecting the source electrode and the pixel electrode, includes: The connection structure is formed covering the source electrode and the drain electrode of the thin-film transistor; A first passivation layer is formed covering the connection structure, and an organic film layer is formed covering the first passivation layer. A second via is formed on the organic film layer. A first via is formed on the first passivation layer that communicates with the second via and exposes the connection structure. The second via and the first via form a via structure that exposes the connection structure. The connection structure is connected to the source electrode. The pixel electrode is formed on the organic film layer, and the pixel electrode is connected to the connection structure through the via structure. A second passivation layer is formed covering the pixel electrode.

15. The preparation method according to claim 14, wherein, The formation of the first passivation layer covering the connection structure, and the formation of the organic film layer covering the first passivation layer, wherein the organic film layer has a second via, and the first passivation layer has a first via communicating with the second via and exposing the connection structure, comprising: A first passivation film is deposited on the connection structure; A layer of photoresist is coated on the first passivation film, and the photoresist is exposed and developed using a mask. An exposed area is formed at the connection structure location, and an unexposed area is formed at other locations. An organic film is deposited on the first passivation film coated with photoresist; A layer of photoresist is coated on an organic film, and the photoresist is exposed and developed using a mask. Partially exposed areas and fully exposed areas are formed at the second via location, and unexposed areas are formed at other locations. The fully exposed area of ​​the organic film is etched away using an etching process; The fully exposed area of ​​the first passivation film is etched by an etching process to form a first passivation layer with the first via hole. The photoresist in part of the exposed area of ​​the organic film is removed by an ashing process to form an organic film layer with a second via.

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