Method and system for scheduling radio access networks (RAN) workloads in multi-core architecture

Abstract

The present disclosure discloses method and system for scheduling Radio Access Networks (RAN) workloads in multi-core architecture. The system allocates plurality of tasks to plurality of processing cores. The plurality of tasks are associated with RAN workloads which exhibits periodicity in predetermined sequence of execution of plurality of tasks. Further, system determines whether an execution time of plurality of allocated tasks is exceeding predefined time limit. Thereafter, system schedules RAN workloads by performing one of: generating an indication to process plurality of allocated tasks when execution time of plurality of allocated tasks is within predefined time limit or assigning wake up time for one or more processing cores when execution time of plurality of allocated tasks is exceeding predefined time limit and allocating plurality of allocated tasks to ensure that execution time of plurality of allocated tasks is within predefined time limit.

Description

METHOD AND SYSTEM FOR SCHEDULING RADIO ACCESS NETWORKS (RAN) WORKLOADS IN MULTI-CORE ARCHITECTURETECHNICAL FIELD

[0001] The present disclosure relates to field of wireless telecommunication network. Particularly, the present disclosure relates to a method and system for scheduling Radio Access Networks (RAN) workloads in multi -core architecture.BACKGROUND

[0002] As Radio Access Networks (RAN) are being deployed using cloud-based platforms for several benefits, it is essential to understand the difference between the workloads RAN software presents to these platforms built around General-Purpose Processors (GPP) as against specialized Digital Signal Processors (DSP) architectures. The hard real-time guarantees that the RAN software demands differ from the traditional applications hosted on public and onpremises cloud platforms. To meet these requirements, several techniques are employed, ranging from manipulation of cache lines to restricting the processor performance states, which try to meet the real-time requirements asymptotically. The aspect of scheduling RAN software on a multi-core GPP platform is limited and providing limits on performance guarantees has been overlooked. Therefore, there is a need to schedule the RAN software on the multi-core GPP platform while ensuring the performance guarantees.

[0003] The information disclosed in this background of the disclosure section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.SUMMARY

[0004] Disclosed herein is a method of scheduling Radio Access Networks (RAN) workloads in multi-core architecture. The method includes allocating a plurality of tasks to a plurality of processing cores. The plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks. Further, the method includes determining whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating a predefined order of execution of the plurality of taskswhich are executed with a predefined periodicity. Finally, the method includes scheduling the RAN workloads by processing the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit or assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit and allocating the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit.

[0005] Further, disclosed herein is a scheduling apparatus for scheduling Radio Access Networks (RAN) workloads in multi -core architecture. The scheduling apparatus comprises a processor and a memory communicatively coupled to the processor, where the memory stores processor executable instructions, which, on execution, may cause the scheduling apparatus to allocate a plurality of tasks to a plurality of processing cores. The plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks. Further, the scheduling apparatus determines whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating a predefined order of execution of the plurality of tasks which are executed with a predefined periodicity. Finally, the scheduling apparatus schedules the RAN workloads by performing one of processing the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit or assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit and allocating the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit.

[0006] The foregoing summary is illustrative only and is not intended to be in any way limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become apparent by reference to the drawings and the following detailed description.BRIEF DESCRIPTION OF THE ACCOMPANYING DRAWINGS

[0007] The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate exemplary embodiments and, together with the description, explain the disclosed principles. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The same numbers are used throughout the figures to reference like features and components. Some embodiments of system and / ormethods in accordance with embodiments of the present subject matter are now described, by way of example only, and regarding the accompanying figures, in which:

[0008] FIG. 1 shows an exemplary architecture for scheduling Radio Access Networks (RAN) workloads in multi-core architecture, in accordance with some embodiments of the present disclosure;

[0009] FIG. 2A illustrates a data flow diagram 200 that includes plurality of tasks, in accordance with some embodiments of the present disclosure;

[0010] FIG. 2B illustrates a block diagram 210 of the spilling over of task execution in subsequent epochs, in accordance with some embodiments of the present disclosure;

[0011] FIG. 3 illustrates a scheduling implementation of the plurality of tasks, in accordance with some embodiments of the present disclosure;

[0012] FIG. 4 illustrates a scheduling implementation of the scheduling technique, in accordance with some embodiments of the present disclosure;

[0013] FIG. 5 illustrates a RAN synchronous DFG that may include both the uplink and downlink processing paths, in accordance with some embodiments of the present disclosure;

[0014] FIG. 6 illustrates a multi-cell, multi-epoch scheduling implementation of the scheduling technique, in accordance with some embodiments of the present disclosure;

[0015] FIG. 7 shows a detailed block diagram of the scheduling apparatus 101 for scheduling Radio Access Networks (RAN) workloads in multi-core architecture, in accordance with some embodiments of the present disclosure;

[0016] FIG. 8A is a flowchart illustrating a method of scheduling Radio Access Networks (RAN) workloads in multi-core architecture, in accordance with some embodiments of the present disclosure;

[0017] FIG. 8B is a flowchart illustrating a method of allocating a plurality of tasks to a plurality of processing cores, in accordance with some embodiments of the present disclosure; and

[0018] FIG. 8C is an exemplary flowchart illustrating a method of scheduling Radio Access Networks (RAN) workloads in multi -core architecture, in accordance with some embodiments of the present disclosure.

[0019] It should be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative systems embodying the principles of the present subject matter. Similarly, it will be appreciated that any flow charts, flow diagrams, state transition diagrams, pseudo code, and the like represent various processes which may be substantially represented in computer readable medium and executed by a computer or processor, whether such computer or processor is explicitly shown.DETAILED DESCRIPTION

[0020] In the present document, the word “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment or implementation of the present subject matter described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments.

[0021] While the disclosure is susceptible to various modifications and alternative forms, specific embodiment thereof has been shown by way of example in the drawings and will be described in detail below. It should be understood, however that it is not intended to limit the disclosure to the specific forms disclosed, but on the contrary, the disclosure is to cover all modifications, equivalents, and alternative falling within the scope of the disclosure.

[0022] The terms “comprises”, “comprising”, “includes”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a setup, device, or method that comprises a list of components or steps does not include only those components or steps but may include other components or steps not expressly listed or inherent to such setup or device or method. In other words, one or more elements in a system or apparatus proceeded by “comprises ... a” does not, without more constraints, preclude the existence of other elements or additional elements in the system or method.

[0023] In the following detailed description of the embodiments of the disclosure, reference is made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments in which the disclosure may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice thedisclosure, and it is to be understood that other embodiments may be utilized and that changes may be made without departing from the scope of the present disclosure. The following description is, therefore, not to be taken in a limiting sense.

[0024] Definitions of the key terminologies used in the present disclosure are defined below for proper understanding of the description comprising various embodiments of the present disclosure:- Activation time: The activation time is associated with a task. This is immutable during the course of execution. The activation time may depend on a waveform definition. Each task may have an activation time before which the tasks cannot be executed.Start time: Each task has a start time at which the task starts executing. The start time depends on the scheduling and actual execution on the processing element. This can change in multiple instances of the Data Flow Graph (DFG) execution or multiple time instances of the same DFG.- Wake up time: The wake up time indicates a time instance at which the processing core is available for next execution. In other words, time duration before which the processing core does not take up tasks from new epoch for execution.

[0025] FIG. 1 shows an exemplary architecture for scheduling Radio Access Networks (RAN) workloads in multi-core architecture, in accordance with some embodiments of the present disclosure.

[0026] Exemplary architecture illustrates a scheduling apparatus 101 and a multi-core processor 103. The multi-core processor 103 includes a plurality of cores 105. The scheduling apparatus 101 and the multi-core processor 103 may communicate through a communication network (not shown in figure). As an example, the scheduling apparatus 101 may be a computing system. The multi-core processor 103 may be a General-Purpose Processor (GPP) which may be configured to execute the RAN workload in the plurality of cores 105. In an embodiment, the scheduling apparatus 101 may be a functional element within a RAN which may be configured to perform the aspects of the present disclosure. In an embodiment, the scheduling apparatus 101 may be configured to schedule the RAN workload in the plurality of cores 105 in the multi-core processor 103. An exemplary illustration of the RAN workload in a form of synchronous data flow graph is shown in FIG. 2A.

[0027] In an embodiment, the scheduling apparatus 101 may be configured to allocate a plurality of tasks to a plurality of processing cores. The plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks. In other words, the RAN workloads repeat in consistent time intervals. For performing allocation of the plurality of tasks to the plurality of processing cores, the scheduling apparatus 101 may determine one or more independent tasks among the plurality of tasks. The independent tasks here refer to tasks whose execution is not dependent on other tasks. As an example, the tasks which are executed first may be referred to as independent tasks as they are not dependent on succeeding tasks. The one or more independent tasks are added in a traversal list and visit flag corresponding to each of the one or more independent tasks is set to False. The visit flag False indicates that the independent task is not allocated to a processing core in the plurality of processing cores. Upon determining the one or more independent tasks, the scheduling apparatus 101 may sequentially select an independent task (T) from the one or more determined independent tasks in the traversal list based on at least one of, a priority of the independent task and an estimated runtime of the independent task. Upon selecting the independent task (T), the scheduling apparatus 101 may for the selected independent task, perform allocating one or more instances of the selected independent task (T) to the one or more processing cores. The selected tasks may have one or more instances which indicate the number of times the selected independent task should be executed.

[0028] In an embodiment, for allocating the one or more instances, the scheduling apparatus 101 may be configured to determine whether a processing core among the plurality of processing cores that has executed parent task of the selected independent task is available to execute the selected independent task. Upon determining, the scheduling apparatus 101 may be configured to perform an allocation of the selected independent task to the determined processing core which executed the parent task when the processing core is available for allocation based on timeline information. This is done to reduce unnecessary data transfer between cores. In some embodiment, when the processing core which executed the parent task is not available for allocation based on timeline information, the scheduling apparatus 101 may allocate the selected independent task to a sibling processing core of the determined processing core . The sibling processing core may refer to a virtual cores which may share same underlying physical core. The allocation to the sibling processing core is performed to avoid cache latencies as the virtual cores are related to the same physical core. As an example, when aprocessor includes one physical core and the physical core further includes two virtual cores, the virtual cores sharing same cache memory are referred to as sibling processing cores.

[0029] In an embodiment, upon allocating the one or more instances of the of the selected independent task, the scheduling apparatus 101 may determine one or more subsequent tasks dependent on the selected independent task (T). The one or more subsequent tasks are added in the traversal list when at least one of, the visit flag of the one or more subsequent tasks is False and activation time of the one or more subsequent tasks is less than the estimated runtime of the independent task. Each task has an activation time before which the tasks cannot be executed. For instance, Demodulation Reference Signal (DMRS) symbols from the current slot cannot be executed unless the symbol time for DMRS symbols is over and sufficient time is provided for data related to DMRS symbols to be transported back to Distributed Unit (DU) for processing. The scheduling apparatus 101 wake up the task to do processing only after the time provided for data related to DMRS symbols to be transported back to DU is completed. Thereafter, the scheduling apparatus 101 may update the visit flag of the independent task (T) to True upon determination, thereby allocating the plurality of tasks to the plurality of processing cores. Updating the visit flag to True indicates allocation of the independent task (T).

[0030] In an embodiment, upon allocating a plurality of tasks, the scheduling apparatus 101 may be configured to determine whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating a predefined order of execution of the plurality of tasks which are executed with a predefined periodicity. The predefined time limit may vary for depending on the plurality of tasks and plurality of the processing cores.

[0031] In an embodiment, upon determining whether the execution time of the plurality of allocated tasks is exceeding a predefined time limit, the scheduling apparatus 101 may schedule the RAN workloads by processing the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit. In an embodiment, the scheduling apparatus 101 may schedule the RAN workloads by assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit. The wake-up time indicates a time instance at which the processing core is available for next execution. In an embodiment, the scheduling apparatus 101 may determine the wake-up time for one or more processing cores based on a duration of time exceeding the predefined time limit. Further, the scheduling apparatus 101 may allocatethe plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit. Further, the scheduling apparatus 101 may generate an indication to process the RAN workloads when the execution time is within the predefined time limit. In some embodiment, the scheduling apparatus 101 may generate an indication not to process the RAN workloads when the execution time is exceeding the predefined time limit.

[0032] FIG. 2A illustrates a data flow diagram 200 that includes plurality of tasks. In an embodiment, the multi-core processor 103 may execute operations on a set of tasks that need to be executed in a time-bound manner (i.e., there is an upper bound on the total execution time of the set), and this repeats at a fixed periodic instance of time (called epochs). Each task may depend on several preceding tasks, and their relation may be represented as the DFG, as shown in FIG. 2A. The arrowhead indicates the dependency on a task. As an example, task E is dependent on task C, i.e., task E may only start when task C is complete. In an embodiment, C is the parent task for E, and F and G are the child tasks from task D. At a given epoch, one task starts and gets executed on a specific processing core or tile (the term being used interchangeably) until its completion.

[0033] FIG. 2B illustrates a block diagram 210 of the spilling over of task execution in subsequent epochs. In an embodiment, in a repetitive execution scenario, the spilling over of this execution is allowed in the next epoch. This implies that in the current epoch, there will be a spillover from the previous epoch, such as wrapping around the task within the execution time constraints, as shown in FIG. 2B.

[0034] In an embodiment, consider the DFG representing a discrete-time system with the following characteristics:• The DFG consists of nodes representing tasks or computations.• Each node has an associated execution time.• The edges between nodes represent data dependencies and have associated data transfer times or bounds.• The system operates in epochs, where each epoch represents a fixed time interval.• The instances of the DFG repeat at each epoch independently.• Now, consider an example DFG with 6 nodes (A, B, C, D, E, F) and the following execution times and data transfer bounds:• Node A: execution time = 2 units• Node B: execution time = 3 units• Node C: execution time = 2 units• Node D: execution time = 4 units• Node E: execution time = 2 units• Node F : execution time = 3 units• Edge A B: data transfer bound = 1 unit• Edge A C: data transfer bound = 1 unit• Edge B D: data transfer bound = 2 units• Edge C - > E: data transfer bound = 1 unit• Edge D F: data transfer bound = 1 unit• Edge E F: data transfer bound = 1 unit

[0035] In an embodiment, the scheduling apparatus 101 may initiate the allocation by selecting a node with the lowest execution time among the nodes without any immediate predecessors (i.e., nodes that may be executed independently). In this case, both nodes A and C have an execution time of 2 units and no immediate predecessors, so either one may be selected. Consider a scenario in which node A is chosen. In an embodiment, the scheduling apparatus 101 may then explore the immediate followers of node A, which are nodes B and C. The scheduling apparatus 101 may select the node with the lowest execution time among these immediate followers, which is node C (execution 10 time = 2 units).

[0036] In an embodiment, the scheduling apparatus 101 may continue the process by exploring the immediate followers of node C, which is node E. Since node E has no other immediate predecessors, it is selected for execution. After executing node E, the technique or mechanism backtracks to node C and explores its other immediate follower, node B. Node B is selected for execution since it has no other immediate predecessors.

[0037] In an embodiment, the scheduling apparatus 101 may may explore the immediate follower of node B, which is node D. Node D is selected for execution. Finally, the scheduling apparatus 101 may explore the immediate follower of node D, which is node F. Node F is selected for execution. The resulting execution order of the nodes is A C E B D F. For instance, consider a scenario od spillage in the context of epochs. Suppose each epoch has a duration of 10 units. Epoch 1 : Node A (2 units) and Node C (2 units) are executed; Epoch 2: Node E (2 units), Node B (3 units), and part of Node D (3 units out of 4) are executed. Epoch3: The remaining part of Node D (1 unit) and Node F (3 units) are executed. In an embodiment, the present disclosure allows for the spillage of execution across epochs, ensuring that nodes execution continues seamlessly from one epoch to the next. This spillage effect is possible because the instances of the DFG repeat independently at each epoch, allowing for the wraparound of task execution.

[0038] FIG. 3 illustrates a scheduling implementation of the plurality of tasks. In an embodiment, the scheduling now considers the start time for tasks, but it results in Task 2 instances spilling over the predefined time limit, resulting in constraint violation, as shown in FIG. 3. This is where the periodicity of the tasks plays its role. As shown in the FIG. 3, on processor core P2, the initial time slots are not utilized. So, if the scheduling accounts for this unused time and is used to accommodate the portion of spillover, it may still maintain the schedule. The result looks like wrapping over the Task 2 instance around the epoch boundary. Referring to FIG. 4 the Task 2 which was spilling over the predefined time limit is pipelines to processor core P2 which is available to execute the instances spilling over the predefined time limit. As the Task 2 is spilling over, the wake-up time of the processor core P2 is updated. In an embodiment, with the generated schedule, back-to-back SDF may be executed as tasks are properly pipelined on the multi-core processor 103 for the given epoch budget.

[0039] FIG. 5 illustrates a RAN synchronous DFG that may include both the uplink and downlink processing paths, with each node representing an action or event and the edges showing the execution dependencies. Although the graph is built based on a commercially available reference implementation, the representation would be structurally like the one shown here.

[0040] FIG. 6 illustrates a multi-cell, multi-epoch scheduling implementation of the scheduling technique as disclosed in present disclosure. FIG. 6 is described in conjunction with FIGs 1-5. In an embodiment, FIG. 6 shows an illustration of a multi-cell, multi-epoch scheduling implementation of the technique disclosed in present disclosure. FIG. 6 shows the scheduling implementation used by two radio nodes or cells. The epoch budget is 11 and for every 11 -unit time, two sets of the graphs need to be scheduled for execution. The total execution can be over two epochs.

[0041] FIG. 7 shows a detailed block diagram of the scheduling apparatus 101 for scheduling Radio Access Networks (RAN) workloads in multi -core architecture, in accordance with some embodiments of the present disclosure.

[0042] In some implementations, the scheduling apparatus 101 may include an I / O interface 701, a multi-core processor 103 and a memory 703. In an embodiment, the memory 703 may be communicatively coupled to the multi-core processor 103. The multi-core processor 103 may be configured to perform one or more functions of the scheduling apparatus 101 for scheduling Radio Access Networks (RAN) workloads in multi -core architecture, using the data 705 and the one or more modules 707 of the scheduling apparatus 101. In an embodiment, the memory 703 may store the data 705.

[0043] In an embodiment, the data 705 stored in the memory 703 may include, without limitation, task data 709 and other data 711. In some implementations, the data 705 may be stored within the memory 703 in the form of various data structures. Additionally, the data 705 may be organized using data models, such as relational or hierarchical data models. The other data 711 may include various temporary data and files generated by the one or more modules 707.

[0044] In an embodiment, the task data 709 may include data related to plurality of tasks to be scheduled to a plurality of processing cores. The task data 709 may include task Identification, start time, execution time, parent task information, and number of instances of execution.

[0045] In an embodiment, the data 705 may be processed by one or more modules 707 of the scheduling apparatus 101. In some implementations, the one or more modules 707 may be communicatively coupled to the multi -core processor 103 for performing one or more functions of the scheduling apparatus 101. In an implementation, the one or more modules 707 may include, without limiting to, an allocation module 713, a determination module 715, a scheduling module 717 and other modules 719.

[0046] As used herein, the term module may refer to an Application Specific Integrated Circuit (ASIC), an electronic circuit, a hardware processor (shared, dedicated, or group) and memory that execute one or more software or firmware programs, a combinational logic circuit, and / or other suitable components that provide the described functionality. In an implementation, each of the one or more modules 707 may be configured as stand-alone hardware computing units. In an embodiment, the other modules 719 may be used to perform various miscellaneousfunctionalities on the scheduling apparatus 101. It will be appreciated that such one or more modules 707 may be represented as a single module or a combination of different modules.

[0047] In an embodiment, the allocation module 713 may be configured to allocate the plurality of tasks to the plurality of processing cores. The plurality of tasks may be associated with RAN workloads which exhibit periodicity in sequence of execution of the plurality of tasks. In an embodiment, the allocation module 713 may be configured to determine the one or more independent tasks among the plurality of tasks. The one or more independent tasks may be added in the traversal list and the visit flag corresponding to each of the one or more independent tasks which may be set to “False.” Further, the allocation module 713 may be configured to sequentially select the independent task (T) from the one or more determined independent tasks in the traversal list. The sequential selection may be performed by the allocation module 713 based on at least one of, the priority of the independent task and the estimated runtime of the independent task.

[0048] Thereafter, the allocation module 713 may be configured to perform further steps for the selected independent task to update the visit flag. Particularly, the allocation module 713 may be configured to perform allocating of the one or more instances of the selected independent task (T) to the one or more processing cores. Further, the allocation module 713 may be configured to determine the one or more subsequent tasks dependent on the selected independent task (T). The one or more subsequent tasks may be added in the traversal list when at least one of, the visit flag of the one or more subsequent tasks may correspond to “False” and activation time of the one or more subsequent tasks may be less than the estimated runtime of the independent task. Furthermore, the allocation module 713 may be configured to update the visit flag of the independent task (T) to “True” thereby allocating the plurality of tasks to the plurality of processing cores. In an embodiment, updating the visit flag to “True” indicates allocation of the independent task (T).

[0049] In an embodiment, the allocation module 713 may be configured to determine whether a processing core among the plurality of processing cores that has executed parent task of the selected independent task is available to execute the selected independent task. Thereafter, the allocation module 713 may be configured to allocate the selected independent task by performing one of the following two approaches. In the first approach, the allocation module 713 may allocate the selected independent task to the determined processing core which may have executed the parent task when the processing core is available for allocation based on thetimeline information. In the second approach, the allocation module 713 may allocate the selected independent task to the sibling processing core of the determined processing core when the processing core which may have executed the parent task is not available for allocation based on the timeline information.

[0050] Thereafter, the allocation module 713 may be configured to send data related to the plurality of tasks to the determination module 715.

[0051] In an embodiment, the determination module 715 may be configured to receive the data related to the plurality of tasks from the allocation module 713. The determination module 715 may be further configured to determine whether the execution time of the plurality of allocated tasks is exceeding the predefined time limit without violating a predefined order of execution of the plurality of tasks which are executed with a predefined periodicity. In an embodiment, the results of determination with respect to the execution time exceeding the predefined time limit, may be sent by the determination module 715 to the scheduling module 717 for performing further processing.

[0052] In an embodiment, the scheduling module 717 may be configured to receive the results of determination from the determination module 715. Thereafter, the scheduling module 717 may be configured to schedule the RAN workloads by performing one of the following two approaches. In the first approach, the scheduling module 717 may be configured to process the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit. In the second approach, the scheduling module 717 may be configured to update the wake-up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit. Thereafter, upon assigning the wake up time, the scheduling module 717 may be configured to allocate the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit. In an embodiment, the wake-up time may be indicative of the time instance at which the processing core is available for the next execution. In an embodiment, the wake-up time for one or more processing cores may be determined by the determination module 715 based on a duration of time exceeding the predefined time limit.

[0053] In an embodiment, the scheduling module 717 may be further configured to generate indications based on the execution time and the predefined time limit. Particularly, in one embodiment, the scheduling module 717 may be configured to process the RAN workloadswhen the execution time is within the predefined time limit. In another embodiment, the scheduling module 717 may be configured to not process the RAN workloads when the execution time is exceeding the predefined time limit.

[0054] FIG. 8A is a flowchart illustrating a method of scheduling Radio Access Networks (RAN) workloads in multi-core architecture, in accordance with some embodiments of the present disclosure.

[0055] As illustrated in FIG. 8A, the method 800 may include one or more blocks illustrating a method of scheduling Radio Access Networks (RAN) workloads in multi-core architecture using the scheduling apparatus 101 illustrated in FIG. 8A. The method 800 may be described in the general context of computer executable instructions. Generally, computer executable instructions can include routines, programs, objects, components, data structures, procedures, modules, and functions, which perform specific functions or implement specific abstract data types.

[0056] The order in which the method 800 is described is not intended to be construed as a limitation, and any number of the described method blocks can be combined in any order to implement the method. Additionally, individual blocks may be deleted from the methods without departing from the scope of the subject matter described herein. Furthermore, the method can be implemented in any suitable hardware, software, firmware, or combination thereof.

[0057] At block 801, the method 800 includes allocating, by a multi-core processor 103 of the scheduling apparatus 101, a plurality of tasks to a plurality of processing cores. The plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks. In an embodiment, for allocating the plurality of tasks to the plurality of processing cores, the multi-core processor 103 may determine one or more independent tasks among the plurality of tasks. The one or more independent tasks are added in a traversal list and visit flag corresponding to each of the one or more independent tasks is set to False. Further, the multi -core processor 103 may sequentially select an independent task (T) from the one or more determined independent tasks in the traversal list based on at least one of, a priority of the independent task and an estimated runtime of the independent task. Thereafter, for the selected independent task, the multi-core processor 103 may allocate one or more instances of the selected independent task (T) to the one or more processing cores. Uponallocating, the multi-core processor 103 may determine one or more subsequent tasks dependent on the selected independent task (T). The one or more subsequent tasks are added in the traversal list when at least one of, the visit flag of the one or more subsequent tasks is False and activation time of the one or more subsequent tasks is less than the estimated runtime of the independent task. After determining, the multi-core processor 103 may update the visit flag of the independent task (T) to True upon determination. Updating the visit flag to True indicates allocation of the independent task (T). In an embodiment, for allocating the one or more instances, the multi-core processor 103 may determine whether a processing core among the plurality of processing cores that has executed parent task of the selected independent task is available to execute the selected independent task. Further, the multi-core processor 103 may perform one of: allocating the selected independent task the determined processing core which executed the parent task when the processing core is available for allocation based on timeline information or allocating the child task to a sibling processing core of the determined processing core when the processing core which executed the parent task is not available for allocation based on timeline information.

[0058] At block 803, the method 800 includes determining, by the multi-core processor 103, whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating a predefined order of execution of the plurality of tasks which are executed with a predefined periodicity. The wake-up time indicates a time instance at which the processing core is available for next execution. In an embodiment, the wake-up time for one or more processing cores is determined based on a duration of time exceeding the predefined time limit.

[0059] At block 805, the method 800 includes scheduling, by the multi-core processor 103, the RAN workloads by performing one of: process the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit or assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit and allocating the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit. Further, the multi-core processor 103 may process the RAN workloads when the execution time is within the predefined time limit. In an embodiment, the RAN workloads may not be processed when the execution time is exceeding the predefined time limit.

[0060] FIG. 8B is a flowchart illustrating a method of allocating a plurality of tasks to a plurality of processing cores, in accordance with some embodiments of the present disclosure.

[0061] At step 811, the scheduling apparatus 101 for a selected task instance in a plurality of tasks determines whether task instance T can start executing at time S (considering wake up time) and estimated time is E. Further, at step 813, when a tile needs to assign to T, check the tile of parent task R of the task instance T is available for assigning and execution. Tile here refers to a processing core in a multi -core processor 103. At step 815, if the tile (P) of the parent task R is free as per information from timeline (i.e., the tile (P) is free from time S to S+E, and avoiding tile wake up time), the scheduling apparatus 101 may assign the current task T to the same tile (P). This is to reduce unnecessary data transfer between cores, if the tile (P) is not free, check for sibling core of P. At step 817, if tile (P) or sibling core of P are not free, check all other tiles (starting sequentially from P+1), where the task can run at zero or smallest delay. At step 819, determine whether any tile is available. If yes, at step 821, assign the tile to the task instance. If no tile is available, at step 823, report not possible.

[0062] FIG. 8C is an exemplary flowchart illustrating a method of scheduling Radio Access Networks (RAN) workloads in multi -core architecture, in accordance with some embodiments of the present disclosure.

[0063] At step 831, the scheduling apparatus 101 allocates a plurality of tasks to a plurality of processing cores. Further, at step 833 the scheduling apparatus 101 determines whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit. If no allocation is exceeding the predefined time limit, the process moves to step 835 i.e., the execution time of the plurality of allocated tasks is within the predefined time limit, at step 835 the scheduling apparatus 101 may process the plurality of allocated tasks. When the execution time of the plurality of allocated tasks is exceeding the predefined time limit, the process moves to step 837 and at step 837, the scheduling apparatus 101 updates wake up time for the one or more processing cores. At step 839, the scheduling apparatus 101 allocates a plurality of tasks to a plurality of processing cores. At step 841, process end and execution of the tasks takes place in accordance with the allocation.

[0064] In light of the technical advancements provided by the disclosed method, the claimed steps, as discussed above, are not routine, conventional, or not well-known aspects in the art, as the claimed steps provide the aforesaid solutions to the technical problems existing in theconventional technologies. Further, the claimed steps clearly bring an improvement in the functioning of the system itself, as the claimed steps provide a technical solution to a technical problem.

[0065] The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "one embodiment" mean "one or more (but not all) embodiments of the invention(s)" unless expressly specified otherwise.

[0066] The terms "including", "comprising", “having” and variations thereof mean "including but not limited to", unless expressly specified otherwise.

[0067] The enumerated listing of items does not imply that any or all the items are mutually exclusive, unless expressly specified otherwise. The terms "a", "an" and "the" mean "one or more", unless expressly specified otherwise.

[0068] A description of an embodiment with several components in communication with each other does not imply that all such components are required. On the contrary, a variety of optional components are described to illustrate the wide variety of possible embodiments of the invention.

[0069] When a single device or article is described herein, it will be clear that more than one device / article (whether they cooperate) may be used in place of a single device / article. Similarly, where more than one device / article is described herein (whether they cooperate), it will be clear that a single device / article may be used in place of the more than one device / article or a different number of devices / articles may be used instead of the shown number of devices or programs. The functionality and / or features of a device may be alternatively embodied by one or more other devices which are not explicitly described as having such functionality / features. Thus, other embodiments of invention need not include the device itself.

[0070] Finally, the language used in the specification has been principally selected for readability and instructional purposes, and it may not have been selected to delineate or circumscribe the inventive subject matter. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by any claims that issue on an application based here on. Accordingly, the embodiments of the present invention are intended to beillustrative, but not limiting, of the scope of the invention, which is set forth in the following claims.

[0071] While various aspects and embodiments have been disclosed herein, other aspects and embodiments will be apparent to those skilled in the art. The various aspects and embodiments disclosed herein are for purposes of illustration and are not intended to be limiting, with the true scope and spirit being indicated by the following claims.

Claims

WE CLAIM:

1. A method of scheduling Radio Access Networks (RAN) workloads in multi-core architecture, the method comprising: allocating a plurality of tasks to a plurality of processing cores, wherein the plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks; determining whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating a predefined order of execution of the plurality of tasks which are executed with a predefined periodicity; and scheduling the RAN workloads by performing one of: processing the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit; or assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit and allocating the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit.

2. The method as claimed in claim 1, wherein allocating the plurality of tasks to the plurality of processing cores comprises: determining one or more independent tasks among the plurality of tasks, wherein the one or more independent tasks are added in a traversal list and visit flag corresponding to each of the one or more independent tasks is set to False; sequentially selecting an independent task (T) from the one or more determined independent tasks in the traversal list based on at least one of, a priority of the independent task and an estimated runtime of the independent task; and for the selected independent task, performing: allocating one or more instances of the selected independent task (T) to the one or more processing cores; determining one or more subsequent tasks dependent on the selected independent task (T), wherein the one or more subsequent tasks are added in the traversal list when at least one of, the visit flag of the one or more subsequenttasks is False and activation time of the one or more subsequent tasks is less than the estimated runtime of the independent task; and updating the visit flag of the independent task (T) to True upon determination thereby allocating the plurality of tasks to the plurality of processing cores, wherein updating the visit flag to True indicates allocation of the independent task (T).

3. The method as claimed in claim 2, wherein allocating the one or more instances comprises: determining whether a processing core among the plurality of processing cores that has executed parent task of the selected independent task is available to execute the selected independent task; and performing one of: allocating the selected independent task to the determined processing core which executed the parent task when the processing core is available for allocation based on timeline information; or allocating the selected independent task to a sibling processing core of the determined processing core when the processing core which executed the parent task is not available for allocation based on timeline information.

4. The method as claimed in claim 1, wherein allocating the plurality of allocated tasks further comprises: processing the RAN workloads when the execution time is within the predefined time limit.

5. The method as claimed in claim 1, wherein the wake up time indicates a time instance at which the processing core is available for next execution.

6. The method as claimed in claim 1 , wherein the wake up time for one or more processing cores is determined based on a duration of time exceeding the predefined time limit.

5. A scheduling apparatus for scheduling Radio Access Networks (RAN) workloads in multi-core architecture, the method comprising:a processor; and a memory communicatively coupled to the processor, wherein the memory stores processor instructions, which, on execution, causes the processor to: allocate a plurality of tasks to a plurality of processing cores, wherein the plurality of tasks are associated with RAN workloads which exhibits periodicity in sequence of execution of the plurality of tasks; determine whether an execution time of the plurality of allocated tasks is exceeding a predefined time limit without violating the predefined order of execution of the plurality of tasks which are executed with a predefined periodicity; and schedule the RAN workloads by performing one of: processing the plurality of allocated tasks when the execution time of the plurality of allocated tasks is within the predefined time limit; or assigning wake up time for the one or more processing cores when the execution time of the plurality of allocated tasks is exceeding the predefined time limit and allocating the plurality of allocated tasks to ensure that the execution time of the plurality of allocated tasks is within the predefined time limit.

6. The scheduling apparatus as claimed in claim 5, wherein to allocating the plurality of tasks to the plurality of processing cores the processor is configured to: determine one or more independent tasks among the plurality of tasks, wherein the one or more independent tasks are added in a traversal list and visit flag corresponding to each of the one or more independent tasks is set to False; sequentially select an independent task (T) from the one or more determined independent tasks in the traversal list based on at least one of, a priority of the independent task and an estimated runtime of the independent task; and for the selected independent task, perform: allocating one or more instances of the selected independent task (T) to the one or more processing cores; determining one or more subsequent tasks dependent on the selected independent task (T), wherein the one or more subsequent tasks are added in the traversal list when at least one of, the visit flag of the one or more subsequenttasks is False and activation time of the one or more subsequent tasks is less than the estimated runtime of the independent task; and updating the visit flag of the independent task (T) to True upon determination thereby allocating the plurality of tasks to the plurality of processing cores, wherein updating the visit flag to True indicates allocation of the independent task (T).

7. The scheduling apparatus as claimed in claim 6, wherein to allocate the one or more instances, the processor is configured to: determine whether a processing core among the plurality of processing cores that has executed parent task of the selected independent task is available to execute the selected independent task; and perform one of: allocating the selected independent task to the determined processing core which executed the parent task when the processing core is available for allocation based on timeline information; or allocating the selected independent task to a sibling processing core of the determined processing core when the processing core which executed the parent task is not available for allocation based on timeline information.

8. The scheduling apparatus as claimed in claim 5, wherein to allocate the plurality of allocated tasks the processor is further configured to: process the RAN workloads when the execution time is within the predefined time limit.

7. The scheduling apparatus as claimed in claim 5, wherein the wake up time indicates a time instance at which the processing core is available for next execution.

8. The scheduling apparatus as claimed in claim 5, wherein the processor determines the wake up time for one or more processing cores based on a duration of time exceeding the predefined time limit.

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