Display panel and manufacturing method therefor

Abstract

A display panel according to one embodiment of the present invention comprises: a display element layer including a light-emitting element for outputting source light; and an optical structure layer which is disposed on the light-emitting element and which transmits the source light therethrough or converts the source light into light of a different wavelength. The optical structure layer includes a light control layer disposed on the light-emitting element. The light control layer includes: a bank including a first bank opening portion and a second bank opening portion that are adjacent to each other in a first direction; a first light control pattern disposed in the first bank opening portion; a second light control pattern disposed in the second bank opening portion; and a metal pattern disposed between the first light control pattern and the second light control pattern. The bank is optically transparent and a part of the bank overlaps the first light control pattern in a planar view. A part of the metal pattern overlaps at least a part of the first light control pattern and the second light control pattern in a planar view.

Description

Display panel and manufacturing method thereof

[0001] The present invention relates to a display panel and a method for manufacturing the same, and more particularly, to a display panel having improved display efficiency while increasing resolution, and a method for manufacturing the same.

[0002] The display panel includes a transmissive display panel that selectively transmits source light generated from a light source and an emissive display panel that generates source light within the display panel itself. The display panel may include different types of light control patterns depending on the pixels to generate a color image. The light control patterns may transmit only a portion of the wavelength range of the source light or change the color of the source light. Some light control patterns may change the characteristics of the light without changing the color of the source light.

[0003] The purpose of the present invention is to provide a display panel capable of high resolution implementation and improved display efficiency.

[0004] The purpose of the present invention is to provide a method for manufacturing a display panel with improved display efficiency.

[0005] According to one embodiment of the present invention, a display panel includes a display element layer including a light-emitting element that outputs source light, and an optical structure layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength. The optical structure layer includes a light control layer disposed on the light-emitting element. The light control layer includes a bank including a first bank opening and a second bank opening that are adjacent in a first direction, a first light control pattern disposed within the first bank opening, a second light control pattern disposed within the second bank opening, and a metal pattern disposed between the first light control pattern and the second light control pattern. The bank is optically transparent, and a portion of the bank overlaps the first light control pattern in a plane. A portion of the metal pattern overlaps at least a portion of the first light control pattern and the second light control pattern in a plane.

[0006] The above bank may include a material having a transmittance of 85% or more in the visible light range.

[0007] The metal pattern is disposed between the first light control pattern and the bank, and can contact at least a portion of a side surface of the first light control pattern.

[0008] The metal pattern is disposed between the second light control pattern and the bank, and can contact at least a portion of a side surface of the second light control pattern.

[0009] The above metal pattern may have a ring shape that follows the edge of at least one of the first light control pattern and the second light control pattern on a plane.

[0010] The bank may further include a third bank opening adjacent to the second bank opening along the first direction. The light control layer may further include a third light control pattern disposed within the third bank opening.

[0011] The metal pattern may include a first metal pattern disposed between the first light control pattern and the second light control pattern in the first direction, and a second metal pattern disposed between the second light control pattern and the third light control pattern in the first direction.

[0012] Each of the first light control pattern and the third light control pattern may include a photosensitive resin.

[0013] Each of the first light control pattern and the third light control pattern may include a scatterer and may not include a light emitter.

[0014] The second light control pattern may include a base resin and quantum dots dispersed in the base resin.

[0015] The thickness of the second light control pattern may be greater than or equal to the thickness of the first light control pattern.

[0016] The bank may include a first portion disposed on one surface of the first light control pattern, and a second portion that does not overlap with the first light control pattern in a plane. The first portion and the second portion may have an integral shape.

[0017] The width of the first portion in the first direction may be greater than the width of the second portion in the first direction.

[0018] In the first direction, the first portion may not overlap with the first light control pattern and may overlap with the second light control pattern.

[0019] A first bank region defined by the first bank opening can emit light of a first wavelength, and a second bank region defined by the second bank opening can emit light of a second wavelength. The first wavelength can be shorter than the second wavelength.

[0020] The above display element layer may further include an encapsulating layer covering the light emitting element. The light control layer may be disposed directly on the encapsulating layer.

[0021] The optical structure layer may further include a color filter layer disposed on the light control layer and including a first color filter and a second color filter. The first color filter may overlap at least the first light control pattern on a plane, and the second color filter may overlap at least the second light control pattern on a plane.

[0022] The above light control layer may further include a first barrier layer covering one side of each of the first light control pattern and the second light control pattern.

[0023] According to one embodiment of the present invention, a display panel includes a display element layer including a light-emitting element that outputs source light, and an optical structure layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength. The optical structure layer includes a light control layer disposed on the light-emitting element. The light control layer includes a bank including a first bank opening, a second bank opening, and a third bank opening arranged along a first direction, a first light control pattern disposed within the first bank opening, a second light control pattern disposed within the second bank opening, a third light control pattern disposed within the third bank opening, and a metal pattern disposed between at least the first light control pattern and the second light control pattern. The bank is optically transparent, the first light control pattern and the third light control pattern each include a photosensitive resin, and the second light control pattern includes a base resin and a quantum dot.

[0024] A method for manufacturing a display panel according to one embodiment of the present invention includes the steps of preparing a display element layer including a light-emitting element that outputs source light, and the steps of forming an optical structure layer on the light-emitting element. The step of forming the optical structure layer includes the steps of patterning a first preliminary layer including a photosensitive material to form a first light control pattern, depositing a reflective metal layer and then patterning it to form a metal pattern, forming an optically transparent preliminary bank layer and then patterning it to form a bank including a first bank opening exposing a portion of the first light control pattern and a second bank opening adjacent to the first bank opening along a first direction, and forming a second light control pattern in the second bank opening through an inkjet process. A portion of the bank overlaps the first light control pattern in a plane, and a portion of the metal pattern overlaps at least a portion of the first light control pattern and the second light control pattern in a plane.

[0025] According to one embodiment of the present invention, a portion of a light control pattern included in a light control layer is formed as a photoresist pattern, a portion of an optically transparent bank covers the light control pattern formed as a photoresist pattern, and a metal pattern formed of a reflective metal is arranged on one side of the light control pattern. Accordingly, the light conversion efficiency of the light control layer can be improved, and while increasing the aperture ratio of the bank, the area where the metal pattern is arranged can be secured widely, so that a display panel including the light control layer can have a high resolution while improving display efficiency.

[0026] Figure 1a is a perspective view of a display panel according to one embodiment of the present invention.

[0027] Figure 1b is a cross-sectional view of a display panel according to one embodiment of the present invention.

[0028] Figure 1c is a plan view of a display panel according to one embodiment of the present invention.

[0029] FIG. 2 is an enlarged plan view of a portion of a display panel according to one embodiment of the present invention.

[0030] FIG. 3 is a cross-sectional view of a portion of a display panel according to one embodiment of the present invention.

[0031] FIGS. 4A to 4D are cross-sectional views of a portion of a display panel according to one embodiment of the present invention.

[0032] Figure 5 is a cross-sectional view of a light emitting device according to one embodiment of the present invention.

[0033] FIGS. 6A to 6C are each an enlarged cross-sectional view of a portion of a configuration of a display panel according to one embodiment of the present invention.

[0034] FIGS. 7A and 7B are each enlarged plan views of a portion of a configuration of a display panel according to one embodiment of the present invention.

[0035] Figure 8a is a flowchart showing a method for manufacturing a display panel according to one embodiment of the present invention.

[0036] Figure 8b is a flowchart showing some steps of a method for manufacturing a display panel according to one embodiment of the present invention.

[0037] FIGS. 9A to 9E are cross-sectional views illustrating some steps of a method for manufacturing a display panel according to one embodiment of the present invention.

[0038] Hereinafter, embodiments of the present invention will be described with reference to the drawings.

[0039] In this specification, when it is said that a component (or region, layer, portion, etc.) is “on,” “connected to,” or “coupled to” another component, it means that it can be directly connected / coupled to the other component, or a third component may be disposed between them.

[0040] Identical drawing numbers indicate identical components. Furthermore, in the drawings, the thicknesses, proportions, and dimensions of components are exaggerated for the purpose of effectively illustrating the technical content. "And / or" encompasses any combination of one or more of the associated components.

[0041] While terms such as "first" and "second" may be used to describe various components, these components should not be limited by these terms. These terms are used solely to distinguish one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a "second component," and similarly, a second component may also be referred to as a "first component." Singular expressions include plural expressions unless the context clearly indicates otherwise.

[0042] Additionally, terms such as "below," "lower," "above," and "upper" are used to describe the relationships between components depicted in the drawings. These terms are relative concepts and are described based on the directions indicated in the drawings.

[0043] Terms such as "include" or "have" should be understood to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but not to exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0044] In this specification, "directly disposed" may mean that there are no additional layers, films, regions, plates, etc., between a portion of a layer, film, region, plate, etc. and another portion. For example, "directly disposed" may mean disposed between two layers or two members without using an additional member, such as an adhesive member.

[0045] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should be interpreted to have a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an overly idealistic or overly formal sense unless explicitly defined herein.

[0046] Hereinafter, a display panel and a method for manufacturing the display panel according to one embodiment of the present invention will be described with reference to the drawings.

[0047] FIG. 1A is a perspective view of a display panel according to an embodiment of the present invention. FIG. 1B is a cross-sectional view of a display panel according to an embodiment of the present invention. FIG. 1C is a plan view of a display panel according to an embodiment of the present invention.

[0048] As illustrated in FIG. 1A, the display panel (DP) can display an image through a display surface (DP-IS). The display surface (DP-IS) is parallel to a plane defined by a first direction (DR1) and a second direction (DR2). The display surface (DP-IS) can include a display area (DA) and a non-display area (NDA). Pixels (PX) are arranged in the display area (DA), and pixels (PX) are not arranged in the non-display area (NDA). The non-display area (NDA) is defined along the border of the display surface (DP-IS). The non-display area (NDA) can surround the display area (DA). However, the present invention is not limited thereto, and in one embodiment of the present invention, the non-display area (NDA) may be omitted or arranged only on one side of the display area (DA).

[0049] The normal direction of the display surface (DP-IS), i.e., the thickness direction of the display panel (DP), is indicated by the third direction (DR3). The front (or upper surface) and the back (or lower surface) of each layer or unit described below are distinguished by the third direction (DR3). However, the first to third directions (DR1, DR2, DR3) illustrated in this embodiment are merely examples.

[0050] In one embodiment of the present invention, a display panel (DP) having a flat display surface (DP-IS) is illustrated, but is not limited thereto. The display panel (DP) may include a curved display surface or a three-dimensional display surface. The three-dimensional display surface may include a plurality of display areas pointing in different directions.

[0051] As illustrated in FIG. 1b, the display panel (DP) includes a base substrate (BS), a circuit element layer (DP-CL), a display element layer (DP-LED), and an optical structure layer (OSL). The base substrate (BS) may include a synthetic resin substrate or a glass substrate. The circuit element layer (DP-CL) includes at least one insulating layer and circuit elements. The circuit elements include signal lines, pixel driving circuits, etc. The circuit element layer (DP-CL) may be formed through a process of forming an insulating layer, a semiconductor layer, and a conductive layer by coating, deposition, etc., and a process of patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process. The display element layer (DP-LED) includes at least a display element. The optical structure layer (OSL) may convert the color of light provided from the display element. The optical structure layer (OSL) may include a light control pattern and a structure for increasing light conversion efficiency.

[0052] Fig. 1c illustrates the planar arrangement of signal lines (GL1 to GLn, DL1 to DLm) and pixels (PX11 to PXnm). The signal lines (GL1 to GLn, DL1 to DLm) may include a plurality of gate lines (GL1 to GLn) and a plurality of data lines (DL1 to DLm).

[0053] Each of the pixels (PX11 to PXnm) is connected to a corresponding gate line among a plurality of gate lines (GL1 to GLn) and a corresponding data line among a plurality of data lines (DL1 to DLm). Each of the pixels (PX11 to PXnm) may include a pixel driving circuit and a display element. Depending on the configuration of the pixel driving circuit of the pixels (PX11 to PXnm), more types of signal lines may be provided in the display panel (DP).

[0054] The gate driver circuit (GDC) can be integrated into the display panel (DP) through an oxide silicon gate driver circuit (OSG) or amorphose silicon gate driver circuit (ASG) process.

[0055] Fig. 2 is an enlarged plan view of a portion of a display panel according to an embodiment of the present invention. Fig. 3 is a cross-sectional view of a portion of a display panel according to an embodiment of the present invention. Figs. 4a to 4d are cross-sectional views of a portion of a display panel according to an embodiment of the present invention. Fig. 3 illustrates a cross-section corresponding to the line II' illustrated in Fig. 2. Figs. 4a to 4d illustrate cross-sections corresponding to the line II-II' illustrated in Fig. 2.

[0056] FIG. 2 illustrates the arrangement relationship of a plurality of pixel areas arranged in a display area (DA) in a display panel (DP, see FIG. 1a) of one embodiment. In one embodiment of the present invention, the shapes of the pixel areas (PXA-B, PXA-R, PXA-G) illustrated in FIG. 2 may be repeatedly arranged throughout the display area (DA, see FIG. 1a).

[0057] Referring to FIG. 2, a peripheral region (NPXA) is arranged around the first to third pixel regions (PXA-B, PXA-R, PXA-G). The peripheral region (NPXA) sets a boundary of the first to third pixel regions (PXA-B, PXA-R, PXA-G). The peripheral region (NPXA) may surround the first to third pixel regions (PXA-B, PXA-R, PXA-G). Meanwhile, in the present specification, one first pixel region (PXA-B), one second pixel region (PXA-R), and one third pixel region (PXA-G) arranged side by side in one direction (e.g., the first direction (DR1)) are described as a group as a "pixel unit (PXA-U)."

[0058] A structure that prevents color mixing between the first to third pixel areas (PXA-B, PXA-R, PXA-G), such as a pixel defining layer (PDL, see FIG. 3) or a bank (BMP, see FIG. 3), may be placed in the peripheral area (NPXA). Two or more color filters among the color filters described below may be placed in an overlapping manner in the peripheral area (NPXA).

[0059] As illustrated in FIG. 2, each of the first to third pixel regions (PXA-B, PXA-R, PXA-G) may have a rectangular shape. Each of the first to third pixel regions (PXA-B, PXA-R, PXA-G) may have a rectangular shape having a short side extending along the first direction (DR1) and a long side extending along the second direction (DR2). The first to third pixel regions (PXA-B, PXA-R, PXA-G) may be arranged to be spaced apart from each other along the first direction (DR1).

[0060] Although the first to third pixel areas (PXA-B, PXA-R, PXA-G) are illustrated as rectangular in FIG. 2, the present invention is not limited thereto. Some of the first to third pixel areas (PXA-B, PXA-R, PXA-G) may have polygonal shapes of different shapes (including substantial polygonal shapes) on a plane. In one embodiment, each of the first to third pixel areas (PXA-B, PXA-R, PXA-G) may have a rectangular shape (substantially rectangular shape) with rounded corners on a plane.

[0061] One of the first to third pixel areas (PXA-B, PXA-R, PXA-G) can provide blue light, another can provide red light, and the remaining one can provide green light. In the present embodiment, the first pixel area (PXA-B) can provide blue light, the second pixel area (PXA-R) can provide red light, and the third pixel area (PXA-G) can provide green light. Meanwhile, the first pixel area (PXA-B) can emit light having an emission wavelength of 410 nm to 480 nm, the second pixel area (PXA-R) can emit light having an emission wavelength of 620 nm to 700 nm, and the third pixel area (PXA-G) can emit light having an emission wavelength of 520 nm to 600 nm.

[0062] In Fig. 2, the areas of the first to third pixel areas (PXA-B, PXA-R, PXA-G) are illustrated as being the same, but this is not limited thereto, and the areas of the first to third pixel areas (PXA-B, PXA-R, PXA-G) may be set according to the light emission color. The area of ​​the pixel area emitting red light among the primary colors may be the largest, and the area of ​​the pixel area emitting blue light may be the smallest. That is, the area of ​​the second pixel area (PXA-R) emitting red light may be the largest, and the area of ​​the first pixel area (PXA-B) emitting blue light may be the smallest.

[0063] In one embodiment, a bank opening (BOH) corresponding to each pixel area (PXA) is provided in the display area (DA). The bank opening (BOH) may be provided corresponding to each pixel area (PXA) so that a plurality of light control patterns (CCP-B, CCP-R, CCP-G, see FIG. 4a) to be described later are arranged therein.

[0064] The bank opening (BOH) may include a first bank opening (BOH1) corresponding to a first pixel area (PXA-B), a second bank opening (BOH2) corresponding to a second pixel area (PXA-R), and a third bank opening (BOH3) corresponding to a third pixel area (PXA-G). Each of the first to third bank openings (BOH1, BOH2, BOH3) may have a rectangular shape. Each of the first to third bank openings (BOH1, BOH2, BOH3) may have a rectangular shape having a short side extending along a first direction (DR1) and a long side extending along a second direction (DR2). Each of the first to third bank openings (BOH1, BOH2, BOH3) may be arranged to be spaced apart from each other along the first direction (DR1).

[0065] The bank opening (BOH) may include an additional bank opening (BOHa) provided adjacent to a short side of at least one of the pixel areas (PXA). The additional bank opening (BOHa) may be provided, for example, adjacent to a short side of a second pixel area (PXA-R). An additional light control pattern (CCP-ad, see FIG. 7b), which will be described later, may be provided to be arranged in the additional bank opening (BOHa). The additional bank opening (BOHa) may be provided spaced apart from the second bank opening (BOH2) in a second direction (DR2).

[0066] Although not shown, a bank well region may be defined in the display area (DA). The bank well region may be a region where a bank well is formed to prevent defects due to misprinting in a process of printing some of the plurality of light control patterns (CCP-B, CCP-R, CCP-G, see FIG. 4a) included in the light control layer (CCL, see FIG. 4a). That is, the bank well region may be a region where a bank well formed by removing a portion of a bank (BMP, see FIG. 4a) is defined.

[0067] Referring to FIG. 3, a display panel (DP) of one embodiment may include a base substrate (BS), a circuit element layer (DP-CL) disposed on the base substrate (BS), and a display element layer (DP-LED) disposed on the circuit element layer (DP-CL). In the present specification, the base substrate (BS), the circuit element layer (DP-CL), and the display element layer (DP-LED) may be collectively referred to as a lower panel.

[0068] The base substrate (BS) may be a member that provides a reference surface on which components included in the circuit element layer (DP-CL) are placed. In one embodiment, the base substrate (BS) may be a glass substrate, a metal substrate, a polymer substrate, or the like. However, the embodiment is not limited thereto, and the base substrate (BS) may be an inorganic layer, a functional layer, or a composite material layer.

[0069] The base substrate (BS) may have a multilayer structure. For example, the base substrate (BS) may have a three-layer structure of a polymer resin layer, an adhesive layer, and a polymer resin layer. In particular, the polymer resin layer may include a polyimide-based resin. In addition, the polymer resin layer may include at least one of an acrylate-based resin, a methacrylate-based resin, a polyisoprene-based resin, a vinyl-based resin, an epoxy-based resin, a urethane-based resin, a cellulose-based resin, a siloxane-based resin, a polyamide-based resin, and a perylene-based resin. Meanwhile, in the present specification, an "α-based" resin means one that includes an "α" functional group.

[0070] A circuit element layer (DP-CL) may be arranged on a base substrate (BS). The circuit element layer (DP-CL) may include a transistor (TD) as a circuit element. The configuration of the circuit element layer (DP-CL) may vary depending on the design of the driving circuit of the pixel (PX, see FIG. 1a), and FIG. 3 illustrates one transistor (TD) as an example. The arrangement relationship of the active (AD), source (SD), drain (DD), and gate (GD) constituting the transistor (TD) is illustrated as an example. The active (AD), source (SD), and drain (DD) may be regions distinguished according to the doping concentration or conductivity of the semiconductor pattern.

[0071] The circuit element layer (DP-CL) may include a lower buffer layer (BRL), a first insulating layer (10), a second insulating layer (20), and a third insulating layer (30) disposed on a base substrate (BS). For example, the lower buffer layer (BRL), the first insulating layer (10), and the second insulating layer (20) may be inorganic layers, and the third insulating layer (30) may be an organic layer.

[0072] The display element layer (DP-LED) may include a light-emitting element (LED) as a display element. The light-emitting element (LED) may generate source light. In one embodiment, the source light may be white light or blue light. In the present embodiment, the display element layer (DP-LED) may include an organic light-emitting diode (OLED) as a light-emitting element. That is, the light-emitting layer (EML) included in the light-emitting element (LED) may include an organic light-emitting material as a light-emitting material.

[0073] A light emitting element (LED) includes a first electrode (EL1), a second electrode (EL2), and an emission layer (EML) disposed therebetween. In the present embodiment, the display element layer (DP-LED) may include an organic light emitting diode as the light emitting element. In one embodiment of the present invention, the light emitting element may include a quantum dot light emitting diode. That is, the emission layer (EML) included in the light emitting element (LED) may include an organic light emitting material as the light emitting material, or the emission layer (EML) may include a quantum dot as the light emitting material. Alternatively, the display element layer (DP-LED) in the present embodiment may include an ultra-small light emitting element, which will be described later, as the light emitting element. The ultra-small light emitting element may include, for example, a micro LED element and / or a nano LED element. The ultra-small light emitting element may be a light emitting element having a micro or nano scale size and including an active layer disposed between a plurality of semiconductor layers.

[0074] A first electrode (EL1) is placed on the third insulating layer (30). The first electrode (EL1) can be directly or indirectly connected to the transistor (TD), and the connection structure of the first electrode (EL1) and the transistor (TD) is not shown in FIG. 3.

[0075] The display element layer (DP-LED) includes a pixel defining layer (PDL). For example, the pixel defining layer (PDL) may be an organic layer. An emission aperture (OH) is defined in the pixel defining layer (PDL). The emission aperture (OH) of the pixel defining layer (PDL) exposes at least a portion of the first electrode (EL1). In the present embodiment, a second emission area (EA2) may be defined by the emission aperture (OH).

[0076] A hole control layer (HTR), an emission layer (EML), and an electron control layer (ETR) overlap at least a pixel area (PXA-R). Each of the hole control layer (HTR), the emission layer (EML), the electron control layer (ETR), and the second electrode (EL2) may be commonly arranged in the first to third pixel areas (PXA-B, PXA-R, PXA-G, see FIG. 4a). Each of the hole control layer (HTR), the emission layer (EML), the electron control layer (ETR), and the second electrode (EL2) overlapping the first to third pixel areas (PXA-B, PXA-R, PXA-G, see FIG. 4a) may have an integral shape. However, without limitation thereto, at least one of the hole control layer (HTR), the emission layer (EML), and the electron control layer (ETR) may be formed separately for each of the first to third pixel areas (PXA-B, PXA-R, PXA-G, see FIG. 4a). In one embodiment, the emission layer (EML) may be patterned within the emission opening (OH) and formed separately for each of the first to third pixel areas (PXA-B, PXA-R, PXA-G, see FIG. 4a).

[0077] The hole control layer (HTR) includes a hole transport layer and may further include a hole injection layer.

[0078] The emission layer (EML) can generate a third light, which is a source light. The emission layer (EML) can generate blue light. The blue light can include light with a wavelength of 410 nm to 480 nm. The emission spectrum of the blue light can have a maximum peak in the wavelength range of 440 nm to 460 nm.

[0079] The electron control layer (ETR) includes an electron transport layer and may further include an electron injection layer.

[0080] The display element layer (DP-LED) may include a thin film encapsulation layer (TFE) that protects the second electrode (EL2). The thin film encapsulation layer (TFE) may include an organic material or an inorganic material. The thin film encapsulation layer (TFE) may have a multilayer structure in which inorganic layers / organic layers are repeated. In the present embodiment, the thin film encapsulation layer (TFE) may include a first encapsulation inorganic layer (IOL1) / encapsulation organic layer (OL) / second encapsulation inorganic layer (IOL2). The first and second encapsulation inorganic layers (IOL1 / IOL2) protect the light emitting element (LED) from external moisture, and the encapsulation organic layer (OL) may prevent the light emitting element (LED) from being damaged by foreign substances introduced during the manufacturing process. Although not shown, the display panel (DP) may further include a refractive index control layer on the upper side of the thin film encapsulation layer (TFE) to improve light emission efficiency.

[0081] As illustrated in FIG. 3, an optical structure layer (OSL) may be disposed on a thin film encapsulation layer (TFE). The optical structure layer (OSL) may include a light control layer (CCL), a filler layer (FML), a color filter layer (CFL), and a base layer (BL). In this specification, the optical structure layer (OSL) may be referred to as an upper panel.

[0082] A light control layer (CCL) may be disposed on a display element layer (DP-LED) including a light emitting element (LED). The light control layer (CCL) may include a bank (BMP), a second light control pattern (CCP-R), a first barrier layer (CAP1), and a second barrier layer (CAP2).

[0083] A bank (BMP) may include a base resin and additives. The base resin may be composed of various resin compositions, which may be generally referred to as a binder. The additives may include a coupling agent and / or a photoinitiator. The additives may further include a dispersant.

[0084] In one embodiment, the bank (BMP) included in the light control layer (CCL) is optically transparent. The bank (BMP) may include an optically transparent material. The base resin included in the bank (BMP) may be optically transparent. The bank (BMP) may include a material having a transmittance of 85% or more in the visible light range. The bank (BMP) may not include a separate coloring agent. The bank (BMP) may include a black dye or black pigment mixed into the base resin. In one embodiment, the bank (BMP) may not include a light-blocking material having a black color, such as carbon black, or a pigment or dye having a blue color, etc.

[0085] The bank (BMP) may include a bank opening (BOH2) corresponding to the light-emitting opening (OH). In a plan view, the bank opening (BOH2) overlaps the light-emitting opening (OH) and has a larger area than the light-emitting opening (OH). That is, the bank opening (BOH2) may have a larger area than the light-emitting area (EA2) defined by the light-emitting opening (OH). Meanwhile, in the present specification, "corresponds" means that two configurations overlap when viewed in the thickness direction (DR3) of the display panel (DP), and is not limited to the same area.

[0086] A second optical control pattern (CCP-R) may be arranged inside the bank opening (BOH2). The second optical control pattern (CCP-R) may change the optical properties of the source light.

[0087] The second light control pattern (CCP-R) may include a first quantum dot (QD1) for changing the optical properties of the source light. The second light control pattern (CCP-R) may include a first quantum dot (QD1) for converting the source light into light of a different wavelength. In the second light control pattern (CCP-R) overlapping the second pixel area (PXA-R), the first quantum dot (QD1) may convert the source light into red light.

[0088] As used herein, "quantum dot" refers to a crystal of a semiconductor compound. Quantum dots can emit light of various emission wavelengths depending on the size of the crystal. Quantum dots can also emit light of various emission wavelengths by adjusting the element ratio within the quantum dot compound.

[0089] The diameter of the quantum dot may be, for example, about 1 nm to 10 nm.

[0090] The above quantum dots can be synthesized by a wet chemical process, an organometallic chemical vapor deposition process, a molecular beam epitaxy process, or a similar process.

[0091] The above wet chemical process is a method for growing quantum dot particle crystals by mixing an organic solvent and a precursor material. As the crystals grow, the organic solvent naturally acts as a dispersant coordinated to the quantum dot crystal surface, controlling the crystal growth. Therefore, the wet chemical process is easier and less expensive than vapor deposition methods such as metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), allowing for controlled growth of quantum dot particles.

[0092] The core of the quantum dot can be selected from a group II-VI compound, a group III-V compound, a group III-VI compound, a group I-III-VI compound, a group IV-VI compound, a group IV element, a group IV compound, and a combination thereof.

[0093] The group II-VI compound is a binary compound selected from the group consisting of CdSe, CdTe, CdS, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS and mixtures thereof; a ternary compound selected from the group consisting of CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, CdHgTe, HgZnS, HgZnSe, HgZnTe, MgZnSe, MgZnS and mixtures thereof; And it may be selected from the group consisting of a four-element compound selected from the group consisting of HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe and mixtures thereof. Meanwhile, the II-VI group semiconductor compound may further include a Group I metal and / or a Group IV element. The Group I-II-VI compound may be selected from CuSnS or CuZnS, and the Group II-IV-VI compound may be selected from ZnSnS, etc. The Group I-II-IV-VI compound may be selected from a four-element compound selected from the group consisting of Cu2ZnSnS2, Cu2ZnSnS4, Cu2ZnSnSe4, Ag2ZnSnS2 and mixtures thereof.

[0094] The III-VI group compounds may include binary compounds such as In2S3, In2Se3, etc., ternary compounds such as InGaS3, InGaSe3, etc., or any combination thereof.

[0095] Group I-III-VI compounds are ternary compounds selected from the group consisting of AgInS, AgInS2, CuInS, CuInS2, AgGaS2, CuGaS2CuGaO2, AgGaO2, AgAlO2 and mixtures thereof, or AgInGaS2, It can be selected from four-element compounds such as CuInGaS2.

[0096] The group III-V compound may be selected from the group consisting of binary compounds selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof, ternary compounds selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InAlP, InNP, InNAs, InNSb, InPAs, InPSb, and mixtures thereof, and quaternary compounds selected from the group consisting of GaAlNP, GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, and mixtures thereof. Meanwhile, the group III-V compound may further include a group II metal. For example, InZnP may be selected as the group III-II-V compound.

[0097] The group IV-VI compound may be selected from the group consisting of binary compounds selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe and mixtures thereof; ternary compounds selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe and mixtures thereof; and quaternary compounds selected from the group consisting of SnPbSSe, SnPbSeTe, SnPbSTe and mixtures thereof.

[0098] Examples of the above II-IV-V group semiconductor compounds may be ternary compounds selected from the group consisting of ZnSnP, ZnSnP2, ZnSnAs2, ZnGeP2, ZnGeAs2, CdSnP2, and CdGeP2 and mixtures thereof.

[0099] The group IV element may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

[0100] Each element included in the multi-element compounds such as the above binary, ternary and quaternary compounds may exist in the particles in a uniform or non-uniform concentration. That is, the chemical formula indicates the type of elements included in the compound, and the element ratio within the compound may be different. For example, AgInGaS2 is AgIn x Ga 1-x It can mean S2 (where x is a real number between 0 and 1).

[0101] Here, binary, ternary, or quaternary compounds may exist within the particle at a uniform concentration, or may exist within the same particle with partially different concentration distributions. Furthermore, one quantum dot may have a core / shell structure, where one quantum dot surrounds another. In a core / shell structure, the concentration of the element present in the shell may have a concentration gradient, decreasing toward the core.

[0102] In some embodiments, the quantum dot may have a core-shell structure comprising a core comprising the aforementioned nanocrystals and a shell surrounding the core. The shell of the quantum dot may function as a protective layer to maintain semiconductor properties by preventing chemical modification of the core and / or as a charging layer to impart electrophoretic properties to the quantum dot. The shell may be a single layer or a multilayer. Examples of the shell of the quantum dot include a metal or non-metal oxide, a semiconductor compound, or a combination thereof.

[0103] For example, the oxide of the metal or non-metal may be a binary compound such as SiO2, Al2O3, TiO2, ZnO, MnO, Mn2O3, Mn3O4, CuO, FeO, Fe2O3, Fe3O4, CoO, Co3O4, NiO, or a ternary compound such as MgAl2O4, CoFe2O4, NiFe2O4, CoMn2O4, but the present invention is not limited thereto.

[0104] In addition, the semiconductor compound may be exemplified by CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc., but the present invention is not limited thereto.

[0105] Quantum dots can have a full width of half maximum (FWHM) of an emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, and more preferably about 30 nm or less, and color purity and color reproducibility can be improved within this range. In addition, since light emitted by these quantum dots is emitted in all directions, a wide viewing angle can be improved.

[0106] In addition, the shape of the quantum dot is not particularly limited to a shape commonly used in the field, but more specifically, a shape such as a spherical, pyramidal, multi-arm, or cubic nanoparticle, nanotube, nanowire, nanofiber, or nanoplatelet particle can be used.

[0107] Since the energy band gap of quantum dots can be controlled by adjusting the size of the quantum dots or the element ratio within the quantum dot compound, light of various wavelengths can be obtained from the quantum dot light-emitting layer. Therefore, by using quantum dots as described above (using quantum dots of different sizes or varying the element ratio within the quantum dot compound), a light-emitting device that emits light of various wavelengths can be implemented. Specifically, the size of the quantum dots or the element ratio within the quantum dot compound can be selected to emit red, green, and / or blue light. In addition, the quantum dots can be configured to emit white light by combining light of various colors.

[0108] In one embodiment, the first quantum dot (QD1) included in the second light control pattern (CCP-R) overlapping the second pixel area (PXA-R) may have a red emission color. The smaller the particle size of the quantum dot, the more it may emit light in a shorter wavelength range. For example, among quantum dots having the same core, the particle size of a quantum dot that emits green light may be smaller than the particle size of a quantum dot that emits red light. Additionally, among quantum dots having the same core, the particle size of a quantum dot that emits blue light may be smaller than the particle size of a quantum dot that emits green light. However, the embodiment is not limited thereto, and even among quantum dots having the same core, the particle size may be controlled depending on a shell forming material, shell thickness, etc.

[0109] Meanwhile, if quantum dots have various emission colors such as blue, red, and green, quantum dots with different emission colors may have different core materials.

[0110] The second light control pattern (CCP-R) may further include a scatterer (SP). The second light control pattern (CCP-R) may include a first quantum dot (QD1) that converts blue light into red light and a scatterer (SP) that scatters light.

[0111] The scatterer (SP) may be an inorganic particle. For example, the scatterer (SP) may include at least one of TiO2, ZnO, Al2O3, SiO2, and hollow silica. The scatterer (SP) may include any one of TiO2, ZnO, Al2O3, SiO2, and hollow silica, or may be a mixture of two or more materials selected from TiO2, ZnO, Al2O3, SiO2, and hollow silica.

[0112] The second light control pattern (CCP-R) may include a second base resin (BR2) that disperses the first quantum dot (QD1) and the scatterer (SP). The second base resin (BR2) is a medium in which the first quantum dot (QD1) and the scatterer (SP) are dispersed, and may be formed of various resin compositions that may generally be referred to as binders. For example, the second base resin (BR2) may be an acrylic resin, a urethane resin, a silicone resin, an epoxy resin, etc. The second base resin (BR2) may be a transparent resin. The second base resin (BR2) may be a resin selected to perform an inkjet process.

[0113] In this embodiment, the second light control pattern (CCP-R) can be formed by an inkjet process. The second light control pattern (CCP-R) can be formed by a curing process after a liquid composition is provided within the second bank opening (BOH2). A composition polymerized by a thermal or photo-curing process can have a reduced volume after curing.

[0114] The light control layer (CCL) may include a first barrier layer (CAP1) disposed on one surface of the second light control pattern (CCP-R). The first barrier layer (CAP1) may serve to prevent the penetration of moisture and / or oxygen (hereinafter referred to as “moisture / oxygen”) and to improve the optical characteristics of the optical structure layer (OSL) by controlling the refractive index. The first barrier layer (CAP1) may be disposed on one upper surface or one lower surface of the second light control pattern (CCP-R) to block the second light control pattern (CCP-R) from being exposed to moisture / oxygen, and in particular, may block quantum dots included in the second light control pattern (CCP-R) from being exposed to moisture / oxygen. The first barrier layer (CAP1) may also protect the second light control pattern (CCP-R) from external impact.

[0115] In one embodiment, the first barrier layer (CAP1) may be disposed spaced apart from the display element layer (DP-LED) with the second light control pattern (CCP-R) interposed therebetween. That is, the first barrier layer (CAP1) may be disposed on an upper surface of the second light control pattern (CCP-R). In one embodiment, the light control layer (CCL) may include a second barrier layer (CAP2) disposed between the second light control pattern (CCP-R) and the display element layer (DP-LED). The first barrier layer (CAP1) may cover an upper surface of the second light control pattern (CCP-R) adjacent to the filling layer (FML), and the second barrier layer (CAP2) may cover a lower surface of the second light control pattern (CCP-R) adjacent to the display element layer (DP-LED). Meanwhile, in this specification, the “upper surface” may be a surface located above in the third direction (DR3), and the “lower surface” may be a surface located below in the third direction (DR3).

[0116] Additionally, the first barrier layer (CAP1) and the second barrier layer (CAP2) may cover one side of the bank (BMP) as well as the second light control pattern (CCP-R).

[0117] The first barrier layer (CAP1) may cover one side of the bank (BMP) adjacent to the filling layer (FML) and the second light control pattern (CCP-R). The first barrier layer (CAP1) may be disposed directly under the filling layer (FML). The second barrier layer (CAP2) may be disposed directly on the thin film encapsulation layer (TFE). The light control layer (CCL) may be disposed on the display element layer (DP-LED) and the thin film encapsulation layer (TFE) with the second barrier layer (CAP2) interposed therebetween. The light control patterns (CCP-B, CCP-R, CCP-G) of the light control layer (CCL) may be formed in a continuous process on the second barrier layer (CAP2) disposed on the thin film encapsulation layer (TFE).

[0118] The first barrier layer (CAP1) and the second barrier layer (CAP2) may be formed of an inorganic material. In the display panel (DP) of one embodiment, the first barrier layer (CAP1) may include silicon oxynitride (SiON). The first barrier layer (CAP1) and the second barrier layer (CAP2) may both include silicon oxynitride. However, the present invention is not limited thereto, and each of the first barrier layer (CAP1) and the second barrier layer (CAP2) may include silicon oxide (SiO x ) or silicon nitride (SiN x ) may be included. In one embodiment, the first barrier layer (CAP1) disposed on the upper side of the second light control pattern (CCP-R) may include silicon oxynitride, and the second barrier layer (CAP2) disposed on the lower side of the second light control pattern (CCP-R) may include silicon oxide.

[0119] A color filter layer (CFL) may be disposed on the light control layer (CCL). The color filter layer (CFL) includes at least one color filter. The color filter transmits light within a specific wavelength range and blocks light outside the corresponding wavelength range. The second color filter (CF2) corresponding to the second pixel area (PXA-R) may transmit red light and block green and blue light.

[0120] The second color filter (CF2) includes a base resin and a dye and / or pigment dispersed in the base resin. The base resin is a medium in which the dye and / or pigment is dispersed and may be composed of various resin compositions, which may generally be referred to as a binder.

[0121] The second color filter (CF2) may have a uniform thickness within the second pixel area (PXA-R). Light converted from a blue source light to red light through the second light control pattern (CCP-R) may be provided to the outside with uniform brightness within the second pixel area (PXA-R).

[0122] The optical structure layer (OSL) may further include a filling layer (FML) disposed between the light control layer (CCL) and the color filter layer (CFL). In one embodiment, the filling layer (FML) may fill a space between the light control layer (CCL) and the color filter layer (CFL). The filling layer (FML) may be disposed directly on the first barrier layer (CAP1), and the color filter layer (CFL) may be disposed directly on the filling layer (FML). A lower surface of the filling layer (FML) may be in contact with an upper surface of the first barrier layer (CAP1), and an upper surface of the filling layer (FML) may be in contact with lower surfaces of the color filters (CF1, CF2, CF3) of the color filter layer (CFL).

[0123] The filler layer (FML) can function as a buffer between the light control layer (CCL) and the color filter layer (CFL). In one embodiment, the filler layer (FML) can have a shock absorption function, etc., and can increase the strength of the display panel (DP). The filler layer (FML) can be formed from a filler resin including a polymer resin. For example, the filler layer (FML) can be formed from a filler resin including an acrylic resin or an epoxy resin.

[0124] Meanwhile, the filler layer (FML) may be positioned between the light control layer (CCL) and the color filter layer (CFL) to increase light extraction efficiency or may function as an optical functional layer, such as preventing reflected light from entering the light control layer (CCL). The filler layer (FML) may be a layer having a lower refractive index compared to adjacent layers.

[0125] In one embodiment, the display panel (DP) may further include a base layer (BL) disposed on a color filter layer (CFL). The base layer (BL) may be a member that provides a reference surface on which the color filter layer (CFL), the low-refractive layer (LR), and the light control layer (CCL) are disposed. The base layer (BL) may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the embodiment is not limited thereto, and the base layer (BL) may be an inorganic layer, an organic layer, or a composite material layer. In addition, unlike the embodiment illustrated, the base layer (BL) may be omitted in one embodiment.

[0126] Although not shown, an anti-reflection layer may be disposed on the base layer (BL). The anti-reflection layer may be a layer that reduces the reflectance of external light incident from the outside. The anti-reflection layer may be a layer that selectively transmits light emitted from the display panel (DP). In one embodiment, the anti-reflection layer may be a single layer including a dye and / or pigment dispersed in a base resin. The anti-reflection layer may be provided as a single continuous layer that completely overlaps the entire first to third pixel areas (PXA-B, PXA-R, PXA-G, see FIG. 4A).

[0127] The anti-reflection layer may not include a polarizing layer. Accordingly, light passing through the anti-reflection layer and incident on the display element layer (DP-LED) may be unpolarized light. The display element layer (DP-LED) can receive unpolarized light from above the anti-reflection layer.

[0128] Referring to FIG. 4A, the display panel (DP) may include a base substrate (BS) and a circuit element layer (DP-CL) disposed on the base substrate (BS). The circuit element layer (DP-CL) may be disposed on the base substrate (BS). The circuit element layer (DP-CL) may include an insulating layer, a semiconductor pattern, a conductive pattern, a signal line, and the like. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base substrate (BS) by a coating, deposition, or the like, and then the insulating layer, the semiconductor layer, and the conductive layer may be selectively patterned through multiple photolithography processes. Thereafter, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit element layer (DP-CL) may be formed. In one embodiment, the circuit element layer (DP-CL) may include a transistor, a buffer layer, and a plurality of insulating layers.

[0129] According to one embodiment, a light emitting device (LED) may include a first electrode (EL1), a second electrode (EL2) facing the first electrode (EL1), and an emission layer (EML) disposed between the first electrode (EL1) and the second electrode (EL2). The emission layer (EML) included in the light emitting device (LED) may include an organic light emitting material as a light emitting material or may include quantum dots. The light emitting device (LED) may further include a hole control layer (HTR) and an electron control layer (ETR). Meanwhile, although not shown, the light emitting device (LED) may further include a capping layer (not shown) disposed on the second electrode (EL2).

[0130] A pixel defining layer (PDL) is disposed on a circuit element layer (DP-CL) and can cover a portion of a first electrode (EL1). A light-emitting aperture (OH) is defined in the pixel defining layer (PDL). The light-emitting aperture (OH) of the pixel defining layer (PDL) exposes at least a portion of the first electrode (EL1). In the present embodiment, light-emitting areas (EA1, EA2, EA3) are defined to correspond to a portion of the first electrode (EL1) exposed by the light-emitting aperture (OH).

[0131] The display element layer (DP-LED) may include a first light-emitting area (EA1), a second light-emitting area (EA2), and a third light-emitting area (EA3). The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may be areas defined by a pixel defining layer (PDL). The first light-emitting area (EA1), the second light-emitting area (EA2), and the third light-emitting area (EA3) may correspond to the first pixel area (PXA-B), the second pixel area (PXA-R), and the third pixel area (PXA-G), respectively.

[0132] The light-emitting areas (EA1, EA2, EA3) may overlap with the pixel areas (PXA-B, PXA-R, PXA-G). When viewed in a planar manner, the area of ​​the pixel areas (PXA-B, PXA-R, PXA-G) defined by the color filters (CF1, CF2, CF3) may be substantially the same as the area of ​​the light-emitting areas (EA1, EA2, EA3) defined by the pixel defining layer (PDL).

[0133] In a light-emitting diode (LED), a first electrode (EL1) is disposed on a circuit element layer (DP-CL). The first electrode (EL1) may be an anode or a cathode. Additionally, the first electrode (EL1) may be a pixel electrode. The first electrode (EL1) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0134] A hole control layer (HTR) may be disposed between the first electrode (EL1) and the light emitting layer (EML). The hole control layer (HTR) may include at least one of a hole injection layer, a hole transport layer, and an electron blocking layer. The hole control layer (HTR) may be disposed as a common layer so as to overlap the entire light emitting areas (EA1, EA2, EA3) and the pixel defining layer (PDL) that separates the light emitting areas (EA1, EA2, EA3). However, the embodiment is not limited thereto, and the hole control layer (HTR) may be patterned and provided so as to be disposed separately corresponding to each of the light emitting areas (EA1, EA2, EA3).

[0135] An emission layer (EML) is disposed on a hole control layer (HTR). In one embodiment, the emission layer (EML) may be provided as a common layer so as to overlap the entire emission areas (EA1, EA2, EA3) and the pixel defining layer (PDL) that separates the emission areas (EA1, EA2, EA3). In one embodiment, the emission layer (EML) may emit blue light. The emission layer (EML) may overlap the entire hole control layer (HTR) and the electron control layer (ETR).

[0136] However, the embodiment is not limited thereto, and in one embodiment, the light-emitting layer (EML) may be disposed within the light-emitting aperture (OH). That is, the light-emitting layer (EML) may be formed separately to correspond to light-emitting areas (EA1, EA2, EA3) defined by the pixel defining layer (PDL). The light-emitting layers (EML) formed separately to correspond to the light-emitting areas (EA1, EA2, EA3) may all emit blue light, or may emit light in different wavelength regions.

[0137] The light-emitting layer (EML) may have a multilayer structure having a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. The light-emitting layer (EML) may include a fluorescent or phosphorescent material. In the light-emitting device of one embodiment, the light-emitting layer (EML) may include an organic light-emitting material, a metal-organic complex, or a quantum dot as a light-emitting material. Meanwhile, although FIGS. 3 and 4A illustrate a light-emitting device (LED) including one light-emitting layer (EML), in one embodiment, the light-emitting device (LED) may include multiple light-emitting stacks, each of which includes at least one light-emitting layer.

[0138] Fig. 5 is a cross-sectional view of a light-emitting device according to one embodiment of the present invention. Unlike the light-emitting device of the embodiment illustrated in Figs. 3 and 4a, Fig. 5 exemplarily illustrates a light-emitting device (LED) including a plurality of light-emitting stacks (ST1, ST2, ST3, ST4).

[0139] Referring to FIG. 5, a light emitting element (LED) of one embodiment may include a first electrode (EL1), a second electrode (EL2) facing the first electrode (EL1), and first to fourth light emitting stacks (ST1, ST2, ST3, ST4) disposed between the first electrode (EL1) and the second electrode (EL2). Meanwhile, FIG. 5 exemplarily illustrates that the light emitting element (LED) includes four light emitting stacks, but the number of light emitting stacks included in the light emitting element (LED) may be less or more than this.

[0140] The light emitting diode (LED) may include first to third charge generation layers (CGL1, CGL2, CGL3) disposed between first to fourth light emitting stacks (ST1, ST2, ST3, ST4).

[0141] When voltage is applied, each of the first to third charge generation layers (CGL1, CGL2, CGL3) can generate charges (electrons and holes) by forming a complex through an oxidation-reduction reaction. Thereafter, the first to third charge generation layers (CGL1, CGL2, CGL3) can provide the generated charges to the adjacent stacks (ST1, ST2, ST3, ST4), respectively. The first to third charge generation layers (CGL1, CGL2, CGL3) can double the efficiency of current generated in the adjacent stacks (ST1, ST2, ST3, ST4) and can play a role in controlling the balance of charges between the adjacent stacks (ST1, ST2, ST3, ST4).

[0142] Each of the first to third charge generation layers (CGL1, CGL2, CGL3) may include an n-type layer and a p-type layer. The first to third charge generation layers (CGL1, CGL2, CGL3) may have a structure in which the n-type layer and the p-type layer are bonded to each other. However, the present invention is not limited thereto, and the first to third charge generation layers (CGL1, CGL2, CGL3) may include only one of the n-type layer and the p-type layer. The n-type layer may be a charge generation layer that provides electrons to an adjacent stack. The n-type layer may be a layer in which an n-dopant is doped into a base material. The p-type layer may be a charge generation layer that provides holes to an adjacent stack.

[0143] In one embodiment, the thickness of each of the first to third charge generation layers (CGL1, CGL2, CGL3) may be 1 angstrom (Å) or more and 150 angstroms (Å) or less. The concentration of the n-dopant doped in the first to third charge generation layers (CGL1, CGL2, CGL3) may be 0.1% or more and 3% or less, and specifically, 1% or less. When the concentration is less than 0.1%, the effect of the first to third charge generation layers (CGL1, CGL2, CGL3) controlling the balance of charges may hardly occur. When the concentration is greater than 3%, the light efficiency of the light emitting diode (LED) may be reduced.

[0144] Each of the first to third charge generation layers (CGL1, CGL2, CGL3) may include a charge generation compound composed of an aryl amine organic compound, a metal, an oxide, carbide, fluoride of a metal, or a mixture thereof. For example, the aryl amine organic compound may include α-NPD, 2-TNATA, TDATA, MTDATA, sprio-TAD, or sprio-NPB. The metal may include cesium (Cs), molybdenum (Mo), vanadium (V), titanium (Ti), tungsten (W), barium (Ba), or lithium (Li). The oxide, carbide, and fluoride of the metal may include Re2O7, MoO3, V2O5, WO3, TiO2, Cs2CO3, BaF, LiF, or CsF. However, the materials of the first to third charge generation layers (CGL1, CGL2, CGL3) are not limited to the above examples.

[0145] Each of the first to fourth light-emitting stacks (ST1, ST2, ST3, and ST4) may include a light-emitting layer. The first light-emitting stack (ST1) may include a first light-emitting layer (BEML1), the second light-emitting stack (ST2) may include a second light-emitting layer (BEML2), the third light-emitting stack (ST3) may include a third light-emitting layer (BEML3), and the fourth light-emitting stack (ST4) may include a fourth light-emitting layer (GEML). Some of the light-emitting layers included in the first to fourth light-emitting stacks (ST1, ST2, ST3, and ST4) may emit substantially the same color light, and some may emit different color light.

[0146] In one embodiment, the first to third light-emitting layers (BEML1, BEML2, BEML3) of the first to third light-emitting stacks (ST1, ST2, ST3) can emit substantially the same first color light. For example, the first color light can be blue light, which is the source light described above. The wavelength range of the light emitted by the first to third light-emitting layers (BEML1, BEML2, BEML3) can be about 420 nm or more and 480 nm or less.

[0147] The fourth light-emitting layer (GEML) of the fourth light-emitting stack (ST4) can emit a second color light different from the first color light. For example, the second color light can be green light. The wavelength range of the light emitted by the fourth light-emitting layer (GEML) can be about 520 nm or more and 600 nm or less.

[0148] A light emitting element (LED) can emit light from a first electrode (EL1) toward a second electrode (EL2). In one embodiment of the light emitting element (LED), each of the plurality of stacks (ST1, ST2, ST3, ST4) can include a hole transport region (HTR1, HTR2, HTR3, HTR4) and an electron transport region (ETR1, ETR2, ETR3, ETR4). The hole transport regions (HTR1, HTR2, HTR3, HTR4) can transfer holes provided from the first electrode (EL1) or the charge generation layer (CGL1, CGL2, CGL3) to the light emitting layer. The electron transport regions (ETR1, ETR2, ETR3, ETR4) can transfer electrons provided from the second electrode (EL2) or the charge generation layer (CGL1, CGL2, CGL3) to the light emitting layer.

[0149] An example of a light emitting diode (LED) is a structure in which hole transport regions (HTR1, HTR2, HTR3, HTR4) are arranged below light emitting layers (BEML1, BEML2, BEML3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4) with respect to a direction in which light is emitted, and electron transport regions (ETR1, ETR2, ETR3, ETR4) are arranged above light emitting layers (BEML1, BEML2, BEML3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4). That is, the light emitting device (LED) of one embodiment may have a forward device structure, but is not limited thereto, and may have an inverted device structure in which electron transport regions (ETR1, ETR2, ETR3, ETR4) are arranged below light emitting layers (BEML1, BEML2, BEML3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4) and hole transport regions (HTR1, HTR2, HTR3, HTR4) are arranged above light emitting layers (BEML1, BEML2, BEML3, GEML) included in a plurality of stacks (ST1, ST2, ST3, ST4) based on the light emitting direction.

[0150] Each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) may include a hole injection layer (HIL1, HIL2, HIL3, HIL4) and a hole transport layer (HTL1, HTL2, HTL3, HTL4) disposed on the hole injection layer (HIL1, HIL2, HIL3, HIL4). The hole transport layer (HTL1, HTL2, HTL3, HTL4) may contact a lower surface of the light emitting layer. However, the present invention is not limited thereto, and the hole transport regions (HTR1, HTR2, HTR3, HTR4) may further include a hole-side additional layer disposed on the hole transport layer (HTL1, HTL2, HTL3, HTL4). The hole-side additional layer may include at least one of a hole buffer layer, a light emitting auxiliary layer, and an electron blocking layer. The hole buffer layer may be a layer that compensates for a resonance distance according to a wavelength of light emitted from the light emitting layer to increase light emission efficiency. The electron blocking layer may be a layer that serves to prevent electron injection from the electron transport region to the hole transport region.

[0151] The electron transport regions (ETR1, ETR2, ETR3, ETR4) may include an electron transport layer. The electron transport regions (ETR1, ETR2, ETR3, ETR4) may further include an electron injection layer disposed on the electron transport layer. For example, the fourth electron transport region (ETR4) included in the fourth light-emitting stack (ST4) may further include a fourth electron injection layer (EIL4) disposed on the fourth electron transport layer (ETL4). The electron transport regions (ETR1, ETR2, ETR3, ETR4) may further include an electron-side additional layer disposed between the electron transport layer and the light-emitting layers. The electron-side additional layer may include at least one of an electron buffer layer and a hole blocking layer.

[0152] In a light emitting device (LED) according to one embodiment, the first electrode (EL1) may be a reflective electrode. For example, the first electrode (EL1) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (for example, a mixture of Ag and Mg) having high reflectivity. Alternatively, the first electrode (EL1) may have a multi-layer structure including a reflective film formed of the above materials and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the first electrode (EL1) may have a two-layer structure of ITO / Ag and a three-layer structure of ITO / Ag / ITO, but is not limited thereto. In addition, the embodiment is not limited thereto, and the first electrode (EL1) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials. The thickness of the first electrode (EL1) may be about 70 nm to about 1000 nm. For example, the thickness of the first electrode (EL1) may be about 100 nm to about 300 nm.

[0153] In a light emitting diode (LED) according to one embodiment, each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) may have a multilayer structure having a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials.

[0154] Each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0155] Each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) contains a phthalocyanine compound such as copper phthalocyanine, DNTPD(N 1 ,N 1' -([1,1'-biphenyl]-4,4'-diyl)bis(N 1 -phenyl-N 4 ,N 4-di-m-tolylbenzene-1,4-diamine)), m-MTDATA(4,4',4"-[tris(3-methylphenyl)phenylamino] triphenylamine), TDATA(4,4'4"-Tris(N,N-diphenylamino)triphenylamine), 2-TNATA(4,4',4"-tris[N(2-naphthyl)-N-phenylamino]-triphenylamine), PEDOT / PSS(Poly(3,4-ethylenedioxythiophene) / Poly(4-styrenesulfonate)), PANI / DBSA(Polyaniline / Dodecylbenzenesulfonic acid), PANI / CSA(Polyaniline / Camphor sulfonicacid), PANI / PSS(Polyaniline / Poly(4-styrenesulfonate)), NPB(N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), 트리페닐아민을 포함하는 폴리에테르케톤(TPAPEK), 4-Isopropyl-4'-methyldiphenyliodonium [Tetrakis(pentafluorophenyl)borate], HATCN(dipyrazino[2,3-f: 2',3'-h] quinoxaline-2,3,6,7,10,11-hexacarbonitrile) 등을 포함할 수 있다.

[0156] Each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) contains carbazole derivatives such as N-phenylcarbazole and polyvinylcarbazole, fluorene derivatives, triphenylamine derivatives such as TPD (N,N'-bis(3-methylphenyl)-N,N'-diphenyl-[1,1'-biphenyl]-4,4'-diamine), TCTA (4,4',4"-tris(N-carbazolyl)triphenylamine), NPB (N,N'-di(naphthalene-l-yl)-N,N'-diphenyl-benzidine), TAPC (4,4'-Cyclohexylidene bis[N,N-bis(4-methylphenyl)benzenamine]), HMTPD (4,4'-Bis[N,N'-(3-tolyl)amino]-3,3'-dimethylbiphenyl), It may also contain mCP (1,3-Bis(N-carbazolyl)benzene).

[0157] Additionally, each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) may include CzSi (9-(4-tert-Butylphenyl)-3,6-bis(triphenylsilyl)-9H-carbazole), CCP (9-phenyl-9H-3,9'-bicarbazole), or mDCP (1,3-bis(1,8-dimethyl-9H-carbazol-9-yl)benzene).

[0158] The hole transport region (HTR1, HTR2, HTR3, HTR4) may include compounds of the above-described hole transport region in at least one of the hole injection layer (HIL1, HIL2, HIL3, HIL4), the hole transport layer (HTL1, HTL2, HTL3, HTL4), and the hole-side additional layer.

[0159] The thickness of each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) may be from about 10 nm to about 1000 nm, for example, from about 10 nm to about 500 nm. The thickness of each of the hole injection layers (HIL1, HIL2, HIL3, HIL4) may be from about 5 nm to about 100 nm, for example. The thickness of each of the hole transport layers (HTL1, HTL2, HTL3, HTL4) may be from about 5 nm to about 100 nm. When the hole transport regions (HTR1, HTR2, HTR3, HTR4) include a hole-side additional layer, the thickness of the hole-side additional layer may be from about 1 nm to about 100 nm. When the hole transport regions (HTR1, HTR2, HTR3, HTR4) and the thickness of each layer included therein satisfy the ranges described above, satisfactory hole transport characteristics can be obtained without a substantial increase in driving voltage.

[0160] In addition to the aforementioned materials, each of the hole transport regions (HTR1, HTR2, HTR3, HTR4) may further include a charge generating material to improve conductivity. The charge generating material may be uniformly or non-uniformly dispersed within the hole transport regions (HTR1, HTR2, HTR3, HTR4). The charge generating material may be, for example, a p-type dopant. The p-type dopant may include, but is not limited to, at least one of a halogenated metal compound, a quinone derivative, a metal oxide, and a cyano group-containing compound. For example, p-type dopants may include, but are not limited to, halogenated metal compounds such as CuI and RbI, quinone derivatives such as TCNQ (Tetracyanoquinodimethane) and F4-TCNQ (2,3,5,6-tetrafluoro-7,7'8,8-tetracyanoquinodimethane), and metal oxides such as tungsten oxide and molybdenum oxide.

[0161] Each of the blue light-emitting layers (BEML1, BEML2, BEML3) and the green light-emitting layer (GEML) may include a host material and a dopant material. Each of the blue light-emitting layers (BEML1, BEML2, BEML3) and the green light-emitting layer (GEML) may include a material including a carbazole derivative moiety or an amine derivative moiety as a hole-transporting host material. Each of the blue light-emitting layers (BEML1, BEML2, BEML3) and the green light-emitting layer (GEML) may include a material including a nitrogen-containing aromatic ring structure such as a pyridine derivative moiety, a pyridazine derivative moiety, a pyrimidine derivative moiety, a pyrazine derivative moiety, or a triazine derivative moiety as an electron-transporting host material.

[0162] Each of the blue light-emitting layers (BEML1, BEML2, BEML3) and the green light-emitting layer (GEML) may include, as a host material, an anthracene derivative, a pyrene derivative, a fluoranthene derivative, a chrysene derivative, a dihydrobenzanthracene derivative, or a triphenylene derivative. In addition, each of the blue light-emitting layers (BEML1, BEML2, BEML3) and the green light-emitting layer (GEML) may further include, as a host material, a general material known in the art. For example, each of the blue emitting layers (BEML1, BEML2, BEML3) and the green emitting layer (GEML) may include at least one of DPEPO (Bis[2-(diphenylphosphino)phenyl] ether oxide), CBP (4,4'-Bis(carbazol-9-yl)biphenyl), mCP (1,3-Bis(carbazol-9-yl)benzene), PPF (2,8-Bis(diphenylphosphoryl)dibenzo[b,d]furan), TCTA (4,4',4''-Tris(carbazol-9-yl)-triphenylamine), and TPBi (1,3,5-tris(1-phenyl-1H-benzo[d]imidazole-2-yl)benzene) as a host material.However, it is not limited thereto, and for example, Alq3(tris(8-hydroxyquinolino)aluminum), PVK(poly(N-vinylcarbazole), ADN(9,10-di(naphthalene-2-yl)anthracene), TBADN(2-tert-butyl-9,10-di(naphth-2-yl)anthracene), DSA(distyrylarylene), CDBP(4,4'-bis(9-carbazolyl)-2,2'-dimethyl-biphenyl), MADN(2-Methyl-9,10-bis(naphthalen-2-yl)anthracene), CP1(Hexaphenyl cyclotriphosphazene), UGH2 (1,4-Bis(triphenylsilyl)benzene), DPSiO3(Hexaphenylcyclotrisiloxane), DPSiO4(Octaphenylcyclotetra siloxane), etc. can be used as the host material.

[0163] In one embodiment, the blue emitting layers (BEML1, BEML2, BEML3) are known fluorescent dopant materials, such as styryl derivatives (e.g., 1,4-bis[2-(3-N-ethylcarbazoryl)vinyl]benzene(BCzVB), 4-(di-p-tolylamino)-4'-[(di-p-tolylamino)styryl]stilbene(DPAVB), N-(4-((E)-2-(6-((E)-4-(diphenylamino)styryl)naphthalen-2-yl)vinyl)phenyl)-N-phenylbenzenamine(N-BDAVBi)), 4,4'-bis[2-(4-(N,N-diphenylamino)phenyl)vinyl]biphenyl(DPAVBi), perylene and derivatives thereof (e.g., 2,5,8,11-Tetra-t-butylperylene (TBP)), pyrene and its derivatives (e.g., 1,1-dipyrene, 1,4-dipyrenylbenzene, 1,4-Bis(N, N-Diphenylamino)pyrene), etc.

[0164] The green emitting layer (GEML) may include a known phosphorescent dopant material. For example, the phosphorescent dopant may be a metal complex including iridium (Ir), platinum (Pt), osmium (Os), gold (Au), titanium (Ti), zirconium (Zr), hafnium (Hf), europium (Eu), terbium (Tb), or thulium (Tm). Specifically, FIrpic (iridium(III) bis(4,6-difluorophenylpyridinato-N,C2')picolinate), Fir6 (Bis(2,4-difluorophenylpyridinato)-tetrakis(1-pyrazolyl)borate iridium(²), or PtOEP (platinum octaethyl porphyrin) may be used as the phosphorescent dopant.

[0165] Each of the electron transport regions (ETR1, ETR2, ETR3, ETR4) may have a multilayer structure including a single layer made of a single material, a single layer made of multiple different materials, or multiple layers made of multiple different materials. For example, at least some of the electron transport regions (ETR1, ETR2, ETR3, ETR4) may include an electron transport layer (ETL4) and an electron injection layer (EIL4).

[0166] Each of the electron transport regions (ETR1, ETR2, ETR3, ETR4) can be formed using various methods such as vacuum deposition, spin coating, casting, Langmuir-Blodgett (LB) method, inkjet printing, laser printing, and laser induced thermal imaging (LITI).

[0167] The electron transport domains (ETR1, ETR2, ETR3, ETR4) may contain anthracene compounds. However, it is not limited thereto, and each of the electron transport domains (ETR1, ETR2, ETR3, ETR4) may be, for example, Alq3 (Tris(8-hydroxyquinolinato)aluminum), 1,3,5-tri[(3-pyridyl)-phen-3-yl]benzene, T2T (2,4,6-tris(3'-(pyridin-3-yl)biphenyl-3-yl)-1,3,5-triazine), 2-(4-(N-phenylbenzoimidazol-1-yl)phenyl)-9,10-dinaphthylanthracene, TPBi (1,3,5-Tri(1-phenyl-1H-benzo[d]imidazol-2-yl)benzene), BCP (2,9-Dimethyl-4,7-diphenyl-1,10-phenanthroline), Bphen (4,7-Diphenyl-1,10-phenanthroline), It may include TAZ(3-(4-Biphenylyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole), NTAZ(4-(Naphthalen-1-yl)-3,5-diphenyl-4H-1,2,4-triazole), tBu-PBD(2-(4-Biphenylyl)-5-(4-tert-butylphenyl)-1,3,4-oxadiazole), BAlq(Bis(2-methyl-8-quinolinolato-N1,O8)-(1,1'-Biphenyl-4-olato)aluminum), Bebq2(berylliumbis(benzoquinolin-10-olate)), ADN(9,10-di(naphthalene-2-yl)anthracene), BmPyPhB(1,3-Bis[3,5-di(pyridin-3-yl)phenyl]benzene) and mixtures thereof.

[0168] In addition, each of the electron transport regions (ETR1, ETR2, ETR3, and ETR4) may include a halogenated metal such as LiF, NaCl, CsF, RbCl, RbI, CuI, and KI, a lanthanide metal such as Yb, and a co-deposition material of the halogenated metal and the lanthanide metal. For example, the electron transport regions (ETR1, ETR2, ETR3, and ETR4) may include KI:Yb, RbI:Yb, and the like as the co-deposition material. The electron transport regions (ETR1, ETR2, ETR3, and ETR4) may include two or more materials selected from Mg, Ag, Yb, and Al. For example, the electron transport regions (ETR1, ETR2, ETR3, and ETR4) may include Mg and Yb.

[0169] Meanwhile, the electron transport regions (ETR1, ETR2, ETR3, ETR4) may use metal oxides such as Li2O, BaO, or Liq (8-hydroxyl-Lithium quinolate), but the embodiment is not limited thereto. Each of the electron transport regions (ETR1, ETR2, ETR3, ETR4) may also be formed of a material in which an electron transport material and an insulating organometal salt are mixed. The organometal salt may be a material having an energy band gap of approximately 4 eV or more. Specifically, for example, the organometal salt may include metal acetate, metal benzoate, metal acetoacetate, metal acetylacetonate, or metal stearate.

[0170] Each of the electron transport regions (ETR1, ETR2, ETR3, ETR4) may further include at least one of BCP (2,9-dimethyl-4,7-diphenyl-1,10-phenanthroline) and Bphen (4,7-diphenyl-1,10-phenanthroline) in addition to the aforementioned materials, but the embodiments are not limited thereto.

[0171] The electron transport regions (ETR1, ETR2, ETR3, ETR4) may include the compounds of the electron transport regions described above in the electron injection layer or the electron transport layer. When the electron transport regions (ETR1, ETR2, ETR3, ETR4) include an electron-side additional layer, the electron-side additional layer may include the above-described material. In one embodiment, the electron injection layer (EIL4) may be composed of two or more materials selected from Mg, Ag, Yb, and Al. The electron injection layer (EIL4) may be composed of a mixture of Mg and Yb, for example.

[0172] The thickness of each of the electron transport regions (ETR1, ETR2, ETR3, and ETR4) may be, for example, about 10 nm to about 150 nm. The thickness of the electron transport layer may be, for example, about 0.1 nm to about 100 nm, for example, about 0.3 nm to about 50 nm. When the thickness of the electron transport layer satisfies the range described above, satisfactory electron transport characteristics can be obtained without a substantial increase in driving voltage.

[0173] The second electrode (EL2) is provided on a plurality of light-emitting stacks (ST1, ST2, ST3, ST4). The second electrode (EL2) may be a common electrode. The second electrode (EL2) may be a cathode or an anode, but the embodiment is not limited thereto. For example, when the first electrode (EL1) is an anode, the second electrode (EL2) may be a cathode, and when the first electrode (EL1) is a cathode, the second electrode (EL2) may be an anode.

[0174] The second electrode (EL2) may be a semi-transmissive electrode or a transmissive electrode. When the second electrode (EL2) is a transmissive electrode, the second electrode (EL2) may be made of a transparent metal oxide, for example, ITO (indium tin oxide), IZO (indium zinc oxide), ZnO (zinc oxide), ITZO (indium tin zinc oxide), etc.

[0175] When the second electrode (EL2) is a semi-transmissive electrode or a reflective electrode, the second electrode (EL2) may include Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, Yb, W, In, Zn, Sn, or a compound or mixture including these (for example, AgMg, AgYb, or MgAg). Alternatively, the second electrode (EL2) may have a multi-layer structure including a reflective film or a semi-transmissive film formed of the above material and a transparent conductive film formed of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), or the like. For example, the second electrode (EL2) may include the above-described metal material, a combination of two or more metal materials selected from the above-described metal materials, or an oxide of the above-described metal materials.

[0176] Although not shown, the second electrode (EL2) may be connected to an auxiliary electrode. When the second electrode (EL2) is connected to the auxiliary electrode, the resistance of the second electrode (EL2) may be reduced.

[0177] Meanwhile, a capping layer (CPL) may be further disposed on the second electrode (EL2) of the light emitting element (LED) of one embodiment. The capping layer (CPL) may include a multilayer or a single layer.

[0178] In one embodiment, the capping layer (CPL) may be an organic layer or an inorganic layer. For example, when the capping layer (CPL) includes an inorganic material, the inorganic material may be an alkali metal compound such as LiF, an alkaline earth metal compound such as MgF2, SiON, SiN. X , SiOy, etc.

[0179] For example, when the capping layer (CPL) includes an organic material, the organic material may include α-NPD, NPB, TPD, m-MTDATA, Alq3, CuPc, TPD15 (N4,N4,N4',N4'-tetra (biphenyl-4-yl) biphenyl-4,4'-diamine), TCTA (4,4',4"- Tris (carbazol sol-9-yl) triphenylamine), etc., or may include an acrylate such as an epoxy resin or a methacrylate.

[0180] Meanwhile, the refractive index of the capping layer (CPL) may be 1.6 or greater. Specifically, the refractive index of the capping layer (CPL) may be 1.6 or greater for light in the wavelength range of 550 nm or greater and 660 nm or less.

[0181] Referring again to FIG. 4A, in the light emitting element (LED) of one embodiment, the electron control layer (ETR) may be disposed between the light emitting layer (EML) and the second electrode (EL2). The electron control layer (ETR) may include at least one of an electron injection layer, an electron transport layer, and a hole blocking layer. Referring to FIG. 4A, the electron control layer (ETR) may be disposed as a common layer so as to overlap the entire light emitting areas (EA1, EA2, EA3) and the pixel defining layer (PDL) that separates the light emitting areas (EA1, EA2, EA3). However, the embodiment is not limited thereto, and the electron control layer (ETR) may be patterned and provided so as to be disposed separately corresponding to each of the light emitting areas (EA1, EA2, EA3).

[0182] The second electrode (EL2) is provided on the electronic control layer (ETR). The second electrode (EL2) may be a common electrode. The second electrode (EL2) may be a cathode or an anode, but the embodiment is not limited thereto. For example, when the first electrode (EL1) is an anode, the second electrode (EL2) may be a cathode, and when the first electrode (EL1) is a cathode, the second electrode (EL2) may be an anode. The second electrode (EL2) may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0183] The encapsulation layer (TFE) may be disposed on the light emitting element (LED). For example, in one embodiment, the encapsulation layer (TFE) may be disposed on the second electrode (EL2). In addition, when the light emitting element (LED) includes a capping layer (not shown), the encapsulation layer (TFE) may be disposed on the capping layer (not shown). As described above, the encapsulation layer (TFE) may include at least one organic film and at least one inorganic film, and the inorganic films and the organic films may be disposed alternately.

[0184] A display panel (DP) of one embodiment may include an optical structure layer (OSL) disposed on a display element layer (DP-LED). The optical structure layer (OSL) may include a light control layer (CCL), a color filter layer (CFL), and a base layer (BL).

[0185] A portion of the light control layer (CCL) may include a light converter. The light converter may be a quantum dot or a phosphor, etc. The light converter may convert the wavelength of the light provided and emit it. That is, the light control layer (CCL) may be a layer including quantum dots at least in a portion or a layer including a phosphor.

[0186] The optical control layer (CCL) may include a plurality of optical control patterns (CCP-B, CCP-R, CCP-G). The optical control patterns (CCP-B, CCP-R, CCP-G) may be spaced apart from each other. The optical control patterns (CCP-B, CCP-R, CCP-G) may be arranged spaced apart from each other by banks (BMP).

[0187] The optical control patterns (CCP-B, CCP-R, CCP-G) may be arranged within bank openings (BOH1, BOH2, BOH3) defined in the bank (BMP). However, the embodiment is not limited thereto. In Fig. 4a, the bank (BMP) has a polygonal shape in cross-section and is illustrated as not overlapping with the optical control patterns (CCP-B, CCP-R, CCP-G). However, some edges of the optical control patterns (CCP-B, CCP-R, CCP-G) may overlap at least partly with the bank (BMP). For example, the edge of the second optical control pattern (CCP-R) may be arranged to overlap with the bank (BMP) in a plane.

[0188] A bank (BMP) may include a base resin and additives. The base resin may be composed of various resin compositions, which may be generally referred to as a binder. The additives may include a coupling agent and / or a photoinitiator. The additives may further include a dispersant.

[0189] In one embodiment, the bank (BMP) included in the light control layer (CCL) is optically transparent. The bank (BMP) may include an optically transparent material. The base resin included in the bank (BMP) may be optically transparent. The bank (BMP) may include a material having a transmittance of 85% or more in the visible light range. The bank (BMP) may not include a separate coloring agent. The bank (BMP) may include a black dye or black pigment mixed into the base resin. In one embodiment, the bank (BMP) may not include a light-blocking material having a black color, such as carbon black, or a pigment or dye having a blue color, etc.

[0190] A portion of the bank (BMP) overlaps at least some of the light control patterns (CCP-B, CCP-R, CCP-G) in a planar manner. As illustrated in FIG. 4A, a portion of the bank (BMP) overlaps the first light control pattern (CCP-B) in a planar manner. A portion of the bank (BMP) may overlap the third light control pattern (CCP-G) in a planar manner. A portion of the bank (BMP) may be disposed on the first light control pattern (CCP-B) and the third light control pattern (CCP-G). In the light control layer (CCL) of one embodiment, the bank (BMP) includes a transparent material and may overlap the first light control pattern (CCP-B) and the third light control pattern (CCP-G) formed through a photoresist process in a planar manner.

[0191] In a display panel (DP) according to one embodiment, a step may occur between a top surface of a bank (BMP) and top surfaces of light control patterns (CCP-B, CCP-R, CCP-G). That is, the top surface of the bank (BMP) may be defined to be higher than top surfaces of at least some of the light control patterns (CCP-B, CCP-R, CCP-G). The height difference between the top surface of the bank (BMP) and the top surfaces of the light control patterns (CCP-B, CCP-R, CCP-G) may be, for example, about 2 μm to about 3 μm.

[0192] The light control pattern (CCP-B, CCP-R, CCP-G) may be a portion that converts the wavelength of light provided from the display element layer (DP-LED) or transmits the provided light.

[0193] The light control layer (CCL) may include a first light control pattern (CCP-B) that provides blue light as the first light, a second light control pattern (CCP-R) that provides red light as the second light, and a third light control pattern (CCP-G) that provides green light as the third light. The light control layer (CCL) may include a first light control pattern (CCP-B) that transmits source light provided from a light-emitting element (LED), i.e., first light, a second light control pattern (CCP-R) that converts the source light into second light, and a third light control pattern (CCP-G) that transmits third light.

[0194] Some of the light control patterns (CCP-B, CCP-R, CCP-G) may be formed by an inkjet process. In one embodiment, the second light control pattern (CCP-R) may be formed by an inkjet process. A liquid ink composition may be provided inside the second bank opening (BOH2), and the provided ink composition may be polymerized by a thermal curing process or a photocuring process to form the second light control pattern (CCP-R).

[0195] The remaining light control patterns (CCP-B, CCP-R, CCP-G) may be formed by a photoresist process. In one embodiment, the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may be formed by a photoresist process. After a photoresist composition is provided at least within each of the first bank opening (BOH1) and the third bank opening (BOH3), the provided photoresist composition may be cured to form the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0196] Some of the light control patterns (CCP-B, CCP-R, CCP-G) may include quantum dots that convert source light into light of a specific wavelength. The second light control pattern (CCP-R) may include a first quantum dot (QD1) that converts source light into light of a second wavelength, as described above.

[0197] Each of the light control patterns (CCP-B, CCP-R, CCP-G) may further include a scatterer (SP). The second light control pattern (CCP-R) may include a first quantum dot (QD1) and a scatterer (SP), and each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may not include a quantum dot but include a scatterer (SP). Each of the first light control pattern (CCP-B), the second light control pattern (CCP-R), and the third light control pattern (CCP-G) may further include a base resin (BR1, BR2, BR3) that disperses the quantum dot (QD1) and the scatterer (SP). Meanwhile, each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may include a photosensitive resin since it is formed through a photoresist process as described below.

[0198] The light control layer (CCL) includes a metal pattern (MSP). A portion of the metal pattern (MSP) may overlap with a bank (BMP) in a plan view. The metal pattern (MSP) is disposed between at least a first light control pattern (CCP-B) and a second light control pattern (CCP-R). The metal pattern (MSP) may be disposed between the second light control pattern (CCP-R) and a third light control pattern (CCP-G). A portion of the metal pattern (MSP) may overlap with at least a portion of the first light control pattern (CCP-B) and the second light control pattern (CCP-R) in a plan view. The metal pattern (MSP) may be disposed between adjacent light control patterns (CCP-B, CCP-R, CCP-G) along a first direction (DR1) to prevent color mixing between the adjacent light control patterns (CCP-B, CCP-R, CCP-G).

[0199] The metal pattern (MSP) includes a reflective metal. The metal pattern (MSP) may include a highly reflective metal. For example, the metal pattern (MSP) may include highly reflective Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg).

[0200] The light control layer (CCL) may include a first barrier layer (CAP1) disposed on one surface of the light control patterns (CCP-B, CCP-R, CCP-G). The light control layer (CCL) may include a first barrier layer (CAP1) spaced apart from the display element layer (DP-LED) with the light control patterns (CCP-B, CCP-R, CCP-G) interposed therebetween, and a second barrier layer (CAP2) adjacent to the display element layer (DP-LED).

[0201] The first barrier layer (CAP1) may be arranged to follow the steps of the bank (BMP) and the light control patterns (CCP-B, CCP-R, CCP-G). The first barrier layer (CAP1) may be arranged directly under the filling layer (FML).

[0202] In a display panel (DP), an optical structure layer (OSL) includes a color filter layer (CFL) disposed on a light control layer (CCL). The color filter layer (CFL) may include color filters (CF1, CF2, CF3). The color filter layer (CFL) may include a first color filter (CF1) that transmits first light, a second color filter (CF2) that transmits second light, and a third color filter (CF3) that transmits source light. In one embodiment, the first color filter (CF1) may be a red filter, the second color filter (CF2) may be a green filter, and the third color filter (CF3) may be a blue filter.

[0203] Each of the color filters (CF1, CF2, CF3) includes a polymer photosensitive resin and a colorant. The first color filter (CF1) may include a blue colorant, the second color filter (CF2) may include a red colorant, and the third color filter (CF3) may include a green colorant. The first color filter (CF1) may include a blue pigment or a blue dye, the second color filter (CF2) may include a red pigment or a red dye, and the third color filter (CF3) may include a green pigment or a green dye.

[0204] Each of the first to third color filters (CF1, CF2, CF3) may be arranged to correspond to each of the first pixel area (PXA-B), the second pixel area (PXA-R), and the third pixel area (PXA-G). In addition, each of the first to third color filters (CF1, CF2, CF3) may be arranged to correspond to each of the first light control patterns (CCP-B, CCP-R, CCP-G).

[0205] In addition, a plurality of color filters (CF1, CF2, CF3) that transmit different light may be overlapped and arranged corresponding to the peripheral area (NPXA) arranged between the pixel areas (PXA-B, PXA-R, PXA-G). A plurality of color filters (CF1, CF2, CF3) may be overlapped and arranged in the third direction (DR3), which is the thickness direction, to distinguish the boundary between adjacent light-emitting areas (PXA-B, PXA-R, PXA-G). Meanwhile, unlike the drawing, the color filter layer (CFL) may include a light-shielding portion (not shown) that distinguishes the boundary between adjacent color filters (CF1, CF2, CF3). The light-shielding portion (not shown) may be formed by including a blue filter, or an organic light-shielding material including a black pigment or a black dye, or an inorganic light-shielding material.

[0206] The optical structure layer (OSL) may include a filler layer (FML) disposed between a light control layer (CCL) and a color filter layer (CFL). The filler layer (FML) may be disposed between light control patterns (CCP-B, CCP-R, CCP-G) and color filters (CF1, CF2, CF3). The filler layer (FML) may be disposed on the light control layer (CCL) to block the light control patterns (CCP-B, CCP-R, CCP-G) from being exposed to moisture / oxygen. In addition, the filler layer (FML) may be disposed between the light control patterns (CCP-B, CCP-R, CCP-G) and the color filters (CF1, CF2, CF3) to increase light extraction efficiency or may function as an optical functional layer to prevent reflected light from being incident on the light control layer (CCL). The fill layer (FML) may be a layer with a lower refractive index compared to other adjacent layers.

[0207] In one embodiment, the optical structure layer (OSL) may further include a base layer (BL) disposed on the color filter layer (CFL). The base layer (BL) may be a member that provides a base surface on which the color filter layer (CFL) and the light control layer (CCL) are disposed. The base layer (BL) may be a glass substrate, a metal substrate, a plastic substrate, or the like. However, the embodiment is not limited thereto, and the base layer (BL) may be an inorganic layer, an organic layer, or a composite material layer. In addition, unlike the embodiment illustrated, the base layer (BL) may be omitted in one embodiment.

[0208] FIGS. 4b to 4d each illustrate a display panel (DP) of one embodiment illustrated in FIG. 4a and display panels (DP-1, DP-2, DP-3) of other embodiments.

[0209] Referring to FIG. 4B, a display panel (DP-1) according to one embodiment may include a lower panel including a base substrate (BS), a circuit element layer (DP-CL) disposed on the base substrate (BS), and a display element layer (DP-LED) disposed on the circuit element layer (DP-CL), and an optical structure layer (OSL-1) disposed on the lower panel. The optical structure layer (OSL-1) may include a light control layer (CCL-1), a color filter layer (CFL-1), and a base layer (BL).

[0210] A display panel (DP-1) according to one embodiment includes a lower panel including a display element layer (DP-LED) and an upper panel (optical structure layer, OSL-1) including a light control layer (CCL) and a color filter layer (CFL), and in one embodiment, a filling layer (FML-1) may be disposed between the lower panel and the upper panel (OSL-1).

[0211] In one embodiment, the charging layer (FML-1) may be a charging layer between the display element layer (DP-LED) and the light control layer (CCL-1). The charging layer (FML-1) may be directly disposed on the encapsulation layer (TFE), and the second barrier layer (CAP2) may be directly disposed on the charging layer (FML-1). The lower surface of the charging layer (FML-1) may be in contact with the upper surface of the encapsulation layer (TFE), and the upper surface of the charging layer (FML-1) may be in contact with the lower surface of the first barrier layer (CAP1).

[0212] The filling layer (FML-1) can function as a buffer between the display element layer (DP-LED) and the light control layer (CCL-1). In one embodiment, the filling layer (FML-1) can have a shock absorption function, etc., and can increase the strength of the display panel (DP-1). The filling layer (FML-1) can be formed from a filling resin including a polymer resin. For example, the filling layer (FML-1) can be formed from a filling layer resin including an acrylic resin or an epoxy resin.

[0213] Compared to the display panel (DP) illustrated in FIG. 4a, the display panel (DP-1) according to an embodiment illustrated in FIG. 4b is an example in which a charging layer (FML-1) is disposed between a display element layer (DP-LED) and a light control layer (CCL-1). That is, in the display panel (DP-1) of FIG. 4b, the lower panel may be formed such that a circuit element layer (DP-CL) and a display element layer (DP-LED) are sequentially formed on one surface of a base substrate (BS) as a base surface, and the upper panel (optical structure layer, OSL-1) may be formed such that a color filter layer (CFL) and a light control layer (CCL-1) are sequentially formed on one surface of a base layer (BL) as a base surface, and then the lower panel and the upper panel are joined with the charging layer (FML-1) therebetween.

[0214] In a display panel (DP-1) according to one embodiment, a step may occur between a lower surface of a bank (BMP) and lower surfaces of light control patterns (CCP-B, CCP-R, CCP-G). That is, the lower surface of the bank (BMP) may be defined lower than the lower surfaces of the light control patterns (CCP-B, CCP-R, CCP-G). The height difference between the lower surface of the bank (BMP) and the lower surfaces of the light control patterns (CCP-B, CCP-R, CCP-G) may be, for example, about 2 μm to about 3 μm.

[0215] The first barrier layer (CAP1) may be arranged to follow the steps of the bank (BMP) and the light control patterns (CCP-B, CCP-R, CCP-G). The first barrier layer (CAP1) may be arranged directly on top of the filling layer (FML-1).

[0216] A display panel (DP-1) of one embodiment may include a low-refractive-index layer (LR). The low-refractive-index layer (LR) may be disposed between a light control layer (CCL-1) and a color filter layer (CFL). The low-refractive-index layer (LR) may be disposed on the light control layer (CCL-1) to block the light control patterns (CCP-B, CCP-R, CCP-G) from being exposed to moisture / oxygen. In addition, the low-refractive-index layer (LR) may be disposed between the light control patterns (CCP-B, CCP-R, CCP-G) and the color filters (CF1, CF2, CF3) to increase light extraction efficiency or may function as an optical functional layer to prevent reflected light from entering the light control layer (CCL-1). The low-refractive-index layer (LR) may be a layer having a lower refractive index than an adjacent layer.

[0217] The low-refractive-index layer (LR) may include at least one inorganic layer. For example, the low-refractive-index layer (LR) may include silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, titanium oxide, tin oxide, cerium oxide, and silicon oxynitride, or a metal thin film having secured light transmittance. However, the embodiment is not limited thereto, and the low-refractive-index layer (LR) may include an organic film. The low-refractive-index layer (LR) may have a structure in which a plurality of hollow particles are dispersed in an organic polymer resin, for example. The low-refractive-index layer (LR) may be composed of a single layer or a plurality of layers.

[0218] Referring to FIG. 4C, a display panel (DP-2) according to one embodiment may include a lower panel including a base substrate (BS), a circuit element layer (DP-CL) disposed on the base substrate (BS), and a display element layer (DP-LED) disposed on the circuit element layer (DP-CL), and an optical structure layer (OSL-2) disposed on the lower panel. In the display panel (DP-2) according to one embodiment, the optical structure layer (OSL-2) may include a light control layer (CCL), a low-refractive layer (LR-1), a color filter layer (CFL-1), and a base layer (BL-1) sequentially laminated on a thin film encapsulation layer (TFE). The optical structure layer (OSL-2) may include a first barrier layer (CAP1) and a second barrier layer (CAP2) disposed on the upper and lower surfaces of the light control layer (CCL).

[0219] A light control layer (CCL) may be disposed on a display element layer (DP-LED) and a thin film encapsulation layer (TFE) with a second barrier layer (CAP2) therebetween. The light control layer (CCL) may include a plurality of banks (BMP) and light control patterns (CCP-B, CCP-R, CCP-G) disposed between the banks (BMP). A low-refractive-index layer (LR-1) may be disposed on the light control layer (CCL).

[0220] The color filter layer (CFL-1) may include a plurality of color filters (CF1, CF2, CF3) and a light-shielding portion (BM).

[0221] Compared with the display panel (DP-1) illustrated in FIG. 4b, the display panel (DP-2) according to an embodiment illustrated in FIG. 4c is an example in which a light control layer (CCL), a low-refractive-index layer (LR-1), and a color filter layer (CFL-1) are arranged with the upper surface of a thin film encapsulation layer (TFE) as a base surface. That is, the light control patterns (CCP-B, CCP-R, CCP-G) of the light control layer (CCL) may be formed on the thin film encapsulation layer (TFE) through a continuous process, and the color filters (CF1, CF2, CF3) of the color filter layer (CFL-1) may be sequentially formed on the light control layer (CCL) through a continuous process. The color filter layer (CFL-1) is formed with the upper surface of the low-refractive-index layer (LR-1) as a base surface, and may have a different shape from that illustrated in FIGS. 4a and 4b.

[0222] In one embodiment of the color filter layer (CFL-1), the light-shielding portion (BM) may be a black matrix. The light-shielding portion (BM) may be formed by including an organic light-shielding material or an inorganic light-shielding material including a black pigment or black dye. The light-shielding portion (BM) may prevent light leakage and demarcate boundaries between adjacent color filters (CF1, CF2, CF3).

[0223] Referring to FIG. 4d, a display element layer (DP-LED1) included in a display panel (DP-3) of one embodiment includes a light-emitting element (LED-1), and the light-emitting element (LED-1) may be a micro LED element or a nano LED element. The light-emitting element (LED-1) may be disposed between pixel defining layers (PDLs) and may be electrically connected to a contact portion (SC), and the length and width of the light-emitting element (LED-1) may be between several hundred nanometers and several hundred micrometers. The light-emitting element (LED-1) may be an LED element including an active layer and at least one semiconductor material layer. The light-emitting element (LED-1) may further include an insulating layer covering surfaces of the active layer and the semiconductor material layer. The light-emitting element (LED-1) may be patterned and disposed to overlap each of the light-emitting areas (PXA-B, PXA-R, PXA-G). The display panel (DP) may include a buffer layer (BFL) disposed on the light-emitting element (LED-1). The buffer layer (BFL) may be disposed on the light-emitting element (LED-1) to cover the light-emitting element (LED-1). Meanwhile, in the display panel (DP-3) of one embodiment illustrated in FIG. 4D, the buffer layer (BFL) may be omitted.

[0224] FIGS. 6A to 6C are each an enlarged cross-sectional view of a portion of a configuration of a display panel according to one embodiment of the present invention. FIGS. 6A to 6C illustrate a cross-section corresponding to FIG. 4A, focusing on a configuration included in a light control layer (CCL, see FIG. 4A) of the display panel according to one embodiment.

[0225] Referring to FIGS. 2, 3, 4a, and 6a together, the light control layer (CCL) includes a plurality of light control patterns (CCP-B, CCP-R, CCP-G), a bank (BMP), and a metal pattern (MSP). The light control layer (CCL) may further include a first barrier layer (CAP1) and a second barrier layer (CAP2).

[0226] A light control layer (CCL) may be disposed on a base member (BSL). The base member (BSL) may be a member that provides a base surface on which the light control layer (CCL) is formed. The base member (BSL) may be the encapsulation layer (TFE) described above in FIG. 4a, or the low refractive index layer (LR) described above in FIG. 4b.

[0227] The optical control patterns (CCP-B, CCP-R, CCP-G) included in the optical control layer (CCL) may be spaced apart from each other. The optical control patterns (CCP-B, CCP-R, CCP-G) may be arranged spaced apart from each other by banks (BMP).

[0228] A bank (BMP) may include a base resin and additives. The base resin may be composed of various resin compositions, which may be generally referred to as a binder. The additives may include a coupling agent and / or a photoinitiator. The additives may further include a dispersant.

[0229] In one embodiment, the bank (BMP) included in the light control layer (CCL) is optically transparent. The bank (BMP) may include an optically transparent material. The base resin included in the bank (BMP) may be optically transparent. The bank (BMP) may include a material having a transmittance of 85% or more in the visible light range. The bank (BMP) may not include a separate coloring agent. The bank (BMP) may include a black dye or black pigment mixed into the base resin. In one embodiment, the bank (BMP) may not include a light-blocking material having a black color, such as carbon black, or a pigment or dye having a blue color, etc.

[0230] A bank aperture (BOH) may be defined in a bank (BMP). Optical control patterns (CCP-B, CCP-R, CCP-G) may be positioned within the bank apertures (BOH1, BOH2, BOH3) defined in the bank (BMP).

[0231] A portion of the bank (BMP) overlaps at least some of the light control patterns (CCP-B, CCP-R, CCP-G) in a planar manner. As illustrated in FIG. 6A, a portion of the bank (BMP) overlaps the first light control pattern (CCP-B) in a planar manner. A portion of the bank (BMP) may be disposed on the first light control pattern (CCP-B). The bank (BMP) may include a first portion (PP1) disposed on one surface of the first light control pattern (CCP-B), and a second portion (PP2) that does not overlap the first light control pattern (CCP-B) in a planar manner. The first portion (PP1) and the second portion (PP2) may have an integral shape. The first portion (PP1) and the second portion (PP2) may include the same material and may be formed through the same process. A portion of the bank (BMP) may overlap with the third light control pattern (CCP-G) in a plane. A portion of the bank (BMP) may be arranged on the upper portion of the third light control pattern (CCP-G). The bank (BMP) may include a first portion (PP1) arranged on one surface of the third light control pattern (CCP-G), and a second portion (PP2) that does not overlap with the third light control pattern (CCP-G) in a plane.

[0232] In the first direction (DR1), the first portion (PP1) may have a first width (W1), and the second portion (PP2) may have a second width (W2). The first width (W1) may be greater than the second width (W2). In one embodiment, the first width (W1) may be about 6 μm to about 9 μm. The second width (W2) may be about 1.5 μm to about 4.5 μm. The first width (W1) may be at least twice as large as the second width (W2). In the light control layer (CCL) of one embodiment, by designing the first width (W1) to be greater than the second width (W2), the aperture ratio of the bank (BMP) can be increased while securing a wide area in which the metal pattern (MSP) is arranged, so that the display efficiency of the display panel including the light control layer (CCL) can be improved.

[0233] In one embodiment of the light control layer (CCL), the bank (BMP) includes a transparent material and can overlap on a plane the first light control pattern (CCP-B) and the third light control pattern (CCP-G) formed through a photoresist process.

[0234] Some of the light control patterns (CCP-B, CCP-R, CCP-G) may be formed by an inkjet process. In one embodiment, the second light control pattern (CCP-R) may be formed by an inkjet process. A liquid ink composition may be provided inside the second bank opening (BOH2), and the provided ink composition may be polymerized by a thermal curing process or a photocuring process to form the second light control pattern (CCP-R).

[0235] The remaining light control patterns (CCP-B, CCP-R, CCP-G) may be formed by a photoresist process. In one embodiment, the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may be formed by a photoresist process. After a photoresist composition is provided at least within each of the first bank opening (BOH1) and the third bank opening (BOH3), the provided photoresist composition may be cured to form the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0236] In a display panel (DP) according to one embodiment, a step may occur between a top surface of a bank (BMP) and top surfaces of light control patterns (CCP-B, CCP-R, CCP-G). That is, the top surface of the bank (BMP) may be defined to be higher than top surfaces of at least some of the light control patterns (CCP-B, CCP-R, CCP-G). The bank (BMP) may have a thicker thickness than the first light control pattern (CCP-B) and the third light control pattern (CCP-G), so that the top surface of the bank (BMP) may be defined to be higher than top surfaces of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G). The upper surface of each of the first portion (PP1) and the second portion (PP2) of the bank (BMP) may be defined higher than the upper surface of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0237] Meanwhile, the second light control pattern (CCP-R) may have a greater thickness than each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G), and may have a thickness less than or equal to the thickness of the bank (BMP). As illustrated in FIG. 6a, the upper surface of the second light control pattern (CCP-R) may be defined to be higher than each of the upper surfaces of the first light control pattern (CCP-B) and the third light control pattern (CCP-G). The second light control pattern (CCP-R) may have a shape in which the thickness decreases from a portion adjacent to the bank (BMP) toward the center. The upper surface of the second light control pattern (CCP-R) may be defined to be the same height as the upper surface of the bank (BMP), or may be defined to be lower than the upper surface of the bank (BMP).

[0238] The second light control pattern (CCP-R) may include a first quantum dot (QD1) that converts source light into light of a second wavelength, as described above. Each of the light control patterns (CCP-B, CCP-R, CCP-G) may further include a scatterer (SP). The second light control pattern (CCP-R) may include the first quantum dot (QD1) and the scatterer (SP). Each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may not include a light-emitting body such as a quantum dot, but may include the scatterer (SP). Each of the first light control pattern (CCP-B), the second light control pattern (CCP-R), and the third light control pattern (CCP-G) may further include a base resin (BR1, BR2, BR3) that disperses the quantum dot (QD1) and the scatterer (SP). Meanwhile, since each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) is formed through a photoresist process, it may include a photosensitive resin. The first base resin (BR1) and the third base resin (BR3) included in each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) may be a photosensitive resin. The second base resin (BR2) included in the second light control pattern (CCP-R) may be an inkjet resin. The first base resin (BR1) and the third base resin (BR3) may include the same material. In one embodiment of the light control layer (CCL), the second light control pattern (CCP-R) corresponding to the red pixel area includes the first quantum dot (QD1) and is formed through an inkjet process, and the first light control pattern (CCP-B) and the third light control pattern (CCP-G) corresponding to the blue pixel area and the green pixel area, respectively, do not include quantum dots and can be formed through a photoresist process.

[0239] The light control layer (CCL) includes a metal pattern (MSP). A portion of the metal pattern (MSP) may overlap with the bank (BMP) on a plane. The metal pattern (MSP) may include a first metal pattern (MSP1) disposed between a first light control pattern (CCP-B) and a second light control pattern (CCP-R), and a second metal pattern (MSP2) disposed between the second light control pattern (CCP-R) and a third light control pattern (CCP-G).

[0240] A portion of the metal pattern (MSP) may overlap at least a portion of the first light control pattern (CCP-B) and the second light control pattern (CCP-R) on a plane. As illustrated in FIG. 6A, a portion of the metal pattern (MSP) may overlap the first light control pattern (CCP-B) on a plane. A portion of the metal pattern (MSP) may be disposed on the first light control pattern (CCP-B). A portion of the first metal pattern (MSP1) may be disposed on the first light control pattern (CCP-B).

[0241] A first metal pattern (MSP1) may be disposed between a first light control pattern (CCP-B) and a bank (BMP). The first metal pattern (MSP1) may be disposed adjacent to at least a side surface of the first light control pattern (CCP-B) and may be disposed between a second portion (PP2) and the first light control pattern (CCP-B) in the first direction (DR1). At least a portion of the first metal pattern (MSP1) may be in contact with the first light control pattern (CCP-B). A portion of the first metal pattern (MSP1) may be in contact with a side surface of the first light control pattern (CCP-B), and a portion of the first metal pattern (MSP1) may be in contact with a portion of an upper surface of the first light control pattern (CCP-B).

[0242] A portion of the metal pattern (MSP) may overlap with the third light control pattern (CCP-G) on a plane. A portion of the metal pattern (MSP) may be arranged on top of the third light control pattern (CCP-G). A portion of the second metal pattern (MSP2) may be arranged on top of the third light control pattern (CCP-G).

[0243] The second metal pattern (MSP2) may be disposed between the third light control pattern (CCP-G) and the bank (BMP). The second metal pattern (MSP2) may be disposed adjacent to at least a side surface of the third light control pattern (CCP-G) and may be disposed between the third light control pattern (CCP-G) and the second portion (PP2) in the first direction (DR1). At least a portion of the second metal pattern (MSP2) may be in contact with the third light control pattern (CCP-G). A portion of the second metal pattern (MSP2) may be in contact with a side surface of the third light control pattern (CCP-G), and a portion of the second metal pattern (MSP2) may be in contact with a portion of an upper surface of the third light control pattern (CCP-G).

[0244] Meanwhile, the metal pattern (MSP) may be provided as a single layer between the first light control pattern (CCP-B) and the second light control pattern (CCP-R). A first metal pattern (MSP1) provided as a single layer may be arranged between the first light control pattern (CCP-B) and the second light control pattern (CCP-R). With respect to the first direction (DR1), the first metal pattern (MSP1) may contact a side surface of the first light control pattern (CCP-B), the second portion (PP2) of the bank (BMP) may contact a side surface of the first metal pattern (MSP1), and the second light control pattern (CCP-R) may contact a side surface of the second portion (PP2). The metal pattern (MSP) may be provided as a single layer between the second light control pattern (CCP-R) and the third light control pattern (CCP-G). A second metal pattern (MSP2) provided as a single layer may be arranged between the second light control pattern (CCP-R) and the third light control pattern (CCP-G). With respect to the first direction (DR1), the second metal pattern (MSP2) may contact a side surface of the third light control pattern (CCP-G), the second portion (PP2) of the bank (BMP) may contact a side surface of the second metal pattern (MSP2), and the second light control pattern (CCP-R) may contact a side surface of the second portion (PP2).

[0245] The metal pattern (MSP) includes a reflective metal. The metal pattern (MSP) may include a highly reflective metal. For example, the metal pattern (MSP) may include highly reflective Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (e.g., a mixture of Ag and Mg).

[0246] The optical control layer (CCL) may further include a first barrier layer (CAP1) disposed on one surface of the optical control patterns (CCP-B, CCP-R, CCP-G) and a second barrier layer (CAP2) disposed on the other surface of the optical control patterns (CCP-B, CCP-R, CCP-G). The first barrier layer (CAP1) may be disposed to follow the steps of the bank (BMP) and the optical control patterns (CCP-B, CCP-R, CCP-G).

[0247] A light control layer (CCL) included in a display panel of one embodiment includes an optically transparent bank (BMP), and a portion of the bank (BMP) overlaps a first light control pattern (CCP-B) in a plane. Furthermore, the light control layer (CCL) of one embodiment includes a metal pattern (MSP) that overlaps at least a portion of the first light control pattern (CCP-B) and a second light control pattern (CCP-R) in a plane. In the display panel of one embodiment, the inclusion of the metal pattern (MSP) can improve the light conversion efficiency of the light control patterns (CCP-B, CCP-R, CCP-G), while having a structure in which the optically transparent bank (BMP) is disposed on a portion of an upper portion of the first light control pattern (CCP-B), thereby increasing the aperture ratio of the bank (BMP) and widening the area in which the metal pattern (MSP) is disposed. Accordingly, a display panel including a light control layer (CCL) can have high resolution while improving display efficiency.

[0248] Referring to FIG. 6B, unlike those illustrated in FIGS. 4A and 6A, the second light control pattern (CCP-G1) may include a second quantum dot (QD2). In the second light control pattern (CCP-G1), the second quantum dot (QD2) may convert source light into green light. The second quantum dot (QD2) may have a green emission color. The second pixel area corresponding to the second bank opening (BOH2) in which the second light control pattern (CCP-G1) is arranged may emit light having an emission wavelength of 520 nm or more and 600 nm or less.

[0249] In the light control layer (CCL-a) of one embodiment illustrated in FIG. 6b, the second light control pattern (CCP-G1) may include a second quantum dot (QD2) and a scatterer (SP), and each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) may not include a quantum dot but include a scatterer (SP). Each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) may not include a light-emitting body such as a quantum dot but include a scatterer (SP). Each of the first light control pattern (CCP-B), the second light control pattern (CCP-G1), and the third light control pattern (CCP-R1) may further include a base resin (BR1, BR2, BR3) that disperses the quantum dot (QD2) and the scatterer (SP). Meanwhile, since each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) is formed through a photoresist process, it may include a photosensitive resin. The first base resin (BR1) and the third base resin (BR3) included in each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) may be a photosensitive resin. The second base resin (BR2) included in the second light control pattern (CCP-G1) may be an inkjet resin. In the light control layer (CCL-a) of one embodiment, the second light control pattern (CCP-G1) corresponding to the green pixel area includes a second quantum dot (QD2) and is formed through an inkjet process, and the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) corresponding to the blue pixel area and the red pixel area do not include a quantum dot and may be formed through a photoresist process.

[0250] The optical control patterns (CCP-B, CCP-G1, CCP-R1) included in the optical control layer (CCL-a) may be spaced apart from each other. The optical control patterns (CCP-B, CCP-G1, CCP-R1) may be arranged spaced apart from each other by banks (BMP).

[0251] A bank aperture (BOH) may be defined in a bank (BMP). Optical control patterns (CCP-B, CCP-G1, CCP-R1) may be positioned within the bank aperture (BOH1, BOH2, BOH3) defined in the bank (BMP).

[0252] A portion of the bank (BMP) overlaps at least some of the light control patterns (CCP-B, CCP-G1, CCP-R1) in a plane. As illustrated in FIG. 6B, a portion of the bank (BMP) overlaps the first light control pattern (CCP-B) in a plane. A portion of the bank (BMP) may be disposed on the first light control pattern (CCP-B). The bank (BMP) may include a first portion (PP1) disposed on one surface of the first light control pattern (CCP-B), and a second portion (PP2) that does not overlap the first light control pattern (CCP-B) in a plane.

[0253] A portion of the bank (BMP) may overlap with the third light control pattern (CCP-R1) in a plane. A portion of the bank (BMP) may be arranged on the upper portion of the third light control pattern (CCP-R1). The bank (BMP) may include a first portion (PP1) arranged on one surface of the third light control pattern (CCP-R1), and a second portion (PP2) that does not overlap with the third light control pattern (CCP-R1) in a plane.

[0254] In one embodiment of the light control layer (CCL-a), the bank (BMP) includes a transparent material and can overlap on a plane with the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) formed through a photoresist process.

[0255] Some of the light control patterns (CCP-B, CCP-G1, CCP-R1) may be formed by an inkjet process. In one embodiment, the second light control pattern (CCP-G1) may be formed by an inkjet process. A liquid ink composition may be provided inside the second bank opening (BOH2), and the provided ink composition may be polymerized by a thermal curing process or a photocuring process to form the second light control pattern (CCP-G1).

[0256] The remaining light control patterns (CCP-B, CCP-G1, CCP-R1) may be formed by a photoresist process. In one embodiment, the first light control pattern (CCP-B) and the third light control pattern (CCP-R1) may be formed by a photoresist process. After a photoresist composition is provided at least within each of the first bank opening (BOH1) and the third bank opening (BOH3), the provided photoresist composition may be cured to form the first light control pattern (CCP-B) and the third light control pattern (CCP-R1).

[0257] In a display panel (DP) according to one embodiment, a step may occur between a top surface of a bank (BMP) and top surfaces of light control patterns (CCP-B, CCP-G1, CCP-R1). That is, a top surface of the bank (BMP) may be defined to be higher than top surfaces of at least some of the light control patterns (CCP-B, CCP-G1, CCP-R1). The bank (BMP) may have a thicker thickness than the first light control pattern (CCP-B) and the third light control pattern (CCP-R1), so that a top surface of the bank (BMP) may be defined to be higher than top surfaces of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1). The upper surface of each of the first portion (PP1) and the second portion (PP2) of the bank (BMP) may be defined higher than the upper surface of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1).

[0258] Meanwhile, the second light control pattern (CCP-G1) may have a greater thickness than each of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1), and may have a thickness less than or equal to the thickness of the bank (BMP). As illustrated in FIG. 6B, the upper surface of the second light control pattern (CCP-G1) may be defined higher than each of the upper surfaces of the first light control pattern (CCP-B) and the third light control pattern (CCP-R1). The second light control pattern (CCP-G1) may have a shape in which the thickness decreases from a portion adjacent to the bank (BMP) toward the center. The upper surface of the second light control pattern (CCP-G1) may be defined to have the same height as the upper surface of the bank (BMP), or may be defined to be lower than the upper surface of the bank (BMP).

[0259] The light control layer (CCL-a) includes a metal pattern (MSP). A portion of the metal pattern (MSP) may overlap with the bank (BMP) on a plane. The metal pattern (MSP) may include a first metal pattern (MSP1) disposed between a first light control pattern (CCP-B) and a second light control pattern (CCP-G1), and a second metal pattern (MSP2) disposed between the second light control pattern (CCP-G1) and a third light control pattern (CCP-R1).

[0260] A portion of the metal pattern (MSP) may overlap at least a portion of the first light control pattern (CCP-B) and the second light control pattern (CCP-G1) on a plane. As illustrated in FIG. 6B, a portion of the metal pattern (MSP) may overlap the first light control pattern (CCP-B) on a plane. A portion of the metal pattern (MSP) may be disposed on the first light control pattern (CCP-B). A portion of the first metal pattern (MSP1) may be disposed on the first light control pattern (CCP-B).

[0261] A first metal pattern (MSP1) may be disposed between a first light control pattern (CCP-B) and a bank (BMP). The first metal pattern (MSP1) may be disposed adjacent to at least a side surface of the first light control pattern (CCP-B) and may be disposed between a second portion (PP2) and the first light control pattern (CCP-B) in the first direction (DR1). At least a portion of the first metal pattern (MSP1) may be in contact with the first light control pattern (CCP-B). A portion of the first metal pattern (MSP1) may be in contact with a side surface of the first light control pattern (CCP-B), and a portion of the first metal pattern (MSP1) may be in contact with a portion of an upper surface of the first light control pattern (CCP-B).

[0262] A portion of the metal pattern (MSP) may overlap with the third light control pattern (CCP-R1) on a plane. A portion of the metal pattern (MSP) may be arranged on top of the third light control pattern (CCP-R1). A portion of the second metal pattern (MSP2) may be arranged on top of the third light control pattern (CCP-R1).

[0263] The second metal pattern (MSP2) may be disposed between the third light control pattern (CCP-R1) and the bank (BMP). The second metal pattern (MSP2) may be disposed adjacent to at least a side surface of the third light control pattern (CCP-R1) and may be disposed between the third light control pattern (CCP-R1) and the second portion (PP2) in the first direction (DR1). At least a portion of the second metal pattern (MSP2) may be in contact with the third light control pattern (CCP-R1). A portion of the second metal pattern (MSP2) may be in contact with the side surface of the third light control pattern (CCP-R1), and a portion of the second metal pattern (MSP2) may be in contact with a portion of an upper surface of the third light control pattern (CCP-R1).

[0264] Meanwhile, the metal pattern (MSP) may be provided as a single layer between the first light control pattern (CCP-B) and the second light control pattern (CCP-G1). The first metal pattern (MSP1) provided as a single layer may be arranged between the first light control pattern (CCP-B) and the second light control pattern (CCP-G1). With respect to the first direction (DR1), the first metal pattern (MSP1) may contact a side surface of the first light control pattern (CCP-B), the second portion (PP2) of the bank (BMP) may contact a side surface of the first metal pattern (MSP1), and the second light control pattern (CCP-G1) may contact a side surface of the second portion (PP2). The metal pattern (MSP) may be provided as a single layer between the second light control pattern (CCP-G1) and the third light control pattern (CCP-R1). A second metal pattern (MSP2) provided as a single layer may be arranged between the second light control pattern (CCP-G1) and the third light control pattern (CCP-R1). With respect to the direction opposite to the first direction (DR1), the second metal pattern (MSP2) may contact a side surface of the third light control pattern (CCP-R1), the second portion (PP2) of the bank (BMP) may contact a side surface of the second metal pattern (MSP2), and the second light control pattern (CCP-G1) may contact a side surface of the second portion (PP2).

[0265] The light control layer (CCL-a) may further include a first barrier layer (CAP1) disposed on one surface of the light control patterns (CCP-B, CCP-G1, CCP-R1) and a second barrier layer (CAP2) disposed on the other surface of the light control patterns (CCP-B, CCP-G1, CCP-R1). The first barrier layer (CAP1) may be disposed to follow the steps of the bank (BMP) and the light control patterns (CCP-B, CCP-G1, CCP-R1).

[0266] Referring to FIG. 6c, the light control layer (CCL-b) of one embodiment includes a bank (BMP'), and the bank (BMP') may include a first portion (PP1') disposed on one surface of a first light control pattern (CCP-B), and a second portion (PP2') that does not overlap with the first light control pattern (CCP-B) in a plane. The first portion (PP1') and the second portion (PP2') may have an integral shape. The first portion (PP1') and the second portion (PP2') may include the same material and may be formed through the same process. A portion of the bank (BMP') may overlap with the third light control pattern (CCP-G) in a plane. A portion of the bank (BMP') may be disposed on the third light control pattern (CCP-G). The bank (BMP') may include a first portion (PP1') disposed on one surface of the third light control pattern (CCP-G), and a second portion (PP2') that does not overlap with the third light control pattern (CCP-G) in a plane. The first portion (PP1') may be directly disposed on the upper surfaces of the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0267] In one embodiment, the light control layer (CCL-b) includes a metal pattern (MSP'), and a portion of the metal pattern (MSP') may overlap with the bank (BMP') on a plane. The metal pattern (MSP') may include a first metal pattern (MSP1') disposed between a first light control pattern (CCP-B) and a second light control pattern (CCP-R), and a second metal pattern (MSP2') disposed between the second light control pattern (CCP-R) and a third light control pattern (CCP-G).

[0268] A portion of the metal pattern (MSP') may overlap at least a portion of the first light control pattern (CCP-B) and the second light control pattern (CCP-R) on a plane. As illustrated in FIG. 6C, a portion of the metal pattern (MSP') may overlap the second light control pattern (CCP-R) on a plane. A portion of the metal pattern (MSP') may be disposed under the second light control pattern (CCP-R). A portion of each of the first metal pattern (MSP1') and the second metal pattern (MSP2') may be disposed under the second light control pattern (CCP-R).

[0269] A first metal pattern (MSP1') may be disposed between a second light control pattern (CCP-R) and a bank (BMP'). The first metal pattern (MSP1') may be disposed adjacent to at least a side surface of the second light control pattern (CCP-R) and may be disposed between a second portion (PP2') and the second light control pattern (CCP-R) in the first direction (DR1). A portion of the first metal pattern (MSP1') may be disposed on the second portion (PP2'). At least a portion of the first metal pattern (MSP1') may be in contact with the second light control pattern (CCP-R). A portion of the first metal pattern (MSP1') may be in contact with a side surface of the second light control pattern (CCP-R), and a portion of the first metal pattern (MSP1') may be in contact with a portion of an upper surface of the second portion (PP2').

[0270] The second metal pattern (MSP2') may be disposed between the second light control pattern (CCP-R) and the bank (BMP'). The second metal pattern (MSP2') may be disposed adjacent to at least a side surface of the second light control pattern (CCP-R) and may be disposed between the second light control pattern (CCP-R) and the second portion (PP2') in the first direction (DR1). A portion of the second metal pattern (MSP2') may be disposed on the second portion (PP2'). At least a portion of the second metal pattern (MSP2') may be in contact with the second light control pattern (CCP-R). A portion of the second metal pattern (MSP2') may be in contact with the side surface of the second light control pattern (CCP-R), and a portion of the second metal pattern (MSP2') may be in contact with a portion of an upper surface of the second portion (PP2').

[0271] Meanwhile, the metal pattern (MSP') may be provided as a single layer between the first light control pattern (CCP-B) and the second light control pattern (CCP-R). A first metal pattern (MSP1') provided as a single layer may be arranged between the first light control pattern (CCP-B) and the second light control pattern (CCP-R). With respect to the first direction (DR1), the first metal pattern (MSP1') may contact a side surface of the second light control pattern (CCP-R), the second portion (PP2') of the bank (BMP') may contact a side surface of the first metal pattern (MSP1'), and the first light control pattern (CCP-B) may contact a side surface of the second portion (PP2'). The metal pattern (MSP') may be provided as a single layer between the second light control pattern (CCP-R) and the third light control pattern (CCP-G). A second metal pattern (MSP2') provided as a single layer may be arranged between the second light control pattern (CCP-R) and the third light control pattern (CCP-G). With respect to the first direction (DR1), the second metal pattern (MSP2') may contact a side surface of the second light control pattern (CCP-R), the second portion (PP2') of the bank (BMP') may contact a side surface of the second metal pattern (MSP2'), and the third light control pattern (CCP-G) may contact a side surface of the second portion (PP2').

[0272] The metal pattern (MSP') includes a reflective metal. The metal pattern (MSP') may include a metal with high reflectivity. The metal pattern (MSP') may include, for example, highly reflective Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (for example, a mixture of Ag and Mg).

[0273] In the light control layer (CCL-b) of one embodiment, the bank (BMP') may further include a valley portion (BMP-VP). The valley portion (BMP-VP) may be adjacent to the first light control pattern (CCP-B) in the first direction (DR1) and may be a portion that is recessed in the thickness direction by removing a portion of the bank (BMP'). The width of the valley portion (BMP-VP) in the first direction (DR1) may be smaller than the width of each of the first to third bank openings (BOH1, BOH2, BOH3). The metal pattern (MSP') may further include a third metal pattern (MSP3') arranged on the inside of the valley portion (BMP-VP). The bank (BMP') of the light control layer (CCL-b) of one embodiment may further include the valley portion (BMP-VP) to prevent light leakage from occurring between adjacent light control patterns. More specifically, the valley portion (BMP-VP) can block light between the adjacent first light control pattern (CCP-B) and the third light control pattern (CCP-G), thereby preventing light leakage from occurring between the adjacent first light control pattern (CCP-B) and the third light control pattern (CCP-G). In the light control layer (CCL-b) of one embodiment, the light leakage from occurring between the adjacent light control patterns can be prevented by the third metal pattern (MSP3') disposed inside the valley portion (BMP-VP).

[0274] FIGS. 7A and 7B are each an enlarged plan view of a portion of a configuration of a display panel according to an embodiment of the present invention. FIG. 7A illustrates a planar shape of bank openings (BOHs) corresponding to each of the first to third pixel areas (PXA-B, PXA-R, PXA-G) included in one pixel unit (PXA-U) illustrated in FIG. 2. FIG. 7B illustrates a planar arrangement structure of a portion of a light control pattern corresponding to each of the first to third pixel areas (PXA-B, PXA-R, PXA-G) included in one pixel unit (PXA-U) illustrated in FIG. 2, and a metal pattern (MSP) and an additional metal pattern (MSP-a).

[0275] Referring to FIGS. 2, 4A, 7A, and 7B together, for the first to third bank openings BOH1, BOH2, and BOH3 corresponding to one pixel unit PXA-U, each of the first to third bank openings BOH1, BOH2, and BOH3 may have a rectangular shape having a short side SS1 extending in a first direction DR1 and a long side SS2 extending in a second direction DR2. The bank opening BOH may include an additional bank opening BOHa provided adjacent to the short side of at least one of the first to third bank openings BOH1, BOH2, and BOH3. The additional bank opening BOHa may be provided, for example, adjacent to the short side SS1 of the second bank opening BOH2. The additional bank opening (BOHa) may be provided parallel to the second bank opening (BOH2) in the second direction (DR2) and spaced apart from the second bank opening (BOH2) by a predetermined distance.

[0276] The first optical control pattern (CCP-B) and the third optical control pattern (CCP-G) may be provided corresponding to the first bank opening (BOH1) and the third bank opening (BOH3), respectively. The first optical control pattern (CCP-B) and the third optical control pattern (CCP-G) may be fully overlapped with the first bank opening (BOH1) and the third bank opening (BOH3), respectively, on a plane.

[0277] According to one embodiment, a light control layer (CCL) of a display panel (DP) may further include an additional light control pattern (CCP-ad) provided corresponding to an additional bank opening (BOHa). The additional light control pattern (CCP-ad) may include the same material as each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G), and may be formed in the same process as the process for forming the first light control pattern (CCP-B) and the third light control pattern (CCP-G). The additional light control pattern (CCP-ad) may be formed by a photoresist process and may include a photosensitive resin. The additional light control pattern (CCP-ad) may further include a scatterer.

[0278] The aforementioned metal pattern (MSP) can be arranged to follow the edges of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G) on a plane. The first metal pattern (MSP1) is arranged between at least the first bank opening (BOH1) and the second bank opening (BOH2), overlaps with at least a portion of the first light control pattern (CCP-B), and can be arranged to have a square ring shape on a plane along the edge of the first light control pattern (CCP-B). The second metal pattern (MSP2) is arranged between at least the second bank opening (BOH2) and the third bank opening (BOH3), overlaps with at least a portion of the third light control pattern (CCP-G), and can be arranged to have a square ring shape on a plane along the edge of the third light control pattern (CCP-G).

[0279] The light control layer (CCL) of one embodiment may further include an additional metal pattern (MSP-a). The additional metal pattern (MSP-a) may be arranged to follow the edge of the additional light control pattern (CCP-ad) on a plane. The additional metal pattern (MSP-a) is arranged between at least the second bank opening (BOH2) and the additional bank opening (BOHa), overlaps at least a portion of the additional light control pattern (CCP-ad), and may be arranged to have a square ring shape on a plane along the edge of the additional light control pattern (CCP-ad). The additional light control pattern (CCP-ad) and the additional metal pattern (MSP-a) may be provided to prevent color mixing between pixel units (PXA-U) that are arranged adjacently along the second direction (DR2).

[0280] Below, a method for manufacturing a display panel according to one embodiment of the present invention is described.

[0281] FIG. 8A is a flowchart illustrating a method for manufacturing a display panel according to an embodiment of the present invention. FIG. 8B is a flowchart illustrating some steps of a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 9A to 9E are cross-sectional views illustrating some steps of a method for manufacturing a display panel according to an embodiment of the present invention. FIGS. 9A to 9E briefly illustrate some steps of a step of forming an optical structure layer in a method for manufacturing a display panel according to an embodiment.

[0282] Referring to FIG. 8A, a method for manufacturing a display panel according to one embodiment includes a step of preparing a display element layer including a light-emitting element that outputs source light (S100), and a step of forming an optical structure layer (S200) on the light-emitting element. The step of forming the optical structure layer in the method for manufacturing a display panel according to one embodiment includes a step of forming a first light control pattern by patterning a photosensitive material (S210), a step of forming a metal pattern by depositing and then patterning a reflective metal layer, a step of forming an optically transparent preliminary bank layer and then patterning the same to form a bank including a first bank opening exposing a portion of the first light control pattern and a second bank opening adjacent to the first bank opening along a first direction (S230), and a step of forming a second light control pattern in the second bank opening through an inkjet process (S240).

[0283] Referring to FIGS. 8B, 9A, and 9B, a method for manufacturing a display panel according to one embodiment includes a step (S210) of forming a first light control pattern by patterning a first preparatory layer (CCL-p) including a photosensitive material. The first preparatory layer (CCL-p) includes a base resin (BR-a) including a photosensitive resin and a scatterer (SP). The first preparatory layer (CCL-p) may be formed by applying a photoresist material including a base resin (BR-a) including a photosensitive resin and a scatterer (SP). The first preparatory layer (CCL-p) may be provided over the entire surface of the base member (BSL) and the second barrier layer (CAP2), and an uncured portion may be removed after an exposure process that provides light (L) to form the first light control pattern (CCP-B). Meanwhile, in the step of patterning the first preparatory layer (CCL-p), a mask (MSK) may be provided to perform an exposure process only on a portion. The mask (MSK) includes a mask opening (MSK-OP) that overlaps a portion of the first preparatory layer (CCL-p) on a plane, and light (L) may be irradiated to a portion of the first preparatory layer (CCL-p) exposed by the mask opening (MSK-OP). The mask (MSK) may be disposed on the first preparatory layer (CCL-p) and may be spaced apart from the first preparatory layer (CCL-p). The mask opening (MSK-OP) may be provided corresponding to a portion where light control patterns (CCP-B, CCP-G) are to be formed. The first preparatory layer (CCL-p) can be provided over the entire surface of the base member (BSL), and after an exposure process that provides light (L), an uncured portion is removed to form the first light control pattern (CCP-B) and the third light control pattern (CCP-G).In FIG. 9b, an example is illustrated in which light (L) is irradiated to the first preliminary layer (CCL-p) corresponding to the portion where the first light control pattern (CCP-B) and the third light control pattern (CCP-G) are to be formed, thereby curing the first preliminary layer (CCL-p), that is, the base resin (BR-a) includes a negative photoresist. However, the present invention is not limited thereto, and the base resin (BR-a) of the first preliminary layer (CCL-p) may include a positive photoresist that is irradiated with light in the remaining portions except for the portions where the first light control pattern (CCP-B) and the third light control pattern (CCP-G) are to be formed.

[0284] Referring to FIGS. 8B, 9B, and 9C, a method for manufacturing a display panel according to one embodiment includes a step (S220) of forming a metal pattern (MSP) by depositing a reflective metal layer and then patterning the deposited reflective metal layer. The metal pattern (MSP) may include a first metal pattern (MSP1) and a second metal pattern (MSP2). A portion of the first metal pattern (MSP1) may be disposed on the first light control pattern (CCP-B). A portion of the first metal pattern (MSP1) may contact a side surface of the first light control pattern (CCP-B), and a portion of the first metal pattern (MSP1) may contact a portion of an upper surface of the first light control pattern (CCP-B). A portion of the second metal pattern (MSP2) may be disposed on the third light control pattern (CCP-G). A portion of the second metal pattern (MSP2) may contact a side surface of the third light control pattern (CCP-G), and a portion of the second metal pattern (MSP2) may contact a portion of the upper surface of the third light control pattern (CCP-G). The metal pattern (MSP) may be provided as a single layer that covers a portion of the side surface and the upper surface of each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0285] The metal pattern (MSP) can be formed of a reflective metal. The metal pattern (MSP) can be formed by patterning a metal monolayer formed by depositing a highly reflective metal. The metal pattern (MSP) can be formed of, for example, highly reflective Ag, Mg, Cu, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Li, Ca, LiF / Ca, LiF / Al, Mo, Ti, W, In, Zn, Sn, or compounds or mixtures thereof (for example, a mixture of Ag and Mg).

[0286] Referring to FIGS. 8b, 9c and 9d, a method for manufacturing a display panel according to one embodiment includes a step (S230) of forming an optically transparent preliminary bank layer and then patterning the formed bank layer to form a first bank opening (BOH1) exposing a portion of a first light control pattern (CCP-B) and a second bank opening (BOH2) adjacent to the first bank opening (BOH1) along a first direction (DR1).

[0287] A first bank opening (BOH1), a second bank opening (BOH2), and a third bank opening (BOH3) are formed in the bank (BMP). The bank (BMP) can be formed by patterning each of the first bank opening (BOH1), the second bank opening (BOH2), and the third bank opening (BOH3) after an optically transparent preliminary bank layer is formed. The preliminary bank layer can be formed to cover each of the first light control pattern (CCP-B) and the third light control pattern (CCP-G).

[0288] As illustrated in FIG. 9d, a portion of the bank (BMP) is formed to overlap the first light control pattern (CCP-B) in a plane. A portion of the bank (BMP) may be formed on the upper portion of the first light control pattern (CCP-B). The bank (BMP) may include a first portion (PP1) disposed on one surface of the first light control pattern (CCP-B), and a second portion (PP2) that does not overlap the first light control pattern (CCP-B) in a plane. The first portion (PP1) and the second portion (PP2) may have an integral shape. The first portion (PP1) and the second portion (PP2) may include the same material and may be formed through the same process.

[0289] A portion of the bank (BMP) may be formed to overlap with the third light control pattern (CCP-G) on a plane. A portion of the bank (BMP) may be formed on the upper portion of the third light control pattern (CCP-G). The bank (BMP) may include a first portion (PP1) disposed on one surface of the third light control pattern (CCP-G), and a second portion (PP2) that does not overlap with the third light control pattern (CCP-G) on a plane.

[0290] Meanwhile, in FIGS. 9b to 9d, a method for manufacturing a display panel according to one embodiment exemplarily illustrates that a metal pattern (MSP) is formed first and then a bank (BMP) covering at least a portion of the metal pattern (MSP) is formed. However, this is not limited thereto, and the order of forming the metal pattern (MSP) and the bank (BMP) may be changed. That is, unlike FIGS. 9b to 9d, the bank (BMP) may be formed first and then a metal pattern (MSP', see FIG. 6c) covering a portion of the bank (BMP) may be formed. When the bank (BMP) is formed first and the metal pattern (MSP', see FIG. 6c) is formed later, as illustrated in FIG. 6c, the metal pattern (MSP') may be formed to cover a portion of the side and upper surface of the second portion (PP2) of the bank (BMP).

[0291] Referring to FIGS. 8b, 9d, and 9e, a method for manufacturing a display panel according to one embodiment includes a step (S240) of forming a second light control pattern (CCP-R) in a second bank opening (BOH2) through an inkjet process.

[0292] The second light control pattern (CCP-R) can be formed by providing ink (INK) into the second bank opening (BOH2) through a nozzle (NZ). The ink (INK) forming the second light control pattern (CCP-R) can include a first quantum dot (QD1). The ink (INK) includes the first quantum dot (QD1) and a scatterer (SP), and can include a second base resin (BR2) in which the first quantum dot (QD1) and the scatterer (SP) are dispersed. The second base resin (BR2) can be an inkjet resin. After the second light control pattern (CCP-R) is formed, a first barrier layer (CAP1) covering one surface of the light control patterns (CCP-B, CCP-R, CCP-G) can be formed.

[0293] While the present invention has been described above with reference to preferred embodiments, it will be understood by those skilled in the art or those with ordinary knowledge in the art that various modifications and changes can be made to the present invention without departing from the spirit and technical scope of the present invention as set forth in the claims below. Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

[0294] The present invention, which provides a display panel with improved display efficiency and a method for manufacturing the same, has industrial applicability.

Claims

1. A display element layer including a light-emitting element that outputs source light; and An optical structure layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength; The optical structure layer includes a light control layer disposed on the light-emitting element, The above optical control layer A bank including a first bank opening and a second bank opening adjacent to each other along a first direction; A first light control pattern disposed within the first bank opening; a second light control pattern disposed within the second bank opening; and A metal pattern disposed between the first light control pattern and the second light control pattern; The above bank is optically transparent, A portion of the above bank overlaps the first optical control pattern in the plane, A display panel in which a portion of the metal pattern overlaps at least a portion of the first light control pattern and the second light control pattern on a plane.

2. In paragraph 1, The above bank is a display panel including a material having a transmittance of 85% or more in the visible light range.

3. In paragraph 1, A display panel in which the metal pattern is disposed between the first light control pattern and the bank and contacts at least a portion of a side surface of the first light control pattern.

4. In paragraph 1, A display panel in which the metal pattern is disposed between the second light control pattern and the bank and contacts at least a portion of a side surface of the second light control pattern.

5. In paragraph 1, A display panel in which the metal pattern has a ring shape that follows the border of at least one of the first light control pattern and the second light control pattern on a plane.

6. In paragraph 1, The above bank further includes a third bank opening adjacent to the second bank opening along the first direction, The above optical control layer A display panel further comprising a third light control pattern disposed within the third bank opening.

7. In paragraph 6, The above metal pattern is In the first direction, a first metal pattern disposed between the first light control pattern and the second light control pattern; and A display panel comprising a second metal pattern disposed between the second light control pattern and the third light control pattern in the first direction.

8. In paragraph 6, A display panel wherein each of the first light control pattern and the third light control pattern includes a photosensitive resin.

9. In paragraph 6, A display panel in which each of the first light control pattern and the third light control pattern includes a scatterer and does not include a light emitting body.

10. In paragraph 1, The second light control pattern is a display panel including a base resin and quantum dots dispersed in the base resin.

11. In paragraph 1, A display panel in which the thickness of the second light control pattern is greater than or equal to the thickness of the first light control pattern.

12. In paragraph 1, The above bank A first part disposed on one side of the first light control pattern; and A second portion that does not overlap with the first light control pattern on a plane; A display panel in which the first part and the second part have an integral shape.

13. In paragraph 12, A display panel in which the width of the first portion in the first direction is greater than the width of the second portion in the first direction.

14. In paragraph 12, A display panel in which, in the first direction, the first portion does not overlap with the first light control pattern and overlaps with the second light control pattern.

15. In paragraph 1, The first bank region defined by the first bank opening emits light of the first wavelength, The second bank region defined by the second bank opening emits light of a second wavelength, A display panel wherein the first wavelength is shorter than the second wavelength.

16. In paragraph 1, The above display element layer further includes an encapsulating layer covering the light emitting element, A display panel in which the above light control layer is directly disposed on the above encapsulating layer.

17. In paragraph 1, The above optical structure layer Further comprising a color filter layer disposed on the light control layer and including a first color filter and a second color filter, The first color filter overlaps at least the first light control pattern on a plane, A display panel in which the second color filter overlaps at least the second light control pattern on a plane.

18. In paragraph 1, A display panel wherein the light control layer further includes a first barrier layer covering one side of each of the first light control pattern and the second light control pattern.

19. A display element layer including a light-emitting element that outputs source light; and An optical structure layer disposed on the light-emitting element and transmitting the source light or converting the source light into light of a different wavelength; The optical structure layer includes a light control layer disposed on the light-emitting element, The above optical control layer A bank comprising a first bank opening, a second bank opening, and a third bank opening arranged along a first direction; A first light control pattern disposed within the first bank opening; A second optical control pattern disposed within the second bank opening; a third optical control pattern disposed within the third bank opening; and A metal pattern disposed between at least the first light control pattern and the second light control pattern; The above bank is optically transparent, Each of the first light control pattern and the third light control pattern includes a photosensitive resin, The second light control pattern is a display panel including a base resin and quantum dots.

20. A step of preparing a display element layer including a light-emitting element that outputs source light; and A step of forming an optical structure layer on the light-emitting element; including; The step of forming the above optical structure layer is A step of forming a first light control pattern by patterning a first preparatory layer including a photosensitive material; A step of forming a metal pattern by depositing a reflective metal layer and then patterning it; A step of forming an optically transparent preliminary bank layer and then patterning it to form a bank including a first bank opening exposing a portion of the first light control pattern and a second bank opening adjacent to the first bank opening along a first direction; and A step of forming a second light control pattern in the second bank opening through an inkjet process; including; A portion of the above bank overlaps the first optical control pattern in the plane, A method for manufacturing a display panel in which a portion of the metal pattern overlaps at least a portion of the first light control pattern and the second light control pattern on a plane.

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