Display substrate and manufacturing method therefor, and display apparatus

Abstract

A display substrate and a manufacturing method therefor, and a display apparatus. The display substrate comprises a display area and a bonding area provided on one side of the display area. The display area comprises a plurality of circuit units which form a plurality of unit rows and a plurality of unit columns, wherein at least one circuit unit comprises a pixel driving circuit. The bonding area at least comprises a plurality of data lead-out lines. The display area further comprises a plurality of data signal lines and a plurality of data connection lines, wherein the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected to the data lead-out lines by means of the data connection lines; and at least one of the data connection lines comprises at least two transverse sublines extending in a first direction and at least two longitudinal sublines extending in a second direction, the two transverse sublines being arranged in different unit rows, and the two longitudinal sublines being arranged in different unit columns. The present disclosure can reduce and even eliminate muras.

Description

Display substrate, preparation method thereof and display device

[0001] The present application claims priority to the Chinese patent application No. 202410472215.7, filed on April 18, 2024, and entitled "Display substrate, preparation method thereof and display device", the content of which is incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of display, in particular to a display substrate, a preparation method thereof and a display device. BACKGROUND

[0003] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of self-emission, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, low cost, etc. With the continuous development of display technology, flexible display devices using OLED or QLED as light-emitting devices and controlled by Thin Film Transistor (TFT) have become the mainstream products in the current display field. SUMMARY

[0004] The following is a summary of the subject matter of the detailed description herein. This summary is not intended to limit the scope of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a display area and a binding area disposed on one side of the display area, the display area comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the binding area comprising at least a plurality of data lead-out lines; the display area further comprising a plurality of data signal lines and a plurality of data connection lines, the data signal lines being configured to provide data signals to the pixel driving circuit, the data signal lines being connected to the data lead-out lines through the data connection lines; at least one data connection line comprising at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines being disposed in different unit rows, the two vertical sub-lines being disposed in different unit columns, the first direction and the second direction intersecting.

[0006] In an exemplary embodiment, at least two horizontal sub-lines are disposed in at least one unit row, and the two horizontal sub-lines are connected to different vertical sub-lines.

[0007] In an exemplary embodiment, at least two vertical sub-lines are arranged in at least one unit column, and the two vertical sub-lines connect different horizontal sub-lines.

[0008] In an exemplary embodiment, a projection of the at least one horizontal sub-line on the display substrate at least partially overlaps with a projection of the at least one vertical sub-line on the display substrate.

[0009] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display region includes a plurality of conductive layers, the two horizontal sub-lines are arranged in the same conductive layer, the two vertical sub-lines are arranged in the same conductive layer, and the horizontal sub-line and the vertical sub-line are arranged in different conductive layers.

[0010] In an exemplary embodiment, the plurality of conductive layers at least include a first source-drain metal layer arranged on a substrate and a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line is arranged in the first source-drain metal layer, and the vertical sub-line is arranged in the second source-drain metal layer.

[0011] In an exemplary embodiment, the at least two horizontal sub-lines at least include a first horizontal sub-line and a second horizontal sub-line, and the at least two vertical sub-lines at least include a first vertical sub-line and a second vertical sub-line; the data signal line is connected with the data lead-out line through the data connection line, including: a first end of the first vertical sub-line is connected with the data lead-out line, a second end of the first vertical sub-line extends toward a direction away from the binding region, and then is connected with a first end of the first horizontal sub-line, a second end of the first horizontal sub-line extends toward a direction close to the second vertical sub-line, and then is connected with a first end of the second vertical sub-line, a second end of the second vertical sub-line extends toward a direction away from the binding region, and then is connected with a first end of the second horizontal sub-line, and a second end of the second horizontal sub-line extends toward a direction close to the data signal line, and then is connected with the data signal line.

[0012] In an exemplary embodiment, the display region further includes a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected with the first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected with the first data connection block through a via hole; in at least another circuit unit, the first data connection block is connected with the first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected with the first data connection block through a via hole.

[0013] In an exemplary embodiment, the display region further comprises a plurality of data transfer strips, in at least one circuit unit, the first end of the first horizontal sub-line is connected to the first data connection block through the data transfer strip; in at least another circuit unit, the first end of the second horizontal sub-line is connected to the first data connection block through the data transfer strip.

[0014] In an exemplary embodiment, in at least one circuit unit, the first horizontal sub-line, the first data connection block and the data transfer strip are an integrated structure connected to each other; in at least another circuit unit, the second horizontal sub-line, the first data connection block and the data transfer strip are an integrated structure connected to each other.

[0015] In an exemplary embodiment, the display region further comprises a plurality of first dummy electrodes, the position and connection structure of at least one of the first dummy electrodes in one circuit unit are the same as the position and connection structure of at least one of the first data connection blocks in another circuit unit.

[0016] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one of the first dummy electrodes through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one of the first dummy electrodes through a via hole.

[0017] In an exemplary embodiment, the display region further comprises a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected to the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected to the second data connection block through a via hole.

[0018] In an exemplary embodiment, in at least one circuit unit, the first horizontal sub-line and the second data connection block are an integrated structure connected to each other.

[0019] In an exemplary embodiment, the display region further comprises a plurality of second dummy electrodes, the position and connection structure of at least one of the second dummy electrodes in one circuit unit are the same as the position and connection structure of at least one of the second data connection blocks in another circuit unit.

[0020] In an exemplary embodiment, in at least one circuit unit, the first vertical sub-line is connected to at least one of the second dummy electrodes through a via hole; in at least another circuit unit, the second vertical sub-line is connected to at least one of the second dummy electrodes through a via hole.

[0021] In another aspect, the present disclosure also provides a display device comprising the aforementioned display substrate.

[0022] In yet another aspect, the present disclosure also provides a method for manufacturing a display substrate, the display substrate comprising a display area and a binding area arranged at one side of the display area, the display area comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit; the method comprising:

[0023] forming a plurality of data signal lines and a plurality of data connection lines in the display area, and forming a plurality of data lead-out lines in the binding area, the data signal lines being configured to provide data signals to the pixel driving circuit, the data signal lines being connected to the data lead-out lines through the data connection lines; at least one data connection line comprising at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines being arranged in different unit rows, and the two vertical sub-lines being arranged in different unit columns, the first direction and the second direction intersecting.

[0024] Other aspects can become apparent after reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0025] The accompanying drawings are included to provide a further understanding of the present disclosure, and constitute a part of this specification that is made of the description of the present disclosure, together with the embodiments of the present disclosure, for explaining the technical scheme of the present disclosure, and do not constitute a limitation of the technical scheme of the present disclosure.

[0026] FIG. 1 is a structural schematic diagram of a display device;

[0027] FIG. 2 is a structural schematic diagram of a display substrate;

[0028] FIG. 3 is a plan structural schematic diagram of a display area in a display area;

[0029] FIG. 4 is a cross-sectional structural schematic diagram of a display area in a display area;

[0030] FIG. 5 is an equivalent circuit diagram of a pixel driving circuit;

[0031] FIG. 6 is a structural schematic diagram of a data connection line in a display substrate;

[0032] FIG. 7 is a structural schematic diagram of a data connection line in an exemplary embodiment of the present disclosure;

[0033] FIG. 8 is a structural schematic diagram of a display substrate in an exemplary embodiment of the present disclosure;

[0034] FIG. 9 is a schematic diagram after forming a first semiconductor layer pattern in an embodiment of the present disclosure;

[0035] FIGS. 10A and 10B are schematic diagrams after forming a first conductive layer pattern in an embodiment of the present disclosure;

[0036] FIGS. 11A and 11B are schematic diagrams of the formation of a second conductive layer pattern according to an embodiment of the present disclosure;

[0037] FIGS. 12A and 12B are schematic diagrams of the formation of a second semiconductor layer pattern according to an embodiment of the present disclosure;

[0038] FIGS. 13A and 13B are schematic diagrams of the formation of a third conductive layer pattern according to an embodiment of the present disclosure;

[0039] FIG. 14 is a schematic diagram of the formation of a sixth insulating layer pattern according to an embodiment of the present disclosure;

[0040] FIGS. 15A and 15B are schematic diagrams of the formation of a fourth conductive layer pattern according to an embodiment of the present disclosure;

[0041] FIG. 16 is a schematic diagram of the formation of a first planarization layer pattern according to an embodiment of the present disclosure;

[0042] FIGS. 17A and 17B are schematic diagrams of the formation of a fifth conductive layer pattern according to an embodiment of the present disclosure;

[0043] FIG. 17C is a schematic diagram of the connection of horizontal sub-lines and vertical sub-lines according to an exemplary embodiment of the present disclosure;

[0044] FIG. 18 is a schematic diagram of the formation of a second planarization layer pattern according to an embodiment of the present disclosure;

[0045] FIGS. 19A and 19B are schematic diagrams of the formation of an anode conductive layer pattern according to an embodiment of the present disclosure.

[0046] Explanation of reference signs: 11-first active layer; 12-second active layer; 13-third active layer; 14-fourth active layer; 15-fifth active layer; 16-sixth active layer; 17-seventh active layer; 18-eighth active layer; 21-first scan signal line; 22-second scan signal line; 23-third scan signal line; 24-fourth scan signal line; 25-emitting signal line; 31-first plate; 32-second plate; 33-opening; 34-plate connecting strip; 35-shielding line; 41-first initial signal line; 42-second initial signal line; 43-third initial signal line; 51-first connecting electrode; 52-second connecting electrode; 53-third connecting electrode; 54-fourth connecting electrode; 55-fifth connecting electrode; 56-sixth connecting electrode; 57-seventh connecting electrode; 58-eighth connecting electrode; 59-ninth connecting electrode; 61-first initial connecting line; 62-second initial connecting line; 71-first power supply line; 72-data signal line; 73-anode connecting electrode; 74-power supply shielding block; 80-data lead-out line; 81-first data connecting line; 82-second data connecting line; 83-data transfer strip; 84-first data connecting block; 85-second data connecting block; 86-first dummy electrode; 87-second dummy electrode; 91-first power supply trace; 92-second power supply trace; 100-display area; 101-substrate; 102-driving structure layer; 103-emitting structure layer; 104-encapsulation structure layer; 110-first area; 120-second area; 200-bonding area; 300-bezel area. DETAILED DESCRIPTION

[0047] In order to make the objects, technical solutions and advantages of the present disclosure clearer, the following will be used to specifically describe the embodiments of the present disclosure with reference to the drawings. It should be noted that the embodiments can be implemented in a variety of different forms. Those skilled in the art can easily understand that the modes and contents can be changed into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. The embodiments in the present disclosure and the features in the embodiments can be combined with each other arbitrarily without conflict.

[0048] The proportions of the drawings in the present disclosure can be used as a reference in the actual process, but are not limited thereto. For example, the width-length ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are also not limited to the number shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one embodiment of the present disclosure is not limited to the shapes or values shown in the drawings.

[0049] The ordinal numbers "first", "second", "third" and the like in the specification are set to avoid confusion of the components, and are not intended to be limited in terms of quantity.

[0050] In the present specification, for the convenience of description, the words indicating the orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the positional relationship of the components with reference to the drawings, and are only for the convenience of description of the present specification and simplification of the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the specification, and can be appropriately changed according to the situation.

[0051] In the present specification, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the communication inside two elements. Those skilled in the art can understand the specific meaning of the above terms in the present disclosure according to the specific circumstances.

[0052] In this specification, a transistor means an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that, in this specification, the channel region means a region where current flows mainly.

[0053] In this specification, the first terminal can be a drain electrode and the second terminal can be a source electrode, or the first terminal can be a source electrode and the second terminal can be a drain electrode. The functions of the "source electrode" and the "drain electrode" are sometimes interchanged with each other in the case of using a transistor whose polarity is reversed or in the case where the direction of current flowing in a circuit is changed, and the like. Therefore, in this specification, the "source electrode" and the "drain electrode" can be interchanged with each other, and the "source terminal" and the "drain terminal" can be interchanged with each other.

[0054] In this specification, "electrically connected" includes the case where components are connected through an element having some function of electricity. The element having some function of electricity is not particularly limited as long as electric signals can be transmitted and received between components to be connected. Examples of the element having some function of electricity include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, and another element having some function.

[0055] In this specification, "parallel" means a state where the angle formed between two straight lines is greater than or equal to -10° and less than or equal to 10°, and thus includes a state where the angle is greater than or equal to -5° and less than or equal to 5°. In addition, "perpendicular" means a state where the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and thus includes a state where the angle is greater than or equal to 85° and less than or equal to 95°.

[0056] In this specification, a "film" and a "layer" can be interchanged with each other. For example, a "conductive layer" can be replaced with a "conductive film". Similarly, an "insulating film" can be replaced with an "insulating layer".

[0057] In this specification, a triangle, a rectangle, a trapezoid, a pentagon, or a hexagon is not necessarily a strict one, and can be an approximate triangle, rectangle, trapezoid, pentagon, or hexagon. There can be some small deformation due to a tolerance, a rounded corner, a rounded side, or the like. In the present disclosure, "about" means that a value is not strictly limited to a certain value, and a value within a range of a process and measurement error is allowed.

[0058] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device can include a timing controller, a data driver, a scan driver, a light emitting driver, and a pixel array, the timing controller is connected with the data driver, the scan driver, and the light emitting driver respectively, the data driver is connected with a plurality of data signal lines (D1 to Dn) respectively, the scan driver is connected with a plurality of scan signal lines (S1 to Sm) respectively, and the light emitting driver is connected with a plurality of light emitting signal lines (E1 to Eo) respectively. The pixel array can include a plurality of sub-pixels Pxij, i and j can be natural numbers, at least one sub-pixel Pxij can include a circuit unit and a light emitting unit, the circuit unit can include at least a pixel driving circuit, the pixel driving circuit is connected with the scan signal line, the light emitting signal line, and the data signal line respectively, and the light emitting unit can include a light emitting device connected with the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide a gray value and a control signal suitable for the specification of the data driver to the data driver, can provide a clock signal, a scan start signal, and the like suitable for the specification of the scan driver to the scan driver, and can provide a clock signal, an emission stop signal, and the like suitable for the specification of the light emitting driver to the light emitting driver. The data driver can generate data voltages to be provided to the data signal lines D1, D2, D3, …, and Dn using the gray value and the control signal received from the timing controller. For example, the data driver can sample the gray value using the clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of a pixel row. n can be a natural number. The scan driver can generate scan signals to be provided to the scan signal lines S1, S2, S3, …, and Sm by receiving the clock signal, the scan start signal, and the like from the timing controller. For example, the scan driver can sequentially provide the scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register, and can generate the scan signal in a manner that sequentially transfers the scan start signal provided in the form of an on-level pulse to a next stage circuit under the control of the clock signal. m can be a natural number. The light emitting driver can generate emission signals to be provided to the light emitting signal lines E1, E2, E3, …, and Eo by receiving the clock signal, the emission stop signal, and the like from the timing controller. For example, the light emitting driver can sequentially provide the emission signal having an off-level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver can be configured in the form of a shift register, and can generate the emission signal in a manner that sequentially transfers the emission stop signal provided in the form of an off-level pulse to a next stage circuit under the control of the clock signal. o can be a natural number. In an exemplary embodiment, the pixel array can be disposed on a display substrate.

[0059] FIG. 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 can be a flat area including a plurality of sub-pixels constituting a pixel array, the plurality of sub-pixels being configured to display dynamic pictures or static images, and the display area 100 can be referred to as an active area (AA). In an exemplary embodiment, the display substrate can adopt a flexible substrate, and thus the display substrate can be deformable, for example, curled, bent, folded, or rolled up.

[0060] In an exemplary embodiment, the binding area 200 can include, in sequence along a direction away from the display area, a lead-out line area, a bending area, a driving chip area, and a binding pin area, the lead-out line area being connected to the display area 100 and including at least data lead-out lines. The bending area is connected to the lead-out line area and can include at least a composite insulating layer provided with a recess configured to bend the binding area to the back of the display area. The driving chip area can include an integrated circuit (IC) configured to be connected to the plurality of data lead-out lines. The binding pin area can include a bonding pad configured to be connected to an external flexible printed circuit (FPC).

[0061] In an exemplary embodiment, the frame area 300 can include, in sequence along a direction away from the display area 100, a circuit area, a power line area, a crack dam area, and a cutting area. The circuit area is connected to the display area 100 and can include at least a gate drive circuit connected to a scanning signal line and a light-emitting signal line in the display area 100. The power line area is connected to the circuit area and can include at least a frame power lead extending along a direction parallel to an edge of the display area and connected to a cathode in the display area 100. The crack dam area is connected to the power line area and can include at least a plurality of cracks provided on a composite insulating layer. The cutting area is connected to the crack dam area and can include at least a cutting groove provided on the composite insulating layer, the cutting groove being configured to be cut by a cutting device along the cutting groove after all film layers of the display substrate are prepared.

[0062] In an exemplary embodiment, the lead-out line area in the binding area 200 and the power line area in the frame area 300 can be provided with an isolation dam, the isolation dam extending along a direction parallel to an edge of the display area and forming a ring structure surrounding the display area 100, the edge of the display area being an edge of the display area on one side of the binding area or the frame area.

[0063] FIG. 3 is a schematic diagram of a planar structure of a display region in a display substrate. As shown in FIG. 3, the display region can include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P can include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel can include a circuit unit and a light-emitting unit, and the circuit unit can include at least a pixel driving circuit. The pixel driving circuit is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively, and is configured to receive a data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit can include a light-emitting device connected to the pixel driving circuit of the sub-pixel where the light-emitting device is located, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel where the light-emitting device is located.

[0064] In an example embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light. In an example embodiment, the shape of the sub-pixel can be rectangular, diamond, pentagonal, or hexagonal, and the four sub-pixels can be arranged in an RGBG manner.

[0065] In other example embodiments, a pixel unit can include three sub-pixels arranged in a horizontal parallel manner or a vertical parallel manner, and the present disclosure does not limit the same.

[0066] FIG. 4 is a schematic diagram of a cross-sectional structure of a display region in a display substrate, illustrating the structure of four sub-pixels in the display region. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate can include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on a side of the driving circuit layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate can include other film layers, such as a touch structure layer, and the present disclosure does not limit the same.

[0067] In an example embodiment, the substrate 101 can be a flexible substrate or can be a rigid substrate. The driving circuit layer 102 can include a plurality of circuit units, each of which can include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 can include a plurality of light-emitting units, each of which can include a light-emitting device that can include at least an anode, an organic light-emitting layer, and a cathode, the anode being connected to the pixel driving circuit, the organic light-emitting layer being connected to the anode, and the cathode being connected to the organic light-emitting layer, the organic light-emitting layer emitting light of a corresponding color under the driving of the anode and the cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, the first encapsulation layer and the third encapsulation layer can be made of inorganic material, the second encapsulation layer can be made of organic material, the second encapsulation layer being arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0068] FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an example embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit can include 8 transistors (first transistor T1 to eighth transistor T8) and 1 storage capacitor C, and is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, light-emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA, and first power supply line VDD).

[0069] In an example embodiment, the pixel driving circuit can include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8, respectively. The third node N3 is connected to the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, respectively. The fourth node N4 is connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, respectively.

[0070] In an example embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power supply line VDD.

[0071] In an exemplary embodiment, the first transistor T1 can be referred to as a first reset transistor, the gate electrode of the first transistor T1 is connected to the third scan signal line S3, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the third node N3.

[0072] In an exemplary embodiment, the second transistor T2 can be referred to as a compensation transistor, the gate electrode of the second transistor T2 is connected to the fourth scan signal line S4, the first electrode of the second transistor T2 is connected to the first node N1, and the second electrode of the second transistor T2 is connected to the third node N3.

[0073] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0074] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0075] In an exemplary embodiment, the fifth transistor T5 can be referred to as a first emission control transistor, the gate electrode of the fifth transistor T5 is connected to the emission signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0076] In an exemplary embodiment, the sixth transistor T6 can be referred to as a second emission control transistor, the gate electrode of the sixth transistor T6 is connected to the emission signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0077] In an exemplary embodiment, the seventh transistor T7 can be referred to as a second reset transistor, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0078] In an exemplary embodiment, the eighth transistor T8 can be referred to as a third reset transistor, the gate electrode of the eighth transistor T8 is connected to the second scan signal line S2, the first electrode of the eighth transistor T8 is connected to the third initial signal line INIT3, and the second electrode of the eighth transistor T8 is connected to the second node N2.

[0079] In an example embodiment, the first electrode of the light emitting device EL is connected to the fourth node N4, and the second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL can be an OLED including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked, or can be a QLED including a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) stacked.

[0080] In an example embodiment, the first power supply line VDD is configured to provide a constant first voltage signal to the pixel driving circuit, the second power supply line VSS is configured to provide a constant second voltage signal to the light emitting device, and the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial voltage signal, the second initial voltage signal, and the third initial voltage signal can be constant voltage signals, which are not limited in the present disclosure.

[0081] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be P-type transistors, or can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the eighth transistor T8 can include P-type transistors and N-type transistors.

[0082] In an example embodiment, the first transistor T1 to the eighth transistor T8 can be low temperature poly-silicon transistors, or can be oxide transistors, or can be low temperature poly-silicon transistors and metal oxide transistors. The active layer of the low temperature poly-silicon transistor adopts low temperature poly-silicon (LTPS), and the active layer of the metal oxide transistor adopts metal oxide semiconductor (Oxide). The low temperature poly-silicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantage of low leakage current. Integrating the low temperature poly-silicon transistor and the metal oxide transistor on one display substrate forms an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of both and can achieve low frequency driving, reduce power consumption, and improve display quality.

[0083] In an example embodiment, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low temperature poly-silicon transistors.

[0084] With the development of display technology, consumers have increasingly high requirements for display products in terms of display effect and display quality. Full-screen and narrow-frame products have gradually become the development trend of display products due to their large screen ratio and ultra-narrow frame. Therefore, the narrow frame or even frameless design in OLED display product design is increasingly valued. In a display substrate, a fan-out in panel (FIP) structure is adopted, a plurality of data connection lines are arranged in a display area, one end of the plurality of data connection lines is connected to a plurality of data signal lines in the display area, and the other end of the plurality of data connection lines extends to a binding area and is connected to an integrated circuit through a plurality of data lead-out lines in a lead-out line area. Since the lead-out line area does not need to be provided with fan-shaped diagonal lines, the width of the lead-out line area is reduced, thereby reducing the lower frame width.

[0085] FIG. 6 is a structural schematic diagram of a data connection line in a display substrate. As shown in FIG. 6, the display area 100 can include a plurality of data signal lines 72, a plurality of first data connection lines 81 and a plurality of second data connection lines 82, and the binding area 200 can include a plurality of data lead-out lines 80. The shape of the plurality of first data connection lines 81 can be a straight line or a polyline extending along a first direction X, and the shape of the plurality of data signal lines 72, the plurality of second data connection lines 82 and the plurality of data lead-out lines 80 can be a straight line or a polyline extending along a second direction Y.

[0086] In an example embodiment, at least one data signal line 72 is connected to a plurality of pixel driving circuits in one unit column, and the data signal line 72 is configured to provide a data signal to the connected pixel driving circuits. The plurality of first data connection lines 81 are arranged in a set interval in the second direction Y in sequence, and the plurality of second data connection lines 82 are arranged in a set interval in the first direction X in sequence, forming a structure arranged layer by layer outward. The first end of the second data connection line 82 is connected to the data lead-out line 80 in the binding area 200, the second end of the second data connection line 82 is connected to the first end of the first data connection line 81, and the second end of the first data connection line 81 is connected to the data signal line 72, so that the data signal line 72 in the display area is connected to the data lead-out line 80 in the binding area through the first data connection line 81 and the second data connection line 82, forming a FIP structure (also referred to as a FIAA structure). In an example embodiment, the first data connection line 81 and the second data connection line 82 are collectively referred to as a data connection line.

[0087] In the example embodiment, since the data connection lines are arranged in part of the display area, the display area can be divided into a first area 110 and a second area 120 according to whether there are data connection lines as a division basis, the first area 110 can be an area where the first data connection line 81 and the second data connection line 82 are arranged (dark area in FIG. 6), and the second area 120 can be an area where the first data connection line 81 and the second data connection line 82 are not arranged (area outside the dark area in FIG. 6). In the example embodiment, the first area 110 can be referred to as an FIP area, and the second area 120 can be referred to as a non-FIP area.

[0088] At present, the OLED display device adopting the FIP structure has problems such as mura. It is found through research that the mura problem is caused by a large difference in the number of unit columns coupled by the plurality of first data connection lines. As shown in FIG. 6, the first data connection line far from the binding area has a long extension length and is coupled with more unit columns, and the first data connection line close to the binding area has a short extension length and is coupled with fewer unit columns. Due to the large difference in the number of unit columns coupled by the first data connection lines in different unit rows, mura appears at the two corners of the display area close to the binding area.

[0089] In order to eliminate the mura, the example embodiment of the present disclosure provides a display substrate. In the example embodiment, the display substrate includes a display area and a binding area arranged on one side of the display area, the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit includes a pixel driving circuit, and the binding area includes at least a plurality of data lead-out lines; the display area further includes a plurality of data signal lines, a plurality of first data connection lines, and a plurality of second data connection lines, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data lead-out lines are connected to the data signal lines through the first data connection lines and the second data connection lines; at least one first data connection line includes at least two horizontal sub-lines extending along a first direction, the two horizontal sub-lines are arranged in different unit rows, at least one second data connection line includes at least two vertical sub-lines extending along a second direction, the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.

[0090] In the example embodiment, at least two horizontal sub-lines are arranged in at least one unit row, and the two horizontal sub-lines are connected to different vertical sub-lines.

[0091] In the example embodiment, at least two vertical sub-lines are arranged in at least one unit column, and the two vertical sub-lines are connected to different horizontal sub-lines.

[0092] In an example embodiment, a projection of the at least one horizontal sub-line on the display substrate at least partially overlaps with a projection of the at least one vertical sub-line on the display substrate.

[0093] In an example embodiment, the two horizontal sub-lines are a first horizontal sub-line and a second horizontal sub-line, and the two vertical sub-lines are a first vertical sub-line and a second vertical sub-line; the data signal line is connected to the data lead-out line through the data connection line, including: a first end of the first vertical sub-line is connected to the data lead-out line, a second end of the first vertical sub-line extends away from the binding area, and then is connected to a first end of the first horizontal sub-line, a second end of the first horizontal sub-line extends towards the second vertical sub-line, and then is connected to a first end of the second vertical sub-line, a second end of the second vertical sub-line extends away from the binding area, and then is connected to a first end of the second horizontal sub-line, and a second end of the second horizontal sub-line extends towards the data signal line, and then is connected to the data signal line.

[0094] An example embodiment of the present disclosure provides a display substrate adopting a Fanout in Panel (FIP) structure. In an example embodiment, in a plane parallel to the display substrate, the display substrate can include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In a direction perpendicular to the display substrate, the display substrate can include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate, and the driving structure layer of the display area 100 can include a plurality of circuit units, and the light-emitting structure layer of the display area 100 can include a plurality of light-emitting units.

[0095] In an example embodiment, the plurality of circuit units can form a plurality of unit rows and a plurality of unit columns, the plurality of circuit units in each unit row are sequentially arranged along a first direction X, the plurality of circuit units in each unit column are sequentially arranged along a second direction Y, forming an array of circuit units arranged in an array, and the first direction X and the second direction Y intersect. The plurality of light-emitting units can form a plurality of light-emitting rows and a plurality of light-emitting columns, the plurality of light-emitting units in each light-emitting row are sequentially arranged along the first direction X, the plurality of light-emitting units in each light-emitting column are sequentially arranged along the second direction Y, forming an array of light-emitting units arranged in an array. In an example embodiment, at least one circuit unit can include at least a pixel driving circuit, and at least one circuit unit can include a light-emitting device connected to the pixel driving circuit of the corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuit.

[0096] In the example embodiments, the circuit unit as referred to in the present disclosure refers to a region divided according to a pixel driving circuit, and the light emitting unit as referred to in the present disclosure refers to a region divided according to a light emitting device. In the example embodiments, the position of the light emitting unit orthogonally projected on the substrate can correspond to the position of the circuit unit orthogonally projected on the substrate, or the position of the light emitting unit orthogonally projected on the substrate can not correspond to the position of the circuit unit orthogonally projected on the substrate.

[0097] FIG. 7 is a schematic view of a structure of a data connection line according to an example embodiment of the present disclosure. As shown in FIG. 7, the display region 100 can include a plurality of data signal lines 72 and a plurality of data connection lines, and the binding region 200 can include a plurality of data lead-out lines 80. The plurality of data signal lines 72 and the plurality of data lead-out lines 80 can have a shape of a straight line or a polyline extending along the second direction Y, and the plurality of data connection lines can have a shape of a polyline including a straight line extending along the first direction X and a straight line extending along the second direction Y. The data signal line 72 is configured to provide a data signal to the connected pixel driving circuit, and the data signal line 72 is connected to the data lead-out line 80 through the data connection line. Specifically, the first end of the plurality of data connection lines is connected to the plurality of data lead-out lines 80 in the binding region 200, and the second end of the plurality of data connection lines extends away from the binding region 200 and is connected to the plurality of data signal lines 72, so that the data signal line 72 in the display region is connected to the data lead-out line 80 in the binding region through the data connection line, forming a FIP structure (also referred to as a FIAA structure). Since the data connection line is arranged in the display region, the inclined line in the shape of a fan does not need to be arranged in the lead-out line region, thereby reducing the length of the binding region in the second direction Y, reducing the lower frame width, improving the screen-to-body ratio, and facilitating the realization of a full-screen display.

[0098] In the example embodiments, the display region 100 can have a center line O, and the plurality of data signal lines 72, the plurality of data connection lines, and the plurality of data lead-out lines 80 can be mirror-symmetrical with respect to the center line O. The center line O can be a straight line that bisects a plurality of unit columns in a plurality of display regions and extends along the second direction Y.

[0099] In the example embodiments, at least one data connection line can include at least two horizontal sub-lines and at least two vertical sub-lines. The horizontal sub-line can have a shape of a straight line or a polyline extending along the first direction X, and the vertical sub-line can have a shape of a straight line or a polyline extending along the second direction Y. The two horizontal sub-lines can be arranged in different unit rows, and the two vertical sub-lines can be arranged in different unit columns. The horizontal sub-line and the vertical sub-line are connected to each other to form a data connection line in the shape of a polyline including the horizontal sub-line and the vertical sub-line.

[0100] In an example embodiment, at least two horizontal sub-lines can be arranged in at least one unit row, and the two horizontal sub-lines can connect different vertical sub-lines.

[0101] In an example embodiment, at least two vertical sub-lines can be arranged in at least one unit column, and the two vertical sub-lines can connect different horizontal sub-lines.

[0102] In an example embodiment, the orthographic projection of the at least one horizontal sub-line on the display substrate at least partially overlaps the orthographic projection of the at least one vertical sub-line on the display substrate.

[0103] In an example embodiment, the two horizontal sub-lines can be a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2 extending along the first direction X, and the two vertical sub-lines can be a first vertical sub-line 82-1 and a second vertical sub-line 82-2 extending along the second direction Y. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 are arranged in different unit rows, and the first horizontal sub-line 81-1 can be arranged in a unit row close to the binding area, and the second horizontal sub-line 81-2 can be arranged in a unit row away from the binding area on a side of the first horizontal sub-line 81-1. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 are arranged in different unit columns, and the first vertical sub-line 82-1 can be arranged in a unit column close to the center line O, and the second vertical sub-line 82-2 can be arranged in a unit column away from the center line O on a side of the first vertical sub-line 82-1.

[0104] In an example embodiment, in the first direction X, the first horizontal sub-line 81-1 can be arranged on a side of the first vertical sub-line 82-1 away from the center line O, the second vertical sub-line 82-2 can be arranged on a side of the first horizontal sub-line 81-1 away from the center line O, and the second horizontal sub-line 81-2 can be arranged on a side of the second vertical sub-line 82-2 away from the center line O. In the second direction Y, the first horizontal sub-line 81-1 can be arranged on a side of the first vertical sub-line 82-1 away from the binding area, the second vertical sub-line 82-2 can be arranged on a side of the first horizontal sub-line 81-1 away from the binding area, and the second horizontal sub-line 81-2 can be arranged on a side of the second vertical sub-line 82-2 away from the binding area.

[0105] In an example embodiment, the data connection line 72 connected with the data lead-out line 80 through the data connection line can include: the first end of the first vertical sub-line 82-1 connected with the data lead-out line 80, the second end of the first vertical sub-line 82-1 extended in a direction away from the binding area, then connected with the first end of the first horizontal sub-line 81-1, the second end of the first horizontal sub-line 81-1 extended in a direction away from the center line O (in a direction close to the second vertical sub-line 82-2), then connected with the first end of the second vertical sub-line 82-2, the second end of the second vertical sub-line 82-2 extended in a direction away from the binding area, then connected with the first end of the second horizontal sub-line 81-2, the second end of the second horizontal sub-line 81-2 extended in a direction away from the center line O (in a direction close to the data signal line 72), then connected with the data signal line 72.

[0106] In an example embodiment, at least one horizontal sub-line can be connected with two vertical sub-lines. For example, the first end of the first horizontal sub-line 81-1 is connected with the first vertical sub-line 82-1, and the second end of the first horizontal sub-line 81-1 is connected with the second vertical sub-line 82-2.

[0107] In an example embodiment, at least one vertical sub-line can be connected with two horizontal sub-lines. For example, the first end of the second vertical sub-line 82-2 is connected with the first horizontal sub-line 81-1, and the second end of the second vertical sub-line 82-2 is connected with the second horizontal sub-line 81-2.

[0108] In an example embodiment, the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 can be referred to as the first data connection line 81, and the first vertical sub-line 82-1 and the second vertical sub-line 82-2 can be referred to as the second data connection line 82, that is, the data connection line can include the first data connection line 81 and the second data connection line 82, the first data connection line 81 can include the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, and the second data connection line 82 can include the first vertical sub-line 82-1 and the second vertical sub-line 82-2.

[0109] In an example embodiment, the number of data connection lines in the display area can be the same as the number of data signal lines, and each data signal line is connected with a lead-out line through a data connection line. Alternatively, the number of data connection lines in the display area can be less than the number of data signal lines, and part of the data signal lines in the display area are connected with the data lead-out line through the data connection line, and the other part of the data signal lines are directly connected with the data lead-out line, which is not limited in the present disclosure.

[0110] In an example embodiment, the data lead-out line 80 can be directly connected with the data signal line 72 and the data connection line, or can be connected through a via, which is not limited in the present disclosure.

[0111] In an exemplary embodiment, the display area can be divided into a first area 110 and a second area 120, the first area 110 can be an area provided with horizontal sub-lines and vertical sub-lines (dark area in FIG. 7), and the second area 120 can be an area without horizontal sub-lines and vertical sub-lines (area other than the dark area in FIG. 7).

[0112] FIG. 8 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of the area A in FIG. 7. In an exemplary embodiment, the display area can include a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit can include a pixel driving circuit connected to a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a fourth scan signal line 24, an emission signal line 25, a first initial signal line 41, a second initial signal line 42, a third initial signal line 43, a first power supply line 71, and a data signal line 72, respectively.

[0113] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, and the emission signal line 25 are configured to provide a first scan signal, a second scan signal, a third scan signal, a fourth scan signal, and an emission control signal to the pixel driving circuit, respectively, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 are configured to provide a first initial signal, a second initial signal, and a third initial signal to the pixel driving circuit, respectively, the first power supply line 71 is configured to provide a first power supply signal to the pixel driving circuit, and the data signal line 72 is configured to provide a data signal to the pixel driving circuit. Wherein a plurality of signal lines connected to the pixel driving circuit can be located within the corresponding circuit unit.

[0114] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, the fourth scan signal line 24, the emission signal line 25, the first initial signal line 41, the second initial signal line 42, and the third initial signal line 43 can have a shape of a straight line or a broken line with a main part extending along the first direction X, and the first power supply line 71 and the data signal line 72 can have a shape of a straight line or a broken line with a main part extending along the second direction Y.

[0115] In the present disclosure, A extending along B direction means that A can include a main part and a sub part connected to the main part, the main part is a line, a line segment, or a bar-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the sub part extending along other directions. In the following description, A extending along B direction means that the main part of A extending along B direction.

[0116] In the example embodiment, the pixel driving circuit can include at least a storage capacitor and a plurality of transistors. The storage capacitor can include a first plate and a second plate stacked, and the plurality of transistors can include a first transistor T1 as a first reset transistor, a second transistor T2 as a compensation transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light emitting control transistor, a sixth transistor T6 as a second light emitting control transistor, a seventh transistor T7 as a second reset transistor, and an eighth transistor T8 as a third reset transistor. Among them, the second transistor T2 can be a metal oxide transistor, and the first transistor T1, the third transistor T3 to the eighth transistor T8 can be low temperature poly-silicon transistors.

[0117] In the example embodiment, the gate electrode of the first transistor T1 is connected with the third scan signal line 23, the first electrode of the first transistor T1 is connected with the first initial signal line 41, and the second electrode of the first transistor T1 is connected with the second electrode of the second transistor T2, the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6, respectively. The gate electrode of the second transistor T2 is connected with the fourth scan signal line 24, and the first electrode of the second transistor T2 and the first plate of the storage capacitor (also the gate electrode of the third transistor T3) are connected. The first electrode of the third transistor T3 is connected with the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5 and the second electrode of the eighth transistor T8, respectively. The gate electrode of the fourth transistor T4 is connected with the first scan signal line 21, and the first electrode of the fourth transistor T4 is connected with the data signal line 72. The gate electrode of the fifth transistor T5 is connected with the light emitting signal line 25, and the first electrode of the fifth transistor T5 is connected with the first power line 71. The gate electrode of the sixth transistor T6 is connected with the light emitting signal line 25, and the second electrode of the sixth transistor T6 is connected with the second electrode of the seventh transistor T7. The gate electrode of the seventh transistor T7 is connected with the second scan signal line 22, and the first electrode of the seventh transistor T7 is connected with the second initial signal line 42. The gate electrode of the eighth transistor T8 is connected with the second scan signal line 22, and the first electrode of the eighth transistor T8 is connected with the third initial signal line 43.

[0118] In the exemplary embodiment, in the at least one circuit unit, the fourth scan signal line 24 can be disposed on a side of the storage capacitor (the third transistor T3) in a reverse direction of the second direction Y, the first scan signal line 21 can be disposed on a side of the fourth scan signal line 24 away from the storage capacitor, the third scan signal line 23 and the second initial signal line 42 can be disposed on a side of the first scan signal line 21 away from the storage capacitor, and the first initial signal line 41 can be disposed on a side of the third scan signal line 23 away from the storage capacitor. The light emission signal line 25 can be disposed on a side of the storage capacitor in the second direction Y, and the second scan signal line 22 and the third initial signal line 43 can be disposed on a side of the light emission signal line 25 away from the storage capacitor.

[0119] In the exemplary embodiment, a projection of the second initial signal line 42 on the substrate at least partially overlaps a projection of the third scan signal line 23 on the substrate, and a projection of the third initial signal line 43 on the substrate at least partially overlaps a projection of the second scan signal line 22 on the substrate.

[0120] In the exemplary embodiment, the at least one circuit unit can further include a first initial connection line 61. The first initial connection line 61 can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y, and can be connected to the first initial signal line 41. The first initial signal line 41 and the first initial connection line 61 can form a mesh-like communication structure for transmitting the first initial signal in a mesh shape.

[0121] In the exemplary embodiment, the at least one circuit unit can further include a second initial connection line 62. The second initial connection line 62 can have a shape of a straight line or a broken line in which a main body portion extends in the second direction Y, and can be connected to the second initial signal line 42. The second initial signal line 42 and the second initial connection line 62 can form a mesh-like communication structure for transmitting the second initial signal in a mesh shape.

[0122] In the exemplary embodiment, the display area can further include a plurality of data connection lines, and at least one data connection line can include a first horizontal sub-line 81-1, a second horizontal sub-line 81-2, a first vertical sub-line 82-1, and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 can have a shape of a straight line or a broken line extending in the first direction X. The first horizontal sub-line 81-1 can be disposed in an M+5th unit row, and the second horizontal sub-line 81-2 can be disposed in an Mth unit row. The first vertical sub-line 82-1 and the second vertical sub-line 82-2 can have a shape of a straight line or a broken line extending in the second direction Y. The first vertical sub-line 82-1 can be disposed between an N+10th unit column and an N+11th unit column, and the second vertical sub-line 82-2 can be disposed between an Nth unit column and an N+1th unit column.

[0123] In the example embodiment, the first end of the first vertical sub-line 82-1 is connected with the data lead-out line of the binding area, the second end of the first vertical sub-line 82-1 is connected with the first end of the first horizontal sub-line 81-1 after extending along the opposite direction of the second direction Y (towards the direction close to the first horizontal sub-line 81-1), the second end of the first horizontal sub-line 81-1 is connected with the first end of the second vertical sub-line 82-2 after extending along the opposite direction of the first direction X (towards the direction close to the second vertical sub-line 82-2), the second end of the second vertical sub-line 82-2 is connected with the first end of the second horizontal sub-line 81-2 after extending along the opposite direction of the second direction Y (towards the direction close to the second horizontal sub-line 81-2), and the second end of the second horizontal sub-line 81-2 is connected with the data signal line 72 after extending along the opposite direction of the first direction X (towards the direction close to the data signal line 72).

[0124] In the example embodiment, the at least one circuit unit can further include a data transfer strip 83 and a first data connection block 84. The data transfer strip 83 can have a strip shape extending along the second direction Y, the first data connection block 84 can have a block shape (e.g. a rectangular shape), the first end of the data transfer strip 83 is connected with the first horizontal sub-line 81-1 or the second horizontal sub-line 81-2, the second end of the data transfer strip 83 is connected with the first data connection block 84, and the first data connection block 84 is configured to be connected with the first vertical sub-line 82-1 or the second vertical sub-line 82-2. For example, in the Mth unit row, the first data connection block 84 is connected with the second horizontal sub-line 81-2 through the data transfer strip 83, the second end of the second vertical sub-line 82-2 is connected with the first data connection block 84, and the connection between the second end of the second vertical sub-line 82-2 and the first end of the second horizontal sub-line 81-2 is achieved. For another example, in the M+5th unit row, the first data connection block 84 is connected with the first horizontal sub-line 81-1 through the data transfer strip 83, the second end of the first vertical sub-line 82-1 is connected with the first data connection block 84, and the connection between the second end of the first vertical sub-line 82-1 and the first end of the first horizontal sub-line 81-1 is achieved.

[0125] In the example embodiment, the at least one circuit unit can further include a second data connection block 85. The second data connection block 85 can have a block shape (e.g. a rectangular shape) and be connected with the second end of the first horizontal sub-line 81-1, and the second data connection block 85 is configured to be connected with the first end of the second vertical sub-line 82-2. For example, in the M+5th unit row, the second data connection block 85 is connected with the second end of the first horizontal sub-line 81-1, the first end of the second vertical sub-line 82-2 is connected with the second data connection block 85, and the connection between the second end of the first horizontal sub-line 81-1 and the first end of the second vertical sub-line 82-2 is achieved.

[0126] In an example embodiment, the at least one circuit unit can further include a first dummy electrode 86, which can be in a block shape (e.g., a rectangular shape) and configured to be connected with the vertical sub-line. The first dummy electrode 86 can be positioned and connected in substantially the same manner as the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated.

[0127] In an example embodiment, the at least one circuit unit can further include a second dummy electrode 87, which can be in a block shape (e.g., a rectangular shape) and configured to be connected with the vertical sub-line. The second dummy electrode 87 can be positioned and connected in substantially the same manner as the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated.

[0128] In an example embodiment, the driving structure layer of the display area can include a plurality of conductive layers in a direction perpendicular to the display substrate, the lateral sub-line can be disposed in the same conductive layer, the vertical sub-line can be disposed in the same conductive layer, and the lateral sub-line and the vertical sub-line can be disposed in different conductive layers.

[0129] In an example embodiment, the plurality of conductive layers can include at least a first source-drain metal layer (SD1) disposed on the base and a second source-drain metal layer (SD2) disposed on a side of the first source-drain metal layer away from the base, the lateral sub-line can be disposed in the first source-drain metal layer, and the vertical sub-line can be disposed in the second source-drain metal layer.

[0130] In an example embodiment, the first data connection block 84, the second data connection block 85, the first dummy electrode 86, and the second dummy electrode 87 can be disposed in the first source-drain metal layer.

[0131] The preparation process of the display substrate is exemplarily described below. The "patterning process" in the present disclosure includes coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and includes coating organic materials, mask exposure and development and the like for organic materials. The deposition can adopt any one or more of sputtering, evaporation, chemical vapor deposition, the coating can adopt any one or more of spraying, spin coating and inkjet printing, and the etching can adopt any one or more of dry etching and wet etching, which are not limited in the present disclosure. The "thin film" refers to a thin film of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not need a patterning process in the entire preparation process, the "thin film" can also be referred to as a "layer". If the "thin film" needs a patterning process in the entire preparation process, it is referred to as a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed at the same time by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0132] In the exemplary embodiments, taking 72 circuit units (6 unit rows and 12 unit columns) as an example, the preparation process of the display substrate can include the following operations.

[0133] (1) Forming a first semiconductor layer pattern. In the exemplary embodiments, forming the first semiconductor layer pattern can include: sequentially depositing a first insulating thin film and a first semiconductor thin film on a substrate, patterning the first semiconductor thin film by a patterning process, forming a first insulating layer arranged on the substrate, and a first semiconductor layer pattern arranged on the first insulating layer, as shown in FIG. 9.

[0134] In the exemplary embodiments, the first semiconductor layer pattern of each circuit unit can include at least a first active layer 11 of a first transistor T1, a third active layer 13 of a third transistor T3 to an eighth active layer 18 of an eighth transistor T8, and the third active layer 13 to the seventh active layer 17 are an integrated structure connected with each other, and the first active layer 11 and the eighth active layer 18 are separately arranged.

[0135] In the exemplary embodiment, in the first direction X, the first active layer 11 and the sixth active layer 16 can be located on one side of the third active layer 13 in the circuit unit, and the fourth active layer 14 and the fifth active layer 15 can be located on the other side of the third active layer 13 in the circuit unit. In the second direction Y, the first active layer 11 and the fourth active layer 14 can be located on one side of the third active layer 13 in the circuit unit in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, the seventh active layer 17, and the eighth active layer 18 can be located on one side of the third active layer 13 in the circuit unit in the second direction Y.

[0136] In the exemplary embodiment, the third active layer 13 can have an "Ω" shape, the fourth active layer 14 and the sixth active layer 16 can have an "L" shape, and the first active layer 11, the fifth active layer 15, the seventh active layer 17, and the eighth active layer 18 can have an "I" shape.

[0137] In the exemplary embodiment, the first active layer 11, the third active layer 13 to the eighth active layer 18 can each include a first region, a second region, and a channel region between the first region and the second region. In the exemplary embodiment, the first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer can be connected to each other, and the first region 13-1 of the third active layer can serve as both the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer. The second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer can be connected to each other, and the second region 13-2 of the third active layer can serve as the first region 16-1 of the sixth active layer. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer can be connected to each other, and the second region 16-2 of the sixth active layer can serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the second region 11-2 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, the first region 17-1 of the seventh active layer, the first region 18-1 of the eighth active layer, and the second region 18-2 of the eighth active layer can be separately provided.

[0138] In the exemplary embodiments, the first regions 15-1 of the fifth active layers in the partial two adjacent circuit units in one unit row can be connected to each other, and the fifth active layers in the two circuit units can be an integrated structure connected to each other. For example, the fifth active layer in the Nth unit column and the fifth active layer in the N+1th unit column can be an integrated structure connected to each other, the fifth active layer in the N+2th unit column and the fifth active layer in the N+3th unit column can be an integrated structure connected to each other, the fifth active layer in the N+4th unit column and the fifth active layer in the N+5th unit column can be an integrated structure connected to each other, the fifth active layer in the N+6th unit column and the fifth active layer in the N+7th unit column can be an integrated structure connected to each other, the fifth active layer in the N+8th unit column and the fifth active layer in the N+9th unit column can be an integrated structure connected to each other, and the fifth active layer in the N+10th unit column and the fifth active layer in the N+11th unit column can be an integrated structure connected to each other. Since the first region of the fifth active layer in each circuit unit is configured to be connected to the first power line formed subsequently, by forming the fifth active layers of the adjacent circuit units into an integrated structure connected to each other, the first electrode of the fifth transistor T5 in the adjacent circuit units can have the same potential, which is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0139] In the exemplary embodiments, the first semiconductor layers in the adjacent unit columns can be mirror symmetrical relative to the column boundary line. For example, the first semiconductor layer in the Nth unit column and the first semiconductor layer in the N+1th unit column can be mirror symmetrical relative to the column boundary line, and the first semiconductor layer in the N+1th unit column and the first semiconductor layer in the N+2th unit column can be mirror symmetrical relative to the column boundary line. In the exemplary embodiments, the shapes of the first semiconductor layers in the plurality of unit rows can be substantially the same.

[0140] In the exemplary embodiments, the first semiconductor layer can be polycrystalline silicon (p-Si), i.e., the first transistor, the third transistor to the seventh transistor are LTPS transistors. In the exemplary embodiments, the patterning process for patterning the first semiconductor thin film can include: first forming an amorphous silicon (a-si) thin film on the first insulating thin film, performing dehydrogenation treatment on the amorphous silicon thin film, performing crystallization treatment on the amorphous silicon thin film after the dehydrogenation treatment, and forming a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form a first semiconductor layer pattern.

[0141] (2) forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern can include: sequentially depositing a second insulating thin film and a first conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the first semiconductor layer pattern, and forming the first conductive layer pattern on the second insulating layer, as shown in FIGS. 10A and 10B, which is a plan view of the first conductive layer in FIG. 10A. In an exemplary embodiment, the first conductive layer can be referred to as a first gate metal (GATE1) layer.

[0142] In an exemplary embodiment, the first conductive layer pattern of each circuit unit can include at least: a first scan signal line 21, a second scan signal line 22, a third scan signal line 23, a light emitting signal line 25, and a first plate 31 of a storage capacitor.

[0143] In an exemplary embodiment, the first plate 31 can have a rectangular shape, and a corner of the rectangular shape can be chamfered. A normal projection of the first plate 31 on the substrate can at least partially overlap a normal projection of a third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first plate 31 can simultaneously serve as a lower plate of the storage capacitor and a gate electrode of the third transistor T3.

[0144] In an exemplary embodiment, the first scan signal line 21 can have a straight line shape or a broken line shape in which a main body portion extends along the first direction X. The first scan signal line 21 can be located on a side opposite to the second direction Y of the first plate 31. An area in which the first scan signal line 21 overlaps the fourth active layer can serve as a gate electrode of the fourth transistor T4.

[0145] In an exemplary embodiment, the second scan signal line 22 can have a straight line shape or a broken line shape in which a main body portion extends along the first direction X. The second scan signal line 22 can be located on a side of the second direction Y of the first plate 31. An area in which the second scan signal line 22 overlaps the seventh active layer can serve as a gate electrode of the seventh transistor T7, and an area in which the second scan signal line 22 overlaps the eighth active layer can serve as a gate electrode of the eighth transistor T8.

[0146] In an exemplary embodiment, the third scan signal line 23 can have a straight line shape or a broken line shape in which a main body portion extends along the first direction X. The third scan signal line 23 can be located on a side of the first scan signal line 21 away from the first plate 31. An area in which the third scan signal line 23 overlaps the first active layer can serve as a gate electrode of the first transistor T1.

[0147] In an exemplary embodiment, the light emission signal line 25 can be in a straight line shape or a broken line shape with a main body portion extending along the first direction X, the light emission signal line 25 can be located between the second scan signal line 22 and the first plate 31, an area where the light emission signal line 25 overlaps the fifth active layer can serve as a gate electrode of the fifth transistor T5, and an area where the light emission signal line 25 overlaps the sixth active layer can serve as a gate electrode of the sixth transistor T6.

[0148] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can be in a non-equal width design, the width being a dimension in the second direction Y, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines, which is not limited in the present disclosure.

[0149] In an exemplary embodiment, the first scan signal line 21, the second scan signal line 22, the third scan signal line 23, and the light emission signal line 25 can include an area overlapping the first semiconductor layer and an area not overlapping the first semiconductor layer, the width of the signal line in the area overlapping the first semiconductor layer can be greater than the width of the signal line in the area not overlapping the first semiconductor layer.

[0150] In an exemplary embodiment, the first conductive layer of adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the first conductive layer of the Nth unit column and the first conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, and the first conductive layer of the N+1th unit column and the first conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shape of the first conductive layer in the plurality of unit rows can be substantially the same.

[0151] In an exemplary embodiment, after forming the first conductive layer pattern, the first semiconductor layer can be subjected to a conductorization process using the first conductive layer as a shield, the first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 and the third transistor T3 to the eighth transistor T8, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, i.e., the first region and the second region of the first transistor T1, the third transistor T3 to the eighth transistor T8 are conductorized.

[0152] (3) forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern can include: sequentially depositing a third insulating thin film and a second conductive thin film on the substrate on which the aforementioned pattern is formed, patterning the second conductive thin film by using a patterning process, forming a third insulating layer covering the first conductive layer, and forming the second conductive layer pattern disposed on the third insulating layer, as shown in FIG. 11A and FIG. 11B, which is a plan view of the second conductive layer in FIG. 11A. In an exemplary embodiment, the second conductive layer can be referred to as a second gate metal (GATE2) layer.

[0153] In an exemplary embodiment, the second conductive layer pattern of each circuit unit at least includes: a second plate 32 of a storage capacitor, a shielding line 35, and a first initial signal line 41.

[0154] In an exemplary embodiment, the second plate 32 can have a rectangular shape, and a corner of the rectangular shape can be chamfered. A normal projection of the second plate 32 on the substrate at least partially overlaps a normal projection of the first plate 31 on the substrate. The second plate 32 can serve as an upper plate of a storage capacitor, and the first plate 31 and the second plate 32 constitute a storage capacitor of a pixel driving circuit.

[0155] In an exemplary embodiment, the second plate 32 is provided with an opening 33, which can have a rectangular shape and can be located in a middle portion of the second plate 32, so as to form a ring-shaped structure of the second plate 32. The opening 33 exposes the third insulating layer covering the first plate 31, and a normal projection of the first plate 31 on the substrate contains a normal projection of the opening 33 on the substrate. In an exemplary embodiment, the opening 33 is configured to accommodate a thirteenth via hole to be formed subsequently, the thirteenth via hole is located in the opening 33 and exposes the first plate 31, so as to connect a first connection electrode to be formed subsequently to the first plate 31.

[0156] In an exemplary embodiment, the second plate 32 is provided with a plate connection strip 34, which can have a strip shape extending along the first direction X and can be disposed on one side of the second plate 32 in the first direction X or on the side opposite to the first direction X. A first end of the plate connection strip 34 is connected to the second plate 32 in the current circuit unit, and a second end of the plate connection strip 34 is connected to the second plate 32 in a circuit unit adjacent to the first direction X or the side opposite to the first direction X.

[0157] In the example embodiment, the second plate 32 and the plate connecting strip 34 in two adjacent circuit units in one unit row are integrally connected to each other. Since the second plate 32 in each circuit unit is connected to the first power supply line formed subsequently, by forming the second plates 32 of adjacent circuit units into an integrally connected structure, the second plates of the integrally connected structure can be reused as power supply signal lines, which can ensure that the second plates of adjacent circuit units have the same potential, thereby improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0158] In the example embodiment, the shielding line 35 can be in a straight line shape or a broken line shape with a main body extending along the first direction X, and can be located between the first scan signal line 21 and the second plate 32. The shielding line 35 is configured as a shielding layer of the second transistor T2, shields the channel region of the second transistor T2, ensures the electrical performance of the oxide second transistor T2, and is also configured as a bottom gate electrode of the second transistor T2.

[0159] In the example embodiment, the shielding line 35 can be designed in a non-equal width, which can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the signal lines.

[0160] In the example embodiment, the first initial signal line 41 can be in a straight line shape or a broken line shape with a main body extending along the first direction X, and can be located on the side of the third scan signal line 23 away from the second plate 32. The first initial signal line 41 of each circuit unit can be provided with a first initial connecting block 41-1, which can be in a block shape (such as a rectangular shape) and connected to the first initial signal line 41. The first initial connecting block 41-1 is configured to be connected to the first region of the first active layer through a seventh connecting electrode formed subsequently.

[0161] In the example embodiment, the first initial connecting blocks 41-1 of circuit units adjacent in part of the first direction X can be connected to each other to form an integrally connected structure, so that part of the adjacent circuit units share the same first initial connecting block 41-1. For example, the first initial connecting block 41-1 of the N+1 unit column and the first initial connecting block 41-1 of the N+2 unit column are in an integrally connected structure. For another example, the first initial connecting block 41-1 of the N+3 unit column and the first initial connecting block 41-1 of the N+4 unit column are in an integrally connected structure.

[0162] In an example embodiment, the second conductive layers of adjacent cell columns can be mirror symmetrical with respect to the column boundary line. For example, the second conductive layer of the Nth cell column and the second conductive layer of the N+1th cell column can be mirror symmetrical with respect to the column boundary line, and the second conductive layer of the N+1th cell column and the second conductive layer of the N+2th cell column can be mirror symmetrical with respect to the column boundary line. In an example embodiment, the shapes of the second conductive layers in the plurality of cell rows can be substantially the same.

[0163] (4) Forming a second semiconductor layer pattern. In an example embodiment, forming the second semiconductor layer pattern can include: sequentially depositing a fourth insulating thin film and a second semiconductor thin film on the substrate on which the aforementioned pattern is formed, patterning the second semiconductor thin film by a patterning process, forming a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in FIGS. 12A and 12B, FIG. 12B being a plan view of the second semiconductor layer in FIG. 12A.

[0164] In an example embodiment, the second semiconductor layer pattern of each circuit unit at least includes a second active layer 12 of a second transistor T2.

[0165] In an example embodiment, the shape of the second active layer 12 can be in an "L" shape, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the shielding line 35 on the substrate.

[0166] In an example embodiment, the first region 12-1 of the second active layer can be located on the side of the shielding line 35 away from the second plate 32, and the second region 12-2 of the second active layer can be located on the side of the shielding line 35 close to the second plate 32.

[0167] In an example embodiment, the second semiconductor layers of adjacent cell columns can be mirror symmetrical with respect to the column boundary line. For example, the second semiconductor layer of the Nth cell column and the second semiconductor layer of the N+1th cell column can be mirror symmetrical with respect to the column boundary line, and the second semiconductor layer of the N+1th cell column and the second semiconductor layer of the N+2th cell column can be mirror symmetrical with respect to the column boundary line. In an example embodiment, the shapes of the second semiconductor layers in the plurality of cell rows can be substantially the same.

[0168] In an example embodiment, the second semiconductor layer can be an oxide, i.e., the second transistor T2 is an oxide transistor. In an example embodiment, the second semiconductor thin film can be indium gallium zinc oxide (IGZO), and the electron mobility of indium gallium zinc oxide (IGZO) is higher than that of amorphous silicon.

[0169] (5) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern can include: sequentially depositing a fifth insulating thin film and a third conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the third conductive thin film by using a patterning process, forming a fifth insulating layer covering the second semiconductor layer, and forming a third conductive layer pattern on the fifth insulating layer, as shown in FIGS. 13A and 13B, which is a plan view of the third conductive layer in FIG. 13A. In an exemplary embodiment, the second conductive layer can be referred to as a third gate metal (GATE3) layer.

[0170] In an exemplary embodiment, the third conductive layer pattern of each circuit unit at least includes: a fourth scan signal line 24, a second initial signal line 42, and a third initial signal line 43.

[0171] In an exemplary embodiment, the fourth scan signal line 24 can have a shape of a straight line or a broken line in which a main body portion extends along the first direction X, the fourth scan signal line 24 can be located between the first scan signal line 21 and the second plate 32, and an area in which the fourth scan signal line 24 overlaps the second active layer can serve as a gate electrode of the second transistor T2.

[0172] In an exemplary embodiment, the fourth scan signal line 24 and the shield line 35 can be connected to the same signal source, the fourth scan signal line 24 can serve as a top gate electrode of the second transistor T2, and the shield line 35 can serve as a bottom gate electrode of the second transistor T2, forming a top gate-bottom gate structure of the second transistor T2.

[0173] In an exemplary embodiment, the second initial signal line 42 can have a shape of a straight line or a broken line in which a main body portion extends along the first direction X, the second initial signal line 42 can be located on a side of the first scan signal line 21 away from the second plate 32, and each circuit unit can be provided with a second initial connection block 42-1 on the second initial signal line 42, the second initial connection block 42-1 can have a shape of a block (e.g., a rectangular) and be connected to the second initial signal line 42, and the second initial connection block 42-1 can be configured to be connected to the first area of the seventh active layer through a subsequently formed eighth connection electrode.

[0174] In an exemplary embodiment, the second initial signal line 42 and the third scan signal line 23 can at least partially overlap in orthographic projection on the substrate, the second initial signal line 42, which transmits a constant voltage, can shield the third scan signal line 23 from affecting the pixel driving circuit, and the driving quality of the pixel driving circuit can be improved.

[0175] In an exemplary embodiment, the third initial signal line 43 can be in a straight line shape or a zigzag shape with the main body extending along the first direction X, the third initial signal line 43 can be located between the second plate 32 and the first initial signal line 41, and the third initial signal line 43 of each circuit unit can be provided with a third initial connecting block 43-1 in a block shape (e.g., a rectangular shape) connected to the third initial signal line 43, and configured to be connected to the first region of the eighth active layer through the ninth connecting electrode formed subsequently.

[0176] In an exemplary embodiment, the third initial connecting blocks 43-1 of the circuit units adjacent to each other in the partial first direction X can be connected to each other to form an integrated structure connected to each other, so that the circuit units adjacent to each other share the same third initial connecting block 43-1. For example, the third initial connecting block 43-1 of the Nth unit column and the third initial connecting block 43-1 of the N+1th unit column form an integrated structure connected to each other. For another example, the third initial connecting block 43-1 of the N+2th unit column and the third initial connecting block 43-1 of the N+3th unit column form an integrated structure connected to each other.

[0177] In an exemplary embodiment, the orthographic projection of the third initial signal line 43 on the substrate at least partially overlaps the orthographic projection of the second scan signal line 22 on the substrate, and the third initial signal line 43 transmitting a constant voltage can shield the influence of the second scan signal line 22 on the pixel driving circuit, thereby improving the driving quality of the pixel driving circuit.

[0178] In an exemplary embodiment, the third conductive layers of the adjacent unit columns can be mirror-symmetrical with respect to the column boundary line. For example, the third conductive layer of the Nth unit column and the third conductive layer of the N+1th unit column can be mirror-symmetrical with respect to the column boundary line, and the third conductive layer of the N+1th unit column and the third conductive layer of the N+2th unit column can be mirror-symmetrical with respect to the column boundary line. In an exemplary embodiment, the shapes of the third conductive layers in the plurality of unit rows can be substantially the same.

[0179] (6) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming the sixth insulating layer pattern can include: depositing a sixth insulating thin film on the substrate on which the aforementioned patterns are formed, and patterning the fifth insulating thin film by using a patterning process to form a sixth insulating layer covering the third conductive layer, and the sixth insulating layer is provided with a plurality of vias, as shown in FIG. 14.

[0180] In an example embodiment, the plurality of vias of each circuit unit at least includes: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, and a seventeenth via V17.

[0181] In an example embodiment, a normal projection of the first via V1 on the substrate is within a range of a normal projection of the first region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the first via V1 are etched away to expose a surface of the first region of the first active layer, and the first via V1 is configured to allow the seventh connection electrode formed subsequently to connect with the first region of the first active layer through the via.

[0182] In an example embodiment, a normal projection of the second via V2 on the substrate is within a range of a normal projection of the second region of the first active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer within the second via V2 are etched away to expose a surface of the second region of the first active layer, and the second via V2 is configured to allow the second connection electrode formed subsequently to connect with the second region of the first active layer through the via.

[0183] In an example embodiment, a normal projection of the third via V3 on the substrate is within a range of a normal projection of the first region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the third via V3 are etched away to expose a surface of the first region of the second active layer, and the third via V3 is configured to allow the first connection electrode formed subsequently to connect with the first region of the second active layer through the via.

[0184] In an example embodiment, a normal projection of the fourth via V4 on the substrate is within a range of a normal projection of the second region of the second active layer on the substrate, the sixth insulating layer and the fifth insulating layer within the fourth via V4 are etched away to expose a surface of the second region of the second active layer, and the fourth via V4 is configured to allow the second connection electrode formed subsequently to connect with the second region of the second active layer through the via.

[0185] In an example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed subsequently is connected to the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer) through the via. The fifth via V5 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer), and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the fifth via V5 are etched away to expose the surface of the first region of the third active layer (also the second region of the fourth active layer and the second region of the fifth active layer).

[0186] In an example embodiment, the sixth via V6 is configured such that a second connection electrode formed subsequently is connected to the second region of the third active layer (also the first region of the sixth active layer) through the via. The sixth via V6 has a normal projection on the substrate within the range of the normal projection on the substrate of the second region of the third active layer (also the first region of the sixth active layer), and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the third active layer (also the first region of the sixth active layer).

[0187] In an example embodiment, the seventh via V7 is configured such that a third connection electrode formed subsequently is connected to the first region of the fourth active layer through the via. The seventh via V7 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the fourth active layer, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the seventh via V7 are etched away to expose the surface of the first region of the fourth active layer.

[0188] In an example embodiment, the eighth via V8 is configured such that a fourth connection electrode formed subsequently is connected to the first region of the fifth active layer through the via. The eighth via V8 has a normal projection on the substrate within the range of the normal projection on the substrate of the first region of the fifth active layer, and the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eighth via V8 are etched away to expose the surface of the first region of the fifth active layer. In an example embodiment, since the first regions of the fifth active layers of some adjacent circuit units in a unit row are connected to each other, the some adjacent circuit units can share one eighth via V8.

[0189] In an example embodiment, the ninth via V9 is located within the range of the normal projection of the second region of the sixth active layer (also the second region of the seventh active layer) on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the ninth via V9 are etched away to expose the surface of the second region of the sixth active layer (also the second region of the seventh active layer), and the ninth via V9 is configured to allow the sixth connection electrode formed subsequently to connect with the second region of the sixth active layer (also the second region of the seventh active layer) through the via.

[0190] In an example embodiment, the tenth via V10 is located within the range of the normal projection of the first region of the seventh active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the tenth via V10 are etched away to expose the surface of the first region of the seventh active layer, and the tenth via V10 is configured to allow the eighth connection electrode formed subsequently to connect with the first region of the seventh active layer through the via.

[0191] In an example embodiment, the eleventh via V11 is located within the range of the normal projection of the first region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the eleventh via V11 are etched away to expose the surface of the first region of the eighth active layer, and the eleventh via V11 is configured to allow the ninth connection electrode formed subsequently to connect with the first region of the eighth active layer through the via.

[0192] In an example embodiment, the twelfth via V12 is located within the range of the normal projection of the second region of the eighth active layer on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer, the third insulating layer and the second insulating layer within the twelfth via V12 are etched away to expose the surface of the second region of the eighth active layer, and the twelfth via V12 is configured to allow the fifth connection electrode formed subsequently to connect with the second region of the eighth active layer through the via.

[0193] In an example embodiment, the thirteenth via V13 is located within the range of the normal projection of the opening 33 on the substrate, the sixth insulating layer, the fifth insulating layer, the fourth insulating layer and the third insulating layer within the thirteenth via V13 are etched away to expose the surface of the first plate 31, and the thirteenth via V13 is configured to allow the first connection electrode formed subsequently to connect with the first plate 31 through the via.

[0194] In the example embodiment, the fourth via V4 is configured such that a fourth connection electrode formed later connects with the first initial connection block 41-1 via the fourth via V4. In the example embodiment, the fourth via V4 is located within the range of the orthogonal projection of the first initial connection block 41-1 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer within the fourth via V4 are etched away to expose the surface of the first initial connection block 41-1.

[0195] In the example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed later connects with the second initial connection block 42-1 via the fifth via V5. In the example embodiment, the fifth via V5 is located within the range of the orthogonal projection of the second initial connection block 42-1 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer within the fifth via V5 are etched away to expose the surface of the second initial connection block 42-1.

[0196] In the example embodiment, the fifth via V5 is configured such that a fifth connection electrode formed later connects with the second initial connection block 42-1 via the fifth via V5. In the example embodiment, the fifth via V5 is located within the range of the orthogonal projection of the second initial connection block 42-1 on the substrate, and the sixth insulating layer, the fifth insulating layer and the fourth insulating layer within the fifth via V5 are etched away to expose the surface of the second initial connection block 42-1.

[0197] In the example embodiment, the sixth via V6 is configured such that a sixth connection electrode formed later connects with the third initial connection block 43-1 via the sixth via V6. In the example embodiment, the sixth via V6 is located within the range of the orthogonal projection of the third initial connection block 43-1 on the substrate, and the sixth insulating layer within the sixth via V6 is etched away to expose the surface of the third initial connection block 43-1.

[0198] In the example embodiment, the sixth via V6 is configured such that a sixth connection electrode formed later connects with the third initial connection block 43-1 via the sixth via V6. In the example embodiment, the sixth via V6 is located within the range of the orthogonal projection of the third initial connection block 43-1 on the substrate, and the sixth insulating layer within the sixth via V6 is etched away to expose the surface of the third initial connection block 43-1.

[0199] In the example embodiment, the sixth via V6 is configured such that a sixth connection electrode formed later connects with the third initial connection block 43-1 via the sixth via V6. In the example embodiment, the sixth via V6 is located within the range of the orthogonal projection of the third initial connection block 43-1 on the substrate, and the sixth insulating layer within the sixth via V6 is etched away to expose the surface of the third initial connection block 43-1.

[0200] (7) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer can include: depositing a fourth conductive thin film on the substrate on which the aforementioned patterns are formed, patterning the fourth conductive thin film using a patterning process, and forming the fourth conductive layer disposed on the sixth insulating layer, as shown in FIGS. 15A and 15B, which is a plan view of the fourth conductive layer in FIG. 15A. In an exemplary embodiment, the fourth conductive layer can be referred to as a first source-drain metal (SD1) layer.

[0201] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least: a first connection electrode 51, a second connection electrode 52, a third connection electrode 53, a fourth connection electrode 54, a fifth connection electrode 55, a sixth connection electrode 56, a seventh connection electrode 57, an eighth connection electrode 58, and a ninth connection electrode 59.

[0202] In an exemplary embodiment, the first connection electrode 51 can have a shape of a bar whose main body portion extends along the second direction Y, a first end of the first connection electrode 51 is connected to the first region of the second active layer through the third via V3, and a second end of the first connection electrode 51 is connected to the first plate 31 through the thirteenth via V13 after extending along the second direction Y. In an exemplary embodiment, since the first plate 31 simultaneously serves as the gate electrode of the third transistor T3, the first connection electrode 51 makes the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first plate 31 have the same potential, thereby forming the first node N1 of the pixel driving circuit.

[0203] In an exemplary embodiment, the second connection electrode 52 can have a shape of a bar whose main body portion extends along the second direction Y, a first end of the second connection electrode 52 is connected to the second region of the first active layer through the second via V2, and a second end of the second connection electrode 52 is connected to the second region of the third active layer (also the first region of the sixth active layer) through the sixth via V6 after extending along the second direction Y, and a portion between the first end and the second end of the second connection electrode 52 is connected to the second region of the second active layer through the fourth via V4. In an exemplary embodiment, the second connection electrode 52 makes the second electrode of the first transistor T1, the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6 have the same potential, thereby forming the third node N3 of the pixel driving circuit.

[0204] In an exemplary embodiment, the third connection electrode 53 can have a shape of a block (e.g., a rectangle), and the third connection electrode 53 is connected to the first region of the fourth active layer through the seventh via V7, and is configured to be connected to a data signal line formed later.

[0205] In the example embodiment, the fourth connection electrode 54 can have a strip shape extending along the second direction Y, a first end of the fourth connection electrode 54 is connected to the first region of the fifth active layer through the eighth via V8, and a second end of the fourth connection electrode 54 is connected to the plate connection strip 34 through the fourteenth via V14 after extending in the opposite direction of the second direction Y. Since the plate connection strip 34 is connected to the second plate 32, the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in the circuit unit have the same potential.

[0206] In the example embodiment, since one eighth via V8 and one fourteenth via V14 are shared by part of two adjacent circuit units in one unit row, one fourth connection electrode 54 can be shared by part of the adjacent circuit units.

[0207] In the example embodiment, at least one circuit unit can further include a power supply connection block 54-1. The power supply connection block 54-1 can have a strip shape extending along the first direction X, a first end of the power supply connection block 54-1 is connected to the second end of the fourth connection electrode 54, and a second end of the power supply connection block 54-1 extends away from the fourth connection electrode 54 and is configured to be connected to a first power supply line formed subsequently.

[0208] In the example embodiment, the fourth connection electrode 54 and the power supply connection block 54-1 in at least one circuit unit can be an integrated structure connected to each other. Since one fourth connection electrode 54 can be shared by part of the adjacent circuit units, the fourth connection electrode 54 and the power supply connection block 54-1 in part of the two adjacent circuit units can be an integrated structure connected to each other, which can ensure that the first electrode of the fifth transistor T5 and the second plate 32 of the storage capacitor in part of the adjacent circuit units have the same potential, and is beneficial to improve the uniformity of the panel, avoid display defects of the display substrate, and ensure the display effect of the display substrate.

[0209] In the example embodiment, the fifth connection electrode 55 can have a strip shape with a main body extending along the second direction Y, a first end of the fifth connection electrode 55 is connected to the first region of the third active layer through the fifth via V5, and a second end of the fifth connection electrode 55 is connected to the second region of the eighth active layer through the twelfth via V12. In the example embodiment, since the first region of the third active layer is also the second region of the fourth active layer and the second region of the fifth active layer, the fifth connection electrode 55 makes the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second electrode of the fifth transistor T5, and the second electrode of the eighth transistor T8 have the same potential, and forms the second node N2 of the pixel driving circuit.

[0210] In an example embodiment, the sixth connection electrode 56 can be in a block shape (e.g., a rectangular shape), and the sixth connection electrode 56 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through a ninth via V9. In an example embodiment, the sixth connection electrode 56 can simultaneously serve as the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the sixth connection electrode 56 is configured to be connected to an anode connection electrode formed later.

[0211] In an example embodiment, the seventh connection electrode 57 can be in a strip shape extending along the first direction X, and a first end of the seventh connection electrode 57 is connected to the first region of the first active layer through a first via V1, and a second end of the seventh connection electrode 57 is connected to the first initial connection block 41-1 through a fifteenth via V15. In an example embodiment, since the first initial connection block 41-1 is connected to the first initial signal line 41, the seventh connection electrode 57 realizes writing of a first initial signal transmitted by the first initial signal line 41 to the first electrode of the first transistor T1.

[0212] In an example embodiment, since part of the adjacent circuit units share the same first initial connection block 41-1, the seventh connection electrodes 57 of part of the adjacent circuit units can be in an integrated structure connected to each other, which can ensure that the first electrodes of the first transistors T1 of part of the adjacent circuit units have the same potential, and is beneficial to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. For example, the seventh connection electrode 57 of the N+1 unit column and the seventh connection electrode 57 of the N+2 unit column are in an integrated structure connected to each other. For another example, the seventh connection electrode 57 of the N+3 unit column and the seventh connection electrode 57 of the N+4 unit column are in an integrated structure connected to each other.

[0213] In an example embodiment, the eighth connection electrode 58 can be in a strip shape extending along the first direction X, and a first end of the eighth connection electrode 58 is connected to the first region of the seventh active layer through a tenth via V10, and a second end of the eighth connection electrode 58 is connected to the second initial connection block 42-1 through a sixteenth via V16. In an example embodiment, since the second initial connection block 42-1 is connected to the second initial signal line 42, the eighth connection electrode 58 realizes writing of a second initial signal transmitted by the second initial signal line 42 to the first electrode of the seventh transistor T7.

[0214] In the example embodiment, the ninth connection electrode 59 can have a strip shape extending along the first direction X, a first end of the ninth connection electrode 59 is connected to the first region of the eighth active layer through the eleventh via V11, and a second end of the ninth connection electrode 59 is connected to the third initial connection block 43-1 through the seventeenth via V17. In the example embodiment, since the third initial connection block 43-1 is connected to the third initial signal line 43, the ninth connection electrode 59 realizes writing of the third initial signal transmitted by the third initial signal line 43 to the first electrode of the eighth transistor T8.

[0215] In the example embodiment, since the ninth connection electrodes 59 of the partially adjacent circuit units share the same third initial connection block 43-1, the ninth connection electrodes 59 of the partially adjacent circuit units can be an integrated structure connected to each other, which can ensure that the first electrodes of the eighth transistors T8 of the partially adjacent circuit units have the same potential, and is conducive to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate. For example, the ninth connection electrode 59 of the Nth unit column and the ninth connection electrode 59 of the N+1th unit column are an integrated structure connected to each other. For another example, the ninth connection electrode 59 of the N+2th unit column and the ninth connection electrode 59 of the N+3th unit column are an integrated structure connected to each other.

[0216] In the example embodiment, the fourth conductive layer of at least one circuit unit can further include a seventh connection block 57-1. The seventh connection block 57-1 can have a strip shape extending along the second direction Y and be connected to the seventh connection electrode 57, and the seventh connection block 57-1 is configured to be connected to the subsequently formed first initial connection line.

[0217] In the example embodiment, the seventh connection block 57-1 can be arranged between the partially adjacent circuit units, and the adjacent circuit units share the same seventh connection block 57-1, and the seventh connection electrodes 57 in the two circuit units and the shared seventh connection block 57-1 are an integrated structure connected to each other.

[0218] In the example embodiment, the seventh connection block 57-1 can be arranged between the N-1th unit column and the Nth unit column. For another example, the seventh connection block 57-1 can be arranged between the N+3th unit column and the N+4th unit column. For another example, the seventh connection block 57-1 can be arranged between the N+7th unit column and the N+8th unit column.

[0219] In the example embodiment, the fourth conductive layer of at least one circuit unit can further include an eighth connection block 58-1. The eighth connection block 58-1 can have a fold line shape extending along the second direction Y and be connected to the eighth connection electrode 58, and the eighth connection block 58-1 is configured to be connected to the subsequently formed second initial connection line.

[0220] In the example embodiment, the eighth connection blocks 58-1 of the partially adjacent circuit units can be connected to each other, and the eighth connection electrodes 58 and the eighth connection blocks 58-1 in the two circuit units are integrated structures connected to each other. For example, the eighth connection blocks 58-1 can be arranged in the (N+1)th unit column and the (N+2)th unit column. For another example, the eighth connection blocks 58-1 can be arranged in the (N+5)th unit column and the (N+6)th unit column. For still another example, the eighth connection blocks 58-1 can be arranged in the (N+9)th unit column and the (N+10)th unit column.

[0221] In the example embodiment, the fifth conductive layer can further include a plurality of first traces, and the first traces can have a shape of a straight line or a zigzag line extending along the first direction X and can be located between the first scan signal lines and the first initial signal lines 41.

[0222] In the example embodiment, at least one of the first traces can include a first power trace 91 and a horizontal sub-line, and a first break K1 can be arranged between the first power trace 91 and the horizontal sub-line. The first break K1 can cut off the first power trace 91 and the horizontal sub-line from each other, so that the first power trace 91 and the horizontal sub-line on both sides of the first break K1 are insulated from each other. For example, the first trace in the Mth unit row can include the second horizontal sub-line 81-2 and the first power trace 91 arranged in sequence along the first direction X. For another example, the first trace in the (M+1)th unit row can include the fourth horizontal sub-line 81-4 and the first power trace 91 arranged in sequence along the first direction X. For still another example, the first trace in the (M+2)th unit row can include the sixth horizontal sub-line 81-6 and the first power trace 91 arranged in sequence along the first direction X.

[0223] In the example embodiment, at least one of the first traces can include a first power trace 91 and a horizontal sub-line, and a first break K1 can be arranged between the first power trace 91 and the horizontal sub-line. The first break K1 can cut off the first power trace 91 and the horizontal sub-line from each other, so that the first power trace 91 and the horizontal sub-line on both sides of the first break K1 are insulated from each other. For example, the first trace in the Mth unit row can include the second horizontal sub-line 81-2 and the first power trace 91 arranged in sequence along the first direction X. For another example, the first trace in the (M+1)th unit row can include the fourth horizontal sub-line 81-4 and the first power trace 91 arranged in sequence along the first direction X. For still another example, the first trace in the (M+2)th unit row can include the sixth horizontal sub-line 81-6 and the first power trace 91 arranged in sequence along the first direction X.

[0224] In the example embodiment, the at least one first wire can include two transverse sub-wires and a first power supply wire 91, and a first break K1 can be arranged between the two transverse sub-wires, the first break K1 can cut off the two transverse sub-wires, so that the two transverse sub-wires on both sides of the first break K1 are insulated from each other. The first break K1 is arranged between the transverse sub-wire and the first power supply wire 91, and the first break K1 can cut off the transverse sub-wire and the first power supply wire 91. For example, the first wire in the M+3 unit row can include a seventh transverse sub-wire 81-7, a fifth transverse sub-wire 81-5, and a first power supply wire 91 arranged in sequence along the first direction X. For another example, the first wire in the M+4 unit row can include an eighth transverse sub-wire 81-8, a third transverse sub-wire 81-3, and a first power supply wire 91 arranged in sequence along the first direction X.

[0225] In the example embodiment, the first transverse sub-wire 81-1 in the M+5 unit row and the second transverse sub-wire 81-2 in the M unit row can be referred to as the first first data connection line 81, one end of the two transverse sub-wires can be connected together through the second vertical sub-wire formed subsequently, the other end of the first transverse sub-wire 81-1 is configured to be connected with the first vertical sub-wire formed subsequently, and the other end of the second transverse sub-wire 81-2 is configured to be connected with the data signal line formed subsequently.

[0226] In the example embodiment, the third transverse sub-wire 81-3 in the M+4 unit row and the fourth transverse sub-wire 81-4 in the M+1 unit row can be referred to as the second first data connection line 81, one end of the two transverse sub-wires can be connected together through the fourth vertical sub-wire formed subsequently, the other end of the third transverse sub-wire 81-3 is configured to be connected with the third vertical sub-wire formed subsequently, and the other end of the fourth transverse sub-wire 81-4 is configured to be connected with the data signal line formed subsequently.

[0227] In the example embodiment, the fifth transverse sub-wire 81-5 in the M+3 unit row and the sixth transverse sub-wire 81-6 in the M+2 unit row can be referred to as the third first data connection line 81, one end of the two transverse sub-wires can be connected together through the sixth vertical sub-wire formed subsequently, the other end of the fifth transverse sub-wire 81-5 is configured to be connected with the fifth vertical sub-wire formed subsequently, and the other end of the sixth transverse sub-wire 81-6 is configured to be connected with the data signal line formed subsequently.

[0228] In the example embodiment, the seventh transverse sub-wire 81-7 in the M+3 unit row can be referred to as the fourth first data connection line 81, the first end of the seventh transverse sub-wire 81-7 is configured to be connected with the seventh vertical sub-wire formed subsequently, and the second end of the seventh transverse sub-wire 81-7 is configured to be connected with the data signal line formed subsequently.

[0229] In the example embodiment, the eighth lateral sub-line 81-8 in the M+4th unit row can be referred to as a fifth first data connection line 81, a first end of the eighth lateral sub-line 81-8 is configured to be connected with a subsequently formed eighth vertical sub-line, and a second end of the eighth lateral sub-line 81-8 is configured to be connected with a subsequently formed data signal line.

[0230] In the example embodiment, the at least one circuit unit can further include a data transfer strip 83 and a first data connection block 84. The data transfer strip 83 can have a shape of a strip extending along the second direction Y, and the first data connection block 84 can have a shape of a block (e.g., a rectangle). The data transfer strip 83 and the first data connection block 84 can be disposed on a side of the lateral sub-line close to the second electrode plate 32. A first end of the data transfer strip 83 is connected with the side of the lateral sub-line close to the second electrode plate 32, and a second end of the data transfer strip 83 extends toward the second electrode plate 32 and is connected with the lateral sub-line. The first data connection block 84 is configured to be connected with a subsequently formed vertical sub-line.

[0231] In the exemplary embodiment, the data transfer bar 83 and the first data connection block 84 can be disposed between the circuit units adjacent in the first direction X. For example, in the Mth unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the Nth unit column and the N+lth unit column, the first data connection block 84 being connected to the second lateral sub-line 81-2 through the data transfer bar 83. For another example, in the M+lth unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+2th unit column and the N+3th unit column, the first data connection block 84 being connected to the fourth lateral sub-line 81-4 through the data transfer bar 83. For another example, in the M+2th unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+4th unit column and the N+5th unit column, the first data connection block 84 being connected to the sixth lateral sub-line 81-6 through the data transfer bar 83. For another example, in the M+3th unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+4th unit column and the N+5th unit column, the first data connection block 84 being connected to the seventh lateral sub-line 81-7 through the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+6th unit column and the N+7th unit column, the first data connection block 84 being connected to the fifth lateral sub-line 81-5 through the data transfer bar 83. For another example, in the M+4th unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+2th unit column and the N+3th unit column, the first data connection block 84 being connected to the eighth lateral sub-line 81-8 through the data transfer bar 83. Also, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+8th unit column and the N+9th unit column, the first data connection block 84 being connected to the third lateral sub-line 81-3 through the data transfer bar 83. For another example, in the M+5th unit row, the data transfer bar 83 and the first data connection block 84 can be disposed between the N+10th unit column and the N+11th unit column, the first data connection block 84 being connected to the first lateral sub-line 81-1 through the data transfer bar 83.

[0232] In the exemplary embodiment, the lateral sub-line, the data transfer bar 83 and the first data connection block 84 can be an integrated structure connected to each other in at least one of the circuit units.

[0233] In the exemplary embodiment, the at least one circuit unit can further include a second data connection block 85. The second data connection block 85 can have a block shape (e.g., a rectangular shape) and be connected to the lateral sub-line, the second data connection block 85 being configured to be connected to a subsequently formed vertical sub-line.

[0234] In an exemplary embodiment, the second data connection block 85 can be disposed between the circuit units adjacent in the first direction X. For example, in the Mth to (M+2)th unit rows, the second data connection block 85 is not disposed. For another example, in the (M+3)th unit row, the second data connection block 85 can be disposed between the (N+4)th and (N+5)th unit columns and connected with the fifth horizontal sub-line 81-5. For another example, in the (M+4)th unit row, the second data connection block 85 can be disposed between the (N+2)th and (N+3)th unit columns and connected with the third horizontal sub-line 81-3. For another example, in the (M+5)th unit row, the second data connection block 85 can be disposed between the (N)th and (N+1)th unit columns and connected with the first horizontal sub-line 81-1.

[0235] In an exemplary embodiment, in at least one circuit unit, the horizontal sub-line and the second data connection block 85 can be an integrated structure connected with each other.

[0236] In an exemplary embodiment, in at least one unit row, only the first data connection block 84 can be disposed. For example, in the Mth to (M+2)th unit rows, one horizontal sub-line (the second horizontal sub-line 81-2, the fourth horizontal sub-line 81-4 or the sixth horizontal sub-line 81-6) can be disposed, and one end of the horizontal sub-line is connected with the first data connection block 84.

[0237] In an exemplary embodiment, in at least one unit row, the first data connection block 84 and the second data connection block 85 can be disposed simultaneously, and the first data connection block 84 and the second data connection block 85 are disposed at two ends of the horizontal sub-line in the first direction X respectively. For example, in the (M+3)th unit row, two horizontal sub-lines (the fifth horizontal sub-line 81-5 and the seventh horizontal sub-line 81-7) are disposed, and in the (M+4)th unit row, two horizontal sub-lines (the third horizontal sub-line 81-3 and the eighth horizontal sub-line 81-8) are disposed. In each unit row, one end of one horizontal sub-line is connected with the first data connection block 84, and two ends of the other horizontal sub-line are connected with the first data connection block 84 and the second data connection block 85 respectively.

[0238] In an exemplary embodiment, relative to one horizontal sub-line, the first data connection block 84 and the second data connection block 85 can be located at two sides of the horizontal sub-line in the second direction Y respectively.

[0239] In an exemplary embodiment, the orthogonal projection of at least one horizontal sub-line on the substrate at least partially overlaps with the orthogonal projection of the second initial signal line 42 on the substrate, so that the second initial signal line 42 with constant potential can effectively shield the influence of voltage jump in the horizontal sub-line on the pixel driving circuit.

[0240] In an exemplary embodiment, in at least one unit row, the first wiring can only include the first power supply wiring 91.

[0241] In an example embodiment, the at least one circuit unit can further include a first dummy electrode 86, which can be in a block shape (e.g., a rectangular shape) and configured to be connected to a subsequently formed vertical sub-line. In the first direction X, the first dummy electrode 86 can be disposed between circuit units adjacent in the first direction X. In the second direction Y, the first dummy electrode 86 can be disposed on a side of the horizontal sub-line close to the second electrode plate 32.

[0242] In an example embodiment, the first dummy electrode 86 in one circuit unit can have a position and a connection structure substantially the same as those of the first data connection block 84 in another circuit unit, except that the first dummy electrode 86 is isolated and not connected to the horizontal sub-line or other electrodes. In an example embodiment, the first dummy electrode 86 can have a substantially same topography and connection structure as the first data connection block 84. The present disclosure can improve the uniformity of a subsequent etching process and achieve the same display effect under transmitted and reflected light at different positions, thereby eliminating shadows and effectively avoiding appearance defects and mura of the display substrate, and improving display quality and display performance.

[0243] In an example embodiment, the at least one circuit unit can further include a second dummy electrode 87, which can be in a block shape (e.g., a rectangular shape) and configured to be connected to a subsequently formed vertical sub-line. In the first direction X, the second dummy electrode 87 can be disposed between circuit units adjacent in the first direction X. In the second direction Y, the second dummy electrode 87 can be disposed on a side of the horizontal sub-line away from the second electrode plate 32.

[0244] In an example embodiment, the second dummy electrode 87 in one circuit unit can have a position and a connection structure substantially the same as those of the second data connection block 85 in another circuit unit, except that the second dummy electrode 87 is isolated and not connected to the horizontal sub-line or other electrodes. In an example embodiment, the second dummy electrode 87 can have a substantially same topography and connection structure as the second data connection block 85. The present disclosure can improve the uniformity of a subsequent etching process and achieve the same display effect under transmitted and reflected light at different positions, thereby eliminating shadows and effectively avoiding appearance defects and mura of the display substrate, and improving display quality and display performance.

[0245] In an example embodiment, the first dummy electrode 86 and the second dummy electrode 87 can be located on two sides of a horizontal sub-line in the second direction Y, respectively, with respect to the horizontal sub-line.

[0246] (8) Forming a first planar layer pattern. In an example embodiment, forming the first planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a first planar film, patterning the first planar film using a patterning process, forming a first planar layer covering the fourth conductive layer pattern, the first planar layer being provided with a plurality of vias, as shown in FIG. 16.

[0247] In an example embodiment, the plurality of vias in each circuit unit at least includes: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0248] In an example embodiment, the twenty-first via V21 has a projection on the substrate within the projection of the third connection electrode 53 on the substrate, the first planar layer in the twenty-first via V21 is etched away, exposing the surface of the third connection electrode 53, and the twenty-first via V21 is configured to allow a data signal line formed subsequently to pass through the via and connect with the third connection electrode 53.

[0249] In an example embodiment, the twenty-second via V22 has a projection on the substrate within the projection of the power connection block 54-1 of the fourth connection electrode 54 on the substrate, the first planar layer in the twenty-second via V22 is etched away, exposing the surface of the power connection block 54-1, and the twenty-second via V22 is configured to allow a first power line formed subsequently to pass through the via and connect with the power connection block 54-1.

[0250] In an example embodiment, the twenty-third via V23 has a projection on the substrate within the projection of the sixth connection electrode 56 on the substrate, the first planar layer in the twenty-third via V23 is etched away, exposing the surface of the sixth connection electrode 56, and the twenty-third via V23 is configured to allow an anode connection electrode formed subsequently to pass through the via and connect with the sixth connection electrode 56.

[0251] In an example embodiment, at least one circuit unit can further include a twenty-fourth via V24. The twenty-fourth via V24 has a projection on the substrate within the projection of the seventh connection block 57-1 on the substrate, the first planar layer in the twenty-fourth via V24 is etched away, exposing the surface of the seventh connection block 57-1, and the twenty-fourth via V24 is configured to allow a first initial connection line formed subsequently to pass through the via and connect with the seventh connection block 57-1.

[0252] In an example embodiment, the twenty-fourth via V24 can be disposed between partially adjacent circuit units. For example, the twenty-fourth via V24 can be disposed between the N+3th unit column and the N+4th unit column. For another example, the twenty-fourth via V24 can be disposed between the N+7th unit column and the N+8th unit column.

[0253] In an example embodiment, the at least one circuit unit can further include a twenty-fifth via V25. A projection of the twenty-fifth via V25 on the substrate is within a projection of the eighth connection block 58-1 on the substrate, a first planar layer within the twenty-fifth via V25 is etched away to expose a surface of the eighth connection block 58-1, and the twenty-fifth via V25 is configured to enable a subsequently formed second initial connection line to connect to the eighth connection block 58-1 through the via.

[0254] In an example embodiment, the twenty-fifth via V25 can be disposed between partially adjacent circuit units. For example, the twenty-fifth via V25 can be disposed between the N+1th unit column and the N+2th unit column. For another example, the twenty-fifth via V25 can be disposed between the N+5th unit column and the N+6th unit column. For yet another example, the twenty-fifth via V25 can be disposed between the N+9th unit column and the N+10th unit column.

[0255] In an example embodiment, the at least one circuit unit can further include a twenty-sixth via V26. A projection of the twenty-sixth via V26 on the substrate is within a projection of the first data connection block 84 on the substrate, a first planar layer within the twenty-sixth via V26 is etched away to expose a surface of the first data connection block 84, and the twenty-sixth via V26 is configured to enable a subsequently formed vertical sub-line to connect to the first data connection block 84 through the via.

[0256] In an example embodiment, the at least one circuit unit can further include a twenty-seventh via V27. A projection of the twenty-seventh via V27 on the substrate is within a projection of the second data connection block 85 on the substrate, a first planar layer within the twenty-seventh via V27 is etched away to expose a surface of the second data connection block 85, and the twenty-seventh via V27 is configured to enable a subsequently formed vertical sub-line to connect to the second data connection block 85 through the via.

[0257] In an example embodiment, the at least one circuit unit can further include a twenty-eighth via V28. A projection of the twenty-eighth via V28 on the substrate is within a projection of the first dummy electrode 86 on the substrate, a first planar layer within the twenty-eighth via V28 is etched away to expose a surface of the first dummy electrode 86, and the twenty-eighth via V28 is configured to enable a subsequently formed vertical sub-line to connect to the first dummy electrode 86 through the via.

[0258] In the example embodiment, the at least one circuit unit can further include a twenty-ninth via V29. A projection of the twenty-ninth via V29 on the substrate is located within a projection of the second dummy electrode 87 on the substrate, a first planar layer within the twenty-ninth via V29 is etched to expose a surface of the second dummy electrode 87, and the twenty-ninth via V29 is configured to connect a subsequently formed vertical sub-line to the second dummy electrode 87 through the via.

[0259] (9) Forming a fifth conductive layer pattern. In the example embodiment, forming the fifth conductive layer can include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planar layer, as shown in FIGS. 17A and 17B, which is a plan view of the fifth conductive layer in FIG. 17A. In the example embodiment, the fifth conductive layer can be referred to as a second source-drain metal (SD2) layer.

[0260] In the example embodiment, the fifth conductive layer of each circuit unit at least includes: a first power supply line 71, a data signal line 72, and an anode connection electrode 73.

[0261] In the example embodiment, the first power supply line 71 can have a shape of a straight line or a broken line with a main body portion extending along the second direction Y, and the first power supply line 71 is connected to the power supply connection block 54-1 through a twenty-second via V32. Since the power supply connection block 54-1 is connected to the fourth connection electrode 54, which is connected to the first region of the fifth active layer and the second plate 32 of the storage capacitor respectively, the first power supply line 71 writes the first power supply signal to the fifth transistor T5 and the second plate 32 of the storage capacitor.

[0262] In the example embodiment, the first power supply line 71 can be a broken line with non-uniform width, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the first power supply line and the data signal line.

[0263] In the example embodiment, a power supply shielding block 74 can be disposed on the first power supply line 71. The power supply shielding block 74 can have a shape of a block (e.g., a rectangle), can be disposed on the side of the first power supply line 71 close to the second transistor T2, and can be connected to the first power supply line 71. A projection of the power supply shielding block 74 on the substrate at least partially overlaps with a projection of the second active layer of the second transistor T2 on the substrate. In the example embodiment, the power supply shielding block 74 can shield the second active layer, block the light emitted by the light emitting device and the reflection of the film layer from shining on the oxide of the second transistor T2, and can prevent the oxide transistor from drifting due to light, thereby improving the electrical characteristics of the oxide transistor.

[0264] In the example embodiment, the first power supply line 71 and the power supply shielding block 74 have a projection on the substrate that at least partially overlaps with a projection of the first connection electrode 51 on the substrate, so that the first power supply line 71 and the power supply shielding block 74 having a constant potential can effectively shield the data voltage jump and other signals from affecting the first node N1 in the pixel driving circuit, avoiding the data voltage jump and other signals from affecting the potential of the first node N1, and improving the driving performance of the pixel driving circuit.

[0265] In the example embodiment, the first power supply line 71 and the power supply shielding block 74 in at least one circuit unit can be an integrated structure connected to each other.

[0266] In the example embodiment, the data signal line 72 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the data signal line 72 is connected to the third connection electrode 53 through the twenty-first via V21. Since the third connection electrode 53 is connected to the first region of the fourth active layer through the via, the data signal line 72 is connected to the first electrode of the fourth transistor T4, and the data signal line 72 can write a data signal to the first electrode of the fourth transistor T4.

[0267] In the example embodiment, the anode connection electrode 73 can have a shape of a strip extending along the second direction Y, and the anode connection electrode 73 is connected to the sixth connection electrode 56 through the twenty-third via V23. The anode connection electrode 73 is configured to be connected to a subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the sixth active layer and the second region of the seventh active layer through the via, the subsequently formed anode can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7, and the pixel driving circuit can drive the light emitting device to emit light.

[0268] In the example embodiment, the fifth conductive layer of at least one circuit unit can further include a first initial connection line 61. The first initial connection line 61 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the first initial connection line 61 is connected to the seventh connection block 57-1 through the twenty-fourth via V24. Since the seventh connection block 57-1 is connected to the seventh connection electrode 57, and the seventh connection electrode 57 is connected to the first initial signal line 41, the first initial signal line 41 and the first initial connection line 61 are connected to each other, and the first initial signal line 41 and the first initial connection line 61 form a mesh-shaped network structure for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial signal line, reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improves the display uniformity, and improves the display quality and display performance.

[0269] In the example embodiment, the first initial connection line 61 can be arranged between two first power lines 71 of part of adjacent unit columns, and four first power lines 71 can be arranged between two first initial connection lines 61 adjacent in the first direction X. For example, the first initial connection line 61 can be arranged between the first power line 71 of the N+3th unit column and the first power line 71 of the N+4th unit column. For another example, the first initial connection line 61 can be arranged between the first power line 71 of the N+7th unit column and the first power line 71 of the N+8th unit column.

[0270] In the example embodiment, the fifth conductive layer of the at least one circuit unit can further include a second initial connection line 62. The second initial connection line 62 can have a shape of a straight line or a broken line with a main body extending along the second direction Y, and the second initial connection line 62 is connected to the eighth connection block 58-1 through the twenty-fifth via hole V25. Since the eighth connection block 58-1 is connected to the eighth connection electrode 58, and the eighth connection electrode 58 is connected to the second initial signal line 42, the mutual connection between the second initial signal line 42 extending along the first direction X and the second initial connection line 62 extending along the second direction Y is achieved, and the second initial signal line 42 and the second initial connection line 62 form a meshed communication structure for transmitting the second initial signal in a meshed manner, which can effectively reduce the resistance of the second initial signal line, reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance.

[0271] In the example embodiment, the second initial connection line 62 can be arranged between two first power lines 71 of part of adjacent unit columns, and four first power lines 71 can be arranged between two second initial connection lines 62 adjacent in the first direction X. For example, the second initial connection line 62 can be arranged between the first power line 71 of the N+1th unit column and the first power line 71 of the N+2th unit column. For another example, the second initial connection line 62 can be arranged between the first power line 71 of the N+5th unit column and the first power line 71 of the N+6th unit column. For still another example, the second initial connection line 62 can be arranged between the first power line 71 of the N+9th unit column and the first power line 71 of the N+10th unit column.

[0272] In the example embodiment, the first initial connection line 61 and the second initial connection line 62 can be arranged alternately in the first direction X, one second initial connection line 62 can be arranged between two first initial connection lines 61 adjacent in the first direction X, and one first initial connection line 61 can be arranged between two second initial connection lines 62 adjacent in the first direction X.

[0273] In some possible implementation manners, the fifth conductive layer of the at least one circuit unit can further include a third initial connection line extending along the second direction Y, and the third initial connection line can be connected to the third initial signal line through a via hole to form a meshed communication structure for transmitting the third initial signal, which is not limited in the present disclosure.

[0274] In the example implementation, the fifth conductive layer can further include a plurality of second wires, the second wire can be in a straight line shape or a broken line shape with the body part extending along the second direction Y, and can be located between two data signal lines 72 of the partial adjacent unit columns. Two first power supply lines 71 and two data signal lines 72 can be arranged between two second wires adjacent in the first direction X. For example, the second wire can be located between the data signal line 72 of the Nth unit column and the data signal line 72 of the (N+1)th unit column. For another example, the second wire can be located between the data signal line 72 of the (N+2)th unit column and the data signal line 72 of the (N+3)th unit column. For another example, the second wire can be located between the data signal line 72 of the (N+4)th unit column and the data signal line 72 of the (N+5)th unit column.

[0275] In the example implementation, the at least one second wire can include a vertical sub-line and a second power supply wire 92, and a second break K2 can be arranged between the vertical sub-line and the second power supply wire 92, so that the vertical sub-line and the second power supply wire 92 on both sides of the second break K2 are insulated from each other. For example, the second wire located between the (N+6)th unit column and the (N+7)th unit column can include the second power supply wire 92 and the fifth vertical sub-line 82-5 arranged in sequence along the second direction Y. For another example, the second wire located between the (N+8)th unit column and the (N+9)th unit column can include the second power supply wire 92 and the third vertical sub-line 82-3 arranged in sequence along the second direction Y. For another example, the second wire located between the (N+10)th unit column and the (N+11)th unit column can include the second power supply wire 92 and the first vertical sub-line 82-1 arranged in sequence along the second direction Y.

[0276] In the example implementation, the at least one second wire can include a vertical sub-line and two second power supply wires 92, and a second break K2 can be arranged between the vertical sub-line and each of the two second power supply wires 92, so that the vertical sub-line and the second power supply wires 92 are cut off by the second break K2. For example, the second wire located between the Nth unit column and the (N+1)th unit column can include the second power supply wire 92, the second vertical sub-line 82-2, and the second power supply wire 92 arranged in sequence along the second direction Y.

[0277] In the example embodiment, the at least one second wire can include two vertical sub-wires and a second power supply wire 92, and a second break K2 can be arranged between the two vertical sub-wires, so that the two vertical sub-wires on both sides of the second break K2 are insulated from each other. The second break K2 is arranged between the vertical sub-wires and the second power supply wire 92, so that the vertical sub-wires and the second power supply wire 92 are cut off by the second break K2. For example, the second wire between the N+2th unit column and the N+3th unit column can include the second power supply wire 92, the fourth vertical sub-wire 82-4 and the eighth vertical sub-wire 82-8 arranged in sequence along the second direction Y. For another example, the second wire between the N+4th unit column and the N+5th unit column can include the second power supply wire 92, the sixth vertical sub-wire 82-6 and the seventh vertical sub-wire 82-7 arranged in sequence along the second direction Y.

[0278] In the example embodiment, one end of the at least one vertical sub-wire is configured to extend to the binding area and be connected with the data lead-out wire, and the other end is connected with the first data connection block 84 through the twenty-sixth via V26, so that the connection between one vertical sub-wire and one horizontal sub-wire is realized.

[0279] In the example embodiment, one end of the at least one vertical sub-wire is connected with the second data connection block 85 through the twenty-seventh via V27, and the other end is connected with the first data connection block 84 through the twenty-sixth via V26, so that the connection between one vertical sub-wire and two horizontal sub-wires is realized.

[0280] In the example embodiment, the at least one vertical sub-wire is also connected with the first dummy electrode 86 through the twenty-eighth via V28, so that the same topography and connection structure are presented at each position of the display substrate.

[0281] In the example embodiment, the at least one vertical sub-wire is also connected with the second dummy electrode 87 through the twenty-ninth via V29, so that the same topography and connection structure are presented at each position of the display substrate.

[0282] In the example embodiment, the first vertical sub-wire 82-1 between the N+10th unit column and the N+11th unit column and the second vertical sub-wire 82-2 between the Nth unit column and the N+1th unit column can be referred to as the first second data connection line 82, the first vertical sub-wire 82-1 is connected with the first horizontal sub-wire 81-1, and the second vertical sub-wire 82-2 is connected with the first horizontal sub-wire 81-1 and the second horizontal sub-wire 81-2 respectively.

[0283] In an example embodiment, the third vertical sub-line 82-3 between the N+8thunit column and the N+9thunit column and the fourth vertical sub-line 82-4 between the N+2ndunit column and the N+3rdunit column can be referred to as the second second data connection line 82, the third vertical sub-line 82-3 is connected with the third horizontal sub-line 81-3, and the fourth vertical sub-line 82-4 is connected with the third horizontal sub-line 81-3 and the fourth horizontal sub-line 81-4, respectively.

[0284] In an example embodiment, the fifth vertical sub-line 82-5 between the N+6thunit column and the N+7thunit column and the sixth vertical sub-line 82-6 between the N+4thunit column and the N+5thunit column can be referred to as the third second data connection line 82, the fifth vertical sub-line 82-5 is connected with the fifth horizontal sub-line 81-5, and the sixth vertical sub-line 82-6 is connected with the fifth horizontal sub-line 81-5 and the sixth horizontal sub-line 81-6, respectively.

[0285] In an example embodiment, the seventh vertical sub-line 82-7 between the N+4thunit column and the N+5thunit column can be referred to as the fourth second data connection line 82, and the seventh vertical sub-line 82-7 is connected with the seventh horizontal sub-line 81-7.

[0286] In an example embodiment, the eighth vertical sub-line 82-8 between the N+2ndunit column and the N+3rdunit column can be referred to as the fifth second data connection line 82, and the eighth vertical sub-line 82-8 is connected with the eighth horizontal sub-line 81-8.

[0287] FIG. 17C is a schematic diagram of the connection of horizontal sub-lines and vertical sub-lines in an example embodiment of the present disclosure. As shown in FIGS. 17A, 17B, and 17C, the plurality of data connection lines can include at least a first data connection line 80A, a second data connection line 80B, a third data connection line 80C, a fourth data connection line 80D, and a fifth data connection line 80E.

[0288] In an example embodiment, the first data connection line 80A can include at least a first first data connection line and a first second data connection line, the first first data connection line can include at least a first horizontal sub-line 81-1 and a second horizontal sub-line 81-2, and the first second data connection line can include at least a first vertical sub-line 82-1 and a second vertical sub-line 82-2. The first horizontal sub-line 81-1 can be disposed in the M+5thunit row, the second horizontal sub-line 81-2 can be disposed in the Mthunit row, the first vertical sub-line 82-1 can be disposed between the N+10thunit column and the N+11thunit column, and the second vertical sub-line 82-2 can be disposed between the Nthunit column and the N+1stunit column.

[0289] In the example embodiment, the first end of the first vertical sub-line 82-1 is connected with one data lead-out line in the binding area, and the second end of the first vertical sub-line 82-1 is connected with the first end of the first horizontal sub-line 81-1 through the first data connection block 84 after extending in the opposite direction of the second direction Y. The second end of the first horizontal sub-line 81-1 is connected with the first end of the second vertical sub-line 82-2 through the second data connection block 85 after extending in the first direction X or the opposite direction of the first direction X. The second end of the second vertical sub-line 82-2 is connected with the first end of the second horizontal sub-line 81-2 through the first data connection block 84 after extending in the opposite direction of the second direction Y. The second end of the second horizontal sub-line 81-2 is connected with one data signal line after extending in the first direction X or the opposite direction of the first direction X.

[0290] In the example embodiment, the second data connection line 80B can include at least a second first data connection line and a second second data connection line. The second first data connection line can include at least a third horizontal sub-line 81-3 and a fourth horizontal sub-line 81-4, and the second second data connection line can include at least a third vertical sub-line 82-3 and a fourth vertical sub-line 82-4. The first horizontal sub-line 81-1 can be arranged in the M+4th unit row, the fourth horizontal sub-line 81-4 can be arranged in the M+1th unit row, the third vertical sub-line 82-3 can be arranged between the N+8th unit column and the N+9th unit column, and the fourth vertical sub-line 82-4 can be arranged between the N+2th unit column and the N+3th unit column.

[0291] In the example embodiment, the first end of the first vertical sub-line 82-1 is connected with one data lead-out line in the binding area, and the second end of the first vertical sub-line 82-1 is connected with the first end of the first horizontal sub-line 81-1 through the first data connection block 84 after extending in the opposite direction of the second direction Y. The second end of the first horizontal sub-line 81-1 is connected with the first end of the second vertical sub-line 82-2 through the second data connection block 85 after extending in the first direction X or the opposite direction of the first direction X. The second end of the second vertical sub-line 82-2 is connected with the first end of the second horizontal sub-line 81-2 through the first data connection block 84 after extending in the opposite direction of the second direction Y. The second end of the second horizontal sub-line 81-2 is connected with one data signal line after extending in the first direction X or the opposite direction of the first direction X.

[0292] In an exemplary embodiment, the third data connection line 80C can include at least a third first data connection line and a third second data connection line, the third first data connection line can include at least a fifth horizontal sub-line 81-5 and a sixth horizontal sub-line 81-6, and the third second data connection line can include at least a fifth vertical sub-line 82-5 and a sixth vertical sub-line 82-6. The fifth horizontal sub-line 81-5 can be disposed in the M+3 unit row, the sixth horizontal sub-line 81-6 can be disposed in the M+2 unit row, the fifth vertical sub-line 82-5 can be disposed between the N+6 unit column and the N+7 unit column, and the sixth vertical sub-line 82-6 can be disposed between the N+4 unit column and the N+5 unit column.

[0293] In an exemplary embodiment, a first end of the fifth vertical sub-line 82-5 is connected with another data lead-out line in the binding area, and a second end of the fifth vertical sub-line 82-5 extends in the opposite direction of the second direction Y and is connected with a first end of the fifth horizontal sub-line 81-5 through the first data connection block 84. A second end of the fifth horizontal sub-line 81-5 extends in the first direction X or the opposite direction of the first direction X and is connected with a first end of the sixth vertical sub-line 82-6 through the second data connection block 85. A second end of the sixth vertical sub-line 82-6 extends in the opposite direction of the second direction Y and is connected with a first end of the sixth horizontal sub-line 81-6 through the first data connection block 84. A second end of the sixth horizontal sub-line 81-6 extends in the first direction X or the opposite direction of the first direction X and is connected with another data signal line.

[0294] In an exemplary embodiment, the fourth data connection line 80D can include at least a fourth first data connection line and a fourth second data connection line, the fourth first data connection line can include at least a seventh horizontal sub-line 81-7, and the fourth second data connection line can include at least a seventh vertical sub-line 82-7. The seventh horizontal sub-line 81-7 can be disposed in the M+3 unit row, and the seventh vertical sub-line 82-7 can be disposed between the N+4 unit column and the N+5 unit column.

[0295] In an exemplary embodiment, a first end of the seventh vertical sub-line 82-7 is connected with another data lead-out line in the binding area, and a second end of the seventh vertical sub-line 82-7 extends in the opposite direction of the second direction Y and is connected with the seventh horizontal sub-line 81-7 through the first data connection block 84. A second end of the seventh horizontal sub-line 81-7 extends in the first direction X or the opposite direction of the first direction X and is connected with another data signal line.

[0296] In an example embodiment, the fifth data connection line 80E can include at least a fifth first data connection line and a fifth second data connection line, the fifth first data connection line can include at least an eighth horizontal sub-line 81-8, and the fifth second data connection line can include at least an eighth vertical sub-line 82-8. The eighth horizontal sub-line 81-8 can be disposed in the M+4th unit row, and the eighth vertical sub-line 82-8 can be disposed between the N+2th unit column and the N+3th unit column.

[0297] In an example embodiment, a first end of the eighth vertical sub-line 82-8 is connected with another data lead-out line in the binding area, and a second end of the eighth vertical sub-line 82-8 is connected with the eighth horizontal sub-line 81-8 through the first data connection block 84 after extending in the opposite direction of the second direction Y. A second end of the eighth horizontal sub-line 81-8 is connected with another data signal line after extending in the first direction X or the opposite direction of the first direction X.

[0298] In an example embodiment, the first power supply line 91 and the second power supply line 92 can be connected with each other to form a mesh communication structure, which is not limited in the present disclosure.

[0299] In an example embodiment, the first power supply line 91 and the second power supply line 92 can be connected with a power supply lead line transmitting a second power supply signal through the frame area or the binding area, so as to realize a second power supply line in a panel (SIP) structure. This not only can effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display performance, but also can greatly reduce the width of the frame power supply lead line, greatly reduce the frame width, improve the screen ratio, and be conducive to realizing a full-screen display.

[0300] In an example embodiment, the first power supply line 71 of the adjacent unit columns can be mirror-symmetrical relative to the column boundary line, and the data signal line 72 of the adjacent unit columns can be mirror-symmetrical relative to the column boundary line. In an example embodiment, the shapes of the first power supply line 71 and the data signal line 72 in the plurality of unit rows can be substantially the same.

[0301] In an example embodiment, the orthographic projection of at least one second line on the substrate at least partially overlaps the orthographic projection of the column boundary line on the substrate.

[0302] In an example embodiment, in the first direction X, one second line and two data signal lines 72 can be disposed between two first power supply lines 71 of adjacent unit columns, the two first power supply lines 71 can be mirror-symmetrical relative to the second line, and the two data signal lines 72 can be mirror-symmetrical relative to the second line.

[0303] In the exemplary embodiments, in the first direction X, two first power supply lines 71 and two data signal lines 72 can be arranged between two adjacent second traces, and the two second traces can be mirror-symmetrical relative to the column boundary line.

[0304] (10) Forming a second planar layer pattern. In the exemplary embodiments, forming the second planar layer pattern can include: on the substrate on which the aforementioned patterns are formed, coating a second planar film, patterning the second planar film by using a patterning process, forming a second planar layer covering the fifth conductive layer pattern, and the second planar layer being provided with a plurality of anode vias V30, as shown in FIG. 18.

[0305] In the exemplary embodiments, the orthographic projection of each circuit unit's anode via V30 on the substrate is within the range of the orthographic projection of the anode connecting electrode 73 on the substrate, the second planar layer in the anode via V30 is removed, exposing the surface of the anode connecting electrode 73, and the anode via V30 is configured to enable the anode to be connected to the anode connecting electrode 73 through the via in the subsequent formation.

[0306] Up to now, the driving circuit layer has been prepared on the substrate. In a plane parallel to the display substrate, the driving circuit layer can include a plurality of circuit units, each of which can include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a third initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0307] In a plane perpendicular to the display substrate, the driving circuit layer can include, in sequence on the substrate, a first insulating layer, a first semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a second semiconductor layer, a fifth insulating layer, a third conductive layer, a sixth insulating layer, a fourth conductive layer, a first planar layer, a fifth conductive layer, and a second planar layer. The first semiconductor layer can include at least an active layer of a first transistor, a third transistor to an eighth transistor, the first conductive layer can include at least a first scan signal line, a second scan signal line, a third scan signal line, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer can include at least a first initial signal line and a second plate of the storage capacitor, the second semiconductor layer can include at least an active layer of a second transistor, the third conductive layer can include at least a second initial signal line, a third initial signal line, and a fourth scan signal line, the fourth conductive layer can include at least a first data connecting line and a plurality of connecting electrodes, and the fifth conductive layer can include at least a first power supply line, a data signal line, a first initial signal line, a second initial signal line, and a second data connecting line.

[0308] In an exemplary embodiment, the substrate can be a flexible substrate, or can be a rigid substrate. The rigid substrate can include, but is not limited to, one or more of glass, quartz, and the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The material of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the like, and the material of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), or the like, for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer can be amorphous silicon (a-si).

[0309] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer can be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above-mentioned metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, or the like. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multi-layer, or a composite layer. The first planar layer and the second planar layer can be an organic material, such as resin, or the like.

[0310] In an exemplary embodiment, the pixel driving circuits in two adjacent circuit units in one unit row can be substantially mirror-symmetrical with respect to a column boundary line, which is a straight line located between the two adjacent circuit units and extending along the second direction Y. For example, the pixel driving circuit of the Nth unit column and the pixel driving circuit of the (N+1)th unit column can be mirror-symmetrical with respect to the column boundary line. For another example, the pixel driving circuit of the (N+1)th unit column and the pixel driving circuit of the (N+2)th unit column can be mirror-symmetrical with respect to the column boundary line.

[0311] In the exemplary embodiments, the pixel driving circuit in the two adjacent circuit units can be substantially mirror-symmetrical with respect to the column boundary line, which can include any one or more of the following: the first semiconductor layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the first conductive layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the second conductive layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the second semiconductor layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the third conductive layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, the fourth conductive layer (except the first wiring and the data transfer bar) in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line, and the fifth conductive layer in the two adjacent circuit units in one unit row can be mirror-symmetrical with respect to the column boundary line (except the second wiring and the anode connecting electrode).

[0312] In the exemplary embodiments, after the preparation of the driving circuit layer is completed, the light-emitting structure layer can be prepared on the driving circuit layer, and the preparation process of the light-emitting structure layer can include the following operations.

[0313] [According to Rule 91 Correction 08.05.2025](11) Forming an anode conductive layer pattern. In the exemplary embodiments, forming the anode conductive layer pattern can include: on the substrate on which the aforementioned pattern is formed, depositing an anode conductive thin film, patterning the anode conductive thin film by using a patterning process, and forming an anode conductive layer disposed on the second planar layer, the anode conductive layer including at least a plurality of anode patterns, as shown in FIGS. 19A and 19B, FIG. 19B is a plan view of the anode conductive layer in FIG. 19A.

[0314] In the exemplary embodiments, the plurality of anode patterns can include a first anode 90A located at a red light-emitting unit that emits red light, a second anode 90B located at a blue light-emitting unit that emits blue light, a third anode 90C located at a first green light-emitting unit that emits green light, and a fourth anode 90D located at a second green light-emitting unit that emits green light, and the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can be connected to the anode connecting electrode 73 of the circuit unit in which they are located through an anode via V30, respectively.

[0315] In an example embodiment, at least one of the first anode 90A, the second anode 90B, the third anode 90C, and the fourth anode 90D can include an anode main portion and an anode connection portion connected to each other, the anode main portion can have a shape of a rhombus, a corner portion of the rhombus can be provided with a chamfer having a circular arc shape, the anode connection portion can have a shape of a bar, a first end of the anode connection portion is connected to the anode main portion, and a second end of the anode connection portion extends in a direction away from the anode main portion and is connected to the anode connection electrode 73 through the anode via hole V30.

[0316] In an example embodiment, the first anode 90A, the third anode 90C, and the fourth anode 90D do not overlap with the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) in a projection on the substrate.

[0317] In an example embodiment, the first anode 90A, the third anode 90C, and the fourth anode 90D do not overlap with the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) in a projection on the substrate.

[0318] In an example embodiment, the first anode 90A, the third anode 90C, and the fourth anode 90D do not overlap with the first data connection block 84 (or the first dummy electrode 86) and the second data connection block 85 (or the second dummy electrode 87) in a projection on the substrate.

[0319] In an example embodiment, the second anode 90B at least partially overlaps with the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) in a projection on the substrate.

[0320] In an example embodiment, the second anode 90B at least partially overlaps with the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) in a projection on the substrate.

[0321] In an example embodiment, the second anode 90B at least partially overlaps with the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) in a projection on the substrate.

[0322] In an example embodiment, the second anode 90B can have an anode center line, which can be a polyline passing through the geometric center of the anode main body portion of the second anode and extending along the first direction X. The twenty-sixth via hole V26 (or the twenty-eighth via hole V28) can be located on one side of the second direction Y of the anode center line, and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) can be located on the opposite side of the second direction Y of the anode center line, i.e., the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) can be arranged above and below the anode center line.

[0323] In an example embodiment, in the second direction Y, the geometric center of the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the anode center line have a first distance, and the geometric center of the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) and the anode center line have a second distance, which can be a polyline passing through the geometric center of the anode main body portion of the second anode and extending along the first direction X.

[0324] In an example embodiment, the ratio of the first distance to the second distance can be about 0.9 to 1.1, i.e., the twenty-sixth via hole V26 (or the twenty-eighth via hole V28) and the twenty-seventh via hole V27 (or the twenty-ninth via hole V29) can correspond to the positions above and below the anode center line.

[0325] In an example embodiment, the ratio of the first distance to the second distance can be about 1.0.

[0326] In an example embodiment, the anode conductive layer can adopt a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or can adopt a multi-layer composite structure, such as ITO / Ag / ITO, etc.

[0327] In an example embodiment, the subsequent preparation process can include: first forming a pixel definition layer, the pixel definition layer being provided with a plurality of pixel openings, and the plurality of pixel openings respectively exposing the first anode, the second anode, the third anode and the fourth anode. Then, an organic light-emitting layer is formed by using an evaporation or inkjet printing process, and then a cathode is formed on the organic light-emitting layer, and then a packaging structure layer is formed, which can include a first packaging layer, a second packaging layer and a third packaging layer stacked together, the first packaging layer and the third packaging layer can adopt inorganic materials, and the second packaging layer can adopt organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer, which can ensure that external water vapor cannot enter the light-emitting structure layer.

[0328] The display substrate provided by the exemplary embodiments of the present disclosure effectively reduces the difference in the number of unit columns coupled by data connection lines in different unit rows, effectively alleviates or even eliminates the moiré pattern in the two corners of the display area close to the binding area.

[0329] In the exemplary embodiments, taking one of the first data connection lines 81 far from the binding area in FIG. 6 as an example, after the first data connection line 81 is split into the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, although the number of unit columns coupled by the first data connection line 81 in FIG. 6 is basically the same as the sum of the number of unit columns coupled by the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2, the first horizontal sub-line 81-1 and the second horizontal sub-line 81-2 are arranged in different unit rows, so that the number of unit columns coupled by the first horizontal sub-line 81-1 in the unit row where the first horizontal sub-line 81-1 is arranged is less, the number of unit columns coupled by the second horizontal sub-line 81-2 in the unit row where the second horizontal sub-line 81-2 is arranged is less, and the number of unit columns coupled by the first horizontal sub-line 81-1 is close to the number of unit columns coupled by the second horizontal sub-line 81-2, thereby effectively reducing the difference in the number of unit columns coupled by data connection lines in different unit rows.

[0330] In the exemplary embodiments, taking one of the first data connection lines 81 close to the binding area in FIG. 6 as an example, although the first data connection line has a shorter extension length and is coupled with fewer unit columns, since other first data connection lines are split into two horizontal sub-lines, the horizontal sub-line of other data connection lines is arranged in the unit row where the first data connection line is arranged, thereby increasing the number of unit columns coupled by data connection lines in the unit row and making the number of unit columns coupled by data connection lines in the unit row close to the number of unit columns coupled by data connection lines in other unit rows, thereby effectively reducing the difference in the number of unit columns coupled by data connection lines in different unit rows.

[0331] As can be seen from FIG. 6 and the first area 110 of the present disclosure, the present disclosure effectively reduces the area of the first area (FIP area) by splitting the first data connection line with a longer extension length into two horizontal sub-lines and splitting the second data connection line with a longer extension length into two vertical sub-lines, which is conducive to increasing the number of power lines, reducing the power signal voltage drop, effectively improving the display uniformity, and improving the display quality and display performance.

[0332] The embodiment of the present disclosure realizes the FIP structure by arranging the data connection line in the display area, and the data lead-out line of the binding area is connected with the data signal line through the data connection line, so that the inclined line in the shape of a fan does not need to be arranged in the lead-out line area, the length of the lead-out line area is effectively reduced, the lower frame width is greatly reduced, the screen-to-body ratio is improved, and the full-screen display is facilitated.

[0333] The embodiment of the present disclosure realizes the SIP structure by arranging the first power supply trace and the second power supply trace in the display area, which can not only effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of the full-screen display.

[0334] The embodiment of the present disclosure realizes the SIP structure by arranging the first power supply trace and the second power supply trace in the display area, which can not only effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of the full-screen display.

[0335] The embodiment of the present disclosure realizes the SIP structure by arranging the first power supply trace and the second power supply trace in the display area, which can not only effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of the full-screen display.

[0336] The embodiment of the present disclosure realizes the SIP structure by arranging the first power supply trace and the second power supply trace in the display area, which can not only effectively reduce the resistance of the second power supply line, reduce the voltage drop of the second power supply signal, realize low power consumption, effectively improve the uniformity of the second power supply signal in the display substrate, effectively improve the display uniformity, improve the display quality and display quality, but also can greatly reduce the width of the frame power supply lead, greatly reduce the frame width, improve the screen-to-body ratio, and facilitate the realization of the full-screen display.

[0337] The preparation process of the present disclosure can be well compatible with the existing preparation process, the process is simple to realize, easy to implement, high in production efficiency, low in production cost and high in yield.

[0338] The structure and its preparation process shown in the foregoing of the present disclosure are only an exemplary illustration, and in the exemplary embodiment, the corresponding structure can be changed, and the patterning process can be increased or reduced, which is not limited herein.

[0339] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light-emitting diode display (Micro LED or Mini LED), or a quantum dot light-emitting diode display (QDLED), etc., which are not limited herein.

[0340] The present disclosure also provides a method for manufacturing a display substrate to manufacture the display substrate provided in the above embodiments. In an exemplary embodiment, the display substrate includes a display area and a binding area disposed on one side of the display area, the display area includes a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, and at least one circuit unit includes a pixel driving circuit; the manufacturing method can include:

[0341] forming a plurality of data signal lines and a plurality of data connection lines in the display area, and forming a plurality of data lead-out lines in the binding area, the data signal lines are configured to provide data signals to the pixel driving circuit, the data signal lines are connected to the data lead-out lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines are disposed in different unit rows, the two vertical sub-lines are disposed in different unit columns, and the first direction and the second direction intersect.

[0342] Although the embodiments disclosed in the present disclosure are as described above, it should be noted that the above embodiments are merely exemplary and not limiting. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions can be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a display area and a binding area arranged at one side of the display area, the display area comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit, the binding area comprising at least a plurality of data lead-out lines; the display area further comprising a plurality of data signal lines and a plurality of data connection lines, the data signal lines being configured to provide data signals to the pixel driving circuit, the data signal lines being connected to the data lead-out lines through the data connection lines; at least one data connection line comprising at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines being arranged in different unit rows, the two vertical sub-lines being arranged in different unit columns, the first direction and the second direction intersecting. 2.The display substrate of claim 1, wherein, At least two horizontal sub-lines are arranged in at least one unit row, the two horizontal sub-lines connecting different vertical sub-lines. 3.The display substrate of claim 1, wherein, At least two vertical sub-lines are arranged in at least one unit column, the two vertical sub-lines connecting different horizontal sub-lines. 4.The display substrate of claim 1, wherein, A normal projection of at least one horizontal sub-line on the display substrate at least partially overlaps with a normal projection of at least one vertical sub-line on the display substrate. 5.The display substrate of claim 1, wherein, In a direction perpendicular to the display substrate, the display area comprises a plurality of conductive layers, the two horizontal sub-lines being arranged in the same conductive layer, the two vertical sub-lines being arranged in the same conductive layer, the horizontal sub-line and the vertical sub-line being arranged in different conductive layers. 6.The display substrate of claim 5, wherein, The plurality of conductive layers comprise at least a first source-drain metal layer arranged on a substrate and a second source-drain metal layer arranged on a side of the first source-drain metal layer away from the substrate, the horizontal sub-line being arranged in the first source-drain metal layer, the vertical sub-line being arranged in the second source-drain metal layer. 7.The display substrate according to any one of claims 1 to 6, wherein The at least two horizontal sub-lines comprise at least a first horizontal sub-line and a second horizontal sub-line, the at least two vertical sub-lines comprising at least a first vertical sub-line and a second vertical sub-line; the data signal lines being connected to the data lead-out lines through the data connection lines, comprising: a first end of the first vertical sub-line being connected to the data lead-out line, a second end of the first vertical sub-line extending towards a direction away from the binding area and then being connected to a first end of the first horizontal sub-line, a second end of the first horizontal sub-line extending towards a direction close to the second vertical sub-line and then being connected to a first end of the second vertical sub-line, a second end of the second vertical sub-line extending towards a direction away from the binding area and then being connected to a first end of the second horizontal sub-line, a second end of the second horizontal sub-line extending towards a direction close to the data signal line and then being connected to the data signal line. 8.The display substrate of claim 7, wherein, The display region further comprises a plurality of first data connection blocks; in at least one circuit unit, the first data connection block is connected with the first end of the first horizontal sub-line, and the second end of the first vertical sub-line is connected with the first data connection block through a via hole; in at least another circuit unit, the first data connection block is connected with the first end of the second horizontal sub-line, and the second end of the second vertical sub-line is connected with the first data connection block through a via hole. 9.The display substrate of claim 8, wherein, The display region further comprises a plurality of data transfer strips; in at least one circuit unit, the first end of the first horizontal sub-line is connected with the first data connection block through the data transfer strip; in at least another circuit unit, the first end of the second horizontal sub-line is connected with the first data connection block through the data transfer strip. 10.The display substrate of claim 9, wherein, In at least one circuit unit, the first horizontal sub-line, the first data connection block and the data transfer strip are an integrated structure connected with each other; in at least another circuit unit, the second horizontal sub-line, the first data connection block and the data transfer strip are an integrated structure connected with each other. 11.The display substrate of claim 8, wherein, The display region further comprises a plurality of first dummy electrodes; the position and connection structure of at least one first dummy electrode in one circuit unit are the same as the position and connection structure of at least one first data connection block in another circuit unit. 12.The display substrate of claim 11, wherein, In at least one circuit unit, the first vertical sub-line is connected with at least one first dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected with at least one first dummy electrode through a via hole. 13.The display substrate of claim 7, wherein, The display region further comprises a plurality of second data connection blocks; in at least one circuit unit, the second data connection block is connected with the second end of the first horizontal sub-line, and the first end of the second vertical sub-line is connected with the second data connection block through a via hole. 14.The display substrate of claim 13, wherein, In at least one circuit unit, the first horizontal sub-line and the second data connection block are an integrated structure connected with each other. 15.The display substrate of claim 13, wherein, The display region further comprises a plurality of second dummy electrodes; the position and connection structure of at least one second dummy electrode in one circuit unit are the same as the position and connection structure of at least one second data connection block in another circuit unit. 16.The display substrate of claim 15, wherein, In at least one circuit unit, the first vertical sub-line is connected with at least one second dummy electrode through a via hole; in at least another circuit unit, the second vertical sub-line is connected with at least one second dummy electrode through a via hole.

17. A display device comprising the display substrate according to any one of claims 1 to 16.

18. A manufacturing method of a display substrate, the display substrate comprising a display region and a binding region arranged on one side of the display region, the display region comprising a plurality of circuit units forming a plurality of unit rows and a plurality of unit columns, at least one circuit unit comprising a pixel driving circuit; the manufacturing method comprising: A plurality of data signal lines and a plurality of data connection lines are formed in the display area, and a plurality of data lead-out lines are formed in the binding area, the data signal lines are configured to provide data signals to the pixel driving circuit, and the data signal lines are connected with the data lead-out lines through the data connection lines; at least one data connection line includes at least two horizontal sub-lines extending along a first direction and at least two vertical sub-lines extending along a second direction, the two horizontal sub-lines are arranged in different unit rows, the two vertical sub-lines are arranged in different unit columns, and the first direction and the second direction intersect.

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