Display panel and display device

Abstract

Provided are a display panel and a display device. The display panel comprises: a plurality of sub-pixels, wherein at least one of the plurality of sub-pixels comprises a pixel circuit and a light-emitting element, the pixel circuit comprises a first transistor, a second transistor, and a third transistor, a first electrode of the second transistor is connected to a gate of the first transistor, and a first electrode of the third transistor is connected to a first electrode of the first transistor; first gate lines connected to a gate of the second transistor; and second gate lines connected to a gate of the third transistor, wherein the first gate lines extend in a first direction, the second gate lines extend in the first direction, the first gate lines and the second gate lines are arranged at intervals in a second direction, and the first direction intersects the second direction, so as to facilitate structural arrangement of pixel circuits, layout design, increase of an aperture ratio, and improvement of a display effect.

Description

Display panel and display device Technical Field

[0001] At least one embodiment of this disclosure relates to a display panel and a display device. Background Technology

[0002] White organic light-emitting diode (WOLED) products use a white light source and adjust the color through a color filter layer, while organic light-emitting diode (RGB OLED) products emit color light directly from various color light sources.

[0003] Bottom-emitting WOLED products, compared to top-emitting WOLED products, have lower cathode sheet resistance, eliminating the need for complex auxiliary cathode processes and thus offering higher mass production feasibility. Furthermore, compared to directly emitting colored light (RGB OLED) products, they offer lower power consumption. However, for each pixel, the number of sub-pixels increases, resulting in tighter pixel layout space and greater complexity for WOLED products with the same resolution. The smaller aperture spacing between sub-pixels also increases the risk of light leakage.

[0004] Summary of the Invention

[0005] At least one embodiment of this disclosure relates to a display panel and display device that facilitates the structural arrangement of pixel circuits, improves layout design, increases aperture ratio, and enhances display effect.

[0006] At least one embodiment of this disclosure provides a display panel, comprising: a plurality of sub-pixels, at least one of the plurality of sub-pixels including a pixel circuit and a light-emitting element, the pixel circuit including a first transistor, a second transistor and a third transistor, a first terminal of the second transistor being connected to the gate of the first transistor, and a first terminal of the third transistor being connected to the first terminal of the first transistor; a first gate line connected to the gate of the second transistor; a second gate line connected to the gate of the third transistor; the first gate line extending along a first direction, the second gate line extending along the first direction, the first gate line and the second gate line being spaced apart from each other in a second direction, and the first direction and the second direction intersecting.

[0007] For example, the first gate line and the second gate line connected to the second transistor and the third transistor of the same sub-pixel are different gate lines.

[0008] For example, multiple first gate lines and multiple second gate lines are configured, with multiple first gate lines and multiple first gate lines alternately arranged in the second direction.

[0009] For example, within the same sub-pixel, the third transistor is closer to the first transistor than the second transistor.

[0010] For example, the plurality of sub-pixels includes a plurality of pixel groups, each of the plurality of pixel groups includes two rows and two columns of four sub-pixels, the same first gate line is connected to two second transistors in the two rows of sub-pixels respectively, and the four sub-pixels in the same pixel group are symmetrically arranged in layout.

[0011] For example, the pixel circuits at the locations of the four sub-pixels in the same pixel group are symmetrically arranged with respect to a first axis parallel to the first direction and with respect to a second axis parallel to the second direction.

[0012] For example, two second transistors in two rows of sub-pixels connected to the same first gate line are arranged in the first direction.

[0013] For example, in two sub-pixels of four sub-pixels in the same pixel group, the center line connecting the active layers of the first transistor, the second transistor, and the third transistor is an obtuse triangle.

[0014] For example, two second transistors in two rows of sub-pixels connected to the same first gate line are arranged in the second direction.

[0015] For example, in the four sub-pixels of the same pixel group, the center line connecting the active layers of the first transistor, the second transistor, and the third transistor is an obtuse triangle.

[0016] For example, the four sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel and the third sub-pixel are arranged along the first direction, the fourth sub-pixel and the second sub-pixel are arranged along the first direction, the first sub-pixel and the fourth sub-pixel are arranged along the second direction, and the third sub-pixel and the second sub-pixel are arranged along the second direction.

[0017] For example, the first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, and the fourth sub-pixel is a white sub-pixel.

[0018] For example, the display panel also includes a data line, a first power line, and a sensing line. The data line is connected to the second terminal of the second transistor, the first power line is connected to the second terminal of the first transistor, and the sensing line is connected to the second terminal of the third transistor. The data line, the first power line, and the sensing line all extend along the second direction.

[0019] For example, the data lines are configured as multiple lines, including a first data line, a second data line, a third data line, and a fourth data line. The first data line is connected to the second transistor of the first sub-pixel, the second data line is connected to the second transistor of the second sub-pixel, the third data line is connected to the second transistor of the third sub-pixel, and the fourth data line is connected to the second transistor of the fourth sub-pixel.

[0020] For example, the fourth data line, the first data line, the second data line, and the third data line are arranged along the first direction, the sensing line is provided between the first data line and the second data line, and the first data line, the sensing line, and the second data line are located between the pixel openings of two adjacent columns of sub-pixels.

[0021] For example, the fourth data line and the third data line are respectively adjacent to two first power lines. The fourth data line and the adjacent first power line are located between the pixel openings of two adjacent columns of sub-pixels. The third data line and the adjacent first power line are located between the pixel openings of two adjacent columns of sub-pixels, forming a structure in which a first power line, a fourth data line, a column of pixel openings, a first data line, a sensing line, a second data line, another column of pixel openings, a third data line, and another first power line are arranged sequentially in the first direction.

[0022] For example, the multiple data lines do not overlap with each other.

[0023] For example, the first power line and the sensing line are located between the pixel openings of two adjacent columns of sub-pixels, the first data line and the fourth data line are located between the pixel openings of two adjacent columns of sub-pixels, and the third data line and the second data line are located between the pixel openings of two adjacent columns of sub-pixels, forming a structure in which the first data line, the fourth data line, one column of pixel openings, the first power line, the sensing line, another column of pixel openings, the third data line, and the second data line are arranged sequentially in the first direction.

[0024] For example, two signal lines extending along the second direction are provided between the pixel openings of every two adjacent columns of sub-pixels.

[0025] For example, the first power line includes a power body line and a power connection line, the power body line extends along the second direction, the power connection line extends along the first direction, and the power connection line is located between the second gate line and the active layer of the first transistor.

[0026] For example, the power connection line, the first gate line, and the second gate line are located on the same layer.

[0027] For example, the light-emitting element is connected to the pixel circuit through a via, and in the same sub-pixel, the via is closer to the first gate line than the active layer of the first transistor.

[0028] For example, the second gate line includes a main gate line and a branch, the main gate line extends along the first direction, the branch extends along the second direction, the main gate line and the branch are an integral structure, and the branch serves as the gate of the third transistor.

[0029] For example, the display panel also includes a light-shielding layer that overlaps with the first transistor.

[0030] For example, the pixel circuit further includes a storage capacitor, which includes a first electrode and a second electrode. The first electrode is connected to the gate of the first transistor, and the second electrode is connected to the first electrode of the first transistor, the first electrode of the third transistor, and the first electrode of the light-emitting element. The second electrode is also connected to the light-shielding layer.

[0031] For example, the display panel further includes a color filter layer located between the light-emitting element and the pixel circuit, the color filter layer including an opening through which the light-emitting element is connected to the pixel circuit.

[0032] At least one embodiment of this disclosure provides a display device including any of the above-described display panels. Attached Figure Description

[0033] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure and are not intended to limit this disclosure.

[0034] Figure 1 is a schematic diagram of a strip-shaped pixel arrangement.

[0035] Figure 2 is a schematic diagram of a square-shaped pixel arrangement.

[0036] Figure 3A is a schematic diagram of a 3T1C pixel circuit in a display panel provided by an embodiment of the present disclosure.

[0037] Figure 3B shows the signal timing diagram of the pixel circuit during the display process.

[0038] Figures 3C and 3D show the signal timing diagrams of the pixel circuit during the detection process.

[0039] Figure 4 is a layout diagram of a display panel provided in an embodiment of this disclosure.

[0040] Figure 5 is a layout diagram of a display panel provided in an embodiment of this disclosure.

[0041] Figures 6 to 14 are plan views of a single layer in a display panel provided by an embodiment of the present disclosure.

[0042] Figure 15 is a cross-sectional view of a display panel provided in an embodiment of the present disclosure.

[0043] Figure 16 is a layout diagram of a display panel provided in another embodiment of this disclosure.

[0044] Figure 17 is a layout diagram of a display panel provided in another embodiment of this disclosure.

[0045] Figure 18 is a layout diagram of a display panel provided in another embodiment of this disclosure. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0048] Figure 1 is a schematic diagram of a strip-shaped pixel arrangement. Figure 2 is a schematic diagram of a square-shaped pixel arrangement.

[0049] As shown in Figures 1 and 2, the display panel includes multiple pixels PX, and each pixel PX includes multiple sub-pixels SP.

[0050] As shown in Figure 1, pixel PX includes four sub-pixels SP, namely, sub-pixels SP1, SP2, SP3, and SP4. As shown in Figure 1, sub-pixels SP4, SP1, SP2, and SP3 are arranged along the X direction.

[0051] As shown in Figure 2, pixel PX includes four sub-pixels SP, namely, pixel PX includes sub-pixels SP1, SP2, SP3, and SP4.

[0052] As shown in Figure 2, sub-pixels SP1 and SP4 are arranged along the Y direction, sub-pixels SP3 and SP2 are arranged along the Y direction, sub-pixels SP1 and SP3 are arranged along the X direction, and sub-pixels SP4 and SP2 are arranged along the X direction. That is, the four sub-pixels SP are arranged in two rows and two columns. For example, in the display panel shown in Figure 2, in two adjacent columns of sub-pixels, in one column, multiple sub-pixels SP1 and SP4 are arranged alternately along the Y direction, and in the other column, multiple sub-pixels SP3 and SP2 are arranged alternately along the Y direction. For example, in the display panel shown in Figure 2, in two adjacent rows of sub-pixels, in one row, multiple sub-pixels SP1 and SP3 are arranged alternately along the X direction, and in the other row, multiple sub-pixels SP4 and SP2 are arranged alternately along the X direction.

[0053] Figures 1 and 2 illustrate examples with subpixel SP1 as a red subpixel, subpixel SP2 as a green subpixel, subpixel SP3 as a blue subpixel, and subpixel SP4 as a white subpixel. However, the emission color of subpixel SP is not limited to the above description and can emit other colors of light. The embodiments of this disclosure do not specifically limit the emission colors of subpixels SP1, SP2, SP3, and SP4, and can be determined as needed.

[0054] Figures 1 and 2 show the substrate BS. Multiple pixels PX are located on the substrate BS.

[0055] For bottom-emitting WOLED products, the pixel arrangement can be either strip or square. In a bottom-emitting strip pixel arrangement, there are more non-light-emitting areas between sub-pixels, so the aperture of the sub-pixels is generally lower, or the spacing between the pixel apertures is smaller while maintaining the same aperture ratio, resulting in a greater risk of light leakage. Square pixel arrangements have the advantages of a larger aperture ratio and a lower risk of light leakage.

[0056] The display panel provided in the embodiments of this disclosure can adopt the square pixel arrangement shown in FIG2.

[0057] Figure 3A is a schematic diagram of a 3T1C pixel circuit in a display panel provided in an embodiment of this disclosure. The pixel circuit of the display panel provided in this embodiment is not limited to a 3T1C pixel circuit; this embodiment uses a 3T1C pixel circuit as an example to illustrate the structure of the display panel. Depending on the needs, the pixel circuit can also have other structures. For example, the pixel circuit can further include a compensation circuit, a reset circuit, etc., and this embodiment of the disclosure does not limit this.

[0058] Referring to Figure 3A, the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor Cst. The first transistor T1 is a driving transistor, and the second transistor T2 is a data writing transistor. The first terminal of the second transistor T2 is electrically connected to the first plate Ca of the storage capacitor Cst and the gate of the first transistor T1. The second terminal of the second transistor T2 is connected to the data line DT and configured to receive the data signal Vdt. The gate of the second transistor T2 is connected to the gate line G1, which is configured to provide a first control signal Vg1. The second transistor T2 is configured to write the data signal Vdt to the gate of the first transistor T1 and the storage capacitor Cst in response to the first control signal Vg1. The first terminal of the first transistor T1 is electrically connected to the second plate Cb of the storage capacitor Cst and configured to be electrically connected to the first electrode E1 of the light-emitting element EM. The second terminal of the first transistor T1 is connected to the first power supply line PL1 and configured to receive a first power supply voltage (e.g., a high power supply voltage VDD). The first power supply line PL1 is configured to provide the first power supply voltage. The first transistor T1 is configured to control the current used to drive the light-emitting element EM under the control of the voltage of the gate of the first transistor T1. The first terminal of the third transistor T3 is electrically connected to the first terminal of the first transistor T1 and the second plate Cb of the storage capacitor Cst. The second terminal of the third transistor T3 is configured to be connected to the sensing line SS to connect to an external detection circuit. The gate of the third transistor T3 is connected to the gate line G2, which is configured to provide a second control signal Vg2. The third transistor T3 is configured to detect the electrical characteristics of the sub-pixel in response to the second control signal Vg2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and / or carrier mobility of the first transistor T1, or the threshold voltage and driving current of the light-emitting element EM. For example, the external detection circuit is a conventional circuit including a digital-to-analog converter (DAC) and an analog-to-digital converter (ADC), etc., which will not be described in detail in the embodiments of this disclosure. Figure 3A shows the gate g, the first terminal a, and the second terminal b of the transistor.

[0059] As shown in Figure 3A, the first electrode of the second transistor T2, the first plate Ca of the storage capacitor Cst, and the gate of the first transistor T1 are all connected to node G.

[0060] As shown in Figure 3A, the second electrode plate Cb, the first electrode of the first transistor T1, the first electrode of the third transistor T3, and the first electrode E1 of the light-emitting element are all connected to node S.

[0061] As shown in Figure 3A, the second electrode E2 of the light-emitting element EM is connected to the second power supply line PL2 to receive a second power supply voltage (e.g., a low power supply voltage VSS). The second power supply line PL2 is configured to provide the second power supply voltage.

[0062] For example, in a direction perpendicular to the substrate BS, the second electrode Cb and the first electrode Ca overlap each other and an interlayer dielectric layer is provided therebetween to form a storage capacitor Cst.

[0063] The transistors used in the embodiments of this disclosure can all be thin-film transistors, field-effect transistors, or other switching devices with the same characteristics. The embodiments of this disclosure use thin-film transistors as an example for illustration. The source and drain of the transistors used here can be structurally symmetrical, so their source and drain can be structurally indistinguishable. In the embodiments of this disclosure, to distinguish the two terminals of the transistor other than the gate, one terminal is directly described as the first terminal, and the other as the second terminal. Furthermore, transistors can be classified into N-type and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage); when the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltage), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltage). It should be noted that the following description uses the transistor in Figure 3A as an example of an N-type transistor, but this is not intended to limit the scope of this disclosure.

[0064] The working principle of the pixel circuit shown in Figure 3A will be explained below with reference to the signal timing diagrams shown in Figures 3B to 3D. Figure 3B shows the signal timing diagram of the pixel circuit during the display process, while Figures 3C and 3D show the signal timing diagram of the pixel circuit during the detection process. It should be noted that the signal timing diagram of the pixel circuit shown in Figure 3A is not limited to the cases shown in Figures 3B to 3D.

[0065] For example, as shown in Figure 3B, the display process of each frame of the image includes a data writing and reset phase 1 and a light emission phase 2. Figure 3B shows the timing waveforms of each signal in each phase. One working process of the 3T1C pixel circuit includes: in the data writing and reset phase 1, the first control signal Vg1 and the second control signal Vg2 are both on signals, the second transistor T2 and the third transistor T3 are turned on, the data signal Vdt is transmitted to the gate of the first transistor T1 through the second transistor T2, the analog-to-digital converter writes a reset signal to the first electrode E1 (e.g., the anode of the OLED) of the light-emitting element EM through the sensing line SS and the third transistor T3, the first transistor T1 is turned on and generates a driving current to charge the first electrode E1 of the light-emitting element EM to the working voltage; in the light emission phase 2, the first control signal Vg1 and the second control signal Vg2 are both off signals, due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains unchanged, the first transistor T1 operates in saturation and the current remains unchanged, and drives the light-emitting element EM to emit light.

[0066] For example, Figure 3C shows the signal timing diagram of the pixel circuit when detecting the threshold voltage. One operating process of the 3T1C pixel circuit includes: both the first control signal Vg1 and the second control signal Vg2 are on signals, the second transistor T2 and the third transistor T3 are turned on, and the data signal Vdt is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3; the first transistor T1 turns on and charges node S until it turns off; the digital-to-analog converter samples the voltage on the sensing line SS to obtain the threshold voltage of the first transistor T1. This process can, for example, be performed when the display device is powered off. Vs in Figure 3C represents the voltage at node S.

[0067] For example, Figure 3D shows the signal timing diagram of the pixel circuit when detecting carrier mobility. One operation of the 3T1C pixel circuit includes: In the first stage, both the first control signal Vg1 and the second control signal Vg2 are on signals, the second transistor T2 and the third transistor T3 are on, and the data signal Vdt is transmitted to the gate of the first transistor T1 via the second transistor T2; the analog-to-digital converter writes a reset signal to the first electrode E1 (node ​​S) of the light-emitting element EM through the sensing line SS and the third transistor T3; In the second stage, the first control signal Vg1 is off, the second control signal Vg2 is on, the second transistor T2 is off, the third transistor T3 is on, and the sensing line SS is floated; due to the bootstrap effect of the storage capacitor Cst, the voltage across the storage capacitor Cst remains constant, the first transistor T1 operates in saturation with a constant current, and drives the light-emitting element to emit light. Then, the digital-to-analog converter samples the voltage on the sensing line SS, and by combining the magnitude and duration of the emitted current, it can calculate the carrier mobility in the first transistor T1. For example, this process can be performed during the blanking phase between display phases.

[0068] The electrical characteristics of the first transistor T1 can be obtained through the above detection, and the corresponding compensation algorithm can be implemented.

[0069] For example, the display panel may also include a data driving circuit and a scan driving circuit (not shown). The data driving circuit is configured to emit a data signal, such as the aforementioned data signal Vdt, as needed (e.g., an image signal input to the display device); the pixel circuit of each sub-pixel is also configured to receive the data signal and apply it to the gate of the first transistor. The scan driving circuit is configured to output various scan signals, such as the aforementioned first control signal Vg1 and second control signal Vg2, which may be, for example, an integrated circuit chip (IC) or a gate-on-array (GOA) circuit directly fabricated on the display panel.

[0070] For example, the display panel also includes control circuitry. This control circuitry is configured to control the data driving circuitry to apply data signals and to control the gate driving circuitry to apply scan signals. An example of this control circuitry is a timing control circuit (T-con). The control circuitry can take various forms, including, for example, a processor and memory, where the memory includes executable code that the processor runs to perform the aforementioned detection method.

[0071] For example, the processor can be a central processing unit (CPU) or other forms of processing device with data processing and / or instruction execution capabilities, such as a microprocessor, a programmable logic controller (PLC), etc.

[0072] For example, the memory may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and a processor may execute the functions expected by the program instructions. Various application programs and various data, such as electrical characteristic parameters obtained in the above-described detection method, may also be stored in the computer-readable storage medium.

[0073] Figure 4 is a layout diagram of a display panel provided in an embodiment of the present disclosure. Figure 4 shows two rows and two columns of sub-pixels. Figure 5 is a layout diagram of a display panel provided in an embodiment of the present disclosure. Figure 5 shows four rows and four columns of sub-pixels. Figures 6 to 14 are plan views of a single layer in a display panel provided in an embodiment of the present disclosure. Figure 15 is a cross-sectional view of a display panel provided in an embodiment of the present disclosure.

[0074] Figure 6 is a plan view of a conductive layer LY0 in a display panel according to an embodiment of the present disclosure. Figure 7 is a plan view of a conductive layer LY1 in a display panel according to an embodiment of the present disclosure. Figure 8 is a plan view of a semiconductor-conductor layer LYS in a display panel according to an embodiment of the present disclosure. Figure 9 is a plan view of a first insulating layer (via VH1) in a display panel according to an embodiment of the present disclosure. Figure 10 is a plan view of a conductive layer LY2 in a display panel according to an embodiment of the present disclosure. Figure 11 is a plan view of a second insulating layer (via VH2) in a display panel according to an embodiment of the present disclosure. Figure 12 is a plan view of a conductive layer LY3 in a display panel according to an embodiment of the present disclosure. Figure 13 is a plan view of a pixel defining layer (pixel aperture OPN1) in a display panel according to an embodiment of the present disclosure. Figure 14 is a plan view of a color filter layer CF in a display panel according to an embodiment of the present disclosure.

[0075] As shown in Figures 2, 3A, and 4 to 14, an embodiment of the present disclosure provides a display panel including: a plurality of sub-pixels SP, a gate line G1, and a gate line G2. At least one of the plurality of sub-pixels SP includes a pixel circuit PXC and a light-emitting element EM. The pixel circuit PXC includes a first transistor T1, a second transistor T2, and a third transistor T3. The first terminal of the second transistor T2 is connected to the gate of the first transistor T1, and the first terminal of the third transistor T3 is connected to the first terminal of the first transistor T1. The gate line G1 is connected to the gate of the second transistor T2, and the gate line G2 is connected to the gate of the third transistor T3. The gate line G1 extends along the X direction, the gate line G2 extends along the X direction, the gate lines G1 and G2 are spaced apart from each other in the Y direction, and the X and Y directions intersect.

[0076] Embodiments of this disclosure provide a display panel in which gate line G1 extends along direction X, gate line G2 extends along direction X, and gate lines G1 and G2 are spaced apart from each other in direction Y. Second transistor T2 and third transistor T3 are respectively connected to different gate lines so that signals can be input separately, which is beneficial for the separate control of second transistor T2 and third transistor T3. By adjusting the position of the transistors, the structure and arrangement of the pixel circuit are facilitated, which is beneficial for layout design, thereby improving the aperture ratio and display effect.

[0077] For example, as shown in Figures 4, 5, and 10, the gate lines G1 and G2 connected to the second transistor T2 and the third transistor T3 of the same sub-pixel SP are different gate lines to facilitate layout design and separate control of the second transistor T2 and the third transistor T3. Taking the upper left sub-pixel shown in Figures 4 and 5 as an example, the second transistor T2 and the third transistor T3 are spaced apart in the Y direction, and the gate lines G1 and G2 are spaced apart in the Y direction, making G1 and G2 two different gate lines.

[0078] For example, as shown in Figures 4, 5 and 10, multiple gate lines G1 and multiple gate lines G2 are set, and multiple gate lines G1 are alternately set in the Y direction to facilitate the formation of a periodic sub-pixel arrangement.

[0079] Figure 4 shows three transistors in the same sub-pixel SP. The three transistors in the same sub-pixel SP are connected by dashed lines to form a triangle.

[0080] Figures 4 and 8 show the active layers of the transistors. Figures 4 and 8 show the active layer T1s of the first transistor T1, the active layer T2s of the second transistor T2, and the active layer T3s of the third transistor T3.

[0081] For example, as shown in Figures 4 and 5, within the same sub-pixel SP, the third transistor T3 is closer to the first transistor T1 than the second transistor T2, to facilitate layout design. As shown in Figures 4 and 5, the distance between the third transistor T3 and the first transistor T1 is less than the distance between the second transistor T2 and the first transistor T1. A comparison of the distances between transistors can be referenced to a comparison of the distances between the active layers of transistors.

[0082] For example, as shown in Figures 4 and 5, multiple sub-pixels SP include multiple pixel groups 66. Each pixel group 66 includes four sub-pixels SP in two rows and two columns. The same gate line G1 is connected to two second transistors T2 in the two rows of sub-pixels SP respectively. The pixel circuits at the locations of the four sub-pixels SP in the same pixel group 66 are symmetrically arranged in the layout to facilitate layout design. Figure 4 shows one pixel group 66. Figure 5 shows four pixel groups 66. As shown in Figures 4 and 5, the same gate line G1 is connected to two second transistors T2 in the two rows of sub-pixels SP respectively. One second transistor T2 (the second transistor T2 on the left) is used to transmit data signals to the sub-pixels located above the gate line G1, and the other second transistor T2 (the second transistor T2 on the right) is used to transmit data signals to the sub-pixels located below the gate line G1. Thus, in the layout design, the pixel circuits at the locations of the four sub-pixels SP in the same pixel group 66 are symmetrically arranged in the layout. For example, the symmetrical arrangement of pixel circuits at the locations of the four sub-pixels SP in the same pixel group 66 can refer to the symmetrical arrangement of transistor positions in the layout. When examining the layout design at the location of the same pixel group 66, it is not only the transistors belonging to the four sub-pixels SP in this pixel group 66 that are considered, but also the second transistors T2 located in the region of this pixel group that are connected to the gate line G1, such as the four second transistors T2 not connected by the dashed lines in Figure 4. That is, taking Figure 4 as an example, the transistors shown in Figure 4 are all included in the layout of the pixel circuits at the locations of the four sub-pixels SP in the same pixel group 66.

[0083] For example, as shown in Figures 4 and 5, the two second transistors T2 in two rows of sub-pixels SP connected to the same gate line G1 are arranged in the X direction. For example, the two second transistors T2 in two rows of sub-pixels SP connected to the same gate line G1 are arranged sequentially in the X direction. That is, the two second transistors T2 in the upper and lower rows of sub-pixels share the same gate line G1 to save space and facilitate layout.

[0084] For example, as shown in Figures 4 and 5, the four sub-pixels SP in the same pixel group 66 include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4. The first sub-pixel SP1 and the third sub-pixel SP3 are arranged along the X direction, the fourth sub-pixel SP4 and the second sub-pixel SP2 are arranged along the X direction, the first sub-pixel SP1 and the fourth sub-pixel SP4 are arranged along the Y direction, and the third sub-pixel SP3 and the second sub-pixel SP2 are arranged along the Y direction.

[0085] For example, as shown in Figures 4 and 5, in the same sub-pixel SP, among the four sub-pixels SP in the same pixel group 66, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of two sub-pixels forms an obtuse triangle. Figure 5 does not show the triangle formed by the center lines connecting the active layers of the transistors; refer to Figure 4. As shown in Figure 4, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of the fourth sub-pixel SP4 forms an obtuse triangle. As shown in Figure 4, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of the third sub-pixel SP3 also forms an obtuse triangle. The fourth sub-pixel SP4 and the third sub-pixel SP3, whose center lines connecting their active layers form an obtuse triangle, are located in different rows and columns.

[0086] For example, as shown in Figures 4 and 5, in the same sub-pixel SP, among the four sub-pixels SP in the same pixel group 66, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of the other two sub-pixels forms an acute-angled triangle. Figure 5 does not show the triangle formed by the center lines connecting the active layers of the transistors; refer to Figure 4. As shown in Figure 4, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of the first sub-pixel SP1 forms an acute-angled triangle. As shown in Figure 4, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of the second sub-pixel SP2 also forms an acute-angled triangle. The first sub-pixel SP1 and the second sub-pixel SP2, whose center lines connecting their active layers form an acute-angled triangle, are located in different rows and different columns.

[0087] Figure 5 shows the pixel circuit PXC1 for the first sub-pixel SP1, the pixel circuit PXC2 for the second sub-pixel SP2, the pixel circuit PXC3 for the third sub-pixel SP3, and the pixel circuit PXC4 for the fourth sub-pixel SP4.

[0088] For example, as shown in Figures 4 and 5, the pixel circuits PXC at the locations of the four sub-pixels SP in the same pixel group 66 are symmetrically arranged with respect to a first axis A1 parallel to the X direction and with respect to a second axis A2 parallel to the Y direction. Figure 4 shows the first axis A1 and the second axis A2. For example, the first axis A1 is perpendicular to the second axis A2. Similarly, when viewing the symmetrical arrangement of the pixel circuits PXC at the locations of the four sub-pixels SP in the same pixel group 66, we are not only looking at the transistors belonging to the four sub-pixels SP in this pixel group 66, but also including the second transistors T2 located in the region of this pixel group that are connected to the gate line G1, such as the four second transistors T2 not connected by the dashed lines in Figure 4. That is, taking Figure 4 as an example, all the transistors shown in Figure 4 are included in the layout of the pixel circuits at the locations of the four sub-pixels SP in the same pixel group 66.

[0089] For example, as shown in Figures 4 and 5, the first sub-pixel SP1 is a red sub-pixel, the second sub-pixel SP2 is a green sub-pixel, the third sub-pixel SP3 is a blue sub-pixel, and the fourth sub-pixel SP4 is a white sub-pixel. Of course, the emission of each sub-pixel is not limited to this and can be adjusted to emit other colors of light as needed.

[0090] Figure 6 shows the conductive layer LY0. The conductive layer LY0 can be made of a transparent conductive material. For example, the conductive layer LY0 can be made of indium tin oxide. Figure 6 shows four second electrodes Cb. The four second electrodes Cb are spaced apart from each other.

[0091] Figure 7 shows the conductive layer LY1. As shown in Figure 7, the conductive layer LY1 includes a first power line PL1, a data line DT, a connection portion CEm, a connection portion CEn, and a sensing line SS. Figure 7 shows two first power lines PL1. Figure 7 shows four data lines DT. The four data lines DT include a first data line DTR, a second data line DTG, a third data line DTB, and a fourth data line DTW. As shown in Figure 15, no insulating layer is provided between the conductive layer LY0 and the conductive layer LY1. As shown in Figures 7 and 15, the connection portion CEn is in direct contact with the second electrode Cb to be connected to each other. The connection portion CEm is in direct contact with the second electrode Cb to be connected to each other. The connection portion CEm serves as a shielding layer LS for the active layer (channel) T1s of the first transistor T1.

[0092] Figure 8 illustrates the semiconductor-conductor layer LYS. As shown in Figure 8, the semiconductor-conductor layer LYS includes the active layer (channel) of the transistor made of semiconductor material and conductive elements (first electrode Ca, power connection line PL12, and the source and drain of each transistor). Figure 8 shows the active layer T1s of the first transistor T1, the active layer T2s of the second transistor T2, and the active layer T3s of the third transistor T3. The source and drain of the transistor are located on both sides of the active layer of each transistor. The power connection line PL12 is connected to the active layer T1s and is an integral structure. The conductive elements are conductors obtained by doping semiconductors. The power connection line PL12 is an integral structure with the second electrode of the first transistor T1. Figure 8 is a part of the display panel. In the entire display panel, the active layer T2s, the first electrode T2a of the second transistor T2, and the second electrode T2b of the second transistor T2 are an integral structure. For example, by copying the structure shown in Figure 8 and translating it downwards and connecting it with the structure shown in Figure 8, it can be seen that the active layer T2s, the first electrode T2a of the second transistor T2, and the second electrode T2b of the second transistor T2 are integrated into one structure, as shown in Figure 5.

[0093] Figure 9 shows a plan view of the first insulating layer (via VH1) in the display panel. Figure 9 illustrates the first insulating layer with the vias therein. As shown in Figure 9, the via VH1 in the first insulating layer includes via V1, via V2, via V3, via V4, via V5, and via V6.

[0094] For example, the first insulating layer may be the first insulating layer ISL1 in the display panel shown in FIG15. For example, the first insulating layer ISL1 may be a gate insulating layer, but is not limited thereto.

[0095] Figure 10 shows the conductive layer LY2. As shown in Figure 10, the conductive layer LY2 includes connection portions CEa, CEb, CEc, CEd, CEe, and CEf, gate line G1, and gate line G2. Figure 10 shows two gate lines G1 and the gate line G2 located between the two gate lines G1. Figure 10 shows the gate T3g of the third transistor T3. The gate T3g protrudes from the gate line G2. The gate T3g of the third transistor T3 and the gate line G2 are integrally structured.

[0096] Figure 11 shows a plan view of the second insulating layer (via VH2) in the display panel. Figure 11 illustrates the second insulating layer with its vias. As shown in Figure 11, the via VH2 in the second insulating layer includes via H0. Figure 11 shows four vias H0.

[0097] For example, the second insulating layer may be the second insulating layer ISL2 in the display panel shown in FIG15. For example, the second insulating layer ISL2 may include a passivation layer PVX and a planarization layer PLN.

[0098] Figure 12 shows the conductive layer LY3. As shown in Figure 12, the conductive layer LY3 includes the first electrode E1 of the light-emitting element. Figure 12 shows four first electrodes E1.

[0099] Figure 13 shows a plan view of the pixel defining layer (pixel aperture OPN1) in the display panel. Figure 13 illustrates the pixel defining layer PDL with respect to the pixel apertures OPN1. The pixel apertures OPN1 are configured to expose at least a portion of the first electrode E1. The pixel apertures OPN1 of the pixel defining layer PDL are configured to define the light-emitting area of ​​the sub-pixel, i.e., the actual light-emitting area of ​​the sub-pixel. Figure 13 shows four pixel apertures OPN1. The area in Figure 13 other than the four pixel apertures OPN1 is the body of the pixel defining layer PDL.

[0100] Figure 14 shows a plan view of the color filter layer CF in the display panel. As shown in Figure 14, the color filter layer CF includes a first filter CF1, a second filter CF2, and a third filter CF3. The first filter CF1 is configured to transmit a first color light, the second filter CF2 is configured to transmit a second color light, and the third filter CF3 is configured to transmit a third color light. Figure 14 uses red light as the first color light, green light as the second color light, and blue light as the third color light as an example. A light-transmitting part P0 can be provided at the white sub-pixel. For example, the light-transmitting part P0 can be a transparent resin layer, but it is not limited to this.

[0101] As shown in Figures 6 to 10, the connection portion CEe is connected to the second electrode T3b of the third transistor T3 located on one side of the active layer T3s and the sensing line SS through the via V6. The conductor portion located on one side of the active layer T3s and connected to the connection portion CEe can serve as the second electrode T3b of the third transistor T3.

[0102] As shown in Figures 6 to 10, the connecting portion CEd is connected to the first electrode T3a of the third transistor T3 located on one side of the active layer T3s and the connecting portion CEn through the via V5. Thus, the first electrode T3a of the third transistor T3 is connected to the second electrode plate Cb through the connecting portions CEn and CEd. The conductor portion located on one side of the active layer T3s and connected to the connecting portion CEd can serve as the first electrode T3a of the third transistor T3.

[0103] As shown in Figures 6 to 10, the connection portion CEc (the gate of the first transistor T1) is connected to the first electrode plate Ca through the via V3. The conductor portion located on one side of the active layer T2s and connected to the connection portion CEc can serve as the first electrode T2a of the second transistor T2.

[0104] As shown in Figures 9 to 12, the first electrode E1 is connected to the connecting part CEd through the through hole H0, and then connected to the connecting part CEn, and then connected to the second electrode plate Cb.

[0105] As shown in Figures 6 to 10, the connecting portion CEb is connected to the connecting portion CEm and the first electrode T1a of the first transistor T1 located on the active layer T1s side via the via V2. Since the connecting portion CEm is connected to the second electrode Cb, the first electrode T1a of the first transistor T1 is connected to the second electrode Cb. The conductor portion located on the active layer T1s side and connected to the connecting portion CEb can serve as the first electrode T1a of the first transistor T1.

[0106] As shown in Figures 6 to 10, the connection portion CEa is connected to the data line DT and the second electrode T2b of the second transistor T2 located on one side of the active layer T2s through the via V1, so that the data line DT is connected to the second electrode T2b of the second transistor T2. The conductor portion located on one side of the active layer T2s and connected to the data line DT can serve as the second electrode T2b of the second transistor T2.

[0107] As shown in Figures 6 to 10, the connection part CEf is connected to the first power line PL1 (power connection line PL12) and the second terminal T1b of the first transistor T1 located on one side of the active layer T1s through the via V4, thereby connecting the first power line PL1 to the second terminal T1b of the first transistor T1.

[0108] The crosshairs shown in Figures 6 to 14 indicate the center position of the diagram. Figures 6 to 14 can be plan views of a single layer in the display panel shown in Figure 4. Figure 4 can be a group of pixels in the display panel shown in Figure 5.

[0109] As shown in Figures 3A and 6 to 15, a barrier layer BR is provided on the substrate BS. Conductive layers LY0 and LY1 are located on the barrier layer BR, with LY0 formed before LY1. A buffer layer BF is provided on the conductive layers LY0 and LY1. A semiconductor-conductor layer LYS is provided on the buffer layer BF. A first insulating layer ISL1 is provided on the semiconductor-conductor layer LYS. A conductive layer LY2 is provided on the first insulating layer ISL1. A passivation layer PVX is provided on the conductive layer LY2. A color filter layer CF is provided on the passivation layer PVX. A planarization layer PLN is provided on the color filter layer CF. The passivation layer PVX and the planarization layer PLN constitute a second insulating layer ISL2. The first electrode E1 of the light-emitting element (located on the conductive layer LY3) is connected to the pixel circuit PXC through a via H0 penetrating the second insulating layer ISL2. As shown in Figure 15, a pixel delimiting layer PDL is provided on the first electrode E1. A light-emitting functional layer EML is provided on the pixel delimiting layer PDL, and a second electrode E2 is provided on the light-emitting functional layer EML. Figure 15 shows the pixel opening OPN1 of the pixel defining layer PDL. Figure 15 also shows the opening OPN2 of the color filter layer CF. The color filter layer in the display panel shown in Figure 15 can be a filter (e.g., a first filter CF1, a second filter CF2, or a third filter CF3) or a light-transmitting layer P0. Of course, at the white sub-pixel, the color filter layer CF shown in Figure 15 may not have any filter or light-transmitting layer P0.

[0110] In embodiments of this disclosure, the first electrode E1, the light-emitting functional layer EML, and the second electrode E2 constitute a light-emitting element EM. For example, the light-emitting element EM includes, but is not limited to, an organic light-emitting diode (OLED).

[0111] In the embodiments of this disclosure, the substrate BS can be a rigid substrate or a flexible substrate. For example, rigid substrates include, but are not limited to, glass substrates, and flexible substrates include, but are not limited to, polyimide substrates.

[0112] In embodiments of this disclosure, any one of the barrier layer BR, buffer layer BF, first insulating layer ISL1, and passivation layer PVX may be an inorganic insulating material layer. For example, the inorganic insulating material layer includes at least one of silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0113] For example, in embodiments of this disclosure, either the planarization layer PLN or the pixel defining layer PDL may be an organic insulating material layer. For example, the organic insulating material layer includes, but is not limited to, a resin.

[0114] For example, in the embodiments of this disclosure, conductive layers LY0, LY1, LY2, and LY3 are all made of conductive materials.

[0115] For example, both conductive layer LY0 and conductive layer LY3 can be made using transparent conductive oxides such as indium tin oxide.

[0116] For example, both conductive layer LY1 and conductive layer LY2 can be made of metal.

[0117] For example, in an embodiment of this disclosure, the second electrode E2 may be a reflective electrode to improve the display effect.

[0118] For example, in an embodiment of this disclosure, the first electrode E1 may be the anode and the second electrode E2 may be the cathode.

[0119] For example, the first electrode E1 is made of a conductive material. For example, the material of the first electrode E1 includes metals and conductive metal oxides. For example, the first electrode E1 has a structure in which indium tin oxide (ITO), silver (Ag), and indium tin oxide (ITO) are stacked. The material and structure of the first electrode E1 can be set as needed.

[0120] For example, the second electrode E2 is made of a conductive material. For example, the material of the second electrode E2 includes metals or alloys. For example, the material of the second electrode E2 includes a Mg / Ag alloy. The material and structure of the second electrode E2 can be configured as needed.

[0121] It should be noted that the layer structure of the cross-sectional view of the display panel provided in the embodiments of this disclosure is not limited to that shown in FIG15. Those skilled in the art can make adjustments based on this to obtain other layer structures.

[0122] For example, as shown in Figures 3A, 4 to 15, the display panel also includes a data line DT, a first power line PL1, and a sensing line SS. The data line DT is connected to the second terminal of the second transistor T2, the first power line PL1 is connected to the second terminal of the first transistor T1, and the sensing line SS is connected to the second terminal of the third transistor T3. The data line DT, the first power line PL1, and the sensing line SS all extend in the direction Y.

[0123] For example, as shown in Figures 4, 5, and 7, multiple data lines DT are configured. These multiple data lines DT include a first data line DTR, a second data line DTG, a third data line DTB, and a fourth data line DTW. The first data line DTR is connected to the second transistor T2 of the first sub-pixel SP1, the second data line DTG is connected to the second transistor T2 of the second sub-pixel SP2, the third data line DTB is connected to the second transistor T2 of the third sub-pixel SP3, and the fourth data line DTW is connected to the second transistor T2 of the fourth sub-pixel SP4.

[0124] For example, as shown in Figures 4, 5, 7 and 13, the fourth data line DTW, the first data line DTR, the second data line DTG and the third data line DTB are arranged along the direction X. A sensing line SS is provided between the first data line DTR and the second data line DTG, and the first data line DTR, the sensing line SS and the second data line DTG are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP.

[0125] The display panel provided in the embodiments of this disclosure, by adjusting the position of the data lines, places two data lines on both sides of the sensing line SS, which facilitates wiring and improves the aperture ratio of sub-pixels.

[0126] In the display panel shown in Figures 4 and 5, two or three signal lines are provided between the pixel apertures OPN1 of two adjacent columns of sub-pixels SP, which facilitates wiring and improves the aperture ratio of the sub-pixels.

[0127] For example, as shown in Figures 4, 5, 7, and 13, the fourth data line DTW and the third data line DTB are adjacent to the two first power lines PL1 respectively. The fourth data line DTW and its adjacent first power line PL1 are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP, and the third data line DTB and its adjacent first power line PL1 are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP. This forms a structure in which one first power line PL1, one fourth data line DT, one column of pixel openings OPN1, one first data line DT, one sensing line SS, one second data line DT, one column of pixel openings OPN1, one third data line DTB, and another first power line PL1 are arranged sequentially in the X direction. This display panel improves the aperture ratio and reduces the risk of light leakage between sub-pixels by balancing the distance distribution of the opaque signal lines between sub-pixels.

[0128] For example, as shown in Figures 4, 5, 7, and 13, the multiple data lines DT do not overlap with each other.

[0129] The display panel provided in the embodiments of this disclosure has no overlapping of the data lines DT, which reduces coupling, avoids mutual interference of signals, avoids affecting the display, and improves the display effect.

[0130] For example, as shown in Figure 17, the first power line PL1 and the sensing line SS are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP; the first data line DTR and the fourth data line DTW are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP; and the third data line DTB and the second data line DTG are located between the pixel openings OPN1 of two adjacent columns of sub-pixels SP. This forms a structure in which the first data line DTR, the fourth data line DTW, one column of pixel openings OPN1, the first power line PL1, the sensing line SS, another column of pixel openings OPN1, the third data line DTB, and the second data line DTG are arranged sequentially in the X direction. This display panel improves the aperture ratio and reduces the risk of light leakage between sub-pixels by balancing the distance distribution of the opaque signal lines between sub-pixels.

[0131] The display panel provided in the embodiments of this disclosure has signal lines evenly distributed, which is beneficial for wiring and layout.

[0132] For example, as shown in Figure 17, two signal lines extending in the Y direction are set between the pixel openings OPN1 of each two adjacent columns of sub-pixels SP, which facilitates the wiring of vertical signal lines, improves the aperture ratio, and enhances the display effect.

[0133] The display panel provided in the embodiments of this disclosure has signal lines evenly distributed between different sub-pixels, which can increase pixel openings, reduce light leakage, and prevent data lines DT and sensing lines SS from overlapping, thus avoiding interference with data signals and improving display performance.

[0134] The signal lines in the embodiments of this disclosure include data lines DT, first power lines PL1, sensing lines SS, and other conductors extending in the Y direction.

[0135] For example, as shown in Figures 4, 5, and 7, the display panel also includes a light-shielding layer LS, which overlaps with the first transistor T1 to improve the performance of the first transistor T1. For example, the light-shielding layer LS overlaps with the active layer T1s of the first transistor T1.

[0136] For example, as shown in Figures 4 to 15, the pixel circuit PXC also includes a storage capacitor Cst. The storage capacitor Cst includes a first electrode Ca and a second electrode Cb. The first electrode Ca is connected to the gate of the first transistor T1, the second electrode Cb is connected to the first electrode of the first transistor T1, the first electrode of the third transistor T3, and the first electrode of the light-emitting element EM, and the second electrode Cb is connected to the light-shielding layer LS.

[0137] For example, as shown in Figures 14 and 15, the display panel also includes a color filter layer CF, which is located between the light-emitting element EM and the pixel circuit PXC. The color filter layer CF includes an opening OPN2, through which the light-emitting element EM is connected to the pixel circuit PXC. Thus, a bottom-emitting display panel is formed.

[0138] Figure 16 is a layout diagram of a display panel provided in another embodiment of the present disclosure. Figure 17 is a layout diagram of a display panel provided in another embodiment of the present disclosure. Figure 18 is a layout diagram of a display panel provided in another embodiment of the present disclosure.

[0139] For example, as shown in Figures 7, 8, and 16, the first power line PL1 includes a main power line PL11 and a power connection line PL12. The main power line PL11 extends along the Y direction, and the power connection line PL12 extends along the X direction. The power connection line PL12, the gate line G1, and the gate line G2 are located on the same layer. The display panel shown in Figure 16 adjusts the power connection line PL12 to the conductive layer LY2, using a conductive material with good current resistance, which helps improve the uniformity of the power connection line PL12 and enhances its conductivity.

[0140] As shown in Figure 8, the power connection line PL12 is made of a semiconductor conductor that has been doped.

[0141] For example, as shown in Figure 16, the power connection line PL12 is located between the gate line G2 and the active layer T1s of the first transistor T1.

[0142] For example, as shown in Figure 16, the power connection line PL12 is connected to the main power line PL11 through the via Vm, and the power connection line PL12 is connected to the first transistor T1 through the via Vn.

[0143] For example, as shown in Figure 15, the light-emitting element EM is connected to the pixel circuit PXC through via H0. As shown in Figure 18, in the same sub-pixel SP, via H0 is closer to the gate line G1 than the active layer T1s of the first transistor T1. Because via H0 is deeper, this setting keeps via H0 further away from the pixel opening OPN1, avoiding the impact of a deeper via H0 on the display, reducing the risk of light leakage from the sub-pixel, and improving the display effect.

[0144] As shown in Figure 18, in the same sub-pixel SP, the via H0 and the active layer T1s of the first transistor T1 are arranged sequentially in the Y direction.

[0145] For example, as shown in Figures 10 and 18, the gate line G2 includes a main gate line G21 and a branch G22. The main gate line G21 extends along the direction X, and the branch G22 extends along the direction Y. The main gate line G21 and the branch G22 are an integral structure, and the branch G22 serves as the gate T3g of the third transistor T3.

[0146] For example, as shown in Figure 18, in the same sub-pixel SP, in the four sub-pixels SP in the same pixel group 66, the center line connecting the active layers of the first transistor T1, the second transistor T2, and the third transistor T3 of each sub-pixel is an obtuse triangle.

[0147] As shown in Figure 18, the via H0 is outside the obtuse triangle.

[0148] In the display panels shown in Figures 4 to 17, at least a portion of the via H0 is within a triangle (obtuse or acute angle triangle) formed by the center lines of the active layers of the transistors.

[0149] As shown in Figure 18, the second transistors T2 of two adjacent rows of sub-pixels are arranged in the Y direction.

[0150] For example, as shown in Figures 4 to 18, the power supply line PL12 of each sub-pixel is individually connected to the main power supply line PL11, which can reduce the sub-pixel differences caused by one-to-many connections.

[0151] Embodiments of this disclosure also provide a display device including any of the above-described display panels. For example, the display device is a bottom-emitting display device. The beneficial effects of this display device can be referred to the beneficial effects of the display panel, and will not be repeated here.

[0152] In some of the accompanying drawings of embodiments of this disclosure, plan views show directions X and Y, and cross-sectional views show direction Z. Directions X and Y are both parallel to the main surface of the substrate BS. Direction Z is perpendicular to the main surface of the substrate BS. Direction Z is perpendicular to direction X and perpendicular to direction Y. For example, direction Y intersects direction X. Embodiments of this disclosure are described with the example of directions X and Y being perpendicular. As shown in the cross-sectional view, the main surface of the substrate BS is the surface of the substrate BS used for fabricating various components. As shown in the cross-sectional view, the upper surface of the substrate BS is the main surface of the substrate BS.

[0153] For example, in embodiments of this disclosure, direction X may be a first direction, and direction Y may be a second direction. Gate line G1 may be a first gate line, and gate line G2 may be a second gate line.

[0154] It should be noted that ordinal numbers in components can be removed or replaced with other ordinal numbers depending on their order of appearance.

[0155] For clarity, the thickness of layers or regions is magnified in the drawings used to describe embodiments of this disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “above” or “below” another element, the element may be “directly” located “above” or “below” the other element, or there may be intermediate elements present.

[0156] Where there is no conflict, the embodiments of this disclosure and the features thereof may be combined with each other.

[0157] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A display panel, comprising: Multiple sub-pixels, at least one of the multiple sub-pixels includes a pixel circuit and a light-emitting element, the pixel circuit includes a first transistor, a second transistor and a third transistor, the first terminal of the second transistor is connected to the gate of the first transistor, and the first terminal of the third transistor is connected to the first terminal of the first transistor; The first gate line is connected to the gate of the second transistor; The second gate line is connected to the gate of the third transistor. Wherein, the first gate line extends along a first direction, the second gate line extends along the first direction, the first gate line and the second gate line are spaced apart from each other in a second direction, and the first direction and the second direction intersect.

2. The display panel according to claim 1, wherein, The first gate line and the second gate line, which are connected to the second transistor and the third transistor of the same sub-pixel, are different gate lines.

3. The display panel according to claim 1 or 2, wherein, The first gate line is configured as multiple lines, the second gate line is configured as multiple lines, and the multiple first gate lines are alternately arranged in the second direction.

4. The display panel according to any one of claims 1-3, wherein, The plurality of sub-pixels includes a plurality of pixel groups. Each pixel group includes two rows and two columns of four sub-pixels. The same first gate line is connected to two second transistors in the two rows of sub-pixels respectively. The pixel circuits at the locations of the four sub-pixels in the same pixel group are symmetrically arranged in the layout.

5. The display panel according to claim 4, wherein, The pixel circuits at the locations of the four sub-pixels in the same pixel group are symmetrically arranged with respect to a first axis parallel to the first direction and with respect to a second axis parallel to the second direction.

6. The display panel according to claim 4 or 5, wherein, Two second transistors in two rows of sub-pixels connected to the same first gate line are arranged in the first direction.

7. The display panel according to claim 6, wherein, In two sub-pixels of four sub-pixels in the same pixel group, the center line connecting the active layers of the first transistor, the second transistor, and the third transistor forms an obtuse triangle.

8. The display panel according to claim 7, wherein, In the other two sub-pixels of the four sub-pixels in the same pixel group, the center line connecting the active layers of the first transistor, the second transistor, and the third transistor forms an acute-angled triangle.

9. The display panel according to claim 4 or 5, wherein, Two second transistors in two rows of sub-pixels connected to the same first gate line are arranged in the second direction.

10. The display panel according to claim 9, wherein, In the four sub-pixels of the same pixel group, the center line connecting the active layers of the first transistor, the second transistor, and the third transistor is an obtuse triangle.

11. The display panel according to any one of claims 4-10, wherein, The four sub-pixels include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel. The first sub-pixel and the third sub-pixel are arranged along the first direction, the fourth sub-pixel and the second sub-pixel are arranged along the first direction, the first sub-pixel and the fourth sub-pixel are arranged along the second direction, and the third sub-pixel and the second sub-pixel are arranged along the second direction.

12. The display panel according to claim 11, wherein, The first sub-pixel is a red sub-pixel, the second sub-pixel is a green sub-pixel, the third sub-pixel is a blue sub-pixel, and the fourth sub-pixel is a white sub-pixel.

13. The display panel according to any one of claims 11-12, further comprising a data cable, a first power cable, and a sensing cable, wherein, The data line is connected to the second terminal of the second transistor. The first power line is connected to the second terminal of the first transistor. The sensing line is connected to the second terminal of the third transistor. The data line, the first power line, and the sensing line all extend along the second direction.

14. The display panel according to claim 13, wherein, The data lines are configured as multiple lines, including a first data line, a second data line, a third data line, and a fourth data line. The first data line is connected to the second transistor of the first sub-pixel, the second data line is connected to the second transistor of the second sub-pixel, the third data line is connected to the second transistor of the third sub-pixel, and the fourth data line is connected to the second transistor of the fourth sub-pixel.

15. The display panel according to claim 14, wherein, The fourth data line, the first data line, the second data line, and the third data line are arranged along the first direction. The sensing line is provided between the first data line and the second data line, and the first data line, the sensing line, and the second data line are located between the pixel openings of two adjacent columns of sub-pixels.

16. The display panel according to claim 15, wherein, The fourth data line and the third data line are respectively adjacent to the two first power lines. The fourth data line and the adjacent first power line are located between the pixel openings of two adjacent columns of sub-pixels. The third data line and the adjacent first power line are located between the pixel openings of two adjacent columns of sub-pixels, forming a structure in which a first power line, a fourth data line, a column of pixel openings, a first data line, a sensing line, a second data line, another column of pixel openings, a third data line, and another first power line are arranged sequentially in the first direction.

17. The display panel according to claim 16, wherein, The multiple data lines do not overlap with each other.

18. The display panel according to claim 14, wherein, The first power line and the sensing line are located between the pixel openings of two adjacent columns of sub-pixels, the first data line and the fourth data line are located between the pixel openings of two adjacent columns of sub-pixels, and the third data line and the second data line are located between the pixel openings of two adjacent columns of sub-pixels, forming a structure in which the first data line, the fourth data line, one column of pixel openings, the first power line, the sensing line, another column of pixel openings, the third data line, and the second data line are arranged sequentially in the first direction.

19. The display panel according to claim 18, wherein, Two signal lines extending along the second direction are provided between the pixel openings of each pair of adjacent sub-pixels.

20. The display panel according to any one of claims 13-19, wherein, The first power line includes a power main line and a power connection line. The power main line extends along the second direction, and the power connection line extends along the first direction. The power connection line, the first gate line, and the second gate line are located on the same layer.

21. The display panel according to claim 20, wherein, The power connection line is located between the second gate line and the active layer of the first transistor.

22. The display panel according to any one of claims 1-21, wherein, The light-emitting element is connected to the pixel circuit through a via. In the same sub-pixel, the via is closer to the first gate line than the active layer of the first transistor.

23. The display panel according to any one of claims 1-22, wherein, The second gate line includes a main gate line and a branch. The main gate line extends along the first direction, and the branch extends along the second direction. The main gate line and the branch are an integral structure, and the branch serves as the gate of the third transistor.

24. The display panel according to any one of claims 1-23, further comprising a light-shielding layer, wherein, The light-shielding layer overlaps with the first transistor.

25. The display panel according to claim 24, wherein, The pixel circuit further includes a storage capacitor, which includes a first electrode and a second electrode. The first electrode is connected to the gate of the first transistor, and the second electrode is connected to the first electrode of the first transistor, the first electrode of the third transistor, and the first electrode of the light-emitting element. The second electrode is also connected to the light-shielding layer.

26. The display panel according to any one of claims 1-25, further comprising a color filter layer, wherein, The color filter layer is located between the light-emitting element and the pixel circuit. The color filter layer includes an opening through which the light-emitting element is connected to the pixel circuit.

27. A display device comprising a display panel according to any one of claims 1-26.

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