Data processing method, apparatus and system

Abstract

Disclosed in embodiments of the present application are a data processing method, apparatus and system. Specifically, DQPSK mapping is performed on p first data streams having undergone RS encoding to obtain a plurality of DP-DQPSK signals, each DP-DQPSK signal comprising a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction. Compared with a cascade FEC transmission scheme, the embodiments of the present application do not need to perform cascade FEC encoding before DQPSK mapping, so that the plurality of DP-DQPSK signals to be sent have a lower bit rate and Baud rate. Therefore, the data processing method provided by the embodiments of the present application has the advantages of low complexity, low power consumption, low delay and the like, can be applied to multiple transmission scenarios, and is particularly suitable for coherent transmission scenarios of 800 Gbps or above (such as 1.6 Tbps) in the future.

Description

A data processing method, apparatus and system

[0001] This application claims priority to Chinese Patent Application No. 202410509410.2, filed with the State Intellectual Property Office of China on April 25, 2024, entitled “A Data Processing Method, Apparatus and System”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0003] Driven by 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards higher capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information.

[0004] Forward error correction (FEC) coding is used to correct transmission errors, resolving transmission errors and recovering the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, performs symbol mapping on the bit sequence resulting from the second FEC encoding to generate a corresponding symbol sequence, and finally transmits the generated symbol sequence to the receiving end via optical fiber. The second FEC encoding typically uses soft-decision decoding, which has high complexity and power consumption. Furthermore, convolutional interleaving is performed between the first and second FEC encodings to improve the overall performance of the cascaded FEC scheme, but this results in higher latency. Existing cascaded FEC coding schemes cannot meet the requirements of low complexity, low power consumption, and low latency coherent scenarios with speeds of 800Gbps or higher (such as 1.6Tbps), which is an urgent problem to be solved in the future. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system. These methods offer advantages such as low complexity, low power consumption, and low latency, making them applicable to a wide range of transmission scenarios, particularly suitable for future coherent transmission scenarios exceeding 800Gbps (e.g., 1.6Tbps).

[0006] In a first aspect, embodiments of this application provide a data processing method. Specifically, p first data streams encoded by Reed-Solomon (RS) are first acquired, where p is a positive integer multiple of 4 and p is an integer power of 2. Then, differential quadrature phase shift keying (DQPSK) is performed on the p first data streams to obtain multiple dual-polarization (DP) DQPSK signals, each DP-DQPSK signal including a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

[0007] It should be understood that for concatenated FEC coding schemes using RS encoding for the outer code, the introduction of the inner code leads to increased coding redundancy and a higher required baud rate. Furthermore, the inner code uses soft-decision decoding, requiring soft value information, resulting in higher overall power consumption for the concatenated FEC coding scheme. In this embodiment, DQPSK mapping is performed on the p first data streams encoded by RS to obtain multiple DP-DQPSK signals. Compared to the concatenated FEC coding scheme, this embodiment does not require concatenated FEC coding including the inner code before DQPSK mapping, reducing coding redundancy caused by the inner code encoding. This results in multiple DP-DQPSK signals to be transmitted having lower bit rates and baud rates. Since this scheme does not require inner code encoding, soft-decision decoding is not used, and soft value information is not required, which helps reduce overall power consumption. Moreover, DQPSK modulation can effectively combat colored noise. Therefore, the data processing method provided in this application has the advantages of low complexity, low power consumption, and low latency, and can be applied to a wide range of transmission scenarios, especially suitable for future coherent transmission scenarios of 800Gbps and above (such as 1.6Tbps).

[0008] In some possible implementations, DQPSK mapping of p first data streams to obtain multiple DP-DQPSK signals includes: DQPSK mapping of p first data streams to obtain q DP-DQPSK signals, where q = p / 2 or q = p / 4. That is, it can be that every 2 first data streams are DQPSK mapped to obtain 1 DP-DQPSK signal, or every 4 first data streams are DQPSK mapped to obtain 1 DP-DQPSK signal, thus adapting to various different scenarios.

[0009] In some possible implementations, p = 8, q = p / 2 = 4; or p = 16, q = p / 4 = 4 or q = p / 2 = 8; or p = 32, q = p / 4 = 8. This provides multiple correspondences between the values ​​of p and q, expanding the application scenarios of this scheme. It should be noted that for the scheme obtaining q = 4 DP-DQPSK signals through DQPSK mapping, the baud rate corresponding to each DP-DQPSK signal is 106.25 G Baud. For the 1.6T direct detection scheme widely used in short-range scenarios, it uses PAM4 modulation, transmits data through 8 channels, and also has a baud rate of 106.25 G Baud. That is to say, the data processing method provided in this application can use some of the devices in the existing 1.6T direct detection scheme, which has the advantage of lower cost.

[0010] In some possible implementations, each a in each first data stream RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS The p-value is a power of 2 greater than or equal to 4. For example, in each first data stream, every four adjacent RS symbols come from four RS codewords. The code length of the RS code is counted in units of symbols, and the symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code, which has a code length of 544 RS symbols, meaning that an RS codeword contains 544 RS symbols, and one RS symbol contains 10 bits. In each first data stream, every four adjacent RS symbols come from four RS codewords, and p is a positive integer multiple of 4 and a power of 2, which provides good resistance to colored noise.

[0011] In some possible implementations, p first data streams are obtained by processing 16 second data streams through a symbol-multiplexed Physical Media Attachment (PMA) layer. These 16 second data streams are obtained by processing the service data to be transmitted through a Physical Coding Sublayer (PCS) including RS coding. This document provides a specific implementation method for processing the service data to be transmitted to obtain p first data streams, improving the completeness of this scheme. For example, the bit rate of the data stream after 1.6T PCS processing is 1700 Gbits per second. After DQPSK mapping, four DP-DQPSK signals are obtained, with the same bit rate as before DQPSK mapping, and a corresponding baud rate (also called symbol rate) of 106.25 GBaud. For the 1.6T direct detection scheme widely used in short-range scenarios, PAM4 modulation is used, data is transmitted through 8 channels, and the baud rate is also 106.25 GBaud. In other words, the data processing method proposed in this application can use some of the devices in the existing 1.6T direct detection scheme, which has the advantage of lower cost.

[0012] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing, and t signals are obtained from 16 second data streams through 16:t PMA processing, where t is a positive integer multiple of 4. This provides a scheme for obtaining p first data streams by performing two-step PMA processing on the second data streams after PCS processing, which is well compatible with the application scenario shown in Figure 2. One step of the PMA processing is performed by the sending device, and the other step is performed by the sending processing module.

[0013] In some possible implementations, p first data streams are obtained by processing 16 second data streams through a 16:p PMA process. Here, a scheme is provided to obtain p first data streams by performing a one-step PMA process on the second data streams after PCS processing, which is well compatible with the application scenario shown in Figure 3. This PMA process is performed by the sending device.

[0014] In some possible implementations, the p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing. That is, for the application scenario shown in Figure 2, the sending processing module obtains the p first data streams by performing t:p PMA processing based on symbol multiplexing on t signals from the sending device, thus improving the data processing flow of the sending processing module.

[0015] In some possible implementations, t = 8, p = 8; or t = 16, p = 8; or t = 8, p = 16; or t = 16, p = 16. Several possible implementations of the t:p PMA processing are given here, which improves the scalability of this solution.

[0016] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding. This provides a method to directly obtain p first data streams by PCS processing of the service data to be sent, without requiring PMA processing, allowing for flexible selection of different implementation methods according to actual needs.

[0017] In some possible implementations, the method of having p=8 first data streams participate in DQPSK mapping can also be applied to scenarios containing two 800G services, improving the compatibility of this solution. Specifically, the first group of p first data streams consists of 4 first signals processed by 4:4PMA, 4 first signals processed by 32 third data streams processed by 32:4PMA, and 32 third data streams processed by PCS including RS encoding from the first service data to be sent. The second group of p first data streams consists of 4 first data streams processed by 4:4PMA, 4 second signals processed by 32 fourth data streams processed by 32:4PMA, and 32 fourth data streams processed by PCS including RS encoding from the second service data to be sent.

[0018] In some possible implementations, the method of having p=8 first data streams participate in DQPSK mapping can also be applied to scenarios containing four 400G services, improving the compatibility of this solution. In the p first data streams, the first group of two first data streams is obtained by processing two third signals using 2:2PMA, the two third signals are obtained by processing 16 fifth data streams using 16:2PMA, and the 16 fifth data streams are obtained by processing the third service data to be transmitted using PCS including RS encoding. In the p first data streams, the second group of two first data streams is obtained by processing two fourth signals using 2:2PMA, the two fourth signals are obtained by processing 16 sixth data streams using 16:2PMA, and the 16 sixth data streams are obtained by processing the fourth service data to be transmitted using PCS including RS encoding. In the p-stream of first data, the two first data streams in group 3 are obtained by processing two fifth signals using a 2:2 PMA. The two fifth signals are obtained by processing 16 seventh data streams using a 16:2 PMA. The 16 seventh data streams are obtained by processing the fifth service data to be transmitted using a PCS including RS encoding. In the p-stream of first data, the two first data streams in group 4 are obtained by processing two sixth signals using a 2:2 PMA. The two sixth signals are obtained by processing 16 eighth data streams using a 16:2 PMA. The 16 eighth data streams are obtained by processing the sixth service data to be transmitted using a PCS including RS encoding.

[0019] In some possible implementations, performing data processing including DQPSK mapping on p first data streams to obtain q dual-polarization DP-DQPSK signals includes: performing DQPSK mapping on every two first data streams in the p first data streams to obtain one DP-DQPSK signal, resulting in a total of q = p / 2 DP-DQPSK signals. The DQPSK mapping extracts two consecutive bits from each input first data stream and uses them as the phase change between two adjacent symbols in the DQPSK signal according to a mapping rule. It should be understood that the two bits mapped to one DP-DQPSK symbol come from four data streams, which is beneficial for combating colored noise.

[0020] In some possible implementations, each of the p first data streams undergoes DQPSK mapping to obtain a DQPSK signal in one polarization direction in a DP-DQPSK signal, ensuring that every two first data streams can be DQPSK mapped to obtain one DP-DQPSK signal.

[0021] In some possible implementations, performing data processing including DQPSK mapping on p first data streams to obtain q dual-polarization DP-DQPSK signals includes: performing DQPSK mapping on every 4 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, resulting in a total of q = p / 4 DP-DQPSK signals. It should be understood that the 4 bits mapped to one DP-DQPSK symbol come from 4 data streams, which helps to combat colored noise.

[0022] In some possible implementations, every two first data streams in the p first data streams are DQPSK mapped to obtain a DQPSK signal in one polarization direction in a DP-DQPSK signal, ensuring that every four first data streams can be DQPSK mapped to obtain a DP-DQPSK signal.

[0023] In some possible implementations, the data processing method provided in this application is applied to scenarios including Ethernet, optical transport networks, and space optical communication.

[0024] Secondly, embodiments of this application provide a data processing apparatus, comprising an acquisition unit and a processing unit. The acquisition unit is configured to acquire p first data streams encoded by RS, where p is a positive integer multiple of 4 and p is an integer power of 2. The processing unit is configured to perform DQPSK mapping on the p first data streams to obtain multiple DP-DQPSK signals, each DP-DQPSK signal including a DQPSK signal in a first polarization direction and a DQPSK signal in a second polarization direction.

[0025] In some possible implementations, the processing unit is specifically used to perform DQPSK mapping on p first data streams to obtain q DP-DQPSK signals, where q = p / 2 or q = p / 4.

[0026] In some possible implementations, p = 8, q = p / 2 = 4; or, p = 16, q = p / 4 = 4 or q = p / 2 = 8; or, p = 32, q = p / 4 = 8.

[0027] In some possible implementations, each a in each first data stream RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS An integer power greater than or equal to 4 and equal to 2. For example, in each first data stream, every four adjacent RS symbols come from four RS codewords.

[0028] In some possible implementations, p first data streams are obtained by PMA processing based on symbol multiplexing from 16 second data streams, and the 16 second data streams are obtained by PCS processing including RS encoding from the service data to be sent.

[0029] In some possible implementations, p first data streams are obtained by processing t signals through t:p PMA, and t signals are obtained by processing 16 second data streams through 16:t PMA, where t is a positive integer multiple of 4.

[0030] In some possible implementations, p first data streams are obtained by processing 16 second data streams through 16:p PMA.

[0031] In some possible implementations, p first data streams are obtained from t signals through t:p PMA processing based on symbol multiplexing.

[0032] In some possible implementations, t = 8, p = 8; or, t = 16, p = 8; or, t = 8, p = 16; or, t = 16, p = 16.

[0033] In some possible implementations, p first data streams are obtained from the service data to be sent through PCS processing, including RS encoding.

[0034] In some possible implementations, p = 8. The four first data streams in the first group of p first data streams are obtained by processing four first signals using a 4:4 PMA; the four first signals are obtained by processing 32 third data streams using a 32:4 PMA; and the 32 third data streams are obtained by processing the first service data to be transmitted using a PCS including RS encoding. The four first data streams in the second group of p first data streams are obtained by processing four second signals using a 4:4 PMA; the four second signals are obtained by processing 32 fourth data streams using a 32:4 PMA; and the 32 fourth data streams are obtained by processing the second service data to be transmitted using a PCS including RS encoding.

[0035] In some possible implementations, p = 8. The two first data streams in the first group of p first data streams are obtained by processing two third signals using a 2:2PMA process. The two third signals are obtained by processing 16 fifth data streams using a 16:2PMA process. The 16 fifth data streams are obtained by processing the third service data to be transmitted using a PCS including RS encoding. The two first data streams in the second group of p first data streams are obtained by processing two fourth signals using a 2:2PMA process. The two fourth signals are obtained by processing 16 sixth data streams using a 16:2PMA process. The 16 sixth data streams are obtained by processing the fourth service data to be transmitted using a PCS including RS encoding. The two first data streams in the third group of p first data streams are obtained by processing two fifth signals using a 2:2PMA process. The two fifth signals are obtained by processing 16 seventh data streams using a 16:2PMA process. The 16 seventh data streams are obtained by processing the fifth service data to be transmitted using a PCS including RS encoding. The two first data streams in the fourth group of p first data streams are obtained by processing the two sixth signals through 2:2PMA. The two sixth signals are obtained by processing the 16 eighth data streams through 16:2PMA. The 16 eighth data streams are obtained by processing the sixth service data to be sent through PCS including RS encoding.

[0036] In some possible implementations, the processing unit is specifically used to perform DQPSK mapping on every 2 first data streams in p first data streams to obtain 1 DP-DQPSK signal, so as to obtain a total of q = p / 2 DP-DQPSK signals.

[0037] In some possible implementations, each of the p first data streams is DQPSK mapped to obtain a DQPSK signal in one polarization direction in a DP-DQPSK signal.

[0038] In some possible implementations, the processing unit is specifically used to perform DQPSK mapping on every 4 first data streams in p first data streams to obtain 1 DP-DQPSK signal, so as to obtain a total of q = p / 4 DP-DQPSK signals.

[0039] In some possible implementations, every two first data streams in the p first data streams are DQPSK mapped to obtain a DQPSK signal in one polarization direction in a DP-DQPSK signal.

[0040] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0041] Thirdly, embodiments of this application provide a chip for performing the method as described in any of the embodiments of the first aspect.

[0042] Fourthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0043] Fifthly, embodiments of this application provide a transmitting device. The transmitting device includes a host-side device and an optical module as described in any embodiment of the fourth aspect. The optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

[0044] Sixthly, embodiments of this application provide an apparatus. The apparatus includes a processor and an interface. The processor is used to execute the method described in any embodiment of the first aspect and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The apparatus may be a router, switch, server, or optical transport network equipment, etc.

[0045] In a seventh aspect, embodiments of this application provide a communication system, which includes the transmitting device and receiving device described in the fifth aspect, wherein the transmitting device is used to transmit optical signals to the receiving device.

[0046] Eighthly, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any embodiment of the first aspect to be implemented.

[0047] Ninthly, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first aspect. Attached Figure Description

[0048] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0049] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0050] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0051] Figure 4 is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0052] Figure 5(a) is a data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0053] Figure 5(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0054] Figure 5(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0055] Figure 5(d) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0056] Figure 5(e) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0057] Figure 6(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application;

[0058] Figure 6(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0059] Figure 6(c) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0060] Figure 7 is a schematic diagram of an embodiment of DQPSK mapping of p first data streams in this application;

[0061] Figure 8 is a schematic diagram of another implementation of DQPSK mapping for p first data streams in this application;

[0062] Figure 9(a) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0063] Figure 9(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0064] Figure 10(a) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0065] Figure 10(b) is another data processing flowchart corresponding to the data processing method in the embodiments of this application;

[0066] Figure 11 is another data processing flowchart corresponding to the data processing method in the embodiment of this application;

[0067] Figure 12 is a schematic diagram of a data processing device in an embodiment of this application;

[0068] Figure 13 is a schematic diagram of an optical module in an embodiment of this application;

[0069] Figure 14 is a schematic diagram of a transmitting device in an embodiment of this application. Detailed Implementation

[0070] This application provides a data processing method, apparatus, and system. These methods offer advantages such as low complexity, low power consumption, and low latency, making them applicable to a wide range of transmission scenarios, particularly suitable for future coherent transmission scenarios exceeding 800Gbps (e.g., 1.6Tbps).

[0071] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0072] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be an LR optical module, such as a 1600LR module (a coherent optical module). Furthermore, the transmitting end device 01, transmitting end processing module 02, channel transmission medium 03, receiving end processing module 04, and receiving end device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0073] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs Reed-Solomon (RS) encoding on the data and then transmits the RS-encoded data to the transmitting processing module 02. The transmitting processing module 02 performs Differential Quadrature Phase Shift Keying (DQPSK) mapping on the RS-encoded data to obtain q dual-polarization (DP) DQPSK signals. These q DP-DQPSK signals are transmitted to the receiving processing module 04 via the channel transmission medium 03. The receiving processing module 04 performs DP-DQPSK demapping on the received q DP-DQPSK signals and transmits the demapping data to the receiving device 05. The receiving device 05 decodes the received data.

[0074] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs RS encoding and DQPSK mapping to obtain q DP-DQPSK signals and sends them to the transmission medium 03. The receiving device 05 performs DP-DQPSK demapping and decoding on the data received from the transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0075] It should be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0076] Figure 4 is a schematic flowchart of a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied to the sending end, for example, it can be implemented by the sending end processing module 02 shown in Figure 2 above, or by the sending end device 01 shown in Figure 3 above.

[0077] 101. Obtain p first data streams after RS ​​encoding.

[0078] In this embodiment, all p first data streams are RS-encoded data streams. It should be noted that the code length of the RS code in this embodiment is counted in units of symbols; the symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, meaning that an RS codeword includes 544 RS symbols, and one RS symbol contains 10 bits. Specifically, in each first data stream, every four adjacent RS symbols come from four RS codewords, where p is an integer multiple of 4 and a power of 2. Typically, p is 4, 8, 16, or 32, etc.

[0079] For example, in service transmissions applied to 1.6T Ethernet (1.6Terabit Ethernet, abbreviated as 1.6TE), the integer p is 8 or 16. As another example, in service transmissions applied to 3.2T Ethernet, the integer p is 16 or 32.

[0080] 102. Perform DQPSK mapping on p first data streams to obtain q DP-DQPSK signals.

[0081] It should be understood that a DP-DQPSK signal comprises one DQPSK signal in the X-polarization direction and one DQPSK signal in the Y-polarization direction, wherein the X-polarization direction and the Y-polarization direction are orthogonal to each other. The X-polarization direction can also be referred to as the first polarization direction, and the Y-polarization direction as the second polarization direction.

[0082] In some applications, DQPSK mapping is performed on every two first data streams from p first data streams to obtain one DP-DQPSK signal, resulting in a total of q = p / 2 DP-DQPSK signals. Specifically, one of the two first data streams is DQPSK mapped to obtain one DP-DQPSK signal in the X-polarization direction, and the other of the two first data streams is DQPSK mapped to obtain one DP-DQPSK signal in the Y-polarization direction. For example, p = 8, q = p / 2 = 4. Another example is p = 16, q = p / 2 = 8.

[0083] In other applications, DQPSK mapping is performed on every four first data streams out of p first data streams to obtain one DP-DQPSK signal, resulting in a total of q = p / 4 DP-DQPSK signals. Specifically, two of the four first data streams are DQPSK mapped to obtain one DP-DQPSK signal in the X-polarization direction, and the other two of the four first data streams are DQPSK mapped to obtain one DP-DQPSK signal in the Y-polarization direction. For example, p = 16, q = p / 4 = 4. Another example is p = 32, q = p / 4 = 8.

[0084] It should be noted that the combination of DQPSK mapping oriented towards the X polarization direction and DQPSK mapping oriented towards the Y polarization direction can also be called DP-DQPSK mapping.

[0085] Considering 1.6T Ethernet service transmission, the total bit rate of p first data streams is 106.25 × 2 × 8 = 1700 Gbits per second. It should also be understood that the bit rates in this application are nominal rates; in practical applications, the bit rate will have a certain offset range, for example, ±V0 (ppm) error, where V0 can be 20, 25, 50, or 100, etc. Each first data stream contains four consecutive RS symbols from four different RS codewords; each first data stream is also called a 4-symbol-quartet stream. In some specific applications, the first data streams also undergo symbol multiplexing-based Physical Media Attachment (PMA) processing, also known as PMA-S. More specifically, the first data streams are obtained through PMA processing based on 4-symbol-quartet multiplexing. It should be noted that, in the embodiments of this application, m0:m1 PMA means that m0 input data streams are symbolically multiplexed to obtain m1 output data streams. In some other specific applications, the first data stream is also processed by a Physical Coding Sublayer (PCS).

[0086] Figure 5(a) is a data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. Specifically, the 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are then subjected to symbol distribution and interleave to obtain 16 PCS Lanes. Among them, the symbol distribution is granular with 10 bits. Each of the 4 adjacent RS symbols in the 16 PCS Lanes comes from 4 different RS codewords. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6TAUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation, with a corresponding baud rate (also known as symbol rate) of 106.25 GBaud. Therefore, the total bit rate of the eight 1.6TAUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called the 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also called the 1.6TBASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 8 1.6T AUI-8 signals. The 8 1.6T AUI-8 signals are first processed by 1.6T 8:8PMA to obtain p = 8 first data streams, and then DQPSK mapping is performed to obtain q = p / 2 = 4 DP-DQPSK signals to be sent.

[0087] Figure 5(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(b), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. Each of the 16 1.6T AUI-16 signals has a bit rate of 106.25 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 53.125 G Baud. Therefore, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first processes them through 1.6T 16:8PMA to obtain p = 8 first data streams, and then performs DQPSK mapping to obtain q = p / 2 = 4 DP-DQPSK signals to be transmitted.

[0088] Figure 5(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(c), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is granular with 10 bits. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain p = 8 first data streams, and DQPSK mapping is performed to obtain q = p / 2 = 4 DP-DQPSK signals to be transmitted. The 1.6T PCS processing, 1.6T16:8PMA, and DQPSK mapping are implemented in the transmitting device 01.

[0089] Figure 6(a) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(a), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. Among them, the symbol distribution is in 10-bit granularity. The 16 PCS Lanes are processed by 1.6T 16:8PMA based on 4-symbol multiplexing to obtain 8 1.6T AUI-8 signals. Each of the eight 1.6T AUI-8 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the eight 1.6T AUI-8 signals is 106.25 × 2 × 8 = 1700 Gbits per second. Considering 1.6T Ethernet services, the 1.6T PCS is also called the 1.6T BASE-R PCS, and the 1.6T 16:8PMA is also called the 1.6T BASE-R 16:8PMA. The 1.6T PCS processing and 1.6T 16:8PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the eight 1.6T AUI-8 signals, first processes them through 1.6T 8:16PMA to obtain p = 16 first data streams, and then performs DQPSK mapping to obtain q = p / 4 = 4 DP-DQPSK signals to be transmitted.

[0090] Figure 6(b) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(b), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. The 16 PCS Lanes are processed by 1.6T 16:16PMA based on 4-symbol multiplexing to obtain 16 1.6T AUI-16 signals. Each of the 16 1.6T AUI-16 signals has a bit rate of 106.25 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 53.125 G Baud. Therefore, the total bit rate of the 16 1.6T AUI-16 signals is 106.25 × 16 = 1700 Gbits per second. The 1.6T PCS processing and 1.6T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives the 16 1.6T AUI-16 signals, first processes them through 1.6T 16:16PMA to obtain p = 16 first data streams, and then performs DQPSK mapping to obtain q = p / 4 = 4 DP-DQPSK signals to be transmitted.

[0091] Figure 6(c) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 6(c), 1.6T service data is processed by 1.6T PCS to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 16 PCS Lanes. The total bit rate of the 16 PCS Lanes is 106.25 × 16 = 1700 Gbits per second. The 16 PCS Lanes are used as p = 16 first data streams, and DQPSK mapping is performed to obtain q = p / 4 = 4 DP-DQPSK signals to be transmitted. The 1.6T PCS processing and DQPSK mapping are implemented in the transmitting device 01.

[0092] It should be noted that in the scenarios for 1.6T services shown in Figures 5(a), 5(b), and 5(c), p = 8 first data streams participate in DQPSK mapping. In the scenarios for 1.6T services shown in Figures 6(a), 6(b), and 6(c), p = 16 first data streams participate in DQPSK mapping. The method of p = 8 first data streams participating in DQPSK mapping is applicable not only to the 1.6T service scenarios described above but also to other service scenarios with a total rate of 1.6T, such as two 800G services or four 400G services.

[0093] Figure 5(d) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(d), consider two 800G service scenarios, where each 800G service data is processed by an 800G PCS to obtain 32 PCS Lanes. Specifically, each 800G PCS process includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain 32 PCS Lanes. The symbol distribution is granular with 10 bits. The 32 PCS Lanes are processed by 800G 32:4PMA based on 4-symbol multiplexing to obtain four 800G AUI-4 signals. The two 800G service data, after the above 800G PCS and 800G 32:4PMA, obtain a total of two sets of 800G AUI-4 signals, totaling eight signal streams. Each of the two 800G AUI-4 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the two 800G AUI-4 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the two 800G AUI-4 signals. Each 800G AUI-4 signal is processed by 800G 4:4 PMA to obtain four first data streams, resulting in a total of p = eight first data streams. These eight first data streams are then DQPSK mapped to obtain q = p / 2 = four DP-DQPSK signals to be transmitted.

[0094] Figure 5(e) is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 5(e), consider four 400G service scenarios, where each 400G service data is processed by 400G PCS to obtain 16 PCS Lanes. Specifically, each 400G PCS process includes two RS encoding processing units. For example, the 400G PCS process in the figure may include RS-A and RS-B, and the 400G PCS process may also include RS-C and RS-D. The encoded data streams obtained after the two RS encoding processing units are then symbol-distributed and interleaved to obtain 16 PCS Lanes. The symbol distribution is granular with 10 bits. The 16 PCS Lanes are processed by 400G 16:2PMA based on 4-symbol multiplexing to obtain two 400G AUI-2 signals. The four 400G service data are processed by the above 400G PCS and 400G 16:2PMA to obtain a total of four sets of 400G AUI-2 signals, totaling eight signal streams. Each of the four 400G AUI-2 signals has a bit rate of 212.5 Gbits per second, using PAM4 modulation with a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. Therefore, the total bit rate of the four 400G AUI-2 signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The transmitting processing module 02 receives the four 400G AUI-2 signals. Each 400G AUI-2 signal is processed through 400G 2:2 PMA to obtain two first data streams, resulting in a total of p = 8 first data streams. These 8 first data streams are then DQPSK mapped to obtain q = p / 2 = 4 DP-DQPSK signals to be transmitted.

[0095] It should be noted that in the data processing method proposed in this application, four DP-DQPSK signals to be transmitted are obtained after DQPSK mapping, and the baud rate of each DP-DQPSK signal is 106.25 G Baud. For the 1.6T direct detection scheme widely used in short-range scenarios, PAM4 modulation is used, and data is transmitted through 8 channels, with a baud rate of 106.25 G Baud as well. In other words, the data processing method provided in this application can utilize some of the devices in existing 1.6T direct detection schemes, offering the advantage of lower cost.

[0096] It should also be understood that the baud rates in this application are all nominal rates. In practical applications, the baud rate of the DP-DQPSK signal will have a certain error range. For example, the baud rate may have an error of ±V1 (ppm), where V1 can be 20, 25, 50 or 100, etc.

[0097] The following section details the method for performing DQPSK mapping on p first data streams, taking into account the possible values ​​of p.

[0098] For the scenario where p=8, for example, as shown in Figure 5(a), 8 first data streams are obtained from 1.6T 8:8PMA. As another example, as shown in Figures 5(b) and 5(c), 8 first data streams are obtained from 1.6T 16:8PMA. As yet another example, as shown in Figure 5(d), a total of 8 first data streams are obtained from 2 groups of 800G 32:4PMA. And as yet another example, as shown in Figure 5(e), a total of 8 first data streams are obtained from 4 groups of 400G 16:2PMA.

[0099] Figure 7 is a schematic diagram of one embodiment of DQPSK mapping for p first data streams in this application. As shown in Figure 7, taking p=8 as an example, every two first data streams in p=8 (i.e., first data stream 0 to first data stream 7) are mapped by DP-DQPSK to obtain one DP-DQPSK signal, resulting in a total of q=4 DP-DQPSK signals. Specifically, each of the eight first data streams is mapped by DQPSK to obtain one DP-DQPSK signal in one polarization direction. For example, first data stream 0 is mapped by DQPSK to obtain DP-DQPSK signal 0 in the X polarization direction, first data stream 1 is mapped by DP-DQPSK to obtain DQPSK signal 0 in the Y polarization direction, and so on.

[0100] It should be understood that the DQPSK mapping obtains two consecutive bits (A, B) from the first input data stream i (0 ≤ i ≤ 7) and uses them as the phase change between successive symbols in the DQPSK signal according to the mapping rules shown in Table 1 below. The phase change is represented in radians. Table 1 also shows the mapping relationship between the two bits and the DQPSK symbol values.

[0101] Table 1

[0102] Considering 1.6T services, the total bit rate of the eight first data streams and four DP-DQPSK signals is 106.25 × 2 × 4 × 2 = 1700 Gbits per second. The baud rate corresponding to the four DP-DQPSK signals is 106.25 G Baud. For the 1.6T direct detection scheme widely used in short-range scenarios, PAM4 modulation is employed, and data is transmitted through eight channels, also with a baud rate of 106.25 G Baud. In other words, the data processing method proposed in this application can utilize some of the components of existing 1.6T direct detection schemes, offering the advantage of lower cost.

[0103] It should be noted that the first data processing with p=8 mentioned above is applicable to service scenarios with a total rate of 1.6T, including one 1.6T service, two 800G services, and four 400G services, and can be applied to a wider range of scenarios.

[0104] For the scenario where p=16, for example, as shown in Figure 6(a), 16 first data streams are obtained from 1.6T 8:16PMA. Another example, as shown in Figure 6(b), 16 first data streams are obtained from 1.6T 16:16PMA. Yet another example, as shown in Figure 6(c), 16 first data streams are obtained from 1.6T PCS.

[0105] Figure 8 is a schematic diagram of another implementation of DQPSK mapping for p first data streams in this application. As shown in Figure 8, every 4 first data streams in p = 16 (i.e., first data stream 0 to first data stream 15) are mapped using DP-DQPSK to obtain 1 DP-DQPSK signal, resulting in a total of q = 4 DP-DQPSK signals. Specifically, every 2 first data streams in the 16 first data streams are mapped using DQPSK to obtain 1 DP-DQPSK signal in one polarization direction. For example, first data stream 0 and first data stream 1 are mapped using DQPSK to obtain DP-DQPSK signal 0 in the X polarization direction, first data stream 2 and first data stream 3 are mapped using DQPSK to obtain DP-DQPSK signal 0 in the Y polarization direction, and so on.

[0106] It should be understood that the DQPSK mapping obtains one bit from each of the two input first data streams, for a total of two bits (A, B), and uses them as the phase change of two adjacent symbols in the DQPSK signal according to the mapping rules shown in Table 1.

[0107] It should be noted that, using the data processing method proposed in this application, the data stream after processing by 1.6T PCS has a bit rate of 1700 Gbits per second. After DQPSK mapping, four DP-DQPSK signals are obtained, with the same bit rate as before DQPSK mapping, and a corresponding baud rate (also known as symbol rate) of 106.25 G Baud. For the 1.6T direct detection scheme widely used in short-range scenarios, PAM4 modulation is employed, data is transmitted through 8 channels, and the baud rate is also 106.25 G Baud. In other words, the data processing method proposed in this application can utilize some of the devices in existing 1.6T direct detection schemes, offering the advantage of lower cost.

[0108] It should be understood that, compared with existing cascaded FEC schemes, the embodiments of this application do not require cascaded FEC encoding before DQPSK mapping, resulting in multiple DP-DQPSK signals to be transmitted having lower bit rates and baud rates. Therefore, the data processing method proposed in this application has advantages such as low complexity, low power consumption, and low latency, and can be applied to a wide range of transmission scenarios, especially suitable for future coherent transmission scenarios above 800Gbps (such as 1.6Tbps).

[0109] The above considers the data processing method for 1.6T Ethernet service transmission. The following presents the data processing method for future 3.2T service transmission.

[0110] Figure 9(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. Figure 9(b) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. As shown in Figures 9(a) and 9(b), in some specific applications, p = 16 and q = 8.

[0111] As shown in Figure 9(a), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. Symbol distribution is performed at a 10-bit granularity. The 16 PCS Lanes are then processed by 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and 3.2T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through a 3.2T 16:16PMA to obtain p = 16 first data streams, and then performs DQPSK mapping to obtain q = p / 2 = 8 DP-DQPSK signals to be transmitted. At this time, the baud rate (also known as the symbol rate) corresponding to each DP-DQPSK signal is 106.25G Baud.

[0112] As shown in Figure 9(b), the 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. These 16 PCS Lanes serve as p = 16 first data streams, which are then mapped using DQPSK to obtain q = p / 2 = 8 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and DQPSK mapping are implemented in the transmitting device 01. At this time, the baud rate (also known as the symbol rate) corresponding to each DP-DQPSK signal is 106.25 G Baud.

[0113] Figure 10(a) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. Figure 10(b) is another data processing flowchart corresponding to the data processing method in the embodiment of this application. As shown in Figures 10(a) and 10(b), in some specific applications, p = 16 and q = 4.

[0114] As shown in Figure 10(a), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 1.6T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units undergo symbol distribution and interleaving to obtain the 16 PCS Lanes. Symbol distribution is performed at a 10-bit granularity. The 16 PCS Lanes are then processed by 3.2T 16:16PMA based on 4-symbol multiplexing to obtain 16 3.2T AUI-16 signals. The 3.2T PCS processing and 3.2T 16:16PMA are implemented in the transmitting device 01. The transmitting processing module 02 receives 16 1.6T AUI-16 signals, first processes them through 3.2T 16:16PMA to obtain p = 16 first data streams, and then performs DQPSK mapping to obtain q = p / 4 = 4 DP-DQPSK signals to be transmitted. At this time, the baud rate (also known as the symbol rate) corresponding to each DP-DQPSK signal is 212.5G Baud.

[0115] As shown in Figure 10(b), 3.2T service data undergoes 3.2T PCS processing to obtain 16 PCS channel data streams, also known as 16 PCS Lanes. The 3.2T PCS processing includes four RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the four RS encoding processing units are symbol-distributed and interleaved to obtain the 16 PCS Lanes. These 16 PCS Lanes serve as p = 16 first data streams, which are then mapped using DQPSK to obtain q = p / 4 = 4 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and DQPSK mapping are implemented in the transmitting device 01. At this time, the baud rate (also known as the symbol rate) corresponding to each DP-DQPSK signal is 212.5 G Baud.

[0116] Figure 11 is another data processing flowchart corresponding to the data processing method in this application embodiment. As shown in Figure 11, in some specific applications, p = 32 and q = 8. 3.2T service data is processed by 3.2T PCS to obtain 32 PCS channel data streams, also known as 32 PCS Lanes. The 3.2T PCS processing includes 4 RS encoding processing units, namely RS-A, RS-B, RS-C, and RS-D in the figure. The encoded data streams obtained after the 4 RS encoding processing units are symbol-distributed and interleaved to obtain 32 PCS Lanes. The 32 PCS Lanes serve as the first data stream with p = 32, and DQPSK mapping is performed to obtain q = p / 4 = 8 DP-DQPSK signals to be transmitted. The 3.2T PCS processing and DQPSK mapping are implemented in the transmitting device 01. At this time, the baud rate (also known as the symbol rate) corresponding to each DP-DQPSK signal is 106.25 G Baud.

[0117] Figure 12 is a schematic diagram of a data processing device according to an embodiment of this application. As shown in Figure 12, the data processing device includes an acquisition unit 201 and a processing unit 202. The acquisition unit 201 is used to execute the operation of step 101 in the above embodiment, and the processing unit 202 is used to execute the operation of step 102 in the above embodiment. It should be understood that the data processing device provided in this application can also be implemented in other ways. For example, the unit division in the above device is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system. In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or they can be independent physical units, or two or more functional units can be integrated into one processing unit. The integrated unit can be implemented in hardware or in the form of software functional units.

[0118] Figure 13 is a schematic diagram of an optical module structure in an embodiment of this application. As shown in Figure 13, the optical module includes a processor 301 and an interface 302. The processor 301 is used to execute the operation of step 102 in the above embodiment. In one possible implementation, the processor 301 includes the processing unit 202 shown in Figure 12. The interface 302 can be a transceiver or an input / output interface. The interface 302 is used to receive signals from other devices and transmit them to the processor 301 or to send signals from the processor 301 to other devices. As an example, after the processor 301 performs the above DQPSK mapping, it obtains a DP-DQPSK signal and sends the DP-DQPSK signal through the interface 302. In this example, the interface 202 can specifically refer to an electrical interface. As another example, after the processor 301 performs DQPSK mapping, it obtains a DP-DQPSK signal. The modulator in the optical module performs electro-optical conversion and other signal processing based on the DP-DQPSK signal to obtain an optical signal, and then sends the optical signal through the interface 302. In this example, the interface 302 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 303, wherein the memory 303 is used to store program instructions and data.

[0119] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0120] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules are connected to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0121] Figure 14 is a schematic diagram of a transmitting device according to an embodiment of this application. As shown in Figure 14, the transmitting device includes a host-side device 401 and an optical module 402. The host-side device 401 is used to send data to the optical module 402, and the optical module 402 generates an optical signal based on the data sent by the host-side device 401 and transmits the optical signal through the channel. For example, the host-side device may specifically be a switch, router, or server. The transmitting device can be a communication device including the host-side device 401 and the optical module 402. It should also be understood that the transmitting device in the embodiments of this application is named based on the data flow direction and does not limit the function of the device. For example, the transmitting device may also have a receiving function.

[0122] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0123] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0124] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0125] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the method performed as described in the above method embodiments to be implemented.

[0126] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0127] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0128] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0129] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0130] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0131] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0132] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Obtain p first data streams after Reed-Solomon RS encoding, where p is a positive integer multiple of 4 and p is an integer power of 2; Differential quadrature phase shift keying (DQPSK) mapping is performed on the p first data streams to obtain multiple dual-polarization DP-DQPSK signals. Each DP-DQPSK signal includes a DQPSK signal in the first polarization direction and a DQPSK signal in the second polarization direction.

2. The method according to claim 1, characterized in that, Performing DQPSK mapping on the p first data streams to obtain multiple DP-DQPSK signals includes: The p first data streams are DQPSK mapped to obtain q DP-DQPSK signals, where q = p / 2 or q = p / 4.

3. The method according to claim 2, characterized in that, p = 8, q = p / 2 = 4; Alternatively, p = 16, q = p / 4 = 4 or q = p / 2 = 8; Alternatively, p = 32, q = p / 4 = 8.

4. The method according to any one of claims 1 to 3, characterized in that, Each a in the first data stream RS The adjacent RS symbols are respectively from a RS One RS codeword, a RS An integer power greater than or equal to 4 and equal to 2.

5. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained by processing 16 second data streams through a symbol-based physical media adaptation layer (PMA). The 16 second data streams are obtained by processing the service data to be sent through a physical coding sublayer (PCS) including RS coding.

6. The method according to claim 5, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA, and the t signals are obtained by processing the 16 second data streams through 16:t PMA, where t is a positive integer multiple of 4.

7. The method according to claim 5, characterized in that, The p first data streams are obtained by processing the 16 second data streams using 16:pPMA.

8. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained by processing t signals through t:p PMA based on symbol multiplexing.

9. The method according to claim 6 or 8, characterized in that, t = 8, p = 8; or t = 16, p = 8; or t = 8, p = 16; Alternatively, t = 16, p = 16.

10. The method according to any one of claims 1 to 4, characterized in that, The p first data streams are obtained by processing the service data to be sent through a PCS including RS encoding.

11. The method according to any one of claims 1 to 4, characterized in that, p＝8； The four first data streams in the first group of the p first data streams are obtained by processing four first signals through 4:4PMA. The four first signals are obtained by processing 32 third data streams through 32:4PMA. The 32 third data streams are obtained by processing the first service data to be sent through PCS including RS encoding. The four first data streams in the second group of the p first data streams are obtained by processing four second signals through a 4:4 PMA. The four second signals are obtained by processing 32 fourth data streams through a 32:4 PMA. The 32 fourth data streams are obtained by processing the second service data to be sent through a PCS including RS encoding.

12. The method according to any one of claims 1 to 4, characterized in that, p＝8； The two first data streams in the first group of the p first data streams are obtained by processing two third signals through 2:2PMA. The two third signals are obtained by processing 16 fifth data streams through 16:2PMA. The 16 fifth data streams are obtained by processing the third service data to be sent through PCS including RS encoding. The two first data streams in the second group of the p first data streams are obtained by processing two fourth signals through 2:2PMA. The two fourth signals are obtained by processing 16 sixth data streams through 16:2PMA. The 16 sixth data streams are obtained by processing the fourth service data to be sent through PCS including RS encoding. The two first data streams in the third group of the p first data streams are obtained by processing the two fifth signals through 2:2PMA. The two fifth signals are obtained by processing the 16 seventh data streams through 16:2PMA. The 16 seventh data streams are obtained by processing the fifth service data to be sent through PCS including RS encoding. The two first data streams in the fourth group of the p first data streams are obtained by processing the two sixth signals through a 2:2PMA process. The two sixth signals are obtained by processing the 16 eighth data streams through a 16:2PMA process. The 16 eighth data streams are obtained by processing the sixth service data to be sent through a PCS process including RS encoding.

13. The method according to any one of claims 1 to 12, characterized in that, Data processing, including DQPSK mapping, is performed on the p first data streams to obtain q dual-polarization DP-DQPSK signals, including: DQPSK mapping is performed on every 2 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so that a total of q = p / 2 DP-DQPSK signals are obtained.

14. The method according to claim 13, characterized in that, Each of the p first data streams is DQPSK mapped to obtain a DQPSK signal in one polarization direction of the 1 DP-DQPSK signal.

15. The method according to any one of claims 1 to 12, characterized in that, Data processing, including DQPSK mapping, is performed on the p first data streams to obtain q dual-polarization DP-DQPSK signals, including: DQPSK mapping is performed on every 4 first data streams in the p first data streams to obtain 1 DP-DQPSK signal, so that a total of q = p / 4 DP-DQPSK signals are obtained.

16. The method according to claim 15, characterized in that, In the p first data streams, every two first data streams are DQPSK mapped to obtain a DQPSK signal in one polarization direction in the 1 DP-DQPSK signal.

17. The method according to any one of claims 1 to 16, characterized in that, The data processing method is applicable to scenarios including Ethernet, optical transport networks, and space optical communication.

18. The method according to any one of claims 1 to 17, characterized in that, In each of the first data streams, every four adjacent RS symbols come from four RS codewords.

19. A data processing apparatus, characterized in that, The data processing device includes: an acquisition unit and a processing unit; The acquisition unit is used to: acquire p first data streams encoded by Reed-Solomon RS, where p is a positive integer multiple of 4 and p is an integer power of 2; The processing unit is used to: perform differential quadrature phase shift keying (DQPSK) mapping on the p first data streams to obtain multiple dual-polarization DP-DQPSK signals, each of the DP-DQPSK signals including a DQPSK signal in the first polarization direction and a DQPSK signal in the second polarization direction.

20. The data processing apparatus according to claim 19, characterized in that, The processing unit is specifically used to: perform DQPSK mapping on the p first data streams to obtain q DP-DQPSK signals, where q = p / 2 or q = p / 4.

21. The data processing apparatus according to claim 20, characterized in that, p = 8, q = p / 2 = 4; Alternatively, p = 16, q = p / 4 = 4 or q = p / 2 = 8; Alternatively, p = 32, q = p / 4 = 8.

22. The data processing apparatus according to any one of claims 19 to 21, characterized in that, In each of the first data streams, every four adjacent RS symbols come from four RS codewords.

23. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 18.

24. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used to perform the method as described in any one of claims 1 to 18 and to transmit and receive signals through the interface.

25. A transmitting device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 24, wherein the optical module is used to generate an optical signal based on data from the host-side device and to transmit the optical signal.

26. A communication system, characterized in that, include: The transmitting device and the receiving device as described in claim 25, wherein the transmitting device is configured to transmit a signal to the receiving device.

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