PWM signal generation circuit, pixel circuit, display substrate, display device and electronic device

Abstract

A PWM signal generation circuit, comprising: a first signal transmission circuit; and a second signal transmission circuit, wherein a first output end of the first signal transmission circuit is connected to a second output end of the second signal transmission circuit and serves as an output end of the PWM signal generation circuit; a first high level for generating a first output signal of the first signal transmission circuit is different from a second high level for generating a second output signal of the second signal transmission circuit; and an output signal of the PWM signal generation circuit has a step between the first high level and the second high level. Also provided are a pixel circuit, a display substrate, a display device and an electronic device.

Description

PWM signal generation circuit, pixel circuit, display substrate, display device and electronic device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of circuit, and more particularly, to a pulse width modulation (PWM) signal generation circuit, a pixel circuit, a display substrate comprising the pixel circuit, a display device comprising the display substrate, and an electronic device comprising the display device. BACKGROUND

[0002] When driving display using LEDs in a pulse width modulation (PWM) driving mode, if a Gamma 2.2 luminance scheme of 8 bits is to be implemented, at least 10 to 12 sub-frames are usually required. For applications with a large number of rows of display screens, the writing time of each row of data signals is less than 1 μs, and therefore the data writing time is severely insufficient.

[0003] SUMMARY

[0004] Embodiments of the present disclosure aim to provide a pixel circuit to implement a Gamma 2.2 luminance scheme of 8 bits using fewer sub-frames, so as to ensure that the refresh time of each sub-frame is sufficient for the writing of each row of data signals. Embodiments of the present disclosure also provide a PWM signal generation circuit to generate a Sweep signal that can be applied to the pixel circuit according to the present disclosure. In addition, embodiments of the present disclosure also provide a display substrate comprising the pixel circuit according to the present disclosure, a display device comprising the display substrate according to embodiments of the present disclosure, and an electronic device comprising the display device according to embodiments of the present disclosure.

[0005] Embodiments of the present disclosure provide a PWM signal generation circuit, comprising: a first signal transfer circuit; and a second signal transfer circuit, wherein a first output end of the first signal transfer circuit is connected to a second output end of the second signal transfer circuit, and serves as an output end of the PWM signal generation circuit, and wherein a first high level used to generate a first output signal of the first signal transfer circuit is different from a second high level used to generate a second output signal of the second signal transfer circuit, and the output signal of the PWM signal generation circuit has a step between the first high level and the second high level.

[0006] According to embodiments of the present disclosure, the first signal transfer circuit and the second signal transfer circuit are connected to a first clock signal and a second clock signal, the first clock signal and the second clock signal are periodic signals, have the same waveform, and have a duty cycle of 20%-40%.

[0007] According to embodiments of the present disclosure, the first signal transfer circuit includes a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module. The first input module, the first forward voltage generation module, the first reverse voltage generation module, and the first signal generation module are connected to a first node of the first signal transfer circuit. The first forward voltage generation module and the first reverse voltage generation module are connected to a first control node of the first signal transfer circuit. The first reverse voltage generation module and the first signal generation module are connected to a second node of the first signal transfer circuit. The first signal generation module and the first output enable module are connected to a first output node of the first signal transfer circuit. The second signal transfer circuit includes a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module. The second input module, the second forward voltage generation module, the second reverse voltage generation module, and the second signal generation module are connected to a third node of the second signal transfer circuit. The second forward voltage generation module and the second reverse voltage generation module are connected to a second control node of the second signal transfer circuit. The second reverse voltage generation module and the second signal generation module are connected to a fourth node of the second signal transfer circuit. The second signal generation module and the second output enable module are connected to a second output node of the second signal transfer circuit.

[0008] According to embodiments of the present disclosure, the first input module includes a first input transistor, and the second input module includes a second input transistor. A first end of the first input transistor serves as a first input end of the first signal transfer circuit, a first input signal is applied to the first end of the first input transistor, a second end of the first input transistor is connected to the first node, and the second clock signal is applied to a gate of the first input transistor. A first end of the second input transistor serves as a second input end of the second signal transfer circuit, a second input signal is applied to the first end of the second input transistor, a second end of the second input transistor is connected to the third node, and the first clock signal is applied to a gate of the second input transistor.

[0009] According to embodiments of the present disclosure, the first forward voltage generating module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second forward voltage generating module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. A high level is applied to a first terminal of the first transistor, a gate of the first transistor is connected to the first control node, and a second terminal of the first transistor is connected to a first terminal of the second transistor. A second terminal of the second transistor is connected to the first node, and the first clock signal is applied to a gate of the second transistor. The second clock signal is applied to a first terminal of the third transistor and a gate of the fourth transistor, a gate of the third transistor is connected to the first node, a second terminal of the third transistor and a second terminal of the fourth transistor are connected to the first control node, and a first terminal of the fourth transistor is connected to a low level. A high level is applied to a first terminal of the fifth transistor, a gate of the fifth transistor is connected to the second control node, and a second terminal of the fifth transistor is connected to a first terminal of the sixth transistor. A second terminal of the sixth transistor is connected to the third node, and the second clock signal is applied to a gate of the sixth transistor. The first clock signal is applied to a first terminal of the seventh transistor and a gate of the eighth transistor, a gate of the seventh transistor is connected to the third node, a second terminal of the seventh transistor and a second terminal of the eighth transistor are connected to the second control node, and a first terminal of the eighth transistor is connected to a low level.

[0010] According to embodiments of the present disclosure, the first reverse voltage generation module includes a ninth transistor, a tenth transistor and an eleventh transistor, and the second reverse voltage generation module includes a twelfth transistor, a thirteenth transistor and a fourteenth transistor. A high level is applied to a first terminal of the ninth transistor, a gate of the ninth transistor is connected to the first node, and a second terminal of the ninth transistor is connected to the second node. A first terminal of the tenth transistor is connected to a second terminal of the eleventh transistor, and is connected to the first control node via a first capacitor. The first clock signal is applied to a gate of the tenth transistor and a first terminal of the eleventh transistor, a second terminal of the tenth transistor is connected to the second node, and a gate of the eleventh transistor is connected to the first control node. A high level is applied to a first terminal of the twelfth transistor, a gate of the twelfth transistor is connected to the third node, and a second terminal of the twelfth transistor is connected to the fourth node. A first terminal of the thirteenth transistor is connected to a second terminal of the fourteenth transistor, and is connected to the second control node via a second capacitor. The second clock signal is applied to a gate of the thirteenth transistor and a first terminal of the fourteenth transistor, a second terminal of the thirteenth transistor is connected to the fourth node, and a gate of the fourteenth transistor is connected to the second control node.

[0011] According to embodiments of the present disclosure, the first signal generation module includes a fifteenth transistor and a sixteenth transistor, and the second signal generation module includes a seventeenth transistor and an eighteenth transistor. The first high level is applied to a first terminal of the fifteenth transistor, a gate of the fifteenth transistor is connected to the second node, and is connected to the first terminal of the fifteenth transistor via a third capacitor, and a second terminal of the fifteenth transistor is connected to the first output node. A first terminal of the sixteenth transistor is connected to a low level, a gate of the sixteenth transistor is connected to the first node, and a second terminal of the sixteenth transistor is connected to the first output node. The second high level is applied to a first terminal of the seventeenth transistor, a gate of the seventeenth transistor is connected to the fourth node, and is connected to the first terminal of the seventeenth transistor via a fourth capacitor, and a second terminal of the seventeenth transistor is connected to the second output node. A first terminal of the eighteenth transistor is connected to a low level, a gate of the eighteenth transistor is connected to the third node, and a second terminal of the eighteenth transistor is connected to the second output node.

[0012] According to embodiments of the present disclosure, the first output enable module includes a first output transistor, the second output enable module includes a second output transistor, the first output transistor is connected between the first output node and the first output terminal, and the second output transistor is connected between the second output node and the second output terminal. The first output signal is output to the first output terminal via the first output transistor, and the second output signal is output to the second output terminal via the second output transistor. The first output signal is also output to the gate of the second output transistor as an output enable signal of the second signal transfer circuit, and the second output signal is also output to the gate of the first output transistor as an output enable signal of the first signal transfer circuit.

[0013] According to embodiments of the present disclosure, the first signal generation module further includes a fifth capacitor and a nineteenth transistor, and the second signal generation module further includes a sixth capacitor and a twentieth transistor. The first clock signal is applied to a first terminal of the fifth capacitor, and a second terminal of the fifth capacitor is connected to the gate of the sixteenth transistor. The second clock signal is applied to a second terminal of the sixth capacitor, and a second terminal of the sixth capacitor is connected to the gate of the eighteenth transistor. The gate of the sixteenth transistor is connected to the first node via the nineteenth transistor, and the gate of the eighteenth transistor is connected to the third node via the twentieth transistor.

[0014] According to embodiments of the present disclosure, the second high level is twice the first high level.

[0015] According to embodiments of the present disclosure, the output signal of the PWM signal generation circuit is at the first duration of the first high level and at the second duration of the second high level.

[0016] Embodiments of the present disclosure also provide a pixel circuit, including: a driving module; a light emitting control module; and a light emitting element. The driving module is connected to the light emitting control module, and the light emitting control module and the light emitting element are connected in series between a power supply voltage and a ground voltage. The light emitting control module includes a first light emitting control module and a second light emitting control module connected to each other. The first light emitting control module is accessed with a first data signal and a first Sweep signal, the second light emitting control module is accessed with a second data signal and a second Sweep signal, and the first light emitting control module and the second light emitting control module are accessed with a first scan signal. The first Sweep signal and the second Sweep signal are different, and the first Sweep signal and the second Sweep signal are generated by a PWM signal generation circuit according to embodiments of the present disclosure.

[0017] According to embodiments of the present disclosure, the first light emitting control module includes a first control transistor, a second control transistor and a first control capacitor, and the second light emitting control module includes a third control transistor, a fourth control transistor and a second control capacitor. The first Sweep signal is applied to a first terminal of the first control capacitor, and a second terminal of the first control capacitor is connected to a gate of the first control transistor. The first data signal is applied to a first terminal of the second control transistor, the first scan signal is applied to a gate of the second control transistor, and a second terminal of the second control transistor is connected to the gate of the first control transistor. The second Sweep signal is applied to a first terminal of the second control capacitor, and a second terminal of the second control capacitor is connected to a gate of the third control transistor. The second data signal is applied to a first terminal of the fourth control transistor, the first scan signal is applied to a gate of the fourth control transistor, and a second terminal of the fourth control transistor is connected to the gate of the third control transistor. A first terminal of the first control transistor is connected to a first terminal of the third control transistor, and a second terminal of the first control transistor is connected to a second terminal of the third control transistor.

[0018] According to embodiments of the present disclosure, the driving module is accessed with a second scan signal, and the driving module includes a first driving transistor, a second driving transistor, a third driving transistor and a first driving capacitor. A driving current is applied to a first terminal of the first driving transistor and a first terminal of the second driving transistor, the second scan signal is applied to a gate of the first driving transistor and a gate of the second driving transistor, a second terminal of the first driving transistor is connected to a first terminal of the third driving transistor, and a second terminal of the second driving transistor is connected to a gate of the third driving transistor. A first terminal of the first driving capacitor is connected to the gate of the third driving transistor, and a second terminal of the first driving capacitor is connected to the second terminal of the third driving transistor.

[0019] According to embodiments of the present disclosure, the pixel circuit further includes a switch module. The switch module, the light emitting control module and the light emitting element are connected in series between the power supply voltage and the ground voltage, and the driving module is connected to the light emitting control module via the switch module.

[0020] According to embodiments of the present disclosure, the switch module includes a switch transistor, and the gate of the third driving transistor is connected to a gate of the switch transistor.

[0021] According to the embodiment of the present disclosure, the driving module is connected with the first scan signal, the second scan signal and the third scan signal, and the driving module comprises a fourth driving transistor, a fifth driving transistor, a sixth driving transistor, a seventh driving transistor, an eighth driving transistor, a ninth driving transistor and a second driving capacitor. The fourth driving transistor is connected between the first node of the driving module and the ground voltage, and the second scan signal is applied to the gate of the fourth driving transistor. The fifth driving transistor is connected between the first node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the fifth driving transistor. The sixth driving transistor is connected between the second node of the driving module and the ground voltage, and the third scan signal is applied to the gate of the sixth driving transistor. The seventh driving transistor is connected between the first node of the driving module and the reference voltage, and the first scan signal is applied to the gate of the seventh driving transistor. The power supply voltage is applied to the first terminal of the eighth driving transistor, the gate of the eighth driving transistor is connected to the second node of the driving module, and the second terminal of the eighth driving transistor is connected to the second terminal of the ninth driving transistor. The first terminal of the ninth driving transistor is connected to the second node of the driving module, and the second scan signal is applied to the gate of the ninth driving transistor. The second driving capacitor is connected between the first node of the driving module and the second node of the driving module.

[0022] The embodiment of the present disclosure further provides a display substrate comprising the pixel circuit according to the embodiments of the present disclosure.

[0023] The embodiment of the present disclosure further provides a display device comprising the display substrate according to the embodiments of the present disclosure.

[0024] The embodiment of the present disclosure further provides an electronic device comprising the display device according to the embodiments of the present disclosure.

[0025] According to the pixel circuit of the present disclosure, 8bit Gamma2.2 luminance scheme can be realized by using fewer subframes, so that the refresh time of each subframe can be ensured to be sufficient for the writing of data signals of each row even for the application with more rows of screen. According to the PWM signal generation circuit of the present disclosure, the Sweep signal which can be applied to the pixel circuit according to the present disclosure can be generated, which is beneficial to realize the pixel circuit according to the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings are included to provide a further understanding of embodiments of the present disclosure and are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and are used to explain the present disclosure, but do not constitute a limitation on the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the specific embodiments described below, taken in conjunction with the accompanying drawings. Embodiments as described in the present disclosure are shown in the drawings by way of example and not limitation. In the drawings, like reference numerals indicate similar elements. Also, the drawings are not drawn to scale for the purpose of illustration.

[0027] FIG. 1 shows a PWM signal generation circuit according to an embodiment of the present disclosure;

[0028] FIG. 2 shows a timing diagram of the PWM signal generation circuit according to an embodiment of the present disclosure;

[0029] FIG. 3 shows a pixel circuit according to an embodiment of the present disclosure;

[0030] FIG. 4 shows another pixel circuit according to an embodiment of the present disclosure;

[0031] FIG. 5 shows a timing diagram of a light emission control module in the pixel circuit according to an embodiment of the present disclosure;

[0032] FIG. 6 shows a jump example of a Sweep signal used in the pixel circuit according to an embodiment of the present disclosure;

[0033] FIG. 7 shows a timing diagram of three subframe combinations in the pixel circuit according to an embodiment of the present disclosure;

[0034] FIGS. 8A to 8C show timing diagrams of a driving module in the pixel circuit according to an embodiment of the present disclosure;

[0035] FIG. 9 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure;

[0036] FIG. 10 shows a schematic block diagram of a display device according to an embodiment of the present disclosure; and

[0037] FIG. 11 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0038] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the PWM signal generation circuit, the pixel circuit, the display substrate, the display device and the electronic device provided by the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0039] Example embodiments will be described more fully hereinafter with reference to the accompanying drawings; however, these embodiments can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the disclosure to those skilled in the art.

[0040] The embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0041] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0042] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0044] FIG. 1 shows a PWM signal generation circuit according to an embodiment of the present disclosure.

[0045] As shown in FIG. 1, the PWM signal generation circuit according to an embodiment of the present disclosure includes a first signal transfer circuit and a second signal transfer circuit. The first signal transfer circuit includes a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module; and the second signal transfer circuit includes a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module.

[0046] The first output end of the first signal transfer circuit is connected to the second output end of the second signal transfer circuit, and serves as an output end of the PWM signal generation circuit.

[0047] As shown in FIG. 1, the first high level VGH1 for generating the first output signal EA(n) of the first signal transfer circuit is different from the second high level VGH2 for generating the second output signal EB(n) of the second signal transfer circuit, so the output signal Sweep(n) of the PWM signal generation circuit has a step between the first high level VGH1 and the second high level VGH2 (see the Sweep(n) signal shown in FIG. 2). How to generate the output signal Sweep(n) will be explained in detail later with reference to FIG. 2.

[0048] As shown in FIG. 1, the first input module, the first forward voltage generation module, the first reverse voltage generation module and the first signal generation module are connected to the first node N1 of the first signal transfer circuit; the first forward voltage generation module and the first reverse voltage generation module are connected to the first control node CN1 of the first signal transfer circuit; the first reverse voltage generation module and the first signal generation module are connected to the second node N2 of the first signal transfer circuit; the first signal generation module and the first output enable module are connected to the first output node ON1 of the first signal transfer circuit. The second input module, the second forward voltage generation module, the second reverse voltage generation module and the second signal generation module are connected to the third node N3 of the second signal transfer circuit; the second forward voltage generation module and the second reverse voltage generation module are connected to the second control node CN2 of the second signal transfer circuit; the second reverse voltage generation module and the second signal generation module are connected to the fourth node N4 of the second signal transfer circuit; the second signal generation module and the second output enable module are connected to the second output node ON2 of the second signal transfer circuit.

[0049] The first signal transfer circuit and the second signal transfer circuit are respectively connected with the first clock signal ECK1 and the second clock signal ECK2. The first clock signal ECK1 and the second clock signal ECK2 are periodic signals, have the same waveform, and have a duty cycle of 20%-40% (see FIG. 2). It should be recognized that the "same waveform" described herein includes reasonable errors within the allowable range, that is, it is substantially the same waveform, which can achieve the required function, and it is not necessarily a completely identical waveform.

[0050] As shown in FIG. 1, the first input module includes a first input transistor IN_T1, and the second input module includes a second input transistor IN_T2.

[0051] The first end of the first input transistor IN_T1 is as a first input end of the first signal transfer circuit, and a first input signal EA(n-1) is applied to the first end of the first input transistor IN_T1. The second end of the first input transistor IN_T1 is connected to the first node N1, and a second clock signal ECK2 is applied to the gate of the first input transistor IN_T1. The first end of the second input transistor IN_T2 is as a second input end of the second signal transfer circuit, and a second input signal EB(n-1) is applied to the first end of the second input transistor IN_T2. The second end of the second input transistor IN_T2 is connected to the third node N3, and a first clock signal ECK1 is applied to the gate of the second input transistor IN_T2.

[0052] As shown in FIG. 1, the first forward voltage generation module includes a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4, and the second forward voltage generation module includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and an eighth transistor T8.

[0053] A high level VGH is applied to the first end of the first transistor T1, the gate of the first transistor T1 is connected to a first control node CN1, and the second end of the first transistor T1 is connected to the first end of the second transistor T2. The second end of the second transistor T2 is connected to the first node N1, and a first clock signal ECK1 is applied to the gate of the second transistor T2. A second clock signal ECK2 is applied to the first end of the third transistor T3 and the gate of the fourth transistor T4, the gate of the third transistor T3 is connected to the first node N1, the second end of the third transistor T3 and the second end of the fourth transistor T4 are connected to the first control node CN1, and the first end of the fourth transistor T4 is connected to a low level VGL.

[0054] A high level VGH is applied to the first end of the fifth transistor T5, the gate of the fifth transistor T5 is connected to a second control node CN2, and the second end of the fifth transistor T5 is connected to the first end of the sixth transistor T6. The second end of the sixth transistor T2 is connected to the third node N3, and a second clock signal ECK2 is applied to the gate of the sixth transistor T6. A first clock signal ECK1 is applied to the first end of the seventh transistor T7 and the gate of the eighth transistor T8, the gate of the seventh transistor T7 is connected to the third node N3, the second end of the seventh transistor T7 and the second end of the eighth transistor T8 are connected to the second control node CN2, and the first end of the eighth transistor T8 is connected to a low level VGL.

[0055] As shown in FIG. 1, the first reverse voltage generation module includes a ninth transistor T9, a tenth transistor T10, and an eleventh transistor T11, and the second reverse voltage generation module includes a twelfth transistor T12, a thirteenth transistor T13, and a fourteenth transistor T14.

[0056] A high level VGH is applied to a first terminal of the ninth transistor T9, a gate of the ninth transistor T9 is connected to the first node N1, and a second terminal of the ninth transistor T9 is connected to the second node N2. A first terminal of the tenth transistor T10 is connected to a second terminal of the eleventh transistor T11 and to the first control node CN1 via the first capacitor C1. A gate of the tenth transistor T10 and a first terminal of the eleventh transistor T11 are applied with the first clock signal ECK1, a second terminal of the tenth transistor T10 is connected to the second node N2, and a gate of the eleventh transistor T11 is connected to the first control node CN1.

[0057] A high level VGH is applied to a first terminal of the twelfth transistor T12, a gate of the twelfth transistor T12 is connected to the third node N3, and a second terminal of the twelfth transistor T12 is connected to the fourth node N4. A first terminal of the thirteenth transistor T13 is connected to a second terminal of the fourteenth transistor T14 and to the second control node CN2 via the second capacitor C2. A gate of the thirteenth transistor T13 and a first terminal of the fourteenth transistor T14 are applied with the second clock signal ECK2, a second terminal of the thirteenth transistor T13 is connected to the fourth node N4, and a gate of the fourteenth transistor T14 is connected to the second control node CN2.

[0058] As shown in FIG. 1, the first signal generation module includes a fifteenth transistor T15 and a sixteenth transistor T16, and the second signal generation module includes a seventeenth transistor T17 and an eighteenth transistor T18.

[0059] A first high level VGH1 is applied to a first terminal of the fifteenth transistor T15, a gate of the fifteenth transistor T15 is connected to the second node N2, and the first terminal of the fifteenth transistor T15 is connected to the first output node ON1 via a third capacitor C3. A first terminal of the sixteenth transistor T16 is connected to a low level VGL, a gate of the sixteenth transistor T16 is connected to the first node N1, and a second terminal of the sixteenth transistor T16 is connected to the first output node ON1.

[0060] A second high level VGH2 is applied to a first terminal of a seventeenth transistor T17, a gate of the seventeenth transistor T17 is connected to the fourth node N4, and is connected to the first terminal of the seventeenth transistor T17 via a fourth capacitor C4, a second terminal of the seventeenth transistor T17 is connected to the second output node ON2. A first terminal of an eighteenth transistor T18 is connected to the low level VGL, a gate of the eighteenth transistor T18 is connected to the third node N3, and a second terminal of the eighteenth transistor T18 is connected to the second output node ON2.

[0061] As shown in FIG. 1, the first signal generation module further includes a fifth capacitor C5 and a nineteenth transistor T19, and the second signal generation module further includes a sixth capacitor C6 and a twentieth transistor T20.

[0062] A first clock signal ECK1 is applied to a first terminal of the fifth capacitor C5, and a second terminal of the fifth capacitor C5 is connected to a gate of the sixteenth transistor T16. A second clock signal ECK2 is applied to a second terminal of the sixth capacitor C6, and a second terminal of the sixth capacitor C6 is connected to a gate of the eighteenth transistor T18. The gate of the sixteenth transistor T16 is connected to the first node N1 via the nineteenth transistor T19, and the gate of the eighteenth transistor T18 is connected to the third node N3 via the twentieth transistor T20.

[0063] As shown in FIG. 1, the first output enable module includes a first output transistor OUT T1, and the second output enable module includes a second output transistor OUT T2. The first output transistor OUT T1 is connected between the first output node ON1 and a first output end of the first signal transfer circuit, and the second output transistor OUT T2 is connected between the second output node OUT T2 and a second output end of the second signal transfer circuit.

[0064] The first output signal EA(n) is output to the first output end of the first signal transfer circuit via the first output transistor OUT T1, and the second output signal EB(n) is output to the second output end of the second signal transfer circuit via the second output transistor OUT T2. The first output signal EA(n) is also output to the gate of the second output transistor OUT T2 as an output enable signal of the second signal transfer circuit, and the second output signal EB(n) is also output to the gate of the first output transistor OUT T1 as an output enable signal of the first signal transfer circuit.

[0065] It should be recognized that the high level VGH shown in FIG. 1 can be the same level or different levels as the first high level VGH1 or the second high level VGH2.

[0066] The high level VGH shown in FIG. 1 is used to set the first node N1, the second node N2, the third node N3 and the fourth node N4, so that the transistors connected with the first node N1, the second node N2, the third node N3 and the fourth node N4 are turned off, and therefore, the high level VGH can be implemented as the off voltage of the transistors.

[0067] On the other hand, the first high level VGH1 and the second high level VGH2 shown in FIG. 1 are respectively used to generate the high levels in which the first output signal EA(n) and the second output signal EB(n) are located, and further generate the output signal Sweep(n) having a step between the first high level VGH1 and the second high level VGH2. Therefore, the first high level VGH1 and the second high level VGH2 are different from each other. For example, the second high level VGH2 can be twice the first high level VGH1.

[0068] The PWM signal generation circuit shown in FIG. 1 is applied to the driving of a display substrate having multiple rows of pixel circuits. In each row of pixel circuits, the first row to be driven is referred to as a “start row” or a “start stage”. For the start row (or start stage), a start input signal is input. In the same stage, the output signal has the same waveform as the input signal and has a fixed phase difference. Between subsequent stages, the output signal (e.g., the first output signal and the second output signal) of the previous stage is used as the input signal (e.g., the first input signal and the second input signal) of the next stage, so that the initial start input signal is transmitted between stages with a fixed phase difference.

[0069] In the following, how to obtain the output signal Sweep(n) having different first duration at the first high level and second duration at the second high level by the PWM signal generation circuit of the embodiments of the present disclosure will be explained in detail with reference to FIG. 2.

[0070] FIG. 2 shows a timing diagram of the PWM signal generation circuit according to the embodiments of the present disclosure.

[0071] Referring to FIGS. 1 and 2, during the time period P1, the first clock signal ECK1 and the second clock signal ECK2 are both at the high level, the first input signal EA(n-1) is at the high level, and the second input signal EB(n-1) is at the low level.

[0072] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is at a low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0073] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is at a low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0074] The first output transistor OUT_T1 and the second output transistor OUT_T2 are both turned on, and the output signal Sweep(n) is at a low level.

[0075] During the time period P2, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0076] In the first signal transfer circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the high level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at the high level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at the low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at the high level, and the fifteenth transistor T15 is turned off; the first output node ON1 is maintained at the low level, and the first output signal EA(n) is at the low level.

[0077] In the second signal transfer circuit: the second input transistor IN_T2 is turned off, the sixth transistor T6 is turned on, the eighth transistor T8 is turned off, and the thirteenth transistor T13 is turned on; the third node N3 is maintained at the low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at the high level, and the fifth transistor T5 and the fourteenth transistor T14 are turned off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at the high level, and the seventeenth transistor T17 is turned off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at the low level, and the second output signal EB(n) is at the low level.

[0078] The first output transistor OUT_T1 and the second output transistor OUT_T2 are both turned on, and the output signal Sweep(n) is at the low level.

[0079] During the time period P3, the first clock signal ECK1 and the second clock signal ECK2 are both at the high level, the first input signal EA(n-1) is at the high level, and the second input signal EB(n-1) is at the low level.

[0080] In the first signal transfer circuit: the first input transistor IN_T1 is turned off, the second transistor T2 is turned off, the fourth transistor T4 is turned off, and the tenth transistor T10 is turned off; the first node N1 is maintained at the high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the first control node CN1 is maintained at the low level, the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at the high level, and the fifteenth transistor T15 is turned off; the first output node ON1 is maintained at the low level, and the first output signal EA(n) is at the low level.

[0081] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0082] The first output transistor OUT_T1 and the second output transistor OUT_T2 are both turned on, and the output signal Sweep(n) is at a low level.

[0083] During the time period P4, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0084] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is turned on, the fourth transistor T4 is off, and the tenth transistor T10 is turned on; the first control node CN1 is maintained at a low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the first node N1 through the first transistor T1 and the second transistor T2, the first node N1 is at a high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the low level of the first clock signal ECK1 is applied to the second node N2 through the eleventh transistor T11 and the tenth transistor T10, the second node N2 is at a low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0085] In the second signal transfer circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the low level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a low level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the low level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is turned off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0086] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0087] During the time period P5, the first clock signal ECK1 and the second clock signal ECK2 are both at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0088] In the first signal transfer circuit: the first input transistor IN_T1 is turned off, the second transistor T2 is turned off, the fourth transistor T4 is turned off, and the tenth transistor T10 is turned off; the first node N1 is maintained at a high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the first control node CN1 is maintained at a low level, the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0089] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0090] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0091] During the time period P6, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0092] In the first signal transfer circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is off, the fourth transistor T4 is turned on, and the tenth transistor T10 is off; the high level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0093] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is on, the eighth transistor T8 is off, and the thirteenth transistor T13 is on; the third node N3 is maintained at a low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at a high level, and the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0094] The first output transistor OUT_T1 is on, the second output transistor OUT_T2 is off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0095] During the time period P7, the first clock signal ECK1 and the second clock signal ECK2 are both at a high level, the first input signal EA(n-1) is at a high level, and the second input signal EB(n-1) is at a low level.

[0096] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are off; the first control node CN1 is maintained at a low level, the first transistor T1 and the eleventh transistor T11 are on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0097] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, the thirteenth transistor T13 is off; the third node N3 is maintained at low level, the seventh transistor T7, the twelfth transistor T12 and the eighteenth transistor T18 are turned on; the high level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the second control node CN2 is at high level, the fifth transistor T5 and the fourteenth transistor T14 are off; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at high level, the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at low level, the second output signal EB(n) is at low level.

[0098] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0099] During the time period P8, the first clock signal ECK1 is at low level, the second clock signal ECK2 is at high level, the first input signal EA(n-1) is at low level, and the second input signal EB(n-1) is at high level.

[0100] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is turned on, the fourth transistor T4 is off, and the tenth transistor T10 is turned on; the first control node CN1 is maintained at low level, the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the first node N1 through the first transistor T1 and the second transistor T2, the first node N1 is at high level, the third transistor T3, the ninth transistor T9 and the sixteenth transistor T16 are off; the low level of the first clock signal ECK1 is applied to the second node N2 through the eleventh transistor T11 and the tenth transistor T10, the second node N2 is at low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0101] In the second signal transfer circuit: the second input transistor IN_T2 is turned on, the sixth transistor T6 is turned off, the eighth transistor T8 is turned on, and the thirteenth transistor T13 is turned off; the high level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a high level, and the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, and the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at a high level, and the seventeenth transistor T17 is turned off; the second output node ON2 is maintained at a low level, and the second output signal EB(n) is at a low level.

[0102] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0103] During the time period P9, the first clock signal ECK1 and the second clock signal ECK2 are both at a high level, the first input signal EA(n-1) is at a low level, and the second input signal EB(n-1) is at a high level.

[0104] In the first signal transfer circuit: the first input transistor IN_T1 is turned off, the second transistor T2 is turned off, the fourth transistor T4 is turned off, and the tenth transistor T10 is turned off; the first node N1 is maintained at a high level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned off; the first control node CN1 is maintained at a low level, the first transistor T1 and the eleventh transistor T11 are turned on; the second node N2 is maintained at a low level, and the fifteenth transistor T15 is turned on; the first high level VGH1 is applied to the first output node ON1 through the fifteenth transistor T15, the first output node ON1 is at the first high level VGH1, and the first output signal EA(n) is at the first high level VGH1.

[0105] In the second signal transfer circuit: the second input transistor IN_T2 is turned off, the sixth transistor T6 is turned off, the eighth transistor T8 is turned off, and the thirteenth transistor T13 is turned off; the third node N3 is maintained at a high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the second control node CN2 is maintained at a low level, the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at a high level, and the seventeenth transistor T17 is turned off; the second output node ON2 is maintained at a low level, and the second output signal EB(n) is at a low level.

[0106] The first output transistor OUT_T1 is turned on, the second output transistor OUT_T2 is turned off, and the output signal Sweep(n) is at the first high level VGH1 of the first output signal EA(n).

[0107] During the time period P10, the first clock signal ECK1 is at the high level, the second clock signal ECK2 is at the low level, the first input signal EA(n-1) is at the low level, and the second input signal EB(n-1) is at the high level.

[0108] In the first signal transfer circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the low level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at the low level, and the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the low level of the second clock signal ECK2 is applied to the first control node CN1 through the T3 transistor, the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at the low level, and the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at the high level, and the fifteenth transistor T15 is turned off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at the low level, and the first output signal EA(n) is at the low level.

[0109] In the second signal transfer circuit: the second input transistor IN_T2 is turned off, the sixth transistor T6 is turned on, the eighth transistor T8 is turned off, and the thirteenth transistor T13 is turned on; the second control node CN2 is maintained at the low level, the fifth transistor T5 and the fourteenth transistor T14 are turned on; the high level is applied to the third node N3 through the fifth transistor T5 and the sixth transistor T6, the third node N3 is at the high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the low level of the second clock signal ECK2 is applied to the fourth node N4 through the fourteenth transistor T14 and the thirteenth transistor T13, the fourth node N4 is at the low level, and the seventeenth transistor T17 is turned on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0110] The first output transistor OUT_T1 is turned off, the second output transistor OUT_T2 is turned on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0111] During the time period P11, the first clock signal ECK1 and the second clock signal ECK2 are both at high level, the first input signal EA(n-1) is at low level, and the second input signal EB(n-1) is at high level.

[0112] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at low level, and the first output signal EA(n) is at low level.

[0113] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the second control node CN2 is maintained at low level, the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at low level, and the seventeenth transistor T17 is turned on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0114] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is turned on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0115] During the time period P12, the first clock signal ECK1 is at low level, the second clock signal ECK2 is at high level, the first input signal EA(n-1) is at low level, and the second input signal EB(n-1) is at high level.

[0116] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first node N1 is maintained at a low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0117] In the second signal transfer circuit: the second input transistor IN_T2 is on, the sixth transistor T6 is off, the eighth transistor T8 is on, and the thirteenth transistor T13 is off; the high level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the low level is applied to the second control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, the fifth transistor T5 and the fourteenth transistor T14 are on; the fourth node N4 is maintained at a low level, and the seventeenth transistor T17 is on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0118] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0119] During the time periods P13, P15, and P17, the states of the circuit are the same as those during the time period P11; during the time periods P14 and P16, the states of the circuit are the same as those during the time period P12, which will not be described herein again.

[0120] During the time period P18, the first clock signal ECK1 is at a high level, the second clock signal ECK2 is at a low level, the first input signal EA(n-1) and the second input signal EB(n-1) are both at a low level.

[0121] In the first signal transfer circuit: the first input transistor IN_T1 is turned on, the second transistor T2 is turned off, the fourth transistor T4 is turned on, and the tenth transistor T10 is turned off; the low level of the first input signal EA(n-1) is applied to the first node N1 through the first input transistor IN_T1, the first node N1 is at a low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the low level of the second clock signal ECK2 is applied to the first control node CN1 through the T3 transistor, the low level is applied to the first control node CN1 through the fourth transistor T4, the first control node CN1 is at a low level, the first transistor T1 and the eleventh transistor T11 are turned on; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is turned off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0122] In the second signal transfer circuit: the second input transistor IN_T2 is turned off, the sixth transistor T6 is turned on, the eighth transistor T8 is turned off, and the thirteenth transistor T13 is turned on; the second control node CN2 is maintained at a low level, the fifth transistor T5 and the fourteenth transistor T14 are turned on; the high level is applied to the third node N3 through the fifth transistor T5 and the sixth transistor T6, the third node N3 is at a high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are turned off; the low level of the second clock signal ECK2 is applied to the fourth node N4 through the fourteenth transistor T14 and the thirteenth transistor T13, the fourth node N4 is at a low level, and the seventeenth transistor T17 is turned on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0123] The first output transistor OUT_T1 is turned off, the second output transistor OUT_T2 is turned on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0124] During the time period P19, the first clock signal ECK1 and the second clock signal ECK2 are both at a high level, the first input signal EA(n-1) and the second input signal EB(n-1) are both at a low level.

[0125] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is off, the fourth transistor T4 is off, and the tenth transistor T10 is off; the first node N1 is maintained at a low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are turned on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0126] In the second signal transfer circuit: the second input transistor IN_T2 is off, the sixth transistor T6 is off, the eighth transistor T8 is off, and the thirteenth transistor T13 is off; the third node N3 is maintained at a high level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are off; the second control node CN2 is maintained at a low level, the fifth transistor T5 and the fourteenth transistor T14 are turned on; the fourth node N4 is maintained at a low level, and the seventeenth transistor T17 is turned on; the second high level VGH2 is applied to the second output node ON2 through the seventeenth transistor T17, the second output node ON2 is at the second high level VGH2, and the second output signal EB(n) is at the second high level VGH2.

[0127] The first output transistor OUT_T1 is off, the second output transistor OUT_T2 is turned on, and the output signal Sweep(n) is at the second high level VGH2 of the second output signal EB(n).

[0128] During the time period P20, the first clock signal ECK1 is at a low level, the second clock signal ECK2 is at a high level, the first input signal EA(n-1) and the second input signal EB(n-1) are both at a low level.

[0129] In the first signal transfer circuit: the first input transistor IN_T1 is off, the second transistor T2 is on, the fourth transistor T4 is off, and the tenth transistor T10 is on; the first node N1 is maintained at a low level, the third transistor T3, the ninth transistor T9, and the sixteenth transistor T16 are on; the high level of the second clock signal ECK2 is applied to the first control node CN1 through the third transistor T3, the first control node CN1 is at a high level, and the first transistor T1 and the eleventh transistor T11 are off; the high level is applied to the second node N2 through the ninth transistor T9, the second node N2 is at a high level, and the fifteenth transistor T15 is off; the low level is applied to the first output node ON1 through the sixteenth transistor T16, the first output node ON1 is at a low level, and the first output signal EA(n) is at a low level.

[0130] In the second signal transfer circuit: the second input transistor IN_T2 is on, the sixth transistor T6 is off, the eighth transistor T8 is on, and the thirteenth transistor T13 is off; the low level of the second input signal EB(n-1) is applied to the third node N3 through the second input transistor IN_T2, the third node N3 is at a low level, the seventh transistor T7, the twelfth transistor T12, and the eighteenth transistor T18 are on; the low level of the first clock signal ECK1 is applied to the second control node CN2 through the seventh transistor T7, the low level is applied to the control node CN2 through the eighth transistor T8, the second control node CN2 is at a low level, the fifth transistor T5 and the fourteenth transistor T14 are on; the high level is applied to the fourth node N4 through the twelfth transistor T12, the fourth node N4 is at a high level, and the seventeenth transistor T17 is off; the low level is applied to the second output node ON2 through the eighteenth transistor T18, the second output node ON2 is at a low level, and the second output signal EB(n) is at a low level.

[0131] The first output transistor OUT_T1 and the second output transistor OUT_T2 are both on, and the output signal Sweep(n) is at a low level.

[0132] It should be recognized that the time period P1 is a time period specific to the start stage and is not included when transferring between subsequent stages.

[0133] Furthermore, it is recognized that the high period of the first input signal EA(n-1) includes the time period P1, but it is recognized that the high period of the first input signal EA(n-1) will not include the time period P1 when passed between subsequent stages since the time period P1 is a time period unique to the start stage. For example, the first output signal EA(n) as an input signal to the next stage (i.e., stage n+1) will not include a time period corresponding to the time period P1. That is, for the start stage (i.e., n=1), the EA(n-1) (i.e., EA(0)) shown in FIG. 2 is provided as the first input signal to the start stage.

[0134] It is also recognized that the first input signal EA(0) and the second input signal EB(0) provided to the start stage (i.e., start input signals) are passed between subsequent stages without the time period P1 of the first input signal EA(0). In each stage, the phase difference between the first input signal EA(n-1) and the first output signal EA(n) is the same as the phase difference between the first clock signal ECK1 and the second clock signal ECK2 (not considering the time period P1 included by the first input signal EA(0) of the start stage), and the phase difference between the second input signal EB(n-1) and the second output signal EB(n) is the same as the phase difference between the first clock signal ECK1 and the second clock signal ECK2. Since the first clock signal ECK1 and the second clock signal ECK2 are periodic signals, have the same waveform, and have a duty cycle of 20% to 40%, the initial start input signals are passed between stages with a fixed phase difference.

[0135] It should also be appreciated that the first duration of the output signal Sweep(n) at the first high level VGH1 is the same as the duration of the first output signal EA(n) at the first high level VGH1, and the second duration of the output signal Sweep(n) at the second high level VGH2 is the same as the duration of the second output signal EB(n) at the second high level VGH2. In order to make the first duration of the output signal Sweep(n) at the first high level VGH1 and the second duration of the output signal Sweep(n) at the second high level VGH2 different, the duration of the first output signal EA(n) at the first high level VGH1 and the duration of the second output signal EB(n) at the second high level VGH2 should be different. Since the first input signal EA(n-1) has the same waveform and fixed phase difference with the first output signal EA(n), and the second input signal EB(n-1) has the same waveform and fixed phase difference with the second output signal EB(n), the duration of the first input signal EA(n-1) at the first high level VGH1 and the duration of the second input signal EB(n-1) at the second high level VGH2 should be different. It can be inferred that the start input signals EA(0) and EB(0) should each have different high level time periods.

[0136] For example, referring to FIG. 1 and FIG. 2, the low level portions of the first clock signal ECK1 and the second clock signal ECK2 can make the transistors connected thereto conduct (e.g., the second transistor T2 and the fourth transistor T4), thus the low level portions (e.g., time periods P2 and P4) of the first clock signal ECK1 and the second clock signal ECK2 shown in FIG. 2 are called "enabling portions". The high level time period of the first input signal EA(n-1) covers a total of three enabling portions (time periods P2, P4 and P6) of the first clock signal ECK1 and the second clock signal ECK2, and the high level time period of the second input signal EB(n-1) covers a total of five enabling portions (time periods P8, P10, P12, P14 and P16) of the first clock signal ECK1 and the second clock signal ECK2.

[0137] The first duration of the output signal Sweep(n) at the first high level VGH1 and the second duration of the output signal Sweep(n) at the second high level VGH2 can be made different by adjusting the high level time periods of the start input signals EA(0) and EB(0) to cover different numbers of enabling portions of the first clock signal ECK1 and the second clock signal ECK2, respectively. In addition, a plurality of output signals Sweep each having different first durations (at the first high level VGH1) and different second durations (at the second high level VGH2) can also be achieved.

[0138] According to the PWM signal generation circuit of the present disclosure, a Sweep signal capable of being applied to the pixel circuit of the present disclosure can be generated. By combining different Sweep signals, the pixel circuit of the present disclosure is facilitated to be implemented.

[0139] The inventors of the present application have noticed that, when implementing the driving display of the LED using the PWM driving mode, if the 8bit Gamma 2.2 luminance scheme is to be implemented, at least 10 to 12 subframes are required. Assuming that 12 subframes are adopted, the refresh time of each subframe is: (1 / 60Hz) / 12=1.4ms. For the application with a small number of display screen rows (for example, wearable devices such as smart watches), the number of rows of the display screen thereof is usually between 480 and 600, and the writing time of each row of data signal is: 1.4ms / 600=2.3μs, which basically meets the requirement of the data writing time. However, for the application with a large number of display screen rows (for example, mobile phones or televisions, etc.), the number of rows of the display screen thereof is usually around 2000 to 4000, and the writing time of each row of data signal is less than 1μs, so the data writing time is seriously insufficient.

[0140] In order to solve such problems, the present disclosure proposes a pixel circuit capable of implementing the 8bit Gamma 2.2 luminance scheme by using fewer subframes (for example, 3 subframes), so as to ensure that the refresh time of each subframe is sufficient for the writing of each row of data signal even for the application with a large number of display screen rows.

[0141] Specifically, in the technical solution of the present disclosure, the Gate driver On Array (GOA) can include 2N rows (N is the number of rows of the display screen), and two rows of driving circuits correspond to one row of pixel circuits. That is, two different Sweep signals are respectively generated by using two PWM signal generation circuits of the present disclosure, and then the two different Sweep signals are applied to one row of pixel circuits, so that 9 different light-emitting durations can be implemented for each subframe. The 9 light-emitting durations of the three subframes are different from each other, so that the writing of 9x9x9=729 gray scales can be implemented by using the three subframes, so as to implement the 8bit Gamma 2.2 luminance scheme. The pixel circuit according to the present disclosure will be described in detail below with reference to FIG. 3 and FIG. 4.

[0142] FIG. 3 shows a pixel circuit according to an embodiment of the present disclosure, and FIG. 4 shows another pixel circuit according to an embodiment of the present disclosure.

[0143] Referring to FIGS. 3 and 4, the pixel circuit according to the embodiments of the present disclosure includes a driving module, a light emitting control module, and a light emitting element. The driving module is connected to the light emitting control module, and the light emitting control module and the light emitting element are connected in series between a power voltage ELVDD and a ground voltage VSS.

[0144] The light emitting control module includes a first light emitting control module and a second light emitting control module connected to each other. The first light emitting control module is accessed with a first data signal and a first Sweep signal Sweep1(n), the second light emitting control module is accessed with a second data signal and a second Sweep signal Sweep2(n), and the first light emitting control module and the second light emitting control module are accessed with a first scan signal Scan(n). The first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n) are different, and the first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n) are respectively generated by the PWM signal generation circuit according to the embodiments of the present disclosure.

[0145] As shown in FIGS. 3 and 4, the first light emitting control module includes a first control transistor CT1, a second control transistor CT2, and a first control capacitor CC1, and the second light emitting control module includes a third control transistor CT3, a fourth control transistor CT4, and a second control capacitor CC2.

[0146] The first Sweep signal Sweep1(n) is applied to a first terminal of the first control capacitor CC1, and a second terminal of the first control capacitor CC1 is connected to a gate of the first control transistor CT1. A first data signal Data1 is applied to a first terminal of the second control transistor CT2, a first scan signal Scan(n) is applied to a gate of the second control transistor CT2, and a second terminal of the second control transistor CT2 is connected to the gate of the first control transistor CT1.

[0147] The second Sweep signal Sweep2(n) is applied to a first terminal of the second control capacitor CC2, and a second terminal of the second control capacitor CC2 is connected to a gate of the third control transistor CT3. A second data signal Data2 is applied to a first terminal of the fourth control transistor CT4, the first scan signal Scan(n) is applied to a gate of the fourth control transistor CT4, and a second terminal of the fourth control transistor CT4 is connected to the gate of the third control transistor CT3.

[0148] A first terminal of the first control transistor CT1 is connected to a first terminal of the third control transistor CT3, and a second terminal of the first control transistor CT1 is connected to a second terminal of the third control transistor CT3.

[0149] The operation timing of the light emitting control module in the pixel circuit according to the embodiments of the present disclosure is described below with reference to FIG. 5.

[0150] FIG. 5 shows a timing diagram of the light emitting control module in the pixel circuit according to the embodiments of the present disclosure.

[0151] Referring to FIGS. 3-5, during the time period CP1, the A-point position and the B-point position are the last frame data values, and the first control transistor CT1 and the third control transistor CT3 are turned off.

[0152] During the time period CP2, the first scan signal Scan(n) is at a high level, the second control transistor CT2 and the fourth control transistor CT4 are turned on, and the values data1 corresponding to the first data signal Data1 and data2 corresponding to the second data signal Data2 are written at the A-point position and the B-point position, respectively, i.e., the potential at the A-point is data1, and the potential at the B-point is data2.

[0153] The Sweep signal (i.e., the first Sweep signal Sweep1(n) and the second Sweep signal Sweep2(n)) used in the present embodiment is a signal generated by the PWM signal generation circuit according to the embodiments of the present disclosure, and such Sweep signal has a step between the first high level VGH1 and the second high level VGH2. That is, the Sweep signal used in the present embodiment has two jumps, the first jump is from the low level VGL to the first high level VGH1, and the second jump is from the first high level VGH1 to the second high level VGH2.

[0154] During the time period CP3, the first Sweep signal Sweep1(n) jumps from the low level VGL to the first high level VGH1; during the time period CP4, the first Sweep signal Sweep1(n) jumps from the first high level VGH1 to the second high level VGH2; during the time period CP5, the second Sweep signal Sweep2(n) jumps from the low level VGL to the first high level VGH1; and during the time period CP6, the second Sweep signal Sweep2(n) jumps from the first high level VGH1 to the second high level VGH2.

[0155] Referring to FIG. 6, it is assumed that the amplitude of each jump is ΔV, i.e., the first high level VGH1 = ΔV, and the second high level VGH2 = 2ΔV. Accordingly, during the time period CP3, the potential at the A-point is data1 + ΔV; during the time period CP4, the potential at the A-point is data1 + 2ΔV; during the time period CP5, the potential at the B-point is data2 + ΔV; and during the time period CP6, the potential at the B-point is data2 + 2ΔV.

[0156] Thus, the following three cases can occur:

[0157] Case 1 : The written value data1 is a negative value, i.e., -V, and -V+ΔV is greater than the turn-on voltage of the first control transistor CT1, thus the light emitting element emits light in both time periods shown by E0 and E1;

[0158] Case 2: -V+ΔV is less than the turn-on voltage of the first control transistor CT1, and -V+2ΔV is greater than the turn-on voltage of the first control transistor CT1, thus the light emitting element does not emit light in the time period shown by E0, and emits light in the time period shown by E1;

[0159] Case 3: -V+ΔV and -V+2ΔV are both less than the turn-on voltage of the first control transistor CT1, thus the light emitting element does not emit light in both time periods shown by E0 and E1.

[0160] Similarly to the value data1, the writing of the value data2 can also have the above three cases, and based on the combination of respective cases, the following nine different light emitting durations can be formed:

[0161] No light emission; E1; E3; E0+E1; E2+E3; E1+E3; E1+E2+E3; E0+E1+E3; E0+E1+E2+E3.

[0162] It should be appreciated that the first Sweep signal Sweep1(n) is different in the first duration E0 at the first high voltage VGH1 and the second duration E1 at the second high voltage VGH2, and the second Sweep signal Sweep2(n) is different in the first duration E2 at the first high voltage VGH1 and the second duration E3 at the second high voltage VGH2, thus the above nine different light emitting durations can be obtained.

[0163] FIG. 7 shows a timing diagram of three subframe combinations.

[0164] As shown in FIG. 7, each subframe corresponds to four light emitting durations, the first subframe corresponds to E0, E1, E2 and E3; the second subframe corresponds to E4, E5, E6 and E7; the third subframe corresponds to E8, E9, E10 and E11. E0 to E11 are different from each other.

[0165] Based on the above analysis, each subframe contains 9 different light emitting durations, and through the combination of three subframes, 729 gray scales can be written, thus the 8bit Gamma2.2 luminance scheme is realized.

[0166] Referring back to FIG. 3, according to the embodiment of the present disclosure, the driving module of the pixel circuit is accessed with the second scan signal Scan(n-1), and the driving module includes a first driving transistor DT1, a second driving transistor DT2, a third driving transistor DT3, and a first driving capacitor DC1.

[0167] The driving current I Pixel The second scan signal Scan(n-1) is applied to the gate of the first driving transistor DT1 and the gate of the second driving transistor DT2, the second end of the first driving transistor DT1 is connected to the first end of the third driving transistor DT3, and the second end of the second driving transistor DT2 is connected to the gate of the third driving transistor DT3. The first end of the first driving capacitor DC1 is connected to the gate of the third driving transistor DT3, and the second end of the first driving capacitor DC1 is connected to the second end of the third driving transistor DT3.

[0168] As shown in FIG. 3, the pixel circuit according to the disclosed embodiment can further include a switching module. The switching module, the light-emitting control module, and the light-emitting element are connected in series between the power supply voltage ELVDD and the ground voltage Vss, and the driving module is connected to the light-emitting control module and the light-emitting element via the switching module.

[0169] As shown in FIG. 3, the switching module includes a switching transistor ST, and the gate of the third driving transistor DT3 is connected to the gate of the switching transistor ST.

[0170] Referring to the timing diagram of FIG. 5, during the time period CP1, the second scan signal Scan(n-1) is high, the first driving transistor DT1 and the second driving transistor DT2 are turned on, and the driving current I Pixel C is charged through the second driving transistor DT2. When the voltage across the first driving capacitor DC1 reaches a certain value, the driving current I Pixel flows through the third driving transistor DT3 through the first driving transistor DT1. Since the gate voltages of the third driving transistor DT3 and the switching transistor ST are equal, according to the current mirror principle, the current I LED The following calculation formula is satisfied:

[0171] wherein, μ is the field effect mobility, C OX is the capacitance per unit area of the insulating layer, W and L are the channel width and length of the MOS tube, respectively. Since the third driving transistor DT3 and the switching transistor ST can be transistors made of the same process, W is a constant.

[0172] In the driving pixel light-emitting stage, the switch transistor ST works in the saturation region, and the influence of the threshold voltage V th does not need to be considered. Therefore, the light-emitting driving current of all pixels is consistent, and there is no color deviation.

[0173] Referring back to FIG. 4, according to an embodiment of the present disclosure, the driving module of the pixel circuit can adopt constant current control. The current of the LED can control the brightness size of the full-screen LED light-emitting time, and is not affected by the IR drop.

[0174] As shown in FIG. 4, the driving module is connected with a first scan signal Scan(n), a second scan signal Scan(n-1) and a third scan signal Scan(n-2), and the driving module includes a fourth driving transistor DT4, a fifth driving transistor DT5, a sixth driving transistor DT6, a seventh driving transistor DT7, an eighth driving transistor DT8, a ninth driving transistor DT9 and a second driving capacitor DC2.

[0175] The fourth driving transistor DT4 is connected between the first node Node1 of the driving module and the ground voltage Vss, and the second scan signal Scan(n-1) is applied to the gate of the fourth driving transistor DT4.

[0176] The fifth driving transistor DT5 is connected between the first node Node1 of the driving module and the ground voltage Vss, and the third scan signal Scan(n-2) is applied to the gate of the fifth driving transistor DT5.

[0177] The sixth driving transistor DT6 is connected between the second node Node2 of the driving module and the ground voltage Vss, and the third scan signal Scan(n-2) is applied to the gate of the sixth driving transistor DT6.

[0178] The seventh driving transistor DT7 is connected between the first node Node1 of the driving module and the reference voltage Vref, and the first scan signal Scan(n) is applied to the gate of the seventh driving transistor DT7.

[0179] The power supply voltage ELVDD is applied to the first end of the eighth driving transistor DT8, the gate of the eighth driving transistor DT8 is connected to the second node Node2 of the driving module, and the second end of the eighth driving transistor DT8 is connected to the second end of the ninth driving transistor DT9.

[0180] The first end of the ninth driving transistor DT9 is connected to the second node Node2 of the driving module, and the second scan signal Scan(n-1) is applied to the gate of the ninth driving transistor DT9.

[0181] The second drive capacitor DC2 is connected between the first node Node1 of the drive module and the second node Node2 of the drive module.

[0182] In the circuit diagram shown in FIG. 4, the fourth drive transistor DT4 to the ninth drive transistor DT9 constitute a constant current control unit. When the LED emits light, since the current is constant, there is no color deviation problem. Adding this structure can reduce the threshold voltage V th of the switching transistor between pixels. In addition, as the driving current of the LED increases, the photoelectric efficiency will be in a state of rising.

[0183] The operation timing of the drive module (i.e., the constant current control unit) in this embodiment is described below with reference to FIGS. 8A to 8C.

[0184] FIGS. 8A to 8C show timing diagrams of the drive module in the pixel circuit according to an embodiment of the present disclosure.

[0185] As shown in FIG. 8A, during the time period DP1, the third scan signal Scan(n-2) is high, and the fifth drive transistor DT5 and the sixth drive transistor DT6 are turned on. The first scan signal Scan(n) and the second scan signal Scan(n-1) are low, and the fourth drive transistor DT4, the seventh drive transistor DT7, and the ninth drive transistor DT9 are turned off. The ground voltage Vss is applied to the first node Node1 and the second node Node2 through the fifth drive transistor DT5 and the sixth drive transistor DT6 to reset the first node Node1 and the second node Node2.

[0186] As shown in FIG. 8B, during the time period DP2, the second scan signal Scan(n-1) is high, and the fourth drive transistor DT4 and the ninth drive transistor DT9 are turned on. The first scan signal Scan(n) and the third scan signal Scan(n-2) are low, and the fifth drive transistor DT5, the sixth drive transistor DT6, and the seventh drive transistor DT7 are turned off. The power supply voltage ELVDD is applied to the second node Node2 through the eighth drive transistor DT8 and the ninth drive transistor DT9 to charge the second node Node2. When the potential of the second node Node2 is charged to ELVDD+V th , the eighth drive transistor DT8 is turned off, and V th is the threshold voltage of the eighth drive transistor DT8.

[0187] As shown in FIG. 8C, during the time period DP3, the first scan signal Scan(n) is at a high level, and the seventh drive transistor DT7 is turned on. The second scan signal Scan(n-1) and the third scan signal Scan(n-2) are at low levels, and the fourth drive transistor DT4, the fifth drive transistor DT5, the sixth drive transistor DT6 and the ninth drive transistor DT9 are turned off. The potential of the first node Node1 jumps from the ground voltage Vss to the reference voltage Vref. The potential of the second node Node2 jumps from the voltage ELVDD+V th to the voltage ELVDD+V th +Vref-Vss.

[0188] Table 1 lists the potentials of the first node Node1 and the second node Node2 during the time period DP1 to the time period DP3.

[0189] Table 1

[0190] The current passing through the eighth drive transistor DT8 is the source-drain current I ds , which is calculated by the following formula: I ds =k*(V gs -V th ) 2 =k*(ELVDD+V th +Vref-Vss-ELVDD-V th ) 2 =k*(Vref-Vss) 2

[0191] wherein V gs is the gate-source voltage of the eighth drive transistor DT8, V th is the threshold voltage of the eighth drive transistor DT8, and k is a constant related to the W / L capacitance mobility (W and L are the channel width and length of the MOS transistor, respectively) of the eighth drive transistor DT8.

[0192] As can be seen from the above formula, the current passing through the eighth drive transistor DT8 is the source-drain current I ds , which is only related to the reference voltage Vref and the ground voltage Vss, thereby realizing constant current control.

[0193] According to the pixel circuit of the embodiments of the present disclosure, the 8bit Gamma 2.2 luminance scheme can be realized by using fewer subframes, so that even for the application with a large number of rows of the screen, the refresh time of each subframe can be ensured to be sufficient for the writing of the data signals of each row. According to the driving module of the pixel circuit shown in FIG. 3, during the driving and light emitting stage of the pixel, the switching transistor ST works in the saturation region, and the threshold voltage V thTherefore, the light emitting driving current of all the pixels is consistent, and there is no color deviation. According to the driving module of the pixel circuit shown in FIG. 4, when the LED emits light, since the current is constant, there is no color deviation problem. Adding this structure can reduce the threshold voltage Vth of the switching transistor between pixels th Different bands bring different current problems. In addition, as the driving current of the LED increases, the photoelectric efficiency will be in a state of rising.

[0194] According to the PWM signal generation circuit of the present disclosure, a Sweep signal capable of being applied to the pixel circuit according to the present disclosure can be generated, which is beneficial to realize the pixel circuit according to the embodiments of the present disclosure.

[0195] FIG. 9 shows a schematic block diagram of a display substrate according to an embodiment of the present disclosure.

[0196] The display substrate according to the embodiments of the present disclosure can include the pixel circuit according to the embodiments of the present disclosure.

[0197] FIG. 10 shows a schematic block diagram of a display device according to an embodiment of the present disclosure.

[0198] The display device according to the embodiments of the present disclosure can include the display substrate according to the embodiments of the present disclosure.

[0199] FIG. 11 shows a schematic block diagram of an electronic device according to an embodiment of the present disclosure.

[0200] The electronic device according to the embodiments of the present disclosure can include the display device according to the embodiments of the present disclosure.

[0201] The display substrate, the display device and the electronic device according to the embodiments of the present disclosure all include the pixel circuit according to the embodiments of the present disclosure, so that the 8bit Gamma 2.2 brightness scheme can be realized with fewer subframes, and even for applications with a large number of rows of screens, the refresh time of each subframe can be ensured to be sufficient for the writing of the data signal of each row.

[0202] It should be appreciated that although specific types of transistors are shown in the various figures, for example, low-level on transistors and high-level on transistors, those skilled in the art should appreciate that the shown transistors can be replaced by other types of transistors as needed, and various corresponding control signals are applied according to the adjusted circuit. The present disclosure is intended to protect all these technical solutions.

[0203] In the present disclosure, the terms first, second, third, etc. can be used to describe various elements, and these elements should not be limited by these terms. These terms are only used to distinguish one element from another.

[0204] In the present disclosure, reference to a layer, region, or substrate being "on" or extending "onto" another element means that it can be directly on or extend directly onto the other element, or an intervening element can also be present. Further, when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element and / or connected or coupled to the other element via one or more intervening elements.

[0205] In the present disclosure, reference to "one embodiment", "certain embodiments", "one or more embodiments", or "an embodiment" means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the disclosure. The appearances of the phrases such as "in one or more embodiments", "in certain embodiments", "in one embodiment", or "in an embodiment" in various places in the specification are not necessarily referring to the same embodiment of the disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics can be combined in any suitable manner.

[0206] While the present disclosure has been described with reference to certain embodiments thereof, it is understood that variations and modifications will be obvious to those skilled in the art. It is the intention, therefore, to include variations and modifications in the scope of the present disclosure. It is also understood that the present disclosure is intended to cover all of the following claims, and any equivalents.

Claims

1. A pulse width modulation (PWM) signal generation circuit, comprising: a first signal transfer circuit; and a second signal transfer circuit, wherein a first output terminal of the first signal transfer circuit and a second output terminal of the second signal transfer circuit are connected, and serve as an output terminal of the PWM signal generation circuit, and wherein a first high level used for generating a first output signal of the first signal transfer circuit is different from a second high level used for generating a second output signal of the second signal transfer circuit, and an output signal of the PWM signal generation circuit has a step between the first high level and the second high level. 2.The PWM signal generation circuit of claim 1, wherein the first signal transfer circuit and the second signal transfer circuit are connected with a first clock signal and a second clock signal, the first clock signal and the second clock signal are periodic signals, have the same waveform, and have a duty cycle of 20%-40%. 3.The PWM signal generation circuit of claim 2, wherein the first signal transfer circuit comprises a first input module, a first forward voltage generation module, a first reverse voltage generation module, a first signal generation module, and a first output enable module, the first input module, the first forward voltage generation module, the first reverse voltage generation module, and the first signal generation module are connected to a first node of the first signal transfer circuit, the first forward voltage generation module and the first reverse voltage generation module are connected to a first control node of the first signal transfer circuit, the first reverse voltage generation module and the first signal generation module are connected to a second node of the first signal transfer circuit, the first signal generation module and the first output enable module are connected to a first output node of the first signal transfer circuit, the second signal transfer circuit comprises a second input module, a second forward voltage generation module, a second reverse voltage generation module, a second signal generation module, and a second output enable module, the second input module, the second forward voltage generation module, the second reverse voltage generation module, and the second signal generation module are connected to a third node of the second signal transfer circuit, the second forward voltage generation module and the second reverse voltage generation module are connected to a second control node of the second signal transfer circuit, the second reverse voltage generation module and the second signal generation module are connected to a fourth node of the second signal transfer circuit, the second signal generation module and the second output enable module are connected to a second output node of the second signal transfer circuit. 4.The PWM signal generation circuit of claim 3, wherein the first input module comprises a first input transistor, and the second input module comprises a second input transistor, ​ ​ a first end of the first input transistor is a first input end of the first signal transfer circuit, a first input signal is applied to the first end of the first input transistor, a second end of the first input transistor is connected to the first node, and the second clock signal is applied to a gate of the first input transistor, a first end of the second input transistor is a second input end of the second signal transfer circuit, a second input signal is applied to the first end of the second input transistor, a second end of the second input transistor is connected to the third node, and the first clock signal is applied to a gate of the second input transistor. 5.The PWM signal generation circuit of claim 4, wherein the first forward voltage generation module includes a first transistor, a second transistor, a third transistor, and a fourth transistor, and the second forward voltage generation module includes a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, a high level is applied to a first end of the first transistor, a gate of the first transistor is connected to the first control node, and a second end of the first transistor is connected to a first end of the second transistor, a second end of the second transistor is connected to the first node, and the first clock signal is applied to a gate of the second transistor, the second clock signal is applied to a first end of the third transistor and a gate of the fourth transistor, a gate of the third transistor is connected to the first node, a second end of the third transistor and a second end of the fourth transistor are connected to the first control node, and a first end of the fourth transistor is connected to a low level, a high level is applied to a first end of the fifth transistor, a gate of the fifth transistor is connected to the second control node, and a second end of the fifth transistor is connected to a first end of the sixth transistor, a second end of the sixth transistor is connected to the third node, and the second clock signal is applied to a gate of the sixth transistor, the first clock signal is applied to a first end of the seventh transistor and a gate of the eighth transistor, a gate of the seventh transistor is connected to the third node, a second end of the seventh transistor and a second end of the eighth transistor are connected to the second control node, and a first end of the eighth transistor is connected to a low level. 6.The PWM signal generation circuit of claim 5, wherein the first reverse voltage generation module includes a ninth transistor, a tenth transistor, and an eleventh transistor, and the second reverse voltage generation module includes a twelfth transistor, a thirteenth transistor, and a fourteenth transistor, a high level is applied to a first end of the ninth transistor, a gate of the ninth transistor is connected to the first node, and a second end of the ninth transistor is connected to the second node, a first end of the tenth transistor is connected to a second end of the eleventh transistor, and is connected to the first control node via a first capacitor, a second end of the twelfth transistor is connected to a second end of the thirteenth transistor, and is connected to the second control node via a second capacitor, and a high level is applied to a first end of the fourteenth transistor, a gate of the fourteenth transistor is connected to the third node, and a second end of the fourteenth transistor is connected to a low level. the first clock signal is applied to a gate of the tenth transistor and a first terminal of the eleventh transistor, a second terminal of the tenth transistor is connected to the second node, and a gate of the eleventh transistor is connected to the first control node, a high level is applied to the first terminal of the twelfth transistor, a gate of the twelfth transistor is connected to the third node, and a second terminal of the twelfth transistor is connected to the fourth node, a first terminal of the thirteenth transistor is connected to a second terminal of the fourteenth transistor and to the second control node via a second capacitor, the second clock signal is applied to a gate of the thirteenth transistor and a first terminal of the fourteenth transistor, a second terminal of the thirteenth transistor is connected to the fourth node, and a gate of the fourteenth transistor is connected to the second control node.

7. The PWM signal generation circuit according to claim 6, wherein the first signal generation module includes a fifteenth transistor and a sixteenth transistor, and the second signal generation module includes a seventeenth transistor and an eighteenth transistor, the first high level is applied to a first terminal of the fifteenth transistor, a gate of the fifteenth transistor is connected to the second node and to the tenth a first terminal of the fifteenth transistor, a second terminal of the fifteenth transistor is connected to the first output node, a first terminal of the sixteenth transistor is connected to a low level, a gate of the sixteenth transistor is connected to the first node, and a second terminal of the sixteenth transistor is connected to the first output node, the second high level is applied to a first terminal of the seventeenth transistor, a gate of the seventeenth transistor is connected to the fourth node and to the tenth a first terminal of the eighteenth transistor is connected to a low level, a gate of the eighteenth transistor is connected to the third node, and a second terminal of the eighteenth transistor is connected to the second output node.

8. The PWM signal generation circuit according to claim 7, wherein the first output enable module includes a first output transistor, the second output enable module includes a second output transistor, the first output transistor is connected between the first output node and the first output terminal, and the second output transistor is connected between the second output node and the second output terminal, the first output signal is output to the first output terminal via the first output transistor, and the second output signal is output to the second output terminal via the second output transistor, the first output signal is further output to a gate of the second output transistor as an output enable signal of the second signal transfer circuit, and the second output signal is further output to a gate of the first output transistor as an output enable signal of the first signal transfer circuit.

9. The PWM signal generation circuit according to claim 7, wherein The first signal generation module further includes a fifth capacitor and a nineteenth transistor, and the second signal generation module further includes a sixth capacitor and a twentieth transistor, The first clock signal is applied to a first end of the fifth capacitor, and a second end of the fifth capacitor is connected to a gate of the sixteenth transistor, The second clock signal is applied to a second end of the sixth capacitor, and a second end of the sixth capacitor is connected to a gate of the eighteenth transistor, The gate of the sixteenth transistor is connected to the first node via the nineteenth transistor, and the gate of the eighteenth transistor is connected to the third node via the twentieth transistor. The second high level is twice the first high level.

10. The PWM signal generation circuit of claim 1, wherein, The first duration of the first high level and the second duration of the second high level are different.

11. The PWM signal generation circuit of claim 1, wherein, 12. A pixel circuit, comprising: a driving module; a light emitting control module; and a light emitting element, wherein the driving module is connected to the light emitting control module, and the light emitting control module and the light emitting element are connected in series between a power supply voltage and a ground voltage, the light emitting control module includes a first light emitting control module and a second light emitting control module connected to each other, the first light emitting control module is accessed with a first data signal and a first Sweep signal, the second light emitting control module is accessed with a second data signal and a second Sweep signal, and the first light emitting control module and the second light emitting control module are accessed with a first scan signal, the first Sweep signal and the second Sweep signal are different, and the first Sweep signal and the second Sweep signal are generated by the PWM signal generation circuit of any one of claims 1 to 11.

13. The pixel circuit of claim 12, wherein the first light emitting control module includes a first control transistor, a second control transistor, and a first control capacitor, and the second light emitting control module includes a third control transistor, a fourth control transistor, and a second control capacitor, the first Sweep signal is applied to a first end of the first control capacitor, and a second end of the first control capacitor is connected to a gate of the first control transistor, the first data signal is applied to a first end of the second control transistor, the first scan signal is applied to a gate of the second control transistor, and a second end of the second control transistor is connected to the gate of the first control transistor, the second Sweep signal is applied to a first end of the second control capacitor, and a second end of the second control capacitor is connected to a gate of the third control transistor, the second data signal is applied to a first end of the fourth control transistor, the first scan signal is applied to a gate of the fourth control transistor, and a second end of the fourth control transistor is connected to the gate of the third control transistor, ​ A first end of the first control transistor is connected to a first end of the third control transistor, and a second end of the first control transistor is connected to a second end of the third control transistor.

14. The pixel circuit according to claim 13, wherein The drive module is connected to a second scan signal, and the drive module includes a first drive transistor, a second drive transistor, a third drive transistor, and a first drive capacitor, a drive current is applied to a first end of the first drive transistor and a first end of the second drive transistor, the second scan signal is applied to a gate of the first drive transistor and a gate of the second drive transistor, a second end of the first drive transistor is connected to a first end of the third drive transistor, and a second end of the second drive transistor is connected to a gate of the third drive transistor, a first end of the first drive capacitor is connected to the gate of the third drive transistor, and a second end of the first drive capacitor is connected to a second end of the third drive transistor.

15. The pixel circuit according to claim 14, further comprising a switch module, the switch module, the light emission control module, and the light emitting element are connected in series between the power supply voltage and the ground voltage, and the drive module is connected to the light emission control module via the switch module.

16. The pixel circuit according to claim 15, wherein the switch module includes a switch transistor, and the gate of the third drive transistor is connected to a gate of the switch transistor.

17. The pixel circuit according to claim 13, wherein the drive module is connected to the first scan signal, a second scan signal, and a third scan signal, and the drive module includes a fourth drive transistor, a fifth drive transistor, a sixth drive transistor, a seventh drive transistor, an eighth drive transistor, a ninth drive transistor, and a second drive capacitor, the fourth drive transistor is connected between a first node of the drive module and the ground voltage, and the second scan signal is applied to a gate of the fourth drive transistor, the fifth drive transistor is connected between the first node of the drive module and the ground voltage, and the third scan signal is applied to a gate of the fifth drive transistor, the sixth drive transistor is connected between a second node of the drive module and the ground voltage, and the third scan signal is applied to a gate of the sixth drive transistor, the seventh drive transistor is connected between the first node of the drive module and a reference voltage, and the first scan signal is applied to a gate of the seventh drive transistor, the power supply voltage is applied to a first end of the eighth drive transistor, a gate of the eighth drive transistor is connected to the second node of the drive module, and a second end of the eighth drive transistor is connected to a second end of the ninth drive transistor, a first end of the ninth drive transistor is connected to the second node of the drive module, and the second scan signal is applied to a gate of the ninth drive transistor, a first end of the eighth drive transistor is connected to the second node of the drive module, and the second scan signal is applied to a gate of the eighth drive transistor, The second drive capacitor is connected between the first node of the drive module and the second node of the drive module.

18. A display substrate, comprising the pixel circuit according to any one of claims 12 to 17.

19. A display device, comprising the display substrate according to claim 18.

20. An electronic device, comprising the display device according to claim 19.

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