Shift register unit, gate driving circuit and display device

Abstract

Provided is a shift register unit, comprising: an input circuit, an output circuit, a node potential control circuit, a discharge circuit and a reset circuit, wherein at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit comprises a threshold-voltage-adjustable transistor; and the threshold-voltage-adjustable transistor comprises a substrate, a gate electrode, a source / drain electrode and a bias electrode, the source / drain electrode being arranged on the side of the substrate that faces the gate electrode, the bias electrode being arranged on the side of the substrate that faces away from the gate electrode, and the bias electrode being configured to receive a bias voltage, so as to adjust a threshold voltage of the threshold-voltage-adjustable transistor.

Description

Shift register unit, gate driving circuit, display device TECHNICAL FIELD

[0001] The present application relates to the technical field of display, and more particularly, to a shift register unit, a gate driving circuit comprising the shift register unit, and a display device comprising the gate driving circuit. BACKGROUND

[0002] A display device such as a liquid crystal display, an organic light emitting display, etc. usually comprises a gate driver disposed in a peripheral non-display area of the display device or between adjacent pixels in a display area, the gate driver comprising a plurality of shift register units cascaded, the shift register units being capable of obtaining a scan signal provided to each gate line based on an input clock signal.

[0003] Each shift register unit in the gate driver outputs a scan signal for each row of pixels in turn, and the stability or reliability of the scan signal is an important factor affecting the image display quality of the display device. Each shift register unit usually comprises a plurality of thin film transistors, and a change in the parameters or performance of the thin film transistors will affect whether the shift register unit outputs the scan signal normally. However, for the existing shift register units or gate drivers, little attention is paid to the adverse effect of a change in the threshold voltage of the thin film transistors on the output scan signal. SUMMARY

[0004] Embodiments of the present application propose a shift register unit, a gate driving circuit comprising the shift register unit, and a display device comprising the gate driving circuit, to alleviate the problem of the adverse effect of a drift or change in the threshold voltage of a transistor device in the shift register unit on the output scan signal.

[0005] According to various embodiments of the present application, a shift register unit comprises: an input circuit configured to be electrically connected to an input terminal and a first node to control a potential of the first node based on an input signal received from the input terminal; an output circuit configured to receive a clock signal and electrically connected to the first node, a second node, an output terminal and a first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under control of the potential of the first node and the potential of the second node; a node potential control circuit configured to be electrically connected to the first node, the second node, the first reference voltage terminal and a second reference voltage terminal to control the potential of the second node according to a second reference voltage provided by the second reference voltage terminal and the potential of the first node; a discharge circuit configured to be electrically connected to the first node, the second node and the first reference voltage terminal to discharge the first node under control of the potential of the second node; and a reset circuit configured to receive a reset signal and electrically connected to the first node to reset the first node under control of the reset signal, at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit comprises a threshold voltage adjustable transistor, the threshold voltage adjustable transistor comprises a substrate, a gate, a source-drain electrode and a bias electrode, wherein the source-drain electrode is disposed on a side of the substrate facing the gate, the bias electrode is disposed on a side of the substrate away from the gate, and the bias electrode is configured to receive a bias voltage to adjust a threshold voltage of the threshold voltage adjustable transistor.

[0006] In some embodiments, the threshold voltage adjustable transistor further comprises an active layer between the gate and the source-drain electrode, and a base for carrying the gate, wherein a footprint of the bias electrode on the base covers a footprint of the active layer on the base.

[0007] In some embodiments, the threshold voltage adjustable transistor further comprises a gate insulating layer between the source-drain electrode and the base, and covering the gate.

[0008] In some embodiments, the shift register unit further comprises a threshold voltage compensation transistor and a bias voltage receiving terminal for receiving the bias voltage, a control terminal of the threshold voltage compensation transistor is electrically connected to a control terminal of the threshold voltage adjustable transistor, one of the input terminal, an output terminal of the output circuit, a first terminal and a second terminal of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving terminal and the bias electrode of the threshold voltage adjustable transistor respectively.

[0009] In some embodiments, the shift register unit further comprises a switch transistor connected in series with the threshold voltage compensation transistor, the switch transistor being configured to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor.

[0010] In some embodiments, the threshold voltage adjustable transistor comprises a first type of transistor with a positive threshold voltage shift and a second type of transistor with a negative threshold voltage shift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein a control terminal of the first compensation transistor is electrically connected to a control terminal of the first type of transistor, a first terminal and a second terminal of the first compensation transistor are electrically connected to the first voltage receiving end and a bias electrode of the first type of transistor respectively, a control terminal of the second compensation transistor is electrically connected to a control terminal of the second type of transistor, a first terminal and a second terminal of the second compensation transistor are electrically connected to the second voltage receiving end and a bias electrode of the second type of transistor respectively, and wherein the first voltage receiving end and the second voltage receiving end are configured to receive a first voltage and a second voltage different from each other respectively.

[0011] In some embodiments, the threshold voltage adjustable transistor comprises a first type of transistor with a positive threshold voltage shift and a second type of transistor with a negative threshold voltage shift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein a control terminal of the first compensation transistor and a control terminal of the second compensation transistor are electrically connected to one of the first node, an input terminal of the input circuit or an output terminal of the output circuit, a first terminal and a second terminal of the first compensation transistor are electrically connected to the first voltage receiving end and a bias electrode of the first type of transistor respectively, a first terminal and a second terminal of the second compensation transistor are electrically connected to the second voltage receiving end and a bias electrode of the second type of transistor respectively, and wherein the first voltage receiving end and the second voltage receiving end are configured to receive a first voltage and a second voltage different from each other respectively.

[0012] In some embodiments, the shift register unit comprises a substrate for carrying the input circuit, the output circuit, the discharge circuit and the reset circuit, the substrate comprises a first region for arranging the first type of transistor and a second region for arranging the second type of transistor.

[0013] In some embodiments, the switch transistor includes a first switch transistor connected in series with the first compensation transistor, and a second switch transistor connected in series with the second compensation transistor, a control terminal of the first switch transistor and a control terminal of the second switch transistor being electrically connected to a compensation enable terminal providing a compensation enable signal.

[0014] In some embodiments, the input circuit includes a first transistor, a control terminal of the first transistor being electrically connected to the input terminal, a first terminal of the first transistor being electrically connected to the input terminal or a first control signal terminal, a second terminal of the first transistor being electrically connected to the first node, the reset circuit includes a second transistor, a control terminal of the second transistor being configured to receive a reset signal, a first terminal of the second transistor being electrically connected to the first node, a second terminal of the second transistor being electrically connected to a second control signal terminal or the first reference voltage terminal, the output circuit includes a third transistor, a fourth transistor and a capacitor, a control terminal of the third transistor being electrically connected to the first node, a first terminal of the third transistor being configured to receive the clock signal, a second terminal of the third transistor being electrically connected to the output terminal, a control terminal of the fourth transistor being electrically connected to the second node, a first terminal and a second terminal of the fourth transistor being electrically connected to the output terminal and the first reference voltage terminal respectively, the capacitor being electrically connected between the first node and the output terminal, the node potential control circuit includes a fifth transistor, a sixth transistor, a control terminal and a first terminal of the fifth transistor being electrically connected to the second reference voltage terminal, a second terminal of the fifth transistor being electrically connected to the second node, a control terminal of the sixth transistor being electrically connected to the first node, a first terminal and a second terminal of the sixth transistor being electrically connected to the second node and the first reference voltage terminal respectively,

[0015] the discharge circuit includes a seventh transistor, a control terminal of the seventh transistor being electrically connected to the second node, a first terminal and a second terminal of the first transistor being electrically connected to the first node and the first reference voltage terminal respectively, the first type of transistor includes the second transistor, the third transistor and the seventh transistor, the second type of transistor includes the first transistor.

[0016] In some embodiments, the substrate further includes a third region, the fourth transistor, the fifth transistor and the sixth transistor are arranged in the third region.

[0017] Another embodiment of the present application provides a gate drive circuit comprising a plurality of cascaded shift register units as described in the foregoing embodiments, the gate drive circuit further comprising a threshold voltage compensation circuit, the threshold voltage compensation circuit comprising a threshold voltage compensation transistor and a bias voltage receiving end for receiving the bias voltage, a control terminal of the threshold voltage compensation transistor being electrically connected to one of the output terminal, the input terminal or the first node in each shift register unit, a first terminal and a second terminal of the threshold voltage compensation transistor being electrically connected to the bias voltage receiving end and a bias electrode of the threshold voltage adjustable transistor in each shift register unit respectively.

[0018] In some embodiments, the threshold voltage adjustable transistor comprises a first type of transistor with a threshold voltage positive shift and a second type of transistor with a threshold voltage negative shift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein a control terminal of the first compensation transistor and a control terminal of the second compensation transistor are electrically connected to one of the output terminal, the input terminal or the first node in each shift register unit, a first terminal and a second terminal of the first compensation transistor are electrically connected to the first voltage receiving end and a bias electrode of the first type of transistor respectively, a first terminal and a second terminal of the second compensation transistor are electrically connected to the second voltage receiving end and a bias electrode of the second type of transistor respectively, wherein the first voltage receiving end and the second voltage receiving end are configured to receive a first voltage and a second voltage different from each other respectively.

[0019] In some embodiments, the threshold voltage compensation circuit further comprises a first switch transistor connected in series with the first compensation transistor and a second switch transistor connected in series with the second compensation transistor, a control terminal of the first switch transistor and a control terminal of the second switch transistor being electrically connected to a compensation enable end configured to provide a compensation enable signal.

[0020] In some embodiments, each shift register unit comprises a substrate for carrying the input circuit, the output circuit, the discharge circuit and the reset circuit, the substrate comprising a first region for arranging the first type of transistor and a second region for arranging the second type of transistor.

[0021] Another embodiment of the present application provides a display device comprising the gate drive circuit as described in any of the foregoing embodiments.

[0022] These and other advantages of the present application will become apparent to those skilled in the art from the following description, taken in combination with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0023] Embodiments of the present application will now be described in more detail and with reference to the drawings, in which:

[0024] Figure 1A illustrates a circuit structure block diagram of a shift register unit according to one embodiment of the present application;

[0025] Figure 1B schematically illustrates a partial cross-sectional view of a threshold voltage adjustable transistor in the shift register unit;

[0026] Figure 2A illustrates a detailed circuit schematic diagram of a shift register unit according to one embodiment of the present application;

[0027] Figure 2B illustrates a signal timing diagram of the shift register unit shown in Figure 2A according to one embodiment of the present application;

[0028] Figure 3 illustrates a detailed circuit schematic diagram of a shift register unit according to another embodiment of the present application;

[0029] Figure 4 illustrates a detailed circuit schematic diagram of a shift register unit according to yet another embodiment of the present application;

[0030] Figure 5 illustrates an electrical connection between a threshold voltage adjustable transistor and a threshold voltage compensation transistor in a shift register unit according to one embodiment of the present application;

[0031] Figure 6 illustrates an electrical connection between a threshold voltage adjustable transistor and a threshold voltage compensation transistor in a shift register unit according to another embodiment of the present application;

[0032] Figure 7 illustrates an electrical connection between a threshold voltage adjustable transistor, a threshold voltage compensation transistor, and a switching transistor in a shift register unit according to another embodiment of the present application;

[0033] Figure 8 illustrates an electrical connection between a threshold voltage adjustable transistor, a threshold voltage compensation transistor, and a switching transistor in a shift register unit according to yet another embodiment of the present application;

[0034] Figure 9 illustrates a partial plan structure diagram of a display device provided according to one embodiment of the present application;

[0035] Figure 10 schematically illustrates an electrical connection of a first compensation transistor and a first type of transistor, and an electrical connection of a second compensation transistor and a second type of transistor in a shift register unit provided according to one embodiment of the present application;

[0036] Figure 11 illustrates a partial circuit schematic diagram of a shift register unit provided according to another embodiment of the present application;

[0037] Fig. 12 illustrates a partial circuit schematic of a shift register unit provided according to another embodiment of the present application;

[0038] Fig. 13 is used to illustrate a sub-area layout for individual transistors in a shift register unit;

[0039] Fig. 14 is used to schematically illustrate a plurality of shift register units in cascade;

[0040] Fig. 15 schematically shows the electrical connection relationship between a threshold voltage adjustable transistor and a corresponding threshold voltage compensating transistor in two cascaded shift register units; and

[0041] Fig. 16 schematically illustrates two shift register units in a gate driving circuit and a threshold voltage compensating circuit. DETAILED DESCRIPTION

[0042] The following description provides specific details for a thorough understanding and enabling of various embodiments of the application. However, one skilled in the art will understand that the application can be practiced without one or more of the specific details. In some instances, well-known structures or functions have not been described in detail in order to avoid obscuring the description of the various embodiments of the application. The techniques of the present application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art.

[0043] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the description of the various embodiments of the application. The terms used in the description of the application should be interpreted to cover all spatial structures falling within the meaning and scope of the term.

[0044] Here, first, some of the terms involved in the embodiments of the present application are explained, so as to facilitate the understanding of the skilled in the art.

[0045] The "control terminal" mentioned herein refers to the gate of a transistor for receiving a scanning signal, and the transistor can be in a conductive state or a non-conductive state under the control of the signal received at the control terminal. The "first terminal" mentioned herein refers to one of the two terminals other than the control terminal among the terminals of the transistor, and the "second terminal" refers to the other of the two terminals other than the control terminal among the terminals of the transistor. That is, the first terminal can be one of the source and the drain of the transistor, and the second terminal can be the other of the source and the drain of the transistor. The "display device" mentioned herein can be a complete display product with an image display function, or can be a part of the complete display product, but the part includes the shift register unit or the gate driving circuit described in the embodiments of the present application.

[0046] The embodiments of the present application provide a shift register unit, which includes an input circuit, an output circuit, a node potential control circuit, a discharge circuit and a reset circuit. The input circuit is configured to be electrically connected to an input terminal and a first node to control a potential of the first node based on an input signal received from the input terminal. The output circuit is configured to receive a clock signal and be electrically connected to the first node, a second node, an output terminal and a first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under the control of the potential of the first node and the potential of the second node. The node potential control circuit is configured to be electrically connected to the first node, the second node, the first reference voltage terminal and a second reference voltage terminal to control the potential of the second node according to a second reference voltage provided by the second reference voltage terminal and the potential of the first node. The discharge circuit is configured to be electrically connected to the first node, the second node and the first reference voltage terminal to discharge the first node under the control of the potential of the second node. The reset circuit is configured to receive a reset signal and be electrically connected to the first node to reset the first node under the control of the reset signal. At least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit includes a threshold voltage adjustable transistor, which includes a substrate, a gate, a source-drain electrode and a bias electrode. The source-drain electrode is arranged on a side of the substrate facing the gate, and the bias electrode is arranged on a side of the substrate away from the gate. The bias electrode is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor.

[0047] The inventors of the present application realize that the threshold voltage of a transistor is related to the substrate bias voltage thereof. Taking an N-type metal oxide transistor as an example, if the substrate of the transistor is commonly connected to a ground with the source, the voltage difference V SB between the source and the substrate is equal to zero, and the threshold voltage of the transistor is V th0When the substrate voltage V B drops to a negative potential less than zero, more positive holes will be attracted to the vicinity of the substrate, leaving a large amount of immobile negative charges under the gate, thus causing the width of the depletion layer to increase. As the substrate bias voltage drops, the total number of charges in the depletion layer increases, which causes the threshold voltage V th to increase, which is known as the body effect. In the case of considering the body effect, the threshold voltage of a metal-oxide transistor can be expressed as the following formula:

[0048] where V th0 is the threshold voltage when the voltage difference between the source and the substrate of the transistor is zero, γ is the body effect factor, which is a constant and is related to the process of manufacturing the transistor, is the built-in potential.

[0049] Therefore, when the substrate bias voltage V B is a large positive voltage, the voltage difference V SB <0, the threshold voltage V th of the transistor decreases, while when the substrate bias voltage V B is a large negative voltage, the voltage difference V SB >0, the threshold voltage V th of the transistor increases. According to the body effect, the threshold voltage of a transistor can be adjusted by controlling the substrate bias voltage V B .

[0050] For the shift register unit provided by the embodiments of the present application, at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit includes a threshold voltage adjustable transistor, in other words, among the transistors included in the shift register unit, at least one threshold voltage adjustable transistor is included, the threshold voltage adjustable transistor includes the above-mentioned bias electrode, and the threshold voltage adjustable transistor can receive a bias voltage through the bias electrode, so as to adjust the threshold voltage of the threshold voltage adjustable transistor. In particular, after the shift register unit has been operated for a period of time, threshold voltage drift phenomenon may occur in at least some of the transistors, and in the case that the shift register unit includes a threshold voltage adjustable transistor, by applying an appropriate bias voltage to the bias electrode of the threshold voltage adjustable transistor, the threshold voltage drift phenomenon can be improved, the stability of the threshold of the transistors in the shift register unit can be promoted, and thus the stability and reliability of the output signal of the shift register unit can be improved, and the quality of the image displayed by the display device using the shift register unit can be improved.

[0051] Fig. 1A schematically shows a circuit structure diagram of a shift register unit. As shown in Fig. 1A, the shift register unit comprises an input circuit 101, an output circuit 103, a node potential control circuit 104, a discharge circuit 105 and a reset circuit 102. The input circuit 101 is electrically connected to an input terminal In and a first node N1 to control a potential of the first node N1 based on an input signal received from the input terminal In. The output circuit 103 is configured to receive a clock signal CLK and is electrically connected to the first node N1, a second node N2, an output terminal Out and a first reference voltage terminal Vr1 to provide an output signal to the output terminal Out based on the clock signal CLK under control of the potential of the first node N1 and the potential of the second node N2. The node potential control circuit 104 is configured to be electrically connected to the first node N1, the second node N2, the first reference voltage terminal Vr1 and a second reference voltage terminal Vr2 to control the potential of the second node N2 according to a second reference voltage provided by the second reference voltage terminal Vr2 and the potential of the first node N1. The discharge circuit 105 is configured to be electrically connected to the first node N1, the second node N2 and the first reference voltage terminal Vr1 to discharge the first node N1 under control of the potential of the second node N2. The reset circuit 102 receives a reset signal Re and is electrically connected to the first node N1 to reset the first node N1 under control of the reset signal Re. The present application does not make specific limitation on the specific circuit of the shift register unit, that is, the input circuit 101, the output circuit 103, the node potential control circuit 104, the discharge circuit 105 and the reset circuit 102 can have any specific form of circuit structure as long as the respective circuit units in the shift register unit can realize the corresponding functions.

[0052] As mentioned above, in the embodiments of the present application, at least part of the transistors includes a bias electrode for receiving a bias voltage, so as to adjust the threshold voltage of the part of the transistors, which are referred to as threshold voltage adjustable transistors in this document. FIG. IB schematically shows an example of a partial cross-sectional view of a threshold voltage adjustable transistor. As shown in FIG. IB, the threshold voltage adjustable transistor includes a substrate SB, a gate GA, a source-drain electrode including a source SE and a drain DE, and a bias electrode PE, the source-drain electrode is disposed on a side of the substrate SB facing the gate GA, the bias electrode PE is disposed on a side of the substrate PE away from the gate GA, and the bias electrode PE is configured to receive a bias voltage to adjust the threshold voltage of the threshold voltage adjustable transistor. In some embodiments, the threshold voltage adjustable transistor further includes an active layer between the gate and the source-drain electrode, and a base for carrying the gate, and a positive projection of the bias electrode on the base covers a positive projection of the active layer on the base. Further, the threshold voltage adjustable transistor further includes a gate insulating layer between the source-drain electrode and the base, and covering the gate. In some embodiments, the substrate SB includes an insulating material, which can be the same as the material of the gate insulating layer.

[0053] As shown in FIG. IB, the threshold voltage adjustable transistor further includes a base GB (for example, a glass base made of a glass material) and a gate insulating layer GI between the source-drain electrode SE, DE and the gate GA, and the base GB is disposed on a side of the gate GA away from the source-drain electrode to carry the gate GA. In fact, other layers of the threshold voltage adjustable transistor can be carried by the base GB. The material of the bias electrode includes but is not limited to indium tin oxide ITO or a metal film layer. In some embodiments, as shown in FIG. IB, the threshold voltage adjustable transistor further includes an active layer AL between the gate GA and the source-drain electrode SE, DE, and a positive projection of the bias electrode PE on the base GB covers a positive projection of the active layer AL on the base GB. That is, in this embodiment, the bias electrode PE is located above the active layer AL and covers an area as large as possible, and the positive projection of the bias electrode PE on the base GB covering the positive projection of the active layer AL on the base GB means that the coverage of the bias electrode includes the channel region of the threshold voltage adjustable transistor, so as to facilitate the adjustment of the threshold voltage of the threshold voltage adjustable transistor by the bias voltage via the bias electrode.

[0054] Fig. 2A illustrates a circuit schematic of a specific circuit of a shift register unit. As shown in Fig. 2A, the shift register unit comprises an input circuit 201, an output circuit 203, a node potential control circuit 204, a discharge circuit 205 and a reset circuit 202. The input circuit 201 comprises a first transistor M1, one of the first and second ends of the first transistor M1 is electrically connected to the control end thereof, the other of the first and second ends of the first transistor is electrically connected to a first node N1, and the control end of the first transistor receives an input signal In. In another embodiment, different from that shown in Fig. 2A, one of the first and second ends of the first transistor M1 is electrically connected to the first node N1, and the other of the first and second ends of the first transistor M1 can not be electrically connected to the control end thereof, but is electrically connected to a proper fixed potential or a pulse signal, as long as the control end of the first transistor M1 can be turned on when receiving the active level of the input signal. The reset circuit 202 comprises a second transistor M2, the control end of the second transistor M2 receives a reset signal Re, one of the first and second ends of the second transistor M2 is electrically connected to the first node N1, and the other of the first and second ends of the second transistor M2 is electrically connected to a first reference voltage terminal to receive a first reference voltage Vr1, and the second transistor M2 and the first transistor M1 actually form a series connection. The output circuit 203 comprises a third transistor M3, a fourth transistor M4 and a capacitor C, one of the first and second ends of the third transistor M3 is electrically connected to an output terminal, the other of the first and second ends of the third transistor M3 is used to receive a clock signal CLK, the control end of the third transistor M3 is electrically connected to the first node N1, and the capacitor C is electrically connected between the first node N1 and the output terminal. One of the first and second ends of the fourth transistor M4 is electrically connected to the output terminal, the other of the first and second ends of the fourth transistor M4 is electrically connected to the first reference voltage terminal, and the control end of the fourth transistor M4 is electrically connected to a second node N2. The node potential control circuit 204 comprises a fifth transistor M5 and a sixth transistor M6, one of the first and second ends of the fifth transistor M5 is electrically connected to the control end thereof, and the control end is also electrically connected to a second reference voltage terminal to receive a second reference voltage Vr2, the other of the first and second ends of the fifth transistor M5 is electrically connected to the second node N2, one of the first and second ends of the sixth transistor M6 is electrically connected to the second node N2, the other of the first and second ends of the sixth transistor M6 is electrically connected to the first reference voltage terminal, and the control end of the sixth transistor M6 is electrically connected to the first node N1. The discharge circuit 205 comprises a seventh transistor M7, the control end of the seventh transistor M7 is electrically connected to the second node N2, one of the first and second ends of the seventh transistor is electrically connected to the first node N1, and the other of the first and second ends of the seventh transistor is electrically connected to the first reference voltage terminal.It can be seen that the third transistor M3 and the fourth transistor M4 are actually connected in series between the clock signal receiving end and the first reference voltage end, and the fifth transistor M5 and the sixth transistor M6 are actually connected in series between the second reference voltage end and the first reference voltage end.

[0055] Figure 2B illustrates an example of a signal timing diagram for the shift register unit shown in Figure 2A. In this example, each of the transistors in the shift register unit shown in Figure 2A is an N-type thin film transistor (e.g., an NMOS transistor), the first reference voltage Vr1 received at the first reference voltage terminal is a constant low voltage, and the second reference voltage Vr2 received at the second reference voltage terminal is a constant high voltage. Figure 2B illustrates the signal timing diagram over one cycle. As shown in Figure 2B, at time t1, the shift register unit receives a valid input signal, i.e., the input signal In changes from low to high at time t1, accordingly, the first transistor M1 is turned on by the high input signal received at its control terminal, the capacitor C is charged, and the potential PN1 of the first node N1 jumps from an initial low potential to a first higher potential. This, in turn, turns on the third transistor M3 and the sixth transistor M6, and the potential PN2 of the second node N2 is the first reference voltage of the first reference voltage terminal, i.e., the potential PN2 of the second node N2 is low. Thus, the fourth transistor M4 and the seventh transistor M7 are in an off state. Since the clock signal CLK is low at this time, the output signal Out of the output terminal of the shift register unit remains low. In addition, the reset signal Re is low at this time, and thus the second transistor M2 is in an off state. At time t2, the clock signal CLK jumps from low to high, and due to the bootstrap effect of the capacitor C, the potential PN1 of the first node N1 is pulled up from the previous first higher potential to a second higher potential, the third transistor M3 and the sixth transistor M6 remain in an on state, the potential PN2 of the second node N2 remains the previous low, and the fourth transistor M4 and the seventh transistor M7 remain in an off state. The output signal Out of the output terminal of the shift register unit jumps from the previous low to high. At time t3, the clock signal CLK changes from high to low, and the output signal Out also changes from high to low accordingly. Similarly, due to the bootstrap effect of the capacitor C, the potential PN1 of the first node N1 starts to decrease from the previous second higher potential. When the potential PN1 of the first node N1 decreases to low (at time t4), the third transistor M3 and the sixth transistor M6 are turned off, and the potential PN2 of the second node N2 is not affected by the first reference voltage of the first reference voltage terminal at this time, and changes from the previous low to high. The high potential PN2 of the second node N2 turns on the fourth transistor M4 and the seventh transistor M7, so that the output signal Out of the output terminal remains low. In addition, the first node N1 discharges to the first reference voltage terminal via the seventh transistor M7, reducing or clearing the charge accumulated on the first node N1. In addition, the second transistor M2 is turned on by the valid reset signal Re (high between times t4 and t5) at time t4, ensuring that the output of the shift register unit is not affected by the change of the clock signal.

[0056] The shift register unit as shown in FIG. 2A can be applied to a gate driving circuit, which can include a plurality of shift register units as shown in FIG. 2A cascaded, and the output signal of each shift register unit can be provided as a scan signal to one of the gate lines of the display device, for example, the output signal of each shift register unit can be provided as a row scan signal for turning on a row of pixels. The active level (e.g., high level) of the output signal of each shift register unit comes in time sequence, thereby realizing row scanning of each row of pixels of the display device.

[0057] FIG. 3 illustrates a variant embodiment based on FIG. 2A. In this embodiment, the input circuit is electrically connected to the input terminal and the first node N1, and is further electrically connected to the first signal terminal to receive a first signal VS1, and the reset circuit receives a reset signal, and is further electrically connected to the first node N1 and the second signal terminal to receive a second signal VS2. The other circuits of the shift register unit are substantially the same as the embodiment shown in FIG. 2A. The first signal VS1 and the second signal VS2 can be adjusted, for example, the first signal VS1 and the second signal VS2 are set as a high level signal and a low level signal respectively, or the first signal VS1 and the second signal VS2 are set as a low level signal and a high level signal respectively. The gate driving circuit applying the shift register unit as shown in FIG. 2A can realize unidirectional scanning of multiple rows of pixels, and by changing the level of the first signal VS1 and the second signal VS2, the gate driving circuit applying the shift register unit as shown in FIG. 3 can realize bidirectional scanning (e.g., from top to bottom, or from bottom to top) of multiple rows of pixels.

[0058] Fig. 4 shows another example of a shift register unit, which includes an input circuit 401, a reset circuit 402, a discharge circuit 405, a node potential control circuit 404, and an output circuit 403. In this example, the node potential control circuit 404 includes a fifth transistor M6 and a sixth transistor M6 connected in series between the second reference voltage terminal and the first reference voltage terminal, an eighth transistor M8 and a ninth transistor M9 connected in series between the second reference voltage terminal and the first reference voltage terminal, the control terminals of the sixth transistor M6 and the ninth transistor M9 are electrically connected to the first node N1, one of the first terminal and the second terminal of the eighth transistor M8 is electrically connected to the control terminal thereof, and the other of the first terminal and the second terminal of the eighth transistor M8 is electrically connected to the control terminal of the fifth transistor. The connection point between the fifth transistor M6 and the sixth transistor M6 forms the second node N2. As for the first transistor M1, the second transistor M2, the seventh transistor M7, the third transistor M3, and the fourth transistor M4 in this shift register unit, their connection manners are basically the same as those of the embodiment shown in Fig. 2A, and thus will not be described here again. For the shift register unit shown in Fig. 4, the second reference voltage Vr2 received by the second reference voltage terminal is no longer a constant high-level voltage, but another clock signal which is complementary to the clock signal CLK. In the case where the clock signal CLK is a square wave signal, the second reference voltage Vr2 is a square wave signal having the same duty cycle as the clock signal CLK, but opposite phase.

[0059] According to some embodiments of the present application, the shift register unit further includes a threshold voltage compensation transistor and a bias voltage receiving terminal for receiving the bias voltage, the control terminal of the threshold voltage compensation transistor is electrically connected to one of the control terminal of the threshold voltage adjustable transistor, the input terminal, and the output terminal of the output circuit, and the first terminal and the second terminal of the threshold voltage compensation transistor are respectively electrically connected to the bias voltage receiving terminal and the bias electrode of the threshold voltage adjustable transistor.

[0060] Fig. 5 and Fig. 6 schematically show an example of the electrical connection relationship between the threshold voltage adjustable transistor and the threshold voltage compensation transistor in the shift register unit. The threshold voltage adjustable transistor can be any transistor in the shift register unit, which is uniformly denoted by reference sign MT in the figures, the control terminal of the threshold voltage adjustable transistor is denoted by reference sign A, the first terminal and the second terminal of the threshold voltage adjustable transistor are denoted by reference signs B and C respectively, and the bias electrode of the threshold voltage adjustable transistor for receiving the bias voltage is denoted by reference sign PE. As shown in Fig. 5, the control terminal of the threshold voltage compensation transistor Mb is electrically connected to the control terminal of the threshold voltage adjustable transistor MT, and the first terminal and the second terminal of the threshold voltage compensation transistor Mb are electrically connected to the bias voltage receiving terminal Vp and the bias electrode PE of the threshold voltage adjustable transistor respectively. In this embodiment, the control terminal of the threshold voltage compensation transistor and the control terminal of the threshold voltage adjustable transistor are controlled by the same control signal, so that when the threshold voltage adjustable transistor is turned on, the threshold voltage compensation transistor applies a bias voltage to the bias electrode of the threshold voltage adjustable transistor, thereby achieving compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor.

[0061] As shown in Fig. 6, the control terminal of the threshold voltage compensation transistor Mb is electrically connected to the output terminal or the input terminal of the shift register unit, and the first terminal and the second terminal of the threshold voltage compensation transistor Mb are electrically connected to the bias voltage receiving terminal Vp and the bias electrode PE of the threshold voltage adjustable transistor respectively. In this embodiment, the control terminal of the threshold voltage compensation transistor receives the aforementioned input signal or output signal, so that when the shift register unit receives a valid input signal In or outputs a valid output signal Out, the threshold voltage compensation transistor applies a bias voltage to the bias electrode PE of the threshold voltage adjustable transistor, thereby achieving compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor.

[0062] The threshold voltage adjustable transistor described above can be any transistor in the circuit schematic diagram of the shift register unit as shown in Fig. 2A, Fig. 3 or Fig. 4. In practice, different threshold voltage drifts can occur in different transistors in the shift register unit. For example, in the case of positive threshold voltage drift of the threshold voltage adjustable transistor MT, a positive bias voltage can be applied to the bias voltage receiving terminal Vp, thereby controlling the negative movement of the threshold voltage of the threshold voltage adjustable transistor MT, achieving compensation for the positive threshold voltage drift, promoting the stability of the threshold voltage of the threshold voltage adjustable transistor MT, and improving the stability and reliability of the output scan signal of the shift register unit. Conversely, in the case of negative threshold voltage drift of the threshold voltage adjustable transistor MT, a negative bias voltage can be applied to the bias voltage receiving terminal Vp, thereby controlling the positive movement of the threshold voltage of the threshold voltage adjustable transistor MT, achieving compensation for the negative threshold voltage drift.

[0063] According to another embodiment of the present application, the shift register unit further comprises a switch transistor connected in series with the threshold voltage compensation transistor, the switch transistor being used to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor. FIG. 7 and FIG. 8 illustrate an example of the electrical connection relationship of the threshold voltage compensation transistor, the threshold voltage adjustable transistor and the switch transistor in the shift register unit. As shown in FIG. 7 and FIG. 8, the shift register unit further comprises a switch transistor Ms connected in series with the threshold voltage compensation transistor Mb, the switch transistor Ms can control whether the bias voltage received from the bias voltage receiving terminal is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor Mb. The control terminal of the switch transistor Ms can be used to receive a control signal Vk, by using different levels of the control signal Vk, the switch transistor Ms can be controlled to be turned on or turned off. In other words, in this embodiment, the switch transistor Ms or the control signal Vk can have an enable function of whether to enable the adjustment or compensation of the threshold voltage of the threshold voltage adjustable transistor, therefore, the control signal Vk can also be referred to as a compensation enable signal. When the adjustment or compensation of the threshold voltage of the threshold voltage adjustable transistor MT is not needed, the switch transistor Ms can be turned off by using the control signal Vk, so as to prevent the transient compensation of the threshold voltage of the threshold voltage adjustable transistor and reduce the power consumption. The on time of the switch transistor Ms can be set according to different conditions. For example, after the shift register unit runs for a certain period of time which is set in advance, the switch transistor Ms can be turned on by using the control signal Vk, so as to enable the compensation or adjustment function of the threshold voltage compensation transistor Mb on the threshold voltage of the threshold voltage adjustable transistor. In other embodiments, the node potentials of some nodes and / or output signals of some shift register units in the gate driving circuit of the display device can be monitored, and whether to start the compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor can be determined according to the waveform changes of the node potentials and / or the waveform changes of the output signals.

[0064] [Corrected according to Rule 91 23.04.2025] For example, FIG. 9 illustrates a partial planar structural diagram of a display device provided according to one embodiment of the present application. As shown in FIG. 9, the display device includes a display area AA and a non-display area outside the display area AA, and further includes gate driving circuits GC1, GC2 located in the non-display area, which in this embodiment are distributed on both sides of the display area AA. The gate driving circuits GC1, GC2 can include a plurality of shift register units as described in any of the preceding embodiments. In addition, the display device further includes a shift register unit disposed in at least one corner of the four corners of its display surface, and FIG. 9 illustrates four shift register units disposed in the four corners of the display surface, respectively, which have the module structure as shown in FIG. 1A, all denoted by reference GOA. As shown in FIG. 9, signal lines are drawn from the first node N1, the second node and the output terminal of each shift register unit GOA, respectively, and the first node N1, the second node and the output terminal in the two shift register units GOA on the left are electrically connected to signal lines N1_L, N2_L and Out_L, respectively, and the first node N1, the second node and the output terminal in the two shift register units GOA on the right are electrically connected to signal lines N1_R, N2_R and Out_R, respectively. Thus, the signals of the first node, the second node and the output terminal of the four shift register units GOA can be monitored via these signal lines. When the waveforms of the node potentials and / or the waveforms of the output signals deviate greatly from the expected waveforms of the node potentials and the output signals of the output terminal, compensation or adjustment of the threshold voltage of the threshold voltage adjustable transistor can be initiated.

[0065] The threshold variations of the transistors in the shift register unit can be different for different transistors. For example, a portion of the transistors can have a positive threshold voltage shift, and another portion of the transistors can have a negative threshold voltage shift. Different threshold voltage adjustments or compensations can be performed for the transistors with positive threshold voltage shift and the transistors with negative threshold voltage shift. Therefore, in some embodiments, the threshold voltage adjustable transistors in the shift register unit include a first type of transistors with positive threshold voltage shift and a second type of transistors with negative threshold voltage shift, the threshold voltage compensation transistors include a first compensation transistor and a second compensation transistor, and the bias voltage receiving ends include a first voltage receiving end and a second voltage receiving end. Thus, different threshold voltage adjustments or compensations can be performed for the first type of transistors and the second type of transistors through the first voltage receiving end and the second voltage receiving end, the first compensation transistor and the second compensation transistor, respectively. FIG. 10 schematically shows the electrical connections of the first compensation transistor and the first type of transistors, and the electrical connections of the second compensation transistor and the second type of transistors in this embodiment. As shown in FIG. 10, the shift register unit GOA includes the first type of transistors MT1 with positive threshold voltage shift and the second type of transistors MT2 with negative threshold voltage shift, the threshold voltage compensation transistors include the first compensation transistor Mb1 and the second compensation transistor Mb2, the bias voltage receiving ends include the first voltage receiving end Vp1 and the second voltage receiving end Vp2, the control end of the first compensation transistor Mb1 is electrically connected to the control end A of the first type of transistors MT1, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the first voltage receiving end Vp1 and the bias electrode of the first type of transistors MT1, respectively, the control end of the second compensation transistor Mb1 is electrically connected to the control end of the second type of transistors, and the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp1 and the bias electrode of the second type of transistors MT2, respectively. The first voltage receiving end Vp1 and the second voltage receiving end Vp2 are used to receive a first voltage and a second voltage, respectively, which are different from each other. In some embodiments, the first type of transistors include at least one of the second transistor M2, the third transistor M3 and the seventh transistor M7 in the shift register unit shown in FIG. 2A, the second type of transistors include the first transistor M1 in the shift register unit shown in FIG. 2A, the first voltage is a positive voltage, and the second voltage is a negative voltage. Thus, the threshold voltage of the first type of transistors with positive threshold voltage shift can be reduced, and the threshold voltage of the second type of transistors with negative threshold voltage shift can be increased. In the embodiment of FIG. 10, the control end of the first compensation transistor and the control end of the first type of transistors are connected together, and the control end of the second compensation transistor and the control end of the second type of transistors are connected together.Alternatively, the first compensation transistor and the first type transistor can be controlled by different control signals respectively, and the second compensation transistor and the second type transistor can be controlled by different control signals respectively, for example, the control terminals of the first compensation transistor Mb1 and the second compensation transistor Mb2 can be electrically connected to the input end of the shift register unit to receive the input signal In or the output end to receive the output signal Out.

[0066] Fig. 11 illustrates a partial circuit of a shift register unit provided according to another embodiment of the present application. As shown in Fig. 11, the shift register unit GOA includes the first type transistors MT11, MT12 with positive threshold voltage drift and the second type transistors MT21, MT22 with negative threshold voltage drift, the threshold voltage compensation transistors include the first compensation transistors Mb11, Mb12 and the second compensation transistors Mb21, Mb22, the bias voltage receiving end includes the first voltage receiving end Vp1 and the second voltage receiving end Vp2, and the shift register unit GOA further includes two switch transistors Ms1, Ms2, the control terminals of the switch transistors Ms1, Ms2 are controlled by the control signal Vk, the first compensation transistors Mb11 and Mb12 are connected in parallel and then connected in series with the switch transistor Ms1, and the second compensation transistors Mb21 and Mb22 are connected in parallel and then connected in series with the switch transistor Ms2. The control terminals of the first compensation transistors Mb11, Mb12 are connected to the nodes Z1, Z2 respectively, for example, the nodes Z1 and Z2 can be electrically connected to the gate electrodes of the first type transistors MT11, MT12 respectively, and the control terminals of the second compensation transistors Mb21, Mb22 are connected to the nodes F1, F2 respectively, for example, the nodes F1 and F2 can be electrically connected to the gate electrodes of the second type transistors MT21, MT22 respectively. Therefore, when the control terminals of the switch transistors Ms1, Ms2 receive the effective control signal Vk, and the control terminals of the first compensation transistors Mb11 and Mb12 and the second compensation transistors Mb21, Mb22 receive the effective control signal to turn on, the first voltage (at this time, a positive voltage) received from the first voltage receiving end Vp1 can be applied to the bias electrodes of the first type transistors MT11, MT12 via the switch transistor Ms1 and the first compensation transistors Mb11, Mb12 respectively, so as to compensate or adjust the threshold voltage of the first type transistors MT11, MT12, and the second voltage (at this time, a negative voltage) received from the second voltage receiving end Vp2 can be applied to the bias electrodes of the second type transistors MT21, MT22 via the switch transistor Ms2 and the second compensation transistors Mb21, Mb22 respectively, so as to compensate or adjust the threshold voltage of the second type transistors MT21, MT22.

[0067] [Corrected according to Rule 91 23.04.2025] FIG. 12 illustrates a partial circuit schematic diagram of a shift register unit provided according to another embodiment of the present application. Similar to the foregoing embodiments, the threshold voltage adjustable transistors in the shift register unit include first type of transistors with threshold voltage positive shift and second type of transistors with threshold voltage negative shift (not shown in FIG. 12), the threshold voltage compensation transistors include first compensation transistor Mb1 and second compensation transistor Mb2, the bias voltage receiving ends include first voltage receiving end Vp1 and second voltage receiving end Vp1, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to node N, which can be one of the first node in the shift register unit, the input end of the input circuit or the output end of the output circuit discussed with reference to FIG. 1A, the first end and the second end of the first compensation transistor Mb1 are electrically connected to the first voltage receiving end Vp1 and the bias electrode PE1 of the first type of transistors respectively, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp2 and the bias electrode PE2 of the second type of transistors respectively, and the first voltage receiving end and the second voltage receiving end are used to receive first voltage and second voltage respectively, which are different from each other. The signal at node N in FIG. 12 can be the potential of the first node N1 in the shift register unit, the input signal In of the input end of the input circuit or the output signal Out of the output end of the output circuit discussed with reference to FIG. 1A.

[0068] With continued reference to FIG. 12, in some embodiments, the switch transistors include first switch transistor Ms1 connected in series with the first compensation transistor Mb1 and second switch transistor Ms2 connected in series with the second compensation transistor Mb2, the control end of the first switch transistor Ms1 and the control end of the second switch transistor Ms2 are electrically connected to a compensation enable end providing a compensation enable signal Vk. In this way, whether to compensate the threshold voltage of the first type of transistors and the second type of transistors can be controlled according to the compensation enable signal Vk provided by the compensation enable end, and different voltages (first voltage and second voltage) can be used to make different compensation or adjustment to the threshold voltage of the first type of transistors and the second type of transistors respectively.

[0069] According to some embodiments of the present application, the shift register unit comprises a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, the substrate comprises a first region for arranging the first type of transistors, and a second region for arranging the second type of transistors. The substrate of the threshold voltage adjustable transistor mentioned in the previous embodiments can be part of the substrate mentioned in the present embodiments, that is, the substrate of the threshold voltage adjustable transistor can extend in a plane to form the substrate in the present embodiments. Alternatively, in another embodiment, the substrate mentioned in the present embodiments is another support structure different from the substrate of the threshold voltage adjustable transistor. In this embodiment, the first type of transistors are arranged in the first region, and the second type of transistors are arranged in the second region, that is, all the transistors with positive threshold voltage drift in the shift register unit are arranged in the first region, and all the transistors with negative threshold voltage drift are arranged in the second region different from the first region. FIG. 13 schematically shows a first region A1 and a second region A2 of the substrate of the shift register unit. All the transistors with positive threshold voltage drift in the shift register unit are arranged in the first region A1, therefore, the first region A1 can also be referred to as a threshold voltage positive drift compensation region, and the second region A2 can also be referred to as a threshold voltage negative drift compensation region, in which case, the same bias voltage (for example, a positive voltage) can be applied to the bias electrodes of each first type of transistor in the first region A1, and the same bias voltage (for example, a negative voltage) can be applied to the bias electrodes of each second type of transistor in the second region A2, while the integrated design of the bias electrodes of each first type of transistor and the integrated design of the bias electrodes of each second type of transistor can be achieved, which is conducive to simplifying the manufacturing process of the bias electrodes of the threshold voltage adjustable transistor in the shift register unit. In the embodiment of FIG. 13, the substrate further comprises a third region A3 between the first region A1 and the second region A2, and the transistors in the shift register unit whose threshold voltage does not drift or whose working characteristics do not change easily can be arranged in the third region A3. For the transistors whose threshold voltage does not drift seriously or does not drift easily, there is no need to compensate or adjust the threshold voltage, therefore, the third region A3 can be referred to as a threshold voltage non-compensation region. By using the partitioned layout of each transistor as illustrated in the embodiment of FIG. 13, the compensation of the threshold voltage of the threshold voltage adjustable transistor can be optimized.

[0070] The first type of transistor and the second type of transistor are exemplarily illustrated in combination with FIG. 2A and FIG. 3. As shown in FIG. 2A or FIG. 3, the input circuit includes a first transistor M1, a control terminal of the first transistor M1 is electrically connected to an input terminal, a first terminal of the first transistor M1 is electrically connected to the input terminal or a first control signal terminal (a terminal receiving a first control signal Vs1), and a second terminal of the first transistor M1 is electrically connected to a first node N1. The reset circuit includes a second transistor M2, a control terminal of the second transistor M2 is configured to receive a reset signal Re, a first terminal of the second transistor M2 is electrically connected to the first node N1, and a second terminal of the second transistor M2 is electrically connected to a second control signal terminal (a terminal receiving a second control signal Vs2) or a first reference voltage terminal. The output circuit includes a third transistor M3, a fourth transistor M4, and a capacitor C. A control terminal of the third transistor M3 is electrically connected to the first node N1, a first terminal of the third transistor M3 is configured to receive the clock signal CLK, and a second terminal of the third transistor M3 is electrically connected to an output terminal. A control terminal of the fourth transistor M4 is electrically connected to a second node N2, a first terminal and a second terminal of the fourth transistor M4 are electrically connected to the output terminal and the first reference voltage terminal, respectively. The capacitor C is electrically connected between the first node N1 and the output terminal. The node potential control circuit includes a fifth transistor M5 and a sixth transistor M5. A control terminal and a first terminal of the fifth transistor M5 are electrically connected to a second reference voltage terminal, and a second terminal of the fifth transistor M5 is electrically connected to the second node N2. A control terminal of the sixth transistor M6 is electrically connected to the first node N1, a first terminal and a second terminal of the sixth transistor M6 are electrically connected to the second node N2 and the first reference voltage terminal, respectively. The discharge circuit includes a seventh transistor M7, a control terminal of the seventh transistor M7 is electrically connected to the second node N2, and a first terminal and a second terminal of the first transistor M1 are electrically connected to the first node N1 and the first reference voltage terminal, respectively. Through a large number of experimental monitoring and research, the inventors of the present application realize that the second transistor M2, the third transistor M3, and the seventh transistor M7 in the shift register unit are prone to positive threshold voltage drift, and the first transistor M1 is prone to negative threshold voltage drift. Therefore, in this embodiment, the first type of transistor includes the second transistor M2, the third transistor M3, or the seventh transistor M7, and the second type of transistor includes the first transistor M1. The threshold voltages of the fourth transistor M4, the fifth transistor M5, and the sixth transistor M6 are not prone to drift. At this time, the second transistor M2, the third transistor M3, or the seventh transistor M7 can be arranged in the aforementioned first region, and the fourth transistor M4, the fifth transistor M5, and the sixth transistor M5 are arranged in the aforementioned third region.

[0071] Another embodiment of the present application provides a gate drive circuit including a plurality of shift register units as described in the foregoing embodiments, which are cascaded with each other to output a plurality of scan signals respectively staggered in timing. FIG. 14 schematically shows four cascaded shift register units, each of which includes an input terminal for receiving an input signal IN, a clock signal input terminal for receiving a clock signal CLK, a reset terminal for receiving a reset signal Re, an output terminal for providing an output signal OUT (i.e., a scan signal), and further, an output signal OUT of a preceding shift register unit is provided as an input signal IN to an adjacent subsequent shift register unit. Signal lines SL1 and SL2 transmit the clock signal and the reset signal to each shift register unit, respectively. According to some embodiments of the present application, the gate drive circuit further includes a threshold voltage compensation circuit, which can include a plurality of threshold voltage compensation transistors corresponding to the shift register units, a control terminal of each threshold voltage compensation transistor being electrically connected to one of the output terminal, the input terminal or the first node in the corresponding shift register unit, and a first terminal and a second terminal of the threshold voltage compensation transistor being electrically connected to the bias voltage receiving terminal and a bias electrode of the threshold voltage adjustable transistor in the corresponding shift register unit, respectively. For example, FIG. 15 schematically shows the electrical connection relationship between the threshold voltage adjustable transistor M3 and the corresponding threshold voltage compensation transistor Mb in two cascaded shift register units.

[0072] According to another embodiment of the present application, the threshold voltage compensation circuit in the gate drive circuit includes threshold voltage compensation transistors and a bias voltage receiving terminal for receiving a bias voltage, a control terminal of each threshold voltage compensation transistor being electrically connected to one of the output terminal, the input terminal or the first node in each shift register unit, and a first terminal and a second terminal of the threshold voltage compensation transistor being electrically connected to the bias voltage receiving terminal and a bias electrode of the threshold voltage adjustable transistor in each shift register unit, respectively. That is, in this embodiment, the same threshold voltage adjustable transistors in each shift register unit or threshold voltage adjustable transistors with the same threshold voltage drift characteristics (e.g., the first type of transistors) share one threshold voltage compensation transistor, thereby simplifying the design of the threshold voltage compensation circuit for the threshold voltage of the threshold voltage adjustable transistors in each shift register unit.

[0073] According to another embodiment of the present application, the threshold voltage adjustable transistor comprises a first type of transistor with threshold voltage positive shift and a second type of transistor with threshold voltage negative shift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to one of the output end, the input end or the first node in each shift register unit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor respectively, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor respectively, wherein the first voltage receiving end and the second voltage receiving end are used for receiving a first voltage and a second voltage different from each other respectively. For example, FIG. 16 schematically illustrates two shift register units in a gate driving circuit and a threshold voltage compensation circuit. As shown in FIG. 16, each shift register unit comprises a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, the substrate comprises a first area A1 for arranging the first type of transistor and a second area A2 for arranging the second type of transistor. The first area A1 comprises the first type of transistor with threshold voltage positive shift, the second area A2 comprises the second type of transistor with threshold voltage negative shift, and the transistor with threshold voltage without compensation or adjustment is arranged in a third area A3. As shown in FIG. 16, the threshold voltage compensation transistor comprises a first compensation transistor Mb1 and a second compensation transistor Mb2, the bias voltage receiving end comprises a first voltage receiving end Vp1 and a second voltage receiving end Vp2, the control end of the first compensation transistor Mb1 and the control end of the second compensation transistor Mb2 are electrically connected to the output end in each shift register unit, the first end and the second end of the first compensation transistor Mb1 are electrically connected to the first voltage receiving end Vp1 and the bias electrode of the first type of transistor respectively, the first end and the second end of the second compensation transistor Mb2 are electrically connected to the second voltage receiving end Vp1 and the bias electrode of the second type of transistor respectively, and the first voltage receiving end Vp1 and the second voltage receiving end Vp2 are used for receiving a first voltage and a second voltage different from each other respectively.In the embodiment of FIG. 16, the transistors in each shift register unit are arranged in different regions according to threshold voltage drift characteristics, and the threshold voltages of the transistors in different regions can be compensated or adjusted by the first compensation transistor Mb1 and the second compensation transistor Mb2. For example, the first voltage received by the first voltage receiving end Vp1 can be a positive voltage to facilitate the negative shift (lower threshold voltage) of the threshold voltage of the first type of transistors in the first region A1, and the second voltage received by the second voltage receiving end Vp2 can be a negative voltage to facilitate the positive shift (increase threshold voltage) of the threshold voltage of the second type of transistors in the second region A2. Meanwhile, the threshold voltage compensation circuit can be shared by each shift register unit, which is conducive to the structural simplification of the gate drive circuit. In FIG. 16, the control ends of the first compensation transistor Mb1 and the second compensation transistor Mb2 are electrically connected to the output ends Out1 and Out2 in each shift register unit, but in other embodiments, the control ends of the first compensation transistor Mb1 and the second compensation transistor Mb2 are electrically connected to the input ends or the first nodes in each shift register unit.

[0074] With continued reference to FIG. 16, according to some embodiments of the present application, the threshold voltage compensation circuit further comprises a first switch transistor Ms1 connected in series with the first compensation transistor Mb1, and a second switch transistor Ms2 connected in series with the second compensation transistor Mb2, and the control ends of the first switch transistor Ms1 and the second switch transistor Ms2 are electrically connected to a compensation enable end for providing a compensation enable signal Vk. Therefore, by means of the compensation enable signal Vk received by the compensation enable end, the conduction and non-conduction of the first switch transistor Ms1 and the second switch transistor Ms2 can be controlled, so as to control whether the corresponding bias voltage is applied to the bias electrode of the threshold voltage adjustable transistor in each shift register unit, facilitating the user's control of whether the threshold voltage compensation function is enabled.

[0075] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various devices, elements, components or parts, these devices, elements, components or parts should not be limited by these terms. For example, the aforementioned first to seventh sub-package structures are only used to distinguish the names of the sub-package structures in different embodiments of the power amplification device. In addition, the "electrically connected" mentioned herein includes "directly connected" or "indirectly connected". Although the technical solutions of the present application have been described in conjunction with some embodiments, the scope of protection of the present application is not limited to the specific forms set forth herein, and the scope of protection of the present application is defined by the appended claims.

Claims

1. A shift register unit characterized by comprising: The shift register unit comprises: an input circuit configured to be electrically connected to an input terminal and a first node to control a potential of the first node based on an input signal received from the input terminal; an output circuit configured to receive a clock signal and electrically connected to the first node, a second node, an output terminal and a first reference voltage terminal to provide an output signal to the output terminal based on the clock signal under control of the potential of the first node and the potential of the second node; a node potential control circuit configured to be electrically connected to the first node, the second node, the first reference voltage terminal and a second reference voltage terminal to control the potential of the second node according to a second reference voltage provided by the second reference voltage terminal and the potential of the first node; a discharge circuit configured to be electrically connected to the first node, the second node and the first reference voltage terminal to discharge the first node under control of the potential of the second node; and a reset circuit configured to receive a reset signal and electrically connected to the first node to reset the first node under control of the reset signal, wherein at least one of the input circuit, the output circuit, the node potential control circuit, the discharge circuit and the reset circuit comprises a threshold voltage adjustable transistor comprising a substrate, a gate, a source-drain electrode and a bias electrode, wherein the source-drain electrode is disposed on a side of the substrate facing the gate, the bias electrode is disposed on a side of the substrate facing away from the gate, and the bias electrode is configured to receive a bias voltage to adjust a threshold voltage of the threshold voltage adjustable transistor.

2. The shift register cell of claim 1, wherein, The threshold voltage adjustable transistor further comprises an active layer between the gate and the source-drain electrode, and a base for bearing the gate, wherein a footprint of the bias electrode on the base covers a footprint of the active layer on the base.

3. The shift register cell of claim 2, wherein, The threshold voltage adjustable transistor further comprises a gate insulating layer between the source-drain electrode and the base, and covering the gate.

4. The shift register cell of claim 1, wherein, The shift register unit further comprises a threshold voltage compensation transistor and a bias voltage receiving terminal for receiving the bias voltage, a control terminal of the threshold voltage compensation transistor is electrically connected to a control terminal of the threshold voltage adjustable transistor, one of the input terminal, an output terminal of the output circuit, a first terminal and a second terminal of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving terminal and the bias electrode of the threshold voltage adjustable transistor respectively.

5. The shift register cell of claim 4, wherein, The shift register unit further comprises a switch transistor connected in series with the threshold voltage compensation transistor, the switch transistor is used to control whether the bias voltage is provided to the bias electrode of the threshold voltage adjustable transistor via the threshold voltage compensation transistor.

6. The shift register cell of claim 4, wherein, The threshold voltage adjustable transistor comprises a first type of transistor with positive threshold voltage drift and a second type of transistor with negative threshold voltage drift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, and the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor is electrically connected to the control end of the first type of transistor, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor respectively, the control end of the second compensation transistor is electrically connected to the control end of the second type of transistor, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor respectively, and the first voltage receiving end and the second voltage receiving end are used for receiving first voltage and second voltage different from each other respectively.

7. The shift register cell of claim 4, wherein, The threshold voltage adjustable transistor comprises a first type of transistor with positive threshold voltage drift and a second type of transistor with negative threshold voltage drift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, and the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein the control end of the first compensation transistor and the control end of the second compensation transistor are electrically connected to one of the first node, the input end of the input circuit or the output end of the output circuit, the first end and the second end of the first compensation transistor are electrically connected to the first voltage receiving end and the bias electrode of the first type of transistor respectively, the first end and the second end of the second compensation transistor are electrically connected to the second voltage receiving end and the bias electrode of the second type of transistor respectively, and the first voltage receiving end and the second voltage receiving end are used for receiving first voltage and second voltage different from each other respectively.

8. The shift register unit according to claim 6 or 7, characterized in that, The shift register unit comprises a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit and the reset circuit, and the substrate comprises a first region for arranging the first type of transistor and a second region for arranging the second type of transistor.

9. The shift register cell of claim 6 or 7, wherein, The switch transistor comprises a first switch transistor connected in series with the first compensation transistor and a second switch transistor connected in series with the second compensation transistor, and the control end of the first switch transistor and the control end of the second switch transistor are electrically connected to a compensation enable end for providing a compensation enable signal.

10. The shift register cell of claim 8, wherein, The input circuit comprises a first transistor, the control end of the first transistor is electrically connected to the input end, the first end of the first transistor is electrically connected to the input end or a first control signal end, the second end of the first transistor is electrically connected to the first node, The reset circuit comprises a second transistor, the control end of the second transistor is used for receiving a reset signal, the first end of the second transistor is electrically connected to the first node, and the second end of the second transistor is electrically connected to a second control signal end or the first reference voltage end, The output circuit comprises a third transistor, a fourth transistor and a capacitor, a control end of the third transistor is electrically connected to the first node, a first end of the third transistor is configured to receive the clock signal, a second end of the third transistor is electrically connected to the output end, a control end of the fourth transistor is electrically connected to the second node, a first end and a second end of the fourth transistor are electrically connected to the output end and the first reference voltage end respectively, the capacitor is electrically connected between the first node and the output end, The node potential control circuit comprises a fifth transistor and a sixth transistor, a control end and a first end of the fifth transistor are electrically connected to the second reference voltage end, a second end of the fifth transistor is electrically connected to the second node, a control end of the sixth transistor is electrically connected to the first node, a first end and a second end of the sixth transistor are electrically connected to the second node and the first reference voltage end respectively, The discharge circuit comprises a seventh transistor, a control end of the seventh transistor is electrically connected to the second node, a first end and a second end of the first transistor are electrically connected to the first node and the first reference voltage end respectively, The first type of transistor comprises the second transistor, the third transistor and the seventh transistor, and the second type of transistor comprises the first transistor.

11. The shift register cell of claim 10, wherein, The substrate further comprises a third region, and the fourth transistor, the fifth transistor and the sixth transistor are arranged in the third region.

12. A gate drive circuit comprising a plurality of cascaded shift register units as claimed in any one of claims 1-3, characterized in that, The gate drive circuit further comprises a threshold voltage compensation circuit, the threshold voltage compensation circuit comprises a threshold voltage compensation transistor and a bias voltage receiving end configured to receive the bias voltage, a control end of the threshold voltage compensation transistor is electrically connected to one of the output end, the input end or the first node in each shift register unit, a first end and a second end of the threshold voltage compensation transistor are electrically connected to the bias voltage receiving end and a bias electrode of the threshold voltage adjustable transistor in each shift register unit respectively.

13. The gate drive circuit according to claim 12, characterized by The threshold voltage adjustable transistor comprises a first type of transistor with positive threshold voltage drift and a second type of transistor with negative threshold voltage drift, the threshold voltage compensation transistor comprises a first compensation transistor and a second compensation transistor, the bias voltage receiving end comprises a first voltage receiving end and a second voltage receiving end, wherein a control end of the first compensation transistor and a control end of the second compensation transistor are electrically connected to one of the output end, the input end or the first node in each shift register unit, a first end and a second end of the first compensation transistor are electrically connected to the first voltage receiving end and a bias electrode of the first type of transistor respectively, a first end and a second end of the second compensation transistor are electrically connected to the second voltage receiving end and a bias electrode of the second type of transistor respectively, and the first voltage receiving end and the second voltage receiving end are configured to receive a first voltage and a second voltage different from each other respectively.

14. The gate drive circuit according to claim 13, characterized by The threshold voltage compensation circuit further comprises a first switch transistor connected in series with the first compensation transistor, and a second switch transistor connected in series with the second compensation transistor, a control terminal of the first switch transistor and a control terminal of the second switch transistor being electrically connected to a compensation enable terminal providing a compensation enable signal.

15. The gate drive circuit of claim 13, wherein, Each shift register unit comprises a substrate for carrying the input circuit, the output circuit, the pull-up circuit, the pull-down circuit, the discharge circuit, and the reset circuit, the substrate comprising a first area for arranging the first type of transistors, and a second area for arranging the second type of transistors.

16. A display device comprising the gate driver circuit of any one of claims 12-15.

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