Methods, device, chip, medium, system and circuit

Abstract

Methods, a device, a chip, a medium, a system and a circuit. A data writing method comprises: on the basis of write configuration information, writing into X×Y storage blocks in a first memory a first data packet to be written, wherein the first memory comprises at least N×M storage sub-blocks, each storage block at least comprises n×m storage sub-blocks, N≥n, M≥m, and N, n, Y, M, m and X are all integers greater than 0. In the solution provided in the embodiments of the present application, on the basis of write configuration information and by means of write remapping, each first data packet to be written is separately written into a plurality of storage blocks in a memory, so that a requirement for flexible reading can be met, the efficiency of on-demand data retrieval in specific application scenarios is improved, and the data read / write speed requirements of complex applications are met.

Description

Method, equipment, chip, medium, system, circuit Cross-references to related applications

[0001] This application is based on and claims priority to Chinese patent application No. 202411029456.0, filed on July 29, 2024, and Chinese patent application No. 202410581843.9, filed on May 10, 2024, the entire contents of which are hereby incorporated herein by reference. Technical Field

[0002] This application relates to chip technology, and more particularly to a method, device, chip, medium, system, and circuit. Background Technology

[0003] In the field of chip technology, efficient data access schemes are one of the key factors affecting chip performance. Some specialized chips involve the processing of various types of related data. Beyond improving general data access schemes, exploring the relationships between different types of data and proposing targeted data access schemes can further improve chip data processing efficiency and enhance chip performance. Summary of the Invention

[0004] This application provides a data writing method, a data reading method, an electronic device, a chip, and a storage medium. According to the writing configuration information, a write remapping method is used to write each first data packet to be written into multiple storage blocks in the memory. This can meet the need for flexible reading, improve the efficiency of on-demand data retrieval in specific application scenarios, and meet the data read and write speed requirements of complex applications.

[0005] This application provides a data writing method, including: writing a first data packet to be written into X×Y storage blocks on a first memory according to writing configuration information; wherein, the first memory includes at least N×M storage sub-blocks, and each storage block includes at least n×m storage sub-blocks; N≥n, M≥m, and N, n, Y, M, m, and X are all integers greater than 0.

[0006] This application also provides a data reading method, comprising: reading data from multiple storage sub-blocks in a first memory according to a read mode marker to form a first read data packet; wherein the first memory includes at least N×M storage sub-blocks; N and M are both integers greater than 0; the first read data packet includes data written according to the data writing method described in any embodiment of this application.

[0007] This application embodiment also provides a data writing method, including: a first chip sequentially writing a first group of multiple first data packets to be written into X1×Y1 storage blocks on the first memory of the first chip according to the data writing method provided in this application embodiment; a second chip sequentially writing a second group of multiple first data packets to be written into X2×Y2 storage blocks on the first memory of the second chip according to the data writing method provided in this application embodiment; and writing all or part of the data in the X1×Y1 storage blocks on the first memory of the first chip into other storage blocks on the second chip besides the X2×Y2 storage blocks.

[0008] This application also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the data writing method as described in any embodiment of this application, and / or implement the data reading method as described in any embodiment of this application.

[0009] This application also provides a chip, including a processor, the processor being configured to implement the data writing method as described in any embodiment of this application, and / or to implement the data reading method as described in any embodiment of this application.

[0010] This application also provides an electronic device, including a plurality of chips as described in any embodiment of this application; wherein each chip further includes a first memory, at least two of the first memories of the chips share the same memory, or the first memory of each chip is independently configured.

[0011] This application also provides a computer-readable storage medium having a computer program stored thereon. When executed by a processor, the program implements the data writing method as described in any embodiment of this application, and / or implements the data reading method as described in any embodiment of this application.

[0012] This application provides an access control method, comprising: determining a memory address range corresponding to a memory module pointed to by an access request based on a source address in an obtained access request; wherein the memory module is divided into a non-mapped address range and a mapped address range; if the memory address range is the non-mapped address range, then the source address is directly accessed; if the memory address range is the mapped address range, then a target address is determined according to the mapping rules corresponding to the source address and the mapped address range, and the target address is accessed.

[0013] This application embodiment also provides an access control system, including: a configuration module, an access module, a mapping module, and at least one memory module; the configuration module is used to divide the memory address range of at least one memory module into a non-mapped address range and a mapped address range, and configure corresponding mapping rules for the mapped address range; the access module is used to send an access request to the mapping module, the access request carrying a source address; the mapping module is used to determine the memory address range corresponding to the memory module pointed to by the access request based on the source address, and when the memory address range corresponding to the access request is a non-mapped address range, control the access module to directly access the source address; the mapping module is also used to determine the target address based on the mapping rules corresponding to the source address and the mapped address range when the memory address range corresponding to the access request is a mapped address range, and control the access module to access the target address.

[0014] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the access control method described above.

[0015] This application also provides an integrated circuit, including: a radio frequency module for generating radio frequency transmission signals and receiving radio frequency reception signals; an analog signal processing module for down-converting the radio frequency reception signals to obtain intermediate frequency signals; and a processing module for performing access control on the intermediate frequency signals based on the above-described access control method.

[0016] This application also provides a wireless device, including: a carrier; an integrated circuit as described above, disposed on the carrier; and an antenna disposed on the carrier for transmitting and receiving radio signals.

[0017] This application also provides a terminal device, including: a device body; and a wireless device as described above disposed on the device body, the wireless device being used for target detection.

[0018] This application embodiment also provides a signal processing method, including: writing echo digital signal data into memory according to the data writing method described in any of the preceding claims; reading the written echo digital signal data from memory according to the data reading method described in any of the preceding claims; and processing the read echo digital signal data according to a multi-level calculation in a preset digital signal processing flow, wherein after each level of calculation in the multi-level calculation is completed, the calculated result is written into memory, and before the s-th level calculation in the multi-level calculation, the memory is accessed according to the access control method described in any of the preceding claims to read data for the s-th level calculation, 1 < s ≤ t, where t is the total number of levels of calculation included in the multi-level calculation.

[0019] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings. Attached Figure Description

[0020] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0021] Figure 1 is a schematic diagram of the storage space division of a first memory in an embodiment of this application;

[0022] Figure 2 is a flowchart of a data writing method in an embodiment of this application;

[0023] Figure 3 is a schematic diagram of data writing / reading in an embodiment of this application;

[0024] Figure 4 is a schematic diagram of a data writing result in an embodiment of this application;

[0025] Figure 5 is a schematic diagram of a data readout result in an embodiment of this application;

[0026] Figure 6 is a schematic diagram of another data writing result in an embodiment of this application;

[0027] Figure 7 is a schematic diagram of another data readout result in an embodiment of this application;

[0028] Figure 8 is a flowchart of a data writing method in an embodiment of this application;

[0029] Figure 9 is a schematic diagram of the structure of a radar system according to an embodiment of this application;

[0030] Figure 10 is a schematic diagram of a storage controller structure in an embodiment of this application;

[0031] Figure 11 is a schematic diagram of another radar receiver in an embodiment of this application;

[0032] Figure 12 is a schematic diagram of another radar receiver in an embodiment of this application;

[0033] Figure 13 is a schematic diagram of another radar receiver in an embodiment of this application;

[0034] Figure 14 is a schematic diagram of another radar receiver in an embodiment of this application;

[0035] Figure 15 is a schematic diagram of another radar receiver in an embodiment of this application;

[0036] Figure 16 is a flowchart of an access control method provided in an embodiment of this application;

[0037] Figure 17 is a schematic diagram of the memory address mapping architecture in one embodiment of this application;

[0038] Figure 18 is a schematic diagram of address mapping based on mapping rules in one embodiment of this application;

[0039] Figure 19 is a schematic diagram of the access control system structure provided in another embodiment of this application;

[0040] Figure 20 is a schematic diagram of an integrated circuit provided in another embodiment of this application. Detailed Implementation

[0041] This application describes several embodiments, but these descriptions are exemplary and not restrictive, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0042] This application includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this application may also be combined with any conventional features or elements to form a unique inventive scheme as defined by the claims. Any feature or element of any embodiment may also be combined with features or elements from other inventive schemes to form another unique inventive scheme as defined by the claims. Therefore, it should be understood that any feature shown and / or discussed in this application may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0043] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that it does not depend on such a specific order. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims concerning the method and / or process should not be limited to the steps performed in the written order, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments of this application.

[0044] In various specialized chips, data access is often the key factor affecting the overall efficiency of application functionality. Taking millimeter-wave radar signal processing as an example, signal data involves multiple transmission channels and multiple reception channels, and depending on the application requirements of target identification, it involves various data processing dimensions such as range, velocity, reception, and transmission. The solution provided in this application embodiment, based on the data storage structure and configured with corresponding write and read methods, can meet the needs of data reading in different dimensions.

[0045] It should be noted that the embodiments of this application use the writing and reading of millimeter-wave radar data as an example to illustrate the writing and reading scheme, but do not limit the scheme to only this aspect. Based on this specific example, those skilled in the art can understand other schemes with related data relationships, and are not limited to the aspects exemplified in the embodiments of this application.

[0046] Taking a radar chip as an example, the radar antenna emits electromagnetic waves and receives reflected echo signals from the target object. These initial emitted signals and / or echo signals are sampled, Fourier transformed, and processed to obtain target detection data. This process involves writing and reading a large amount of raw data, intermediate process data, and target data. The radar chip includes a storage medium / memory to store this data.

[0047] The on-chip first memory provided in this application includes at least N×M memory sub-blocks. In some exemplary embodiments, the first memory is divided into at least N columns and M rows, that is, the entire memory space is divided into at least N columns, corresponding to N column memory sub-blocks, with column indices from 0 to N-1 (or 1 to N). Each column memory sub-block is further divided into at least M rows, corresponding to M memory sub-blocks, with row indices from 0 to M-1 (or 1 to M). The bit width of each column memory sub-block is L bits, and correspondingly, the bit width of each memory sub-block is also L bits. Alternatively, the entire memory space is divided into at least M rows, corresponding to M row memory sub-blocks, with column indices from 0 to M-1 (or 1 to M). Each row memory sub-block is further divided into at least N columns, corresponding to N memory sub-blocks, with row indices from 0 to N-1 (or 1 to N). The bit width of each memory sub-block is also L bits.

[0048] It should be noted that, in the embodiments of this application, unless otherwise specified, the i-th column storage sub-block and the i-th column storage sub-block are equivalent concepts, and the j-th row storage sub-block and the j-th row storage sub-block are equivalent concepts.

[0049] In some exemplary embodiments, each column storage sub-block (the storage sub-block in each column) in the first memory independently sets a read / write enable signal. For example, if the i-th column storage sub-block (the i-th column storage sub-block) is write-enabled, then writing can be performed on the corresponding storage sub-block in that column based on the row address. Each row corresponds to an address depth. In some exemplary embodiments, when one or more column storage sub-blocks are read / write enabled, one or more storage sub-blocks in the same row on the enabled column storage sub-block are accessed using the same row index or row address.

[0050] Alternatively, each row storage sub-block (a storage sub-block in each row) in the first memory can be independently configured with a read / write enable signal. For example, if the j-th row storage sub-block (the j-th row storage sub-block) is write-enabled, then writing can be performed on the corresponding storage sub-block in that row based on the column address. Each column corresponds to an address depth. In some exemplary embodiments, one or more row storage sub-blocks are read / write enabled, and one or more storage sub-blocks in the same row on the enabled row storage sub-block are accessed using the same column index or column address. It should be noted that this disclosure describes more detailed examples using the example of each column storage sub-block corresponding to one read / write enable signal, and those skilled in the art can infer the corresponding implementation method of each row storage block corresponding to one read / write enable signal.

[0051] In some exemplary embodiments, as shown in FIG1, N=16, M=36, the first memory is divided into 36 rows and 16 columns, that is, it includes 16 column storage sub-blocks, 0-15, each column storage sub-block includes 36 storage sub-blocks, 0-35, each storage sub-block has a bit width of L bits of data, A0, B0, C0, ..., A1, B1, C1, ....

[0052] Depending on application needs, these storage sub-blocks are further divided into multiple storage blocks, each consisting of adjacent m rows and n columns of storage sub-blocks. Each storage block can store a data set with certain data relationships, depending on application requirements. The specific values ​​of m and n are determined based on the amount of data contained in the data set and the bit width of the storage sub-blocks. For example, as shown in Figure 1, the 36×16 storage sub-blocks on the first memory are used to construct 3×4 storage blocks, each of which includes 12 storage sub-blocks on 4 column storage sub-blocks, meaning each storage block includes 12×4=48 storage sub-blocks.

[0053] This application provides a data writing method, as shown in Figure 2, including:

[0054] Step 210: According to the write configuration information, write the first data packet to be written into X×Y storage blocks on the first memory;

[0055] The first memory includes at least N×M storage sub-blocks, and each storage block includes at least n×m storage sub-blocks.

[0056] N≥n, M≥m, N, n, Y, M, m, X are all integers greater than 0.

[0057] In some exemplary embodiments, the first memory includes at least N×M storage sub-blocks, which can be understood as the first memory including at least N column storage sub-blocks, and each column storage sub-block including at least M storage blocks. Each storage block includes at least n×m storage sub-blocks, which can be understood as each storage block including at least m storage sub-blocks from each of the n column storage sub-blocks.

[0058] In some exemplary embodiments, the data writing method further includes: obtaining a first data packet to be written from a first data writing instruction.

[0059] In some exemplary embodiments, the data to be written included in the first data write instruction constitutes a first data packet to be written. The first data packet to be written obtained from the first data write instruction is distributed and written into the respective storage sub-blocks of multiple storage blocks.

[0060] In some exemplary embodiments, the first data write instruction further includes a first write enable signal and a first write address. The first write address includes any one of the following: a write location identifier corresponding to the first data packet to be written, a data source identifier of the first data packet to be written, or a memory address.

[0061] In some exemplary embodiments, the first data packet to be written is divided into Xi second data packets to be written, and each second data packet to be written is divided into Yj third data packets to be written, where Xi×Yj=X×Y, and Yj and Xi are both integers greater than 0. At this time, writing the first data packet to be written into X×Y storage blocks on the first memory includes: writing the Xi×Yj third data packets to be written included in the first data packet to be written into the X×Y storage blocks respectively.

[0062] In some exemplary embodiments, Xi = A × X, Yj = Y / A, and A is an integer greater than 0. For example, A = 1, or A = 2, or other values.

[0063] In some exemplary embodiments, writing the first data packet to be written into X×Y storage blocks on the first memory includes: for each of the Xi second data packets to be written, performing the following steps to write data: writing the Yj third data packets to be written corresponding to the second data packet to be written into the Yj storage sub-blocks in the same row of the Yj column storage sub-blocks.

[0064] That is, each time the Yj column storage sub-blocks (Yj column storage sub-blocks) are simultaneously enabled for writing, the Yj third data to be written is written to the Yj column that is enabled for writing using the same row address.

[0065] In some exemplary embodiments, A=1, the first data packet to be written is divided into X second data packets to be written, and each second data packet to be written is divided into Y third data packets to be written; writing the first data packet to be written into X×Y storage blocks on the first memory includes: writing the X×Y third data packets to be written included in the first data packet to be written into the X×Y storage blocks respectively.

[0066] In some exemplary embodiments, writing the first data packet to be written into X×Y storage blocks on the first memory includes: for each of the X second data packets to be written, performing the following steps to write data: writing the Y third data packets to be written corresponding to the second data packet to be written into the Y storage sub-blocks of the same row on the Y column storage sub-blocks respectively.

[0067] In some exemplary embodiments, a first data write instruction is mapped to Xi second data write instructions, and these Xi second data write instructions are executed respectively, writing one second data packet to be written each time. The second data write instruction includes: data to be written, a second write enable signal, and a second write address.

[0068] It can be understood that the first write address is the logical address specified by the sender of the first data write instruction, and the mapped second write address is the physical address to be written. In some exemplary embodiments, the second write address is a row index or a row address.

[0069] The second write enable signal comprises Yj signals, each corresponding to one of the Yj column storage sub-blocks. These Yj second write enable signals control the write capability of the corresponding Yj column storage sub-blocks. The process is divided into Xi write clock cycles, during which Xi second data packets to be written are written sequentially. In each write clock cycle, the same second write address is used to write Yj third data packets to one storage sub-block on each of the Yj column storage sub-blocks.

[0070] It should be noted that the relevant read and write processes are described using column enable as an example in this application embodiment. For the case of exercise enable, the corresponding implementation can be carried out, and they are not described in detail one by one.

[0071] In some exemplary embodiments, the data writing method is applied to a radar system, which includes: x receiving antennas and y transmitting antennas; X×Y=x×y, where x and y are both integers greater than 0; and a first data packet to be written includes signal data of the radar system in one range dimension of a chirp.

[0072] In some exemplary embodiments, the radar system includes U range dimensions; the data writing method further includes writing U first data packets to be written generated by a chirp into a first memory.

[0073] In this dataset, the total range dimension data of a chirp consists of one receiving antenna and one transmitting antenna, denoted as a bank; the data of a dataset is stored in a storage block in the first memory.

[0074] In some exemplary embodiments, M = X × m.

[0075] In some exemplary embodiments, N = Y × n.

[0076] It can be understood that one receiving antenna of the radar system corresponds to one receiving dimension of radar signal data, and one transmitting antenna corresponds to one transmitting dimension of radar signal data. A radar system with x receiving antennas corresponds to x receiving dimensions of radar signal data, and a radar system with y transmitting antennas corresponds to y transmitting dimensions of radar signal data. One bank corresponds to one transmitting-receiving dimension of signal data. There are x receiving dimensions: receiving dimension 1, receiving dimension 2, ..., receiving dimension X, and Y transmitting dimensions: transmitting dimension 1, transmitting dimension 2, ..., transmitting dimension y, for a total of x×y transmitting-receiving dimensions of signal data. The signal data of each transmitting-receiving dimension constitutes a dataset, denoted as a bank, for a total of x×y banks. These banks are correspondingly written into x×y = X×Y storage blocks in the first memory, with each storage block storing the signal data of one bank.

[0077] In some exemplary embodiments, the radar signal data of the radar system includes U range dimensions, with each bank corresponding to data for all range points in the receive-transmit dimension. The U range-dimensional signal data of the radar system in one chirp corresponds to U first data packets to be written.

[0078] In some exemplary embodiments, the first memory is RAM (Random Access Memory) or FLASH (flash memory). In some exemplary embodiments, the first memory is a memory of other types of storage media.

[0079] In some exemplary embodiments, X is also denoted as row_bnk_num, indicating the number of banks in the row direction in the first memory; Y is also denoted as col_bnk_num, indicating the number of banks in the column direction; n is also denoted as bnk_col_siz, indicating the number of column storage sub-blocks corresponding to one bank; m is also denoted as bnk_row_siz, indicating the number of row storage sub-blocks corresponding to one bank. U is also denoted as pkg_num, indicating the number of the first data packets to be written.

[0080] Based on this, the size of a first data packet to be written is pkg_siz×L, where pkg_siz=X×Y.

[0081] A bank corresponds to m×n storage sub-blocks, which are m×n storage sub-blocks on m adjacent rows of n adjacent column storage sub-blocks.

[0082] In some exemplary embodiments, the configuration information written includes the values ​​of the following configuration parameters: X, Y, N, and M.

[0083] In some exemplary embodiments, writing configuration information also includes the values ​​of the following configuration parameters: n and m.

[0084] In some exemplary embodiments, writing configuration information also includes the value of the following configuration parameter: L.

[0085] In some exemplary embodiments, writing configuration information also includes the value of the following configuration parameter: U.

[0086] In some exemplary embodiments, writing configuration information also includes the values ​​of the following configuration parameters: Xi and Yj.

[0087] In some exemplary embodiments, as shown in Figure 3, when radar signal data is written to RAM via DMA (Direct Memory Access), the remapping module (addr_remapping) remaps the write address and write enable, determining the mapping result based on the values ​​of various configuration parameters included in the configuration information. The first data write instruction includes an instruction part and a data part. The instruction part includes a first read / write enable and a first write address, and the data part includes a first data packet to be written (data[31:0]*4). The first data write instruction is divided into two paths: one instruction part is connected to the remapping module, and the other data part is connected to all column storage sub-blocks (RAM bank 1…N) on the first memory RAM via a second multiplexer MUX. The remapping module maps the first read / write enable and the first write address (addr / wen / ren) to obtain Y second read / write enable and X second write addresses (row addresses) (addr / wen / ren*4). The multiple instructions obtained by mapping are connected to all column storage sub-blocks on the first memory RAM via a first multiplexer MUX. The second read / write enable indicates which column storage sub-block in RAM is selected, and the second write address indicates which row address is read / written. The sel signal generated by the remapping module is used as the MUX data selection signal.

[0088] In some exemplary embodiments, the first data write instruction is a DMA instruction, and correspondingly, the first data packet to be written is denoted as a DMA package.

[0089] In some exemplary embodiments, as shown in Figure 4, A = 1, X = Xi = 4, Y = Yj = 4. A chirped ADC (Analog to Digital Converter) data is written to RAM according to the receive dimension, transmit dimension, and distance dimension. The receive dimension size is 4, the transmit dimension size is 4, and the distance dimension size is 512. In the example, Y / col_bnk_num is 4, X / row_bnk_num is 4, m / bnk_row_siz is 512 / 4 = 128, n / bnk_col_siz is 4, U / pkg_num is 512, and pkg_siz is 16 × L bits, where L is 32. That is, a storage sub-block stores 32 bits of the third data to be written, which is DMA package 1 data (i.e., A1 A2……D1 D2 D3 D4). It is divided into 4 parts and written to the corresponding storage blocks of 16 banks in 4 write data cycles: when the first write data cycle arrives, the second data packet to be written, A1 A2, is written. A3 and A4 (corresponding to the four receiving antennas) are written into four storage sub-blocks in the same row of four columns. A1 is written into the first position in bank1, A2 into the first position in bank2, A3 into the first position in bank3, and A4 into the first position in bank4. Bank1 stores all distance points in both the receiving dimension 1 and the transmitting dimension 1, bank2 stores all distance points in both the receiving dimension 2 and the transmitting dimension 1, and so on.

[0090] When the second write data cycle arrives, the second data packets to be written, A5, A6, A7, and A8 (corresponding to the four receiving antennas), are written to the four storage sub-blocks in the same row of the four columns. A5 is written to the first position in bank5, A6 is written to the first position in bank6, A7 is written to the first position in bank7, and A8 is written to the first position in bank8.

[0091] ...

[0092] When the fourth write data cycle arrives, the second data packets to be written, A13, A14, A15, and A16 (corresponding to the four receiving antennas), are written into the four storage sub-blocks in the same row of the four columns. A13 is written to the first position in bank13, A14 is written to the first position in bank14, A15 is written to the first position in bank15, and A16 is written to the first position in bank16.

[0093] With this distributed writing, the data of each DMA package will be distributed to various banks, and each bank stores all the distance point data of the corresponding transmit-receive dimension channel.

[0094] In some exemplary embodiments, when performing 1D-FFT (1D Fast Fourier Transform) processing, the FFT processing engine only needs to read all distance point data in the corresponding bank for calculation, and then write the processed frequency domain data back to the corresponding position.

[0095] In some exemplary embodiments, the sender of the first data write instruction includes: a DMA controller, an MCU (microcontroller unit), or a CPU (central processing unit), etc.

[0096] This application also provides a data reading method, including:

[0097] According to the read mode marking, data is read from multiple storage sub-blocks on the first memory to form the first read data packet.

[0098] The first memory includes at least N×M storage sub-blocks; N and M are both integers greater than 0; the first read data packet includes data written according to the data writing method of any embodiment of this application.

[0099] In some exemplary embodiments, the read mode marker indicates a first read mode; the plurality of storage sub-blocks are at least n×m storage sub-blocks included in any one of the X×Y storage blocks in the first memory. Reading data from the plurality of storage sub-blocks in the first memory according to the read mode marker includes: reading data from m×n storage sub-blocks in one storage block according to the first read mode.

[0100] In some exemplary embodiments, reading data from multiple storage sub-blocks in a first memory includes: reading data in m steps, each step of which involves reading data from n storage sub-blocks in the same row of n column storage sub-blocks in any one storage block.

[0101] In some exemplary embodiments, the data reading method further includes: obtaining a read mode flag from a first data read instruction.

[0102] The readout mode marker indicates either the first readout mode or the second readout mode.

[0103] In some exemplary embodiments, the sender of the first data readout instruction includes a DMA controller, an MCU, or a CPU, etc.

[0104] In some exemplary embodiments, the first data read instruction includes a first read enable signal and a first read address. The first read address includes any one of the following: a memory block identifier corresponding to the target read data packet, a dataset identifier of the read data packet, or a memory address.

[0105] In some exemplary embodiments, a first data read instruction is mapped to m second data read instructions, and these m second data read instructions are executed respectively, reading one second data packet at a time. The second data read instruction includes a second read enable signal and a second read address. The second read enable signals include n signals, each corresponding to one of the n column storage sub-blocks. The process is divided into m read clock cycles, sequentially reading m second data packets. In each read clock cycle, the same second read address is used to read data from one storage sub-block on each of the n column storage sub-blocks.

[0106] It can be understood that the first read address is the logical address specified by the sender of the first data read instruction, and the mapped second read address is the physical address to be read. In some exemplary embodiments, the second read address is a row index or a row address.

[0107] Taking Figure 4 as an example, the first read data packet corresponds to the data: A1 B1 C1 D1... n=4, m=512 / 4=124. This first read data packet is read from 4 column storage sub-blocks in 128 times (128 read clock cycles). Each read clock cycle reads 4 packets from the same row, which in turn form 128 second read data packets A1 B1 C1 D1, A2 B2 C2 D2,...

[0108] In some exemplary embodiments, the data readout method is applied to a radar system; the method further includes performing a one-dimensional fast Fourier transform (1D-FFT) based on the first readout data packet.

[0109] Taking Figure 4 as an example, the first read data packet corresponds to data such as A1 B1 C1 D1... or A2 B2 C2 D2... etc. Each first read data packet corresponds to all 512 range-dimensional radar signal data in a bank. During 1D-FFT processing, after acquiring the 512 data points in a bank, performing calculations, and obtaining the corresponding frequency domain data, it is written back to the m×n storage sub-blocks corresponding to that bank.

[0110] In some exemplary embodiments, the read mode marker indicates a second read mode; the plurality of storage sub-blocks are one storage sub-block from each of the X×Y storage blocks in the first memory; each storage block includes at least n×m storage sub-blocks. Reading data from the plurality of storage sub-blocks in the first memory according to the read mode marker includes: reading data from one storage sub-block from each of the X×Y storage blocks according to the second read mode.

[0111] In some exemplary embodiments, reading data from multiple storage sub-blocks on a first memory includes: reading data in Xi steps, each time performing the following steps: reading data from Yj storage sub-blocks in the same row of Yj column storage sub-blocks included in X×Y storage blocks, where Xi×Yj = X×Y, and Yj and Xi are both integers greater than 0.

[0112] In some exemplary embodiments, Xi = A × X, Yj = Y / A, and A is an integer greater than 0. For example, A = 1, or A = 2, or other values.

[0113] In some exemplary embodiments, A=1, Xi=X, Yj=Y, reading data from multiple storage sub-blocks on the first memory includes: reading data in X times, each time performing the following steps: reading data from Y storage sub-blocks in the same row of Y column storage sub-blocks included in X×Y storage blocks.

[0114] In some exemplary embodiments, the first data readout instruction includes a first readout enable signal and a first readout address. The first readout address includes any one of the following: a distance dimension identifier corresponding to the target readout data packet, or a memory address.

[0115] In some exemplary embodiments, a first data read instruction is mapped to Xi second data read instructions, and these Xi second data read instructions are executed respectively, reading one second data packet at a time. The second data read instruction includes a second read enable signal and a second read address. The second read enable signal includes Yj signals, each corresponding to Yj column storage sub-blocks. The process is divided into Xi read clock cycles, sequentially reading Xi second data packets. In each read clock cycle, the same second read address is used to read data from one storage sub-block on each of the Yj column storage sub-blocks.

[0116] It can be understood that the first read address is the logical address specified by the sender of the first data read instruction, and the mapped second read address is the physical address to be read. In some exemplary embodiments, the second read address is a row index or a row address.

[0117] Taking Figure 5 as an example, A=1, X=Xi=4, Y=Yj=4, the first read data packet corresponds to the data: A1 A2 A3…A16. X=4, Y=4, this first read data packet is read from 4 column storage sub-blocks in 4 times (4 read clock cycles), and 4 packets from the same row are read in each read clock cycle, which are used to form 4 second read data packets A1 A2 A3 A4, A5 A6 A7 A8, … in sequence.

[0118] In some exemplary embodiments, the data readout method is applied to a radar system; the data readout method further includes: constructing velocity dimension data based on a first readout data packet. The constructed velocity dimension data can be used for subsequent CFAR processing.

[0119] In some exemplary embodiments, the data writing method shown in Figure 4 is used to write the 2D-FFT result data corresponding to 16 banks—512 first data packets to be written (DMA packages 1, 2, ..., 512)—into 16 memory blocks corresponding to the 16 banks. One velocity dimension frequency domain data of the receive-transmit dimension is written into one memory block corresponding to each bank. The data reading method shown in Figure 5 is used to sequentially aggregate and read out the 512 first read data packets. The combiner engine reads 4 packets per clock cycle over 4 read clock cycles, obtaining a first read data packet by reading the same velocity dimension data of all 16 receive-transmit dimensions. This first read data packet is then combined to obtain a velocity unit data. This process is repeated until all 512 first read data packets are obtained, and after merging, all 512 velocity unit data are obtained.

[0120] In some exemplary embodiments, X = x = 8, Y = y = 8, U = 512, n = 4, m = 16. The radar system includes 8 receiving antennas and 8 transmitting antennas, including 512 range dimensions. 64 storage blocks correspond to 64 banks. Each storage block includes 4 data packets. The data writing method is executed, A = 2, Xi = 2 × 8 = 16, Yj = 8 / 2 = 4, as shown in Figure 6. There are 512 first data packets to be written. Each first data packet to be written is divided into Xi = 16 second data packets to be written. Each second data packet to be written is divided into Yj = 4 third data packets to be written. Each first data packet to be written is written in 16 parts, with 4 packets written each time.

[0121] When the first write data cycle arrives, the second data packet A1 A2 A3 A4 to be written is written to the four sub-storage blocks on the four columns;

[0122] When the second write data cycle arrives, the second data packet to be written, A5 A6 A7 A8, is written to the four sub-storage blocks on the four columns;

[0123] ...

[0124] When the sixteenth write data cycle arrives, the second data packet to be written, A61 A62 A63 A64, is written to the four sub-storage blocks on the four columns.

[0125] Accordingly, the read mode marker indicates the second read mode, executing 512 data read operations to form 512 corresponding first read data packets, as shown in Figure 7. Each data read is further divided into 16 read cycles, reading 4 data packets each time. The first read data includes:

[0126] The first data read cycle arrives, and data A1 A2 A3 A4 is read from the four sub-blocks on the four columns;

[0127] The second data read cycle arrives, and data A5 A6 A7 A8 is read from the four sub-blocks on the four columns;

[0128] ...

[0129] The sixteenth data read cycle arrives, and data A61 A62 A63 A64 is read from the four sub-blocks on the four columns;

[0130] The first read data packet is formed: A1 A2 A3 A4…A61 A62 A63 A64.

[0131] In other exemplary embodiments, A = 1, Xi = X = 8, Yj = Y = 8, 512 first data packets to be written, each first data packet to be written is divided into Xi = 8 second data packets to be written, each second data packet to be written is divided into Yj = 8 third data packets to be written, and each first data packet to be written is written in 8 parts, with 8 packets written each time:

[0132] When the first write data cycle arrives, the second data packet A1 A2 A3 A4 A5 A6 A7 A8 is written to the 8 sub-storage blocks on the 8 columns;

[0133] The second write data cycle arrives, and the second data packet to be written, A9 A10 A11 A12 A13 A14 A15 A16, is written to the 8 sub-storage blocks on the 8 columns;

[0134] ...

[0135] When the eighth write data cycle arrives, the second data packet to be written, A57 A58 A59 A60 A61 A62 A63 A64, is written to the eight sub-storage blocks on the eight columns.

[0136] Accordingly, the read mode marker indicates the second read mode, executing 512 data read operations to form 512 corresponding first read data packets. Each data read is further divided into 8 read cycles, with 8 data packets read each time. These constitute one first read data packet: A1 A2 A3 A4…A61 A62 A63 A64.

[0137] This application embodiment also provides a data writing method, as shown in Figure 8, including:

[0138] Step 810: The first chip writes a first group of multiple first data packets to be written into X1×Y1 storage blocks on the first memory of the first chip in accordance with the data writing method described in any embodiment of this application.

[0139] Step 820: The second chip writes the second group of multiple first data packets to be written into X2×Y2 storage blocks on the first memory of the second chip in accordance with the data writing method described in any embodiment of this application.

[0140] Step 830: Write all or part of the data in the X1×Y1 storage blocks on the first memory of the first chip into other storage blocks on the second chip besides the X2×Y2 storage blocks.

[0141] The data writing method described in steps 810 and 820 is a method for writing the first data packet to be written into the first memory.

[0142] In some exemplary embodiments, all data in the X1×Y1 storage blocks on the first memory of the first chip is written into the other X1×Y1 storage blocks on the second chip, excluding the X2×Y2 storage blocks; that is, the second chip includes at least X1×Y1+X2×Y2 storage blocks.

[0143] In some exemplary embodiments, the first memory of the second chip includes at least X1×Y1+X2×Y2 memory blocks. In some exemplary embodiments, the first memory of the second chip includes at least X2×Y2 memory blocks, and the second memory of the second chip includes at least X1×Y1 memory blocks; this is not limited to any particular aspect.

[0144] The method for writing data to the second chip in step 830 can be flexibly selected and is not limited to a specific aspect. In some exemplary embodiments, step 830 employs a memory data synchronization method, writing all or part of the data in the X1×Y1 memory blocks of the first chip to other memory blocks outside the X2×Y2 memory blocks of the second chip.

[0145] In some exemplary embodiments, the method is applied to a radar receiver, also known as a radar system, which includes at least a first chip and a second chip.

[0146] In some exemplary embodiments, the first chip further includes a first radio frequency module, which includes x1 receiving antennas and y1 transmitting antennas; the second chip further includes a second radio frequency module, which includes x2 receiving antennas and y2 transmitting antennas.

[0147] It can be understood that this radar system uses two cascaded chips with radio frequency modules to form x1+x2 receiving antennas and y1+y2 transmitting antennas, corresponding to (x1+x2)×(y1+y2) data sets. Specifically, the first memory on the first chip includes at least X1×Y1 memory blocks, where X1×Y1 = x1×(y1+y2), and the first memory on the second chip includes at least X2×Y2+X1×Y1 memory blocks, where X2×Y2 = x2×(y1+y2) and X1×Y1 = x1×(y1+y2). Therefore, the first memory of the second chip includes at least (x1+x2)×(y1+y2) memory blocks.

[0148] For example, the radar system shown in Figure 9 includes a first chip 910, also referred to as a slave chip, which is a 4R4T (4-receive-4-transmit) radar chip, including a (first) radio frequency module 9110 and a first memory 9120; the radar system also includes a second chip 920, also referred to as a master chip, which is a 4R4T (4-receive-4-transmit) radar chip, including a (second) radio frequency module 9210 and a first memory 9220. The first memory 9120 of the first chip 910 includes 32 storage blocks (i.e., 32 banks), and the first set of multiple first data packets to be written received by the (first) radio frequency module 9110 is sequentially written into these 32 banks; the first memory 9220 of the second chip 920 includes 64 storage blocks (i.e., 32+32 banks), and the second set of multiple first data packets to be written received by its (second) radio frequency module 9210 is sequentially written into 32 of these banks; the data in the 32 storage blocks of the first memory 9120 is synchronized to the other 32 banks of the first memory 9220.

[0149] The specific method for synchronizing data from bank 32 of the first memory 9120 of the first chip 910 to bank 32 of the first memory 9220 of the second chip 920 can be flexibly selected as needed.

[0150] It is understood that the first chip 910 includes a processor to execute the write method and / or data read method; the second chip 920 includes a processor to execute the write method and / or data read method.

[0151] By adopting the above data writing scheme, the device or on-chip system can use two chips to perform data processing and storage writing in parallel. For radar systems, using a multi-chip solution to expand more radio frequency signal transceiver channels can improve detection accuracy. The parallel execution of data processing and storage writing by multiple chips improves system efficiency and ensures the detection performance of the radar system to meet more application needs.

[0152] This application embodiment also provides a storage controller, as shown in FIG10, including:

[0153] Remapping module 1010 and first memory 1020;

[0154] The first memory is divided into N columns and M rows, totaling M×N storage sub-blocks; each column is set with a second enable signal, and storage sub-blocks in the same row on different columns correspond to the same second address; N and M are both integers greater than 1.

[0155] The remapping module is used to map the received first address to multiple second addresses and the received first enable signal to multiple second enable signals.

[0156] The first enable signal includes either a first write enable signal or a first read enable signal; the second enable signal includes either a second write enable signal or a second read enable signal; the first address includes either a first write address or a first read address; and the second address includes either a second write address or a second read address.

[0157] In some exemplary embodiments, the remapping module 1010 is configured to map the received first address to a plurality of second addresses and the received first enable signal to a plurality of second enable signals according to configuration information.

[0158] In some exemplary embodiments, the storage controller is applied to the radar system, and the configuration information includes: the number of columns corresponding to each bank (bnk_col_siz), the number of rows corresponding to each bank (bnk_row_siz), the number of banks in the column direction (col_bnk_num), and the number of banks in the row direction (row_bnk_num).

[0159] In some exemplary embodiments, the configuration information further includes: the number of data packets to be read and written, pkg_num, and the size of each data packet, pkg_siz×L; where L is the bit width of the storage sub-block.

[0160] In some exemplary embodiments, L = 32 bits.

[0161] As shown in Figure 5, bnk_col_siz=4, bnk_row_siz=128, col_bnk_num=4, row_bnk_num=4, pkg_num=512, pkg_siz=16.

[0162] In some exemplary embodiments, applied to radar systems, col_bnk_num equals the number of receive dimensions, i.e., the number of receive antennas; row_bnk_num equals the number of transmit dimensions, i.e., the number of transmit antennas; pkg_num equals the number of range dimensions, i.e., divided into pkg_num range cells; and pkg_siz equals the number of banks.

[0163] In some exemplary embodiments, M storage sub-blocks in the same column constitute a column storage sub-block; N storage sub-blocks in the same row constitute a row storage sub-block. A second write enable signal controls the write enable of a column storage sub-block, and a second read enable signal controls the read enable of a column storage sub-block.

[0164] In some exemplary embodiments, the remapping module is configured to map one first address to X second addresses and one first enable signal to Y second enable signals. Alternatively, the remapping module is configured to map one first address to m second addresses and one first enable signal to n second enable signals. Where N≥n, M≥m, and N, n, Y, M, m, and X are all integers greater than 0.

[0165] In some exemplary embodiments, the remapping module is further configured to generate a first multiplexer selection control signal based on configuration information and a write clock cycle signal.

[0166] In some exemplary embodiments, the remapping module is further configured to generate a second multiplexer selection control signal based on configuration information and a read clock cycle signal.

[0167] In some exemplary embodiments, a first multiplexer 1030 and a second multiplexer 1040 are also included;

[0168] The first terminal of the first multiplexer 1030 receives multiple second addresses and multiple second enable signals output by the remapping module 1010. The second terminal of the first multiplexer 1030 is connected to all column storage sub-blocks of the first memory. The selection signal of the first multiplexer 1030 is the first multiplexer selection control signal output by the remapping module. According to the first multiplexer selection control signal, the first multiplexer 1030 selects to output the multiple second addresses and multiple second enable signals to the corresponding column storage sub-blocks.

[0169] The first terminal of the second multiplexer 1040 is connected to all column storage sub-blocks of the first memory, and the second terminal of the second multiplexer 1040 outputs the first read data. The selection signal of the second multiplexer is the second multiplexer selection control signal output by the remapping module. The second multiplexer 1040 selects to output the input data from the column storage sub-block according to the second multiplexer selection control signal; or, the second multiplexer selects to output the input data packet to be written to the corresponding column storage sub-block according to the second multiplexer selection control signal.

[0170] In some exemplary embodiments, applied to a radar system, there are 4 transmitting antennas x = 4, 4 receiving antennas y = 4, bnk_col_siz = 4, bnk_row_siz = 128, col_bnk_num = 8, row_bnk_num = 2, pkg_num = 512, and pkg_siz = 16. col_bnk_num equals 2 × the number of receiving dimensions (2 × the number of receiving antennas), row_bnk_num equals the number of transmitting dimensions / 2 (the number of transmitting antennas / 2), pkg_num equals the number of range dimensions, i.e., divided into pkg_num range cells, and pkg_siz equals the number of banks.

[0171] In some exemplary embodiments, in the corresponding data writing and reading methods, X=2, Y=8, n=4, m=128, N=16, M=512, L=32 bits. A first data packet to be written is 16×32 bits in size. Each first data packet to be written is divided into two second data packets to be written. The data is written to 16 memory blocks in two write clock cycles: in the first write clock cycle, 8×32 bits of data are written to eight sub-blocks within the eight memory blocks corresponding to the eight banks; in the second write clock cycle, the remaining 8×32 bits of data are written to eight sub-blocks within the eight memory blocks corresponding to the other eight banks. The consistency of the data reading scheme can be controlled accordingly, and will not be described in detail here. As can be seen, compared with the write / read method of X=4 and Y=4, this embodiment improves the write / read data bit width and improves the write / read speed. Each write / read clock cycle corresponds to the write enable of 8 column storage sub-blocks. The same second write / read address is used to write / read data in 8 storage sub-blocks.

[0172] The storage controller scheme, data writing method, and data reading scheme provided in this application embodiment can be configured according to the hardware of the radar system (radar chip) and the radar signal data processing needs, and are not limited to the specific values ​​in the examples of this application.

[0173] According to the solution provided in this application, the data to be written in the data write instruction can be written in a distributed manner, and then the required reading method can be selected according to the processing needs after reading, achieving different aggregated reading purposes. Essentially, it is an address remapping scheme determined by configuration information. Applied to radar systems / radar chips, each bank stores the same receive-transmit dimension data, while different receive-transmit dimension data are stored between banks. When switching data dimensions, the required reading method can be selected according to the reading needs, meeting the flexible data access requirements and significantly improving write and read speeds.

[0174] This application also provides a chip, including a processor, which is configured to implement a data writing method as described in any embodiment of this application, and / or to implement a data reading method as described in any embodiment of this application.

[0175] In some exemplary embodiments, the chip is a radar chip.

[0176] In some exemplary embodiments, the chip is a millimeter-wave radar chip.

[0177] In some exemplary embodiments, the chip further includes a radio frequency (RF) module, which includes x receiving antennas and y transmitting antennas.

[0178] This application also provides an electronic device, including a plurality of chips as described in any embodiment of this application;

[0179] Each chip also includes a first memory. At least two chips share the same first memory, or each chip has its own independently configured first memory.

[0180] In some exemplary embodiments, the electronic device includes a radar receiver, as shown in FIG11, comprising a first chip (slave chip) and a second chip (master chip). The slave chip includes four transmit antennas and four receive antennas, and the master chip includes four transmit antennas and four receive antennas. The slave chip also includes an ADC module for converting analog radio frequency signals into digital signals; it also includes a one-dimensional fast Fourier transform (1D-FFT) processing module for performing one-dimensional fast Fourier transform (1D-FFT) processing on all range dimension data corresponding to each receive-transmit dimension, and writing the resulting frequency domain data into 32 storage blocks of the slave chip's first memory according to the method of any embodiment of this application; wherein the first memory includes at least 32 storage blocks, corresponding to storing data of 32 banks.

[0181] The main chip also includes an ADC module for converting analog radio frequency signals into digital signals; it also includes a one-dimensional fast Fourier transform (1D-FFT) processing module for performing one-dimensional fast Fourier transform (1D-FFT) processing on all distance dimension data corresponding to each receive-transmit dimension, and writing the resulting frequency domain data into 32 storage blocks of the main chip's first memory according to the method of any embodiment of this application; wherein the first memory includes at least 64 storage blocks.

[0182] The chip or main chip also includes a synchronization module for synchronizing data from 32 memory blocks in the chip's first memory to another 32 memory blocks in the main chip's first memory.

[0183] In some exemplary embodiments, the main chip also includes a 2D-FFT (Two-Dimensional Fast Fourier Transform) processing module, which performs 2D-FFT processing on the first read data packet read from the first memory of the main chip, and writes the processed data into 64 storage blocks of the first memory of the main chip according to the data writing method of any embodiment of the present application.

[0184] In some exemplary embodiments, the two-dimensional fast Fourier transform processing module is also used to read a first read data packet from 64 storage blocks of the first memory of the main chip according to the data readout method of any embodiment of the present application, and construct a velocity dimension data.

[0185] In some exemplary embodiments, the main chip also includes a Constant False-Alarm Rate (CFAR) module for performing CFAR processing, detecting target signals, and maintaining a constant false alarm rate.

[0186] In some exemplary embodiments, the main chip also includes a Direction of Arrival (DoA) detection module for determining the direction in which the target signal arrives at the radar receiving antenna.

[0187] In some exemplary embodiments, as shown in Figure 12, in the radar receiver, the first chip (cluster chip) and the second chip (main chip) work independently, that is, the two chips work at the same time but not at the same time, and only process the radio frequency signal and the corresponding echo signal transmitted by themselves. That is, they are self-transmitting and self-receiving, and independently process their own 4 transmit and 4 receive data. The first memory of each chip includes 16 storage blocks, corresponding to 16 banks of data.

[0188] In some exemplary embodiments, as shown in FIG13, in the radar receiver, at any given time, only one of the first chip (cluster chip) and the second chip (main chip) transmits radio frequency signals, and one of the two chips receives and processes radio frequency signals; that is, any chip receives the echo signal of the signal transmitted by its own antenna, or receives the echo signal of the signal transmitted by the antenna of the other chip, and the echo signal receiving chip performs 4-receive-4-transmit data processing. The first memory of each chip includes at least 16 storage blocks, corresponding to 16 banks of data.

[0189] It is understood that in some exemplary embodiments, each chip can obtain the transmission signal data or other data from another chip through the inter-chip data link in order to complete related business functions.

[0190] In some exemplary embodiments, as shown in Figure 14, in the radar receiver, the first chip (cluster chip) and the second chip (main chip) transmit radio frequency signals at any given time, and one of the two chips receives and processes radio frequency signals; that is, any chip receives the echo signal of the signal transmitted by its own antenna, and also receives the echo signal of the signal transmitted by the antenna of the other chip. Both chips perform 4 transmit and 4 receive data processing. The first memory of each chip includes at least 32 storage blocks, corresponding to 32 banks of data.

[0191] In some exemplary embodiments, at any given time, one of the first chip (cluster chip) and the second chip (main chip) transmits radio frequency signals, and both chips receive and process radio frequency signals; that is, any chip receives the echo signal of the signal transmitted by its own antenna, or receives the echo signal of the signal transmitted by the antenna of the other chip, and both chips perform 4-to-4 data transmission and reception. The first memory of each chip includes at least 32 memory blocks, corresponding to 32 banks of data.

[0192] In some exemplary embodiments, when there is a need for memory data sharing between chips, the number of storage blocks in the first memory is expanded accordingly to store data from other chips, based on the data processing needs of the radar system.

[0193] In some exemplary embodiments, as shown in Figure 15, in the radar receiver, the first chip (cluster chip) and the second chip (main chip) transmit radio frequency signals at any given time, and the two chips receive and process radio frequency signals; that is, each chip receives the echo signal of the signal transmitted by its own antenna, and also receives the echo signal of the signal transmitted by the antenna of the other chip. Both chips perform 4 transmit and 4 receive data processing. The two chips share a first memory, which includes at least 64 memory blocks, corresponding to 64 banks of data.

[0194] It should be noted that the structural diagrams of the radar system / electronic device in this application only illustrate the relevant components / modules and are not intended to limit the radar system / electronic device to which the solution in this application applies to include only the illustrated components / modules. Based on the above-described electronic device solution including two chips, other implementations including three or more chips can be understood, which will not be described in detail here.

[0195] This application also provides an electronic device, including: one or more processors; and a storage device for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement a data writing method as described in any embodiment of this application, and / or implement a data reading method as described in any embodiment of this application.

[0196] This application also provides a computer-readable storage medium storing a computer program thereon. When the program is executed by a processor, it implements the data writing method as described in any embodiment of this application, and / or implements the data reading method as described in any embodiment of this application.

[0197] Based on the storage space partitioning provided in the embodiments of this application, the data writing and reading scheme provided in the embodiments of this application is essentially an address remapping scheme, which can meet the needs of flexible data writing and reading. Applied to radar systems or radar chips, by combining different configuration information and different reading methods, the needs of data reading in different dimensions can be met, improving data reading efficiency and thus enhancing the chip's data processing performance.

[0198] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM (Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory or other memory technologies, CD-ROM (Compact Disc Read-Only Memory), Digital Video Disc (DVD) or other optical disc storage, cartridges, magnetic tapes, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0199] It's understandable that data access involves more than just the initial data, such as the digital signal obtained after analog-to-digital conversion of radar echo signals. Subsequent processing of the digital signal by corresponding digital signal processing algorithms also involves data access. For example, after 2D-FFT, there's CFAR processing, DOA processing, etc. These processes might be performed by different engines, basebands, or CPUs. In this case, the results of previous processing need to be stored, and subsequent processing will read the stored results to continue processing.

[0200] Taking a vehicle-mounted millimeter-wave radar chip as an example, it transmits signals through a transmitting antenna. These signals are reflected by the target object, forming an echo signal (received signal) that can be received by the receiving antenna. The radar then performs mixing and discrete sampling on the transmitted and echo signals to obtain a signal containing target information. By performing Fast Fourier Transform (FFT) on the range dimension (1D-FFT) and Fast Fourier Transform (FFT) on the velocity dimension (2D-FFT) on the signal to be processed, target detection and measurement of target parameters such as distance, velocity, and angle are achieved. The entire measurement process involves multiple computation modules, such as 1D-FFT and 2D-FFT. After the 1D-FFT operation, the results are divided into multiple dimensions and stored in real-time in the chip's on-chip memory according to a certain pattern. For 2D-FFT, it is usually necessary to continuously extract the results of a certain dimension obtained from the 1D-FFT for calculation. These dimensions of data may reside in a series of discrete address spaces in the on-chip memory, thus affecting the computational efficiency of subsequent modules and consequently the overall performance of the chip system.

[0201] While Direct Memory Access (DMA) allows for the transfer of large amounts of data between different addresses without consuming significant CPU time and impacting the efficiency of other programs, it necessitates a DMA controller in the electronic system. This often requires multiple DMA controllers or multiple DMA controller channels to meet the access needs of various computing modules, significantly increasing hardware requirements and software complexity. Furthermore, traditional DMA controllers offer limited address mapping capabilities, typically adding or removing fixed address intervals based on the source or destination address, thus accommodating relatively simple distributed and clustered access scenarios. Therefore, even with a DMA controller, it struggles to adapt to increasingly complex data transfer scenarios and cannot meet the computational demands of computing modules.

[0202] To meet the computational needs of the aforementioned computing modules while avoiding increased hardware requirements and software complexity, this application also proposes an access control method, specifically applicable to radar chips or processors. In this embodiment, based on the source address in the obtained access request, the corresponding memory address range in the memory module pointed to by the access request is determined. The memory module is divided into non-mapped address ranges and mapped address ranges. If the memory address range is a non-mapped address range, the source address is directly accessed. If the memory address range is a mapped address range, the target address is determined according to the mapping rules corresponding to the source address and the mapped address range, and the target address is accessed. For cases where the source address in the access request belongs to a mapped address range, determining the target address through the mapping rules corresponding to the source address and the mapped address range allows the series of discrete address spaces that the subsequent computing modules need to access to be equivalent to accessing a continuous address space. This enables the transmission of data between different memory addresses in both distributed and clustered types, thereby ensuring efficient on-chip data interaction capabilities and improving the computational efficiency of the subsequent computing modules. In other words, by using the mapping rules corresponding to the mapped address ranges to integrate a series of discrete address spaces, when the operation begins, the source addresses accessed by the subsequent computing modules can all be continuous, without additional hardware and software overhead. This allows for efficient reading of data from discrete address spaces, improving the efficiency of data interaction and enhancing the chip's performance.

[0203] The implementation details of the memory address access control method in this embodiment are described below. The following content is only for the convenience of understanding and is not necessary for implementing this solution.

[0204] The specific flow of the access control method in this embodiment can be shown in Figure 16, including:

[0205] Step S101: Based on the source address in the (obtained) access request, determine the corresponding memory address range in the memory module pointed to by the access request; wherein, the memory module is divided into an unmapped address range and a mapped address range.

[0206] In some exemplary embodiments, the memory address space can be pre-divided into unmapped address ranges and mapped address ranges according to different application requirements. These two address ranges are isolated from each other and do not affect each other. In one example, the memory module can be divided into unmapped address ranges and mapped address ranges in the following way:

[0207] In the memory module, determine the unmapped start address and unmapped end address, and configure the address range between the unmapped start address and unmapped end address as the unmapped address interval. In the memory module, determine the mapped start address and mapped end address, and configure the corresponding mapping rules for the address range between the mapped start address and mapped end address to obtain the mapped address interval. The memory unit module can be the chip's on-chip memory.

[0208] In one example, the addresses contained in the mapped address range and / or unmapped address range can also be a series of addresses with uniform intervals, as shown in Figure 17. A series of source addresses with uniform intervals from the start address 0x0 to the end address 0xN is divided into the unmapped address range, i.e., memory address range 0; a series of source addresses with uniform intervals from the start address 0x100 to the end address 0x10N is divided into the mapped address range, i.e., memory address range 1.

[0209] In some exemplary embodiments, determining the corresponding memory address range in the memory module pointed to by the access request based on the source address in the obtained access request includes: obtaining the source address in the access request initiated by the computing module, and determining the corresponding memory address range in the memory module pointed to by the access request based on the source address, wherein the computing module can be an algorithm engine. In the example shown in Figure 17, if the source address in the access request is an address in access address group 0, such as 0x0 or 0x4, then the memory address range pointed to by the access request can be determined to be memory address range 0; if the source address in the access request is an address in access address group 1, such as 0x100 or 0x104, then the memory address range pointed to by the access request can be determined to be memory address range 1.

[0210] In step S102, it is detected whether the memory address range corresponding to the memory module pointed to by the access request is a non-mapped address range. If it is a non-mapped address range, then proceed to step S103.

[0211] Taking the scenario shown in Figure 17 as an example, if it is determined that the memory address pointed to by the access request belongs to memory address range 0, it means that the memory address range pointed to is a non-mapped address range, and proceed to step S103: directly access the source address in the access request. That is to say, since the addresses in memory address range 0 are outside the configured mapping range, all source addresses initiated in this range will be guaranteed to be consistent with the destination address, that is, accessing the destination address with the same interval from 0x0 to 0xN. This type of access can usually be used by the CPU to execute program code.

[0212] If the detection result in step S102 is: the memory address range corresponding to the memory module pointed to by the access request is detected as a mapped address range, then proceed to step S104: determine the target address according to the mapping rules corresponding to the source address and the mapped address range, and access the target address. For operations accessing the mapped address range, different mapping rules can be configured to map the access to the source address to the target address that needs to be mapped.

[0213] In the example shown in Figure 17, for access requests pointing to memory addresses within memory address range 1, all source addresses originating from within memory address range 1 will be mapped to new target addresses according to the mapping rules. For example, a series of evenly spaced source addresses starting from address 0x100 and ending at address 0x10N will be distributed to target addresses of 0x100, 0x200, ..., 0xN00 after mapping, thus amplifying the range of intervals between these adjacent addresses. This mapping of consecutive addresses into distributed address access can typically be handled by the computing module.

[0214] In one example, the front-end computation module performs a distance-dimensional FFT on the data, while the back-end computation module performs a velocity-dimensional FFT. In other words, after the front-end computation module (e.g., 1D-FFT) completes its calculations, it stores the results in memory in real time. When the back-end computation module (e.g., 2D-FFT) starts, it can continuously transfer data of a specific dimension from the memory to its own computation unit via address mapping. This improves the efficiency of input / output data interaction between the front-end and back-end computation modules in the radar chip, thereby enhancing the radar chip's performance.

[0215] In one example, each address in the mapped address range corresponds to several dimensions. Access requests are used to initiate continuous access to data in one of these dimensions, which is stored discretely within the mapped address range. The preceding computation module writes the processed data into the memory module according to the first arrangement rule of the several dimensions. Access requests are initiated by the following computation module, and these requests also contain the second arrangement rule corresponding to the following computation module. Based on the second arrangement rule in the access request and the first arrangement rule used by the memory module when writing data, a mapping rule corresponding to the mapped address range is constructed. Based on the source address and the constructed mapping rule, the target address is determined and accessed.

[0216] In some exemplary embodiments, a memory address can be divided into multiple partial addresses corresponding to different dimensions. For example, a 32-bit memory address can be divided into four partial addresses, each occupying 8 bits. These four partial addresses correspond to the four dimensions: velocity, distance, Tx (transmitting antenna), and Rx (receiving antenna). As shown in Figure 18, the right side illustrates the arrangement format of the data obtained after processing by the front-end computing module in the memory unit. Taking information with four dimensions as an example, it is distributed in four address spaces: A, B, C, and D. The address combination of the four dimensions corresponds to an actual physical address in the memory unit: addr_mem = {A_addr, B_addr, C_addr, D_addr}, where A_addr corresponds to the velocity dimension, B_addr corresponds to the distance dimension, C_addr corresponds to the transmitting antenna Tx dimension, and D_addr corresponds to the receiving antenna Rx dimension. If a subsequent computation module needs to perform calculations based on the results of a continuous sequence of preceding computation modules in dimension C, then it needs to retrieve data from the memory locations stored in the preceding computation modules according to the address list on the left: addr_raw = {A_addr, B_addr, D_addr, C_addr}. It can be observed that since the left-hand addresses are source addresses initiated consecutively in sequence according to C_addr, while the right-hand addresses are destination addresses arranged consecutively in sequence according to D_addr, the data accessed by the source address is scattered across various memory addresses. Without address mapping, this would inevitably lead to the retrieval of incorrect preceding data, causing errors in the subsequent computation.

[0217] Therefore, in this embodiment, by constructing mapping rules corresponding to the mapped address range, the source address in the access request is mapped to the target address, so as to correctly extract the valid data scattered in addr_mem. For example, in some exemplary embodiments, the arrangement order of each dimension in the first arrangement rule and the second arrangement rule is first determined. By comparing the arrangement order of each dimension in the second arrangement rule and the first arrangement rule, the target dimension whose arrangement order is different from that in the first arrangement rule is determined. Based on the target dimension, the mapping rules corresponding to the mapped address range are constructed, and the target address is determined for access according to the source address and the constructed mapping rules.

[0218] As shown in Figure 18, the front-end calculation module writes the processed data into the memory module according to the arrangement rule {A_addr, B_addr, C_addr, D_addr}, while the back-end calculation module initiates access requests according to the arrangement rule {A_addr, B_addr, D_addr, C_addr}. In this embodiment, the source address access initiated by the back-end calculation module will be mapped to the corresponding target address according to the mapping rule corresponding to the mapped address range. For example, for the first address {Aa-1, B0, D0, C0} starting from addr_raw, the first valid data segment will be obtained from {Aa-1, B0, C0, D0} in addr_mem; for the second address {Aa-1, B0, D0, C1} in addr_raw, the second valid data segment will be obtained from {Aa-1, B0, C1, D0} in addr_mem; and so on, for A in addr_raw... For the 00 addresses {Aa-1,Bb-1,D0,C0}, the A00th valid data segment will be obtained from {Aa-1,Bb-1,C0,D0} in addr_mem; for the A04 addresses {Aa-1,Bb-1,D0,C1} in addr_raw, the A04th valid data segment will be obtained from {Aa-1,Bb-1,C1,D0} in addr_mem, until the subsequent computing module obtains enough data for computation.

[0219] In one example, the memory module includes a first memory module and a second memory module. While the subsequent computing module reads data from the first memory module, the preceding computing module writes processed data into the second memory module. The data read by the subsequent computing module from the first memory module is the same data written by the preceding computing module during the previous data write process. Alternatively, while the subsequent computing module reads data from the second memory module, the preceding computing module writes processed data into the first memory module. The data read by the subsequent computing module from the second memory module is the same data written by the preceding computing module during the previous data write process. For example, the front-end computation module 1D-FFT writes data D1 to memory module 1 at time T0, and data D2 to memory module 2 at time T1. Simultaneously, the back-end computation module 2D-FFT reads the data D1 written by 1D-FFT at time T0 from memory module 1 at time T1. When 1D-FFT writes data D3 to memory module 1 at time T2, 2D-FFT reads the data D2 written by 1D-FFT at time T1 from memory module 2. This ping-pong data read and write operation further improves the computational efficiency of the computation module, thereby enhancing the chip's performance.

[0220] Taking Figure 18 as an example, a memory address `addr_mem` is divided into four sub-addresses {A_addr, B_addr, C_addr, D_addr}, corresponding to the four dimensions of speed, distance, Tx, and Rx, respectively. The front-end calculation module writes the processed data into `addr_mem` according to the arrangement rule {A_addr, B_addr, C_addr, D_addr}. The back-end calculation module initiates access requests according to the arrangement rule {A_addr, B_addr, D_addr, C_addr}. Therefore, the constructed mapping rule is: map the source address {A_addr, B_addr, D_addr, C_addr} to the target address {A_addr, B_addr, C_addr, D_addr}. However, in practical applications, the rules for address mapping are not limited. The number of dimensions corresponding to the elements in the address to be mapped, the range of each dimension, and the starting address and range of the mapping can all be implemented differently depending on the application scenario. This ensures that, in various application scenarios, the series of discrete address spaces accessed by the subsequent computing module can be equivalent to accessing a continuous address space. This enables the transmission of data in both distributed and aggregated types between different memory addresses, ensuring efficient on-chip data interaction and improving the computational efficiency of the subsequent computing module. For example, for a radar with one transmitter and one receiver (Tx), transmitting 1024 chirps per frame, and each chirp being decomposed into 1024 range points, the 20-bit memory address can correspond to two dimensions: 10 bits for velocity and 10 bits for range. For a radar with one transmitter and four receivers (one transmitting antenna and four receiving antennas), transmitting 1024 chirs per frame, with each chirp decomposed into 256 range points, the 20-bit memory address corresponds to three dimensions: 10 bits for velocity, 8 bits for range, and 2 bits for the receiving antenna dimension. For a radar with four transmitters and four receivers (transmitting 256 chirs per frame, each chirp decomposed into 256 range points), the 20-bit memory address corresponds to four dimensions: 8 bits for velocity, 8 bits for range, 2 bits for the receiving antenna dimension, and 2 bits for the transmitting antenna dimension. Since these dimensions can include any combination of the following dimensions: velocity, range, transmitting antenna dimension, and receiving antenna dimension, the radar chip can construct mapping rules corresponding to the address intervals based on actual conditions without additional hardware and software overhead. This allows the subsequent computing modules in the radar chip to efficiently read data from the discrete address space, improving the efficiency of data interaction.

[0221] In some exemplary embodiments, a memory module can be further divided into several unmapped address ranges and several mapped address ranges, with different mapping rules corresponding to different mapped address ranges; or, there can be several memory modules, with different mapping rules corresponding to the mapped address ranges of different memory modules. That is, multiple mapped address regions can be configured by configuring multiple mapping start addresses, the range of mapped addresses, and the mapping rules to be implemented within the mapped addresses. Similarly, multiple unmapped address regions can be configured by configuring multiple unmapped start addresses and the range of unmapped addresses. This embodiment does not limit the number of mapped address ranges and unmapped address ranges.

[0222] In this embodiment, when the source address in the access request belongs to a mapped address range, the target address is determined by the mapping rules corresponding to the source address and the mapped address range. By integrating a series of discrete address spaces using the mapping rules corresponding to the mapped address range, when the operation begins, the source addresses accessed by the subsequent calculation module can all be continuous, without additional hardware and software overhead. This allows for efficient reading of data from discrete address spaces, improving data interaction efficiency and enhancing chip performance.

[0223] The steps of the various methods described above are only for clarity. In practice, they can be combined into one step or some steps can be split into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this patent. Adding insignificant modifications or introducing insignificant designs to the algorithm or process, but without changing the core design of the algorithm and process, are also within the scope of protection of this patent.

[0224] Some embodiments of this application relate to an access control system, as shown in FIG19, including a configuration module M401, an access module M402, a mapping module M403, and at least one memory module M404.

[0225] The configuration module M401 is used to divide the memory address range of at least one memory module M404 into an unmapped address range and a mapped address range, and to configure corresponding mapping rules for the mapped address range.

[0226] The access module M402 is used to send an access request to the mapping module M403, and the access request carries the source address.

[0227] The mapping module M403 is used to determine the memory address range in the memory module M404 to which the access request points based on the source address. If the memory address range corresponding to the access request is a non-mapped address range, it controls the access module M402 to directly access the source address. If the memory address range corresponding to the access request is a mapped address range, it determines the target address according to the mapping rules corresponding to the source address and the mapped address range, and controls the access module M402 to access the determined target address.

[0228] In one example, configuration module M401 is specifically used to obtain the address range of at least one memory module M404, determine the unmapped start address, unmapped end address, mapped start address, and mapped end address within the address range, configure the address range between the unmapped start address and the unmapped end address as the unmapped address interval, and configure the corresponding mapping rules for the address range between the mapped start address and the mapped end address to obtain the mapped address interval. Each address in the mapped address interval corresponds to several dimensions. An access request is used to initiate continuous access to data in one of the several dimensions, and the data in that dimension is discretely stored in the mapped address interval. The several dimensions include any combination of the following dimensions: velocity dimension, distance dimension, transmit antenna dimension, and receive antenna dimension.

[0229] Memory module M404 receives processed data written by the preceding computation module (e.g., 1D-FFT) according to a first arrangement rule across several dimensions. The access request initiated by access module M402 also carries the second arrangement rule corresponding to the subsequent computation module (e.g., 2D-FFT). Configuration module M401 configures the corresponding mapping rule for the mapping address range by: constructing the mapping rule corresponding to the mapping address range based on the second arrangement rule and the first arrangement rule in the access request. For example, by comparing the arrangement order of each dimension in the second and first arrangement rules, the first target dimension in the second arrangement rule with a different arrangement order from the first arrangement rule is determined; based on the target dimension, the mapping rule corresponding to the mapping address range is constructed. When the memory address range corresponding to the access request is a mapping address range, mapping module M403 determines the target address based on the source address and the mapping rule corresponding to the mapping address range, and controls access module M402 to access the determined target address. Access module M402 can be a central processing unit or a baseband computation module.

[0230] In some exemplary embodiments, when the source address in the access request belongs to a mapped address range, the target address is determined by the mapping rules corresponding to the source address and the mapped address range. By integrating a series of discrete address spaces using the mapping rules corresponding to the mapped address range, when the operation begins, the source addresses accessed by the subsequent computing module can all be continuous, without additional hardware and software overhead. This allows for efficient reading of data from discrete address spaces, improving the efficiency of data interaction and enhancing the chip's performance.

[0231] In one example, a memory module is specifically divided into several unmapped address ranges and several mapped address ranges, with different mapping rules corresponding to different mapped address ranges. In another example, there are several memory modules, and the mapping rules corresponding to the mapped address ranges of different memory modules are different. In practical applications, there are no restrictions on the address mapping rules. That is, the number of dimensions corresponding to the elements in the address to be mapped, the range size of each dimension, the starting address of the mapping, and the range size can all be implemented differently depending on the application scenario of the algorithm. This ensures that, under various application scenarios, the series of discrete address spaces that the subsequent computing module needs to access can be equivalent to accessing a continuous address space, realizing the transmission of data in both distributed and clustered types between different memory addresses. This ensures efficient on-chip data interaction capabilities and improves the computing efficiency of the subsequent computing module.

[0232] In some exemplary embodiments, the memory module M404 may further include a first memory module and a second memory module. While the access module 402 reads data from the first memory module, the preceding computing module writes the processed data to the second memory module. The data read from the first memory module is the same data written to the first memory module by the preceding computing module during a previous data write operation. Alternatively, while the access module M402 reads data from the second memory module, the preceding computing module writes the processed data to the first memory module. The data read from the second memory module is the same data written to the second memory module by the preceding computing module during a previous data write operation. This ping-pong data read and write operation further improves the computational efficiency of the computing module, thereby enhancing the chip's performance.

[0233] It is worth mentioning that all modules involved in this embodiment are logical modules. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. Furthermore, to highlight the innovative aspects of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed in this application; however, this does not mean that other units are absent in this embodiment.

[0234] Another embodiment of this application relates to a computer-readable storage medium storing a computer program. When executed by a processor, the computer program implements the method embodiments described above.

[0235] That is, those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by a program instructing related hardware. This program is stored in a storage medium and includes several instructions to cause a device (which may be a microcontroller, chip, etc.) or processor to execute all or part of the steps of the methods described in the various embodiments of this application (such as interference detection methods and / or constant false alarm rate detection methods, etc.). The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory, random access memory, magnetic disks, or optical disks.

[0236] Another embodiment of this application relates to an integrated circuit. A schematic diagram of the integrated circuit in this embodiment is shown in Figure 20. The integrated circuit may include: a radio frequency (RF) module M501, an analog signal processing module M502, and a processing module M503. The RF module M501 is used to generate RF transmit signals and receive RF receive signals; the analog signal processing module M502 is used to down-convert the RF receive signals to obtain intermediate frequency (IF) signals; and the processing module M503 is used to perform access control on the IF signals based on the access control method in the above method embodiment. In some exemplary embodiments, the processing module M503 determines the corresponding memory address range in the memory module pointed to by the access request based on the source address in the obtained access request. The memory module is divided into non-mapped address ranges and mapped address ranges. If the pointed-to memory address range is a non-mapped address range, the source address is directly accessed; if the pointed-to memory address range is a mapped address range, the target address is determined according to the mapping rules corresponding to the source address and the mapped address range, and the determined target address is accessed.

[0237] In some exemplary embodiments, the integrated circuit described above can be a millimeter-wave radar chip or a lidar chip (such as an FMCW (Frequency Modulated Continuous Wave) lidar chip) to acquire information such as the target's distance, angle, velocity, shape, size, surface roughness, and dielectric properties. In some exemplary embodiments, the integrated circuit can be an antenna-in-package (AiP) chip structure, an antenna-on-package (AoP) chip structure, or an antenna-on-chip (AoC) chip structure, etc.

[0238] By utilizing the mapping rules corresponding to the mapped address ranges, a series of discrete address spaces in the radar chip are integrated. When the operation begins, the source addresses accessed by the subsequent calculation modules (such as 2D-FFT) can all be continuous, without additional hardware and software overhead. This allows for efficient reading of data from discrete address spaces, improving the data interaction efficiency between the preceding calculation modules (such as 1D-FFT) and the subsequent calculation modules (such as 2D-FFT), and enhancing the working performance of the radar chip.

[0239] Another embodiment of this application relates to a wireless device, which includes a carrier, an integrated circuit as described above disposed on the carrier, and an antenna for transmitting and receiving radio signals disposed on the carrier. The antenna can be integrated with the integrated circuit as a single device disposed on the carrier (i.e., the antenna can be an antenna in an AiP or AoC structure). Alternatively, the integrated circuit and the antenna can be two separate components, connected to form a system-on-chip (SoC) structure. The carrier can be a printed circuit board (PCB), such as a development board, data acquisition board, or the motherboard of a device, and the first transmission line can be a PCB trace.

[0240] In some embodiments, this application also provides a terminal device, which may include a device body and a wireless device disposed on the device body as described in the above embodiments; wherein the wireless device can be used to achieve target detection.

[0241] Based on the above embodiments, in some embodiments of this application, the wireless device may be disposed outside the device body or inside the device body. In other optional embodiments of this application, the wireless device may be partially disposed inside the device body and partially disposed outside the device body. This application does not limit the scope of the embodiments and may be determined according to the specific circumstances.

[0242] In some embodiments, the aforementioned device body can be a component or product applied in fields such as smart cities, smart homes, transportation, smart homes, consumer electronics, security monitoring, industrial automation, in-cabin detection (such as smart cockpits), medical devices, and healthcare. For example, the device body can be intelligent transportation equipment (such as automobiles, bicycles, motorcycles, ships, subways, trains, etc.), security equipment (such as cameras), liquid level / flow rate detection equipment, smart wearable devices (such as wristbands, glasses, etc.), smart home devices (such as robot vacuum cleaners, door locks, televisions, air conditioners, smart lights, etc.), various communication devices (such as mobile phones, tablets, etc.), as well as devices such as barriers, intelligent traffic lights, intelligent signs, traffic cameras, and various industrial robotic arms (or robots). It can also be various instruments for detecting vital signs parameters and various devices equipped with such instruments, such as in-cabin vital sign detection in automobiles, indoor personnel monitoring, smart medical devices, and consumer electronic devices.

[0243] It should be noted that wireless devices can detect targets by transmitting and receiving radio signals, thereby providing the device itself with target information and assisting or even controlling the operation of the device.

[0244] For example, when the aforementioned equipment is applied to an Advanced Driving Assistance System (ADAS), wireless devices (such as millimeter-wave radar and lidar) used as vehicle sensors can assist the ADAS system in achieving applications such as adaptive cruise control, Autonomous Emergency Braking (AEB), Blind Spot Detection (BSD), Lane Change Assist (LCA), Rear Cross Traffic Alert (RCTA), parking assistance, rear vehicle warning, collision avoidance, and pedestrian detection. It can also be applied to applications such as collision avoidance when a car opens its doors.

[0245] Therefore, the access control method, system, computer-readable storage medium, and terminal device provided in this application can improve the efficiency of data interaction in different address spaces, thereby improving the computational efficiency of the computing module. Specifically, the memory module is pre-divided into unmapped address ranges and mapped address ranges, and it is identified whether the memory address range pointed to by the access request belongs to a mapped address range. If the source address in the access request belongs to a mapped address range, the target address is determined through the mapping rules corresponding to the source address and the mapped address range. This can transform the series of discrete address spaces that the subsequent computing module needs to access into an equivalent access to a continuous address space, enabling the transmission of data in both distributed and aggregated types between different memory addresses, thereby ensuring efficient on-chip data interaction capabilities and improving the computational efficiency of the subsequent computing module.

[0246] It is understood that, based on the descriptions of the foregoing embodiments, it is easy to see that the data writing method, data reading method, and access control method provided in this application can be applied in conjunction with each other in the processing of an echo signal. For example, in some exemplary embodiments, a signal processing method can be provided, including: writing echo digital signal data into memory according to the data writing method described in any of the preceding embodiments; reading the written echo digital signal data from memory according to the data reading method described in any of the preceding embodiments; and processing the read echo digital signal data according to a multi-level calculation in a preset digital signal processing flow, wherein, after each level of calculation in the multi-level calculation is completed, the calculated result is written into memory, and before the s-th level calculation in the multi-level calculation, the memory is accessed according to the access control method described in any of the preceding embodiments to read data for the s-th level calculation, 1 < s ≤ t, where t is the total number of levels of calculation included in the multi-level calculation. The data writing method, data reading method, and access control method have been described in the foregoing embodiments, and will not be repeated here.

[0247] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0248] The embodiments described above are merely preferred embodiments of this application and the technical principles employed. While the descriptions are specific and detailed, they should not be construed as limiting the scope of the invention patent. Those skilled in the art can make various obvious changes, readjustments, and substitutions without departing from the protection scope of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments. Many other equivalent embodiments may be included without departing from the concept of this application. In practical applications, various changes can be made in form and detail without departing from the spirit and scope of this application.

Claims

1. A data writing method, comprising: According to the write configuration information, the first data packet to be written is written into X×Y storage blocks on the first memory; The first memory includes at least N×M storage sub-blocks, and each storage block includes at least n×m storage sub-blocks; N≥n, M≥m, N, n, Y, M, m, X are all integers greater than 0.

2. The data writing method according to claim 1, wherein, The first data packet to be written is divided into Xi second data packets to be written, and each second data packet to be written is divided into Yj third data packets to be written, where Xi×Yj=X×Y, and Yj and Xi are both integers greater than 0; The step of writing the first data packet to be written into X×Y storage blocks on the first memory includes: The Xi×Yj third data to be written included in the first data packet to be written are respectively written into the X×Y storage blocks.

3. The data writing method according to claim 2, wherein, The step of writing the first data packet to be written into X×Y storage blocks on the first memory includes: For each of the Xi second data packets to be written, perform the following steps to write the data: Write the Yj third data to be written corresponding to the second data packet to be written into the Yj storage sub-blocks in the same row of the Yj column storage sub-blocks respectively.

4. The data writing method according to any one of claims 1 to 3, wherein, The method is applied to a radar system, which includes x receiving antennas and y transmitting antennas; X×Y=x×y, where x and y are both integers greater than 0; The first data packet to be written includes signal data of the radar system in one range dimension of a chirp.

5. The data writing method according to claim 4, wherein, The radar system includes U range dimensions; The method further includes writing U first data packets to be written generated by a chirp into the first memory respectively.

6. The data writing method according to claim 4 or 5, wherein, A dataset is formed by the signal data of a receiving antenna and a transmitting antenna across the entire range of a chirp. The data of one dataset is stored in one of the storage blocks in the first memory.

7. The data writing method according to any one of claims 4 to 6, wherein, M = X × m, N = Y × n.

8. A data reading method, comprising: According to the read mode marking, data is read from multiple storage sub-blocks in the first memory to form a first read data packet; The first memory includes at least N×M storage sub-blocks, where N and M are both integers greater than 0; The first read data packet includes data written according to the data writing method as described in any one of claims 1 to 7.

9. The data reading method according to claim 8, wherein, The readout mode marker indicates the first readout mode; The plurality of storage sub-blocks are at least n×m storage sub-blocks included in any one of the X×Y storage blocks in the first memory.

10. The data reading method according to claim 9, wherein, The step of reading data from multiple storage sub-blocks on the first memory includes: The data is read in m separate steps, each step of which involves performing the following steps: Read data from n storage sub-blocks in the same row of n column storage sub-blocks in any one of the storage blocks.

11. The data readout method according to claim 9 or 10, wherein, The method is applied to radar systems; The method further includes performing a one-dimensional fast Fourier transform based on the first read data packet.

12. The data reading method according to claim 8, wherein, The readout mode marker indicates the second readout mode; The plurality of storage sub-blocks are one storage sub-block from each of the X×Y storage blocks in the first memory; Each storage block consists of at least n×m storage sub-blocks.

13. The data reading method according to claim 12, wherein, The step of reading data from multiple storage sub-blocks on the first memory includes: The data is read in two separate steps, each of which involves performing the following steps: Data is read from the Yj storage sub-blocks in the same row of the Yj column storage sub-blocks included in the X×Y storage blocks, where Xi×Yj=X×Y, and Yj and Xi are all integers greater than 0.

14. The data readout method according to claim 12 or 13, wherein, The method is applied to radar systems; The method further includes: constructing a velocity dimension based on the first read data packet.

15. A data writing method, comprising: According to the data writing method as described in any one of claims 1-7, the first chip sequentially writes a first group of multiple first data packets to be written into X1×Y1 storage blocks on the first memory of the first chip. According to the data writing method as described in any one of claims 1-7, the second chip sequentially writes a second group of multiple first data packets to be written into X2×Y2 storage blocks on the first memory of the second chip. All or part of the data in the X1×Y1 storage blocks of the first memory of the first chip is written into other storage blocks on the second chip besides the X2×Y2 storage blocks.

16. An electronic device comprising: One or more processors; Storage device for storing one or more programs. When the one or more programs are executed by the one or more processors, the one or more processors implement the data writing method as described in any one of claims 1-7 and 15, and / or implement the data reading method as described in any one of claims 8-14.

17. A chip including a processor configured to implement the data writing method as claimed in any one of claims 1-7 and 15, and / or to implement the data reading method as claimed in any one of claims 8-14.

18. An electronic device comprising a plurality of chips as described in claim 17; in, Each of the chips also includes a first memory, and at least two of the first memories of the chips share the same memory, or the first memory of each of the chips is set independently.

19. A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the data writing method as described in any one of claims 1-7 and 15, and / or implements the data reading method as described in any one of claims 8-14.

20. An access control method, comprising: Based on the source address in the obtained access request, the corresponding memory address range in the memory module pointed to by the access request is determined; wherein, the memory module is divided into a non-mapped address range and a mapped address range; If the memory address range is the non-mapped address range, then the source address is accessed directly; If the memory address range is the mapped address range, then the target address is determined according to the mapping rules corresponding to the source address and the mapped address range, and the target address is accessed.

21. The access control method according to claim 20, wherein, The memory module is divided into unmapped address ranges and mapped address ranges, including: In the memory module, a non-mapped start address and a non-mapped end address are determined, and the address range between the non-mapped start address and the non-mapped end address is configured as the non-mapped address interval. In the memory module, the start address and end address of the mapping are determined, and corresponding mapping rules are configured for the address range between the start address and the end address to obtain the mapping address range.

22. The access control method according to claim 20 or 21, wherein, Each address in the mapped address range corresponds to several dimensions; the access request is used to initiate continuous access to the data of one of the several dimensions, and the data of the one dimension is discretely stored in the mapped address range.

23. The access control method according to claim 22, wherein, The front-end computing module writes the processed data into the memory module according to the first arrangement rule of the aforementioned several dimensions. The access request is initiated by the back-end computing module, and the access request also includes the second arrangement rule corresponding to the back-end computing module. The step of determining the target address based on the mapping rules corresponding to the source address and the mapped address range, and accessing the target address, includes: Based on the second arrangement rule in the access request and the first arrangement rule used when the memory module writes data, construct the mapping rule corresponding to the mapping address range; Based on the source address and the constructed mapping rules, the target address is determined and accessed.

24. The access control method according to claim 23, wherein, The step of constructing the mapping rule corresponding to the mapping address range based on the second arrangement rule in the access request and the first arrangement rule used when the memory module writes data includes: By comparing the arrangement order of each dimension in the second arrangement rule and the first arrangement rule, the target dimension whose first arrangement order is different from that in the first arrangement rule is determined. Based on the target dimension, construct the mapping rules corresponding to the mapping address range.

25. The access control method according to claim 23 or 24, wherein, The front-end computation module is used to perform a distance-dimensional FFT on the data; the back-end computation module is used to perform a velocity-dimensional FFT on the data.

26. The access control method according to any one of claims 22-25, wherein, The aforementioned dimensions include any combination of the following dimensions: Velocity dimension, distance dimension, transmitting antenna dimension, receiving antenna dimension.

27. The access control method according to any one of claims 22-26, wherein, The memory module includes a first memory module and a second memory module. While the subsequent computing module reads data from the first memory module, the preceding computing module writes the processed data into the second memory module. The data read by the subsequent computing module from the first memory module is the data written to the first memory module by the preceding computing module during the previous data writing process. Alternatively, while the subsequent computing module reads data from the second memory module, the preceding computing module writes the processed data into the first memory module; wherein the data read by the subsequent computing module from the second memory module is the data written to the second memory module by the preceding computing module during the previous data writing process.

28. The access control method according to any one of claims 20-27, wherein, The memory module is specifically divided into several unmapped address ranges and several mapped address ranges, and the mapping rules for different mapped address ranges are different.

29. The access control method according to any one of claims 20-28, wherein, There are several memory modules, and the mapping rules corresponding to the mapping address ranges of different memory modules are different.

30. An access control system, the system comprising a configuration module, an access module, a mapping module, and at least one memory module; The configuration module is used to divide the memory address range of the at least one memory module into a non-mapped address range and a mapped address range, and configure corresponding mapping rules for the mapped address range; The access module is used to send an access request to the mapping module, and the access request carries the source address; The mapping module is used to determine the memory address range corresponding to the memory module pointed to by the access request based on the source address. If the memory address range corresponding to the access request is the non-mapped address range, the module is controlled to directly access the source address. The mapping module is further configured to, when the memory address range corresponding to the access request is the mapping address range, determine the target address according to the mapping rules corresponding to the source address and the mapping address range, and control the access module to access the target address.

31. The access control system according to claim 30, wherein, Each address in the mapped address range corresponds to several dimensions; the access request is used to initiate continuous access to the data of one of the several dimensions, and the data of the one dimension is discretely stored in the mapped address range.

32. The access control system according to claim 30 or 31, wherein, The memory module is also used to receive processed data written by the front-end computing module according to the first arrangement rule of the several dimensions; The access request also carries a second arrangement rule corresponding to the subsequent calculation module. The configuration module configures the corresponding mapping rule for the mapping address range by: constructing the mapping rule corresponding to the mapping address range according to the second arrangement rule and the first arrangement rule in the access request.

33. The access control system according to any one of claims 30-32, wherein, The access module is a central processing unit or a baseband computing module.

34. A computer-readable storage medium comprising a computer program or instructions which, when executed by a processor, implement the access control method of any one of claims 20 to 29.

35. An integrated circuit, comprising: The radio frequency module is used to generate radio frequency transmission signals and receive radio frequency reception signals; An analog signal processing module is used to down-frequency the received radio frequency signal to obtain an intermediate frequency signal; as well as A processing module is configured to perform access control on the intermediate frequency signal based on the access control method as described in any one of claims 20-29.

36. The integrated circuit according to claim 35, wherein the integrated circuit is a radar chip.

37. A terminal device, comprising: Equipment body; A wireless device disposed on the device body, the wireless device being used for target detection; The wireless device includes: a carrier; The integrated circuit as described in claim 35 is disposed on the carrier; An antenna, mounted on the carrier, is used to transmit and receive radio signals.

38. A signal processing method, comprising: According to the data writing method as described in any one of claims 1-7, echo digital signal data is written into memory; The echo digital signal data written to memory is read from the data readout method according to any one of claims 8-14; The read echo digital signal data is processed according to the multi-level calculation in the preset digital signal processing flow. After each level of calculation is completed, the result is written into memory. Before the s-th level calculation in the multi-level calculation, the memory is accessed according to the access control method as described in any one of claims 20-29 to read data for the s-th level calculation, where 1 < s ≤ t, and t is the total number of levels of calculation included in the multi-level calculation.

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