Array substrate and electronic-paper display panel

Abstract

An array substrate (300) and an electronic-paper display panel (10). The array substrate (300) comprises: data lines (463) and scan lines (421), which are vertically and horizontally arranged to define a plurality of pixel regions; and a pixel electrode layer (500), which comprises a plurality of pixel electrodes (510), wherein the pixel electrodes (510) correspond to the pixel regions on a one-to-one basis. The array substrate (300) further comprises a common electrode (422), which is located on a first metal layer (420) or a second metal layer (460); and a passivation layer (480), which is provided with pixel electrode trenches (490), wherein the pixel electrode trenches (490) are located between the pixel electrodes (510) and the common electrode (422), the pixel electrodes (510) are at least partially located in the pixel electrode trenches (490), the pixel electrode trenches (490) correspond to the pixel regions on a one-to-one basis, the passivation layer (480) is further provided with first channels (610), the first channels (610) enable the pixel electrode trenches (490) in different pixel regions to be in communication, and the depths of the first channels (610) are equal to the depths of the pixel electrode trenches (490) so as to expel bubbles from the pixel electrode trenches (490). By means of the design, bubbles can be prevented from remaining in the pixel electrode trenches (490), thereby improving the display uniformity of the electronic-paper display panel (10).

Description

Array substrate and electronic paper display panel Technical Field

[0001] This application relates to the field of display technology, and more particularly to an array substrate and an electronic paper display panel. Background Technology

[0002] With the development of digital technology, more and more display devices are entering people's lives, such as electronic paper display panels. Electronic paper display panels work by uniformly dispersing electrophoretic particles in a medium solution with a certain viscosity. An electric field causes the electrophoretic particles to move electrophoretically, producing color display. Because the displayed color is achieved by colored particles reflecting external light, the display has the effect of ordinary paper, winning the favor of readers. Furthermore, due to the bistable effect, electronic paper display panels can still display content even when the power is off, offering significant energy savings compared to other types of display devices.

[0003] However, the storage capacity of the capacitor can be improved by placing the pixel electrode in the pixel electrode slot. However, this method causes air bubbles to remain at the position of the pixel electrode slot when the electronic paper film is bonded to the array substrate, which leads to a decrease in the display uniformity of the electronic paper display panel. Summary of the Invention

[0004] The purpose of this application is to provide an array substrate and an electronic paper display panel to prevent air bubbles from remaining in the pixel electrode slots and improve the display uniformity of the electronic paper display panel.

[0005] This application discloses an array substrate for use in an electronic paper display panel. The array substrate includes a substrate and a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode layer sequentially disposed on the substrate. The array substrate also includes data lines and scan lines, which are located in the first metal layer or the second metal layer and are disposed in different layers. The data lines and the scan lines are arranged in a longitudinal and transverse manner to define multiple pixel regions. The pixel electrode layer includes multiple pixel electrodes, each pixel electrode corresponding to a pixel region. The array substrate also includes a common electrode, which is located in the first metal layer or the second metal layer.

[0006] The passivation layer has pixel electrode grooves located between the pixel electrode and the common electrode, with at least a portion of the pixel electrode located within the pixel electrode grooves. Each pixel electrode groove corresponds to a pixel region. The passivation layer also has a first channel connecting the pixel electrode grooves in different pixel regions. The depth of the first channel is equal to the depth of the pixel electrode groove, and it is used to expel air bubbles from the pixel electrode grooves.

[0007] Optionally, the scan line is located in the first metal layer, the data line is located in the second metal layer, the length direction of the data line is the first direction, the length direction of the first channel is the same as the first direction, and the first channel only connects the pixel electrode slots in the first direction.

[0008] Optionally, the array substrate further includes a drain electrode located in the second metal layer, and the array substrate further includes a connection hole that penetrates the passivation layer and the second insulating layer, through which the pixel electrode is connected to the drain electrode;

[0009] The array substrate further includes a second channel that connects adjacent adapter holes. The length direction of the second channel is the same as the first direction, and the second channel only connects the adapter holes in the first direction. The depth of the second channel is the same as the depth of the adapter holes.

[0010] Optionally, the second direction is along the length of the scan line, and the width of the first channel along the second direction is the same as the width of the pixel electrode groove along the second direction; among the two sidewalls of the first channel along the second direction and the two sidewalls of the pixel electrode groove along the second direction, the sidewall of the first channel near the same side of the data line is flush with the sidewall of the pixel electrode groove.

[0011] The array substrate further includes a drain electrode located in the second metal layer. The array substrate also includes a transition hole that penetrates the passivation layer and the second insulating layer. The pixel electrode is connected to the drain electrode through the transition hole. Each transition hole in each pixel region corresponds to a pixel electrode slot. The array substrate also includes a third channel that connects the transition hole and the pixel electrode slot. The length direction of the third channel forms an acute angle with the first direction.

[0012] Optionally, the scan line is located in the first metal layer, the data line is located in the second metal layer, the direction along the scan line is the second direction, the length direction of the first channel is the same as the second direction, and the first channel only connects the pixel electrode slots in the second direction.

[0013] Optionally, the first channel is composed of at least two first sub-channels, and a gap is provided between each first sub-channel, the first sub-channels being connected to the pixel electrode groove in the second direction.

[0014] Optionally, along the length direction of the data line as the first direction, the first sub-channel is sequentially divided into a connected first part, a second part, and a third part along the second direction. The width of the first part decreases sequentially along the second direction, and the width of the third part increases sequentially along the second direction. The width of the first part near the second part along the first direction is the same as the width of the second part along the first direction, and the width of the third part near the second part along the first direction is the same as the width of the second part along the first direction.

[0015] The second part is projected onto the substrate, covering the portion of the data line projected onto the substrate.

[0016] Optionally, the direction along the length of the data line is the first direction, and the direction along the length of the scan line is the second direction;

[0017] The pixel electrode groove includes a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a fifth sidewall connected in sequence. The first sidewall, the third sidewall, and the data line are parallel. The second sidewall and the fifth sidewall are parallel to the scan line. The length of the third sidewall along the first direction is less than the length of the first sidewall along the first direction, and the angle between the fourth sidewall and the third sidewall is an obtuse angle.

[0018] The first channel connects the second sidewall and the fifth sidewall of the two pixel electrode slots in the first direction, respectively, and the length of the fifth sidewall along the second direction is equal to the width of the first channel along the second direction.

[0019] Optionally, the width d of the first channel is ≤10um.

[0020] This application also discloses an electronic paper display panel, which includes an electronic paper film and an array substrate, wherein the electronic paper film is bonded to the array substrate.

[0021] Compared to existing solutions, this application improves the storage capacity of the capacitor by setting pixel electrode slots and ensuring that the pixel electrodes are at least partially located within the pixel electrode slots. This shortens the distance between the pixel electrodes and the common electrode. Furthermore, by setting a first channel to connect the pixel electrode slots, air bubbles that were originally hidden in the pixel electrode slots can be discharged from the electronic paper display panel along the first channel during the rolling of the electronic paper film, preventing air bubbles from remaining in the pixel electrode slots and thus improving the display uniformity of the electronic paper display panel. Attached Figure Description

[0022] The accompanying drawings, which form part of the specification, are used to provide a further understanding of the embodiments of this application and illustrate the implementation methods of this application, together with the textual description, to explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any creative effort. In the drawings:

[0023] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of this application;

[0024] Figure 2 is a schematic cross-sectional view of an array substrate according to the first embodiment of this application;

[0025] Figure 3 is a schematic planar diagram of an array substrate according to the first embodiment of this application;

[0026] Figure 4 is a schematic cross-section of a common electrode located in the second metal layer according to the first embodiment of this application;

[0027] Figure 5 is a partially enlarged schematic diagram of an adapter hole according to the first embodiment of this application;

[0028] Figure 6 is a schematic diagram of a pixel electrode groove according to the first embodiment of this application;

[0029] Figure 7 is a schematic diagram of a plan view of a first channel arranged laterally according to a second embodiment of this application;

[0030] Figure 8 is a partially enlarged schematic diagram of a first channel according to a second embodiment of this application;

[0031] Figure 9 is a schematic plan view of a first channel according to a third embodiment of this application;

[0032] Figure 10 is a schematic plan view of a first channel according to a fourth embodiment of this application;

[0033] Figure 11 is a schematic diagram of an array substrate according to the fifth embodiment of this application;

[0034] Figure 12 is a schematic diagram of an opposing substrate according to an embodiment of this application.

[0035] Among them, 10 is an electronic paper display panel; 100 is an opposing substrate; 110 is an opposing substrate; 120 is a common electrode; 121 is a first common electrode; 123 is a second common electrode; 200 is an electronic paper film; 300 is an array substrate; 410 is a substrate; 420 is a first metal layer; 421 is a scan line; 422 is a common electrode; 423 is a gate; 430 is a first insulating layer; 450 is a semiconductor layer; 460 is a second metal layer; 461 is a source electrode; 462 is a drain electrode; 463 is a data line; 464 is an electrode plate; 470 is a second insulating layer; and 480 is a passivation layer. ; 490, Pixel electrode groove; 491, First sidewall; 492, Second sidewall; 493, Third sidewall; 494, Fourth sidewall; 495, Fifth sidewall; 500, Pixel electrode layer; 510, Pixel electrode; 610, First channel; 611, First sub-channel; 612, First portion; 613, Second portion; 614, Third portion; 620, Second channel; 630, Third channel; 640, Fourth channel; 700, Adapter hole. Detailed Implementation

[0036] It should be understood that the terminology, specific structural and functional details used herein are merely for describing particular embodiments and are representative. However, this application may be implemented in many alternative forms and should not be construed as being limited to the embodiments set forth herein.

[0037] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, unless otherwise stated, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature; "multiple" means two or more. The term "comprising" and any variations thereof mean non-exclusive inclusion, where one or more other features, integers, steps, operations, units, components, and / or combinations thereof may be present or added.

[0038] In addition, terms such as “center,” “horizontal,” “up,” “down,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inner,” and “outer” that indicate orientation or positional relationship are based on the orientation or relative positional relationship shown in the accompanying drawings. They are only for the purpose of simplifying the description of this application and do not indicate that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0039] Furthermore, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium, or internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0040] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments.

[0041] Figure 1 is a schematic diagram of an electronic paper display panel according to an embodiment of this application. As shown in Figure 1, this application discloses a display panel. The electronic paper display panel 10 includes an electronic paper film 200 and an array substrate 300. The electronic paper film 200 is bonded to the array substrate 300. The electronic paper film 200 includes an electrowetting type electronic paper film 200 or an electrophoretic particle type electronic paper film 200. Taking the electrophoretic particle type electronic paper film 200 as an example, the array substrate 300 drives the electrophoretic particles in the electronic paper film 200 to move, so as to reflect ambient light for displaying the image.

[0042] The electronic paper display panel 10 further includes a counter substrate 100, which is disposed opposite to the array substrate 300. The counter substrate 100 includes a counter substrate 110 and a common electrode 120. The common electrode 120 is disposed on the counter substrate 110. The electric field formed between the common electrode 120 and the pixel electrode 510 on the array substrate 300 drives the electrophoretic particles in the electronic paper film 200 to move.

[0043] This application also discloses an array substrate 300, which can be used in the electronic paper display panel 10 described above. Regarding the array substrate 300, this application provides the following design, which is specifically described through several embodiments:

[0044] Example 1:

[0045] Figure 2 is a schematic cross-sectional view of an array substrate according to the first embodiment of this application, and Figure 3 is a schematic planar view of an array substrate according to the first embodiment of this application. As shown in Figures 2-3, this embodiment discloses an array substrate 300 for use in the above-mentioned electronic paper display panel 10. The array substrate 300 includes a substrate 410 and a first metal layer 420, a first insulating layer 430, a second metal layer 460, a second insulating layer 470, a passivation layer 480, and a pixel electrode layer 500 sequentially disposed on the substrate 410.

[0046] The array substrate 300 further includes data lines 463 and scan lines 421. The data lines 463 and scan lines 421 are located in the first metal layer 420 or the second metal layer 460 and are disposed in different layers. The data lines 463 and scan lines 421 are arranged in a longitudinal and transverse manner to define multiple pixel regions. The pixel electrode layer 500 includes multiple pixel electrodes 510, each pixel electrode 510 corresponding to a pixel region. The array substrate 300 also includes a common electrode 422. The common electrode 422 is located in the first metal layer 420 or the second metal layer 460. The common electrode 422 is used to form a storage capacitor with the pixel electrodes 510 to maintain the electric field between the pixel electrodes 510 and the common electrode 120.

[0047] The passivation layer 480 has a pixel electrode groove 490, which is located between the pixel electrode 510 and the common electrode 422. The pixel electrode 510 is at least partially located within the pixel electrode groove 490. The pixel electrode groove 490 corresponds one-to-one with the pixel region. The passivation layer 480 also has a first channel 610, which connects the pixel electrode grooves 490 in different pixel regions. The depth of the first channel 610 is equal to the depth of the pixel electrode groove 490, and it is used to discharge air bubbles in the pixel electrode groove 490.

[0048] The array substrate 300 includes an active switch, which comprises a gate 423, a semiconductor layer 450, a source 461, and a drain 462. The active switch includes a top-gate structure and a bottom-gate structure. When the active switch is a top-gate structure, the gate 423 is located in the second metal layer 460, the scan line 421 is located in the second metal layer 460, the source 461 and drain 462 are located in the first metal layer 420, and the data line 463 is located in the first metal layer 420. The semiconductor layer 450... Located between the substrate 410 and the first metal layer 420; when the active switch is a bottom-gate structure, the gate 423 is located in the first metal layer 420, the scan line 421 is located in the first metal layer 420, the source 461 and the drain 462 are located in the second metal layer 460, the data line 463 is located in the second metal layer 460, and the semiconductor layer 450 is located between the first insulating layer 430 and the second metal layer 460; this application uses the active switch as a bottom-gate structure as an example for explanation and illustration.

[0049] This application improves the storage capacity of the capacitor by setting a pixel electrode groove 490 and making the pixel electrode 510 at least partially located within the pixel electrode groove 490. This shortens the distance between the pixel electrode 510 and the common electrode 422. However, this also causes air bubbles to remain at the position corresponding to the pixel electrode groove 490 when the electronic paper film 200 is attached to the array substrate 300. Since the air bubbles are located within the pixel electrode groove 490, they cannot be expelled by rolling the electronic paper film 200. Moreover, the presence of air bubbles will cause a change in the dielectric constant between the pixel electrode 510 and the common electrode 120, resulting in an uneven electric field between the pixel electrode 510 and the common electrode 120, which will lead to display problems.

[0050] Therefore, this application provides a first channel 610 that connects to the pixel electrode groove 490. This allows air bubbles that were originally hidden in the pixel electrode groove 490 to be expelled from the electronic paper display panel 10 along the first channel 610 during the rolling of the electronic paper film 200, preventing air bubbles from remaining in the pixel electrode groove 490 and thus improving the display uniformity of the electronic paper display panel 10. Furthermore, after rolling, a sealing layer is applied to the edge of the electronic paper display panel 10 to prevent external moisture from entering the display panel through the first channel 610.

[0051] Compared to the solution without pixel electrode slot 490, the electronic paper display panel 10 of this application requires a shorter charging time while maintaining the same voltage. Furthermore, compared to the solution with pixel electrode slot 490, since air bubbles in the pixel electrode slot 490 can be discharged through the first channel 610, there will be no difference in electric field at different positions of the common electrode 120 and the pixel electrode 510, resulting in a more uniform display effect.

[0052] This embodiment uses the example of the first channel 610 only connecting the pixel electrode slots 490 in the vertical direction for explanation. Specifically: the scan line 421 is located in the first metal layer 420, the data line 463 is located in the second metal layer 460, the length direction of the data line 463 is the first direction, the length direction of the first channel 610 is the same as the first direction, and the first channel 610 only connects the pixel electrode slots 490 in the first direction.

[0053] In this way, during the rolling process, only rolling along the length of the data line 463 is needed to remove air bubbles from the pixel electrode groove 490. Furthermore, the first channel 610 does not occupy the passivation layer 480 above the data line 463, thus not affecting the protective function of the passivation layer 480 for the data line 463. The width d of the first channel 610 is ≤10µm to prevent the first channel 610 from being too large and affecting the movement of the corresponding electrophoretic particles.

[0054] Figure 4 is a schematic diagram of a cross-section of a common electrode located in the second metal layer according to the first embodiment of this application. As shown in Figure 4, the common electrode 422 is used to connect with the common electrode 120. The common electrode 422 layer can be located in the first metal layer 420 or in the second metal layer 460.

[0055] As shown in Figure 3, when the common electrode 422 is located in the first metal layer 420, the array substrate 300 further includes an electrode plate 464 disposed opposite to the common electrode 422. The electrode plate 464 is located in the second metal layer 460, and the electrode plate 464 is also connected to the pixel electrode 510. The orthographic projection of the electrode plate 464 on the substrate 410 overlaps with the orthographic projection of the common electrode 422 on the substrate 410.

[0056] As shown in Figure 4, when the common electrode 422 is located in the second metal layer 460, the array substrate 300 further includes an electrode plate 464 disposed opposite to the common electrode 422. The electrode plate 464 is located in the first metal layer 420, and the electrode plate 464 is also connected to the pixel electrode 510. The orthographic projection of the electrode plate 464 on the substrate 410 overlaps with the orthographic projection of the common electrode 422 on the substrate 410.

[0057] Currently, for products with relatively small high-resolution pixel areas, the space for forming storage capacitors is limited. Therefore, by placing the common electrode 422 in the second metal layer 460, compared to the scheme where the common electrode 422 is located in the first metal layer 420, two parallel storage capacitor structures are formed. Simply put, a first storage capacitor is formed between the electrode plate 464 and the common electrode 422, and a second storage capacitor is formed between the common electrode 422 and the pixel electrode 510, thereby increasing the size of the storage capacitor.

[0058] By placing the common electrode 422 within the first metal layer 420, compared to a scheme where the common electrode 422 is located within the first metal layer 420, only an adapter hole 700 needs to be provided between the pixel electrode 510 and the drain electrode 462 for connection, and then the drain electrode 462 is extended to form an electrode plate 464, making the process simpler. This application uses a scheme where the common electrode 422 is located within the first metal layer 420 as an example for explanation.

[0059] Figure 5 is a partially enlarged schematic diagram of a transition hole according to the first embodiment of this application. As shown in Figure 5, the array substrate 300 further includes a drain 462 located in the second metal layer 460. The array substrate 300 also includes a transition hole 700 that penetrates the passivation layer 480 and the second insulating layer 470. The pixel electrode 510 is connected to the drain 462 through the transition hole 700. Each transition hole 700 in each pixel region corresponds one-to-one with the pixel electrode groove 490.

[0060] Because bubbles expelled from the original pixel electrode groove 490 during the rolling and degassing process can easily enter the transition hole 700 and fail to escape, the array substrate 300 further includes a third channel 630. The third channel 630 connects the transition hole 700 and the pixel electrode groove 490, and the angle between the length direction of the third channel 630 and the first direction is acute. In simpler terms, the third channel 630 connects to the pixel electrode groove 490 at an upward angle to facilitate the expulsion of bubbles entering the transition hole 700. The width d of the third channel 630 is ≤10µm to prevent excessive width from affecting the movement of electrophoretic particles above it.

[0061] Furthermore, taking the length direction of the scan line 421 as the second direction, the width of the first channel 610 along the second direction is the same as the width of the pixel electrode groove 490 along the second direction; among the two sidewalls of the first channel 610 along the second direction and the two sidewalls of the pixel electrode groove 490 along the second direction, the sidewall of the first channel 610 near the data line 463 on the same side is flush with the sidewall of the pixel electrode groove 490, ensuring that air bubbles can flow smoothly in the pixel electrode groove 490 and the first channel 610; the third channel 630 between the adapter hole 700 and the corresponding pixel electrode groove 490 is inclined upward, which is more conducive to the discharge of air bubbles in the adapter hole 700.

[0062] To ensure proper bubble removal, the width of the pixel electrode groove 490 needs to be equal to the width of the first channel 610. This limits the size of the pixel electrode groove 490, thus restricting the charging capability between the pixel electrode 510 and the common electrode 422. Therefore, this embodiment also improves the shape of the pixel electrode groove 490, as follows:

[0063] Figure 6 is a schematic diagram of a pixel electrode groove according to the first embodiment of this application. As shown in Figure 6, the length direction along the data line 463 is the first direction, and the length direction along the scan line 421 is the second direction.

[0064] The pixel electrode groove 490 includes a first sidewall 491, a second sidewall 492, a third sidewall 493, a fourth sidewall 494, and a fifth sidewall 495 connected in sequence. The first sidewall 491, the third sidewall 493, and the data line 463 are parallel. The second sidewall 492 and the fifth sidewall 495 are parallel to the scan line 421. The length of the third sidewall 493 along the first direction is less than the length of the first sidewall 491 along the first direction, and the angle between the fourth sidewall 494 and the third sidewall 493 is an obtuse angle.

[0065] The first channel 610 connects the second sidewall 492 and the fifth sidewall 495 of the two pixel electrode slots 490 in the first direction, respectively. The length of the fifth sidewall 495 along the second direction is equal to the width of the first channel 610 along the second direction.

[0066] Since the fourth sidewall 494 is inclined, when the electronic paper film 200 is rolled from bottom to top, the air bubbles in the pixel electrode groove 490 can smoothly enter the first channel 610 along the inclined fourth sidewall 494. This can further increase the size of the pixel electrode groove 490, thereby increasing the area ratio of the pixel electrode 510 and the common electrode 422 that are closer together, and improving the charging capability of the pixel electrode 510 and the common electrode 422.

[0067] The array substrate 300 further includes a fourth channel 640, which connects the adapter hole 700 and the pixel electrode groove 490. Specifically, one end of the fourth channel 640 is connected to the adapter hole 700, and the other end is connected to the second sidewall 492 of the pixel electrode groove 490. The length direction of the fourth channel 640 is the same as the first direction, allowing air bubbles in the adapter hole 700 to be smoothly discharged into the pixel electrode groove 490 during bottom-to-top rolling, and then discharged outside the electronic paper display panel 10 through the first channel 610. The width d of the fourth channel 640 is ≤10µm to prevent excessive width from affecting the movement of electrophoretic particles above it.

[0068] Example 2:

[0069] Figure 7 is a schematic diagram of a planar first channel 610 arranged horizontally according to a second embodiment of this application. As shown in Figure 7, unlike the first embodiment, the first channel 610 in this embodiment is arranged horizontally, that is, the scan line 421 is located in the first metal layer 420, the data line 463 is located in the second metal layer 460, the direction along the scan line 421 is the second direction, the length direction of the first channel 610 is the same as the second direction, and the first channel 610 only connects the pixel electrode grooves 490 in the second direction. In this way, when rolling the electronic paper film 200, it can be rolled from left to right or from right to left in the direction of the electronic paper display panel 10, which can discharge the air bubbles originally hidden in the pixel electrode grooves 490 along the first channel 610 to the outside of the electronic paper display panel 10, prevent the appearance of air bubbles in the pixel electrode grooves 490, and thus improve the display uniformity of the electronic paper display panel 10.

[0070] Furthermore, when the data line 463 is in the first metal layer 420 and the scan line 421 is in the second metal layer 460, the first channel 610 is set along the second direction. Only the passivation layer 480 above the data line 463 in the first metal layer 420 needs to be hollowed out, but the passivation layer 480 above the scan line 421 in the second metal layer 460 does not need to be hollowed out, so the protective effect on the scan line 421 in the second metal layer 460 is not lost.

[0071] Figure 8 is a partially enlarged schematic diagram of a first channel according to a second embodiment of this application. As shown in Figure 8, since the first channel 610 needs to span the data line 463, this application further divides the first channel 610 into two parallel first sub-channels 611. Specifically, the first channel 610 is composed of at least two first sub-channels 611, and a gap is provided between each first sub-channel 611. The first sub-channels 611 connect to the pixel electrode groove 490 in the second direction. This reduces the occupied area of ​​the first channel 610 above the corresponding data line 463, maintaining the protective effect of the passivation layer 480 on the data line 463 below.

[0072] Furthermore, the first sub-channel 611 can be configured with a shape that is narrow in the middle and wide at both ends, specifically as follows: the first sub-channel 611 is sequentially divided into a first part 612, a second part 613, and a third part 614 along the second direction. The width of the first part 612 decreases sequentially along the second direction, and the width of the third part 614 increases sequentially along the second direction. The width of the first part 612 near the second part 613 along the first direction is the same as the width of the second part 613 along the first direction, and the width of the third part 614 near the second part 613 along the first direction is the same as the width of the second part 613 along the first direction. The orthographic projection of the second part 613 onto the substrate 410 covers the orthographic projection of the data line 463 onto the substrate 410. This achieves a further reduction in the area occupied by the first channel 610 without affecting the bubble removal capability.

[0073] Example 3:

[0074] Figure 9 is a schematic diagram of a first channel in a third embodiment of this application. As shown in Figure 9, only the pixel electrode groove 490 and the first channel 610 are shown. Unlike the first embodiment, the first channel 610 in this embodiment includes both horizontal and vertical arrangements.

[0075] The first direction is along the length of the data line 463, and the second direction is along the direction of the scan line 421. The first channel 610 connects to the pixel electrode slots 490 arranged along the first direction and also connects to the pixel electrode slots 490 arranged along the second direction. Compared with the solution of the first embodiment, this embodiment can perform rolling in any direction during rolling without pre-defining the starting and ending points of rolling, making rolling more flexible.

[0076] Example 4:

[0077] Figure 10 is a schematic planar view of a first channel according to a fourth embodiment of this application. As shown in Figure 10, only the pixel electrode groove 490 and the first channel 610 are shown. Unlike the first embodiment, the first channel 610 in this embodiment is inclined. Simply put, four adjacent pixel regions arranged in a matrix form a group of pixel regions. The first channel 610 connects the pixel electrode grooves 490 corresponding to two adjacent pixel regions in the inclined direction within a group of pixel regions.

[0078] Compared to the solution in the first embodiment, the first channel 610 in this embodiment is inclined and only connects to the pixel electrode groove 490 in the inclined direction. The way the inclined first channel 610 connects to the pixel electrode groove 490 can cover the adapter hole 700, which is equivalent to simultaneously connecting the adapter hole 700, without needing to set up an additional channel for the adapter hole 700.

[0079] Example 5:

[0080] Figure 11 is a schematic diagram of an array substrate according to the fifth embodiment of this application. As shown in Figure 11, this embodiment differs from the first embodiment in that the adapter hole 700 is independently connected and not connected to the pixel electrode groove 490. That is, the array substrate 300 also includes a drain 462, which is located in the second metal layer 460. The array substrate 300 also includes an adapter hole 700, which penetrates the passivation layer 480 and the second insulating layer 470. The pixel electrode 510 is connected to the drain 462 through the adapter hole 700.

[0081] The array substrate 300 further includes a second channel 620, which connects adjacent transition holes 700. The length direction of the second channel 620 is the same as the first direction, and the second channel 620 only connects the transition holes 700 in the first direction. The depth of the second channel 620 is the same as the depth of the transition holes 700. The width d of the second channel 620 is ≤10µm to avoid the movement of electrophoretic particles above it being affected by an excessively large width.

[0082] Since the depth of the adapter hole 700 is different from the depth of the pixel electrode groove 490, compared with the solution of the first embodiment, this embodiment connects the adapter hole 700 separately with the second channel 620 to avoid air bubbles being hidden under the step formed between the second channel 620 of the adapter hole 700, thereby improving the success rate of rolling to remove air bubbles.

[0083] Figure 12 is a schematic diagram of a counter substrate according to an embodiment of this application. As shown in Figure 12, this application also discloses an electronic paper display panel 10, and improves the common electrode 120 on the counter substrate 100. The common electrode 120 is divided into a first common electrode 121 and a second common electrode 123. A gap is provided between the first common electrode 121 and the second common electrode 123. The distance between the first common electrode 121 and the pixel electrode 510 is greater than the distance between the second common electrode 123 and the pixel electrode 510. The first common electrode 121 is connected to a first common voltage, and the second common electrode 123 is connected to a second common voltage. The magnitude of the first common voltage is greater than the magnitude of the second common voltage. The first common electrode 121 corresponds to the pixel electrode slot 490.

[0084] In simple terms, the common electrode 120 is divided into a first common electrode 121 and a second common electrode 123. The first common electrode 121 corresponds to the position of the pixel electrode slot 490, and the second common electrode 123 corresponds to the position outside the pixel electrode slot 490.

[0085] This ensures that the electrophoretic particles at the position corresponding to the first common electrode 121 and the electrophoretic particles at the position corresponding to the second common electrode 123 within the pixel area move at the same speed, thereby making the display image of the electronic paper display panel 10 more uniform.

[0086] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0087] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate for use in an electronic paper display panel, the array substrate comprising a substrate, and a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a passivation layer, and a pixel electrode layer sequentially disposed on the substrate, wherein, The array substrate further includes data lines and scan lines, the data lines and scan lines are located in a first metal layer or a second metal layer and are disposed in different layers. The data lines and scan lines are arranged in a longitudinal and transverse manner to define multiple pixel regions. The pixel electrode layer includes multiple pixel electrodes, each pixel electrode corresponding to a pixel region. The array substrate further includes a common electrode, which is located in the first metal layer or the second metal layer. The passivation layer has pixel electrode grooves located between the pixel electrode and the common electrode, with at least a portion of the pixel electrode located within the pixel electrode grooves. Each pixel electrode groove corresponds to a pixel region. The passivation layer also has a first channel connecting the pixel electrode grooves in different pixel regions. The depth of the first channel is equal to the depth of the pixel electrode groove, and it is used to expel air bubbles from the pixel electrode grooves.

2. The array substrate according to claim 1, wherein, The scan line is located in the first metal layer, the data line is located in the second metal layer, the length direction of the data line is the first direction, the length direction of the first channel is the same as the first direction, and the first channel only connects the pixel electrode slots in the first direction.

3. The array substrate according to claim 2, wherein, The array substrate further includes a drain electrode located in the second metal layer. The array substrate also includes a connection hole that penetrates the passivation layer and the second insulating layer. The pixel electrode is connected to the drain electrode through the connection hole. The array substrate further includes a second channel that connects adjacent adapter holes. The length direction of the second channel is the same as the first direction, and the second channel only connects the adapter holes in the first direction. The depth of the second channel is the same as the depth of the adapter holes.

4. The array substrate according to claim 3, wherein, The width d of the second channel is ≤ 10 μm.

5. The array substrate according to claim 2, wherein, The second direction is along the length of the scan line. The width of the first channel along the second direction is the same as the width of the pixel electrode groove along the second direction. Among the two sidewalls of the first channel along the second direction and the two sidewalls of the pixel electrode groove along the second direction, the sidewall of the first channel near the same side of the data line is flush with the sidewall of the pixel electrode groove. The array substrate further includes a drain electrode located in the second metal layer. The array substrate also includes a transition hole that penetrates the passivation layer and the second insulating layer. The pixel electrode is connected to the drain electrode through the transition hole. Each transition hole in each pixel region corresponds to a pixel electrode slot. The array substrate also includes a third channel that connects the transition hole and the pixel electrode slot. The length direction of the third channel forms an acute angle with the first direction.

6. The array substrate according to claim 5, wherein, The width d of the third channel is ≤10um.

7. The array substrate according to claim 1, wherein, The scan line is located in the first metal layer, the data line is located in the second metal layer, the direction along the scan line is the second direction, the length direction of the first channel is the same as the second direction, and the first channel only connects the pixel electrode slots in the second direction.

8. The array substrate according to claim 7, wherein, The first channel is composed of at least two first sub-channels, and a gap is provided between each first sub-channel. The first sub-channels are connected to the pixel electrode groove in the second direction.

9. The array substrate according to claim 8, wherein, Along the length direction of the data line is the first direction, and the first sub-channel is sequentially divided into a connected first part, a second part, and a third part along the second direction. The width of the first part decreases sequentially along the second direction, and the width of the third part increases sequentially along the second direction. The width of the first part near the second part along the first direction is the same as the width of the second part along the first direction, and the width of the third part near the second part along the first direction is the same as the width of the second part along the first direction. The second part is projected onto the substrate, covering the portion of the data line projected onto the substrate.

10. The array substrate according to claim 1, wherein, The first direction is along the length of the data line, and the second direction is along the length of the scan line; The pixel electrode groove includes a first sidewall, a second sidewall, a third sidewall, a fourth sidewall, and a fifth sidewall connected in sequence. The first sidewall, the third sidewall, and the data line are parallel. The second sidewall and the fifth sidewall are parallel to the scan line. The length of the third sidewall along the first direction is less than the length of the first sidewall along the first direction, and the angle between the fourth sidewall and the third sidewall is an obtuse angle. The first channel connects the second sidewall and the fifth sidewall of the two pixel electrode slots in the first direction, respectively, and the length of the fifth sidewall along the second direction is equal to the width of the first channel along the second direction.

11. The array substrate according to claim 10, wherein, The array substrate further includes a drain electrode located in the second metal layer. The array substrate also includes a connection hole that penetrates the passivation layer and the second insulating layer. The pixel electrode is connected to the drain electrode through the connection hole. The array substrate further includes a fourth channel, one end of which is connected to the adapter hole and the other end of which is connected to the second sidewall of the pixel electrode groove; the length direction of the fourth channel is the same as the first direction.

12. The array substrate according to claim 11, wherein, The width d of the fourth channel is ≤10um.

13. The array substrate according to claim 1, wherein, The width d of the first channel is ≤10um.

14. The array substrate according to claim 1, wherein, The common electrode is located in the first metal layer, and the array substrate further includes an electrode plate disposed opposite to the common electrode. The electrode plate is located in the second metal layer and is also connected to the pixel electrode. The orthogonal projection of the electrode plate on the substrate overlaps with the orthogonal projection of the common electrode on the substrate.

15. The array substrate according to claim 1, wherein, The common electrode is located in the second metal layer. The array substrate also includes an electrode plate disposed opposite to the common electrode. The electrode plate is located in the first metal layer and is also connected to the pixel electrode. The orthogonal projection of the electrode plate on the substrate overlaps with the orthogonal projection of the common electrode on the substrate.

16. The array substrate according to claim 1, wherein, The first direction is along the length of the data line, and the second direction is along the direction of the scan line. The first channel connects to the pixel electrode slots arranged along the first direction and also connects to the pixel electrode slots arranged along the second direction.

17. The array substrate according to claim 1, wherein, The first channel connects the pixel electrode slots corresponding to two adjacent pixel regions arranged in a matrix within the group of pixel regions in the inclined direction.

18. An electronic paper display panel, wherein, The electronic paper display panel includes an electronic paper film and an array substrate as described in any one of claims 1-17, wherein the electronic paper film is bonded to the array substrate.

19. The electronic paper display panel according to claim 18, wherein, The electronic paper display panel further includes a counter substrate, which is disposed opposite to the array substrate. The counter substrate includes a counter substrate and a common electrode, which is disposed on the counter substrate. The electric field formed between the common electrode and the pixel electrode on the array substrate drives the electrophoretic particles in the electronic paper film to move.

20. The electronic paper display panel according to claim 19, wherein, The common electrode is divided into a first common electrode and a second common electrode, and a gap is provided between the first common electrode and the second common electrode. The distance between the first common electrode and the pixel electrode is greater than the distance between the second common electrode and the pixel electrode. The first common electrode is connected to a first common voltage, and the second common electrode is connected to a second common voltage. The magnitude of the first common voltage is greater than the magnitude of the second common voltage. The first common electrode corresponds to the pixel electrode slot.

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