Pixel circuit, testing method, display panel, and display device

Abstract

The present disclosure provides a pixel circuit, a testing method, a display panel, and a display device. The pixel circuit comprises a pixel driving circuit, a light-emitting element, and a test switch circuit. A control end of the test switch circuit is electrically connected to a test control end; and the test switch circuit is arranged between a first test end and a second test end, and is used for controlling the first test end and the second test end to be connected or disconnected under the control of a test control signal. The pixel driving circuit is separately electrically connected to the first test end, the second test end, and the light-emitting element and used for generating a driving current for driving the light-emitting element. The first test end is electrically connected to a first direct-current voltage line, and the second test end is electrically connected to a second direct-current voltage line or a test node; or the first test end is electrically connected to a direct-current voltage line, and the second test end is electrically connected to a data line. In the present disclosure, the performance of each transistor on a current path can be detected.

Description

Pixel circuit, test method, display panel and display device TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and in particular, to a pixel circuit, a test method, a display panel and a display device. BACKGROUND

[0002] The pixel circuit in the form of source follower cannot sense the current flowing through the driving transistor when performing array test, because the signal line providing the data voltage is directly electrically connected to the gate of the driving transistor. Therefore, special design and improvement are needed when performing array test on the pixel circuit.

[0003] SUMMARY

[0004] In one aspect, the present disclosure provides a pixel circuit, comprising a pixel driving circuit, a light emitting element and a test switch circuit; a control terminal of the test switch circuit is electrically connected to a test control terminal;

[0005] The test switch circuit is arranged between a first test terminal and a second test terminal, and is used to control the first test terminal and the second test terminal to be connected or disconnected under the control of a test control signal provided by the test control terminal;

[0006] The pixel driving circuit is electrically connected to the first test terminal, the second test terminal and the light emitting element respectively, and is used to generate a driving current for driving the light emitting element;

[0007] The first test terminal is electrically connected to a first direct current voltage line, and the first test terminal is electrically connected to a second direct current voltage line or a test node; or, the first test terminal is electrically connected to a direct current voltage line, and the second test terminal is electrically connected to a data line.

[0008] Optionally, the pixel driving circuit comprises a driving circuit and a driving control circuit;

[0009] A control terminal of the driving circuit is electrically connected to a first node; a first terminal of the driving circuit is electrically connected to a first test node, and a second terminal of the driving circuit is electrically connected to the light emitting element; the driving circuit is used to generate a driving current under the control of the potential of the first node;

[0010] The driving control circuit is used to control the control terminal of the driving circuit and the first terminal of the driving circuit to be connected when the test switch circuit controls the first test terminal and the second test terminal to be connected.

[0011] Optionally, the first test terminal is electrically connected with a reference voltage line, and the second test terminal is electrically connected with a power voltage line; or the first test terminal is electrically connected with an initial voltage line, and the second test terminal is electrically connected with a data line; or the first test terminal is electrically connected with a reference voltage line, and the second test terminal is electrically connected with a first test node; or the first test terminal is electrically connected with an initial voltage line, and the second test terminal is electrically connected with a second test node.

[0012] Optionally, the test switch circuit comprises a test switch transistor.

[0013] The gate of the test switch transistor is electrically connected with the test control terminal, the first pole of the test switch transistor is electrically connected with the first test terminal, and the second pole of the test switch transistor is electrically connected with the second test terminal.

[0014] Optionally, the drive control circuit comprises a first light-emitting control circuit, a data write circuit, a first reset circuit and a second reset circuit.

[0015] The first light-emitting control circuit is electrically connected with a first light-emitting control line, a power voltage line and a first terminal of the drive circuit respectively, and is used for controlling the power voltage line and the first terminal of the drive circuit to be connected or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control line.

[0016] The data write circuit is electrically connected with a scan line, a data line and a write node respectively, and is used for controlling the data line and the write node to be connected or disconnected under the control of a scan signal provided by the scan line; the second test node is electrically connected with the write node; and the write node is electrically connected with the first node.

[0017] The first reset circuit is electrically connected with a first reset control line, the reference voltage line and the first node respectively, and is used for controlling the reference voltage line and the first node to be connected or disconnected under the control of a first reset control signal provided by the first reset control line.

[0018] The second reset circuit is electrically connected with a second reset control line, an initial voltage line and a reset node respectively, and is used for controlling the initial voltage line and the reset node to be connected or disconnected under the control of a second reset control signal provided by the second reset control line; and the reset node is electrically connected with a second terminal of the drive circuit.

[0019] Optionally, the pixel circuit further comprises a first energy storage circuit and a second energy storage circuit.

[0020] The first energy storage circuit is electrically connected with the first node and the second terminal of the drive circuit respectively, and is used for storing electric energy.

[0021] The second energy storage circuit is electrically connected with the power supply voltage line and the second end of the drive circuit respectively, and is used for storing electric energy.

[0022] Optionally, the pixel circuit further comprises a first energy storage circuit, a second energy storage circuit and a third reset circuit.

[0023] The first energy storage circuit is electrically connected with the write node and the intermediate node respectively, and is used for storing electric energy.

[0024] The second energy storage circuit is electrically connected with the intermediate node and the second end of the drive circuit respectively, and is used for storing electric energy.

[0025] The third reset circuit is electrically connected with a third reset control line, a reference voltage line and the intermediate node respectively, and is used for controlling the reference voltage line and the intermediate node to be connected or disconnected under the control of a third reset control signal provided by the third reset control line.

[0026] Optionally, the pixel circuit further comprises a switch control circuit.

[0027] The first node is electrically connected with the write node through the switch control circuit.

[0028] The control end of the switch control circuit is electrically connected with a switch control line, and the switch control circuit is used for controlling the first node and the write node to be connected or disconnected under the control of a switch control signal provided by the switch control line.

[0029] Optionally, the pixel circuit further comprises a second light emitting control circuit.

[0030] The reset node is electrically connected with the second end of the drive circuit through the second light emitting control circuit; the reset node is electrically connected with the first pole of the light emitting element, and the second pole of the light emitting element is electrically connected with a low voltage line.

[0031] The control end of the second light emitting control circuit is electrically connected with a second light emitting control line, and the second light emitting control circuit is used for controlling the reset node and the second end of the drive circuit to be connected or disconnected under the control of a second light emitting control signal provided by the second light emitting control line.

[0032] Optionally, the drive circuit comprises a drive transistor, the first light emitting control circuit comprises a first transistor, the data write circuit comprises a second transistor, the first reset circuit comprises a third transistor, and the second reset circuit comprises a fourth transistor.

[0033] A gate of the driving transistor is electrically connected with the first node, a first electrode of the driving transistor is electrically connected with the first test node, and a second electrode of the driving transistor is electrically connected with the light emitting element;

[0034] A gate of the first transistor is electrically connected with the first light emitting control line, a first electrode of the first transistor is electrically connected with the power voltage line, and a second electrode of the first transistor is electrically connected with a first electrode of the driving transistor;

[0035] A gate of the second transistor is electrically connected with the scan line, a first electrode of the second transistor is electrically connected with the data line, and a second electrode of the second transistor is electrically connected with the write node;

[0036] A gate of the third transistor is electrically connected with the first reset control line, a first electrode of the third transistor is electrically connected with the reference voltage line, and a second electrode of the third transistor is electrically connected with the first node;

[0037] A gate of the fourth transistor is electrically connected with the second reset control line, a first electrode of the fourth transistor is electrically connected with the initial voltage line, and a second electrode of the fourth transistor is electrically connected with the reset node.

[0038] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor;

[0039] A first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the second end of the driving circuit;

[0040] A first end of the second capacitor is electrically connected with the power voltage line, and a second end of the second capacitor is electrically connected with the second end of the driving circuit.

[0041] Optionally, the first energy storage circuit includes a first capacitor, the second energy storage circuit includes a second capacitor, and the third reset circuit includes a fifth transistor;

[0042] A first end of the first capacitor is electrically connected with the write node, and a second end of the first capacitor is electrically connected with the intermediate node;

[0043] A first end of the second capacitor is electrically connected with the intermediate node, and a second end of the second capacitor is electrically connected with the second end of the driving circuit;

[0044] A gate of the fifth transistor is electrically connected with the third reset control line, a first electrode of the fifth transistor is electrically connected with the reference voltage line, and a second electrode of the fifth transistor is electrically connected with the intermediate node.

[0045] Optionally, the switch control circuit comprises a sixth transistor.

[0046] A gate of the sixth transistor is electrically connected with the switch control line, a first pole of the sixth transistor is electrically connected with the first node, and a second pole of the sixth transistor is electrically connected with the write node.

[0047] Optionally, the second light emitting control circuit comprises a seventh transistor.

[0048] A gate of the seventh transistor is electrically connected with the second light emitting control line, a first pole of the seventh transistor is electrically connected with the second end of the driving circuit, and a second pole of the seventh transistor is electrically connected with the reset node.

[0049] In a second aspect, the embodiments of the present disclosure provide a test method of a pixel circuit, applied to the pixel circuit, and the test method comprises:

[0050] In the detection stage, a valid test control signal is provided to the test control end, and the test switch circuit controls the first test end and the second test end to be in communication under the control of the test control signal.

[0051] Optionally, the test method further comprises:

[0052] In the display stage, an invalid test control signal is provided to the test control end, and the test switch circuit controls the first test end and the second test end to be disconnected under the control of the test control signal, and the pixel driving circuit generates a driving current for driving the light emitting element.

[0053] Optionally, the pixel driving circuit comprises a driving circuit and a driving control circuit, and the test method comprises:

[0054] In the detection stage, the driving control circuit controls the control end of the driving circuit and the first end of the driving circuit to be in communication.

[0055] In a third aspect, the embodiments of the present disclosure provide a display device comprising the pixel circuit.

[0056] In a fourth aspect, the embodiments of the present disclosure provide a display panel comprising a plurality of rows and columns of pixel circuits, a plurality of first direct current voltage lines and a plurality of second direct current voltage lines; the plurality of rows and columns of pixel circuits are arranged in a display area; the display panel further comprises a test switch module arranged in a frame area; the test switch module comprises a plurality of test switch circuits.

[0057] The test switch circuit is electrically connected with a test control terminal, a first direct current voltage line and a second direct current voltage line respectively, and is used for controlling the first direct current voltage line and the second direct current voltage line to be connected or disconnected under the control of a test control signal provided by the test control terminal.

[0058] Optionally, the first direct current voltage line and the second direct current voltage line both extend in a first direction; the display panel includes N rows of pixel circuits; the pixel circuit located in the nth row is electrically connected with the nth first direct current voltage line and the nth second direct current voltage line respectively; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0059] The test switch module includes N test switch circuits;

[0060] The nth test switch circuit is electrically connected with the nth test control terminal, the nth first direct current voltage line and the nth second direct current voltage line respectively, and is used for controlling the nth first direct current voltage line and the nth second direct current voltage line to be connected or disconnected under the control of an nth test control signal provided by the nth test control terminal.

[0061] Optionally, the display panel includes N rows of pixel circuits; the pixel circuit located in the nth row is electrically connected with the nth first direct current voltage line and the nth second direct current voltage line respectively; N is an integer greater than 1, n is a positive integer less than or equal to N, and m is a positive integer less than N;

[0062] The test switch module includes at least one test switch circuit;

[0063] The mth test switch circuit is electrically connected with the mth test control terminal, the mth first direct current voltage line and the m+1th second direct current voltage line respectively, and is used for controlling the mth first direct current voltage line and the m+1th second direct current voltage line to be connected or disconnected under the control of an mth test control signal provided by the mth test control terminal.

[0064] Optionally, the first direct current voltage line includes a plurality of rows of first direct current voltage line parts and a plurality of columns of second direct current voltage line parts which are electrically connected with each other, and the second direct current voltage line includes a plurality of rows of third direct current voltage line parts and a plurality of columns of fourth direct current voltage line parts which are electrically connected with each other;

[0065] The extension direction of the first direct current voltage line part is the same as the extension direction of the third direct current voltage line part, the extension direction of the second direct current voltage line part is the same as the extension direction of the fourth direct current voltage line part, and the extension direction of the first direct current voltage line part intersects with the extension direction of the second direct current voltage line part;

[0066] The test switch module includes a plurality of first test switch circuits and a plurality of second test switch circuits;

[0067] The first test switch circuit is respectively electrically connected with a corresponding test control end, a row of the first direct current voltage line part and a row of the third direct current voltage line part, and is used for controlling the row of the first direct current voltage line part and the row of the third direct current voltage line part to be connected or disconnected under the control of a test control signal provided by the test control end;

[0068] The second test switch circuit is respectively electrically connected with a corresponding test control end, a column of the second direct current voltage line part and a column of the fourth direct current voltage line part, and is used for controlling the column of the second direct current voltage line part and the column of the fourth direct current voltage line part to be connected or disconnected under the control of a test control signal provided by the test control end.

[0069] In a fifth aspect, the display panel provided by the embodiments of the present disclosure includes a plurality of rows of a plurality of columns of pixel circuits, a plurality of third direct current voltage lines and A columns of data lines; A is an integer greater than 1; a is a positive integer less than or equal to A; the plurality of rows of the plurality of columns of pixel circuits are arranged in a display area; the pixel circuit in the a-th column is electrically connected with the a-th column of data lines;

[0070] The display panel further includes a test switch module arranged in a frame area; the test switch module includes A test switch circuits;

[0071] The a-th test switch circuit is respectively electrically connected with the a-th test control end, a third direct current voltage line and the a-th column of data lines, and is used for controlling the third direct current voltage line and the a-th column of data lines to be connected or disconnected under the control of the a-th test control signal provided by the a-th test control end.

[0072] In a sixth aspect, the display device provided by the embodiments of the present disclosure includes the display panel described above. BRIEF DESCRIPTION OF DRAWINGS

[0073] FIG. 1 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0074] FIG. 2 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0075] FIG. 3 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0076] FIG. 4 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0077] FIG. 5 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0078] FIG. 6 is a structural diagram of a pixel circuit according to at least one embodiment of the present disclosure;

[0079] FIG. 7 is a structure diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0080] FIG. 8 is a structure diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0081] FIG. 9 is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0082] FIG. 10A is a timing diagram of at least one embodiment of the pixel circuit of FIG. 9 according to at least one embodiment of the disclosure;

[0083] FIG. 10B is a schematic diagram of a current path of at least one embodiment of the pixel circuit of FIG. 9 during a detection phase according to at least one embodiment of the disclosure;

[0084] FIG. 11A is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0085] FIG. 11B is a schematic diagram of a current path of at least one embodiment of the pixel circuit of FIG. 11A during a detection phase according to at least one embodiment of the disclosure;

[0086] FIG. 12 is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0087] FIG. 13A is a timing diagram of at least one embodiment of the pixel circuit of FIG. 12 according to at least one embodiment of the disclosure;

[0088] FIG. 13B is a schematic diagram of a current path of at least one embodiment of the pixel circuit of FIG. 12 during a detection phase according to at least one embodiment of the disclosure;

[0089] FIG. 14 is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0090] FIG. 15A is a timing diagram of at least one embodiment of the pixel circuit of FIG. 14 according to at least one embodiment of the disclosure;

[0091] FIG. 15B is a schematic diagram of a current path of at least one embodiment of the pixel circuit of FIG. 14 during a detection phase according to at least one embodiment of the disclosure;

[0092] FIG. 16A is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0093] FIG. 16B is a schematic diagram of a current path of at least one embodiment of the pixel circuit of FIG. 16A during a detection phase according to at least one embodiment of the disclosure;

[0094] FIG. 17 is a circuit diagram of a pixel circuit according to at least one embodiment of the disclosure;

[0095] FIG. 18A is a first timing diagram of at least one embodiment of the pixel circuit of FIG. 17 according to at least one embodiment of the disclosure;

[0096] FIG. 18B is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure;

[0097] FIG. 18C is a schematic diagram of a first current path of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure during a detection phase;

[0098] FIG. 18D is a schematic diagram of a second current path of at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure during a detection phase;

[0099] FIG. 19 is a circuit diagram of a pixel circuit in accordance with at least one embodiment of the present disclosure;

[0100] FIG. 20A is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure;

[0101] FIG. 20B is a first operation timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure;

[0102] FIG. 20C is a schematic diagram of a first current path of at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure during a detection phase;

[0103] FIG. 20D is a schematic diagram of a second current path of at least one embodiment of the pixel circuit shown in FIG. 19 of the present disclosure during a detection phase;

[0104] FIG. 21 is a structure diagram of a display panel in accordance with at least one embodiment of the present disclosure;

[0105] FIG. 22 is a structure diagram of a display panel in accordance with at least one embodiment of the present disclosure;

[0106] FIG. 23 is a schematic diagram of pixel circuits in the same column sharing a test switch transistor. DETAILED DESCRIPTION

[0107] The technical solutions in the embodiments of the present disclosure will be described clearly and completely below with reference to the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure.

[0108] The transistors used in all the embodiments of the present disclosure can be thin film transistors or field effect transistors or other devices with the same characteristics. In the embodiments of the present disclosure, in order to distinguish the two poles of the transistor other than the gate, one of the poles is called the first pole and the other is called the second pole.

[0109] In actual operation, when the transistor is a thin-film transistor or a field effect transistor, the first electrode can be a drain electrode, and the second electrode can be a source electrode; or the first electrode can be a source electrode, and the second electrode can be a drain electrode.

[0110] The pixel circuit includes a pixel driving circuit, a light emitting element, and a test switch circuit.

[0111] The test switch circuit is arranged between the first test terminal and the second test terminal, and is configured to control the first test terminal and the second test terminal to be connected or disconnected under the control of a test control signal provided by the test control terminal.

[0112] The pixel driving circuit is electrically connected to the first test terminal, the second test terminal, and the light emitting element, and is configured to generate a driving current for driving the light emitting element.

[0113] The first test terminal is electrically connected to a first direct current voltage line, and the first test terminal is electrically connected to a second direct current voltage line or a test node; or the first test terminal is electrically connected to a direct current voltage line, and the second test terminal is electrically connected to a data line.

[0114] In the detection phase, the test switch circuit controls the first test terminal and the second test terminal to be connected under the control of the test control signal, forms a current path, and detects the performance of each transistor on the current path by detecting the current on the current path.

[0115] As shown in FIG. 1, the pixel circuit includes a pixel driving circuit 10, a light emitting element E1, and a test switch circuit 11.

[0116] The test switch circuit 11 is arranged between the first test terminal VT1 and the second test terminal VT2, and is configured to control the first test terminal VT1 and the second test terminal VT2 to be connected or disconnected under the control of a test control signal provided by the test control terminal AT.

[0117] The pixel driving circuit 10 is electrically connected to the first test terminal VT1, the second test terminal VT2, and the light emitting element E1, and is configured to generate a driving current for driving the light emitting element E1.

[0118] In at least one embodiment of the present disclosure, the pixel driving circuit includes a driving circuit and a driving control circuit.

[0119] A control end of the drive circuit is electrically connected with the first node; a first end of the drive circuit is electrically connected with the first test node, and a second end of the drive circuit is electrically connected with the light-emitting element; the drive circuit is used for generating a drive current under the control of the potential of the first node;

[0120] The drive control circuit is used for controlling the communication between the control end of the drive circuit and the first end of the drive circuit when the test switch circuit controls the communication between the first test end and the second test end.

[0121] In a specific implementation, the pixel drive circuit can include a drive circuit and a drive control circuit; the drive control circuit controls the communication between the control end of the drive circuit and the first end of the drive circuit when the test switch circuit controls the communication between the first test end and the second test end; the current flowing through the drive circuit is detected; and the performance of the drive transistor included in the drive circuit is detected according to the detection result, so as to perform an AT (array test) test on the pixel circuit.

[0122] Optionally, the first test end is electrically connected with a reference voltage line, and the second test end is electrically connected with a power voltage line; or the first test end is electrically connected with an initial voltage line, and the second test end is electrically connected with a data line; or the first test end is electrically connected with a reference voltage line, and the second test end is electrically connected with the first test node; or the first test end is electrically connected with an initial voltage line, and the second test end is electrically connected with the second test node.

[0123] Optionally, the test switch circuit includes a test switch transistor.

[0124] A gate of the test switch transistor is electrically connected with the test control end; a first pole of the test switch transistor is electrically connected with the first test end; and a second pole of the test switch transistor is electrically connected with the second test end.

[0125] In at least one embodiment of the present disclosure, the drive control circuit includes a first light-emitting control circuit, a data writing circuit, a first reset circuit and a second reset circuit.

[0126] The first light-emitting control circuit is electrically connected with a first light-emitting control line, a power voltage line and the first end of the drive circuit respectively; and the first light-emitting control circuit is used for controlling the communication or disconnection between the power voltage line and the first end of the drive circuit under the control of a first light-emitting control signal provided by the first light-emitting control line.

[0127] The data writing circuit is electrically connected with the scan line, the data line and the writing node respectively, and is configured to be controlled to be connected or disconnected between the data line and the writing node under control of a scan signal provided by the scan line; the second test node is electrically connected with the writing node; and the writing node is electrically connected with the first node.

[0128] The first reset circuit is electrically connected with the first reset control line, the reference voltage line and the first node respectively, and is configured to be controlled to be connected or disconnected between the reference voltage line and the first node under control of a first reset control signal provided by the first reset control line.

[0129] The second reset circuit is electrically connected with the second reset control line, the initial voltage line and the reset node respectively, and is configured to be controlled to be connected or disconnected between the initial voltage line and the reset node under control of a second reset control signal provided by the second reset control line; and the reset node is electrically connected with the second end of the driving circuit.

[0130] The pixel circuit further comprises a first energy storage circuit and a second energy storage circuit.

[0131] The first energy storage circuit is electrically connected with the first node and the second end of the driving circuit respectively, and is configured to store electric energy.

[0132] The second energy storage circuit is electrically connected with the power voltage line and the second end of the driving circuit respectively, and is configured to store electric energy.

[0133] As shown in FIG. 2, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test end is electrically connected with the reference voltage line REF, and the second test end is electrically connected with the power voltage line ELVDD.

[0134] The pixel driving circuit comprises a driving circuit 20 and a driving control circuit.

[0135] The control end of the driving circuit 20 is electrically connected with the first node N1; the first end of the driving circuit 20 is electrically connected with the first test node NC1, the second end of the driving circuit 20 is electrically connected with the light emitting element E1, and the driving circuit 20 is configured to generate a driving current for driving the light emitting element E1 under control of the potential of the first node N1.

[0136] The driving control circuit comprises a first light emitting control circuit 71, a data writing circuit 72, a first reset circuit 73 and a second reset circuit 74.

[0137] The first light emitting control circuit 71 is electrically connected with the first light emitting control line EM1, the power voltage line ELVDD and the first end of the driving circuit 20, respectively, for controlling the power voltage line ELVDD and the first end of the driving circuit 20 to be connected or disconnected under the control of the first light emitting control signal provided by the first light emitting control line EM1;

[0138] The data writing circuit 72 is electrically connected with the scanning line GT, the data line DL and the writing node NW, respectively, for controlling the data line DL and the writing node NW to be connected or disconnected under the control of the scanning signal provided by the scanning line GT; the writing node NW is electrically connected with the first node N1;

[0139] The first reset circuit 73 is electrically connected with the first reset control line R1, the reference voltage line REF and the first node N1, respectively, for controlling the reference voltage line REF and the first node N1 to be connected or disconnected under the control of the first reset control signal provided by the first reset control line R1;

[0140] The second reset circuit 74 is electrically connected with the second reset control line R2, the initial voltage line I1 and the reset node NR, respectively, for controlling the initial voltage line I1 and the reset node NR to be connected or disconnected under the control of the second reset control signal provided by the second reset control line R2; the reset node NR is electrically connected with the second end of the driving circuit 20;

[0141] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a first energy storage circuit 81 and a second energy storage circuit 82;

[0142] The first energy storage circuit 81 is electrically connected with the first node N1 and the second end of the driving circuit 20, respectively, for storing electric energy;

[0143] The second energy storage circuit 82 is electrically connected with the power voltage line ELVDD and the second end of the driving circuit 20, respectively, for storing electric energy.

[0144] As shown in FIG. 3, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test terminal is electrically connected with the reference voltage line REF, and the second test terminal is electrically connected with the first test node NC1;

[0145] The pixel driving circuit comprises the driving circuit 20 and a driving control circuit;

[0146] A control terminal of the drive circuit 20 is electrically connected with the first node N1; a first terminal of the drive circuit 20 is electrically connected with a first test node NC1, and a second terminal of the drive circuit 20 is electrically connected with the light emitting element E1; the drive circuit 20 is used for generating a drive current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0147] The drive control circuit comprises a first light emitting control circuit 71, a data writing circuit 72, a first reset circuit 73 and a second reset circuit 74;

[0148] The first light emitting control circuit 71 is electrically connected with a first light emitting control line EM1, a power voltage line ELVDD and the first terminal of the drive circuit 20 respectively, and is used for controlling the communication or disconnection between the power voltage line ELVDD and the first terminal of the drive circuit 20 under the control of a first light emitting control signal provided by the first light emitting control line EM1;

[0149] The data writing circuit 72 is electrically connected with a scan line GT, a data line DL and a writing node NW respectively, and is used for controlling the communication or disconnection between the data line DL and the writing node NW under the control of a scan signal provided by the scan line GT; the writing node NW is electrically connected with the first node N1;

[0150] The first reset circuit 73 is electrically connected with a first reset control line R1, the reference voltage line REF and the first node N1 respectively, and is used for controlling the communication or disconnection between the reference voltage line REF and the first node N1 under the control of a first reset control signal provided by the first reset control line R1;

[0151] The second reset circuit 74 is electrically connected with a second reset control line R2, an initial voltage line I1 and a reset node NR respectively, and is used for controlling the communication or disconnection between the initial voltage line I1 and the reset node NR under the control of a second reset control signal provided by the second reset control line R2; the reset node NR is electrically connected with the second terminal of the drive circuit 20;

[0152] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a first energy storage circuit 81 and a second energy storage circuit 82;

[0153] The first energy storage circuit 81 is electrically connected with the first node N1 and the second terminal of the drive circuit 20 respectively, and is used for storing electric energy;

[0154] The second energy storage circuit 82 is electrically connected with the power voltage line ELVDD and the second terminal of the drive circuit 20 respectively, and is used for storing electric energy.

[0155] The pixel circuit in at least one embodiment of the present disclosure further comprises a first energy storage circuit, a second energy storage circuit and a third reset circuit;

[0156] The first energy storage circuit is electrically connected with the write node and the intermediate node respectively, and is used for storing energy;

[0157] The second energy storage circuit is electrically connected with the intermediate node and the second end of the drive circuit respectively, and is used for storing energy;

[0158] The third reset circuit is electrically connected with a third reset control line, a reference voltage line and the intermediate node respectively, and is used for controlling the reference voltage line to be connected or disconnected with the intermediate node under the control of a third reset control signal provided by the third reset control line.

[0159] The pixel circuit in at least one embodiment of the present disclosure further comprises a switch control circuit;

[0160] The first node is electrically connected with the write node through the switch control circuit;

[0161] The control end of the switch control circuit is electrically connected with a switch control line, and the switch control circuit is used for controlling the first node to be connected or disconnected with the write node under the control of a switch control signal provided by the switch control line.

[0162] As shown in FIG. 4, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test end is electrically connected with a reference voltage line REF, and the second test end is electrically connected with a power voltage line ELVDD;

[0163] The pixel drive circuit comprises a drive circuit 20 and a drive control circuit;

[0164] The control end of the drive circuit 20 is electrically connected with a first node N1, the first end of the drive circuit 20 is electrically connected with a first test node NC1, and the second end of the drive circuit 20 is electrically connected with a light emitting element E1, and the drive circuit 20 is used for generating a drive current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0165] The drive control circuit comprises a first light emitting control circuit 71, a data write circuit 72, a first reset circuit 73 and a second reset circuit 74;

[0166] The first light emitting control circuit 71 is electrically connected with a first light emitting control line EM1, a power voltage line ELVDD and the first end of the drive circuit 20 respectively, and is used for controlling the power voltage line ELVDD to be connected or disconnected with the first end of the drive circuit 20 under the control of a first light emitting control signal provided by the first light emitting control line EM1.

[0167] The data writing circuit 72 is electrically connected with the scan line GT, the data line DL and the writing node NW respectively, and is configured to control the data line DL to be connected or disconnected with the writing node NW under the control of a scan signal provided by the scan line GT;

[0168] The first reset circuit 73 is electrically connected with the first reset control line R1, the reference voltage line REF and the first node N1 respectively, and is configured to control the reference voltage line REF to be connected or disconnected with the first node N1 under the control of a first reset control signal provided by the first reset control line R1;

[0169] The second reset circuit 74 is electrically connected with the second reset control line R2, the initial voltage line I1 and the second end of the driving circuit 20 respectively, and is configured to control the initial voltage line I1 to be connected or disconnected with the second end of the driving circuit 20 under the control of a second reset control signal provided by the second reset control line R2;

[0170] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a first energy storage circuit 81, a second energy storage circuit 82 and a third reset circuit 83;

[0171] The first energy storage circuit 81 is electrically connected with the writing node NW and the intermediate node NZ respectively, and is configured to store energy;

[0172] The second energy storage circuit 82 is electrically connected with the intermediate node NZ and the second end of the driving circuit 20 respectively, and is configured to store energy;

[0173] The third reset circuit 83 is electrically connected with the third reset control line R3, the reference voltage line REF and the intermediate node NZ respectively, and is configured to control the reference voltage line REF to be connected or disconnected with the intermediate node NZ under the control of a third reset control signal provided by the third reset control line R3;

[0174] The pixel circuit provided in at least one embodiment of the present disclosure further comprises a switch control circuit 80;

[0175] The first node N1 is electrically connected with the writing node NW through the switch control circuit 80;

[0176] The control end of the switch control circuit 80 is electrically connected with a switch control line SW, and the switch control circuit 80 is configured to control the first node N1 to be connected or disconnected with the writing node NW under the control of a switch control signal provided by the switch control line SW.

[0177] Optionally, the third reset control line can be a first reset control line, and the switch control line can be a second light-emitting control line.

[0178] As shown in FIG. 5, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test terminal is electrically connected with a reference voltage line REF, and the second test terminal is electrically connected with a power voltage line ELVDD.

[0179] The pixel driving circuit includes a driving circuit 20 and a driving control circuit.

[0180] A control terminal of the driving circuit 20 is electrically connected with a first node N1; a first terminal of the driving circuit 20 is electrically connected with a first test node NC1, and a second terminal of the driving circuit 20 is electrically connected with a light-emitting element E1; the driving circuit 20 is configured to generate a driving current for driving the light-emitting element E1 under the control of a potential of the first node N1.

[0181] The driving control circuit includes a first light-emitting control circuit 71, a data writing circuit 72, a first reset circuit 73, and a second reset circuit 74.

[0182] The first light-emitting control circuit 71 is electrically connected with a first light-emitting control line EM1, a power voltage line ELVDD, and a first terminal of the driving circuit 20, respectively, and is configured to control the power voltage line ELVDD and the first terminal of the driving circuit 20 to be connected or disconnected under the control of a first light-emitting control signal provided by the first light-emitting control line EM1.

[0183] The data writing circuit 72 is electrically connected with a scan line GT, a data line DL, and a writing node NW, respectively, and is configured to control the data line DL and the writing node NW to be connected or disconnected under the control of a scan signal provided by the scan line GT; the writing node NW is electrically connected with the first node N1.

[0184] The first reset circuit 73 is electrically connected with a first reset control line R1, the reference voltage line REF, and the first node N1, respectively, and is configured to control the reference voltage line REF and the first node N1 to be connected or disconnected under the control of a first reset control signal provided by the first reset control line R1.

[0185] The second reset circuit 74 is electrically connected with a second reset control line R2, an initial voltage line I1, and a second terminal of the driving circuit 20, respectively, and is configured to control the initial voltage line I1 and the second terminal of the driving circuit 20 to be connected or disconnected under the control of a second reset control signal provided by the second reset control line R2.

[0186] The pixel circuit in at least one embodiment of the present disclosure further comprises a first energy storage circuit 81, a second energy storage circuit 82, and a third reset circuit 83.

[0187] The first energy storage circuit 81 is electrically connected with the write node NW and the intermediate node NZ respectively, and is used for storing energy.

[0188] The second energy storage circuit 82 is electrically connected with the intermediate node NZ and the second end of the driving circuit 20 respectively, and is used for storing energy.

[0189] The third reset circuit 83 is electrically connected with a third reset control line R3, a reference voltage line REF, and the intermediate node NZ respectively, and is used for controlling the reference voltage line REF to be connected or disconnected with the intermediate node NZ under the control of a third reset control signal provided by the third reset control line R3.

[0190] In at least one embodiment of the present disclosure, the pixel circuit further comprises a second light-emitting control circuit.

[0191] The reset node is electrically connected with the second end of the driving circuit through the second light-emitting control circuit, and is electrically connected with the first pole of the light-emitting element, and the second pole of the light-emitting element is electrically connected with a low-voltage line.

[0192] The control end of the second light-emitting control circuit is electrically connected with a second light-emitting control line, and the second light-emitting control circuit is used for controlling the reset node to be connected or disconnected with the second end of the driving circuit under the control of a second light-emitting control signal provided by the second light-emitting control line.

[0193] As shown in FIG. 6, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test end is electrically connected with a reference voltage line REF, and the second test end is electrically connected with a power voltage line ELVDD.

[0194] The pixel driving circuit comprises a driving circuit 20 and a driving control circuit.

[0195] The control end of the driving circuit 20 is electrically connected with a first node N1, the first end of the driving circuit 20 is electrically connected with a first test node NC1, and the second end of the driving circuit 20 is electrically connected with a light-emitting element E1, and the driving circuit 20 is used for generating a driving current for driving the light-emitting element E1 under the control of the potential of the first node N1.

[0196] The driving control circuit comprises a first light-emitting control circuit 71, a data write circuit 72, a first reset circuit 73, and a second reset circuit 74.

[0197] The first light emitting control circuit 71 is electrically connected with a first light emitting control line EM1, a power voltage line ELVDD and a first end of the driving circuit 20, for controlling the power voltage line ELVDD and the first end of the driving circuit 20 to be connected or disconnected under the control of a first light emitting control signal provided by the first light emitting control line EM1;

[0198] The data writing circuit 72 is electrically connected with a scanning line GT, a data line DL and a writing node NW, for controlling the data line DL and the writing node NW to be connected or disconnected under the control of a scanning signal provided by the scanning line GT; the writing node NW is electrically connected with the first node N1;

[0199] The first reset circuit 73 is electrically connected with a first reset control line R1, the reference voltage line REF and the first node N1, for controlling the reference voltage line REF and the first node N1 to be connected or disconnected under the control of a first reset control signal provided by the first reset control line R1;

[0200] The second reset circuit 74 is electrically connected with a second reset control line R2, an initial voltage line I1 and a reset node NR, for controlling the initial voltage line I1 and the reset node NR to be connected or disconnected under the control of a second reset control signal provided by the second reset control line R2;

[0201] The pixel circuit further comprises a first energy storage circuit 81, a second energy storage circuit 82 and a third reset circuit 83.

[0202] The first energy storage circuit 81 is electrically connected with the writing node NW and an intermediate node NZ, for storing energy;

[0203] The second energy storage circuit 82 is electrically connected with the intermediate node NZ and a second end of the driving circuit 20, for storing energy;

[0204] The third reset circuit 83 is electrically connected with a third reset control line R3, the reference voltage line REF and the intermediate node NZ, for controlling the reference voltage line REF and the intermediate node NZ to be connected or disconnected under the control of a third reset control signal provided by the third reset control line R3;

[0205] The pixel circuit further comprises a second light emitting control circuit 84.

[0206] The reset node NR is electrically connected with the second end of the driving circuit 20 through the second light emitting control circuit 84; the reset node NR is electrically connected with the first pole of the light emitting element E1, and the second pole of the light emitting element E1 is electrically connected with the low voltage line ELVSS;

[0207] The control end of the second light emitting control circuit 84 is electrically connected with the second light emitting control line EM2, and the second light emitting control circuit 84 is used for controlling the communication or disconnection between the reset node NR and the second end of the driving circuit 20 under the control of the second light emitting control signal provided by the second light emitting control line EM2.

[0208] As shown in FIG. 7, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test end is electrically connected with the initial voltage line I1, and the second test end is electrically connected with the second test node; the second test node is electrically connected with the first node N1;

[0209] The pixel driving circuit comprises a driving circuit 20 and a driving control circuit;

[0210] The control end of the driving circuit 20 is electrically connected with the first node N1; the first end of the driving circuit 20 is electrically connected with the first test node NC1, the second end of the driving circuit 20 is electrically connected with the light emitting element E1, and the driving circuit 20 is used for generating a driving current for driving the light emitting element E1 under the control of the potential of the first node N1;

[0211] The driving control circuit comprises a first light emitting control circuit 71, a data writing circuit 72, a first reset circuit 73 and a second reset circuit 74;

[0212] The first light emitting control circuit 71 is electrically connected with the first light emitting control line EM1, the power voltage line ELVDD and the first end of the driving circuit 20 respectively, and is used for controlling the communication or disconnection between the power voltage line ELVDD and the first end of the driving circuit 20 under the control of the first light emitting control signal provided by the first light emitting control line EM1;

[0213] The data writing circuit 72 is electrically connected with the scanning line GT, the data line DL and the writing node NW respectively, and is used for controlling the communication or disconnection between the data line DL and the writing node NW under the control of the scanning signal provided by the scanning line GT; the writing node NW is electrically connected with the first node N1;

[0214] The first reset circuit 73 is electrically connected with the first reset control line R1, the reference voltage line REF and the first node N1 respectively, and is configured to control the reference voltage line REF and the first node N1 to be connected or disconnected under the control of a first reset control signal provided by the first reset control line R1.

[0215] The second reset circuit 74 is electrically connected with the second reset control line R2, the initial voltage line I1 and the reset node NR respectively, and is configured to control the initial voltage line I1 and the reset node NR to be connected or disconnected under the control of a second reset control signal provided by the second reset control line R2. The reset node NR is electrically connected with the second end of the driving circuit 20.

[0216] The pixel circuit further includes a first energy storage circuit 81 and a second energy storage circuit 82.

[0217] The first energy storage circuit 81 is electrically connected with the first node N1 and the second end of the driving circuit 20 respectively, and is configured to store electric energy.

[0218] The second energy storage circuit 82 is electrically connected with the power voltage line ELVDD and the second end of the driving circuit 20 respectively, and is configured to store electric energy.

[0219] As shown in FIG. 8, on the basis of at least one embodiment of the pixel circuit shown in FIG. 1, the first test terminal is electrically connected with the initial voltage line I1, and the second test terminal is electrically connected with the data line DL.

[0220] The pixel driving circuit includes a driving circuit 20 and a driving control circuit.

[0221] The control end of the driving circuit 20 is electrically connected with the first node N1. The first end of the driving circuit 20 is electrically connected with the first test node NC1, and the second end of the driving circuit 20 is electrically connected with the light emitting element E1. The driving circuit 20 is configured to generate a driving current for driving the light emitting element E1 under the control of the potential of the first node N1.

[0222] The driving control circuit includes a first light emitting control circuit 71, a data writing circuit 72, a first reset circuit 73 and a second reset circuit 74.

[0223] The first light emitting control circuit 71 is electrically connected with the first light emitting control line EM1, the power voltage line ELVDD and the first end of the driving circuit 20 respectively, and is configured to control the power voltage line ELVDD and the first end of the driving circuit 20 to be connected or disconnected under the control of a first light emitting control signal provided by the first light emitting control line EM1.

[0224] The data writing circuit 72 is electrically connected with the scan line GT, the data line DL and the write node NW respectively, and is configured to control the data line DL to be connected or disconnected with the write node NW under the control of a scan signal provided by the scan line GT; the write node NW is electrically connected with the first node N1;

[0225] The first reset circuit 73 is electrically connected with the first reset control line R1, the reference voltage line REF and the first node N1 respectively, and is configured to control the reference voltage line REF to be connected or disconnected with the first node N1 under the control of a first reset control signal provided by the first reset control line R1;

[0226] The second reset circuit 74 is electrically connected with the second reset control line R2, the initial voltage line I1 and the reset node NR respectively, and is configured to control the initial voltage line I1 to be connected or disconnected with the reset node NR under the control of a second reset control signal provided by the second reset control line R2; the reset node NR is electrically connected with the second end of the driving circuit 20;

[0227] The pixel circuit further comprises a first energy storage circuit 81 and a second energy storage circuit 82;

[0228] The first energy storage circuit 81 is electrically connected with the first node N1 and the second end of the driving circuit 20 respectively, and is configured to store electric energy;

[0229] The second energy storage circuit 82 is electrically connected with the power voltage line ELVDD and the second end of the driving circuit 20 respectively, and is configured to store electric energy.

[0230] Optionally, the driving circuit comprises a driving transistor, the first light emitting control circuit comprises a first transistor, the data writing circuit comprises a second transistor, the first reset circuit comprises a third transistor, and the second reset circuit comprises a fourth transistor;

[0231] The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the first test node, and the second pole of the driving transistor is electrically connected with the light emitting element;

[0232] The gate of the first transistor is electrically connected with the first light emitting control line, the first pole of the first transistor is electrically connected with the power voltage line, and the second pole of the first transistor is electrically connected with the first pole of the driving transistor;

[0233] The gate of the second transistor is electrically connected with the scan line, the first pole of the second transistor is electrically connected with the data line, and the second pole of the second transistor is electrically connected with the write node;

[0234] a gate of the third transistor is electrically connected with the first reset control line, a first pole of the third transistor is electrically connected with the reference voltage line, and a second pole of the third transistor is electrically connected with the first node;

[0235] a gate of the fourth transistor is electrically connected with the second reset control line, a first pole of the fourth transistor is electrically connected with the initial voltage line, and a second pole of the fourth transistor is electrically connected with the reset node.

[0236] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor.

[0237] a first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with the second end of the driving circuit.

[0238] a first end of the second capacitor is electrically connected with the power voltage line, and a second end of the second capacitor is electrically connected with the second end of the driving circuit.

[0239] Optionally, the first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; and the third reset circuit includes a fifth transistor.

[0240] a first end of the first capacitor is electrically connected with the write node, and a second end of the first capacitor is electrically connected with the intermediate node.

[0241] a first end of the second capacitor is electrically connected with the intermediate node, and a second end of the second capacitor is electrically connected with the second end of the driving circuit.

[0242] a gate of the fifth transistor is electrically connected with the third reset control line, a first pole of the fifth transistor is electrically connected with the reference voltage line, and a second pole of the fifth transistor is electrically connected with the intermediate node.

[0243] Optionally, the switch control circuit includes a sixth transistor.

[0244] a gate of the sixth transistor is electrically connected with the switch control line, a first pole of the sixth transistor is electrically connected with the first node, and a second pole of the sixth transistor is electrically connected with the write node.

[0245] Optionally, the second light-emitting control circuit includes a seventh transistor.

[0246] a gate of the seventh transistor is electrically connected with the second light-emitting control line, a first pole of the seventh transistor is electrically connected with the second end of the driving circuit, and a second pole of the seventh transistor is electrically connected with the reset node.

[0247] As shown in Fig. 9, on the basis of at least one embodiment of the pixel circuit shown in Fig. 2, the light emitting element is an organic light emitting diode O1; the test switch circuit comprises a test switch transistor T0;

[0248] The gate of the test switch transistor T0 is electrically connected with the test control terminal AT, the drain of the test switch transistor T0 is electrically connected with the reference voltage line REF, and the source of the test switch transistor T0 is electrically connected with the power voltage line ELVDD;

[0249] The driving circuit comprises a driving transistor DT, the first light emitting control circuit comprises a first transistor T1, the data writing circuit comprises a second transistor T2, the first reset circuit comprises a third transistor T3, and the second reset circuit comprises a fourth transistor T4;

[0250] The gate of the driving transistor DT is electrically connected with the first node N1, and the source of the driving transistor DT is electrically connected with the anode of O1;

[0251] The gate of the first transistor T1 is electrically connected with the first light emitting control line EM1, the drain of the first transistor T1 is electrically connected with the power voltage line ELVDD, and the source of the first transistor T1 is electrically connected with the drain of the driving transistor DT;

[0252] The gate of the second transistor T2 is electrically connected with the scanning line GT, the drain of the second transistor T2 is electrically connected with the data line DL, and the source of the second transistor T2 is electrically connected with the first node N1;

[0253] The gate of the third transistor T3 is electrically connected with the first reset control line R1, the drain of the third transistor T3 is electrically connected with the reference voltage line REF, and the source of the third transistor T3 is electrically connected with the first node N1;

[0254] The gate of the fourth transistor T4 is electrically connected with the second reset control line R2, the drain of the fourth transistor T4 is electrically connected with the initial voltage line I1, and the source of the fourth transistor T4 is electrically connected with the anode of O1;

[0255] The first energy storage circuit comprises a first capacitor C1, and the second energy storage circuit comprises a second capacitor C2;

[0256] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the anode of O1;

[0257] A first end of the second capacitor C2 is electrically connected to the power supply voltage line ELVDD, and a second end of the second capacitor C2 is electrically connected to an anode of O1; a cathode of O1 is electrically connected to the low voltage line ELVSS.

[0258] In at least one embodiment of the pixel circuit shown in FIG. 9, all the transistors are n-type transistors, but the present disclosure is not limited thereto.

[0259] FIG. 10A is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 9.

[0260] As shown in FIG. 10A, in at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, in the detection stage S0, EM1 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, and AT provides a high voltage signal, as shown in FIG. 10B, T1 is open, T0 is open, T3 is open, T2 is open, T4 is open, and DT is open, forming a current path from I1, T4, DT, T1, T0, T3, and T2 to DL, and by detecting the current in the current path, the performance of each transistor in the current path can be detected.

[0261] At least one embodiment of the pixel circuit shown in FIG. 11A is different from at least one embodiment of the pixel circuit shown in FIG. 9 as follows: the source of T0 is electrically connected to the first test node NC1.

[0262] As shown in FIG. 10A, in at least one embodiment of the pixel circuit shown in FIG. 9 of the present disclosure, in the detection stage S0, EM1 provides a high voltage signal, R2 provides a high voltage signal, R1 provides a high voltage signal, GT provides a high voltage signal, and AT provides a high voltage signal, as shown in FIG. 10B, T1 is open, T0 is open, T3 is open, T2 is open, T4 is open, and DT is open, forming a current path from I1, T4, DT, T1, T0, T3, and T2 to DL, and by detecting the current in the current path, the performance of each transistor in the current path can be detected.

[0263] As shown in FIG. 12, based on at least one embodiment of the pixel circuit shown in FIG. 4, the light emitting element is an organic light emitting diode O1; the test switch circuit includes a test switch transistor T0;

[0264] The gate of the test switch transistor T0 is electrically connected to the test control end AT, the drain of the test switch transistor T0 is electrically connected to the reference voltage line REF, and the source of the test switch transistor T0 is electrically connected to the power supply voltage line ELVDD;

[0265] The driving circuit comprises a driving transistor DT, the first light-emitting control circuit comprises a first transistor T1, the data writing circuit comprises a second transistor T2, the first reset circuit comprises a third transistor T3, and the second reset circuit comprises a fourth transistor T4;

[0266] The gate of the driving transistor DT is electrically connected with the first node N1, and the source of the driving transistor DT is electrically connected with the anode of O1;

[0267] The gate of the first transistor T1 is electrically connected with the first light-emitting control line EM1, the drain of the first transistor T1 is electrically connected with the power voltage line ELVDD, and the source of the first transistor T1 is electrically connected with the drain of the driving transistor DT;

[0268] The gate of the second transistor T2 is electrically connected with the scanning line GT, the drain of the second transistor T2 is electrically connected with the data line DL, and the source of the second transistor T2 is electrically connected with the writing node NW;

[0269] The gate of the third transistor T3 is electrically connected with the first reset control line R1, the drain of the third transistor T3 is electrically connected with the reference voltage line REF, and the source of the third transistor T3 is electrically connected with the first node N1;

[0270] The gate of the fourth transistor T4 is electrically connected with the second reset control line R2, the drain of the fourth transistor T4 is electrically connected with the initial voltage line I1, and the source of the fourth transistor T4 is electrically connected with the anode of O1;

[0271] The first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the third reset circuit comprises a fifth transistor T5;

[0272] The first end of the first capacitor C1 is electrically connected with the writing node NW, and the second end of the first capacitor C1 is electrically connected with the intermediate node NZ;

[0273] The first end of the second capacitor C2 is electrically connected with the intermediate node NZ, and the second end of the second capacitor C2 is electrically connected with the anode of O1;

[0274] The gate of the fifth transistor T5 is electrically connected with the first reset control line R1, the drain of the fifth transistor T5 is electrically connected with the reference voltage line REF, and the source of the fifth transistor T5 is electrically connected with the intermediate node NZ;

[0275] The switch control circuit comprises a sixth transistor T6;

[0276] The gate of the sixth transistor T6 is electrically connected with a second emission control line EM2, the drain of the sixth transistor T6 is electrically connected with the first node N1, and the source of the sixth transistor T6 is electrically connected with the write node NW.

[0277] In at least one embodiment of the pixel circuit shown in FIG. 12, all the transistors are n-type transistors, but the present disclosure is not limited thereto.

[0278] FIG. 13A is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 12.

[0279] As shown in FIG. 13A, at least one embodiment of the pixel circuit shown in FIG. 12 of the present disclosure works as follows. In the detection stage S0, EM2, EM1, R2, R1, GT and AT all provide high voltage signals, T0, T1, T2, T3, T4, T5, T6 and DT are turned on, as shown in FIG. 13B, a current path from I1, T4, DT, T1, T0, T3, T6 and T2 to DL is formed, and by detecting the current in the current path, the performance of each transistor in the current path can be detected.

[0280] As shown in FIG. 14, based on at least one embodiment of the pixel circuit shown in FIG. 5, the light emitting element is an organic light emitting diode O1; the test switch circuit includes a test switch transistor T0;

[0281] The gate of the test switch transistor T0 is electrically connected with the test control terminal AT, the drain of the test switch transistor T0 is electrically connected with a reference voltage line REF, and the source of the test switch transistor T0 is electrically connected with a power voltage line ELVDD.

[0282] The driving circuit includes a driving transistor DT, the first emission control circuit includes a first transistor T1, the data write circuit includes a second transistor T2, the first reset circuit includes a third transistor T3, and the second reset circuit includes a fourth transistor T4.

[0283] The gate of the driving transistor DT is electrically connected with the first node N1, and the source of the driving transistor DT is electrically connected with the anode of O1.

[0284] The gate of the first transistor T1 is electrically connected with the first emission control line EM1, the drain of the first transistor T1 is electrically connected with the power voltage line ELVDD, and the source of the first transistor T1 is electrically connected with the drain of the driving transistor DT.

[0285] The gate of the second transistor T2 is electrically connected with the scan line GT, the drain of the second transistor T2 is electrically connected with the data line DL, and the source of the second transistor T2 is electrically connected with the first node N1.

[0286] The gate of the third transistor T3 is electrically connected with the first reset control line R1, the drain of the third transistor T3 is electrically connected with the reference voltage line REF, and the source of the third transistor T3 is electrically connected with the first node N1;

[0287] The gate of the fourth transistor T4 is electrically connected with the second reset control line R2, the drain of the fourth transistor T4 is electrically connected with the initial voltage line I1, and the source of the fourth transistor T4 is electrically connected with the anode of O1;

[0288] The first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the third reset circuit comprises a fifth transistor T5;

[0289] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the intermediate node NZ;

[0290] The first end of the second capacitor C2 is electrically connected with the intermediate node NZ, and the second end of the second capacitor C2 is electrically connected with the anode of O1;

[0291] The gate of the fifth transistor T5 is electrically connected with the first reset control line R1, the drain of the fifth transistor T5 is electrically connected with the reference voltage line REF, and the source of the fifth transistor T5 is electrically connected with the intermediate node NZ.

[0292] In at least one embodiment of the pixel circuit shown in FIG. 14, all transistors are n-type transistors, but the present disclosure is not limited thereto.

[0293] FIG. 15A is a working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 14.

[0294] As shown in FIG. 15A, at least one embodiment of the pixel circuit shown in FIG. 14 of the present disclosure works as follows. In the detection stage S0, EM2, EM1, R2, R1, GT and AT all provide high voltage signals, T0, T1, T2, T3, T4, T5 and DT are all turned on, as shown in FIG. 15B, a current path from I1, T4, DT, T1, T0, T3 and T2 to DL is formed, and by detecting the current in the current path, the performance of each transistor in the current path can be detected.

[0295] As shown in FIG. 16A, based on at least one embodiment of the pixel circuit shown in FIG. 6, the light emitting element is an organic light emitting diode O1, and the test switch circuit comprises a test switch transistor T0;

[0296] The gate of the test switch transistor T0 is electrically connected with the test control end AT, the drain of the test switch transistor T0 is electrically connected with the reference voltage line REF, and the source of the test switch transistor T0 is electrically connected with the power supply voltage line ELVDD.

[0297] The driving circuit comprises a driving transistor DT, the first light-emitting control circuit comprises a first transistor T1, the data writing circuit comprises a second transistor T2, the first reset circuit comprises a third transistor T3, and the second reset circuit comprises a fourth transistor T4.

[0298] The gate of the driving transistor DT is electrically connected with the first node N1, and the source of the driving transistor DT is electrically connected with the anode of O1.

[0299] The gate of the first transistor T1 is electrically connected with the first light-emitting control line EM1, the drain of the first transistor T1 is electrically connected with the power supply voltage line ELVDD, and the source of the first transistor T1 is electrically connected with the drain of the driving transistor DT.

[0300] The gate of the second transistor T2 is electrically connected with the scanning line GT, the drain of the second transistor T2 is electrically connected with the data line DL, and the source of the second transistor T2 is electrically connected with the first node N1.

[0301] The gate of the third transistor T3 is electrically connected with the first reset control line R1, the drain of the third transistor T3 is electrically connected with the reference voltage line REF, and the source of the third transistor T3 is electrically connected with the first node N1.

[0302] The gate of the fourth transistor T4 is electrically connected with the second reset control line R2, the drain of the fourth transistor T4 is electrically connected with the initial voltage line I1, and the source of the fourth transistor T4 is electrically connected with the anode of O1.

[0303] The first energy storage circuit comprises a first capacitor C1, the second energy storage circuit comprises a second capacitor C2, and the third reset circuit comprises a fifth transistor T5.

[0304] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the intermediate node NZ.

[0305] The first end of the second capacitor C2 is electrically connected with the intermediate node NZ, and the second end of the second capacitor C2 is electrically connected with the source of DT.

[0306] The gate of the fifth transistor T5 is electrically connected with the first reset control line R1, the drain of the fifth transistor T5 is electrically connected with the reference voltage line REF, and the source of the fifth transistor T5 is electrically connected with the intermediate node NZ.

[0307] The second light-emitting control circuit includes a seventh transistor T7.

[0308] The gate of the seventh transistor T7 is electrically connected with the second light-emitting control line EM2, the drain of the seventh transistor T7 is electrically connected with the source of the driving transistor DT, and the source of the seventh transistor T7 is electrically connected with the anode of O1.

[0309] In at least one embodiment of the pixel circuit shown in FIG. 16A, all the transistors are n-type transistors, but the present disclosure is not limited thereto.

[0310] In at least one embodiment of the pixel circuit shown in FIG. 16A, in the detection stage, EM1, EM2, R1, R2, GT and AT all provide high voltage signals, and DT, T0, T1, T2, T3, T4 and T5 are all turned on, as shown in FIG. 16B, forming a current path flowing from I1, T4, T7, DT, T1, T0, T3 and T2 to DL, and by detecting the current in the current path, the performance of each transistor in the current path can be detected.

[0311] As shown in FIG. 17, on the basis of at least one embodiment of the pixel circuit shown in FIG. 7, the light-emitting element is an organic light-emitting diode O1; and the test switch circuit includes a test switch transistor T0.

[0312] The gate of the test switch transistor T0 is electrically connected with the test control terminal AT, the drain of the test switch transistor T0 is electrically connected with the first node N1, and the source of the test switch transistor T0 is electrically connected with the initial voltage line I1.

[0313] The driving circuit includes a driving transistor DT, the first light-emitting control circuit includes a first transistor T1, the data writing circuit includes a second transistor T2, the first reset circuit includes a third transistor T3, and the second reset circuit includes a fourth transistor T4.

[0314] The gate of the driving transistor DT is electrically connected with the first node N1, and the source of the driving transistor DT is electrically connected with the anode of O1.

[0315] The gate of the first transistor T1 is electrically connected with the first light-emitting control line EM1, the drain of the first transistor T1 is electrically connected with the power voltage line ELVDD, and the source of the first transistor T1 is electrically connected with the drain of the driving transistor DT.

[0316] The gate of the second transistor T2 is electrically connected with the scan line GT, the drain of the second transistor T2 is electrically connected with the data line DL, and the source of the second transistor T2 is electrically connected with the first node N1;

[0317] The gate of the third transistor T3 is electrically connected with the first reset control line R1, the drain of the third transistor T3 is electrically connected with the reference voltage line REF, and the source of the third transistor T3 is electrically connected with the first node N1;

[0318] The gate of the fourth transistor T4 is electrically connected with the second reset control line R2, the drain of the fourth transistor T4 is electrically connected with the initial voltage line I1, and the source of the fourth transistor T4 is electrically connected with the anode of O1;

[0319] The first energy storage circuit includes a first capacitor C1, and the second energy storage circuit includes a second capacitor C2;

[0320] The first end of the first capacitor C1 is electrically connected with the first node N1, and the second end of the first capacitor C1 is electrically connected with the anode of O1;

[0321] The first end of the second capacitor C2 is electrically connected with the power voltage line ELVDD, and the second end of the second capacitor C2 is electrically connected with the anode of O1.

[0322] In at least one embodiment of the pixel circuit shown in FIG. 17, all transistors are n-type transistors, but the present disclosure is not limited thereto.

[0323] FIG. 18A is a first working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 17; and FIG. 18B is a first working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 17.

[0324] As shown in FIG. 18A, in at least one embodiment of the pixel circuit shown in FIG. 17 of the present disclosure, in the detection stage S0, EM1, R2 and AT provide low voltage signals, R1 and GT provide high voltage signals, T3 and T2 are turned on, as shown in FIG. 18C, a first current path from REF, T3 and T2 to DL is formed, and by detecting the current on the first current path, the performance of each transistor on the first current path can be detected.

[0325] As shown in FIG. 18B, at least one embodiment of the pixel circuit shown in FIG. 17, when working, in the detection stage S0, EM1, R2, GT and AT all provide high voltage signals, R1 provides a low voltage signal, T1 is open, DT is open, T0 is open, T2 is open, and T4 is open, as shown in FIG. 18D, a second current path from ELVDD, T1, DT, T4, T0 and T2 to DL is formed, and by detecting the current on the second current path, the performance of each transistor on the second current path can be detected.

[0326] At least one embodiment of the pixel circuit shown in FIG. 19 is different from at least one embodiment of the pixel circuit shown in FIG. 17 as follows:

[0327] The drain of T0 is electrically connected with the data line DL.

[0328] FIG. 20A is a first working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19; and FIG. 20B is a second working timing diagram of at least one embodiment of the pixel circuit shown in FIG. 19.

[0329] As shown in FIG. 20A, at least one embodiment of the pixel circuit shown in FIG. 19, when working, in the detection stage S0, EM1, R2 and AT all provide low voltage signals, R1 and GT provide high voltage signals, T3 and T2 are open, as shown in FIG. 20C, a first current path from REF, T3 and T2 to DL is formed, and by detecting the current on the first current path, the performance of each transistor on the first current path can be detected.

[0330] As shown in FIG. 20B, at least one embodiment of the pixel circuit shown in FIG. 19, when working, in the detection stage S0, EM1, R2, R1, GT and AT all provide high voltage signals, T1, DT, T4, T0, T2 and T3 are all open, as shown in FIG. 20C, a second current path from ELVSS, T1, DT, T4 and T0 to DL is formed, and by detecting the current on the second current path, the performance of each transistor on the second current path can be detected.

[0331] The test method of the pixel circuit according to the embodiments of the present disclosure is applied to the pixel circuit described above, and the test method comprises:

[0332] In the detection stage, a valid test control signal is provided to the test control end, and the test switch circuit is controlled by the test control signal to control the communication between the first test end and the second test end.

[0333] In the pixel driving method, in the detection stage, the test switch circuit is controlled by the test control signal to connect the first test terminal and the second test terminal to form a current path, and the performance of each transistor in the current path can be detected by detecting the current in the current path.

[0334] In at least one embodiment of the present disclosure, the test method further comprises:

[0335] In the display stage, an invalid test control signal is provided to the test control terminal, the test switch circuit is controlled by the test control signal to disconnect the first test terminal and the second test terminal, and the pixel driving circuit generates a driving current to drive the light emitting element.

[0336] Optionally, the pixel driving circuit comprises a driving circuit and a driving control circuit, and the test method comprises:

[0337] In the detection stage, the driving control circuit controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit.

[0338] In a specific implementation, the pixel driving circuit can comprise a driving circuit and a driving control circuit, when the test switch circuit controls the connection between the first test terminal and the second test terminal, the driving control circuit controls the connection between the control terminal of the driving circuit and the first terminal of the driving circuit, detects the current flowing through the driving circuit, and according to the detection result, the performance of the driving transistor included in the driving circuit can be detected to perform an array test on the pixel circuit.

[0339] The display device comprises the pixel circuit.

[0340] The display panel comprises a plurality of rows and columns of pixel circuits, a plurality of first direct current voltage lines, and a plurality of second direct current voltage lines, the plurality of rows and columns of pixel circuits are arranged in a display area, the display panel further comprises a test switch module arranged in a frame area, and the test switch module comprises a plurality of test switch circuits.

[0341] The test switch circuit is electrically connected with a test control terminal, a first direct current voltage line, and a second direct current voltage line, and is used to control the connection or disconnection between the first direct current voltage line and the second direct current voltage line under the control of a test control signal provided by the test control terminal.

[0342] Optionally, the first direct current voltage line can be a reference voltage line, and the second direct current voltage line can be a power voltage line; in specific implementation, a test switch circuit can be arranged between the reference voltage line and the direct current voltage line, the first direct current voltage line and the second direct current voltage line can be arranged in a first direction, for example, a horizontal direction; the frame region can include a first frame region and a second frame region, the first frame region can be arranged on the left side of the display region, and the second frame region can be arranged on the right side of the display region; the test switch circuit can be arranged in the first frame region and / or the second frame region, without occupying the space of the display region, which is beneficial to ensuring the PPI (pixel density).

[0343] In at least one embodiment of the present disclosure, the test switch circuit can not be arranged in each pixel circuit, and only one or two test switch circuits need to be arranged for each row of pixel circuits.

[0344] In at least one embodiment of the present disclosure, the first direct current voltage line and the second direct current voltage line both extend in a first direction; the display panel includes N rows of pixel circuits; the pixel circuits located in the nth row are respectively electrically connected with the nth first direct current voltage line and the nth second direct current voltage line; N is an integer greater than 1, and n is a positive integer less than or equal to N;

[0345] The test switch module includes N test switch circuits;

[0346] The nth test switch circuit is respectively electrically connected with the nth test control end, the nth first direct current voltage line and the nth second direct current voltage line, and is used for controlling the communication or disconnection between the nth first direct current voltage line and the nth second direct current voltage line under the control of the nth test control signal provided by the nth test control end.

[0347] As shown in FIG. 21, A0 is the display region, B1 is the first frame region, and B2 is the second frame region;

[0348] P11 is the first row and the first column of pixel circuits, P12 is the first row and the second column of pixel circuits, P1M-1 is the first row and the M-1th column of pixel circuits, and P1M is the first row and the Mth column of pixel circuits;

[0349] P21 is the second row and the first column of pixel circuits, P22 is the second row and the second column of pixel circuits, P2M-1 is the second row and the M-1th column of pixel circuits, and P2M is the second row and the Mth column of pixel circuits;

[0350] P31 is a pixel circuit in the first column of the third row, P32 is a pixel circuit in the second column of the third row, P3M-1 is a pixel circuit in the M-1th column of the third row, and P3M is a pixel circuit in the Mth column of the third row;

[0351] PN-11 is a pixel circuit in the first column of the N-1th row, PN-12 is a pixel circuit in the second column of the N-1th row, P N-1M-1 is a pixel circuit in the M-1th column of the N-1th row, and P N-1M is a pixel circuit in the Mth column of the N-1th row;

[0352] PN1 is a pixel circuit in the first column of the Nth row, PN2 is a pixel circuit in the second column of the Nth row, P NM-1 is a pixel circuit in the M-1th column of the Nth row, and P NM is a pixel circuit in the Mth column of the Nth row;

[0353] N and M are integers greater than 1;

[0354] The pixel circuits in the first row are electrically connected with a first reference voltage line REF1 and a first power voltage line ELVDD1 respectively;

[0355] The pixel circuits in the second row are electrically connected with a second reference voltage line REF2 and a second power voltage line ELVDD2 respectively;

[0356] The pixel circuits in the third row are electrically connected with a third reference voltage line REF3 and a third power voltage line ELVDD3 respectively;

[0357] The pixel circuits in the N-1th row are electrically connected with an N-1th reference voltage line REFN-1 and an N-1th power voltage line ELVDDN-1 respectively;

[0358] The pixel circuits in the Nth row are electrically connected with an Nth reference voltage line REFN and an Nth power voltage line ELVDDN respectively;

[0359] The test switch module includes N test switch circuits; the first test switch circuit includes a first test switch transistor T01, the second test switch circuit includes a second test switch transistor T02, the third test switch circuit includes a third test switch transistor T03, the N-1th test switch circuit includes an N-1th test switch transistor T0N-1, and the Nth test switch circuit includes an Nth test switch transistor T0N;

[0360] The gate of T01 is electrically connected with a first test control end AT1, the drain of T01 is electrically connected with REF1, and the source of T01 is electrically connected with ELVDD1;

[0361] The gate of T02 is electrically connected with a second test control end AT2, the drain of T02 is electrically connected with REF2, and the source of T02 is electrically connected with ELVDD2;

[0362] The gate of T03 is electrically connected with a third test control end AT3, the drain of T03 is electrically connected with REF3, and the source of T03 is electrically connected with ELVDD3;

[0363] The gate of T0N-1 is electrically connected with an (N-1)th test control end ATN-1, the drain of T0N-1 is electrically connected with REF N-1, and the source of T0N-1 is electrically connected with ELVDDN-1;

[0364] The gate of T0N is electrically connected with an Nth test control end ATN, the drain of T0N is electrically connected with REFN, and the source of T0N is electrically connected with ELVDDN;

[0365] T01, T02, T03, T0N-1 and T0N are arranged in the second frame area B2.

[0366] In at least one embodiment shown in FIG. 21, each test switch transistor can also be replaced and arranged in the first frame area, or each test switch transistor can be arranged in the first frame area and the second frame area.

[0367] The display panel disclosed in at least one embodiment of the present disclosure includes N rows of pixel circuits; the pixel circuits in the nth row are respectively electrically connected with the nth first direct-current voltage line and the nth second direct-current voltage line; N is an integer greater than 1, n is a positive integer less than or equal to N; m is a positive integer less than N;

[0368] The test switch module includes at least one test switch circuit;

[0369] The mth test switch circuit is respectively electrically connected with the mth test control end, the mth first direct-current voltage line and the (m+1)th second direct-current voltage line, and is used for controlling the communication or disconnection between the mth first direct-current voltage line and the (m+1)th second direct-current voltage line under the control of the mth test control signal provided by the mth test control end.

[0370] As shown in FIG. 22, A0 is a display area, B1 is a first frame area, and B2 is a second frame area;

[0371] P11 is a first row and a first column of pixel circuits, P12 is a first row and a second column of pixel circuits, P1M-1 is a first row and an (M-1)th column of pixel circuits, and P1M is a first row and an Mth column of pixel circuits;

[0372] P21 is a pixel circuit in the first row and the first column, P22 is a pixel circuit in the first row and the second column, P2M-1 is a pixel circuit in the first row and the M-1th column, and P2M is a pixel circuit in the first row and the Mth column;

[0373] P31 is a pixel circuit in the third row and the first column, P32 is a pixel circuit in the third row and the second column, P3M-1 is a pixel circuit in the third row and the M-1th column, and P3M is a pixel circuit in the third row and the Mth column;

[0374] PN-11 is a pixel circuit in the N-1th row and the first column, PN-12 is a pixel circuit in the N-1th row and the second column, PN-1M-1 is a pixel circuit in the N-1th row and the M-1th column, and PN-1M is a pixel circuit in the N-1th row and the Mth column;

[0375] PN1 is a pixel circuit in the Nth row and the first column, PN2 is a pixel circuit in the Nth row and the second column, PN M-1 is a pixel circuit in the Nth row and the M-1th column, and PN M is a pixel circuit in the Nth row and the Mth column;

[0376] N and M are integers greater than 1;

[0377] The pixel circuits in the first row are electrically connected with a first reference voltage line REF1 and a first power voltage line ELVDD1 respectively;

[0378] The pixel circuits in the second row are electrically connected with a second reference voltage line REF2 and a second power voltage line ELVDD2 respectively;

[0379] The pixel circuits in the third row are electrically connected with a third reference voltage line REF3 and a third power voltage line ELVDD3 respectively;

[0380] The pixel circuits in the N-1th row are electrically connected with an N-1th reference voltage line REFN-1 and an N-1th power voltage line ELVDDN-1 respectively;

[0381] The pixel circuits in the Nth row are electrically connected with an Nth reference voltage line REFN and an Nth power voltage line ELVDDN respectively;

[0382] The test switch module comprises at least one test switch circuit; the first test switch circuit comprises a first test switch transistor T01, the second test switch circuit comprises a second test switch transistor T02, and the N-1th test switch circuit comprises an N-1th test switch transistor T0N-1;

[0383] The gate of T01 is electrically connected with a first test control end AT1, the drain of T01 is electrically connected with ELVDD1, and the source of T01 is electrically connected with REF2;

[0384] The gate of T02 is electrically connected with a second test control end AT2, the drain of T02 is electrically connected with ELVDD2, and the source of T02 is electrically connected with REF3;

[0385] The gate of T0N-1 is electrically connected with an N-1th test control end ATN-1, the drain of T0N-1 is electrically connected with ELVDDN-1, and the source of T0N-1 is electrically connected with REFN;

[0386] T01, T02 and T0N-1 are arranged in the second frame area B2.

[0387] In at least one embodiment shown in FIG. 22, each test switch transistor can also be replaced by being arranged in the first frame area, or each test switch transistor can be arranged in the first frame area and the second frame area.

[0388] In at least one embodiment of the present disclosure, the first direct-current voltage line includes a plurality of rows of first direct-current voltage line parts and a plurality of columns of second direct-current voltage line parts which are electrically connected with each other, and the second direct-current voltage line includes a plurality of rows of third direct-current voltage line parts and a plurality of columns of fourth direct-current voltage line parts which are electrically connected with each other;

[0389] The extension direction of the first direct-current voltage line part is the same as the extension direction of the third direct-current voltage line part, the extension direction of the second direct-current voltage line part is the same as the extension direction of the fourth direct-current voltage line part, and the extension direction of the first direct-current voltage line part intersects with the extension direction of the second direct-current voltage line part;

[0390] The test switch module includes a plurality of first test switch circuits and a plurality of second test switch circuits;

[0391] The first test switch circuit is electrically connected with a corresponding test control end, a row of the first direct-current voltage line part and a row of the third direct-current voltage line part respectively, and is used for controlling the communication or disconnection between the row of first direct-current voltage line part and the row of third direct-current voltage line part under the control of a test control signal provided by the test control end;

[0392] The second test switch circuit is electrically connected with a corresponding test control end, a column of the second direct-current voltage line part and a column of the fourth direct-current voltage line part respectively, and is used for controlling the communication or disconnection between the column of second direct-current voltage line part and the column of fourth direct-current voltage line part under the control of a test control signal provided by the test control end.

[0393] In a specific implementation, the first direct-current voltage lines can include a plurality of rows of first direct-current voltage line portions and a plurality of columns of second direct-current voltage line portions that are electrically connected to each other, and the second direct-current voltage lines include a plurality of rows of third direct-current voltage line portions and a plurality of columns of fourth direct-current voltage line portions that are electrically connected to each other; the first direct-current voltage line portions and the third direct-current voltage line portions can extend in a horizontal direction, the second direct-current voltage line portions and the fourth direct-current voltage line portions can extend in a vertical direction, the plurality of rows of first direct-current voltage line portions and the plurality of columns of second direct-current voltage line portions form a grid structure, the plurality of rows of third direct-current voltage line portions and the plurality of columns of fourth direct-current voltage line portions form a grid structure, the bezel region can include a first bezel region, a second bezel region, a third bezel region, and a fourth bezel region, the first bezel region can be disposed on the left side of the display region, the second bezel region can be disposed on the right side of the display region, the third bezel region can be disposed on the upper side of the display region, and the fourth bezel region can be disposed on the lower side of the display region; each test switch circuit can be disposed in at least one of the first bezel region, the second bezel region, the third bezel region, and the fourth bezel region.

[0394] The display panel includes a plurality of rows of A column pixel circuits, a plurality of third direct-current voltage lines, and A column data lines; A is an integer greater than 1; a is a positive integer less than or equal to A; the plurality of rows of column pixel circuits are disposed in a display region; the pixel circuit in the a-th column is electrically connected to the a-th column data line;

[0395] The display panel further includes a test switch module disposed in a bezel region; the test switch module includes A test switch circuits;

[0396] The a-th test switch circuit is electrically connected to the a-th test control terminal, a third direct-current voltage line, and the a-th column data line, respectively, and is configured to control the third direct-current voltage line and the a-th column data line to be connected or disconnected under the control of an a-th test control signal provided by the a-th test control terminal.

[0397] Optionally, the third direct-current voltage line can be an initial voltage line.

[0398] In a specific implementation, the display panel can include a test switch module disposed in a bezel region, and the test switch module can include a plurality of test switch circuits; the pixel circuits in the same column can share one test switch circuit, the data lines extend in a vertical direction, and the test switch circuits can be disposed in an upper bezel region or a lower bezel region, without occupying the space of the display region, which is conducive to ensuring the PPI (pixel density).

[0399] As shown in FIG. 23, the pixel circuit in the first row and the a-th column can include a first transistor T1a1 in the first row and the a-th column, a second transistor T1a2 in the first row and the a-th column, a third transistor T1a3 in the first row and the a-th column, a fourth transistor T1a4 in the first row and the a-th column, a first capacitor C1a1 in the first row and the a-th column, a second capacitor C1a2 in the first row and the a-th column, a driving transistor DT1a in the first row and the a-th column, and an organic light-emitting diode O1a in the first row and the a-th column;

[0400] The pixel circuit in the n-th row and the a-th column can include a first transistor Tna1 in the n-th row and the a-th column, a second transistor Tna2 in the n-th row and the a-th column, a third transistor Tna3 in the n-th row and the a-th column, a fourth transistor Tna4 in the n-th row and the a-th column, a first capacitor Cna1 in the n-th row and the a-th column, a second capacitor Cna2 in the n-th row and the a-th column, a driving transistor DTna in the n-th row and the a-th column, and an organic light-emitting diode Ona in the n-th row and the a-th column.

[0401] The first reset control line is labeled as R1(1), the second reset control line is labeled as R2(1), the first light-emitting control line is labeled as EM1(1), and the scan line is labeled as GT(1);

[0402] The first reset control line is labeled as R1(n), the second reset control line is labeled as R2(n), the first light-emitting control line is labeled as EM1(n), and the scan line is labeled as GT(n);

[0403] The a-th data line is labeled as DLa.

[0404] The display panel includes an a-th test switch circuit, and the a-th test switch circuit includes an a-th test switch transistor T0a.

[0405] The gate of the T0a is electrically connected to an a-th test control terminal ATa, the drain of the T0a is electrically connected to the DLa, and the source of the T0a is electrically connected to an initial voltage line I1.

[0406] The display device described in the embodiments of the present disclosure includes the display panel described above.

[0407] The above describes the preferred embodiments of the present disclosure. It should be noted that, for those skilled in the art, without departing from the principles of the present disclosure, a number of improvements and refinements can be made, which should also be considered as the protection scope of the present disclosure.

Claims

1. A pixel circuit comprising a pixel driving circuit, a light emitting element and a test switch circuit; a control terminal of the test switch circuit being electrically connected with a test control terminal; the test switch circuit being arranged between a first test terminal and a second test terminal, and being configured to control the first test terminal and the second test terminal to be connected or disconnected under the control of a test control signal provided by the test control terminal; the pixel driving circuit being electrically connected with the first test terminal, the second test terminal and the light emitting element respectively, and being configured to generate a driving current for driving the light emitting element; the first test terminal being electrically connected with a first direct current voltage line, and the first test terminal being electrically connected with a second direct current voltage line or a test node; or, the first test terminal being electrically connected with a direct current voltage line, and the second test terminal being electrically connected with a data line.

2. The pixel circuit of claim 1, wherein, the pixel driving circuit comprising a driving circuit and a driving control circuit; a control terminal of the driving circuit being electrically connected with a first node; a first terminal of the driving circuit being electrically connected with a first test node; a second terminal of the driving circuit being electrically connected with the light emitting element; and the driving circuit being configured to generate the driving current under the control of an electric potential of the first node; the driving control circuit being configured to control the control terminal of the driving circuit and the first terminal of the driving circuit to be connected when the test switch circuit controls the first test terminal and the second test terminal to be connected.

3. The pixel circuit of claim 2, wherein, the first test terminal being electrically connected with a reference voltage line, and the second test terminal being electrically connected with a power voltage line; or, the first test terminal being electrically connected with an initial voltage line, and the second test terminal being electrically connected with a data line; or, the first test terminal being electrically connected with a reference voltage line, and the second test terminal being electrically connected with a first test node; or, the first test terminal being electrically connected with an initial voltage line, and the second test terminal being electrically connected with a second test node.

4. The pixel circuit of claim 1, wherein, the test switch circuit comprising a test switch transistor; a gate of the test switch transistor being electrically connected with the test control terminal; a first pole of the test switch transistor being electrically connected with the first test terminal; and a second pole of the test switch transistor being electrically connected with the second test terminal.

5. The pixel circuit of claim 3, wherein, the driving control circuit comprising a first light emitting control circuit, a data writing circuit, a first reset circuit and a second reset circuit; the first light emitting control circuit being electrically connected with a first light emitting control line, a power voltage line and the first terminal of the driving circuit respectively, and being configured to control the power voltage line and the first terminal of the driving circuit to be connected or disconnected under the control of a first light emitting control signal provided by the first light emitting control line; the data writing circuit being electrically connected with a scanning line, a data line and a writing node respectively, and being configured to control the data line and the writing node to be connected or disconnected under the control of a scanning signal provided by the scanning line; the second test node being electrically connected with the writing node; and the writing node being electrically connected with the first node; the first reset circuit being electrically connected with a first reset control line, the reference voltage line and the first node respectively, control the communication or disconnection between the reference voltage line and the first node under the control of a first reset control signal provided by the first reset control line; The second reset circuit is electrically connected with a second reset control line, an initial voltage line and a reset node respectively, and is used for controlling the communication or disconnection between the initial voltage line and the reset node under the control of a second reset control signal provided by the second reset control line; and the reset node is electrically connected with the second end of the driving circuit.

6. The pixel circuit of claim 5, wherein, Further comprising a first energy storage circuit and a second energy storage circuit; The first energy storage circuit is electrically connected with the first node and the second end of the driving circuit respectively, and is used for storing electric energy; The second energy storage circuit is electrically connected with the power voltage line and the second end of the driving circuit respectively, and is used for storing electric energy.

7. The pixel circuit of claim 5, wherein, Further comprising a first energy storage circuit, a second energy storage circuit and a third reset circuit; The first energy storage circuit is electrically connected with the write node and an intermediate node respectively, and is used for storing electric energy; The second energy storage circuit is electrically connected with the intermediate node and the second end of the driving circuit respectively, and is used for storing electric energy; The third reset circuit is electrically connected with a third reset control line, a reference voltage line and the intermediate node respectively, and is used for controlling the communication or disconnection between the reference voltage line and the intermediate node under the control of a third reset control signal provided by the third reset control line.

8. The pixel circuit of claim 7, wherein, Further comprising a switch control circuit; The first node is electrically connected with the write node through the switch control circuit; The control end of the switch control circuit is electrically connected with a switch control line, and the switch control circuit is used for controlling the communication or disconnection between the first node and the write node under the control of a switch control signal provided by the switch control line.

9. The pixel circuit of claim 7, wherein, Further comprising a second light emitting control circuit; The reset node is electrically connected with the second end of the driving circuit through the second light emitting control circuit; the reset node is electrically connected with the first pole of the light emitting element, and the second pole of the light emitting element is electrically connected with a low voltage line; The control end of the second light emitting control circuit is electrically connected with a second light emitting control line, and the second light emitting control circuit is used for controlling the communication or disconnection between the reset node and the second end of the driving circuit under the control of a second light emitting control signal provided by the second light emitting control line.

10. The pixel circuit of claim 5, wherein, The driving circuit comprises a driving transistor, the first light emitting control circuit comprises a first transistor, the data write circuit comprises a second transistor, the first reset circuit comprises a third transistor, and the second reset circuit comprises a fourth transistor; The gate of the driving transistor is electrically connected with the first node, the first pole of the driving transistor is electrically connected with the first test node, and the second pole of the driving transistor is electrically connected with the light emitting element; The gate of the first transistor is electrically connected with the first light emitting control line, the first pole of the first transistor is electrically connected with the power voltage line, and the second pole of the first transistor is electrically connected with the first pole of the driving transistor; A gate of the second transistor is electrically connected with the scan line, a first electrode of the second transistor is electrically connected with the data line, and a second electrode of the second transistor is electrically connected with the write node; A gate of the third transistor is electrically connected with the first reset control line, a first electrode of the third transistor is electrically connected with the reference voltage line, and a second electrode of the third transistor is electrically connected with the first node; A gate of the fourth transistor is electrically connected with the second reset control line, a first electrode of the fourth transistor is electrically connected with the initial voltage line, and a second electrode of the fourth transistor is electrically connected with the reset node.

11. The pixel circuit of claim 6, wherein, The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; A first end of the first capacitor is electrically connected with the first node, and a second end of the first capacitor is electrically connected with a second end of the drive circuit; A first end of the second capacitor is electrically connected with the power voltage line, and a second end of the second capacitor is electrically connected with the second end of the drive circuit.

12. The pixel circuit of claim 7, wherein, The first energy storage circuit includes a first capacitor, and the second energy storage circuit includes a second capacitor; and the third reset circuit includes a fifth transistor; A first end of the first capacitor is electrically connected with the write node, and a second end of the first capacitor is electrically connected with the intermediate node; A first end of the second capacitor is electrically connected with the intermediate node, and a second end of the second capacitor is electrically connected with the second end of the drive circuit; A gate of the fifth transistor is electrically connected with the third reset control line, a first electrode of the fifth transistor is electrically connected with the reference voltage line, and a second electrode of the fifth transistor is electrically connected with the intermediate node.

13. The pixel circuit of claim 8, wherein, The switch control circuit includes a sixth transistor; A gate of the sixth transistor is electrically connected with the switch control line, a first electrode of the sixth transistor is electrically connected with the first node, and a second electrode of the sixth transistor is electrically connected with the write node.

14. The pixel circuit of claim 9, wherein, The second light-emitting control circuit includes a seventh transistor; A gate of the seventh transistor is electrically connected with the second light-emitting control line, a first electrode of the seventh transistor is electrically connected with the second end of the drive circuit, and a second electrode of the seventh transistor is electrically connected with the reset node.

15. A test method of a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 14, and the test method comprises: In a detection stage, a valid test control signal is provided to a test control end, and a test switch circuit controls the first test end and the second test end to be in communication under the control of the test control signal.

16. The test method of claim 15, wherein, The test method further comprises: In a display stage, an invalid test control signal is provided to the test control end, and the test switch circuit controls the first test end and the second test end to be disconnected under the control of the test control signal, and a pixel drive circuit generates a drive current for driving a light-emitting element.

17. The test method of claim 15 or 16, wherein, The pixel drive circuit includes a drive circuit and a drive control circuit; and the test method comprises: In the detection stage, the drive control circuit controls the control end of the drive circuit and the first end of the drive circuit to be in communication. In the display stage, the drive control circuit controls the control end of the drive circuit and the first end of the drive circuit to be disconnected.

18. A display device comprising the pixel circuit according to any one of claims 1 to 14.

19. A display panel comprising a plurality of rows and columns of pixel circuits, a plurality of first direct current voltage lines and a plurality of second direct current voltage lines; the plurality of rows and columns of pixel circuits are arranged in a display area; the display panel further comprises a test switch module arranged in a frame area; the test switch module comprises a plurality of test switch circuits; each of the test switch circuits is electrically connected with a test control terminal, a first direct current voltage line and a second direct current voltage line, and is configured to control the first direct current voltage line and the second direct current voltage line to be connected or disconnected under the control of a test control signal provided by the test control terminal.

20. The display panel of claim 19, wherein, The first direct current voltage lines and the second direct current voltage lines both extend in a first direction; the display panel comprises N rows of pixel circuits; the pixel circuits in the nth row are electrically connected with the nth first direct current voltage line and the nth second direct current voltage line; N is an integer greater than 1, and n is a positive integer less than or equal to N; the test switch module comprises N test switch circuits; the nth test switch circuit is electrically connected with the nth test control terminal, the nth first direct current voltage line and the nth second direct current voltage line, and is configured to control the nth first direct current voltage line and the nth second direct current voltage line to be connected or disconnected under the control of an nth test control signal provided by the nth test control terminal.

21. The display panel of claim 19, wherein, The display panel comprises N rows of pixel circuits; the pixel circuits in the nth row are electrically connected with the nth first direct current voltage line and the nth second direct current voltage line; N is an integer greater than 1, and n is a positive integer less than or equal to N; m is a positive integer less than N; the test switch module comprises at least one test switch circuit; the mth test switch circuit is electrically connected with the mth test control terminal, the mth first direct current voltage line and the m+1th second direct current voltage line, and is configured to control the mth first direct current voltage line and the m+1th second direct current voltage line to be connected or disconnected under the control of an mth test control signal provided by the mth test control terminal.

22. The display panel of claim 19, wherein, The first direct current voltage lines comprise a plurality of rows of first direct current voltage line parts and a plurality of columns of second direct current voltage line parts which are electrically connected with each other, and the second direct current voltage lines comprise a plurality of rows of third direct current voltage line parts and a plurality of columns of fourth direct current voltage line parts which are electrically connected with each other; the extension direction of the first direct current voltage line part is the same as the extension direction of the third direct current voltage line part, the extension direction of the second direct current voltage line part is the same as the extension direction of the fourth direct current voltage line part, and the extension direction of the first direct current voltage line part intersects with the extension direction of the second direct current voltage line part; the test switch module comprises a plurality of first test switch circuits and a plurality of second test switch circuits; each of the first test switch circuits is electrically connected with a corresponding test control terminal, a row of the first direct current voltage line parts and a row of the third direct current voltage line parts, and is configured to control the row of the first direct current voltage line parts and the row of the third direct current voltage line parts to be connected or disconnected under the control of a test control signal provided by the test control terminal. The second test switch circuit is electrically connected with a corresponding test control terminal, a column of the second direct current voltage line part and a column of the fourth direct current voltage line part, respectively, and is used for controlling the column of the second direct current voltage line part and the column of the fourth direct current voltage line part to be connected or disconnected under the control of a test control signal provided by the test control terminal.

23. A display panel, comprising a plurality of rows of A-column pixel circuits, a plurality of third direct current voltage lines and A-column data lines; A is an integer greater than 1; a is a positive integer less than or equal to A; the plurality of rows of the plurality of columns of pixel circuits are arranged in a display area; the pixel circuit in the a-th column is electrically connected with the a-th column data line; The display panel further comprises a test switch module arranged in a frame area; the test switch module comprises A test switch circuits; The a-th test switch circuit is electrically connected with the a-th test control terminal, a third direct current voltage line and the a-th column data line, respectively, and is used for controlling the third direct current voltage line and the a-th column data line to be connected or disconnected under the control of an a-th test control signal provided by the a-th test control terminal.

24. A display device, comprising the display panel according to any one of claims 19 to 23.

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