Wafer-level selection for enhanced inline inspection in semiconductor manufacturing

Abstract

A method to provide a model-assisted inline wafer-level inspection during high volume manufacturing is disclosed. More particularly, a method for using a computational model to generate fingerprint wafer defect maps and then guide wafer selection for inline inspection is disclosed. A computational probability prediction model is disclosed to generate defective die probability estimates with improved accuracy and versatility to guide different wafers for inspection.

Description

WAFER-LEVEL SELECTION FOR ENHANCED INLINE INSPECTION IN SEMICONDUCTOR MANUFACTURINGCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority of US application 63 / 651,798 which was filed on May 24, 2024, and which is incorporated herein in its entirety by reference.TECHNICAL FIELD

[0002] The embodiments provided herein relate to inline wafer-level inspection during high volume manufacturing, and more particularly to a method to using a computational model to generate fingerprint wafer defect maps and then guide wafer selection for inline inspection.BACKGROUND

[0003] In manufacturing processes of integrated circuits (ICs), unfinished or finished circuit components are inspected to ensure that they are manufactured according to design and are free of defects. Inspection systems utilizing optical microscopes or charged particle (e.g., electron) beam microscopes, such as a scanning electron microscope (SEM) can be employed. As the physical sizes of IC components continue to shrink, accuracy and yield in defect detection become more important. Various metrology tools are developed and used to check whether the ICs are correctly manufactured. To improve defect inspection performance, a computational guided inspection (CGI) machine learning model may be used to assist the tools by indicating areas of a wafer to be inspected.SUMMARY

[0004] The embodiments provided herein disclose a method to inline wafer-level inspection during high volume manufacturing, and more particularly to a method to using a computational model to generate fingerprint wafer defect maps and then guide wafer selection for inline inspection.

[0005] Some embodiments of the present disclosure a method for generating a sampling plan for wafer inspection. The method comprises providing input data for a first wafer to a computational defect probability prediction model, determining defective die probabilities for the first wafer using the computational defect probability prediction model, generating a defect probability map for the first wafer using the defective die probabilities, determining a fingerprint of defective die probabilities from the defect probability map, and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

[0006] In some embodiments, an apparatus is provided. The apparatus comprises a memory storing a set of instructions and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations for generating a sampling plan for wafer inspection. The operationscomprise providing input data for a first wafer to a computational defect probability prediction model, determining defective die probabilities for the first wafer using the computational defect probability prediction model, generating a defect probability map for the first wafer using the defective die probabilities, determining a fingerprint of defective die probabilities from the defect probability map, and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

[0007] In some embodiments, a non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating a sampling plan for wafer inspection. The operations comprise providing input data for a first wafer to a computational defect probability prediction model, determining defective die probabilities for the first wafer using the computational defect probability prediction model, generating a defect probability map for the first wafer using the defective die probabilities, determining a fingerprint of defective die probabilities from the defect probability map, and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

[0008] Other advantages of the present disclosure will become apparent from the following description taken in conjunction with the accompanying drawings wherein are set forth, by way of illustration and example, certain embodiments of the present disclosure.BRIEF DESCRIPTION OF FIGURES

[0009] The above and other aspects of the present disclosure will become more apparent from the description of exemplary embodiments, taken in conjunction with the accompanying drawings.

[0010] FIG. 1 is a schematic diagram illustrating an example charged-particle beam inspection system, consistent with embodiments of the present disclosure.

[0011] FIG. 2 is a schematic diagram illustrating an example multi-beam tool that can be a part of the example charged-particle beam inspection system of FIG. 1, consistent with embodiments of the present disclosure.

[0012] FIG. 3 is a schematic block diagram illustrating throughput to generate input data, consistent with embodiments of the present disclosure.

[0013] FIG. 4 is an example block diagram illustrating training of a CGI model using an initial training dataset.

[0014] FIGs. 5A and 5B are example diagrams illustrating down sampling at the wafer lot level to perform wafer inline defect inspection during high volume manufacturing.

[0015] FIG. 6 is an example block diagram illustrating a system to generate a defect probability wafer map containing grouped fingerprints, consistent with embodiments of the present disclosure.

[0016] FIGS. 7A-7I are example illustrations of fingerprint wafer maps, consistent with embodiments of the present disclosure.

[0017] FIG. 8 is an example workflow, consistent with embodiments of the present disclosure.

[0018] FIG. 9 is an example flow diagram of method, consistent with embodiments of the present disclosure.DETAILED DESCRIPTION

[0019] Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. The following description refers to the accompanying drawings in which the same numbers in different drawings represent the same or similar elements unless otherwise represented. The implementations set forth in the following description of exemplary embodiments do not represent all implementations. Instead, they are merely examples of apparatuses and methods consistent with aspects related to the disclosed embodiments as recited in the appended claims. For example, although some embodiments are described in the context of utilizing electron beams, the disclosure is not so limited. Other types of charged-particle beams (e.g., including protons, ions, muons, or any other particle carrying electric charges) may be similarly applied. Furthermore, other imaging systems may be used, such as optical imaging, photon detection, x-ray detection, ion detection, etc.

[0020] Electronic devices are constructed of circuits formed on a piece of semiconductor material called a substrate. The semiconductor material may include, for example, silicon, gallium arsenide, indium phosphide, or silicon germanium, or the like. Many circuits may be formed together on the same piece of silicon and are called integrated circuits or ICs. The size of these circuits has decreased dramatically so that many more of them can be fit on the substrate. The enhanced computing power of electronic devices, while reducing the physical size of the devices, can be accomplished by significantly increasing the packing density of circuit components such as transistors, capacitors, diodes, etc. on an IC chip. For example, an IC chip of a smart phone, which is the size of a thumbnail, may include over 2 billion transistors, the size of each transistor being less than 1 / 1000th of a human hair.

[0021] ICs may be manufactured using lithography, which is a fabrication process involving creating complex circuit patterns drawn on a mask deposited onto a substrate. Lithography may be performed by a lithographic apparatus, which is a machine that applies a source of radiation (e.g., light or X-ray) onto a target portion of the substrate to form a desired pattern. The target portion of the substrate may be covered with a pattern device (e.g., mask) that may be either eliminated or developed after exposure to the radiation source. This process of transferring the desired pattern to the substrate is called a patterning process. The patterning process may include a patterning step to transfer a pattern from a pattern device (e.g., a mask) to the substrate. There can also be one or more related pattern processing steps, such as mask development by a development apparatus, baking of the substrate using a bake tool, etching the pattern onto the substrate using an etch apparatus, or other chemical and physical processing steps involved in fabricating a pattern onto the substrate. Variations inexperimental parameters (e.g., stochastic variations, errors, or noise due to an inspection tool or pattern processing tool) can potentially limit lithography implementation for high volume manufacturing (HVM), or process yield, of ICs and introduce defects into IC structures.

[0022] In the manufacture of ICs using a lithographic apparatus, typically many lithographic patterning steps are performed, thereby forming functional features in successive layers on the substrate. A critical aspect of performance of the lithographic apparatus is therefore the ability to place the applied pattern correctly and accurately in relation to features laid down in previous layers. For this purpose, the substrate is provided with one or more sets of alignment marks. Each mark is a structure having a position that can be measured later using, for example, an electron beam inspection tool. Defects may occur in which an applied pattern structure or pattern layer is incorrectly placed in relation to a reference mark, or when the fabrication conditions are suboptimal. A reference mark or layout define the desired structure, structure dimensions, and the distance between IC structures (such as gates, capacitors, etc.) or interconnect lines. This may ensure that the IC devices or lines do not interact with one another in an undesirable way. The structure limitations provided by the reference layouts are typically referred to as critical dimensions. A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the critical dimension determines the overall size and packing density of the designed IC. A goal in IC fabrication is to faithfully reproduce the original IC design on the substrate. If an error occurs during fabrication where the created IC design pattern does not match the reference design, this may result in a defect in the IC structure and render the IC inoperable.

[0023] Making these ICs with extremely small structures or components is a complex, timeconsuming, and expensive process, often involving hundreds of individual steps. Errors in even one step have the potential to dramatically affect the function of the final product. Even one “killer defect” can cause device failure. The goal of the manufacturing process is to improve the overall yield of the process. For example, for a 50-step process to get to a 75% yield, each individual step must have a yield greater than 99.4%, and if the individual step yield is 95%, the overall process yield drops to 7%.

[0024] While high process yield is desirable in an IC chip manufacturing facility, maintaining a high wafer throughput, defined as the number of wafers processed per hour, is also essential. High process yields and high wafer throughput can be impacted by the presence of defects, especially if operator intervention is required for reviewing the defects. Thus, high throughput detection and identification of micro and nano-sized defects is desired. One component of improving process yield and wafer throughput may be monitoring the IC fabrication process to ensure a desired number of defect-free ICs are produced. One way to monitor the fabrication process is to inspect the chip circuit structures at various stages of fabrication. Inspection using tools such as, for example, a charged particle beam inspection tool may be used to this effect to maintain high process yield and high wafer throughput. Inspection of a wafer using an electron beam inspection tool may generate images of the wafer tomeasure IC structure dimensions. The measured dimensions may be compared to a reference structure absent any defects to determine the presence of defects in the imaged structure. If the structure is defective, then the fabrication process can be adjusted, so the defect is less likely to recur. However, as wafers may contain up to 1 billion IC structures, inspection of ICs for defect detection is often a time-consuming process and may not inspect a wafer at a correct location to identify a defect.

[0025] Computational guided inspection (CGI) processes guide inspection tools to locations on a wafer where there is a higher probability of defects. A machine learning-based CGI model receives input from various data sources, such as wafer characteristic data (which may include scanner data, metrology data, and fabrication process data) to train the model with inspection results. A CGI machine learning model may be built and used to output a sampling plan indicating a location on a wafer where defects have likely formed after a wafer processing step, so the inspection tool will go to the sampling location to inspect with a higher efficiency than inspecting wafer locations based on experience (e.g., a history of prior defects detected during scanning). The CGI process occurs in-line with wafer fabrication and increases inspection tool efficiency by increasing the accuracy of finding defects on the wafer with capture rates of finding defects higher than a baseline value. The inspection results may be used to confirm a satisfactory wafer yield is maintained throughout manufacturing and to project the failure rate, or die loss per wafer, at the end of production. This projected failure rate may be compared to the results of a wafer probe test, which determines a failure rate for each die fabricated on the wafer. A final metric of a CGI model use case may be the R2correlation score between the estimated and measured die defects for a wafer.

[0026] A CGI model may be applied to characteristic wafer data to estimate a defect probability for each die on a wafer. A sampling plan optimizer or sampling plan generator then aggregates the estimated defective die probability for each die on a wafer to generate a defective die probability map, or a sampling plan. The sampling plan may be generated according to input information that defines a pre-determined wafer region definition and sampling budget per wafer region. The sampling plan may then be used to guide an inspection tool (e.g., a scanning electron microscope, SEM, or an optical tool) to a region on the wafer where the sampling plan has a set number of dies to inspect (e.g., a sampling budget). The inspection results obtained via the sampling plan indicate a number of actual defective die present, and the inspection results may then be used to project an estimated die loss for a wafer. Accordingly, the CGI-generated sampling plan used to guide inspection may be referred to as the “verified sampling plan.” An R2correlation score for the defective die projection provided by the CGI model sampling plan may be determined by collecting the “ground truth” results for a wafer. The “ground truth” results indicate the actual defective die results of a wafer at the end of production and correspond to a probe test result for a fully completed wafer. Accordingly, a probe test result provides accurate identification of defects for each die on a wafer. The final metric of the CGI model may be the correlation R2score between the projected estimated die loss determined by the CGI model and the actual die loss determined by the probe test results.

[0027] Generally, the wafers that are selected for performing inline wafer inspection during HVM are down-sampled at the wafer / batch level. In other words, only a few wafers out of a 25-wafer batch may be selected to inspect after a processing step. A wafer may be randomly selected or selected at a fixed frequency (e.g., wafer #3 is always selected after a processing stop). However, inspection of the wafer(s) selected may miss any defects that form during HVM, and it may only be by random chance if a defect is detected during inspection. As a result, inline wafer inspection may proceed at a slower rate than desired and defects may be missed. This may negatively impact the accuracy and robustness of the CGI defect location prediction model and result in suboptimal wafer yield during HVM.

[0028] Embodiments of the present disclosure provide a method to generate a wafer-level inline inspection sampling plan using a wafer defect probability map generated by the CGI model. Embodiments of the present disclosure may use a CGI model to generate a defect probability wafer map and group predicted defects in the generated wafer map into fingerprints. The grouped defects may indicate distinct categories of defect fingerprints that may then be used to guide inline wafer inspection instead of relying on manually selecting subsequent wafers for inspection by random or fixed sampling. In some embodiments, the grouped defects may provide information on defects that may form after a wafer processing step. Embodiments of the present disclosure provide lot- and wafer-level selection capability for a CGI model to guide inspection of wafers fabricated during HVM.

[0029] Relative dimensions of components in drawings may be exaggerated for clarity. Within the following description of drawings, the same or like reference numbers refer to the same or like components or entities, and only the differences with respect to the individual embodiments are described. As used herein, unless specifically stated otherwise, the term “or” encompasses all possible combinations, except where infeasible. For example, if it is stated that a component may include A or B, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or A and B. As a second example, if it is stated that a component may include A, B, or C, then, unless specifically stated otherwise or infeasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A and B and C.

[0030] FIG. 1 illustrates an example electron beam inspection (EBI) system 100 consistent with embodiments of the present disclosure. EBI system 100 may be used for imaging. As shown in FIG. 1, EBI system 100 includes a main chamber 101, a load / lock chamber 102, a beam tool 104, and an equipment front end module (EFEM) 106. Beam tool 104 is located within main chamber 101. EFEM 106 includes a first loading port 106a and a second loading port 106b. EFEM 106 may include additional loading port(s). First loading port 106a and second loading port 106b receive wafer front opening unified pods (FOUPs) that contain wafers (e.g., semiconductor wafers or wafers made of other material(s)) or samples to be inspected (wafers and samples may be used interchangeably). A “lot” is a plurality of wafers that may be loaded for wafer processing as a batch.

[0031] One or more robotic arms (not shown) in EFEM 106 may transport the wafers to load / lock chamber 102. Load / lock chamber 102 is connected to a load / lock vacuum pump system (not shown) which removes gas molecules in load / lock chamber 102 to reach a first pressure below the atmospheric pressure. After reaching the first pressure, one or more robotic arms (not shown) may transport the wafer from load / lock chamber 102 to main chamber 101. Main chamber 101 is connected to a main chamber vacuum pump system (not shown) which removes gas molecules in main chamber 101 to reach a second pressure below the first pressure. After reaching the second pressure, the wafer is subject to inspection by beam tool 104. Beam tool 104 may be a single-beam system or a multi-beam system.

[0032] A controller 109 is electronically connected to beam tool 104. Controller 109 may be a computer configured to execute various controls of EBI system 100. While controller 109 is shown in FIG. 1 as being outside of the structure that includes main chamber 101, load / lock chamber 102, and EFEM 106, it is appreciated that controller 109 may be a part of the structure.

[0033] In some embodiments, controller 109 may include one or more processors (not shown). A processor may be a generic or specific electronic device capable of manipulating or processing information. For example, the processor may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field- Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. The processor may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0034] In some embodiments, controller 109 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, a compact flash (CF) card, or any type of storage device. The codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0035] FIG. 2 illustrates a schematic diagram of an example multi-beam tool 104 (also referred to herein as apparatus 104) and an image processing system 290 that may be configured for use in EBI system 100 (FIG. 1), consistent with embodiments of the present disclosure.

[0036] Beam tool 104 comprises a charged-particle source 202, a gun aperture 204, a condenser lens 206, a primary charged-particle beam 210 emitted from charged-particle source 202, a source conversion unit 212, a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210, a primary projection optical system 220, a motorized wafer stage 280, a wafer holder 282, multiple secondary charged-particle beams 236, 238, and 240, a secondary optical system 242, and a charged- particle detection device 244. Primary projection optical system 220 can comprise a beam separator 222, a deflection scanning unit 226, and an objective lens 228. Charged-particle detection device 244 can comprise detection sub-regions 246, 248, and 250.

[0037] Charged-particle source 202, gun aperture 204, condenser lens 206, source conversion unit 212, beam separator 222, deflection scanning unit 226, and objective lens 228 can be aligned with a primary optical axis 260 of apparatus 104. Secondary optical system 242 and charged-particle detection device 244 can be aligned with a secondary optical axis 252 of apparatus 104.

[0038] Charged-particle source 202 can emit one or more charged particles, such as electrons, protons, ions, muons, or any other particle carrying electric charges. In some embodiments, charged- particle source 202 may be an electron source. For example, charged-particle source 202 may include a cathode, an extractor, or an anode, wherein primary electrons can be emitted from the cathode and extracted or accelerated to form primary charged-particle beam 210 (in this case, a primary electron beam) with a crossover (virtual or real) 208. For ease of explanation without causing ambiguity, electrons are used as examples in some of the descriptions herein. However, it should be noted that any charged particle may be used in any embodiment of this disclosure, not limited to electrons. Primary charged-particle beam 210 can be visualized as being emitted from crossover 208. Gun aperture 204 can block off peripheral charged particles of primary charged-particle beam 210 to reduce Coulomb effect. The Coulomb effect may cause an increase in size of probe spots.

[0039] Source conversion unit 212 can comprise an array of image-forming elements and an array of beam-limit apertures. The array of image-forming elements can comprise an array of micro-deflectors or micro-lenses. The array of image-forming elements can form a plurality of parallel images (virtual or real) of crossover 208 with a plurality of beamlets 214, 216, and 218 of primary charged-particle beam 210. The array of beam-limit apertures can limit the plurality of beamlets 214, 216, and 218. While three beamlets 214, 216, and 218 are shown in FIG. 2, embodiments of the present disclosure are not so limited. For example, in some embodiments, the apparatus 104 may be configured to generate a first number of beamlets. In some embodiments, the first number of beamlets may be in a range from 1 to 1000. In some embodiments, the first number of beamlets may be in a range from 200-500. In an exemplary embodiment, the apparatus 104 may generate 400 beamlets.

[0040] Condenser lens 206 can focus primary charged-particle beam 210. The electric currents of beamlets 214, 216, and 218 downstream of source conversion unit 212 can be varied by adjusting the focusing power of condenser lens 206 or by changing the radial sizes of the corresponding beam-limit apertures within the array of beam-limit apertures. Objective lens 228 can focus beamlets 214, 216,and 218 onto a wafer 230 for imaging, and can form a plurality of probe spots 270, 272, and 274 on a surface of wafer 230.

[0041] Beam separator 222 can be a beam separator of Wien fdter type generating an electrostatic dipole field and a magnetic dipole field. In some embodiments, if they are applied, the force exerted by the electrostatic dipole field on a charged particle (e.g., an electron) of beamlets 214, 216, and 218 can be substantially equal in magnitude and opposite in a direction to the force exerted on the charged particle by magnetic dipole field. Beamlets 214, 216, and 218 can, therefore, pass straight through beam separator 222 with zero deflection angle. However, the total dispersion of beamlets 214, 216, and 218 generated by beam separator 222 can also be non-zero. Beam separator 222 can separate secondary charged-particle beams 236, 238, and 240 from beamlets 214, 216, and 218 and direct secondary charged-particle beams 236, 238, and 240 towards secondary optical system 242.

[0042] Deflection scanning unit 226 can deflect beamlets 214, 216, and 218 to scan probe spots 270, 272, and 274 over a surface area of wafer 230. In response to the incidence of beamlets 214, 216, and 218 at probe spots 270, 272, and 274, secondary charged-particle beams 236, 238, and 240 may be emitted from wafer 230. Secondary charged-particle beams 236, 238, and 240 may comprise charged particles (e.g., electrons) with a distribution of energies. For example, secondary charged-particle beams 236, 238, and 240 may be secondary electron beams including secondary electrons (energies < 50 eV) and backscattered electrons (energies between 50 eV and landing energies of beamlets 214, 216, and 218). Secondary optical system 242 can focus secondary charged-particle beams 236, 238, and 240 onto detection sub-regions 246, 248, and 250 of charged-particle detection device 244. Detection sub-regions 246, 248, and 250 may be configured to detect corresponding secondary charged-particle beams 236, 238, and 240 and generate corresponding signals (e.g., voltage, current, or the like) used to reconstruct an SCPM image of structures on or underneath the surface area of wafer 230.

[0043] The generated signals may represent intensities of secondary charged-particle beams 236, 238, and 240 and may be provided to image processing system 290 that is in communication with charged-particle detection device 244, primary projection optical system 220, and motorized wafer stage 280. The movement speed of motorized wafer stage 280 may be synchronized and coordinated with the beam deflections controlled by deflection scanning unit 226, such that the movement of the scan probe spots (e.g., scan probe spots 270, 272, and 274) may orderly cover regions of interests on the wafer 230. The parameters of such synchronization and coordination may be adjusted to adapt to different materials of wafer 230. For example, different materials of wafer 230 may have different resistance-capacitance characteristics that may cause different signal sensitivities to the movement of the scan probe spots.

[0044] The intensity of secondary charged-particle beams 236, 238, and 240 may vary according to the external or internal structure of wafer 230, and thus may indicate whether wafer 230 includes defects. Moreover, as discussed above, beamlets 214, 216, and 218 may be projected onto differentlocations of the top surface of wafer 230, or different sides of local structures of wafer 230, to generate secondary charged-particle beams 236, 238, and 240 that may have different intensities. Therefore, by mapping the intensity of secondary charged-particle beams 236, 238, and 240 with the areas of wafer 230, image processing system 290 may reconstruct an image that reflects the characteristics of internal or external structures of wafer 230.

[0045] In some embodiments, image processing system 290 may include an image acquirer 292, a storage 294, and a controller 296. Image acquirer 292 may comprise one or more processors. For example, image acquirer 292 may comprise a computer, server, mainframe host, terminals, personal computer, any kind of mobile computing devices, or the like, or a combination thereof. Image acquirer 292 may be communicatively coupled to charged-particle detection device 244 of beam tool 104 through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, wireless radio, or a combination thereof. In some embodiments, image acquirer 292 may receive a signal from charged-particle detection device 244 and may construct an image. Image acquirer 292 may thus acquire SCPM images of wafer 230. Image acquirer 292 may also perform various post-processing functions, such as generating contours, superimposing indicators on an acquired image, or the like. Image acquirer 292 may be configured to perform adjustments of brightness and contrast of acquired images. In some embodiments, storage 294 may be a storage medium such as a hard disk, flash drive, cloud storage, random access memory (RAM), other types of computer-readable memory, or the like. Storage 294 may be coupled with image acquirer 292 and may be used for saving scanned raw image data as original images, and postprocessed images. Image acquirer 292 and storage 294 may be connected to controller 296. In some embodiments, image acquirer 292, storage 294, and controller 296 may be integrated together as one control unit.

[0046] In some embodiments, image acquirer 292 may acquire one or more SCPM images of a wafer based on an imaging signal received from charged-particle detection device 244. An imaging signal may correspond to a scanning operation for conducting charged particle imaging. An acquired image may be a single image comprising a plurality of imaging areas. The single image may be stored in storage 294. The single image may be an original image that may be divided into a plurality of regions. Each of the regions may comprise one imaging area containing a feature of wafer 230. The acquired images may comprise multiple images of a single imaging area of wafer 230 sampled multiple times over a time sequence. The multiple images may be stored in storage 294. In some embodiments, image processing system 290 may be configured to perform image processing steps with the multiple images of the same location of wafer 230.

[0047] In some embodiments, image processing system 290 may include measurement circuits (e.g., analog-to-digital converters) to obtain a distribution of the detected secondary charged particles (e.g., secondary electrons). The charged-particle distribution data collected during a detection time window, in combination with corresponding scan path data of beamlets 214, 216, and 218 incident on the wafersurface, can be used to reconstruct images of the wafer structures under inspection. The reconstructed images can be used to reveal various features of the internal or external structures of wafer 230, and thereby can be used to reveal any defects that may exist in the wafer.

[0048] In some embodiments, the charged particles may be electrons. When electrons of primary charged-particle beam 210 are projected onto a surface of wafer 230 (e.g., probe spots 270, 272, and 274), the electrons of primary charged-particle beam 210 may penetrate the surface of wafer 230 for a certain depth, interacting with particles of wafer 230. Some electrons of primary charged-particle beam 210 may elastically interact with (e.g., in the form of elastic scattering or collision) the materials of wafer 230 and may be reflected or recoiled out of the surface of wafer 230. An elastic interaction conserves the total kinetic energies of the bodies (e.g., electrons of primary charged-particle beam 210) of the interaction, in which the kinetic energy of the interacting bodies does not convert to other forms of energy (e.g., heat, electromagnetic energy, or the like). Such reflected electrons generated from elastic interaction may be referred to as backscattered electrons (BSEs). Some electrons of primary charged-particle beam 210 may inelastically interact with (e.g., in the form of inelastic scattering or collision) the materials of wafer 230. An inelastic interaction does not conserve the total kinetic energies of the bodies of the interaction, in which some or all of the kinetic energy of the interacting bodies convert to other forms of energy. For example, through the inelastic interaction, the kinetic energy of some electrons of primary charged-particle beam 210 may cause electron excitation and transition of atoms of the materials. Such inelastic interaction may also generate electrons exiting the surface of wafer 230, which may be referred to as secondary electrons (SEs). Yield or emission rates of BSEs and Ses depend on, e.g., the material under inspection and the landing energy of the electrons of primary charged-particle beam 210 landing on the surface of the material, among others. The energy of the electrons of primary charged-particle beam 210 may be imparted in part by its acceleration voltage (e.g., the acceleration voltage between the anode and cathode of charged-particle source 202 in FIG. 2). The quantity of BSEs and Ses may be more or fewer (or even the same) than the injected electrons of primary charged-particle beam 210.

[0049] The images generated by SCPM may be used for defect inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect may be identified. For another example, the SCPM may scan multiple regions of the wafer, each region including a test device region designed as the same, and generate multiple images capturing those test device regions as manufactured. The multiple images may be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect may be identified.

[0050] Although reference may be made in the present disclosure to ICs, it is appreciated that the present disclosure may be applicable to other possible applications or designs. For example, thepresent disclosure may be applied to integrated optical systems, magnetic domain memories, liquidcrystal display panels, thin-film magnetic heads, and other nanoscale structures. It is further appreciated that the terms “die”, “structure”, and “IC structure” are used interchangeably in this disclosure.

[0051] In some embodiments, machine learning may be employed in the generation of inspection images, reference images or other images associated with apparatus 100, 104A, or 104B. For example, in some embodiments a machine learning system may be operated in association with, e.g., controller 109 or 296, image processing system 290, image acquirer 292, or storage unit 294 of FIGs. 1-2. In some embodiments, machine learning may be employed in a method of generating a waferlevel inline inspection sampling plan, e.g., method 900 of FIG. 9, in association with, e.g., an offline computation platform. In some embodiments, a machine learning system may comprise a discriminative model. In some embodiments, a machine learning system may include a generative model. For example, learning can feature two types of mechanisms: discriminative learning that may be used to create classification and detection algorithms, and generative learning that may be used to actually create models that, in the extreme, can render images. For example, as described further below, a generative model may be configured for generating an image from a design clip that resembles a corresponding location on a wafer in a SEM image. This may be performed by 1) training the generative model with design clips and the associated actual SEM images from those locations on the wafer; and 2) using the model in inference mode to feed the model design clips in locations for which simulated SEM images are desired. Such simulated images can be used as reference images in, e.g., die-to-database inspection.

[0052] If the model(s) include one or more discriminative models, the discriminative model(s) may have any suitable architecture or configuration known in the art. Discriminative models, also called conditional models, are a class of models used in machine learning for modeling the dependence of an unobserved variable “y” on an observed variable “x.” Within a probabilistic framework, this may be done by modeling a conditional probability distribution P(y|x), which can be used for predicting y based on x. Discriminative models, as opposed to generative models, may not allow one to generate samples from the joint distribution of x and y. However, for tasks such as classification and regression that do not require the joint distribution, discriminative models may yield superior performance. On the other hand, generative models are typically more flexible than discriminative models in expressing dependencies in complex learning tasks. In addition, most discriminative models are inherently supervised and cannot easily be extended to unsupervised learning. Application specific details ultimately dictate the suitability of selecting a discriminative versus generative model.

[0053] A generative model can be generally defined as a model that is probabilistic in nature. In other words, a “generative” model is not one that performs forward simulation or rule-based approaches and, as such, it may not be necessary to model the physics of the processes involved in generating an actual image or output (for which a simulated image or output is being generated).Instead, the generative model can be learned (in that its parameters can be learned) based on a suitable training set of data. Such generative models may have a number of advantages for the embodiments described herein. In addition, the generative model may be configured to have a deep learning architecture in that the generative model may include multiple layers, which may perform a number of algorithms or transformations. The number of layers included in the generative model may depend on the particular use case. For practical purposes, a suitable range of layers is from 2 layers to a few tens of layers.

[0054] Deep learning is a type of machine learning. Machine learning can be generally defined as a type of artificial intelligence (Al) that provides computers with the ability to learn without being explicitly programmed. Machine learning focuses on the development of computer programs that can teach themselves to grow and change when exposed to new data. Machine learning explores the study and construction of algorithms that can learn from and make predictions on data — such algorithms overcome following strictly static program instructions by making data driven predictions or decisions, through building a model from sample inputs.

[0055] The machine learning described herein may be further performed as described in “Introduction to Statistical Machine Learning,” by Sugiyama, Morgan Kaufmann, 2016, 534 pages; “Discriminative, Generative, and Imitative Learning,” Jebara, MIT Thesis, 2002, 212 pages; and “Principles of Data Mining (Adaptive Computation and Machine Learning)” Hand et al., MIT Press, 2001, 578 pages; which are incorporated by reference as if fully set forth herein. The embodiments described herein may be further configured as described in these references.

[0056] In some embodiments, a machine learning system may comprise a neural network. For example, a model may be a deep neural network with a set of weights that model the world according to the data that it has been fed to train it. Neural networks can be generally defined as a computational approach which is based on a relatively large collection of neural units loosely modeling the way a biological brain solves problems with relatively large clusters of biological neurons connected by axons. Each neural unit is connected with many others, and links can be enforcing or inhibitory in their effect on the activation state of connected neural units. These systems are self-learning and trained rather than explicitly programmed and excel in areas where the solution or feature detection is difficult to express in a traditional computer program.

[0057] Neural networks typically consist of multiple layers, and the signal path traverses from front to back. The goal of the neural network is to solve problems in the same way that the human brain would, although several neural networks are much more abstract. Modem neural network projects typically work with a few thousand to a few million neural units and millions of connections. The neural network may have any suitable architecture and / or configuration known in the art.

[0058] In some embodiments, a model may comprise convolutional and deconvolution neural network. For example, the embodiments described herein can take advantage of learning concepts such as a convolution and deconvolution neural network to solve the normally intractablerepresentation conversion problem (e.g., rendering). The model may have any convolution and deconvolution neural network configuration or architecture known in the art.

[0059] Reference is now made to FIG. 3, which is an example block diagram for generating input data, consistent with embodiments of the present disclosure. Input data may be generated using two steps as illustrated in FIG. 3. A lithographic projection apparatus 301 may be used to fabricate a wafer at a constant fabrication condition (e.g., a focus and dose for a radiation source). An inspection tool 302 (e.g., EBI system 100 in FIG. 1 or multi-beam tool 104 in FIG. 2) may be used to measure metrology information of structures formed on the wafer that was generated by lithographic projection apparatus 301. Metrology information may include, but is not limited to, necking, line pull back, line thinning, critical dimension, edge placement, overlapping, resist top loss, resist undercut, missing defects, and bridging defects of an IC structure on a wafer. A processor 303 (e.g., controller 109 in FIG. 1) with a memory may be communicatively connected to inspection tool 302 to store the measured metrology information.

[0060] The images generated by inspection tool 302 may be used for wafer inspection. For example, a generated image capturing a test device region of a wafer may be compared with a reference image capturing the same test device region. The reference image may be predetermined (e.g., by simulation) and include no known defect. If a difference between the generated image and the reference image exceeds a tolerance level, a potential defect may be identified. For another example, inspection tool 302 may scan multiple regions of the wafer, each region including a test device region designed as the same and generate multiple images capturing those test device regions as manufactured. The multiple images may be compared with each other. If a difference between the multiple images exceeds a tolerance level, a potential defect may be identified.

[0061] In some embodiments, processor 303 may be a generic or specific electronic device capable of manipulating or processing information. For example, processor 303 may include any combination of any number of a central processing unit (or “CPU”), a graphics processing unit (or “GPU”), an optical processor, a programmable logic controller, a microcontroller, a microprocessor, a digital signal processor, an intellectual property (IP) core, a Programmable Logic Array (PLA), a Programmable Array Logic (PAL), a Generic Array Logic (GAL), a Complex Programmable Logic Device (CPLD), a Field-Programmable Gate Array (FPGA), a System On Chip (SoC), an Application-Specific Integrated Circuit (ASIC), and any type circuit capable of data processing. Processor 303 may also be a virtual processor that includes one or more processors distributed across multiple machines or devices coupled via a network.

[0062] In some embodiments, processor 303 may further include one or more memories (not shown). A memory may be a generic or specific electronic device capable of storing codes and data accessible by the processor (e.g., via a bus). For example, the memory may include any combination of any number of a random-access memory (RAM), a read-only memory (ROM), an optical disc, a magnetic disk, a hard drive, a solid-state drive, a flash drive, a security digital (SD) card, a memory stick, acompact flash (CF) card, or any type of storage device. The codes and data may include an operating system (OS) and one or more application programs (or “apps”) for specific tasks. The memory may also be a virtual memory that includes one or more memories distributed across multiple machines or devices coupled via a network.

[0063] A computational guided inspection (CGI) process guides inspection tools to locations on a wafer where there is a higher probability of defects. A machine learning-based CGI model receives input from various data sources, such as wafer characteristic data (which may include scanner data, metrology data, and fabrication process data) to train the model with inspection results. A CGI machine learning model may be built and used to output a sampling plan indicating a location on a wafer where defects have likely formed after a wafer processing step, so the inspection tool will go to the sampling location to inspect with a higher efficiency than inspecting wafer locations based on experience (e.g., a history of prior defects detected during scanning). The CGI process occurs in-line with wafer fabrication and increases inspection tool efficiency by increasing the accuracy of finding defects on the wafer with capture rates of finding defects higher than a baseline value. The inspection results may be used to confirm a satisfactory wafer yield is maintained throughout manufacturing and to project the failure rate, or die loss per wafer, at the end of production. This projected failure rate may be compared to the results of a wafer probe test, which determines a failure rate for each die fabricated on the wafer. A final metric of a CGI model use case may be the R2correlation score between the estimated and measured die defects for a wafer.

[0064] A CGI model may be applied to characteristic wafer data to estimate a defect probability for each die on a wafer. A sampling plan optimizer or sampling plan generator then converts the estimated defective die probability for each die on a wafer to a die-level sampling decision wafer map (also known as a sampling plan). The sampling plan may be generated according to input information that defines a pre-determined wafer region definition and sampling budget per wafer region, as well as user-specified sampling options. The sampling plan may provide a die-level binary sampling decision (e.g., inspect or do not inspect a die on a wafer). The sampling plan may then be used to guide an inspection tool (e.g., a scanning electron microscope, SEM, or an optical tool) to a region on the wafer where the sampling plan has a set number of dies to inspect (e.g., a sampling budget). The inspection results obtained via the sampling plan indicate a number of actual defective die present, and the inspection results may then be used to project an estimated die loss for a wafer. An R2correlation score for the defective die projection provided by the CGI model sampling plan may be determined by collecting the “ground truth” results for a wafer. The “ground truth” results indicate the actual defective die results of a wafer at the end of production and correspond to a probe test result for a fully completed wafer. Accordingly, a probe test result provides accurate identification of defects for each die on a wafer. The final metric of the CGI model and sampling plan optimizer may be the correlation R2score between the projected estimated die loss determined by the CGI model and the actual die loss determined by the probe test results.

[0065] The CGI model provides an output of a defective die probability at a die-to-die level. This means the CGI model estimates a defect probability for each die on a wafer, which may vary from die to die, and from wafer to wafer. The estimated defective die probability may be aggregated to generate a sampling plan for a wafer. Since a sampling plan may be generated for each wafer based on the specific defective die probability for each die on a wafer, the CGI model-generated sampling plan may be referred to as a “dynamic” sampling plan. The dynamic sampling plan may be used to guide inspection of a wafer to project a die loss for a wafer at the end of wafer processing.

[0066] In some embodiments of the present disclosure, the projected die loss may be determined without assuming a uniform defect density or distribution within a wafer region. As described above, die loss may be projected after an inspection result is collected from an inspection tool guided by the CGI generated dynamic sampling plan. The projected die loss may be calculated via the following equations, consistent with embodiments of the present disclosure: . _. (Equation 3)r „ „ . sum(defective die probability of non-sampled dies in reqionScaling factor, S. = 1 + - sumfd -efective d -i -e probabi —lity - of sample -d - dies in regio -n - i) - (Equation 4)

[0067] In Equation 3, Nddis the number of defective dies, Ndis the total number of dies on the wafer, and SLis the scaling factor. The summation in Equation 3 is from one wafer region, i, to the total number of wafer regions, M, on a wafer. In Equation 4, the non-sampled dies are the dies not inspected according to the CGI-generated sampling plan, whereas the sampled dies are the dies that are inspected. However, each die in wafer region i has a defective die probability determined by the CGI model. Thus, the summation in the numerator in Equation 4 is equivalent to the expected number of defective dies that are not inspected, and the summation in the denominator in the Equation 4 is equivalent to the expected number of defective dies that are inspected. As the defective die probability may vary for each die in a wafer region, and in a wafer overall, the scaling factor, SL. in Equation 4 may account for non-uniform defect density distribution. The CGI model may determine the dies to inspect (e.g., sampled dies) by ranking the defective die probabilities according to a per-wafer region basis and selecting, for each wafer region, a number of dies based on the ranking of defective die probabilities. The number of dies may be less than or equal to the sampling budget for a wafer region. In other words, the CGI-generated dynamic sampling plan may combine an Ni number of dies with the highest defective die probabilities, where Ni is the sampling budget for wafer region i.

[0068] A CGI model may use input data from a reference wafer (e.g., a reference pattern, metrology information, etc., according to a fabrication or wafer processing step) to thus guide future inspection of wafers processed during HVM. The CGI model increases inspection tool efficiency by increasingthe accuracy of finding defects on the wafer with capture rates of finding defects higher than a baseline value. However, current CGI systems lack wafer-level selection capability to guide inline wafer inspection. Additionally, conventional methods of down-sampling of wafers at the lot / wafer level may not be an efficient approach to guide inline wafer inspection in conjunction with CGI.

[0069] FIG. 4 is an example block diagram illustrating training of a CGI model 401 using an initial training dataset, consistent with various embodiments of the present disclosure. CGI model 401 may have to be trained using an initial training dataset 405 before it can be used to generate predictions for a wafer. The initial training dataset 405 may be a labeled dataset, which includes process-related data 410a-n and inspection results 415a-n of “n” number of substrates. For example, for a wafer “A,” the initial training dataset 405 may include process-related data 410a and inspection results 415a associated with the substrate “A.” The process-related data 410a may include metrology data such as that described above, or other such data that may contribute to a defect. The inspection results 415a may include an image of an inspected location (e.g., SEM image), location information of the inspected location (e.g., (x, y) coordinates) and whether that location is found to be defective or nondefective. The labeled dataset may be obtained from various sources, including lithographic projection apparatus 301 and inspection tool 302 of FIG. 3.

[0070] CGI model 401 may include a location prediction model 450 and a confidence model 455, both of which may be machine learning models. The training of CGI model 401 may be an iterative process in which each iteration may involve analyzing process-related data 410 associated with a wafer, determining the cost functions, and updating a configuration of CGI model 401 based on the cost function. CGI model 401 may be trained in a “batch” fashion instead of as an iterative process. For example, training dataset 405 having process-related data 410a-n and inspection results 415a-n of “n” number of substrates may be input collectively. After inputting process-related data 410a and inspection results 415a, location prediction model 450 generates predictions 425al-425ax for “x” number of locations on wafer “A” and confidence model 455 assigns confidence scores 430al-430ax for predictions 425al-425ax, respectively. CGI model 401 then compares the predicted results with inspection results 415a to determine a cost function 460 of CGI model 401, which may be indicative of a deviation between predicted results 425al-425ax and the actual inspection results 415a. CGI model 401 may update its configurations (e.g., weights, biases, or other parameters of location prediction model 450 or confidence model 455) based on cost function 460 or other reference feedback information (e.g., user indication of accuracy, reference labels, or other information) to minimize cost function 460. The above process is repeated iteratively with process-related data and inspection results associated with a different substrate in each iteration until a termination condition is satisfied. The termination condition may include a predefined number of iterations, cost function satisfies a specified threshold, or other such conditions. After the termination condition is satisfied, CGI model 401 may be considered to be “trained” and may be used for identifying or predicting defective locations in a new wafer (e.g., a wafer that has not been analyzed using CGI model 401 yet).

[0071] Reference is now made to FIG. 5A, which is an example diagram illustrating fixed down sampling at the lot / wafer level to perform wafer inline defect inspection during HVM. FIG. 5A illustrates a fixed sampling plan to perform inspection for an example batch of wafers that are processed during HVM according to wafer processing step 501, wafer processing step 502, and wafer processing step 503. Each wafer processing step may correspond to a metrology applied to each of wafer A, wafer B, wafer C, wafer D, and wafer E. For example, wafer processing step 501 may be a deposition processing step, wafer processing step 502 may be a lithography processing step, and wafer processing step 503 may be an etching step. The solid, bold outline represents a wafer that is selected for wafer inline defect inspection after a wafer processing step, and the dotted outline represents a wafer that is not selected for wafer inline defect inspection after a wafer processing step. For example, according to a fixed sampling plan, wafer A and wafer D are selected for wafer inspection after each wafer processing step (e.g., wafer processing steps 501, 502, and 503). Inspection information and metrology information corresponding to wafers A and wafer D is therefor available for generating a wafer map, but no wafer map may be generated for wafers B, C, and E. As a result, possible defect detection is limited to the chance that a defect occurs in the selected wafers and may not be representative of all wafers fabricated per lot. Reference is now made to FIG. 5B, which is an example diagram illustrated random down sampling at the lot / wafer level to perform wafer inline defect inspection during HVM. FIG. 5B illustrates a random sampling to perform inspection for the example batch of wafers processed during HVM according to wafer processing steps 501-503. For a random sampling plan, any of wafers A-E may be randomly selected without an understanding of historical data or trends in the wafer fabrication process. FIG. 5B illustrates only wafer A may be selected for inline inspection after wafer processing step 501, wafer C and wafer E may be selected after wafer processing step 502, and wafers B, D, and E may be selected after wafer processing step 503. As a result of either a fixed sampling plan or a random sampling plan, defect detection may miss defects that may form on fabricated wafers. Accordingly, defect detection may be limited to chance and may not be representative of defects that may form on wafers fabricated per lot. Thus, none of wafers A-E in the batch selected for detect inspection may capture defects that form during HVM and that ensure a desirably high wafer yield is achieved.

[0072] Embodiments of the present disclosure may provide a method to generate a wafer-level inline inspection sampling plan using a wafer defect probability map generated by the CGI model. As illustrated in FIGs. 5A and 5B, down-sampling at the lot / wafer level is performed manually in a fixed or random manner. Embodiments of the present disclosure may use a CGI model to generate a defect probability wafer map and group predicted defects in the generated wafer map into fingerprints. The grouped defects may indicate distinct categories of defect fingerprints that may then be used to guide inline wafer inspection instead of relying of random or fixed sampling. In some embodiments, the grouped defects may provide information on defects that may form after a wafer processing step. Embodiments of the present disclosure may thus provide predicted lot- and wafer-level selectioncapability for a CGI model. Embodiments of the present disclosure may also utilize wafer fabrication context information available for each wafer processed during wafer processing. “Fabrication context information” or “context information” may refer to the fabrication or processing information for each wafer during HVM. Each piece of equipment or apparatus used during wafer processing (e.g., lithographic projection apparatus 301 in FIG. 3) has an information log about the parameters and logistics used to process each wafer. For example, wafer A in FIG. 5A or FIG. 5B may be processed according to a context ID (e.g., a tool ID or a chamber ID) and according to a process setting (e.g., a temperature, pressure, gas mixture ratio, etc.) in wafer processing step 501 and may be processed according to a context ID and according to a process setting in wafer processing step 502. All such context information is available for each wafer processed during HVM in a fabrication database, and the fabrication database may be provided to the CGI model. The CGI model may be in communication with the fabrication database, where the context information may be queried and supplied to a CGI model platform and then linked with available metrology information for a wafer. The CGI model may be communicatively connected to the fabrication database through a medium such as an electric conductor, optical fiber cable, portable storage media, IR, Bluetooth, internet, wireless network, or wireless radio.

[0073] Reference is now made to FIG. 6, which is an example block diagram illustrating a system 600 with various modules that may generate a defect probability wafer map containing grouped fingerprints, consistent with embodiments of the present disclosure. The modules in system 600 in FIG. 6 may be applied via controller 109 in FIG 1., controller 290 in FIG. 2, or processor 303 in FIG. 3

[0074] A computational defect probability prediction model 602 (e.g., CGI model 602) may obtain input data 601. In some embodiments, CGI 602 may obtain input data 601 from an inspection tool or a metrology tool. In some embodiments, CGI 602 may obtain input data 601 from a server or an offline source (e.g., a USB). Input data 601 may be obtained from different types of tools. Example tools may include but are not limited to a scatterometry tool or an inspection tool (e.g., beam tool 104 in FIG. 1 or inspection tool 302 in FIG. 3). Input data 601 may be images collected for a wafer or a batch of wafers processed according to a wafer processing step (e.g., wafers A-E after wafer processing step 501 in FIG. 5A or FIG. 5B). The image may contain the inspection or metrology information available for the wafers after a wafer processing step. CGI model 602 may also obtain context information from a fabrication database. Context information may correspond to tool ID / routing information or fabrication conditions or parameters applied to the wafer or batch of wafers when processed according to the wafer processing step. It is appreciated that context information may be available in a fabrication database for every wafer processed according to wafer processing during HVM.

[0075] In some embodiments, CGI model 602 may include a calculator 603, a classifier 606, and a selector 610. Input data 601 may be provided to calculator 603. Calculator 603 may calculate diedefect probabilities from input data 601 and generate a defect probability wafer map 604 based on the calculated die defect probabilities. Defect probability wafer map 604 may indicate a defect probability for each die on a wafer 605. In some embodiments, the die defect probability in defect probability wafer map 604 may be represented as a gradient image, where, for example, a lighter color indicates a larger defective die probability and darker color represents a lower defective die probability. Defect probability wafer map 604 may then be provided to classifier 606. In some embodiments, classifier 606 may determine a pattern or a group on a defect probability map generated by CGI model 602. As a non-limiting example, classifier 606 may generate fingerprint wafer map 607, which contains group 608 and group 609 of die defect probabilities. Group 608 and group 609 may be combined and considered a fingerprint. Classifier 606 may calculate similarity scores for the die defect probabilities in defect probability map 604 and then generate fingerprint wafer map 607. FIG. 6 illustrates fingerprint wafer map 607 that contains group 608 and group 609. In some embodiments, classifier 606 may identify and group dies on defect probability wafer map 604 based on calculated similarity scores. In some embodiments, group 608 and group 609 may indicate a region on a wafer (e.g., wafer 605) that is likely to contain a defect. In some embodiments, group 608 and group 609 may indicate a region on a wafer (e.g., wafer 605) that may contain a defect that forms as a result of a wafer processing step. In some embodiments, classifier 606 may apply a multi-class support vector machine, a convolutional neural network, or any other image classification technology that can categorize input data under a specific label. In some embodiments, the input data is an image. In some embodiments, the specific label is a similarity score. In some embodiments, classifier 606 may be pre-trained using input data from a publicly available database. In some embodiments, classifier 606 may link fingerprint wafer map 607 with context information of wafer 605 such that group 608 and group 609 are linked to a wafer processing step.

[0076] In some embodiments, selector 610 may analyze fingerprint wafer map 607 and suggest a wafer or lot of wafers to be selected for inline inspection. In some embodiments, selector 610 may make a suggestion based on an input. In some embodiments, the input may include, but is not limited to, a number of fingerprints per wafer processing step, a number of wafers to inspect per fingerprint per lot, whether to use a dynamic or static sampling plan based on a similarity score or defect excursion, or any other defined rule or requirement provided by a user.

[0077] Reference is now made to FIGs. 7A-7I, which are example illustrations of fingerprint wafer maps, consistent with embodiments of the present disclosure. A CGI model such as that described above for FIG. 6 may generate the fingerprint wafer maps illustrated in FIGs. 7A-7I. FIG. 7A illustrates an example fingerprint wafer map indicative of a center group 701 (e.g., a center fingerprint). FIG. 7B illustrates an example fingerprint wafer map indicative of a donut group 702 (e.g., a donut fingerprint). FIG. 7C illustrates an example fingerprint wafer map indicative of an edge-local group 703 (e.g., an edge-local fingerprint). FIG. 7D illustrates an example fingerprint wafer map indicative of an edge-ring group 704 (e.g., an edge-ring fingerprint). FIG. 7E illustrates anexample fingerprint wafer map indicative of a local group 705 (e.g., a local fingerprint). FIG. 7F illustrates an example fingerprint wafer map indicative of a random group 706 (e.g., a random fingerprint). It is appreciated that random group 706 is illustrated as identifying only a portion of the random groups in FIG. 7F. FIG. 7G illustrates an example fingerprint wafer map indicative of a scratched group 707 (e.g., a scratched fingerprint). FIG. 7H illustrates an example fingerprint wafer map indicative of a near-full group 708 (e.g., a near-full fingerprint). FIG. 71 illustrates an example grouped wafer map indicative of a nonpattern group (e.g., a nonpattern fingerprint). FIGs. 7A-7I illustrate how embodiments of the present disclosure may provide different signatures for possible defective IC structures and may provide additional insight compared to a conventional method to perform wafer-level selection for accurate and efficient inline wafer inspection.

[0078] Reference is now made to FIG. 8, which is an example workflow for building a defect probability wafer map containing grouped fingerprints to guide selection for wafer-level inline inspection, consistent with embodiments of the present disclosure. Input data 801 may be obtained and provided to a computational defect probability prediction model 802 (e.g., CGI model 802). In some embodiments, input data 801 may be images of wafers or metrology data of wafers fabricated according to a wafer processing step. In some embodiments, input data 801 contains context information about each wafer processing step used to fabricate the wafers. CGI model 802 may calculate die defect probabilities from input data 801 and generate defect probability wafer maps 803, 804, and 805. CGI model 802 may then generate fingerprint wafer maps 806, 807, and 808. Fingerprint wafer map 806 may correspond to defect probability wafer map 803, fingerprint wafer map 807 may correspond to defect probability wafer map 804, and fingerprint wafer map 808 may correspond to defect probability wafer map 805. Fingerprint wafer map 806 may contain group 809, fingerprint wafer map 807 may contain group 810 and group 811, and fingerprint wafer map 808 may contain group 812 and group 813. In some embodiments, CGI model 802 may classify fingerprint wafer maps as a same fingerprint group based on, for example, a similarity score. As illustrated in FIG. 8, fingerprint wafer map 808 and fingerprint wafer map 809 contain similar fingerprints and may exhibit a higher similarity score compared to a calculated similarity score between fingerprint wafer map 806 and fingerprint wafer map 807, or between fingerprint wafer map 806 and fingerprint wafer map 808. Accordingly, CGI model 802 may classify fingerprint wafer map 807 and fingerprint wafer map 808 as fingerprint group 814 and classify fingerprint wafer map 806 as fingerprint group 815.

[0079] Because input data 801 may contain context information for the wafer processing steps, fingerprint group 814 may correspond to wafers fabricated according to a first wafer processing step and fingerprint group 815 may correspond to wafers fabricated according to a second wafer processing step. For example, fingerprint group 815 may correspond to a wafer A and a wafer B that are fabricated according to a wafer processing step 816. Fingerprint group 814 may correspond to a wafer D and a wafer E that are fabricated according to a wafer processing step 817. In someembodiments, fingerprint group 814 may be used to select wafer D and wafer E after wafer processing step 817 to inspect for any defects according to fingerprint wafer map 807 and fingerprint wafer 808. In some embodiments, fingerprint group 815 may be used to select wafer A and wafer B after wafer processing step 816 to inspect for any defects according to fingerprint wafer map 806. Thus, throughput and accuracy inline wafer inspection for defects during HVM may be improved.

[0080] Reference is now made to FIG. 9, which is an example flow diagram illustrating a method 900 of generating a wafer-level inline inspection sampling plan, consistent with embodiments of the present disclosure. The steps of method 900 may be performed by a computing device, e.g., controller 109 of FIG. 1, controller 290 of FIG. 2, or processor 303 of FIG. 3. It is appreciated that the illustrated method 900 may be altered to modify the order of steps and to include the additional steps.

[0081] In step 901, input data for a first wafer is provided to a computational defect probability prediction model (e.g., CGI model 602 of FIG. 6, CGI model 802 of FIG. 8). The input data may be inspection information, context information, or metrology information available for a batch of wafers that are measured after a wafer processing step. The input data may be context information about the wafer processing step. The metrology information may optionally be processed to reduce the dimensionality of the dataset (e.g., fingerprint summarization). The CGI model may acquire the context information from a fabrication database.

[0082] In step 902, defective die probabilities are calculated for the first wafer using the computational defect probability prediction model. The calculation may be based on identified defects in the input data and is influenced by the input data quality. The calculation may be performed by a computing device (e.g., controller 109 of FIG. 1, controller 290 of FIG. 2, or processor 303 of FIG. 3), which may apply the computational defect probability prediction model to the input data of the first wafer. In step 903, a defect probability map for the first wafer is generated by compiling the calculated defective die probabilities.

[0083] In step 904, a fingerprint of defective die probabilities is determined from the defect probability map. The computational defect probability prediction model calculates similarity scores for the defective die probabilities and then generates the fingerprint of defective die probabilities. The calculated fingerprint may identify, and group defective die probabilities based on the calculated similarity scores. In some embodiments, the computational defect probability prediction model applies a multi-class support vector machine, a convolutional neural network, or any other image classification technology that can categorize input data under a specific label. In some embodiments, the input data is an image. In some embodiments, the specific label is a similarity score. In some embodiments, the computational defect probability prediction model is pre-trained to calculate fingerprints using input data from a publicly available database. In some embodiments, the computational defect probability prediction model may link the calculated fingerprints with context information of the first wafer.

[0084] In step 905, a sampling plan is generated for a second wafer based on the fingerprint of defective die probabilities. The sampling is generated for the second wafer, wherein the second wafer has the same context information as the first wafer.

[0085] A benefit provided by embodiments of the present disclosure may be an improved accuracy and throughput in predicting defective die in wafers fabricated during HVM. Embodiments of the present disclosure may address limitations of existing defect probability systems by introducing lotlevel and wafer-level selection capability for a CGI model to assist inspection tools, efficient defect classification and analysis, and improved defect detection. In some embodiments, a computational model is provided that groups die defect probabilities into fingerprint patterns and using the fingerprint patterns to guide inline wafer inspection. Some embodiments of the present disclosure may provide a method to improve a CGI model performance and versatility to guide wafer inspection. Some embodiments of the present disclosure may provide a method to increase defect inspection accuracy and yield of defect-free wafers throughout HVM.

[0086] A non-transitory computer readable medium may be provided that may store instructions for a processor of a controller (e.g., controller 109 of FIG. 1) to carry out, among other things, image inspection, image acquisition, stage positioning, beam focusing, electric field adjustment, beam bending, condenser lens adjusting, activating charged-particle source, beam deflecting, store instructions for a processor of a lithographic projection apparatus (e.g., lithographic projection apparatus 301 of FIG. 3) and inspection tool (e.g., inspection tool 302 of FIG. 3) to determine input data of a sample, perform method 900 of FIG. 9, and other executable functions relating to identifying locations on a wafer for inspection during HVM. Common forms of non-transitory media include, for example, a floppy disk, a flexible disk, hard disk, solid state drive, magnetic tape, or any other magnetic data storage medium, a Compact Disc Read Only Memory (CD-ROM), any other optical data storage medium, any physical medium with patterns of holes, a Random Access Memory (RAM), a Programmable Read Only Memory (PROM), and Erasable Programmable Read Only Memory (EPROM), a FLASH-EPROM or any other flash memory, Non-Volatile Random Access Memory (NVRAM), a cache, a register, any other memory chip or cartridge, and networked versions of the same.

[0087] The embodiments may further be described using the following clauses:1. A method for generating a sampling plan for wafer inspection, the method comprising: providing input data for a first wafer to a computational defect probability prediction model; determining defective die probabilities for the first wafer using the computational defect probability prediction model; generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.2. The method of clause 1, wherein the input data for the first wafer comprises an image containing inspection information, metrology information, or context information of the first wafer.3. The method of clause 2, wherein the context information of the first wafer comprises fabrication data associated with a wafer processing step.4. The method of any one of clauses 1 to 3, wherein defective die probabilities are determined for each die on the first wafer.5. The method of any one of clauses 1 to 4, wherein determining the fingerprint of defective die probabilities from the defect probability map comprises: calculating a characteristic for the defective die probabilities; and grouping the defective die probabilities based on the calculated characteristic.6. The method of clause 5, wherein the characteristic for the defective die probabilities is a similarity score.7. The method of clause 5 or 6, wherein calculating the characteristic for the defective die probabilities is performed by applying a multi-class support vector machine or a convolutional neural network to the defective die probabilities.8. The method of any one of clauses 1 to 7, wherein the second wafer shares a same characteristic with the first wafer.9. The method of clause 8, wherein the second wafer shares context information with the first wafer.10. The method of any one of clauses 1 to 9, wherein the computational defect probability prediction model is pre-trained with a fingerprint of defective die probabilities.11. The method of clause 10, wherein the fingerprint is obtained from input data from a previously collected wafer.12. The method of clause 10, wherein the fingerprint is obtained from a database.13. The method of any one of clauses 1 to 12, further comprising:Using the sampling plan to guide an inspection tool for wafer inspection of the second wafer.14. The method of clause 13, wherein the inspection tool is a scanning charged particle microscope or an optical tool.15. The method of any one of clauses 1 to 14, wherein the computational defect probability prediction model is a computational guided inspection model.16. An apparatus for generating a sampling plan for wafer inspection, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a first wafer to a computational defect probability prediction model; determining defective die probabilities for the first wafer using the computational defect probability prediction model;generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.17. The apparatus of clause 16, wherein the input data for the first wafer comprises an image containing inspection information, metrology information, or context information of the first wafer.18. The apparatus of clause 17, wherein the context information of the first wafer comprises fabrication data associated with a wafer processing step.19. The apparatus of any one of clauses 16 to 18, wherein defective die probabilities are determined for each die on the first wafer.20. The apparatus of any one of clauses 16 to 19, wherein the operations for determining the fingerprint of defective die probabilities from the defect probability map comprises: calculating a characteristic for the defective die probabilities; and grouping the defective die probabilities based on the calculated characteristic.21. The apparatus of clause 20, wherein the characteristic for the defective die probabilities is a similarity score.22. The apparatus of clause 20 or 21, wherein the operations for calculating the characteristic for the defective die probabilities are performed by applying a multi-class support vector machine or a convolutional neural network to the defective die probabilities.23. The apparatus of any one of clauses 16 to 22, wherein the second wafer shares a same characteristic with the first wafer.24. The apparatus of clause 23, wherein the second wafer shares context information with the first wafer.25. The apparatus of any one of clauses 16 to 24, wherein the computational defect probability prediction model is pre-trained with a fingerprint of defective die probabilities.26. The apparatus of clause 25, wherein the fingerprint is obtained from input data from a previously collected wafer.27. The apparatus of clause 25, wherein the fingerprint is obtained from a database.28. The apparatus of any one of clauses 16 to 27, the operations further comprising: using the sampling plan to guide an inspection tool for wafer inspection of the second wafer.29. The apparatus of clause 28, wherein the inspection tool is a scanning charged particle microscope or an optical tool.30. The apparatus of any one of clauses 16 to 29, wherein the computational defect probability prediction model is a computational guided inspection model.31. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating a sampling plan for wafer inspection, the operations comprising: providing input data for a first wafer to a computational defect probability prediction model;determining defective die probabilities for the first wafer using the computational defect probability prediction model; generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.32. The non-transitory computer readable medium of clause 31, wherein the input data for the first wafer comprises an image containing inspection information, metrology information, or context information of the first wafer.33. The non-transitory computer readable medium of clause 32, wherein the context information of the first wafer comprises fabrication data associated with a wafer processing step.34. The non-transitory computer readable medium of any one of clauses 31 to 33, wherein defective die probabilities are determined for each die on the first wafer.35. The non-transitory computer readable medium of any one of clauses 31 to 34, wherein the operations for determining the fingerprint of defective die probabilities from the defect probability map comprises: calculating a characteristic for the defective die probabilities; and grouping the defective die probabilities based on the calculated characteristic.36. The non-transitory computer readable medium of clause 35, wherein the characteristic for the defective die probabilities is a similarity score.37. The non-transitory computer readable medium of clause 35 or 36, wherein the operations for calculating the characteristic for the defective die probabilities are performed by applying a multiclass support vector machine or a convolutional neural network to the defective die probabilities.38. The non-transitory computer readable medium of any one of clauses 31 to 37, wherein the second wafer shares a same characteristic with the first wafer.39. The non-transitory computer readable medium of clause 38, wherein the second wafer shares context information with the first wafer.40. The non-transitory computer readable medium of any one of clauses 31 to 39, wherein the computational defect probability prediction model is pre-trained with a fingerprint of defective die probabilities.41. The non-transitory computer readable medium of clause 40, wherein the fingerprint is obtained from input data from a previously collected wafer.42. The non-transitory computer readable medium of clause 40, wherein the fingerprint is obtained from a database.43. The non-transitory computer readable medium of any one of clauses 31 to 42, the operations further comprising: using the sampling plan to guide an inspection tool for wafer inspection of the second wafer.44. The non-transitory computer readable medium of clause 43, wherein the inspection tool is a scanning charged particle microscope or an optical tool.45. The non-transitory computer readable medium of any one of clauses 31 to 44, wherein the computational defect probability prediction model is a computational guided inspection model.

[0088] Block diagrams in the figures may illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer hardware or software products according to various exemplary embodiments of the present disclosure. In this regard, each block in a schematic diagram may represent certain arithmetical or logical operation processing that may be implemented using hardware such as an electronic circuit. Blocks may also represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical functions. It should be understood that in some alternative implementations, functions indicated in a block may occur out of the order noted in the figures. For example, two blocks shown in succession may be executed or implemented substantially concurrently, or two blocks may sometimes be executed in reverse order, depending upon the functionality involved. Some blocks may also be omitted. It should also be understood that each block of the block diagrams, and combination of the blocks, may be implemented by special purpose hardware-based systems that perform the specified functions or acts, or by combinations of special purpose hardware and computer instructions.

[0089] It will be appreciated that the embodiments of the present disclosure are not limited to the exact construction that has been described above and illustrated in the accompanying drawings, and that various modifications and changes may be made without departing from the scope thereof. The present disclosure has been described in connection with various embodiments, and other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of the technology disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

CLAIMS1. A method for generating a sampling plan for wafer inspection, the method comprising: providing input data for a first wafer to a computational defect probability prediction model; determining defective die probabilities for the first wafer using the computational defect probability prediction model; generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

2. The method of claim 1, wherein the input data for the first wafer comprises an image containing inspection information, metrology information, or context information of the first wafer.

3. The method of claim 2, wherein the context information of the first wafer comprises fabrication data associated with a wafer processing step.

4. The method of claim 1, wherein defective die probabilities are determined for each die on the first wafer.

5. The method of claim 1, wherein determining the fingerprint of defective die probabilities from the defect probability map comprises: calculating a characteristic for the defective die probabilities; and grouping the defective die probabilities based on the calculated characteristic.

6. The method of claim 5, wherein the characteristic for the defective die probabilities is a similarity score.

7. The method of claim 5, wherein calculating the characteristic for the defective die probabilities is performed by applying a multi-class support vector machine or a convolutional neural network to the defective die probabilities.

8. The method of claim 1, wherein the second wafer shares a same characteristic with the first wafer.

9. The method of claim 8, wherein the second wafer shares context information with the first wafer.

10. The method of claim 1, wherein the computational defect probability prediction model is pre-trained with a fingerprint of defective die probabilities.

11. The method of claim 10, wherein the fingerprint is obtained from input data from a previously collected wafer.

12. The method of claim 10, wherein the fingerprint is obtained from a database.

13. The method of claim 1, further comprising:Using the sampling plan to guide an inspection tool for wafer inspection of the second wafer.

14. An apparatus for generating a sampling plan for wafer inspection, comprising: a memory storing a set of instructions; and at least one processor configured to execute the set of instructions to cause the apparatus to perform operations comprising: providing input data for a first wafer to a computational defect probability prediction model; determining defective die probabilities for the first wafer using the computational defect probability prediction model; generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

15. A non-transitory computer readable medium comprising a set of instructions that is executable by one or more processors of a computing device to cause the computing device to perform operations for generating a sampling plan for wafer inspection, the operations comprising: providing input data for a first wafer to a computational defect probability prediction model; determining defective die probabilities for the first wafer using the computational defect probability prediction model; generating a defect probability map for the first wafer using the defective die probabilities; determining a fingerprint of defective die probabilities from the defect probability map; and generating a sampling plan for a second wafer based on the fingerprint of defective die probabilities.

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